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| users manual v1.1 2011-03 microcontrollers TC1798 32-bit single-chip microcontroller www.datasheet.co.kr datasheet pdf - http://www..net/
edition 2011-03 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any ex amples or hints given herein, any typi cal values stated herein and/or any information regarding the application of the device, infi neon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-suppo rt devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.datasheet.co.kr datasheet pdf - http://www..net/ users manual v1.1 2011-03 microcontrollers TC1798 32-bit single-chip microcontroller www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 users manual v1.1, 2011-03 TC1798 users manual revision history: v1.1, 2011-03 previous version: v1.0 chapter subjects (major changes since last revision) changes from TC1798 umv1.0 to TC1798 um v1.1 1 introduction: ? no functional changes 2cpu: ? no functional changes 3scu: ? no functional changes 4 on-chip system buses and bus bridges: ? xbardbcon.master description and increased bitfield to 6 bit 5pmu: ? chapter robust eeprom emulation: highlighted in the description of the robust eeprom emulation that program ver flags should be ignored ? chapter advice for eeprom emulation and robust eeprom emulation: some minor fixes to the description of the eeprom emulation. replaced all ?ignore sbe? by ignore correctable error and the same for dbe. noted in the eepr om advice that the ?other page? should be compared also. noted how a marker should be programmed ? chapter flash read access: corre cted that data reads by tricore from cached pflash are not performed by btr2 but btr4 6lmu: ? no functional changes 7 data access overlay: ? no functional changes 8 firmware: ? no functional changes 9 memory maps: ? no functional changes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 users manual 1-2 v1.1, 2011-03 revision history, 10 general purpose i/o ports and peripheral i/o lines: ? added description of strong sharp minus and strong medium minus for class a2 pads. ? added description for driver strength selection for class b pads 11 pcp: ? no functional module changes 12 dma: ? no functional module changes 13 sdma: ? no functional module changes 14 fce: ? changed reset value of the fce_clc register 15 external bus unit: ? no functional module changes 16 interrupt system: ? changed text that target is to s upport conecyc=1 up to the max fpi frequency ? corrected number of gpt12 interrupts from 4 to 6 17 system timer: ? no functional module changes 18 bmu ? no functional module changes 19 ocds: ? no functional module changes 20 asc: ? no functional module changes 21 ssc: ? no functional module changes 22 sscg: ? no functional module changes 23 msc: ? no functional module changes 24 multican: ? no functional module changes TC1798 users manual revision history: v1.1, 2011-03 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 users manual 1-3 v1.1, 2011-03 revision history, trademarks tricore ? , infineon ? , infineon technologies ? and gpta ? are trademarks of infineon technologies ag. 25 sent: ? no functional module changes 26 e-ray: ? no functional module changes 27 mli: ? corrected description of register tcmdr ? maximum baud rate frequencies where replaced by a baud rate formula 28 gptav5: ? no functional module changes 29 ccu6: ? no functional module changes 30 gpt12: ? no functional module changes 31 adc: ? no functional module changes 32 fadc: ? no functional module changes TC1798 users manual revision history: v1.1, 2011-03 we listen to your comments is there any information in this document that you feel is wrong, unclear or missing? your feedback will help us to continuousl y improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com www.datasheet.co.kr datasheet pdf - http://www..net/ users manual l-1 v1.1, 2011-03 TC1798 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 about this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 related documentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.2 text conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.3 reserved, undefined, and unimplemented terminology . . . . . . . . . . 1-3 1.1.4 register access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.5 abbreviations and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2 system architecture of the TC1798 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.2.1 TC1798 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.2.2 cpu cores of the TC1798 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.2.2.1 high-performance 32-bit cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.2.2.2 high-performance 32-bit peripheral control processor . . . . . . . . . 1-11 1.3 on-chip system units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.3.1 flexible interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.3.1.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.3.2 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . 1-12 1.3.2.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.3.3 safe direct memory access co ntroller . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.3.3.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.3.4 flexible crc engine (fce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.3.4.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.3.5 system timer (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.5.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.6 system control unit (scu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.3.6.1 clock generation unit (cgu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.3.6.2 features of the watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . 1-17 1.3.6.3 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.6.4 external interface (esr, eru) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.6.5 die temperature measurement (dts) . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.7 general purpose i/o ports and peripheral i/o lines (ports) . . . . . . . 1-19 1.3.7.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.3.8 program memory unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.3.8.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.3.9 secure hardware extension (she) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.3.10 local memory unit (lmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.3.10.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.3.11 data access overlay (ovc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.3.11.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.4 on-chip peripheral units of the TC1798 . . . . . . . . . . . . . . . . . . . . . . . . 1-24 1.4.1 asynchronous/synchronous se rial interfaces (asc) . . . . . . . . . . . . 1-24 1.4.1.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 table of contents www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-2 v1.1, 2011-03 1.4.2 high-speed synchronous serial interfaces (ssc) . . . . . . . . . . . . . . 1-27 1.4.2.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 1.4.3 synchronous serial interface guardian ( sscg) . . . . . . . . . . . . . . . . 1-29 1.4.3.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 1.4.4 micro second channel interface (msc) . . . . . . . . . . . . . . . . . . . . . . 1-31 1.4.4.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.4.5 flexray? protocol controller (e-ray) . . . . . . . . . . . . . . . . . . . . . . . 1-33 1.4.5.1 e-ray kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 1.4.5.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 1.4.5.3 features list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 1.4.6 multican controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 1.4.6.1 multican feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37 1.4.6.2 ttcan feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 1.4.7 micro link serial bus interface (mli) . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 1.4.7.1 mli feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 1.4.8 single edge nibble transmission (sent) . . . . . . . . . . . . . . . . . . . . . 1-41 1.4.8.1 sent kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 1.4.9 sent feature overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42 1.4.10 general purpose timer array (gptav5) . . . . . . . . . . . . . . . . . . . . . . 1-44 1.4.10.1 gpta0 and gpta1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 1.4.10.2 ltca2 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46 1.4.11 capture/compare unit 6 (ccu 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47 1.4.11.1 feature list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47 1.4.12 general purpose timer (gpt12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48 1.4.12.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 1.4.13 external bus interface (ebu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50 1.4.13.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50 1.4.14 analog-to-digital converters (adc/fadc) . . . . . . . . . . . . . . . . . . . . 1-51 1.4.15 adc module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 1.4.15.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 1.4.16 fadc module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 1.4.16.1 fadc feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 1.5 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 1.5.1 on-chip debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 1.5.2 real time trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-56 1.5.3 calibration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-56 1.5.4 tool interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-56 1.5.5 self-test support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 1.5.6 far support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 2 cpu subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 TC1798 processor subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 central processing unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-3 v1.1, 2011-03 2.2.1 cpu diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.2 instruction fetch unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.4 general purpose register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3 summary of functional changes from tc1.3.1 . . . . . . . . . . . . . . . . . . . . 2-8 2.4 cpu implementation-specific features . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.1 context save areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.2 program counter (pc) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.3 store buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.4.4 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.4.4.1 interrupt acknowledge decoupling for safety systems . . . . . . . . . 2-12 2.4.5 trap system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.4.6 memory integrity error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.4.6.1 program side memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.4.6.2 data side memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.5 cpu subsystem registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.6 cpu core special function registers (csfr) . . . . . . . . . . . . . . . . . . . 2-20 2.6.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.7 cpu general purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.8 cpu memory protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 2.9 temporal protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.10 fpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 2.10.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.11 memory integrity registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 2.11.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.12 cpu slave interface (cps) registers . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 2.12.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60 2.13 core debug and performance counter registers . . . . . . . . . . . . . . . . . 2-62 2.14 implementation specific reset values . . . . . . . . . . . . . . . . . . . . . . . . . 2-65 2.15 cpu instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66 2.15.1 integer-pipeline instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67 2.15.1.1 simple arithmetic instruction timings . . . . . . . . . . . . . . . . . . . . . . 2-67 2.15.1.2 multiply instruction timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71 2.15.1.3 multiply accumulate (mac) instruction timing . . . . . . . . . . . . . . . 2-72 2.15.1.4 control flow instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73 2.15.2 load-store pipeline instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 2.15.2.1 address arithmetic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 2.15.2.2 csa control flow instruction timing . . . . . . . . . . . . . . . . . . . . . . . 2-75 2.15.2.3 load instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 2.15.2.4 store instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77 2.15.3 floating point pipeline timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78 2.16 program memory interface (pmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79 2.16.1 pmi features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-4 v1.1, 2011-03 2.16.2 scratchpad ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80 2.16.3 instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80 2.16.4 program line buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82 2.16.5 cpu slave interface (cps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82 2.16.6 pmi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82 2.16.6.1 pmi register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83 2.17 data memory interface (dmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 2.17.1 dmi features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 2.17.2 data scratchpad ram (dspr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89 2.17.3 data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89 2.17.4 dmi trap generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90 2.18 memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92 2.18.1 dmi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93 2.18.1.1 dmi register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-94 2.19 safety features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99 2.19.1 sri address phase error injection . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99 2.19.2 sri data phase error capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99 2.19.3 safety interrupt acknowledge decoupling . . . . . . . . . . . . . . . . . . . . . 2-99 2.19.4 registers implementing safety features . . . . . . . . . . . . . . . . . . . . . 2-100 3 system control unit (scu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 clock system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.1 clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.1.2 oscillator circuit (osc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.1.3 phase-locked loop (pll) module . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.1.4 eray phase-locked loop (pll_eray) module . . . . . . . . . . . . . 3-16 3.1.1.5 clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.1.1.6 external clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.1.1.7 cgu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.1.2 module clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53 3.1.2.1 clock control register clc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54 3.2 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68 3.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68 3.2.2 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68 3.2.3 reset sources overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 3.2.4 module reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 3.2.5 general reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70 3.2.6 reset state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 3.2.7 reset counters (rstcnta and rstcntd) . . . . . . . . . . . . . . . . . . 3-72 3.2.8 de-assertion of a reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 3.2.8.1 example1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 3.2.8.2 example2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-5 v1.1, 2011-03 3.2.8.3 example3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 3.2.9 reset triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 3.2.9.1 specific reset triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 3.2.9.2 configurable reset triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 3.2.10 debug specific behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 3.2.11 eec reset specific behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 3.2.12 reset controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75 3.2.12.1 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75 3.2.12.2 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77 3.3 external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82 3.3.1 external service requests (esrx ) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82 3.3.1.1 esrx as reset request trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82 3.3.1.2 esrx as reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83 3.3.1.3 esr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84 3.3.2 external request unit (eru) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91 3.3.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91 3.3.2.2 eru pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93 3.3.2.3 external request select unit (ers) . . . . . . . . . . . . . . . . . . . . . . . 3-93 3.3.2.4 event trigger logic (etl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94 3.3.2.5 connecting matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96 3.3.2.6 output gating unit (ogu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98 3.3.2.7 eru output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102 3.3.2.8 external request un it registers . . . . . . . . . . . . . . . . . . . . . . . . . 3-104 3.4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120 3.4.1 power management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120 3.4.2 power management modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121 3.4.2.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121 3.4.2.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-122 3.4.3 power management contro l and status register, pmcsr . . . . . . 3-122 3.5 software boot support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125 3.5.1 configuration done with start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125 3.5.2 start-up configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-125 3.5.3 start-up registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-126 3.5.3.1 start-up status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-126 3.6 ecc error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129 3.6.1 ecc software testing support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129 3.6.2 ecc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130 3.7 die temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-136 3.7.1 die temperature sensor register . . . . . . . . . . . . . . . . . . . . . . . . . . 3-137 3.8 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-139 3.8.1 watchdog timer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-139 3.8.2 features of the watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-139 3.8.3 the endinit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-140 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-6 v1.1, 2011-03 3.8.3.1 password access to wdt_con0 . . . . . . . . . . . . . . . . . . . . . . . . 3-142 3.8.3.2 modify access to wdt_con0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-143 3.8.3.3 access to endinit-protected registers . . . . . . . . . . . . . . . . . . . . 3-144 3.8.4 timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145 3.8.4.1 timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145 3.8.4.2 wdt reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-146 3.8.4.3 wdt operation during power-saving modes . . . . . . . . . . . . . . . 3-148 3.8.4.4 suspend mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148 3.8.5 watchdog timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-149 3.8.5.1 watchdog timer control register 0 . . . . . . . . . . . . . . . . . . . . . . 3-149 3.8.5.2 watchdog timer control register 1 . . . . . . . . . . . . . . . . . . . . . . 3-151 3.8.5.3 watchdog timer status register . . . . . . . . . . . . . . . . . . . . . . . . . 3-152 3.9 emergency stop output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-155 3.9.1 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-157 3.10 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-159 3.10.1 interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-160 3.11 nmi trap generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-171 3.11.1 trap control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-172 3.12 miscellaneous system control register . . . . . . . . . . . . . . . . . . . . . . . 3-181 3.12.1 gpta input in1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-181 3.12.2 system control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-181 3.12.3 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-183 3.12.4 memory test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-187 3.12.4.1 register memtest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-187 3.12.5 scu kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-187 3.12.6 scu address area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-193 4 on-chip system buses and bus bridges . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 what is new . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 sri crossbar (xbar_sri) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1.1 xbar_sri features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.2 sri transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.3 sri op-codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.2.4 sri error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.5 sri transaction id error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.6 operational overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.6.1 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.2.7 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.7.1 arbitration block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.7.2 default slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.2.7.3 sri ecc error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.2.7.4 error tracking capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-7 v1.1, 2011-03 4.2.7.5 debug trigger event ge neration (ocds level 1) . . . . . . . . . . . . 4-21 4.2.7.6 interrupt and debug ev ents of the xbar_sri module . . . . . . . . . . 4-22 4.2.8 implementation of the cross bar (xba r_sri) in the TC1798 . . . . . . 4-24 4.2.8.1 mapping of sri master modules to xbar_sri master interfaces . 4-24 4.2.8.2 mapping of sri slave modules to xbar_sri slave interfaces . . . 4-25 4.2.8.3 TC1798 sri master / slave interconnection matrix . . . . . . . . . . . . 4-26 4.2.8.4 connection master-slave in xbar_sri . . . . . . . . . . . . . . . . . . . . . 4-26 4.2.9 sri crossbar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 4.2.9.1 TC1798 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 4.3 shared resource interconnect to fpi bus interface (sfi bridge) . . . . . 4-64 4.3.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64 4.4 system peripheral bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 4.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 4.4.2 bus transaction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 4.4.3 reaction of a busy slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 4.4.4 address alignment rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 4.4.5 fpi bus basic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 4.5 fpi bus control unit (sbcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 4.5.1 fpi bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 4.5.1.1 arbitration on the syst em peripheral bus . . . . . . . . . . . . . . . . . . . 4-70 4.5.1.2 starvation prevention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72 4.5.2 fpi bus error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72 4.5.3 bcu debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75 4.5.3.1 address triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75 4.5.3.2 signal status triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76 4.5.3.3 combination of triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-77 4.5.3.4 bcu breakpoint generation examples . . . . . . . . . . . . . . . . . . . . . 4-77 4.5.4 system bus control unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80 4.5.4.1 sbcu id register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82 4.5.4.2 sbcu control registers descriptions . . . . . . . . . . . . . . . . . . . . . . 4-83 4.5.4.3 sbcu error registers descriptions . . . . . . . . . . . . . . . . . . . . . . . . 4-84 4.5.4.4 sbcu ocds registers descriptions . . . . . . . . . . . . . . . . . . . . . . 4-88 4.5.4.5 sbcu service request control regist er description . . . . . . . . . 4-102 4.6 on chip bus master tag assignments . . . . . . . . . . . . . . . . . . . . . . . 4-103 5 program memory unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 generic feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 pmu configuration of TC1798 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.1 features of the bootrom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.2 features of program and data flash . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3 bootrom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4 tuning protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.5 flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-8 v1.1, 2011-03 5.5.1 definition of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.5.2 flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.5.3 flash read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.5.4 flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.5.4.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.5.4.2 command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.5.4.3 command sequence definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.5.4.4 concurrent operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.5.5 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.5.5.1 effective flash read protection . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.5.2 effective flash write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.5.5.3 configuring flash protection in the ucb . . . . . . . . . . . . . . . . . . . . 5-21 5.5.5.4 system wide effects of flash protection . . . . . . . . . . . . . . . . . . . . 5-22 5.5.6 data integrity and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.5.6.1 ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.5.6.2 margin checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.5.7 interrupts and traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.5.8 reset and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.5.9 power reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.6 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.6.1 pmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.6.1.1 pmu identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.6.2 flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.6.2.1 flash status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.6.2.2 flash configuration control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5.6.2.3 flash read buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 5.6.2.4 flash identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 5.6.2.5 flash reservation semaphore . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48 5.6.2.6 margin check control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 5.6.2.7 protection configuration in dication . . . . . . . . . . . . . . . . . . . . . . . . 5-52 5.6.2.8 flash ecc access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 5.6.2.9 she secure internal flash boot . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 5.7 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 5.7.1 changes with respect to audo-ng and audo-f . . . . . . . . . . . . . . . . 5-64 5.7.2 performing flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 5.7.3 eeprom emulation with dflash . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 5.7.3.1 robust eeprom emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5.7.4 performance considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5.7.5 handling flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 5.7.6 cooperation with she . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70 5.7.7 handling errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71 5.7.7.1 handling errors during o peration . . . . . . . . . . . . . . . . . . . . . . . . . 5-71 5.7.7.2 handling errors during startup . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-9 v1.1, 2011-03 5.7.8 resets during flash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-76 5.7.8.1 general advice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77 5.7.8.2 advice for eeprom emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77 5.7.8.3 recovery from aborted logical sect or erase (?alse?) . . . . . . . . 5-78 5.7.9 ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79 6 local memory unit (lmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 local memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.3 emulation memory (emem) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.4 online data acquisition (olda) and its overlay . . . . . . . . . . . . . . . . . . . 6-3 6.5 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.6 lmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 7 data access overlay (ovc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1 basic overlay control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 online data acquisition (olda) and its overlay . . . . . . . . . . . . . . . . . . . 7-4 7.3 enable control of overlay blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.4 target and overlay memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.4.1 target memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.4.2 internal overlay memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.4.3 emulation overlay memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.4.4 external overlay memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5 change of overlay parameters and overlay st art . . . . . . . . . . . . . . . . . 7-6 7.6 concurrent matches and access performance . . . . . . . . . . . . . . . . . . . . 7-6 7.7 overlay control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 8bootrom content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1 startup software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 boot options summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.2 startup software main flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.2.1 entering the startup software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.1.2.2 initial handling of the st artup configuration . . . . . . . . . . . . . . . . . . 8-3 8.1.2.3 flash rampup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.1.2.4 basic device settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.1.2.5 select and prepare startup modes . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.1.2.6 final chip settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.1.2.7 ending the ssw and starti ng the user code . . . . . . . . . . . . . . . . . 8-8 8.1.3 specific ssw features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.1.3.1 header check in alternate boot modes . . . . . . . . . . . . . . . . . . . . . 8-9 8.1.4 startup errors handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.2 bootstrap loaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.2.1 common procedures for all bootloaders . . . . . . . . . . . . . . . . . . . . . . 8-13 8.2.2 asc bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-10 v1.1, 2011-03 8.2.3 can bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8.3 additional information and usage hints . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.3.1 conditions upon user code start . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.3.2 rams handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.3.3 influencing the next ssw-execution . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.3.4 TC1798 registers modified by ssw . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 9 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1 what is new . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 how to read the address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3 contents of the segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.4 address map of the on chip bus system . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.4.1 segments 0 to 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.4.2 segment 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.5 memory module access restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 9.6 side effects from modules to data sc ratch pad sram (dspr) . . . . . . 9-22 10 general purpose i/o ports and peripheral i/o lines (ports) . . . . . . 10-1 10.1 basic port operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2 description scheme for the port io functions . . . . . . . . . . . . . . . . . . . 10-5 10.3 port register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.1 port input/output control registers . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.3.2 pad driver mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10.3.3 pin function decision control register . . . . . . . . . . . . . . . . . . . . . . 10-20 10.3.4 port output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.3.5 port output modification register . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.3.6 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.3.7 port input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.4 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.4.1 port 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.4.2 port 0 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.4.3 port 0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.4.3.1 port 0 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.5 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 10.5.1 port 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 10.5.2 port 1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34 10.5.3 port 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37 10.5.3.1 port 1 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . . . 10-38 10.6 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 10.6.1 port 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 10.6.2 port 2 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 10.6.3 port 2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44 10.6.3.1 port 2 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44 10.6.3.2 port 2 output modification register . . . . . . . . . . . . . . . . . . . . . . . 10-44 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-11 v1.1, 2011-03 10.6.3.3 port 2 input/output cont rol register 0 . . . . . . . . . . . . . . . . . . . . 10-45 10.6.3.4 port 2 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-45 10.6.3.5 port 2 pad driver mode 0 register . . . . . . . . . . . . . . . . . . . . . . . 10-46 10.6.3.6 port 2 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . . . 10-46 10.7 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48 10.7.1 port 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48 10.7.2 port 3 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48 10.7.3 port 3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-54 10.8 port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-55 10.8.1 port 4 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-55 10.8.2 port 4 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-55 10.8.3 port 4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-60 10.9 port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-62 10.9.1 port 5 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-64 10.9.2 port 5 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-64 10.9.3 port 5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-69 10.9.3.1 port 5 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-69 10.9.3.2 port 5 output modification register . . . . . . . . . . . . . . . . . . . . . . . 10-69 10.9.3.3 port 5 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-69 10.9.3.4 port 5 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . . . 10-69 10.10 port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-70 10.10.1 port 6 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-70 10.10.2 port 6 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-71 10.10.3 port 6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-75 10.10.3.1 port 6 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-75 10.10.3.2 port 6 output modification register . . . . . . . . . . . . . . . . . . . . . . . 10-75 10.10.3.3 port 6 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-75 10.10.3.4 port 6 pad driver mode 0 register . . . . . . . . . . . . . . . . . . . . . . . 10-76 10.11 port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-77 10.11.1 port 7 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-77 10.11.2 port 7 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-78 10.11.3 port 7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-80 10.11.3.1 port 7 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-80 10.11.3.2 port 7 output modification register . . . . . . . . . . . . . . . . . . . . . . . 10-80 10.11.3.3 port 7 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-80 10.12 port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-81 10.12.1 port 8 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-81 10.12.2 port 8 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-82 10.12.3 port 8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-85 10.12.3.1 port 8 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-85 10.12.3.2 port 8 output modification register . . . . . . . . . . . . . . . . . . . . . . . 10-85 10.12.3.3 port 8 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-85 10.12.3.4 port 8 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . . . 10-85 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-12 v1.1, 2011-03 10.13 port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-86 10.13.1 port 9 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-86 10.13.2 port 9 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-87 10.13.3 port 9 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-92 10.13.3.1 port 9 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-92 10.13.3.2 port 9 output modification register . . . . . . . . . . . . . . . . . . . . . . . 10-92 10.13.3.3 port 9 input/output control register 8 . . . . . . . . . . . . . . . . . . . . 10-93 10.13.3.4 port 9 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-93 10.13.3.5 port 9 pad driver mode 1 register . . . . . . . . . . . . . . . . . . . . . . . 10-94 10.13.3.6 port 9 pad driver mode 1 register . . . . . . . . . . . . . . . . . . . . . . . 10-95 10.13.3.7 port 9 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . . . 10-95 10.14 port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-96 10.14.1 port 10 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-96 10.14.2 port 10 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-96 10.14.3 port 10 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-98 10.14.3.1 port 10 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-98 10.14.3.2 port 10 output modification register . . . . . . . . . . . . . . . . . . . . . . 10-98 10.14.3.3 port 10 input/output control register 4 . . . . . . . . . . . . . . . . . . . 10-99 10.14.3.4 port 10 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-99 10.14.3.5 port 10 pad driver mode 0 register . . . . . . . . . . . . . . . . . . . . . 10-100 10.15 port 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-101 10.15.1 port 11 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-101 10.15.2 port 11 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-102 10.15.3 port 11 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-106 10.16 port 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-107 10.16.1 port 12 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-107 10.16.2 port 12 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-108 10.16.3 port 12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-109 10.16.3.1 port 12 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-110 10.16.3.2 port 12 output modification register . . . . . . . . . . . . . . . . . . . . . 10-110 10.16.3.3 port 12 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-110 10.17 port 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-111 10.17.1 port 13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-111 10.17.2 port 13 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-112 10.17.3 port 13 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-117 10.17.3.1 port 13 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . 10-117 10.18 port 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-118 10.18.1 port 14 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-118 10.18.2 port 14 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-119 10.18.3 port 14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-124 10.18.3.1 port 14 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . 10-124 10.19 port 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-125 10.19.1 port 15 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-125 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-13 v1.1, 2011-03 10.19.2 port 15 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-126 10.19.3 port 15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-131 10.20 port 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-132 10.20.1 port 16 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-132 10.20.2 port 16 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-133 10.20.3 port 16 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-137 10.20.3.1 port 16 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-137 10.20.3.2 port 16 output modification register . . . . . . . . . . . . . . . . . . . . . 10-137 10.20.3.3 port 16 input/output control register 12 . . . . . . . . . . . . . . . . . 10-138 10.20.3.4 port 16 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-138 10.20.3.5 port 16 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . 10-139 10.20.3.6 port 16 pad driver mode 1 register . . . . . . . . . . . . . . . . . . . . . 10-140 10.21 port 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-141 10.21.1 port 17 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-141 10.21.2 port 17 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-142 10.21.3 port 17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-144 10.21.4 port 17 input/output control registers . . . . . . . . . . . . . . . . . . . . . 10-145 10.21.5 port 17 pin function decision control register . . . . . . . . . . . . . . 10-148 10.22 port 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-152 10.22.1 port 18 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-152 10.22.2 port 18 function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-153 10.22.3 port 18 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-155 10.22.3.1 port 18 output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-155 10.22.3.2 port 18 output modification register . . . . . . . . . . . . . . . . . . . . . 10-155 10.22.3.3 port 18 input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-155 10.22.3.4 port 18 emergency stop register . . . . . . . . . . . . . . . . . . . . . . . 10-155 11 peripheral control processor (pcp) . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 pcp feature/enhancement history list . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.1 switchable core clock ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 peripheral control processor overview . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.1 high integrity operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.3 pcp architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3.1 pcp processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.3.2 pcp code memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3.2.1 cmem protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3.3 pcp parameter ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3.3.1 pram protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.4 fpi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.5 pcp interrupt control unit and service request nodes . . . . . . . . . . 11-6 11.4 pcp programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.4.1 general purpose register set of the pcp . . . . . . . . . . . . . . . . . . . . 11-8 11.4.1.1 register r0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-14 v1.1, 2011-03 11.4.1.2 registers r1, r2, and r3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.4.1.3 registers r4 and r5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.4.1.4 register r6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.4.1.5 register r7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.4.2 contexts and context models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.4.2.1 context models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.4.2.2 context save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.4.2.3 context restore operation for cr6 an d cr7 . . . . . . . . . . . . . . . 11-19 11.4.2.4 context save operation for cr6 and cr7 . . . . . . . . . . . . . . . . . 11-23 11.4.2.5 initialization of the contexts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.4.2.6 context save optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.4.3 channel programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.4.3.1 channel restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.4.3.2 channel resume mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.5 pcp operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11.5.1 pcp initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11.5.2 channel invocation and context restore operation . . . . . . . . . . . . 11-30 11.5.3 channel exit and context save operation . . . . . . . . . . . . . . . . . . . 11-31 11.5.3.1 normal exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11.5.3.2 error condition channel exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.5.3.3 debug exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11.6 pcp interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 11.6.1 issuing service requests to cpu or pcp . . . . . . . . . . . . . . . . . . . . 11-35 11.6.2 pcp interrupt control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 11.6.3 pcp service request nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 11.6.4 issuing pcp service requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 11.6.4.1 service request on exit instruction . . . . . . . . . . . . . . . . . . . . . . 11-37 11.6.4.2 service request on suspension of inte rrupt . . . . . . . . . . . . . . . . 11-37 11.6.4.3 service request on error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 11.6.4.4 queue full operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 11.7 pram protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 11.7.1 protection of pram against fpi writes . . . . . . . . . . . . . . . . . . . . . . 11-41 11.7.2 protection of pram against internal ly generated pram writes . . 11-41 11.7.2.1 context save region protection . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 11.7.2.2 protected channel pram protection . . . . . . . . . . . . . . . . . . . . . 11-42 11.8 fpi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11.8.1 operation as an fpi master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11.8.2 operation as an fpi slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 11.9 pcp error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.9.1 pram protection violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.9.1.1 enforced pram pa rtitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.9.1.2 protected channel pram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11.9.2 fpi write window violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-15 v1.1, 2011-03 11.9.3 channel watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11.9.4 invalid opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11.9.5 instruction address error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11.10 software in-system test support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11.11 memory integrity error detection and correct ion . . . . . . . . . . . . . . . . 11-47 11.11.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 11.11.2 architectural extensions - registers . . . . . . . . . . . . . . . . . . . . . . . . 11-48 11.11.3 memory integrity error control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 11.12 instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49 11.12.1 dma primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49 11.12.2 load and store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50 11.12.3 arithmetic and logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . 11-51 11.12.4 bit manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-53 11.12.5 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-53 11.12.6 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-54 11.12.6.1 fpi bus addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-54 11.12.6.2 pram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-55 11.12.6.3 bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-55 11.12.6.4 flow control destination addressing . . . . . . . . . . . . . . . . . . . . . . 11-55 11.13 fpi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-57 11.13.1 access to the pcp control registers from the fpi bus . . . . . . . . . 11-57 11.13.1.1 pcp control register protection . . . . . . . . . . . . . . . . . . . . . . . . . 11-57 11.13.2 access to the pram from the fpi bus . . . . . . . . . . . . . . . . . . . . . . 11-58 11.13.3 access to the cmem from the fpi bus . . . . . . . . . . . . . . . . . . . . . . 11-58 11.14 debugging the pcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-60 11.15 pcp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-62 11.16 pcp registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-66 11.17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-67 11.17.1 pcp clock control register, pcp_clc . . . . . . . . . . . . . . . . . . . . . 11-67 11.17.2 pcp module identification register, pcp_id . . . . . . . . . . . . . . . . . 11-68 11.17.3 pcp control and status register, pcp_cs . . . . . . . . . . . . . . . . . . 11-69 11.17.4 pcp error/debug status register, pcp_es . . . . . . . . . . . . . . . . . . 11-71 11.17.5 pcp interrupt control register, pcp_icr . . . . . . . . . . . . . . . . . . . 11-73 11.17.6 pcp interrupt threshold register, pcp_it r . . . . . . . . . . . . . . . . . 11-76 11.17.7 pcp interrupt configuration register, pcp_icon . . . . . . . . . . . . . 11-77 11.17.8 pcp stall status register, pcp_ssr . . . . . . . . . . . . . . . . . . . . . . . 11-79 11.17.9 sist mode access control register, pcp_smacon . . . . . . . . . . 11-81 11.17.10 memory integrity erro r control register, pcp_miecon . . . . . . . . 11-82 11.17.11 memory integrity e rror status register for pram, pcp_miestatp 11-83 11.17.12 memory integrity e rror status register for cmem, pcp_miestatc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-84 11.17.13 register protection register, pcp_rprot . . . . . . . . . . . . . . . . . . 11-85 11.17.14 cmem protection register, pcp_cprot . . . . . . . . . . . . . . . . . . . 11-86 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-16 v1.1, 2011-03 11.17.15 pram protection register , pcp_pprot . . . . . . . . . . . . . . . . . . . . 11-87 11.17.16 fpi write window register, pcp_fwwin . . . . . . . . . . . . . . . . . . . 11-91 11.17.17 pcp service request control registers m, pcp_src[1:0] . . . . . . 11-92 11.17.18 pcp service request control registers m, pcp_src[3:2] . . . . . . 11-94 11.17.19 pcp service request control registers m, pcp_src[8:4] . . . . . . 11-95 11.17.20 pcp service request control registers m, pcp_src[11:9] . . . . . 11-96 11.18 pcp instruction set details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-98 11.18.1 instruction codes and fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-98 11.18.1.1 conditional codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-99 11.18.1.2 instruction fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-100 11.18.2 counter operation for copy instruction . . . . . . . . . . . . . . . . . . . . 11-103 11.18.3 counter operation for bcopy instruction . . . . . . . . . . . . . . . . . . . 11-104 11.18.4 divide and multiply instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-105 11.18.5 add, 32-bit addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-106 11.18.6 and, 32-bit logical and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-107 11.18.7 bcopy, dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-108 11.18.8 chkb, check bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-109 11.18.9 clr, clear bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-109 11.18.10 comp, 32-bit compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-110 11.18.11 copy, dma instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-111 11.18.12 debug, debug instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-112 11.18.13 dinit, divide initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113 11.18.14 dstep, divide instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-114 11.18.15 exit, exit instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-115 11.18.16 inb, insert bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-116 11.18.17 jc, jump conditionally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-117 11.18.18 jl, jump long unconditional . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-118 11.18.19 ld, load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-118 11.18.20 ldl, load 16-bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-120 11.18.21 minit, multiply initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-120 11.18.22 mov, move register to r egister . . . . . . . . . . . . . . . . . . . . . . . . . . 11-121 11.18.23 multiply instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-122 11.18.24 neg, negate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-123 11.18.25 nop, no operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-123 11.18.26 not, logical not . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-123 11.18.27 or, logical or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-124 11.18.28 pram bit operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-125 11.18.29 pri, prioritize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-126 11.18.30 rl, rotate left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-127 11.18.31 rr, rotate right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-127 11.18.32 set, set bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-128 11.18.33 shl, shift left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-128 11.18.34 shr, shift right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-129 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-17 v1.1, 2011-03 11.18.35 st, store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-130 11.18.36 sub, 32-bit subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-131 11.18.37 xch, exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-132 11.18.38 xor, 32-bit logical exclusive or . . . . . . . . . . . . . . . . . . . . . . . . . 11-133 11.18.39 flag updates of instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-134 11.18.40 instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-135 11.19 instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-139 11.20 programming of the pcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-145 11.20.1 initial pc of a channel program . . . . . . . . . . . . . . . . . . . . . . . . . . 11-145 11.20.1.1 channel entry table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-145 11.20.1.2 channel resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-146 11.20.2 channel management for small and minimum contexts . . . . . . . 11-147 11.20.3 unused registers as global?s or consta nts . . . . . . . . . . . . . . . . . 11-147 11.20.4 dispatch of low priority tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-148 11.20.5 code reuse across channels (call and return) . . . . . . . . . . . . . 11-148 11.20.6 case-like code switches (computed go-to) . . . . . . . . . . . . . . . . 11-149 11.20.7 simple dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-149 11.20.7.1 copy instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-149 11.20.7.2 bcopy instruction (burst copy) . . . . . . . . . . . . . . . . . . . . . . . . 11-150 11.21 pcp programming notes and tips . . . . . . . . . . . . . . . . . . . . . . . . . . 11-151 11.21.1 notes on pcp configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-151 11.21.2 general purpose register use . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-151 11.21.3 use of channel interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-153 11.21.3.1 dynamic interrupt masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-153 11.21.3.2 control of channel priority (cppn) . . . . . . . . . . . . . . . . . . . . . . 11-153 11.21.4 implementing divide algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . 11-154 11.21.5 implementing multiply algorithms . . . . . . . . . . . . . . . . . . . . . . . . . 11-155 11.22 implementation of the pcp in the TC1798 . . . . . . . . . . . . . . . . . . . . 11-157 11.22.1 pcp memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-157 11.22.2 bcopy instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-157 11.22.3 pcp reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-157 12 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . 12-1 12.1 what is new . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 dma controller kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.2.2 definition of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.3 dma principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.2.4 dma channel functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.2.4.1 shadowed source or destination addre ss . . . . . . . . . . . . . . . . . . 12-6 12.2.4.2 dma channel request control . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 12.2.4.3 dma channel operation modes . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12.2.4.4 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-18 v1.1, 2011-03 12.2.4.5 channel reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 12.2.4.6 transfer count and move count . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 12.2.4.7 circular buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.2.5 transaction control engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.2.6 bus switch, bus switch priorities . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 12.2.7 dma module priorities on on chip busses (fpi bus, sri bus) . . . 12-23 12.2.8 dma module: on chip bus access rights, rmw support . . . . . . . 12-24 12.2.9 dma module on chip bus master interfaces . . . . . . . . . . . . . . . . . 12-25 12.2.10 dma module bridge functionality . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 12.2.11 on-chip debug capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 12.2.11.1 hard-suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 12.2.11.2 soft-suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 12.2.11.3 break signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12.2.12 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12.2.12.1 channel interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12.2.12.2 transaction lost interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 12.2.12.3 move engine interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33 12.2.12.4 wrap buffer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35 12.2.12.5 interrupt request compressor . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36 12.2.13 pattern detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37 12.2.13.1 pattern compare l ogic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12.2.13.2 pattern detection for 8- bit data width . . . . . . . . . . . . . . . . . . . . . 12-40 12.2.13.3 pattern detection for 16- bit data width . . . . . . . . . . . . . . . . . . . . 12-41 12.2.13.4 pattern detection for 32- bit data width . . . . . . . . . . . . . . . . . . . . 12-43 12.2.14 access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44 12.3 dma module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47 12.3.1 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 12.3.2 general control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59 12.3.3 move engine registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-78 12.3.4 channel control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . . 12-85 12.3.5 channel address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-97 12.4 dma module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-100 12.4.1 dma request wiring matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-101 12.4.2 access protection assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-111 12.4.3 implementation-specific dma registers . . . . . . . . . . . . . . . . . . . . 12-123 12.4.3.1 clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-125 12.4.3.2 dma interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-126 12.4.3.3 mli interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-127 12.4.4 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-129 12.5 memory checker module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-130 12.5.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-130 12.5.1.1 ethernet crc-32 endianness . . . . . . . . . . . . . . . . . . . . . . . . . . 12-131 12.5.2 memory checker module registers . . . . . . . . . . . . . . . . . . . . . . . 12-132 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-19 v1.1, 2011-03 12.5.2.1 memory checker module control registers . . . . . . . . . . . . . . . 12-133 13 safe direct memory access controller (sdma) . . . . . . . . . . . . . . . . 13-1 13.1 what is new . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2 sdma controller kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.2.2 definition of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2.3 sdma principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.2.4 sdma channel functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.2.4.1 shadowed source or destination addre ss . . . . . . . . . . . . . . . . . . 13-6 13.2.4.2 sdma channel request control . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.2.4.3 sdma channel operation modes . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.2.4.4 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.2.4.5 channel reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.2.4.6 transfer count and move count . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.2.4.7 circular buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.2.5 transaction control engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 13.2.6 bus switch, bus switch priorities . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 13.2.7 sdma module: on chip bus access rights, rmw support . . . . . . 13-21 13.2.8 sdma on chip bus fpi master interface . . . . . . . . . . . . . . . . . . . . 13-21 13.2.9 on-chip debug capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.2.9.1 hard-suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.2.9.2 soft-suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.2.9.3 break signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24 13.2.10 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26 13.2.10.1 channel interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26 13.2.10.2 transaction lost interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28 13.2.10.3 move engine interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29 13.2.10.4 wrap buffer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30 13.2.10.5 interrupt request compressor . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.2.11 pattern detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32 13.2.11.1 pattern compare l ogic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34 13.2.11.2 pattern detection for 8- bit data width . . . . . . . . . . . . . . . . . . . . . 13-35 13.2.11.3 pattern detection for 16- bit data width . . . . . . . . . . . . . . . . . . . . 13-36 13.2.11.4 pattern detection for 32- bit data width . . . . . . . . . . . . . . . . . . . . 13-38 13.2.12 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-38 13.2.13 sdma checksums . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39 13.3 sdma module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40 13.3.1 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-46 13.3.2 general control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . . 13-51 13.3.3 move engine registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-62 13.3.4 channel control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . . 13-65 13.3.5 channel address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-77 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-20 v1.1, 2011-03 13.3.6 memory protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-80 13.3.7 channel crc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-82 13.4 sdma module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-84 13.4.1 sdma request wiring matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-84 13.4.2 implementation-specific sd ma registers . . . . . . . . . . . . . . . . . . . . 13-90 13.4.2.1 clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-92 13.4.2.2 sdma interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-94 13.4.3 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-95 14 flexible crc engine (fce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 fce features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.3 operational overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.4 fce functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.5 interfaces of the fce module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14.6 fce module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14 14.6.1 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17 14.6.2 crc kernel control/status registers . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.7 programming guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28 14.8 properties of crc code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31 15 sri external bus unit (ebu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.3 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.4 differences between audo-future and audo-max ebus . . . . . . . . . . . 15-3 15.5 ebu interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.5.1 address/data bus, ad[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.5.2 address bus, a[27:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.5.3 global chip select, cscomb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.5.4 chip selects, cs[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.5.5 read/write control lines, rd , rd/wr . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.5.6 address valid, adv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.5.7 byte controls, bc[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.5.8 burst flash clock output/input, bfclko/bfclko /bfclki . . . . . . 15-8 15.5.9 wait input, wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.5.10 burst address advance, baa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.5.11 motorola peripheral write signal, mr/w . . . . . . . . . . . . . . . . . . . . . . 15-8 15.5.12 onfi 2.0 clock output, oclko . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.5.13 ddr clock output/input ddrclko/ddrclko /sdclki . . . . . . . . . 15-9 15.5.14 lpddr-nvm, ddram, sdram control signals, cke, cas and ras . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.5.15 ddr data strobes, dqs[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.5.16 bus arbitration signals, hold , hlda , and breq . . . . . . . . . . . . . . 15-9 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-21 v1.1, 2011-03 15.5.17 ebu reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.5.17.1 allocation of unused signals as gpio . . . . . . . . . . . . . . . . . . . . 15-10 15.6 bus state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 15.7 memory controller structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.8 memory controller read architecture . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.9 access arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.9.1 programming sequence locking . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.9.2 source access inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.10 clocking strategy and local clock generati on . . . . . . . . . . . . . . . . . . 15-16 15.10.1 clocking modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.10.2 local clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.10.3 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 15.10.4 dll operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.10.4.1 locking the dll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.10.4.2 dll operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.10.4.3 dll related access error conditions . . . . . . . . . . . . . . . . . . . . . 15-22 15.10.4.4 dq and dqm outputs (ebu_dllcon.wr_en=1 b ) . . . . . . . . . 15-22 15.10.4.5 dqs inputs (ebu_dllcon.rd_en=1 b ) . . . . . . . . . . . . . . . . . . 15-22 15.10.4.6 duty cycle correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 15.10.5 dll drift detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 15.10.6 generation of ddr control signals without using the dll . . . . . . . 15-24 15.10.7 read data capture for ddr devices . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.10.7.1 read data fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.10.7.2 fifo bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.10.8 external bus clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26 15.11 external bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28 15.11.1 external bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28 15.11.2 arbitration signals and pa rameters . . . . . . . . . . . . . . . . . . . . . . . . . 15-28 15.11.3 arbitration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30 15.11.3.1 no bus arbitration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30 15.11.3.2 sole master arbitration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30 15.11.3.3 arbiter mode arbitration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30 15.11.3.4 ?participant mode? arbitration mode . . . . . . . . . . . . . . . . . . . . . . 15-35 15.11.4 switching arbitration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38 15.11.4.1 exiting no bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38 15.11.4.2 exiting sole master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38 15.11.4.3 exiting arbiter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38 15.11.4.4 exiting participant mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39 15.11.5 arbitration input signal sampling . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39 15.11.6 locking the external bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39 15.11.7 interaction with debug system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40 15.11.8 arbitrating sdram control signals . . . . . . . . . . . . . . . . . . . . . . . . . 15-40 15.12 start-up/boot process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-22 v1.1, 2011-03 15.12.1 disabled (arbitration mode is ?nobus?) . . . . . . . . . . . . . . . . . . . . . . . 15-41 15.12.2 external boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41 15.12.2.1 configuration word fetch process . . . . . . . . . . . . . . . . . . . . . . . 15-42 15.12.2.2 boot configuration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-44 15.13 accessing the external bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-45 15.13.1 external memory regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-45 15.13.2 address comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-48 15.13.2.1 operation address comparison . . . . . . . . . . . . . . . . . . . . . . . . . 15-48 15.13.3 sri bus width translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-51 15.13.4 address alignment during bus accesses . . . . . . . . . . . . . . . . . . . . 15-52 15.13.5 sri data buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-52 15.13.6 chip select control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-53 15.13.7 combined chip select (cscomb ) . . . . . . . . . . . . . . . . . . . . . . . . . 15-53 15.14 connecting external memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-53 15.14.1 programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-54 15.14.2 support for multiplexed device configurations . . . . . . . . . . . . . . . . 15-55 15.14.2.1 twin 16-bit multiplexed device confi guration . . . . . . . . . . . . . . . 15-56 15.14.2.2 16-bit multiplexed memory/peripheral configuration . . . . . . . . . . 15-57 15.14.2.3 8-bit multiplexed memory/peripheral configuration . . . . . . . . . . . 15-58 15.14.2.4 32-bit multiplexed memory/peripheral configuration . . . . . . . . . . 15-58 15.14.3 support for non-multiplexed device configurations . . . . . . . . . . . . 15-59 15.14.3.1 16-bit non-multiplexed memory/peripheral configuration . . . . . . 15-60 15.14.3.2 8-bit non-multiplexed memory/peripheral configuration . . . . . . . 15-60 15.14.3.3 32-bit non-multiplexed memory/peripheral configuration . . . . . . 15-61 15.14.3.4 twin, 16-bit non-multiplexed memo ry/peripheral configuration . 15-61 15.15 phases for asynchronous and synchronous accesses . . . . . . . . . . . 15-62 15.15.1 address phase (ap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-63 15.15.2 address hold phase (ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-64 15.15.3 command delay phase (cd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-64 15.15.4 command phase (cp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-64 15.15.5 data hold phase (dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-65 15.15.5.1 exceptional use of data hold . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-65 15.15.6 burst phase (bp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-65 15.15.7 control hold (ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-66 15.15.8 recovery phase (rp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-67 15.16 asynchronous read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 15-69 15.16.1 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-69 15.16.2 standard asynchronous access phases . . . . . . . . . . . . . . . . . . . . . 15-70 15.16.3 example waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-70 15.16.4 control of adv & other signal delays during asynchronous accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-73 15.16.5 programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-74 15.16.6 asynchronous access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-75 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-23 v1.1, 2011-03 15.16.6.1 external extension of the command phase by wait . . . . . . . . . 15-76 15.16.7 interaction with ddr signal timing . . . . . . . . . . . . . . . . . . . . . . . . . 15-80 15.16.8 interfacing to asynchronous nand flas h devices . . . . . . . . . . . . . . 15-80 15.16.8.1 nand flash page mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-81 15.17 synchronous read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 15-85 15.17.1 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-86 15.17.2 support for four burst flash device types . . . . . . . . . . . . . . . . . . . 15-86 15.17.3 typical burst flash connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-87 15.17.4 standard access phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-88 15.17.5 example waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-88 15.17.6 burst length control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-91 15.17.7 burst flash clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-91 15.17.8 control of adv & control signal delays during synchronous accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-92 15.17.9 interaction with ddr signal timing . . . . . . . . . . . . . . . . . . . . . . . . . 15-95 15.17.10 burst flash clock feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-96 15.17.11 asynchronous address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-96 15.17.12 critical word first read accesses . . . . . . . . . . . . . . . . . . . . . . . . . 15-96 15.17.13 example burst flash access cycle . . . . . . . . . . . . . . . . . . . . . . . . . 15-97 15.17.14 external cycle control via the wait input . . . . . . . . . . . . . . . . . . . 15-99 15.17.15 flash non-array access support . . . . . . . . . . . . . . . . . . . . . . . . . 15-101 15.17.16 termination of a burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-101 15.17.17 burst flash device programming sequenc es . . . . . . . . . . . . . . . . 15-101 15.17.18 cellular ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-102 15.17.18.1 synchronous write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-102 15.17.18.2 fujitsu fcram support (burst write with wr active during data phase) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-104 15.17.19 ddr burst flash support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-104 15.17.19.1 ddr nor burst flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-105 15.17.19.2 onfi 2.0 nand flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-108 15.17.20 programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-111 15.18 sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-113 15.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-113 15.18.2 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-114 15.18.3 external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-115 15.18.4 sdram external bus clock generation . . . . . . . . . . . . . . . . . . . . 15-117 15.18.5 sdram characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-118 15.18.6 supported sdram commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-119 15.18.7 sdram device size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-120 15.18.8 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-121 15.18.9 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-121 15.18.9.1 cold start initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-121 15.18.9.2 warm start initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-123 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-24 v1.1, 2011-03 15.18.10 mobile sdram support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-124 15.18.11 burst accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-124 15.18.12 short burst accesses and byte writes . . . . . . . . . . . . . . . . . . . . . 15-125 15.18.13 sdram addressing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-125 15.18.14 bank address multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-126 15.18.15 column address multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-127 15.18.16 row address multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-128 15.18.17 supported sdram configurations . . . . . . . . . . . . . . . . . . . . . . . . 15-129 15.18.18 sdram bank management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-131 15.18.18.1 decisions over ?row hit? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-132 15.18.19 banks precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-132 15.18.20 refresh cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-133 15.18.21 self-refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-133 15.18.22 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-134 15.18.23 sdram recovery phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-135 15.18.23.1 recovery after sdram command . . . . . . . . . . . . . . . . . . . . . . 15-136 15.18.23.2 write recovery time (t wrc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-136 15.18.24 status register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-136 15.18.24.1 refresh error (referr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-136 15.18.24.2 sdram controller busy (sdrmbusy) . . . . . . . . . . . . . . . . . . 15-137 15.18.24.3 sdram read error (sderr) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-137 15.18.24.4 dll drift detected (drift_warn) . . . . . . . . . . . . . . . . . . . . . 15-137 15.18.25 programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-137 15.19 ddram/mobile ddram support . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-140 15.19.1 ddr mode address outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-142 15.19.2 ddram initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-142 15.19.2.1 cold start initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-143 15.19.2.2 warm start initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-143 15.19.3 ddr external bus clock ge neration . . . . . . . . . . . . . . . . . . . . . . . 15-144 15.20 lpddr nvm flash support (jedec 42.4 lpddr-nvm protocol) . 15-144 15.20.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-144 15.20.2 implementation requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-145 15.20.3 initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-145 15.20.4 additional supported commands . . . . . . . . . . . . . . . . . . . . . . . . . 15-146 15.20.5 normal operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-146 15.20.6 status register reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-148 15.20.7 discrete mode register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-149 15.20.8 page preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-149 15.20.9 page tag control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-150 15.20.10 overlay window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-150 15.20.11 clearing the read fifo error flag . . . . . . . . . . . . . . . . . . . . . . . . 15-151 15.20.12 lpddr-nvm access programmable parameters . . . . . . . . . . . . . 15-151 15.21 ebu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-153 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-25 v1.1, 2011-03 15.21.1 clock control register, clc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-156 15.21.2 configuration register, modcon . . . . . . . . . . . . . . . . . . . . . . . . . 15-158 15.21.3 external boot configuration contro l register, extboot . . . . . . . 15-161 15.21.4 address select register, addrselx . . . . . . . . . . . . . . . . . . . . . . 15-163 15.21.5 bus configuration register, busrconx . . . . . . . . . . . . . . . . . . . 15-165 15.21.6 bus write configuration register, buswconx . . . . . . . . . . . . . . 15-169 15.21.7 bus read access parameter register, busrapx . . . . . . . . . . . . 15-172 15.21.8 bus write access parameter register , buswapx . . . . . . . . . . . . 15-175 15.21.9 sdram control register, sdrmcon . . . . . . . . . . . . . . . . . . . . . 15-178 15.21.10 sdram mode register, sdrmod . . . . . . . . . . . . . . . . . . . . . . . . 15-180 15.21.11 sdram refresh control register, sdrm ref . . . . . . . . . . . . . . . 15-183 15.21.12 sdram status register, sdrstat . . . . . . . . . . . . . . . . . . . . . . . 15-185 15.21.13 dll control register, ebu_dllcon . . . . . . . . . . . . . . . . . . . . . . 15-187 15.21.14 lpddr nvm configuration register, ddrncon . . . . . . . . . . . . 15-190 15.21.15 lpddr nvm mode register, ddrnmod . . . . . . . . . . . . . . . . . . 15-192 15.21.16 lpddr nvm extended mode register, ddrnmod2 . . . . . . . . . 15-194 15.21.17 lpddr nvm status register, ddrnsrr . . . . . . . . . . . . . . . . . . 15-196 15.21.18 ddr preload register, ddrnprld . . . . . . . . . . . . . . . . . . . . . . . 15-197 15.21.19 ddr tag register, ddrntagx . . . . . . . . . . . . . . . . . . . . . . . . . . 15-198 15.21.20 test/control configuration register, usercon . . . . . . . . . . . . . 15-199 15.22 registers for sfr extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-200 16 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.2 service request nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2.1 service request control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2.1.1 general service request control regi ster format . . . . . . . . . . . . 16-3 16.2.1.2 request set and clear bits (setr, clrr) . . . . . . . . . . . . . . . . . . 16-5 16.2.1.3 enable bit (sre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.2.1.4 service request flag (srr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.2.1.5 type-of-service control (tos) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.2.1.6 service request priority number (srpn) . . . . . . . . . . . . . . . . . . . 16-6 16.3 interrupt control units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16.3.1 interrupt control unit (icu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16.3.1.1 icu interrupt control register (icr) . . . . . . . . . . . . . . . . . . . . . . . 16-8 16.3.1.2 operation of the interr upt control unit (icu) . . . . . . . . . . . . . . . . 16-10 16.3.2 pcp interrupt control unit (picu) . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.4 arbitration process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.4.1 controlling the number of arbitration cycl es . . . . . . . . . . . . . . . . . . 16-12 16.4.2 controlling the duration of arbitration cycl es . . . . . . . . . . . . . . . . . 16-13 16.5 entering an interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.6 exiting an interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.7 interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-26 v1.1, 2011-03 16.8 usage of the TC1798 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . 16-18 16.8.1 spanning interrupt service routines across vector entries . . . . . . 16-18 16.8.2 configuring ordinary interrupt service routines . . . . . . . . . . . . . . . 16-19 16.8.3 interrupt priority groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19 16.8.4 splitting interrupt service across different priority levels . . . . . . . 16-20 16.8.5 using different priorities for the same interrupt source . . . . . . . . . . 16-21 16.8.6 interrupt priority 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 16.8.7 software-initiated interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 16.8.8 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 16.9 service request node table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 17 system timer (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2.1 resolution and ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2 compare register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.2.3 compare match interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.3 stm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.3.1 clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.3.2 timer/capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.3.3 compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 17.3.4 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17 17.4 stm module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 17.4.1 on-chip service request connections . . . . . . . . . . . . . . . . . . . . . . 17-21 17.4.2 stm address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 18 bus monitor unit (bmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.2 bmu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.3 operational overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.3.1 microcontroller monitoring framework . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.3.2 bus monitor unit overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.4 bmu functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.4.1 bmu microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.4.2 handling of fpi corner cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 18.4.3 bus transaction table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 18.4.4 write operation and fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . 18-14 18.4.5 read operation and fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 18.4.6 fullness monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16 18.4.7 error correction code (ecc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18 18.4.8 usage in non safety applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 18.4.9 bmu interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 18.4.10 peripheral monitoring select ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 18.5 interfaces of the bmu module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-27 v1.1, 2011-03 18.6 bmu module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 18.6.1 system registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30 18.6.2 bmu control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33 18.6.3 bmu: bus logging configuration registers . . . . . . . . . . . . . . . . . . 18-36 18.6.4 bmu: fifo monitoring registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.6.5 bmu: sist mode access control register . . . . . . . . . . . . . . . . . . . 18-46 18.6.6 interrupt system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-49 19 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.2 ocds level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.2.1 tricore cpu ocds level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.2.1.1 basic concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.2.1.2 debug event generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.2.1.3 debug actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 19.2.1.4 tricore ocds registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 19.2.2 pcp ocds level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.2.3 sbcu ocds level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.2.4 dma/sdma ocds level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.3 debug interface (cerberus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.3.1 rw mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.3.2 communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.3.3 triggered transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.3.4 multi core break switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.4 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.5 device access port (dap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.5.1 dap telegram format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.5.2 dap telegram catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.6 cerberus and jtag registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 20 asynchronous/synchronous serial interface (asc) . . . . . . . . . . . . 20-1 20.1 asc kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.1.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.1.3 asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.1.3.1 asynchronous data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.1.3.2 asynchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.1.3.3 asynchronous reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.1.3.4 rxd/txd data path selection in asynchronous modes . . . . . . . . 20-8 20.1.4 synchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.1.4.1 synchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 20.1.4.2 synchronous reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 20.1.4.3 synchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 20.1.5 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-28 v1.1, 2011-03 20.1.5.1 baud rates in asynchrono us mode . . . . . . . . . . . . . . . . . . . . . . 20-13 20.1.5.2 baud rates in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . 20-16 20.1.6 hardware error detection capabilities . . . . . . . . . . . . . . . . . . . . . . 20-17 20.1.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.2 asc kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.2.1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 20.2.2 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 20.3 asc0/asc1 module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20.3.1 interfaces of the asc modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20.3.2 asc0/asc1 module related external registers . . . . . . . . . . . . . . 20-32 20.3.2.1 clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-33 20.3.2.2 peripheral input select register . . . . . . . . . . . . . . . . . . . . . . . . . 20-35 20.3.2.3 port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-37 20.3.2.4 interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-39 20.3.3 dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-40 20.3.4 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-42 20.3.5 application hint regarding the atm featur e . . . . . . . . . . . . . . . . . 20-44 21 synchronous serial interface (ssc) . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1 ssc kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.1.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.1.2.1 operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.1.2.2 full-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 21.1.2.3 half-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.1.2.4 continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10 21.1.2.5 parity mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 21.1.2.6 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 21.1.2.7 baud rate ge neration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14 21.1.2.8 slave select input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.1.2.9 slave select output generation unit . . . . . . . . . . . . . . . . . . . . . . 21-17 21.1.2.10 error detection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-20 21.1.2.11 queued ssc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24 21.2 ssc kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 21.2.1 module identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 21.2.2 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29 21.2.3 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-42 21.3 ssc0/ssc1/ssc2/ssc3 module implementation . . . . . . . . . . . . . . . 21-43 21.3.1 module identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43 21.3.2 interfaces of the ssc modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43 21.3.3 on-chip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 21.3.4 ssc0/ssc1/ssc2/ssc3 module related external registers . . . . 21-46 21.3.4.1 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-48 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-29 v1.1, 2011-03 21.3.4.2 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-53 21.3.4.3 interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-58 21.3.5 address map of the ssc modules . . . . . . . . . . . . . . . . . . . . . . . . . . 21-59 22 synchronous serial interface guardian (sscg) . . . . . . . . . . . . . . . . 22-1 22.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.1 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2 sscg kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.2.1 details on the operation principles and the architecture . . . . . . . . . 22-3 22.2.1.1 monitoring the slave select and serial clock signals . . . . . . . . . . 22-6 22.3 sscg kernel registers, inherited from ssc . . . . . . . . . . . . . . . . . . . . . 22-8 22.3.1 module identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.3.2 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.3.3 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.3.4 sscg specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25 22.4 sscg0 module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30 22.4.1 module identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30 22.4.2 interfaces of the sscg modu les . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30 22.4.3 on-chip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-32 22.4.3.1 receive input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-32 22.4.4 ssc0/ssc1 module related external registers . . . . . . . . . . . . . . 22-33 22.4.4.1 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34 22.4.4.2 interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-39 22.4.5 sscg address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-40 23 micro second channel (msc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1 msc kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.1.2 downstream channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.1.2.1 frame formats and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.1.2.2 shift register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.1.2.3 transmission modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14 23.1.2.4 downstream counter and enable signals . . . . . . . . . . . . . . . . . . 23-19 23.1.2.5 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20 23.1.2.6 abort of frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20 23.1.3 upstream channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21 23.1.3.1 data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 23.1.3.2 parity checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 23.1.3.3 data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.1.3.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25 23.1.3.5 spike filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.1.4 i/o control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-27 23.1.4.1 downstream channel output control . . . . . . . . . . . . . . . . . . . . . 23-27 23.1.4.2 upstream channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-30 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-30 v1.1, 2011-03 23.1.5 msc interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-31 23.1.5.1 data frame interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-32 23.1.5.2 command frame interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-32 23.1.5.3 time frame finished interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 23-33 23.1.5.4 receive data interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-34 23.1.5.5 interrupt request compressor . . . . . . . . . . . . . . . . . . . . . . . . . . 23-35 23.2 msc kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-36 23.2.1 module identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-38 23.2.2 status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-39 23.2.3 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-59 23.3 msc module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-62 23.3.1 interface connections of the msc modules . . . . . . . . . . . . . . . . . . 23-62 23.3.2 msc0/msc1 module-related external regi sters . . . . . . . . . . . . . . 23-64 23.3.3 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-65 23.3.3.1 clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-67 23.3.3.2 fractional divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-68 23.3.4 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-69 23.3.4.1 input/output function selection . . . . . . . . . . . . . . . . . . . . . . . . . 23-69 23.3.5 on-chip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-72 23.3.5.1 emgstopmsc signal (from scu) . . . . . . . . . . . . . . . . . . . . . . . 23-72 23.3.5.2 altinh and altinl connections . . . . . . . . . . . . . . . . . . . . . . . . 23-72 23.3.5.3 dma controller service requests . . . . . . . . . . . . . . . . . . . . . . . . 23-73 23.3.6 interrupt control regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-74 23.3.7 msc0/msc1 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-75 24 controller area networ k controller (multican) . . . . . . . . . . . . . . . . 24-1 24.1 can basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.1 addressing and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.2 can frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.2.1 data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.2.2 remote frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.1.2.3 error frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 24.1.3 the nominal bit time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.1.4 error detection and error handling . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.2 ttcan basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.2.1 time reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.2.2 basic cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.2.3 global system time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.2.4 the system matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.2.5 generation of the network time unit (ntu ) . . . . . . . . . . . . . . . . . . 24-13 24.2.6 global time generation and drift correctio n . . . . . . . . . . . . . . . . . 24-13 24.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.3.1 multican module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-31 v1.1, 2011-03 24.4 time-triggered extension (ttcan) . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17 24.5 multican kernel functional description . . . . . . . . . . . . . . . . . . . . . . . 24-18 24.5.1 module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18 24.5.2 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21 24.5.3 port input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23 24.5.4 suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23 24.5.5 can node control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-25 24.5.5.1 bit timing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26 24.5.5.2 bitstream processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27 24.5.5.3 error handling unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28 24.5.5.4 can frame counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29 24.5.5.5 can node interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29 24.5.6 message object list structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31 24.5.6.1 basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31 24.5.6.2 list of unallocated elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32 24.5.6.3 connection to the can nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32 24.5.6.4 list command panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24.5.7 can node analysis features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36 24.5.7.1 analyze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36 24.5.7.2 loop-back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-36 24.5.7.3 bit timing analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37 24.5.8 message acceptance filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-39 24.5.8.1 receive acceptance filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-39 24.5.8.2 transmit acceptance filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-40 24.5.9 message postprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-42 24.5.9.1 message object in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-42 24.5.9.2 pending messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-44 24.5.10 message object data handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-46 24.5.10.1 frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-46 24.5.10.2 frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-49 24.5.11 message object functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-52 24.5.11.1 standard message object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-52 24.5.11.2 single data transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-52 24.5.11.3 single transmit trial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-52 24.5.11.4 message obje ct fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . 24-53 24.5.11.5 receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-55 24.5.11.6 transmit fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-56 24.5.11.7 gateway mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-57 24.5.11.8 foreign remote requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-59 24.6 multican kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-60 24.6.1 global module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-63 24.6.2 can node registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-76 24.6.3 message object registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-94 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-32 v1.1, 2011-03 24.7 time-triggered extension (ttcan controller) . . . . . . . . . . . . . . . . . 24-117 24.7.1 generation of the local time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-117 24.7.2 automatic tur adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-118 24.7.3 cycle time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-118 24.7.3.1 local time and synchronization marks . . . . . . . . . . . . . . . . . . . 24-118 24.7.3.2 time marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-119 24.7.3.3 watch trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120 24.7.4 master reference mark (level 2 only) . . . . . . . . . . . . . . . . . . . . . . 24-120 24.7.5 transmit enable window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120 24.7.6 local offset and global time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-121 24.7.7 transmit trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-122 24.7.8 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-123 24.7.8.1 differences to normal can messages . . . . . . . . . . . . . . . . . . . 24-123 24.7.8.2 transmit trigger for a reference message . . . . . . . . . . . . . . . . 24-124 24.8 ttcan scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-126 24.8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-126 24.8.2 scheduler memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-127 24.8.2.1 scheduler entry types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-128 24.8.2.2 scheduler entry type description . . . . . . . . . . . . . . . . . . . . . . . 24-129 24.8.2.3 end of scheduler memory entry . . . . . . . . . . . . . . . . . . . . . . . . 24-144 24.8.3 setup of the scheduler entries . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-145 24.8.4 reading the scheduler entries . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-145 24.8.4.1 instructions during a ba sic cycle . . . . . . . . . . . . . . . . . . . . . . . 24-145 24.8.4.2 instructions at the end of a basic cycl e . . . . . . . . . . . . . . . . . . 24-146 24.8.5 scheduler instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 24-148 24.8.5.1 bcc and csm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-148 24.8.5.2 general instruction sequence rules . . . . . . . . . . . . . . . . . . . . . 24-149 24.8.5.3 scheduler sequence example . . . . . . . . . . . . . . . . . . . . . . . . . 24-150 24.9 ttcan operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-151 24.9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-151 24.9.2 configuration error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-151 24.9.3 synchronization phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-152 24.9.4 time masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-152 24.9.4.1 state of a time master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-152 24.9.4.2 strictly time-triggered behavior . . . . . . . . . . . . . . . . . . . . . . . . 24-152 24.9.5 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-153 24.9.6 application watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-153 24.9.7 msc handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-154 24.9.8 ttcan interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-155 24.10 ttcan registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-157 24.10.1 ttcan timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-160 24.10.2 ttcan control / status / configuration registers . . . . . . . . . . . . 24-172 24.10.3 scheduler registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-195 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-33 v1.1, 2011-03 24.11 multican module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-202 24.11.1 interfaces of the multican module . . . . . . . . . . . . . . . . . . . . . . . . 24-202 24.11.2 multican module external registers . . . . . . . . . . . . . . . . . . . . . . 24-203 24.11.3 module clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-204 24.11.3.1 can clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-205 24.11.4 port and i/o line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-208 24.11.4.1 input/output function selection in ports . . . . . . . . . . . . . . . . . . 24-208 24.11.4.2 node receive input selection . . . . . . . . . . . . . . . . . . . . . . . . . . 24-208 24.11.4.3 external can time trigger inputs . . . . . . . . . . . . . . . . . . . . . . . 24-209 24.11.4.4 dma request outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-209 24.11.4.5 connectons to gpta0 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 24-210 24.11.5 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-211 24.11.5.1 can service request control register . . . . . . . . . . . . . . . . . . . 24-213 24.11.6 multican module register address map . . . . . . . . . . . . . . . . . . . 24-214 25 single edge nibble transmission (sent) . . . . . . . . . . . . . . . . . . . . . 25-1 25.1 sent kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.1.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.1.2.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.1.3 standard sent operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.1.3.1 frame formats and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.1.4 spc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.1.4.1 synchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.1.4.2 range selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.1.4.3 id selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13 25.1.4.4 bidirectional transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 25.1.4.5 spc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 25.1.4.6 abort of frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.1.5 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16 25.1.6 error detection capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18 25.1.7 digital glitch filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19 25.1.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.1.9 trigger outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21 25.2 sent kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22 25.2.1 module control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25 25.2.2 channel baud rate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-29 25.2.3 receiver control and status registers . . . . . . . . . . . . . . . . . . . . . . 25-31 25.2.4 input and output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39 25.2.5 receive data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42 25.2.6 spc control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-45 25.2.7 interrupt control regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-48 25.3 sent module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-64 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-34 v1.1, 2011-03 25.3.1 interface connections of the sent module . . . . . . . . . . . . . . . . . . 25-64 25.3.2 on-chip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-65 25.3.2.1 interrupt and dma controller service requests . . . . . . . . . . . . . 25-65 25.3.2.2 trigger inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-66 25.3.3 sent module-related external registers . . . . . . . . . . . . . . . . . . . 25-67 25.3.3.1 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-67 25.3.3.2 service request control registers . . . . . . . . . . . . . . . . . . . . . . . 25-71 25.3.4 sent register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-73 25.4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-74 26 flexray? protocol controller (e-ray) . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1 e-ray kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.3 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26.5 programmer?s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.5.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.5.2 e-ray kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.5.2.1 customer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-16 26.5.2.2 special registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23 26.5.2.3 service request registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-41 26.5.2.4 communication controller control regist ers . . . . . . . . . . . . . . . 26-88 26.5.2.5 communication controlle r status registers . . . . . . . . . . . . . . . 26-115 26.5.2.6 message buffer control registers . . . . . . . . . . . . . . . . . . . . . . . 26-138 26.5.2.7 message buffer status registers . . . . . . . . . . . . . . . . . . . . . . . 26-145 26.5.2.8 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-166 26.5.2.9 input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-168 26.5.2.10 output buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-179 26.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-196 26.6.1 communication cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-196 26.6.1.1 static segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-196 26.6.1.2 dynamic segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-197 26.6.1.3 symbol window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-197 26.6.1.4 network idle time (nit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-197 26.6.1.5 configuration of network idle time (nit) start and offset correction start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-197 26.6.2 communication modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-199 26.6.3 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-199 26.6.3.1 global time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-199 26.6.3.2 local time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-199 26.6.3.3 synchronization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-200 26.6.3.4 external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 26-201 26.6.4 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-202 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-35 v1.1, 2011-03 26.6.4.1 clock correction failed counter . . . . . . . . . . . . . . . . . . . . . . . . 26-202 26.6.4.2 passive to active counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-203 26.6.4.3 halt command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-203 26.6.4.4 freeze command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-203 26.6.5 communication controller states . . . . . . . . . . . . . . . . . . . . . . . . . 26-205 26.6.5.1 communication controller state diagram . . . . . . . . . . . . . . . . . 26-205 26.6.5.2 default_config state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-207 26.6.5.3 monitor_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-208 26.6.5.4 ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-209 26.6.5.5 wakeup state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-209 26.6.5.6 startup state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-214 26.6.5.7 startup time-outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-217 26.6.5.8 path of leading coldstart node (initiating coldstart) . . . . . . . . . . 26-218 26.6.5.9 normal_active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-220 26.6.5.10 normal_passive state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-220 26.6.5.11 halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-221 26.6.6 network management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-222 26.6.7 filtering and masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-222 26.6.7.1 frame id filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-223 26.6.7.2 channel id filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-223 26.6.7.3 cycle counter filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-224 26.6.7.4 fifo filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-225 26.6.8 transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-226 26.6.8.1 static segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-226 26.6.8.2 dynamic segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-226 26.6.8.3 transmit buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-226 26.6.8.4 frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-227 26.6.8.5 null frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-228 26.6.9 receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-229 26.6.9.1 frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-229 26.6.9.2 null frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-230 26.6.10 fifo function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-230 26.6.10.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-230 26.6.10.2 configuration of the fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-231 26.6.10.3 access to the fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-232 26.6.11 message handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-232 26.6.11.1 host access to message ram . . . . . . . . . . . . . . . . . . . . . . . . . . 26-232 26.6.11.2 data transfers between ibf / ob f and message ram . . . . . . 26-237 26.6.11.3 minimum f clc_eray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-243 26.6.11.4 flexray? protocol controller access to message ram . . . . . 26-247 26.6.12 message ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-248 26.6.12.1 header partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-250 26.6.12.2 data partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-253 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-36 v1.1, 2011-03 26.6.12.3 ecc check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-254 26.6.13 host handling of errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-257 26.6.13.1 self-healing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-257 26.6.13.2 clear_rams command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-257 26.6.13.3 temporary unlocking of header section . . . . . . . . . . . . . . . . . . 26-257 26.7 module service request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-259 26.8 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-262 26.8.1 message buffers with the same frame id . . . . . . . . . . . . . . . . . . . 26-262 26.8.2 data transfers between ibf / obf and message ram . . . . . . . . 26-262 26.9 e-ray module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-263 26.9.1 interconnections of the e-ray module . . . . . . . . . . . . . . . . . . . . . . 26-263 26.9.2 port control and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-264 26.9.2.1 input/output function selection . . . . . . . . . . . . . . . . . . . . . . . . 26-264 26.9.3 on-chip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-266 26.9.3.1 e-ray connections with dma . . . . . . . . . . . . . . . . . . . . . . . . . . 26-266 26.9.3.2 e-ray connections with the external request unit of scu . . . 26-267 26.9.3.3 e-ray connections with the ecc error handling unit of scu . 26-267 26.9.3.4 e-ray connections with the external clock output of scu . . . 26-267 26.9.4 clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-268 26.9.5 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-269 27 micro link interface (mli) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.1.1 general introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.1.1.1 mli overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.1.1.2 naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.1.1.3 mli communication principl es . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.1.2 mli frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.1.2.1 general frame layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11 27.1.2.2 copy base address frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12 27.1.2.3 write offset and data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13 27.1.2.4 optimized write frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14 27.1.2.5 discrete read frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-15 27.1.2.6 optimized read frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16 27.1.2.7 command frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17 27.1.2.8 answer frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18 27.1.3 handshake description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19 27.1.3.1 handshake signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-21 27.1.3.2 error-free handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-21 27.1.3.3 ready delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-22 27.1.3.4 non-acknowledge error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-23 27.1.3.5 signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-24 27.1.4 parity generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-26 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-37 v1.1, 2011-03 27.1.5 address prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-26 27.2 module kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-27 27.2.1 frame handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-27 27.2.1.1 copy base address frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-28 27.2.1.2 write/data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-30 27.2.1.3 read frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-34 27.2.1.4 answer frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-39 27.2.1.5 command frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-41 27.2.2 general mli features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-44 27.2.2.1 parity check and parity error indication . . . . . . . . . . . . . . . . . . . 27-44 27.2.2.2 non-acknowledge error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-47 27.2.2.3 address prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-47 27.2.2.4 automatic data mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-48 27.2.2.5 memory access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-49 27.2.2.6 triggered command transfers . . . . . . . . . . . . . . . . . . . . . . . . . . 27-49 27.2.2.7 transmit priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-50 27.2.2.8 transmission delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-50 27.2.3 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-51 27.2.3.1 transmitter i/o line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-53 27.2.3.2 receiver i/o line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-53 27.2.3.3 connecting several mli modules . . . . . . . . . . . . . . . . . . . . . . . . 27-55 27.2.4 mli service request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-57 27.2.5 transmitter events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-59 27.2.5.1 parity/time-out error event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-60 27.2.5.2 normal frame sent x event . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-60 27.2.5.3 command frame sent events . . . . . . . . . . . . . . . . . . . . . . . . . . 27-61 27.2.6 receiver events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-62 27.2.6.1 discarded read answer event . . . . . . . . . . . . . . . . . . . . . . . . . . 27-62 27.2.6.2 memory access protection/parity error event . . . . . . . . . . . . . . . 27-63 27.2.6.3 normal frame received/move engi ne terminated event . . . . . 27-64 27.2.6.4 interrupt command frame event . . . . . . . . . . . . . . . . . . . . . . . . 27-65 27.2.6.5 command frame received event . . . . . . . . . . . . . . . . . . . . . . . . 27-66 27.2.7 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-67 27.2.8 automatic register overwrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-68 27.3 operating the mli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-69 27.3.1 connection setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-70 27.3.2 local transmitter and pipe setup . . . . . . . . . . . . . . . . . . . . . . . . . . 27-71 27.3.3 remote receiver setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-71 27.3.4 remote transmitter and local receiver se tup . . . . . . . . . . . . . . . . 27-72 27.3.5 delay adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-73 27.3.6 connection to dma mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-75 27.3.7 connection of mli to spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-75 27.4 mli kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-77 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-38 v1.1, 2011-03 27.4.1 general module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-79 27.4.2 general status/control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 27-83 27.4.3 access protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-90 27.4.4 transmitter control/status registers . . . . . . . . . . . . . . . . . . . . . . . . 27-92 27.4.5 transmitter pipe x address offset register . . . . . . . . . . . . . . . . . 27-103 27.4.6 transmitter interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-107 27.4.7 receiver control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . 27-113 27.4.8 receiver address/data registers . . . . . . . . . . . . . . . . . . . . . . . . . 27-117 27.4.9 receiver interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-120 27.5 implementation of the mli0/mli1 in TC1798 . . . . . . . . . . . . . . . . . . . 27-127 27.5.1 interfaces of the mli modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-127 27.5.2 mli module external registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-130 27.5.2.1 automatic register overwr ite . . . . . . . . . . . . . . . . . . . . . . . . . . 27-130 27.5.3 module clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-131 27.5.4 port control and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-133 27.5.4.1 input/output function selection . . . . . . . . . . . . . . . . . . . . . . . . 27-133 27.5.5 on-chip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-136 27.5.5.1 service request output connections . . . . . . . . . . . . . . . . . . . . 27-136 27.5.5.2 break signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-137 27.5.5.3 trigger input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-137 27.5.6 access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-137 27.5.7 mli0/mli1 transfer window address maps . . . . . . . . . . . . . . . . . 27-138 27.5.8 mli0/mli1 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-139 28 general purpose timer array (gpta ? v5) . . . . . . . . . . . . . . . . . . . . . 28-1 28.1 what is new? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.2 gpta ? v5 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.2.1 functionality of gpta0 and gpta1 . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.2.2 functionality of ltca2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.3 gpta0/gpta1 kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8 28.3.1 gtpa units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9 28.3.2 clock generation cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10 28.3.2.1 filter and prescaler cell (fpc) . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12 28.3.2.2 phase discrimination logic (pdl) . . . . . . . . . . . . . . . . . . . . . . . . 28-21 28.3.2.3 duty cycle measurement cell (dcm) . . . . . . . . . . . . . . . . . . . . . 28-26 28.3.2.4 digital phase locked loop cell (pll) . . . . . . . . . . . . . . . . . . . . . 28-30 28.3.2.5 clock distribution cell (cdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-35 28.3.3 signal generation cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-38 28.3.3.1 global timers (gt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-38 28.3.3.2 global timer cell (gtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-55 28.3.3.3 local timer cell (ltc00 to ltc62) . . . . . . . . . . . . . . . . . . . . . . 28-67 28.3.3.4 local timer cell ltc63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-79 28.3.3.5 coherent update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-85 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-39 v1.1, 2011-03 28.3.4 input/output line sharing block (iols) . . . . . . . . . . . . . . . . . . . . . 28-98 28.3.4.1 fpc input line selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-102 28.3.4.2 gtc and ltc output multiplexer select ion . . . . . . . . . . . . . . . 28-103 28.3.4.3 on-chip trigger and gating output multiplexer selection . . . . . 28-108 28.3.4.4 gtc input multiplexer sele ction . . . . . . . . . . . . . . . . . . . . . . . . 28-111 28.3.4.5 ltc input multiplexer selection . . . . . . . . . . . . . . . . . . . . . . . . . 28-116 28.3.4.6 multiplexer register a rray programming . . . . . . . . . . . . . . . . . . 28-121 28.3.5 interrupt sharing block (is) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-123 28.3.6 pseudo code description of gpta ? v5 kernel functional ity . . . . . 28-126 28.3.6.1 fpc algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-126 28.3.6.2 pdl-algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-131 28.3.6.3 dcm-algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-135 28.3.6.4 pll-algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-138 28.3.6.5 gt-algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-140 28.3.6.6 gtc-algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-141 28.3.6.7 ltc-algorithm for cells 0 to 62 . . . . . . . . . . . . . . . . . . . . . . . . . 28-146 28.3.6.8 ltc algorithm for cell 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-154 28.3.7 programming of a gpta ? v5 unit . . . . . . . . . . . . . . . . . . . . . . . . . 28-158 28.4 gpta0/1 kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-160 28.4.1 gpta ? v5 identification register . . . . . . . . . . . . . . . . . . . . . . . . . . 28-166 28.4.2 fpc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-167 28.4.3 phase discriminator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-171 28.4.4 duty cycle measurement registers . . . . . . . . . . . . . . . . . . . . . . . 28-173 28.4.5 digital phase locked loop registers . . . . . . . . . . . . . . . . . . . . . . 28-177 28.4.6 global timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-182 28.4.7 clock bus register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-185 28.4.8 global timer cell registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-187 28.4.9 local timer cell registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-192 28.4.10 multiplexer control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-207 28.4.11 service request registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-223 28.5 ltca kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-234 28.5.1 local timer cell (ltc00 to ltc63) . . . . . . . . . . . . . . . . . . . . . . . . 28-235 28.5.2 input/output line sharing block (iols) . . . . . . . . . . . . . . . . . . . . 28-235 28.5.2.1 output multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-237 28.5.2.2 ltc input multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . 28-242 28.5.2.3 multiplexer register a rray programming . . . . . . . . . . . . . . . . . . 28-245 28.5.3 interrupt sharing block (is) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-248 28.6 ltca kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-250 28.6.1 bit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-251 28.6.2 service request registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-252 28.6.3 local timer cell registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-252 28.6.4 i/o sharing block registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-263 28.6.5 multiplexer control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-267 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-40 v1.1, 2011-03 28.6.5.1 output multiplexer control registers . . . . . . . . . . . . . . . . . . . . . 28-267 28.6.5.2 ltc input multiplexer control registers . . . . . . . . . . . . . . . . . . 28-270 28.7 gpta ? v5 module implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-274 28.7.1 interconnections of gpta0/gpta1/ltca2 units . . . . . . . . . . . . . 28-274 28.7.2 gpta ? v5 module external registers . . . . . . . . . . . . . . . . . . . . . . 28-276 28.7.3 port control and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-276 28.7.3.1 i/o port line assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-276 28.7.3.2 input/output function selection . . . . . . . . . . . . . . . . . . . . . . . . 28-279 28.7.3.3 emergency control of gpta ? v5 output ports lines . . . . . . . . . 28-284 28.7.4 on-chip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-286 28.7.4.1 clock bus connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-286 28.7.4.2 msc controller connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-287 28.7.4.3 connections to scu, multican, fadc, dma, ports . . . . . . . . . 28-294 28.7.5 module clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-296 28.7.5.1 clock control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-300 28.7.5.2 fractional divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-301 28.7.6 limits of cascading gtcs and ltcs . . . . . . . . . . . . . . . . . . . . . . 28-306 28.7.7 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-307 28.7.8 gpta register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-308 28.8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-311 29 capture/compare unit 6 (ccu6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1.1 feature set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.1.3 ccu6 kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.2 operating timer t12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 29.2.1 t12 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 29.2.2 t12 counting scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13 29.2.2.1 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13 29.2.2.2 edge-aligned / center-aligned mode . . . . . . . . . . . . . . . . . . . . . 29-14 29.2.2.3 single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-16 29.2.3 t12 compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-17 29.2.3.1 compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-17 29.2.3.2 channel state bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-18 29.2.3.3 hysteresis-like control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-23 29.2.4 compare mode output path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-24 29.2.4.1 dead-time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-24 29.2.4.2 state selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-26 29.2.4.3 output modulation and level selection . . . . . . . . . . . . . . . . . . . . 29-27 29.2.5 t12 capture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-29 29.2.6 t12 shadow register transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-33 29.2.7 timer t12 operating mode selection . . . . . . . . . . . . . . . . . . . . . . . 29-34 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-41 v1.1, 2011-03 29.2.8 t12 related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-35 29.2.8.1 t12 counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-35 29.2.8.2 period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36 29.2.8.3 capture/compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-37 29.2.8.4 capture/compare shadow registers . . . . . . . . . . . . . . . . . . . . . 29-38 29.2.8.5 dead-time control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-39 29.2.9 capture/compare control registers . . . . . . . . . . . . . . . . . . . . . . . . 29-41 29.2.9.1 channel state bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-41 29.2.9.2 t12 mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-45 29.2.9.3 timer control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-46 29.3 operating timer t13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-55 29.3.1 t13 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-55 29.3.2 t13 counting scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-58 29.3.2.1 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-58 29.3.2.2 t13 counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-59 29.3.2.3 single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-60 29.3.2.4 synchronization to t12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-61 29.3.3 t13 compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-63 29.3.4 compare mode output path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-65 29.3.5 t13 shadow register transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-66 29.3.6 t13 related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-68 29.3.6.1 t13 counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-68 29.3.6.2 period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-69 29.3.6.3 compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-70 29.3.6.4 compare shadow register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-71 29.4 synchronous start feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-72 29.5 trap handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-73 29.6 multi-channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-75 29.7 hall sensor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-77 29.7.1 hall pattern evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-78 29.7.2 hall pattern compare logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-80 29.7.3 hall mode flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-81 29.7.4 hall mode for brushless dc-motor control . . . . . . . . . . . . . . . . . . . 29-83 29.8 modulation control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-85 29.8.1 modulation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-85 29.8.2 trap control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-87 29.8.3 passive state level register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-90 29.8.4 multi-channel mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-91 29.9 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-98 29.9.1 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-98 29.9.2 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-100 29.9.2.1 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-100 29.9.2.2 interrupt status set register . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-103 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-42 v1.1, 2011-03 29.9.2.3 status reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-105 29.9.2.4 interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-107 29.9.2.5 interrupt node pointer r egister . . . . . . . . . . . . . . . . . . . . . . . . . 29-109 29.9.3 service request control registers . . . . . . . . . . . . . . . . . . . . . . . . 29-112 29.10 general module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-113 29.10.1 mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-113 29.10.2 input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-116 29.10.3 input monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-117 29.10.4 general registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-118 29.10.4.1 id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-118 29.10.4.2 port input select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-119 29.10.4.3 kernel state configuration register . . . . . . . . . . . . . . . . . . . . . 29-124 29.10.4.4 kernel state sensitivity control register . . . . . . . . . . . . . . . . . . 29-127 29.10.4.5 module configuration register . . . . . . . . . . . . . . . . . . . . . . . . . 29-128 29.10.4.6 input monitoring register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-130 29.10.4.7 lost indicator register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-133 29.11 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-135 29.11.1 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-135 29.11.1.1 module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-136 29.11.2 module output select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-140 29.11.3 synchronous start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-141 29.12 digital connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-142 29.12.1 connections of ccu60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-142 29.12.2 connections of ccu61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-146 29.12.3 connections of ccu62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-150 29.12.4 connections of ccu63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-154 30 the general purpose timer 12 (gpt12) . . . . . . . . . . . . . . . . . . . . . . 30-1 30.1 timer block gpt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.1.1 gpt1 core timer t3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.1.2 gpt1 core timer t3 operating modes . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.1.3 gpt1 auxiliary timers t2/t4 control . . . . . . . . . . . . . . . . . . . . . . . 30-15 30.1.4 gpt1 auxiliary timers t2/t4 operating modes . . . . . . . . . . . . . . . 30-21 30.1.5 gpt1 clock signal control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-31 30.1.6 gpt1 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-34 30.1.7 interrupt control fo r gpt1 timers . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35 30.2 timer block gpt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37 30.2.1 gpt2 core timer t6 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39 30.2.2 gpt2 core timer t6 operating modes . . . . . . . . . . . . . . . . . . . . . . 30-42 30.2.3 gpt2 auxiliary timer t5 control . . . . . . . . . . . . . . . . . . . . . . . . . . 30-46 30.2.4 gpt2 auxiliary timer t5 operating modes . . . . . . . . . . . . . . . . . . . 30-50 30.2.5 gpt2 register caprel operating modes . . . . . . . . . . . . . . . . . . . 30-55 30.2.6 gpt2 clock signal control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-61 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-43 v1.1, 2011-03 30.2.7 gpt2 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-64 30.2.8 interrupt control for gpt2 timers and caprel . . . . . . . . . . . . . . . 30-66 30.3 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-68 30.4 gpt12 kernel register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-72 30.5 implementation of the gpt12 modules . . . . . . . . . . . . . . . . . . . . . . . . 30-74 30.5.1 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-74 30.5.2 module connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-74 31 analog to digi tal converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.1.1 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.1.2 feature set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.1.3 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.1.4 adc kernel overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.1.5 conversion request unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.1.6 conversion result unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.1.7 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-10 31.1.8 electrical models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11 31.1.8.1 input signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11 31.1.8.2 reference path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12 31.1.9 transfer characteristics and error definiti ons . . . . . . . . . . . . . . . . . 31-14 31.2 operating the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15 31.2.1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.2.2 mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-21 31.2.3 module activation and power saving modes . . . . . . . . . . . . . . . . . 31-23 31.2.4 clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-24 31.2.5 adc module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-25 31.2.5.1 clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-25 31.2.5.2 kernel state configuration register . . . . . . . . . . . . . . . . . . . . . . 31-26 31.2.5.3 service request control registers . . . . . . . . . . . . . . . . . . . . . . . 31-28 31.2.6 general adc kernel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-29 31.2.6.1 request source input registers . . . . . . . . . . . . . . . . . . . . . . . . . 31-29 31.2.6.2 module identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-32 31.2.6.3 interrupt activation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-33 31.2.6.4 global control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-34 31.2.6.5 global configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-37 31.2.6.6 global status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-39 31.2.7 request source arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-42 31.2.7.1 request source priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-43 31.2.7.2 conversion start modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-44 31.2.8 arbiter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-47 31.2.8.1 arbitration slot enable register . . . . . . . . . . . . . . . . . . . . . . . . . . 31-47 31.2.8.2 request source priority register . . . . . . . . . . . . . . . . . . . . . . . . 31-48 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-44 v1.1, 2011-03 31.2.9 scan request source handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-50 31.2.9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-50 31.2.9.2 scan sequence operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.2.9.3 request source event and interrupt . . . . . . . . . . . . . . . . . . . . . . 31-52 31.2.10 scan request source registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-54 31.2.10.1 conversion request control registers . . . . . . . . . . . . . . . . . . . . 31-54 31.2.10.2 conversion request pending registers . . . . . . . . . . . . . . . . . . . 31-56 31.2.10.3 conversion request mode registers . . . . . . . . . . . . . . . . . . . . . 31-57 31.2.11 sequential request source handling . . . . . . . . . . . . . . . . . . . . . . . 31-60 31.2.11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-61 31.2.11.2 sequential source operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-62 31.2.11.3 request source event and interrupt . . . . . . . . . . . . . . . . . . . . . . 31-63 31.2.12 sequential source registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-65 31.2.12.1 queue mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-65 31.2.12.2 queue status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-68 31.2.12.3 queue 0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-70 31.2.12.4 queue backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-72 31.2.12.5 queue input registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-74 31.2.13 channel-related functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-76 31.2.13.1 input classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-76 31.2.13.2 reference selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-77 31.2.13.3 alias feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-77 31.2.13.4 limit checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-78 31.2.13.5 channel event interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-80 31.2.14 channel-related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-81 31.2.14.1 channel control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-81 31.2.14.2 input class registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-83 31.2.14.3 alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-84 31.2.14.4 limit check boundary registers . . . . . . . . . . . . . . . . . . . . . . . . . 31-85 31.2.14.5 channel flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-86 31.2.14.6 channel flag clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-87 31.2.14.7 channel event node pointer registers . . . . . . . . . . . . . . . . . . . . 31-88 31.2.15 conversion result handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-90 31.2.15.1 storage of conversion results . . . . . . . . . . . . . . . . . . . . . . . . . . 31-90 31.2.15.2 wait-for-read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-92 31.2.15.3 result event interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-93 31.2.15.4 result fifo buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-94 31.2.15.5 data reduction filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-96 31.2.15.6 result data filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-98 31.2.16 conversion result-related registers . . . . . . . . . . . . . . . . . . . . . . 31-100 31.2.16.1 result register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-100 31.2.16.2 result registers 1 to 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-102 31.2.16.3 valid flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-104 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-45 v1.1, 2011-03 31.2.16.4 result control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-105 31.2.16.5 event flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-107 31.2.16.6 event flag clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-109 31.2.16.7 event node pointer regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . 31-110 31.2.17 multiplexer test support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-113 31.2.18 external multiplexer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-114 31.2.19 synchronized conversions for parallel sampling . . . . . . . . . . . . . 31-117 31.2.20 equidistant sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-120 31.2.21 access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-122 31.2.22 broken wire detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-123 31.2.23 additional feature registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-125 31.2.23.1 access protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-125 31.2.23.2 external multiplexer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-126 31.2.23.3 synchronization control register . . . . . . . . . . . . . . . . . . . . . . . 31-130 31.2.23.4 broken wire detection enable register . . . . . . . . . . . . . . . . . . 31-132 31.2.23.5 broken wire detection configuration register . . . . . . . . . . . . . 31-133 31.3 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-134 31.3.1 request sources in TC1798 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-134 31.3.2 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-134 31.3.3 result data filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-135 31.3.4 adc module connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-136 31.3.4.1 adc0 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-137 31.3.4.2 adc1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-143 31.3.4.3 adc2 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-149 31.3.4.4 adc3 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-155 31.3.4.5 service request connections . . . . . . . . . . . . . . . . . . . . . . . . . . 31-161 31.3.4.6 kernel synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-162 32 fast analog to di gital converter (fadc) . . . . . . . . . . . . . . . . . . . . . 32-1 32.1 fadc short description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.2 fadc kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5 32.2.1 analog input stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5 32.2.2 result representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7 32.2.3 conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7 32.2.4 channel triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8 32.2.5 channel timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11 32.2.6 conversion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 32.2.6.1 static channel priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 32.2.6.2 dynamic priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 32.2.6.3 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-13 32.2.6.4 suspend mode behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-13 32.2.6.5 alias feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-14 32.2.7 data reduction unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 table of contents users manual l-46 v1.1, 2011-03 32.2.7.1 filter block structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-16 32.2.7.2 filter block operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-16 32.2.7.3 filter concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-17 32.2.7.4 width of result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19 32.2.8 neighbor channel trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-20 32.2.9 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-21 32.2.9.1 offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-22 32.2.10 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-23 32.3 fadc register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-26 32.3.1 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-30 32.3.1.1 clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-30 32.3.1.2 fractional divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-31 32.3.1.3 module identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-33 32.3.1.4 service request control registers . . . . . . . . . . . . . . . . . . . . . . . 32-34 32.3.2 global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-35 32.3.2.1 conversion request status register . . . . . . . . . . . . . . . . . . . . . . 32-35 32.3.2.2 flag modification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-37 32.3.2.3 neighbor channel trigger register . . . . . . . . . . . . . . . . . . . . . . . 32-39 32.3.2.4 global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-42 32.3.2.5 alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-46 32.3.3 channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-48 32.3.3.1 channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 32-48 32.3.3.2 analog control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-52 32.3.3.3 conversion result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-54 32.3.4 filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-55 32.3.4.1 filter control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-55 32.3.4.2 current result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-58 32.3.4.3 intermediate result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-60 32.3.4.4 final result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-62 32.4 implementation of fadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-64 32.4.1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-64 32.4.2 fadc connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-65 32.4.3 service request connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-66 32.4.4 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-67 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-1 v1.1, 2011-03 introduction, v1.3 1 introduction this users manual describes the infineon TC1798, a 32-bit microcontroller dsp, based on the infineon tricore architecture. 1.1 about this document this document is designed to be read pr imarily by design engineers and software engineers who need a detailed description of the interactions of the TC1798 functional units, registers, instru ctions, and exceptions. this TC1798 users manual describes the f eatures of the TC1798 with respect to the tricore architecture. where the TC1798 di rectly implements tricore architectural functions, this manual simply re fers to those functions as features of the TC1798. in all cases where this manual describes a tc 1798 feature without re ferring to the tricore architecture, this means that the TC1798 is a direct implement ation of the tricore architecture. where the TC1798 implements a subset of tricore architec tural features, this manual describes the TC1798 implementation, and then describes how it differs from the tricore architecture. such differences between the TC1798 and the tricore architecture are documented in the section covering each such subject. 1.1.1 related documentations a complete description of the tricore archit ecture is found in the document entitled ?tricore architecture manual?. the architec ture of the TC1798 is described separately this way because of the configurable nature of the tricore specification: different versions of the architecture may contain a different mi x of systems components. the tricore architecture, however, remains consta nt across all derivative designs in order to preserve compatibility. this users manuals together with the ?tr icore architecture manual? are required to understand the complete TC1798 mi cro controller functionality. 1.1.2 text conventions this document uses the following text conventions for named components of the TC1798: ? functional units of the TC1798 are give n in plain upper case. for example: ?the ssc supports full-duplex and half- duplex synchronous communication?. ? pins using negative logic are indicated by an overline. for example: ?the external reset pin, esr0 , has a dual function.?. ? bit fields and bits in register s are in general referenced as ?module_register name.bit field? or ?module_register name.bit?. for example: ?the current cpu priority number bit field cp u_icr.ccpn is cleared?. most of the www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-2 v1.1, 2011-03 introduction, v1.3 register names contain a module name prefix , separated by an underscore character ?_? from the actual register name (for ex ample, ?asc0_con?, where ?asc0? is the module name prefix, and ?con? is the kernel register name). in chapters describing the kernels of the peripheral modules, the registers are mainly referenced with their kernel register names. the peripheral modu le implementation sections mainly refer to the actual register names with module prefixes. ? variables used to describe sets of proc essing units or registers appear in mixed upper and lower cases. for example, regi ster name ?msgcfgn? refers to multiple ?msgcfg? registers with variable n. the bounds of the variables are always given where the register expression is first used (for example, ?n = 0-31?), and are repeated as needed in the rest of the text. ? the default radix is decimal. hexadecima l constants are suffix ed with a subscript letter ?h?, as in 100 h . binary constants are suffixed with a subscript letter ?b?, as in: 111 b . ? when the extent of register fields, groups register bits, or groups of pins are collectively named in the body of th e document, they are represented as ?name[a:b]?, which defines a range for the named group from b to a. individual bits, signals, or pins are given as ?name[c]? wh ere the range of the variable c is given in the text. for example: cfg[2:0] and srpn[0]. ? units are abbreviated as follows: ? mhz = megahertz ? s = microseconds ? kbaud, kbit = 1000 characters/bits per second ? mbaud, mbit = 1,000,000 characters/bits per second ? kbyte, kb = 1024 bytes of memory ? mbyte, mb = 1048576 bytes of memory in general, the k prefix scales a unit by 1000 whereas the k prefix scales a unit by 1024. hence, the kbyte unit scales the ex pression preceding it by 1024. the kbaud unit scales the expression preceding it by 1000. the m prefix scales by 1,000,000 or 1048576, and scales by .000001. for example, 1 kbyte is 1024 bytes, 1 mbyte is 1024 1024 bytes, 1 kbaud/kbit are 1000 characters/bits per second, 1 mbaud/mbit are 1000000 characters/bits per second, and 1 mhz is 1,000,000 hz. ? data format quantities are defined as follows: ? byte = 8-bit quantity ? half-word = 16-bit quantity ? word = 32-bit quantity ? double-word = 64-bit quantity www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-3 v1.1, 2011-03 introduction, v1.3 1.1.3 reserved, undefined, and unimplemented terminology in tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. furthermore, types of bits and bit fields are defined using the abbreviations as shown in table 1-1 . 1.1.4 register access modes read and write access to registers and memo ry locations are sometimes restricted. in memory and register access tables, the terms as defined in table 1-2 are used. table 1-1 bit function terminology function of bits description unimplemented, reserved register bit fields named 0 indicate unimplemented functions with the following behavior. ? reading these bit fields returns 0. ? these bit fields should be written with 0 if the bit field is defined as r or rh. ? these bit fields have to be written with 0 if the bit field is defined as rw. these bit fields are reserved. the detailed description of these bit fields can be found in the register descriptions. rw the bit or bit field can be read and written. rwh as rw, but bit or bit field can be also set or reset by hardware. r the bit or bit field can only be read (read-only). w the bit or bit field can only be written (write-only). a read to this register will always give a default value back. rh this bit or bit field can be modified by hardware (read-hardware, typical example: status flags). a r ead of this bit or bit field give the actual status of this bit or bit field back. writing to this bit or bit field has no effect to the setting of this bit or bit field. s bits with this attribute are ?sticky? in one direction. if their reset value is once overwritten by software, they can be switched again into their reset state only by a reset operation. software cannot switch this type of bit in to its reset state by writing the register. this attribute can be combined to ?rws? or ?rwhs?. f bits with this attribute are readable only when they are accessed by an instruction fetch. normal data read operations will return other values. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-4 v1.1, 2011-03 introduction, v1.3 1.1.5 abbreviations and acronyms the following acronyms and terms are used in this document: table 1-2 access terms symbol description u access mode: access permitted in user mode 0 or 1. reset value: value or bit is not changed by a reset operation. sv access permitted in supervisor mode. r read-only register. 32 only 32-bit word accesses are permi tted to this register/address range. e endinit-protected register/address. pw password-protected register/address. nc no change, indicated register is not changed. be indicates that an access to this address range generates a bus error. nbe indicates that no bus error is generated when accessing this address range, even though it is either an access to an undefined address or the access does not follow the given rules. ne indicates that no error is generat ed when accessing this address or address range, even though the acce ss is to an undefined address or address range. true for cpu accesses (mtcr/mfcr) to undefined addresses in the csfr range. adc analog-to-digital converter agpr address general purpose register alu arithmetic and logic unit asc asynchronous/synchronous serial controller bcu bus control unit bmu bus monitor unit brom boot rom & test rom can controller area network cmem pcp code memory cisc complex instruction set computing cps cpu slave interface www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-5 v1.1, 2011-03 introduction, v1.3 cpu central processing unit crc cyclic redundancy code csa context save area csfr core special function register ccu6 capture compare unit 6 dap device access port das device access server dcache data cache dflash data flash memory dgpr data general purpose register dma direct memory access dmi data memory interface dspr data scratch pad ram ebu external bus interface ecc error correction code emi electro-magnetic interference fadc fast analog-to-digital converter fam flash array module fce flexible crc engine fcs flash command state machine fim flash interface and control module fm-pll pll with frequency modulation support fpi flexible peripheral interconnect (bus) fpu floating point unit gpio general purpose input/output gpr general purpose register gpt12 general purpose timer 12 gpta general purpose timer array icache instruction cache i/o input / output jtag joint test action group = ieee1149.1 ltc local timer cell www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-6 v1.1, 2011-03 introduction, v1.3 mchk memory checker module mli micro link interface mmu memory management unit msb most significant bit msc micro second channel nc not connected nmi non-maskable interrupt ocds on-chip debug support ovram overlay memory pcp peripheral control processor pll phase locked loop pflash program flash memory pmi program memory interface pmu program memory unit pram pcp parameter ram pspr program scratch pad ram ram random access memory risc reduced instruction set computing sbcu system peripheral bus control unit scu system control unit sent single edge nibble transmission she secure hardware extension sfr special function register spb system peripheral bus sri shared resource interconnect sram static data memory srn service request node ssc synchronous serial controller sscg synchronous serial controller guardian stm system timer www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-7 v1.1, 2011-03 introduction, v1.3 wdt watchdog timer xbar, xbar_sri cross bar interconnect, based on the shared resource interconnect protocol www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-8 v1.1, 2011-03 introduction, v1.3 1.2 system architecture of the TC1798 the TC1798 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: ? reduced instruction set computing (risc) processor architecture ? digital signal processing (dsp) operations and addressing modes ? on-chip memories and peripherals dsp operations and addressing modes prov ide the computational power necessary to efficiently analyze complex real-world signals. the risc load/store architecture provides high computational bandwidth with low system cost. on-chip memory and peripherals are designed to support even th e most demanding high-bandwidth real-time embedded control-systems tasks. additional high-level featur es of the TC1798 include: ? efficient memory organization: instru ction and data scratch memories, caches ? serial communication interfaces ? flexible synchronous and asynchronous modes ? peripheral control processor ? standalon e data operations and interrupt servicing ? dma and sdma controller ? dma operations and interrupt servicing ? secure hardware extension ? flexible crc engine ? bus monitor unit ? general-purpose timers ? high-performance on-chip buses ? on-chip debugging and emulation facilities ? flexible interconnections to external components ? flexible power-management the TC1798 is a high-performance microcontroller with tricore cpu, program and data memories, buses, bus arbitration, an interr upt controller, a peripheral control processor and a dma controller and several on-chip peripherals. the TC1798 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, re al-time responsiveness, computational power, data bandwidth, and power consumption are key design elements. the TC1798 offers several versatile on-chip per ipheral units such as serial controllers, timer units, and analog-to-digital converte rs. within the TC1798, all these peripheral units are connected to the tricore cpu/system via the flexible peripheral interconnect (fpi) bus and the local memory bus (sri). several i/o lines on the TC1798 ports are reserved for these peripheral units to communicate with the external world. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-9 v1.1, 2011-03 introduction, v1.3 1.2.1 TC1798 block diagram figure 1-1 shows the block diagram of the TC1798. pls. note that not all features that are shown in the block diagram are available in the other TC1798 package variants. figure 1-1 TC1798 block diagram pmi e-ray (2 channels) ebu ocds l1 debug interface /jtag tricore cpu 16 kb pram pcp2 core 32 kb cmem interrupts bridge (sfi) dmi ldram dcache pmu1 gpta0 1.3v, 3.3v ext. supply gpta1 2 mb pflash 32 kb pspr 16 kb icache 128 kb dspr 16 kb dcache fpu abbreviations: icache: instruction cache dcache data cache pspr: program scratch-pad ram dspr: data scratch-padl data ram brom: boot rom pflash: program flash dflash: data flash pram: parameter ram in pcp cmem: code ram in pcp xbar : sri cross bar (xbar_sri) : on chip bus slave interface : on chip bus master interface dma 16 channels (memcheck ) cross bar interconnect (sri) 2 mb pflash 192 kb dflash 16 kb brom keyflash pmu0 ltca2 mli 128 kb sram xbar multican (4 nodes, 128 mo) sent (8 channels ) interrupt system stm scu ports external request unit ccu6 (2xccu 6) fadc 3 . 3 v e x t . f a d c s u p p l y 64 (3.3v max) (5 v m a x) 8 5 v ( 3 . 3 v s u p p o r t e d a s w e l l ) e x t . a d c s u p p l y adc3 adc2 adc1 adc0 bmu asc 2 2 2 ssc 4 sscg ssc guardian 4 she gpt120 2 msc (lvds) 2 system peripheral bus (spb) sbcu fm-pll pll e-ray fce sdma 8 channels s m/s m/s m m/s m/s m/s s s s m/s s m lmu www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-10 v1.1, 2011-03 introduction, v1.3 1.2.2 cpu cores of the TC1798 the TC1798 includes a high performance cpu and a peripheral control processor. 1.2.2.1 high-performance 32-bit cpu this chapter gives an overview of the tricore 1.6 architecture. tricore (tc1.6) arch itectural highlights ? unified risc mcu/dsp ? 32-bit architecture with 4 gbytes unifie d data, program, and i/o address space ? 32 general purpose registers with fast automatic co ntext-switching ? multiply-accumulate unit able to sustain 2 mac operations per cycle. ? fully pipelined floating point unit ? saturating inte ger arithmetic ? bit handling ? packed data operations ? zero overhead loop ? dedicated integer divide unit. ? precise exceptions ? flexible power management ? flexible memory protection system high-efficiency tricore instruction set ? powerful instruction set ? freely mixable 16-bit and 32-bit instructions for reduced code size ? data types include: boolean, array of bi ts, character, signed and unsigned integer, integer with saturation, signed fraction, double-word integers, and ieee-754 single- precision floating point ? data formats include: bit, 8-bit byte, 16-b it half-word, 32-bit word, and 64-bit double- word ? flexible and efficient addressing mode for high performance and code density integrated cpu rela ted on-chip memories ? instruction memory: ? 32 kbyte instruction scratch-pad ram (pspr) ? 16 kbyte instruction cache (icache) ? data memory: ? 128 kbyte data scratch-pad ram (dspr) ? 16 kbyte data cache (dache) ? all memories are ecc protected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-11 v1.1, 2011-03 introduction, v1.3 1.2.2.2 high-performance 32-bit peripheral control processor the pcp is a flexible peripheral control processor optimized for interrupt handling and thus unloading the cpu. features ? data move between any two memory or i/o locations ? data move with predefined limit supported ? read-modify-write capabilities ? full computation capabilities including basic mul/div ? read/move data and accumulate it to previously read data ? read two data values and perform arithm etic or logical operation and store result ? bit-handling capabilities (testing, setting, clearing) ? flow control instructions (conditi onal/unconditional jumps, breakpoint) ? programmable write protection for code memory and parameter memory ? programmable limit of fpi addresse s than can be written by the pcp ? dedicated interrupt system ? pcp srams with ecc protection ? high integrity operation support integrated pcp related on-chip memories ? 32 kbyte code memory (cmem) ? 16 kbyte parameter memory (pram) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-12 v1.1, 2011-03 introduction, v1.3 1.3 on-chip system units the TC1798 microcontroller offers severa l versatile on-chip system peripheral units such as dma controller modules (dma , sdma), embedded flash modules (pmu0, pmu1), flexible crc engine (fce), system timer unit (stm), system control unit (scu), overlay control unit (ovc), local me mory unit (lmu), bu s monitor unit (bmu), interrupt system and ports modules. 1.3.1 flexible interrupt system the TC1798 includes a programmable interr upt system with the following features: 1.3.1.1 feature list the interrupt system provides the following features: ? fast interrupt response ? hardware arbitration ? independent interrupt systems for cpu and pcp ? programmable service request nodes (srns) ? each srn can be mapped to the cpu or pcp interrupt system ? flexible interrupt-prioritizing scheme with 2 55 interrupt priority levels per interrupt system 1.3.2 direct memory access controller (dma) the TC1798 includes a fast and flexible dma controller with 16 independant dma channels. 1.3.2.1 feature list the dma controller provides the following features: ? 16 independent dma channels ? 2 dma sub-blocks with (8 dma channels per dma sub-block) ? dma sub-blocks with support of parallel channel execution (1 channel per sub- block, both sub-blocks in parallel) ? up to 16 selectable request inputs per dma channel ? 2-level programmable priority of dma channels within the dma sub-block ? software and hardware dma request ? hardware requests by selected on-ch ip peripherals and external inputs ? 3-level programmable priority of the dma sub-blocks at the on chip bus interfaces ? buffer capability for move actions on the buses (at least 1 move per bus is buffered) ? individually programmable operation modes for each dma channel ? single mode: stops and disables dma c hannel after a predefined number of dma transfers www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-13 v1.1, 2011-03 introduction, v1.3 ? continuous mode: dma channel remains enabled after a predefined number of dma transfers; dma transaction can be repeated ? programmable address modification ? two shadow register modes (with / w/o automatic re-set and direct write access). ? full 32-bit addressing capability of each dma channel ? 4 gbyte address range ? data block move supports > 32 kbyte moves per dma transaction ? circular buffer addressing mode with flexible circular buffer sizes ? programmable data width of dma transfer/ transaction: 8-bit, 16-bit, or 32-bit ? register set for each dma channel ? source and destination address register ? channel control and status register ? transfer count register ? flexible interrupt generation (the servic e request node logic for the mli channels is also implemented in the dma modules) ? dma module is working on spb frequency, sri interface on cpu frequency. ? dependant on the target/destination addre ss, read/write requests from the move engines are directed to the spb, lm b, mlis or to the the cerberus. 1.3.3 safe direct memory access controller the TC1798 includes a fast and flexible safe dma controller with 8 independant dma channels. additionally to the normal dma ch annels, the safe dma channels extended with crc features for the read data, source and destination address. 1.3.3.1 feature list the sdma provides the following features: ? 8 independent dma channels ? 8 dma channels in the dma sub-block ? up to 16 selectable request inputs per dma channel ? 2-level programmable priority of dma channels within the dma sub-block ? software and hardware dma request ? hardware requests by selected on-ch ip peripherals and external inputs ? ? upper and lower address boundary checking of the source and destination address. ? 3-level programmable priority of the dma sub-block at the on chip bus interfaces ? buffer capability for move actions on the buses (at least 1 move per bus is buffered) ? individually programmable operation modes for each dma channel ? single mode: stops and disables dma c hannel after a predefined number of dma transfers ? continuous mode: dma channel remains enabled after a predefined number of dma transfers; dma transaction can be repeated www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-14 v1.1, 2011-03 introduction, v1.3 ? programmable address modification ? two shadow register modes (with / w/o automatic re-set and direct write access). ? full 32-bit addressing capability of each dma channel ? 4 gbyte address range ? data block move supports > 32 kbyte moves per dma transaction ? circular buffer addressing mode with flexible circular buffer sizes ? programmable data width of dma transfer/ transaction: 8-bit, 16-bit, or 32-bit ? register set for each dma channel ? source and destination address register ? channel control and status register ? transfer count register ? generation of unique cr c checksums for source and destination addresses. ? generation of in-line crc checksum for read data. ? flexible interrupt generation ? dma module is working on spb frequency. 1.3.4 flexible crc engine (fce) the flexible crc engine (fce) module pr ovides a parallel im plementation of one or more cyclic redundancy code (crc) algorithms. the standard crc polynomial implemented in the fce module is the ieee 802.3 ethernet crc32. the fce is meant to be used as an hardware acceleration engine for software applications or operating systems services (compatible with autosar crc ?s pecification of cr c routines?) using crc signatures. 1.3.4.1 feature list the fce provides the following features: ? two crc polynomials: ? ieee 802.3 crc32 ethernet polynomial: 0x82608edb (crc kernel 0) ? crc32c castagnoli: 0xd419cc15 (crc kernel 1) ? parallel crc implementation (32-bits wide) ? data blocks to be computed by fc e shall be a multip le of 32-bits ? start address of data blocks to be comp uted by fce shall be at least 32-bits aligned ? register interface compliant with autosar specification for crc routines. enables to support reentrant software routines via a software-based save/restore mechanism. ? extended register interface to control reliability of fce execution. ? redundant implementation of critical cont rol registers ? error notification scheme via dedicated interrupt node ? support of hardware configuration: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-15 v1.1, 2011-03 introduction, v1.3 ? each crc kernel supports as generic parameter the degree of the polynomial (poly_degree) directly controlling the wid th of the fce data path. only 32, 16 and 8 are allowed. ? fce is designed as a multi - crc kernel structure supporting co ncurrent operation of each crc - kernel. 1.3.5 system timer (stm) the TC1798?s stm is designed for global system ti ming applications requiring both high precision and long range. 1.3.5.1 feature list the system timer provides the following features: ? free-running 56-bit counter ? all 56 bits can be read synchronously ? different 32-bit portions of the 56- bit counter can be read synchronously ? flexible interrupt generation based on compare match with partial stm content ? counting starts automatically after a reset operation ? stm registers are reset by an application re set if bit arstdis.stmdis is cleared. if bit arstdis.stmdis is set, t he stm registers are not reset. 1) ? stm can be halted in debug/suspend mode special stm register semantics provide syn chronous views of the entire 56-bit counter, or 32-bit subsets at different levels of resolution. the maximum clock period is 2 56 f stm . at f stm = 90 mhz, for example, the stm counts 25.39 years before overflowing. thus, it is capable of continuously timing the entire expected product life time of a system without overflowing. the stm can be optionally disabled for power-saving purposes, or suspended for debugging purposes via its clock control register. in suspend mode of the TC1798 (initiated by writing an appropriate value to stm_clc register), the stm clock is stopped but all registers are still readable. due to the 56-bit width of the stm, it is not possible to r ead its entire content with one instruction. it needs to be read with two lo ad instructions. since the timer would continue to count between the two load operations, ther e is a chance that the two values read are not consistent (due to possible overflow from the low part of the timer to the high part between the two read operations). to enabl e a synchronous and consistent reading of the stm content, a capture re gister (stm_cap) is implemented. it latches the content of the high part of the stm each time when one of the registers stm_tim0 to stm_tim5 is read. thus, stm_cap holds the upper value of the timer at exactly the same time 1) ?stm registers? means all registers except stm_clc, stm_src0, and stm_src1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-16 v1.1, 2011-03 introduction, v1.3 when the lower part is read. the second read operation would t hen read the content of the stm_cap to get the complete timer value. the content of the 56 -bit system timer can be compar ed against the content of two compare values stored in the stm_cmp0 a nd stm_cmp1 registers. interrupts can be generated on a compare match of the stm with the stm_cmp0 or stm_cmp1 registers. figure 1-2 provides an overview on the stm module. it shows the options for reading parts of stm content. figure 1-2 general block diagram of the stm module registers stm module 00 h stm_cap stm_tim6 stm_tim5 00 h 56-bit system timer address decoder clock control mcb06185_mod compare register 0 interrupt control compare register 1 porst stm_tim4 stm_tim3 stm_tim2 stm_tim1 stm_tim0 stm_cmp1 stm_cmp0 enable / disable f stm stm ir0 31 23 15 7 0 31 23 15 7 0 55 47 39 31 23 15 7 0 stm ir1 to dma etc. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-17 v1.1, 2011-03 introduction, v1.3 1.3.6 system control unit (scu) the following scu introduction gives an ov erview about the tc 1798 system control unit (scu). the system control unit (scu) of the tc 1798 handles all system control tasks beside the debug related tasks which are co ntrolled by the ocds/cerberus. the scu contains the follo wing functional sub-blocks: ? clock control ? reset operation ? external interface ? power management ? software boot support ? sram ecc control ? die temperature measurement ? watchdog timer ? emergency stop control ? nmi trap generation 1.3.6.1 clock generation unit (cgu) the clock generation unit (cgu) allows a very flexible clock generation for the TC1798. during user program execution the frequency can be programmed for an optimal ratio between performance and power consumption. 1.3.6.2 features of the watchdog timer (wdt) the main features of the wdt are summarized here. ? 16-bit watchdog counter ? selectable input frequency: f fpi /256 or f fpi /16384 ? 16-bit user-definable reload value for normal watchdog operation, fixed reload value for time-out and prewarning modes ? incorporation of the e ndinit bit and monitori ng of its modifications ? sophisticated password acce ss mechanism with fixed and user-definable password fields ? access error detection: inva lid password (during first access) or invalid guard bits (during second access) trigger the watchdog reset generation ? overflow error detection: an overflow of the counter triggers the watchdog reset generation ? watchdog function can be disabled; acce ss protection and endinit monitor function remain enabled ? double reset detection: if a watchdog i nduced reset occurs t wice, a severe system malfunction is assumed and the TC1798 is held in reset until a system / class 0 reset occurs. this prevents the device from being periodically reset if, for instance, www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-18 v1.1, 2011-03 introduction, v1.3 connection to the external memory has been lost such that even system initialization could not be performed 1.3.6.3 reset operation the following reset request triggers are available: ? 1 external power-on hardware reset request trigger; porst , (cold reset) ? 2 external system request reset triggers; esr0 and esr1 (cold/warm reset) ? watchdog timer (wdt) reset request trigger, (warm reset) ? software reset (sw), (warm reset) ? debug (ocds) reset request trigger, (warm reset) ? jtag reset (special reset) ? resets via the jtag interface note: the jtag and ocds resets ar e described in the ocds chapter. there are two basic types of reset request triggers: ? trigger sources that do not depend on a clock, such as the porst . this trigger force the device into an asynchronous reset assertion independently of any clock. the activation of an asynchronous reset is a synchronous to the system clock, whereas its de-assertion is synchronized. ? trigger sources that need a clock in order to be asserted, such as the input signals esr0 , esr1 , and esr2 , the wdt trigger, the parity trigger, or the sw trigger. 1.3.6.4 external interface (esr, eru) the scu provides inte rface pads for system purpose. various functions are covered by these pins. due to the different tasks some of the pads can not be shared with other functions but most of them can be shared with other functions. the following functions are covered by the scu controlled pads: ? reset request triggers ? reset indication ? trap request triggers ? interrupt request triggers ? non scu module triggers the first three points are covered by the esr pads and the last two points by the eru pads. 1.3.6.5 die temperature measurement (dts) the die temperature sensor (dts) generates a measurement result that indicates directly the current temperatur e. the result of the measurement can be read via an dts register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-19 v1.1, 2011-03 introduction, v1.3 1.3.7 general purpose i/o ports and peripheral i/o lines (ports) the TC1798 has port connections to interface with its peripherals and external devices. as an input port line, the digital signal from other parts of a circuit can be read. alternatively, the port can act as output to control or signal to other peripherals or devices. the TC1798 has a port structure where each port line has a number of control and data bits, enabling flexible usage of the line. if a peripheral unit uses a gpio port line as a bi- directional i/o line, each port pin can be configured for input or output operation. in input mode, it is possible to activate the internal weak pull-up, pull-down, or no input pull device. input signals are connected direct ly to the various inputs of the peripheral units. push-pull or open drain out put modes are available for selection. in addition, the pad output driver strength can be programm ed individually for each port line. the pads are also capable to be configured for different pad levels. when the port is in output mode, the digita l level of the pin can be read by software through the input path or a peripheral can use the pin level as an input.the output multiplexer selects the signal source for th e gpio line when used as output. if the pin is used as general-purpose output, the multiplexe r is switched to the output data register pn_out. the logic state of a port line can be set, cleared or toggled bit-wise. when selected as general-purpose output line, the actual logic level at the pin can be examined and compared against the applied out put level. this can be used to detect some electrical failures at the pin caused through external circuitry. 1.3.7.1 feature list the port modules provide the following features: ? digital general-purpose in put/output (gpio) port lines ? input/output functionality individual ly programmable for each port line ? programmable input characteristi cs (pull-up, pull-down, no pull device) ? pad output driver strength can be programmed individually for each port port line to minimize emi (weak, medium, strong) ? programmable output characteri stics (push-pull, open drain) ? programmable alternate output functions ? output lines of each port can be updat ed port-wise or set/reset/toggled bit-wise www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-20 v1.1, 2011-03 introduction, v1.3 1.3.8 program memory unit (pmu) the program memory unit ?pmu? is part of the processor subsystem. the pmus control the flash memory and the boot rom. the devices of the audo-max have at least one program memory unit. this is named ?pmu0?. with increasing flash memory more pmus are added which are named ?pmu1?, and so on. the TC1798 includes 2 pmus (pmu0, pmu1). the exact configuration of each pmu is described in the pmu chapter in this docum ent. derived devices with a reduced set of memories may exist. their configurat ion is contained in the data sheet. figure 1-3 pmu basic block diagram 1.3.8.1 feature list the pmu modules provides the following features: ? bootrom (?brom?), only in pmu0. ? program flash (?pflash?): ? pmu0: 2 mbyte. ? pmu1: 2 mbyte. ? data flash (?dflash?): ? pmu0: 192 kbyte. ? security flash for she (?keyflash?). ? sri slave interface for all assigned flash memories and registers. pmu crossbar interconnect (sri) bootrom flash standard interface (fsi) flash array pflash dflash she keyflash www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-21 v1.1, 2011-03 introduction, v1.3 ? flash command control. ? flash and brom access control. ? tuning protection. ? interface to se curity module she. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-22 v1.1, 2011-03 introduction, v1.3 1.3.9 secure hardware extension (she) the she module realizes the functionality defined by his as ?she? (secure hardware extension). the storage of keys is done by the pmu0. for further information please contact your infineon representative. 1.3.10 local memory unit (lmu) the local memory unit is an sri peripheral providing access to volatile memory resources. it?s primary purpose is to prov ide 128 kbytes of local memory for general purpose usage but it will also provide access to the separate block of emulation and debug memory (emem) provided in the emulation devices. 1.3.10.1 feature list an overview of the features implemented in the lmu follows: ? 128 kbytes of sram ? organised as 64 bit words ? support for burst access ? support of single data access (byte, half word, word accesses and double word) ? ecc protection ? interface to the emem of the ed device. ? olda region support. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-23 v1.1, 2011-03 introduction, v1.3 1.3.11 data access overlay (ovc) the data overlay functionality provides the capability to redirect data accesses by the tricore to program memory (internal progra m flash or external memory) to the sram in the local memory unit (lmu), or to t he emulation memory in emulation device ed, or to the external memory. this functionalit y makes it possible, for example, to modify the application?s test and calibration paramete rs (which are typically stored in the program memory) during run time of a program . note that read and write data accesses from/to program memory are redirected. 1.3.11.1 feature list the data access overlay provides the following features: ? 16 overlay ranges (?blocks?) configurable for program flash and external memory ? supports usage of lmu sram (128 kb) as internal overlay memory ? support of up to 512 kbyte overlay/calibra tion memory in emulation device (emem) ? support of up to 2 mb overlay memory in external memory (ebu space) ? support of online data acquisition into range of up to 32 kb and of its overlay ? support of different overlay memory sele ctions for every enabled overlay block ? sizes of overlay blocks selectable from 16 byte to 512 kbyte ? all configured overlay ranges can be en abled with only one register write access ? programmable flush (invalidate) control for data cache in dmi www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-24 v1.1, 2011-03 introduction, v1.3 1.4 on-chip peripheral units of the TC1798 the TC1798 microcontroller offers several versatile on-chip peripheral units such as serial controllers, timer units, and analog-to -digital converters. several i/o lines on the TC1798 ports are reserved for these peripher al units to communicate with the external world. on-chip peripheral units ? two asynchronous/synchronous serial c hannels (asc) with baud-rate generator, parity, framing and overrun error detection ? four synchronous serial channels (ssc) with programmable data length and shift direction ? four ssc guardian modules (sscg, one related to each ssc module) ? two micro second bus interfaces (msc) for serial communication ? one can module with four can nodes (multican) for high-efficiency data handling via fifo buffering and gateway data transfer ? two micro link serial bus interfaces (ml i) for serial multip rocessor communication ? two general purpose timer arrays (gpta) with a powerful set of digital signal filtering and timer functionality to acco mplish autonomous and complex input/output management. one additional local timer cell array (lcta). ? four capcom 6 unit modules (ccu6) ? two general purpose 12 timer units (gpt12) ? one sent module (sent) with support of 8 serial communication lines ? four analog-to-digital converter units (adc) with 8-bit, 10-bit, or 12-bit resolution. ? one fast analog-to-digital converter unit (fadc) ? one flexray tm module with 2 channels (e-ray). ? one external bus interface (ebu) 1.4.1 asynchronous/synchronous serial interfaces (asc) the TC1798 includes two asynchronous/synchronous serial interfaces, asc0 and asc1. both asc modules have the same functionality. figure 1-5 shows a global view of the asynchronous/synchronous serial interface (asc). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-25 v1.1, 2011-03 introduction, v1.3 figure 1-4 general block diagram of the asc interface the asc provides serial communication between the TC1798 and other microcontrollers, microprocessors, or external peripherals. the asc supports full-duplex asynchronous communication and half-duplex synchronous communication. in synchronous mode, data is transmitted or received synchronous to a shift clock that is generated by the asc internally. in asynchronous mode, 8-bit or 9-bit data transfer, parity g eneration, and the number of stop bits can be selected. parity, framing, and overrun erro r detection are provided to increase the reliability of data transfers. transmission an d reception of data is double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back option. a 13-bit baud rate generator provides the asc with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider. 1.4.1.1 feature list the asc module provides the following features: ? full-duplex asynchronous operating modes ? 8-bit or 9-bit data frames, lsb first ? parity-bit generation/checking ? one or two stop bits ? baud rate from 6.875 mbit/s to 1.64 bit/s (@ 110 mhz module clock) ? multiprocessor mode for automatic address/data byte detection ? loop-back capability mcb05762_mod clock control address decoder interrupt control f asc asc module (kernel) port control rxd txd rxd txd to dma eir tbir tir rir www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-26 v1.1, 2011-03 introduction, v1.3 ? half-duplex 8-bit synchronous operating mode ? baud rate from 13.75 mbit/s to 1119 bit/s (@ 110 mhz module clock) ? double-buffered transmitter/receiver ? interrupt generation ? on a transmit buffer empty condition ? on a transmit last bit of a frame condition ? on a receive buffer full condition ? on an error condition (fra me, parity, overrun error) ? implementation features ? connections to dma controller ? connections of receiver input to gpta (ltc) for baud rate detection and lin break signal measuring www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-27 v1.1, 2011-03 introduction, v1.3 1.4.2 high-speed synchronous serial interfaces (ssc) the TC1798 includes four high-speed synchronous serial interfaces, ssc0, ssc1, ssc2 and ssc3. all ssc modules have the same functionality. figure 1-5 shows a global view of the of the synchronous serial interface (ssc). figure 1-5 general block diagram of the ssc interface the ssc supports full-duplex and half-duplex serial synchronous communication up to 55.0 mbit/s (@ 110.0 mhz module clock, master mode). the serial clock signal can be generated by the ssc itself (master mode) or can be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compa tible devices. transmission and reception of data is double-buffered. a shift clock generat or provides the ssc with a separate serial clock signal. seven slave select inputs are available for slave mode operation. eight programmable slave select outputs (chi p selects) are supported in master mode. 1.4.2.1 feature list the ssc module provides the following features: ? master and slave mode operation ? full-duplex or half-duplex operation ? automatic pad control possible ? flexible data format mcb06058_mod clock control address decoder interrupt control f ssc ssc module (kernel) mrstb mtsr master rir tir eir slsi[7:1] slsi[7:1] slso[7:0] slso[7:0] mrst mtsr sclk mrsta mtsrb mrst mtsra sclkb sclk sclka slave slave master slave master port control f clc enable m/s select dma requests slsoando[7:0] slsoando[7:0] slsoandi[7:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-28 v1.1, 2011-03 introduction, v1.3 ? programmable number of data bits: 2 to 16 data bits (with parity: 1 to 15 data bits) ? programmable shift directio n: lsb or msb shift first ? programmable clock polarity: idle low or idle high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock ? baud rate generation ? master mode: 55.0 mbit/s to 839.3 bit/s (@ 110 mhz module clock) ? slave mode: 27.5 mbit/s to 839. 3 bit/s (@ 110 mhz module clock) ? interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, b aud rate, transmit error, parity error) ? queued ssc mode supports control and data handling by the dma controller ? flexible ssc pin configuration ? hardware supported parity mode ? individually selectable for transmit and receive frames ? even/odd parity selection ? seven slave select inputs slsi[7:1] in slave mode ? eight programmable slave select outputs slso[7:0] in master mode ? automatic slso generation with programmable timing ? programmable active level and enable control ? combinable with slso output si gnals from other ssc modules www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-29 v1.1, 2011-03 introduction, v1.3 1.4.3 synchronous serial interface guardian (sscg) figure 1-6 shows a sub-system consisting of - one ssc module ssc0 - one sscg module sscg0 this sub-system can be analyzed independently of the rest of the chip. one chip can contain one or more such subsystems. the sscg module monitors the output signals of the corresponding ssc module and in case of a mismatch between the expected and the ongoing signals, it raises an error. the TC1798 includes four high-speed synchronous serial interfaces, ssc0, ssc1, ssc2 and ssc3 and four guardians respecti vely. all sscx/sscgx subsistems provide the same functionality. figure 1-6 general block diagram of an ssc / sscg sub-system 1.4.3.1 feature list the sscg module provides the following features: ? all output signals of the ssc monitored: data, clock and slave selects. ? signals monitored after the output driver; it is included in the monitored loop ssc0 pad pad pad sscg0 open sclk mrst mtsr mrst mtsr sclk fpi_clk 1xssc_1xsscg_subsystem.vsd 0 pad slsx 8 8 sclkg slsig 8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-30 v1.1, 2011-03 introduction, v1.3 ? maximum monitored baud-rate of 4 mbaud . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-31 v1.1, 2011-03 introduction, v1.3 1.4.4 micro second channel interface (msc) the TC1798 includes two micro second channel interfaces, msc0 and msc1. both msc modules have the same functionality. the micro second channel (msc) interface provides serial communication links typically used to connect power switches or other peripheral devices. the serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel. figure 1-7 shows a global view of the interface signals of an msc interface. figure 1-7 general block diagram of the msc interface the downstream and upstream channels of the msc module communicate with the external world via nine i/o lines. eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). one out of eight input lines sdi[7:0] is used as serial data input signal for the upstream channel. the source of the serial data to be transmitted by the downstream channel can be msc register contents or data that is provided on the altinl/altinh input lines. these input lines are typically connected with other on-chip peripheral units (for example with a timer unit such as the gpta). an emergency stop input signal makes it possible to set bits of the serial data stream to dedicated values in an emergency case. clock control, address decoding, and interrupt service request control are managed outside the msc module kernel. service reques t outputs are able to trigger an interrupt or a dma request. 4 msc module (kernel) mcb06059 fcln clock control address decoder interrupt control f msc f clc downstream channel upstream channel fclp en0 en1 en2 en3 son sop sdi[7: 0] sr[3:0] emgstopmsc altinl[15:0] altinh[15:0] to dma 16 16 8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-32 v1.1, 2011-03 introduction, v1.3 1.4.4.1 feature list the micro second bus module provides the following features: ? fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses ? high-speed synchronous serial transmission on downstream channel ? serial output clock frequency: f fcl = f msc /2 ( f mscmax = 110 mhz) ? fractional clock divider for precise frequency control of serial clock f msc ? command, data, and passive frame types ? start of serial frame: software-controlled, timer-controlled, or free-running ? transmission with or without sel bit ? flexible chip select generation indicates status during serial frame transmission ? emergency stop without cpu intervention ? low-speed asynchronous serial reception on upstream channel ? baud rate: f msc divided by 4, 8, 16, 32, 64, 128, or 256 ( f mscmax = 110 mhz) ? standard asynchronous serial frames ? programmable upstream data frame length (16 or 12 bits) ? parity error checker ? 8-to-1 input multiplexer for sdi lines ? built-in spike filter on sdi lines ? selectable pin types of downstream channel interface: four lvds differential output drivers or four digital gpio pins www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-33 v1.1, 2011-03 introduction, v1.3 1.4.5 flexray? protocol controller (e-ray) the e-ray ip-module performs communication according to the flexray? 1) protocol specification v2.1. with maximum specified clock the bitrate can be programmed to values up to 10 mbit/s. additional bus driver (bd) hardware is required for connection to the physical layer. 1.4.5.1 e-ray kernel description figure 1.4.5.1 shows a global view of the e-ray interface. figure 1-8 general block diagram of the e-ray interface 1) infineon ? , infineon technologies ? , are trademarks of infineon technologies ag. flexray? is a trademark of flexray consortium. eray_overview_32.vsd address decoder ir eray module (kernel ) channel a channel b port control external request unit stop watch trigger select stpw mt external clock output f mt rxdb txdb txenb rxda txda txena clock control f c l c_er ay f sc l k f pl l_ er ay f spb port x.y 10 extclk0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-34 v1.1, 2011-03 introduction, v1.3 the e-ray module communicates with the external world via three i/o lines each channel. the rxdax and rxdbx lines are the receive data input signals, txda and txdb lines are the transmit output signals, txena and txenb the transmit enable signals. clock control, address decoding, and servic e request control are managed outside the e-ray module kernel. 1.4.5.2 overview for communication on a flexray? network, individual message buffers with up to 254 data byte are configurable. the message storage consists of a single-ported message ram that holds up to 128 message buffers. all functions concerning the handling of messages are implemented in the message handler. those functions are the acceptance filtering, the transfer of messages between the two flexray? channel protocol controllers and the message ram, maintaining the transmission schedule as well as providing message status information. the register set of the e-ray ip-module can be accessed directly by an external host via the module?s host interface. these regist ers are used to control/configure/monitor the flexray? channel protocol controllers, message handler, global time unit, system universal control, frame and symbol processing, network management, service request control, and to access the message ram via input / output buffer. 1.4.5.3 features list the e-ray ip-module provides the following features: ? conformance with flexray? protocol specification v2.1 ? data rates of up to 10 mbit/s on each channel ? up to 128 message buffers configurable ? 8 kbyte of message ram for storage of e.g. 128 message buffers with max. 48 byte data field or up to 30 message buffers with 254 byte data sections ? configuration of message buffers with different payload lengths possible ? one configurable receive fifo ? each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive fifo ? host access to message buffers via input and output buffer. input buffer: holds message to be transferred to the message ram output buffer: holds message read from the message ram ? filtering for slot counter, cycle counter, and channel ? maskable module service requests ? network management supported ? four service request lines www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-35 v1.1, 2011-03 introduction, v1.3 ? automatic delayed read access to output command request register (obcr) if a data transfer from message ram to output shadow buffer (initiated by a previous write access to the obcr) is ongoing. ? automatic delayed read access to input command request register (ibcr) if a data transfer from input shadow buffer to me ssage ram to (initiated by a previous write access to the ibcr) is ongoing. ? four input buffer for building up transmission frames in parallel. ? flag indicating which input buffer is currently accessible by the host. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-36 v1.1, 2011-03 introduction, v1.3 1.4.6 multican controller the multican module provides four independent can nodes, representing four serial communication interfaces. there is a ttca n extension available on the node 0. the number of available message objects is 128. figure 1-9 overview of the multican module the multican module contains four independe ntly operating can nodes with full-can functionality that are able to exchange data and remote frames via a gateway function. transmission and reception of can frames is handled in accordance to can specification v2.0 b (active). each can node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. all four can nodes share a common set of message objects. each message object can be individually allocated to one of the can nodes. besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the can nodes or to set up a fifo buffer. the message objects are organized in doubl e-chained linked lists, where each can node has its own list of message objects. a can node stores frames only into message objects that are allocated to the message object list of the can node, and it transmits only messages belonging to this message obj ect list. a powerful, command-driven list controller performs all message object list operations. multican module kernel mca06060_n4 can node 0 can control message ob ject buffer 128 objects can node 1 txdc0 rxdc0 txdc1 rxdc1 linked list control port control clock control address decoder interrupt control f can f clc can node 2 txdc2 rxdc2 can node 3 txdc3 rxdc3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-37 v1.1, 2011-03 introduction, v1.3 the bit timings for the can nodes are derived from the module timer clock ( f can ) and are programmable up to a data rate of 1 mbit /s. external bus transceivers are connected to a can node via a pair of receive and transmit pins. 1.4.6.1 multican feature list the mulitican module provides the following features: ? compliant with iso 11898 ? can functionality according to can specification v2.0 b active ? dedicated control registers for each can node ? data transfer rates up to 1 mbit/s ? flexible and powerful message transfer control and error handling capabilities ? advanced can bus bit timing analysis and baud rate detection for each can node via a frame counter ? full-can functionality: a set of 128 message objects can be individually ? allocated (assigned) to any can node ? configured as transmit or receive object ? setup to handle frames with 11-bit or 29-bit identifier ? identified by a timestamp via a frame counter ? configured to remote monitoring mode ? advanced acceptance filtering ? each message object provides an individual acceptance mask to filter incoming frames ? a message object can be configured to a ccept standard or extended frames or to accept both standard and extended frames ? message objects can be grouped into four priority classes for transmission and reception ? the selection of the message to be transmitted first can be based on frame identifier, ide bit and rtr bit according to can arbitration rules, or on its order in the list ? advanced message object functionality ? message objects can be combined to build fifo message buffers of arbitrary size, limited only by the total number of message objects ? message objects can be linked to form a gateway that automatically transfers frames between 2 different can buses. a single gateway can link any two can nodes. an arbitrary number of gateways can be defined ? advanced data management ? the message objects are organized in double-chained lists ? list reorganizations can be performed at an y time, even during full operation of the can nodes ? a powerful, command-driven list controller manages the organization of the list structure and ensures consistency of the list www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-38 v1.1, 2011-03 introduction, v1.3 ? message fifos are based on the list structure and can easily be scaled in size during can operation ? static allocation commands offer compatibility with multican applications that are not list-based ? advanced interrupt handling ? up to 16 interrupt output lines are available. interrupt requests can be routed individually to one of the 16 interrupt output lines ? message post-processing notifications can be combined flexibly into a dedicated register field of 256 notification bits ? module internal sram with ecc protection 1.4.6.2 ttcan feature list the multican module provides the following ttcan features ? full support of basic cycle and system matrix functionality ? support of reference messages level 1 and level 2 ? usable as time master ? arbitration windows supported in time-triggered mode ? global time information available ? can node 0 can be configured either for event-driven or time-triggered mode ? built-in scheduler mechanism and a timing synchronization unit ? write protection for scheduler timing data memory ? timing-related interrupt functionality ? parity protection for scheduler memory www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-39 v1.1, 2011-03 introduction, v1.3 1.4.7 micro link serial bus interface (mli) this TC1798 contains two micro link se rial bus interfaces, mli0 and mli1. the micro link interface (mli) is a fast sy nchronous serial interface to exchange data between microcontrollers or other devices, such as stand-alone peripheral components. figure 1-10 shows how two microcontrollers are typically connected together via their mli interfaces. figure 1-10 typical micro li nk interface connection 1.4.7.1 mli feature list the mli module provides the following features: ? synchronous serial communication between an mli transmitter and an mli receiver ? different system clock speeds supported in mli transmitter and mli receiver due to full handshake protocol (4 lines between a transmitter and a receiver) ? fully transparent read/write acce ss supported (= remote programming) ? complete address range of target device available ? specific frame protocol to transfer commands, addresses and data ? error detection by parity bit ? 32-bit, 16-bit, or 8-bit data transfers supported ? programmable baud rate: f mli /2 (max. f mli = f fpi ) ? address range protection scheme to block unauthorized accesses ? multiple receiving devices supported mca06061 controller 1 cpu peripheral b peripheral a mli system bus controller 2 cpu peripheral d peripheral c mli system bus memory memory www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-40 v1.1, 2011-03 introduction, v1.3 figure 1-11 shows a general block diagram of the mli module. the mli transmitter and mli receiver communicate with other mli receivers and mli transmitters via a four-line serial connection each. several i/o lines of these connections are available outside the mli module kernel as a four-line output or input vector with index numbering a, b, c and d. the mli module internal i/o control blocks define which signal of a vector is actually taken into ac count and also allow polarity inversions (to adapt to different physical interconnection means) figure 1-11 general block di agram of the mli modules 4 mcb06062_mod port control tready[d:a] tvalid[d:a] rclk[d:a] mli transmitter mli receiver mli module tdata tclk rready[d:a] rvalid[d:a] rdata[d:a] fract. divider i/o control i/o control move engine sr[7:0] f ml i f fpi brkout 4 4 4 4 4 tr[3:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-41 v1.1, 2011-03 introduction, v1.3 1.4.8 single edge nibble transmission (sent) this chapter describes the sent interface of the TC1798. 1.4.8.1 sent kernel description figure 1-12 shows a global view of the sent interface. figure 1-12 general block di agram of the sent interface the sent module communicates with the external world via one i/o line for each channel. the stx lines are the receive data input signals. they overlay adc inputs. if the optional spc mode is used, they can be used on a port configured with an open drain transistor. this way the optional spc data can be transmitted and the line is used bidirectionally. in case of an external transceiver, receive and transmit path can be routed to two different ports. dma sent_block_diagram.vsd address decoder interrupt control sent module (kernel ) channel 0 port control . . . timer clock control channel n sensor data spc control sensor data spc control trigger input st0 stm f sent f fpi www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-42 v1.1, 2011-03 introduction, v1.3 1.4.9 sent feature overview the sent interface provides a serial communication link typically used to connect sensors or other peripheral devices. clock control, address decoding, and serv ice request control are managed by the sent module kernel. the sent ip-module performs communication according to the sent specification j2716 feb2008. while staying compliant to this standard, it is able to cover as well the short pwm code (spc) protocol extensions. this enhances the standardized sent protocol defined by j2716 feb2008. spc enables the use of enhanced protocol functionality like ?synchronous?, ?range selection? and ?id selection? protocol mode. receive data on a sent channel can be set up according to the underlying application. in particular the number of nibbles forming one value is configurable. the message storage consists of two 32-bi t registers for each channel, representing a flexible double buffer system. in spc mode, maintaining the sample and transmission schedule as well as providing message status information is support. the register set of the sent module can be accessed directly by the cpu for configuration, data read out and status query. the sent ip-module supports the following features: feature list the sent module provides the following features: ? conformance with sent protocol specification j2716 feb2008 ? data rates of up to 65,8 kbit/s at 3 s tick length and 6 data nibbles on each channel ? support of standard tick times (3 s through 90 s) and ? message tick time programmable between 1 s and 90 s ? 8 sent channels working independently in parallel ? status nibble optionally included in the checksum (default not included) ? sticky interrupt flags, error interrupt optional (default disabled) ? configurable frame length (default is 24 bit), max data size is 32 bits ? serial data processing optional (default: disabled) ? option for bigger frame lengths (must still be fix for each application) ? transparent mode (nibble crcs are written to the receive control register for sw processing) ? support of spc ? support of trailing pause nibble of any length (even longer than 70 ticks) ? indication of system status: stop , initialized, running, synchronized www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-43 v1.1, 2011-03 introduction, v1.3 ? the receiver module will monitor the message for the following error conditions: ? calibration pulse length deviates more than +/-25% from the nominal 56 ticks ? too many or too few nibbles between calibration pulses. ? checksum error. ? successive calibration pulse differ by more than 1.5625% ? any nibble data values measured as < 0 or >15. ? when any of those errors is detected, the receiver module shall declare that a message error has occurred and ignore the entire message. ? any of those errors shall cause the receiver to begin searching for a valid calibration pulse to re synchronize. ? option to enable/disable the check of the next calibration pulse before validation of received data ? digital glitch filter suppressing noise ? buffer overrun detection ? optional output inversion for use of external open drain transistor ? optional input inversion for use of external open transistor for level shifting ? interrupt on status nibble violation ? programmable nibble sorting to support lsn or hsn first and relief cpu www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-44 v1.1, 2011-03 introduction, v1.3 1.4.10 general purpose timer array (gptav5) the TC1798 contains the two general purpose timer arrays (gpta0 and gpta1) with identical functionality, plus the additional local timer cell array (ltca2). the gpta provides a set of timer, com pare, and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. they are optimized for tasks typical of engine, gearbox , and electrical motor control applications, but can also be used to generate simple and complex signal waveforms required for other industrial applications. 1.4.10.1 gpta0 and gpta1 feature list the general purpose timer arrays (gpta0 and gpta1) each provides a set of hardware modules required for high-speed digital signal processing: ? filter and prescaler cells (fpc) support input noise filtering and prescaler operation. ? phase discrimination logic units (pdl) decode the direction information output by a rotation tracking system. ? duty cycle measurement cells (dcm) provide pulse-width measurement capabilities. ? a digital phase locked loop unit (pll) generates a programmable number of gpta module clock ticks during an input signal?s period. ? global timer units (gt) driven by various clock sources are implemented to operate as a time base for the associated global timer cells. ? global timer cells (gtc) can be programmed to capture the contents of a global timer on an external or inter nal event. a gtc may also be used to control an external port pin depending on the result of an internal compare operation. gtcs can be logically concatenated to provide a common external port pin with a complex signal waveform. ? local timer cells (ltc) operating in timer, capture, or compare mode may also be logically tied together to drive a common external port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mode ? can be clocked or triggered by various external or internal events. ? on-chip trigger and gating signals (otgs) can be configured to provide trigger or gating signals to integrated peripherals (gpta0 only). input lines can be shared by an ltc and a gtc to trigger their programmed operation simultaneously. the following list summarizes the specific features of the gpta units. clock generation unit ? filter and prescaler cell (fpc) ? six independent units www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-45 v1.1, 2011-03 introduction, v1.3 ? three basic operating modes: prescaler, delayed debounce filter, immediate debounce filter ? selectable input sources: port lines, gpta module clock, fpc output of preceding fpc cell ? selectable input clocks: gpta module clock, prescaled gpta module clock, dcm clock, compensated or uncompensated pll clock. ? f gpta /2 maximum input signal frequency in filter modes ? phase discriminator logic (pdl) ? two independent units ? two operating modes (2- and 3- sensor signals) ? f gpta /4 maximum input signal frequency in 2-sensor mode, f gpta /6 maximum input signal frequency in 3-sensor mode ? duty cycle measurement (dcm) ? four independent units ? 0 - 100% margin and time-out handling ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? digital phase locked loop (pll) ?one unit ? arbitrary multiplication factor between 1 and 65535 ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? clock distribution unit (cdu) ?one unit ? provides nine clock output signals: f gpta , divided f gpta clocks, fpc1/fpc4 outputs, dcm clock, ltc prescaler clock signal generation unit ? global timers (gt) ? two independent units ? two operating modes (free-running timer and reload timer) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? global timer cell (gtc) ? 32 units related to the global timers ? two operating modes (capture, compare and capture after compare) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? local timer cell (ltc) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-46 v1.1, 2011-03 introduction, v1.3 ? 64 independent units ? three basic operating modes (timer, capture and compare) for 63 units ? special compare modes for one unit ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency interrupt sharing unit ? 143 interrupt sources, generating up to 46 service requests on-chip trigger unit ? 16 on-chip trigger signals i/o sharing unit ? interconnecting inputs and outputs from inte rnal clocks, fpc, gt c, ltc, ports, and msc interface 1.4.10.2 ltca2 feature list the local timer cell array (ltca2) provides a set of hardware modules required for high-speed digital signal processing: ? local timer cells (ltc) operating in timer, capture, or compare mode may also be logically tied together to drive a common external port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mode ? can be clocked or triggered by various external or internal events. the following list summarizes the specific features of the ltca unit. the local timer arrays (ltca2) provides a set of hardware modules required for high- speed digital signal processing: signal generation unit ? local timer cell (ltc) ? 64 independent units ? three basic operating modes (timer, capture and compare) ? special compare modes for one unit ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-47 v1.1, 2011-03 introduction, v1.3 i/o sharing unit ? interconnecting input s and outputs from internal clocks, lt c, ports, and msc interface 1.4.11 capture/comp are unit 6 (ccu6) the capcom6 provides two independent timers (t12, t13), which can be used for pwm generation, especially for ac-motor cont rol. additionally, special control modes for block commutation and multi-phase machines are supported. ccu6061 module consists of ccu60 and ccu61 kernels while ccu6263 consists of ccu62 and ccu63 kernels. figure 1-13 ccu6 block diagram 1.4.11.1 feature list the ccu6 module provides the following features: timer 12 features ? three capture/compare channels, each cha nnel can be used either as capture or as compare channel. ccu6_block_diagram channel 0 channel 1 channel 2 t12 dead- time control input / output control cc62 cout62 cc61 cout61 cc60 cout60 cout63 ct rap channel 3 t13 ccpos0 1 1 1 2 2 2 1 start compare capture 3 multi- channel control address decoder clock system interrupt control trap control compare compare compare compare 1 trap input ccpos1 ccpos2 ou t p ut s el e ct ou t p ut s el e ct 3 hall input ccu6 module kernel f ccu sr[3:0] start control t12hr t13hr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-48 v1.1, 2011-03 introduction, v1.3 ? generation of a three-phase pwm supported (six outputs, individual signals for highside and lowside switches) ? 16 bit resolution, maximum count frequency = peripheral input clock ? dead-time control for each channel to avoid short-circuits in the power stage ? concurrent update of the required t12/13 registers ? center-aligned and edge-aligned pwm can be generated ? single-shot mode supported ? many interrupt request sources ? hysteresis-like control mode ? synchronized start supported (triggered by an external scu signal through t12hr input for each ccu6 module) timer 13 features ? one independent compare channel with one output ? 16 bit resolution, maximum count frequency = peripheral input clock ? can be synchronized to t12 ? interrupt generation at period-match and compare-match ? single-shot mode supported ? synchronized start supported (triggered by an external scu signal through t13hr input for each ccu6 module) additional features ? block commutation for brushl ess dc-drives implemented ? position detection via hall-sensor pattern ? automatic rotational speed measurement for block commutation ? integrated error handling ? fast emergency stop without cpu load via external signal (ctrap ) ? control modes for multi-channel ac-drives ? output levels can be selected and adapted to the power stage the timer t12 can work in capture and/or compare mode for its three channels. the modes can also be combined. the timer t13 can work in compare mode only. the multi- channel control unit generates output patterns which can be modulated by timer t12 and/or timer t13. the modulation sources can be selected and combined for the signal modulation. 1.4.12 general purpose timer (gpt12) the gpt12e unit represents a very flexible multifunctional timer/counter structure which may be used for many different time rela ted tasks such as event timing and counting, pulse width and duty cycle meas urements, pulse gener ation, or pulse mu ltiplication. its functionality includes enhanced incremental interface modes and clock prescaler support. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-49 v1.1, 2011-03 introduction, v1.3 1.4.12.1 feature list the gpt12e module provides the following features. ? timer block gpt1: ? maximum resolution peripheral input clock / 4 ? clock prescaler support ? 3 independent timers/counters (t2, t3, t4). ? timers/counters can be concatenated. ? 4 operating modes (timer, gated timer, counter, incremental). ? enhanced incremental interface modes ? separate interrupt request lines. ? timer block gpt2: ? maximum resolution peripheral input clock / 2 ? clock prescaler support ? 2 independent timers/counters (t5, t6). ? timers/counters can be concatenated. ? 3 operating modes (timer, gated timer, counter). ? extended capture/reload functions via 16-bit capture/reload register caprel ? separate interrupt request lines. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-50 v1.1, 2011-03 introduction, v1.3 1.4.13 external bus interface (ebu) the external bus unit (ebu) of the TC1798 controls the accesses from the cpu and peripheral units to external memories. 1.4.13.1 feature list the ebu module provides the following features: ? 64-bit internal sri interface ? 32-bit external bus interface ? interface can be configured to support memory devices with 32 bit, 16 bit and 8 bit databus connections ? support for 3.3 v and 2.5 v memory devices ? limited support for 1.8 v memories ? flexibly programmable access parameters (e.g. control signal pulse width ,bus turnaround time, burst length for synchronous memories). ? different device settings available for read and write accesses ? programmable address range for each chip select line. ? support for multiple device access protocols ? asynchronous memories e.g. sram, peripheral devices ? synchronous devices e.g. burst nor flash, psram ? ddr nor flash e.g. lpddr-nvm (jedec 42.4), onfi 2.0 (both at limited frequency using 1.8 v i/o supply). ? scalable external bus timing ? derived from sri frequency ( f cpu ) by dividers internal to the ebu. ? can also be derived from the flexray clock. ? maximum 75 mhz ? data buffering supported ? read/write buffer www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-51 v1.1, 2011-03 introduction, v1.3 1.4.14 analog-to-digital converters (adc/fadc) the TC1798 includes analog to digital co nverter modules )adc)and one fast analog to digital converter (fadc). 1.4.15 adc module the analog to digital converter module (adc) allows the conversion of analog input values into discrete digital values based on the successive approximation method. this module contains 4 independent kernels (adc0, adc1, adc2, adc3) that can operate autonomously or can be synchronized to each other. an adc kernel is a unit used to convert an analog input signal (done by an analog part) and provides means for triggering conversions, data handling and storage (done by a digital part). figure 1-14 adc module with four adc kernels adc kernel 2 ad converter conversion control adc kernel 1 ... analog inputs data (result) handling request control bus inter- face ad converter conversion control ... data (result) handling request control analog inputs ad converter conversion control adc kernel 0 ... analog inputs data (result) handling request control adc kernel 3 adc_ 4_kernels ad converter conversion control ... data (result) handling request control analog inputs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-52 v1.1, 2011-03 introduction, v1.3 1.4.15.1 feature list each adc kernel provides the following features: ? analog supply voltage range from 3.3 v (minimum) to 5 v (nominal) for v ddm ? input voltage range from 0 v to analog supply voltage v ddm ? input multiplexer for a maximum of 16 possible analog input channels ? one standard reference input (v aref ) and one alternative reference input (ch0) available ? broken wire detection support for each input channel ? multiplexer test support for input channels with odd channel numbers ? 5 conversion request sources for exte rnal or timer-driven events, auto-scan, programmable sequences, sw-driven conversions, etc. ? synchronization of the adc kernels for concurrent conversion starts and parallel sampling and measuring of analog input signals, e.g. for phase current measurements in ac drives ? control capability for an external analog multiplexer, respecting the additional set up time ? adjustable sampling times to accommodate output impedance of different analog signal sources (sensors, etc.) ? possibility to cancel running conversions on demand with automatic restart ? flexible interrupt generation (possibility of dma support) ? limit checking to reduce interrupt l oad (e.g. for temperature measurements or overload detection, only values exceeding a programmable level lead to an interrupt) ? programmable data reduction filter, e.g. for digital anti-aliasing filtering, by adding a programmable number of conversion results ? independent result registers (16 independent registers) ? support of conversion result fifo mechanism to allow a longer interrupt latency ? programmable result data filter providing 3rd order fir or 1st order iir filter structure ? support of suspend and power saving modes ? individually programmable reference selection for each channel, e.g. to allow measurements of 3.3 v and 5 v signals in the full measurement range with the same adc kernel (with exception of dedicated channels always referring to v aref ) 1.4.16 fadc module as shown in figure 1-15 , the main fadc functional blocks are: ? an input structure containing the diff erential inputs and impedance control. ? an a/d converter stage responsible for the analog-to-digital conversion including an input multiplexer to select between the channel amplifiers ? a data reduction unit containing programmable anti-aliasing and data reduction filters ? a channel trigger control block determining the trigger and gating conditions for the fadc channels www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-53 v1.1, 2011-03 introduction, v1.3 ? a channel timer for each channel to independently trigger the conversions ? an a/d control block responsible for the overall fadc functionality figure 1-15 block diagram of the fadc module with 4 input channels fadc power supply and references the fadc module is supplied by the following power supply and reference voltage lines: ?v ddmf / v ssmf : fadc analog channel amplifier power supply (3.3 v) ?v ddif / v ssmf : fadc analog input stage power supply (3.3 - 5 v), the v ddif supply does not appear as supply pin, because it is internally connected to the v ddm supply of the adc that is sharing the fadc input pins. ?v ddaf / v ssaf : fadc analog part power supply (1.3 v), to be fed in externally ?v faref / v fagnd : fadc reference voltage (3.3 v max.) and fadc reference ground input structure the input structure of the fadc in the TC1798 contains: ? a differential analog input stage for each input channel to select the input impedance (differential or single-ended measurement) and to decouple the fadc input signal from the pins. ? all input channels are overlaid with adc1 input signals (an24 - an31). srx mcb06065_m4 v fagnd v ddaf v ssaf v ddmf v faref v ssmf interrupt control ts[h:a] gs[h:a] clock control f fadc f clc a/d converter stage data reduction unit fain0p fain0n fain1p fain1n input structure channel trigger control channel timers srx dma a/d control v ddif input channel 0 input channel 1 fain2p fain2n fain3p fain3n input channel 2 input channel 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-54 v1.1, 2011-03 introduction, v1.3 ? a channel amplifier for each input channel with a settling time (about 5s) when changing the characteristics of an input stage (changing between unused, differential, single-ended n, or single-ended p mode). figure 1-16 fadc input structure in TC1798 1.4.16.1 fadc feature list the fadc module provides the following features ? extreme fast conversion, 21 cycles of f fadc clock ? 10-bit a/d conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) ? successive approximation conversion method ? all differential input channels with impedance control ? all fadc inputs are overlaid with adc1 inputs ? each differential input channel can also be used as single-ended input ? offset calibration support for each channel ? programmable gain of 1, 2, 4, or 8 for each channel mca06432_m4n fain0n fain0p analog input stages rp rn channel amplifier stages gain a/d a/d control conversion control converter stage chnr v ddaf v ssaf fain2n fain2p rp rn fain1n fain1p rp rn v ddif fain3n fain3p rp rn v ssmf v ssmf v ddmf v ssmf v ddmf v ssmf v ddmf v ssmf v ddmf www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-55 v1.1, 2011-03 introduction, v1.3 ? free-running (channel timers) or triggered conversion modes ? trigger and gating control for external signals ? built-in channel timers for internal triggering ? channel timer request periods independently selectable for each channel ? selectable, programmable digital anti-aliasing and data reduction filter block with four independent filter units 1.5 on-chip debug support (ocds) the TC1798 contains resources for different kinds of ?debugging?, covering needs from software development to real-time-tuning. these resources are either embedded in specific modules (e.g. breakpoint logic of t he tricore) or part of a central peripheral (known as c erberus ). 1.5.1 on-chip debug support the classic software debug approach (start/stop, single-stepping) is supported by several features labelled ?ocds level 1?: ? run/stop and single-step execution independently for tricore and pcp. ? means to request all kinds of reset without usage of sideband pins. ? halt-after-reset for repeatable debug sessions. ? different boot modes to use application software not yet programmed to the flash. ? a total of eight hardware breakpoints for the tricore based on instruction or data address. ? tricore ocds logic fully independent of the memory protection system. ? unlimited number of software breakpoints (debug instruction) for tricore and pcp. ? debug event generated by access to a spec ific address via the system peripheral bus or the sri cross connect. ? tool access to all sfrs and internal memories independent of the cores. ? two central break switches to collect debug events from all modules (tricore, pcp, dma, sri, bcu, break input pins) and distribute them selectively to breakable modules (tricore, pcp, break output pins). ? central suspend switch to suspend parts of the system (tricore, pcp, peripherals) instead if breaking them as reaction to a debug event. ? dedicated interrupt resources to handle debug events inside tricore (breakpoint trap, software interrupt) and cerberus (can trigger pcp), e.g. for implementing monitor programs. ? access to all ocds level 1 resources also for tricore and pcp themselves for debug tools integrated into the application code. ? triggered transfer of data in response to a debug event; if target is programmed to be a device interface simple variable tracing can be done. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-56 v1.1, 2011-03 introduction, v1.3 ? in depth performance analysis and profiling support given by the emulation device through mcds event counters driven by a va riety of trigger signals (e.g. cache hit, wait state, interrupt accepted). 1.5.2 real time trace for detailed tracing of the system?s behavior a pin-compatible emulation device will be available. 1) 1.5.3 calibration support two main use cases are catered for by resources in addition the ocds level 1 infrastructure: overlay of non-volatile on -chip memory and non-intrusive signaling: ? on-chip sram for overlay (allocated from lmu ram pool). ? can be split into up to 16 blocks which can overlay independent memory regions during data reads (e.g. on-chip flash). ? changing the configuration is triggered by a single sfr access to maintain consistency. ? overlay configuration switch does not require the tricore to be stopped or suspended. ? invalidation of the data cache (maintaining write-back data) can be done concurrently with the same sfr. ? 768 kb additional overlay ram on emulation device, shared with the trace functionality. ? a dedicated trigger sfr with 32 independent st atus bits is provided to centrally post requests from application code to the host computer. ? the host is notified automatically when the trigger sfr is updated by the tricore or pcp. no polling via a sy stem bus is required. 1.5.4 tool interfaces three options exist for the communication channel between tools (e.g. debugger, calibration tool) and TC1798: ? two wire dap (device access port) protocol for long connections or noisy environments. ? four (or five) wire jtag (ieee 1149.1) for standardized manufacturing tests. ? can (plus software linked into the application code) for low bandwidth deeply embedded purposes. ? dap and jtag are clocked by the tool. ? bit clock up to 40 mhz for jtag, up to 80 mhz for dap. 1) the ocds l2 interface of audong is not available. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-57 v1.1, 2011-03 introduction, v1.3 ? hot attach (i.e. physical disconnect/reconnect of the host connection without reset of the TC1798) for all interfaces. ? infineon standard das (device access server) implementation for seamless, transparent tool access ov er any supported interface. ? lock mechanism to prevent unauthorized to ol access to critical application code. 1.5.5 self-test support some manufacturing tests can be invoked by the application (e.g. after power-on) if needed: ? hardware-accelerated checksum calc ulation (e.g. for flash content). ? ram tests optimized for the implemented architecture. 1.5.6 far support to efficiently locate and identify faults after integratio n of a TC1798 into a system special functions are available: ? boundary scan (ieee 1149 .1) via jtag and dap. ? sscm (single scan chain mode) for structural scan testing of the chip itself. ? spd (single pin dap) protocol via can0 pins. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 introduction users manual 1-58 v1.1, 2011-03 introduction, v1.3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-1 v1.1, 2011-03 cpu, v1.0 2 cpu subsystem the TC1798 processor contains a tricore 1.6 cpu. this chapter describes the implementation-specific options of the cpu, and should be read in conjunction with the tricore architecture manual, which descr ibes the complete tricore architecture including the register and instruction set. 2.1 TC1798 processor subsystem the diagram below shows the block di agram of the processor subsystem. figure 2-1 TC1798 processor subsystem block diagram ebu tricore cpu pmi system peripheral bus (spb) bridge smif dmi ldram dcache pmu 1 2 mb pflash m m/s 32 kb pspr 16 kb icache 128 kb dspr 16 kb dcache fpu abbreviations: icache: instruction cache dcache data cache pspr: program scratch-pad ram dspr: data scratch-pad ram brom: boot rom pflash: program flash dflash: data flash dma 2 x 8 channels cross bar interconnect (sri) 2 mb pflash 196 kb dflash 16 kb brom pmu 0 lmu 128 kb sram bcu cps www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-2 v1.1, 2011-03 cpu, v1.0 2.2 central processing unit features the 330 mhz tricore TC1798 cpu includes: architecture ? 32-bit load store architecture ? 4 gbyte address range (2 32 ) ? 16-bit and 32-bit instructions for reduced code size ? data types: ? boolean, integer with saturation, bit array, signed fraction, character, double-word integers, signed integer, uns igned integer, ieee-754 sing le-precision floating point ? data formats: ? bit, byte (8-bits), half-word (16-bits), word (32-bits), double-word (64-bits) ? byte and bit addressing ? little-endian byte ordering for data, memory and cpu registers ? multiply and accumulate (mac) instructions: dual 16 16, 16 32, 32 32 ? saturation integer arithmetic ? packed data ? addressing modes: ? absolute, circular, bit reverse, long + short, base + offset with pre- and post-update ? instruction types: ? arithmetic, address arithmetic, compar ison, address comparison, logical, mac, shift, coprocessor, bit logical, branch, bit field, load/store, packed data, system ? general purpose register set (gprs): ? sixteen 32-bit data registers ? sixteen 32-bit address registers ? three 32-bit status and program counter registers (psw, pc, pcxi) ? core debug support (ocds): ? level 1, supported in conjunction with the cps block ? level 3, supported in conjunction with the mcds block (emulation device only). ? flexible memory protection system providin g multiple protection sets with multiple protection ranges per set. ? temporal protection system allowing time bounded real time operation. implementation ? most instructions executed in 1 cycle ? branch instructions in 1, 2 or 3 cycles (using branch prediction) ? wide memory interface for fast context switch ? automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap ? four memory protection register sets ? dual instruction issuing (in parallel into integer pipeline and load/store pipeline) ? third pipeline for loop instruction only (zero overhead loop) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-3 v1.1, 2011-03 cpu, v1.0 ? single precision floating point unit ? dedicated integer divide unit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-4 v1.1, 2011-03 cpu, v1.0 2.2.1 cpu diagram the central processing unit (cpu) comprises of an instruction fetch unit, an execution unit, a general purpose register file (gpr ), a cpu slave interface (cps), and floating point unit (fpu). figure 2-2 cpu block diagram execution unit mcb0606 9 to program memory interface (pmi) integer pipeline general purpose register file (gpr) instruction fetch unit core register access address registers data registers to data memory interface (dmi) coprocessor interface floating point unit (fpu) cpu slave interface (cps) interrupts system control test debug/emulatio n loop pipeline load store pipeline 64 64 64 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-5 v1.1, 2011-03 cpu, v1.0 2.2.2 instruction fetch unit the instruction fetch unit pre-fetches and aligns incoming instructions from the 64-bit wide program memory interface (pmi). instructions are placed in predicted program order in the issue fifo. the issue fifo buffers up to six instructions and directs the instruction to the appropriate execution pipeline. the instruction protec tion unit checks the validity of accesses to the pmi and the integrity of incoming instructions fetched from the pmi. the branch unit examines the fetched instructions for branch conditions and predicts the most likely execution path based on prev ious branch behavior. the program counter unit (pc) is responsible for updating the program counters. figure 2-3 instruction fetch unit mca06070 issue unit to loop pipeline injection pc unit align prefetch instruction protection to load/store pipeline to integer pipeline 64 program memory interface debu g www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-6 v1.1, 2011-03 cpu, v1.0 2.2.3 execution unit the execution unit contains the integer pipeline, the load/store pipeline and the loop pipeline. all three pipelines operate in parallel, permitting up to three instructions to be executed in one clock cycle. in the execution unit all instructions pass through a decode stage followed by two execute stages. pipeli ne hazards (stalls) are minimised by the use of forwarding paths between pipeline stages allowing the results of one instruction to be used by a following instruction as soon as the result becomes available. figure 2-4 execution unit mca06071 loop exec. to register file ea address alu alu bit processor mac load/store decode ip decode integer pipeline loop pipeline load/store pipeline decode execute loop decode i p decode = instruction prefetch and decode m ac = multiply-accumulate unit a lu = arithmetic/logic unit l oop exec. = loop execution unit ea = effective address www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-7 v1.1, 2011-03 cpu, v1.0 2.2.4 general purpose register file the cpu has a general purpose register (gpr) file, divided into an address register file (registers a0 through a15) and a data register file (registers d0 through d15). the data flow for instructions issued to the load/store pipeline is steered through the address register file. the data flow for instructions issued to/from the integer pipeline and for data load/store instructions issued to the load/store pipeline is steered through the data register file. figure 2-5 general purpose register file general purpose register file mca06072 data register file address register file to pipelines 64 data alignment 64 128 to data memory interface www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-8 v1.1, 2011-03 cpu, v1.0 2.3 summary of functional changes from tc1.3.1 to achieve higher frequencies the tricore1.6 pipeline is increased from 4 to 6 stages. figure 2-6 tc1.6 and tc1.3.1 pipelines to mitigate the effects on performance of the longer pipeline the following fetch and branch features are implemented. ? fifo decoupled fetch and execute stages. ? dynamic branch prediction using combined bimodal predictor table and branch target buffer. ? loop aware branch prediction. one effect of the longer pipeline is to increase the load-use penalty to 1 from 0. this necessitates re-scheduling of code to achieve optimum performance. other significant adaptations to the existing tc1.3.1 cpu are as follows: ? fully pipelined floating point unit (fpu) ? most floating point instructions now have a repeat rate of 1 ? improved debug system - now deco upled from protection system. ? 8 comparators proving up to 4 ranges, selectable for pc or load-store address ? expanded and enhanced memory protection unit (mpu) ? 16 data ranges and 8 code ranges shared between 4 protection sets. ? new temporal protection system. tc16_tc131_pipelines.vsd d e wb f d e wb d e wb pd d e1 e2 pd d e1 e2 pd d e1 e2 f2 f1 loop load-store integer loop load-store integer / fpu key: f = fetch, pd = predecode, d=decode, e=execute tc1.3.1 pipeline tc1.6 pipeline www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-9 v1.1, 2011-03 cpu, v1.0 ? guards against task runtime overrun. ? new safe interrupt mode. ? interrupt acknowledge decoupled from interrupt entry. ? new instructions for improved interrupt and data cache manipulation support. ? disable, restore, cachei.i ? new instructions fo r fast integer divide ?div, div.u ? new instructions for fast call and return with minimal saving of state. ? fcall, fcalla, fcalli, fret ? long offset addressing mode introduced for byte, half word and address accesses. ? ld.bu, ld.b, ld.hu, ld.h, st.b, st.h, st.a ? extended range of 16 bit jumps ?jeq, jne ? increased flexibility in the system address map. ? full secded ecc protection for all scratch, cache and tag memory structures. ? cache and scratch memory systems now entirely separated. ? cache memories may be mapped as additional scratch. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-10 v1.1, 2011-03 cpu, v1.0 2.4 cpu implementation-specific features this section describes the implementation-spec ific features of the cpu. for a complete description of all registers, refer to the tricore architecture manual. 2.4.1 context save areas context save areas (csa) may be placed in dspr or external memory (cached or uncached). the cpu uses a uniform context-switching method for function calls, interrupts and traps. in all cases the upper context of the task is automatically saved and restored by hardware. saving and restoring of the lower context may be optionally performed by software. csa placement in dspr the actual timing of context operations is dependent upon the placement of the context save areas. maximum performance is achiev ed when the context save area is placed in dspr. in this case all context save and restores operations take four cycles. csa placement in cached external memory in this case, the timing is also dependent on the state of the data cache. the best case data cache operation occurs when context saves do not incur a cache line writeback, and context restores hit in the data cache. in this case all context saves and restores take eight cycles. 2.4.2 program counter (pc) register the program counter (pc) holds the address of the instruction that is currently fetched and forwarded to the cpu pipelines. the cpu handles updates of the pc automatically. software can use the cu rrent value of the pc for variou s tasks, such as performing code address calculations. reading the pc through software executed by the cpu must only be done with an mfcr instruction. such a read will return the pc of the mfcr instruction itself. explicit writes to the pc through an mtcr instruction must not be done due to possible unexpected behavior of the cpu. the cpu must not perform load/store instructions to the mapped address of the pc in segment 15. a mem trap will be generated in such a case. bit 0 of the pc register is read-only and hard-wired to 0. 2.4.3 store buffers to increase performance the tc1.6 cpu im plements store buffering to decouple memory write operations from cpu instructio n execution. all stores from the cpu are placed in the store buffer prior to being written to local memory or transferred via the bus www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-11 v1.1, 2011-03 cpu, v1.0 system. write data is taken from the store bu ffers and written to memory when the target memory or bus interface becomes available. in normal operation the cpu will prioritise memory load operations over store operatio ns in order to improve performance unless:- ? the store buffer is full. ? the load is to peripheral space and a stor e to peripheral space exists in the store buffer. (in order peripheral space access). ? the load or store is part of an atomic operation. typically the operation of the store buffer is invisible to the end user. if there is a requirement that data is written to memory prior to execution of a subsequent instruction then a dsync instruction may be used to flush the store buffers. to further improve performance consecutive by te writes to the same half word location are merged in the store buffer. the tc1.6 cpu store buffer can hold the data for up to 6 stores. store buffer operation may be disabled be setting the smacon.iodt bit. this should not be done in normal execution as it will severely limit performance. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-12 v1.1, 2011-03 cpu, v1.0 2.4.4 interrupt system an interrupt request can be generated by th e on-chip peripheral units, or it can be generated by external events. requests can be targeted to either the cpu, or to the peripheral control processor (pcp). the interrupt system evaluates service requests for priority and to identify whether the cpu (or pcp) should receive the request. the highest-priority service request is then presented to the cpu (or pcp) by way of an interrupt. the term ?interrupt? is used generally to mean an event directed to the cpu, while the term ?service request? describes an event th at can be directed to either the cpu or the pcp. 2.4.4.1 interrupt acknowledge decoupling for safety systems in order to improve plausibility checks on interrupt service routines (isr) a modification to the interrupt controller (icu) is introduced. when an interrupt service request node (srn) is arbitrated the icu sends an acknowledge indicating which srn is the winner. upon reception of the information the winner srn automatically clears the request flag. this happens before the isr executes. therefore the isr can't directly double check if the node corresponding to it's interrupt level was active or not. the tricore1.6 implements a new mode where the feedback after an arbitration round is controlled by software, a llowing an isr to make cons istency checks a nd then enabling the icu to proceed with terminating the arbitration round and enabling further interrupts. on entering an interrupt the bit safeint.int (0xfe30, bit-0) is set. the cpu holds off acknowledging the interrupt until this bit is cleared by a software write. note that this delays re-arbitration and hence will impact interrupt performance. interrupt acknowledge decoupling is enabled by the compat.int bit. by default the standard, non-decoupled solution is selected. 2.4.5 trap system the following traps have implementation-specific properties. uopc - unimplemented opcode (tin 2) the uopc trap is raised on optional mmu instructions, coprocessor two and coprocessor three instructions. opd - invalid operand (tin 3) the cpu raised opd traps for instructions t hat take even-odd register pairs as an operand where if the operand specifier is odd. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-13 v1.1, 2011-03 cpu, v1.0 dse - data access synchronous error (tin 2) the data access synchronous bus error (d se) trap is generated by the dmi module when a load access from the cpu encounters certain error conditions, such as a bus error, or an out-of-range access to dspr. when a dse trap is generated, the exact cause of the error can be determined by read ing the data synchronous trap register, dstr. for details of possible error conditions and the corresponding flag bits in dstr, see ?dmi trap generation? on page 2-90 . dae - data access asynchronous error (tin 3) the data access asynchronous error trap (dae) is generated by the dmi module when a store or cache management access from the cpu encounters certain error conditions, such as an bus error. when a dae trap is generated, the exact cause of the error can be determined by reading the data asynchronous trap register, datr. for details of possible error conditions and the corresponding flag bits in datr, see ?dmi trap generation? on page 2-90 . pie program memory in tegrity error (tin 5) the pie trap is raised whenever an uncorrectable memory integrity error is detected in an instruction fetch from a local memory . the trap is synchronous to the erroneous instruction. the trap is of class-4 and has a tin of 5. program memories are protected from memory integrity errors on a 64 bit basis. a pie trap is raised when an attempt is made to execute an instruction from any 64bit fetch group containing a memory integrity error. the piear and pietr registers may be interrogated to determine the source of any error more precisely. die data memory integrity error (tin 6) the die trap is raised whenever an uncorrectable memory integrity error is detected in a data access to a local memory. the trap is of class-4 and has a tin of 6. die traps are always asynchronous independent of the operation which encountered the error. a die trap is raised if any memory half word accessed by a load/store operation contains an uncorrectable error. the diear and dietr registers may be interrogated to determine the source of any error more precisely. 2.4.6 memory integrity error handling the tricore 1.6 contains integrated support for the detection and handling of memory integrity errors. the handling of memory integrity errors for the various memory types in tricore 1.6 is as follows: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-14 v1.1, 2011-03 cpu, v1.0 2.4.6.1 program side memories the program side memories of the tricore 1.6 core consist of two independent memory structures:- the program scratchpad ram (pspr) and instruction cache (icache). both memory structures are ecc protected fr om memory integrity errors on a 64bit basis with ecc calculated across both address and data. any sub-64bit write access to the pspr from the bus interface is converted to a 64bit read-modify-write sequence by the pmi module. program scratchpad ram (pspr) the scratchpad ram of tricore 1.6 is protecte d from memory integrity errors on a 64bit basis with ecc calculated across address and data. eight ecc bits are required per 64 bits stored. uncorrectable memory integrity error detection in the pspr is enabled by setting miecon.psmiee to one. when miecon.psmi ee is zero all un correctable memory integrity errors are ignored. error correction is enabled by setting the miecon2.psmsece to one. w hen the miecon2.psmsece is zero all errors are treated as uncorrectable. if a correctable error is detected during a memory read and error correction is enabled via the mi econ2.psmsece then t he read data will be corrected and the ccpier.ccpie_u counter incremented to record the fact the an unresolved correctable program integrity error has been detected. (the error is considered unresolved as the memory itself is not updated with the corrected value). for instruction fetch requests from the tricore cpu to pspr, the ecc bits are read along with the data bits and are passed to the cpu along with their corresponding instructions. whenever an attempt is made to issue an instruction containing an uncorrectable memory integrity error a synchronous pie trap is raised. the trap handler is then responsible for correcting the memory entry and re-starting program execution. for pspr read operations from the bus interf ace, either from the dmi module or another bus master agent, an access that results in the detection of an uncorrectable memory integrity error in the requested data causes a bus error to be returned for the bus transaction. since the tricore cpu may not be involved in the transaction, a separate error is also flagged to the scu module to optionally generate an nmi trap back to the core. writes to program scratchpad memory are on ly ever performed from the bus interface. for write operations of 64bit size or great er, the ecc bit values are pre-computed based on the 64-bit granularity and written to the scratch memory in parallel with the data. for sub 64bit write operations the memory transaction is transformed into a 64bit read- modify-write sequence inside the pmi module. as such, sub-64 bit write operations may result in the detection of uncorrectable memory integrity errors, which are handled as standard read operations. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-15 v1.1, 2011-03 cpu, v1.0 instruction cache (icache) the scratchpad ram of tricore 1.6 is protecte d from memory integrity errors on a 64bit basis with ecc calculated across address and data. the instruction cache stores eight ecc bits per 64 bits. uncorrectable memory integrity error detection in the icache is enabled by setting miecon.pcmiee to one. when miecon.pcm iee is zero all uncorrectable memory integrity errors are ignored. error correction is enabled by setting the miecon2.pcmsece to one. when the miecon2.pcmsece is zero all errors are treated as uncorrectable. if a correctable error is detected during a memory read and error correction is enabled via the miecon2.pcmsece then the read data will be corrected and the ccpier.ccpie_u counter incremented to record the fact the an unresolved correctable program integrity error has been detected. (the error is considered unresolved as the memory itself is not updated with the corrected value). for instruction fetch requests from the tricore cpu to icache, the ecc bits are read along with the data bits of all cache ways, and an uncorrectable error signal generated for each 64 bits of each cache way. in the case of a tag hit, the uncorrectable error signals for the corresponding cache way are passed to the core along with their corresponding instructions. whenever an attempt is made to issue an instruction containing an uncorrectable error a synchronous pie trap is raised. the trap handler is then responsible for checking the source of the memory integrity error. program tag (ptag) the program tag stores a 21-bit tag field for each of the cache ways in a set. as such the program tag is written with 21-bit granularity and six ecc bits are associated with each 21-bit tag way. uncorrectable memory integrity error detection in the ptag is enabled by setting miecon.ptmiee to one. when miecon.ptmiee is zero all uncorrectable memory integrity errors are ignored. error correction is enabled by setting the miecon2.ptmsece to one. when the miec on2.ptmsece is zero all errors are treated as uncorrectable. if a correctable error is detected during a memory read and error correction is enabled via the miecon2.ptmsece then the read data will be corrected and the ccpier.ccpie_u counter incremented to record the fact the an unresolved correctable program integrity error has been detected. (the error is considered unresolved as the memory itself is not updated with the corrected value). for instruction fetch requests from the tricore cpu to icache, the program tag ecc bits are read along with the data bits and an error flag is computed. a way hit is triggered only if the tag address compar ison succeeds, the valid bit is set and no ecc error in the associated tag way is detected, any other result is considered a miss. in the normal case where no error is detected in either cache way then the cache line is filled/refilled as normal. in the case where an error is de tected the cache controller replacement algorithm forces the way indicating an error to be replaced. since such errors are www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-16 v1.1, 2011-03 cpu, v1.0 otherwise transparent to the tricore cpu, th e ccpie_r counter is incremented to allow counting of such error corrections if required. in the case where one cache way flags a cache hit, and another cache way detects an uncorrectable ecc error, the error condition is masked and has no effect on the memory integrity error handling mechanisms. 2.4.6.2 data side memories the data side memories of the tricore 1.6 core consist of two separate memory structures:- the data scratchpad ram (dspr) and data cache (dcache). both memory structures are ecc protected from memory integrity errors on a per-half word basis. any byte write access to either dspr or dcache is converted to a halfword read- modify-write sequence. the transformation of such byte accesses to atomic sequences is performed within the dmi rather than the cpu core itself. in normal operation isolated byte write transactions to the data memories result in no additional stall cycles. data scratchpad ram (dspr) the dspr of tricore 1.6 is protected from memory integrity errors on a per-halfword basis. the dspr is ecc protected, six ec c bits are required per half-word stored. uncorrectable memory integrity error detection in the dspr is enabled by setting miecon.dsmiee to one. when miecon.dsm iee is zero all uncorrectable memory integrity errors are ignored. error correction is enabled by setting the miecon2.dsmsece to one. when the miec on2.dsmsece is zero all errors are treated as uncorrectable. if a correctable error is detected during a memory read and error correction is enabled via the miecon2.dsmsece then the read data will be corrected and the ccpier.ccdie_u counter incremented to record the fact the an unresolved correctable data integrity error has been detected. (the error is considered unresolved as the memory itself is not updated with the corrected value). for data load requests from the tricore cpu to dspr, the ecc bits are read along with the data bits and an uncorrectable error signal is generated for each half-word. if an error is detected associated with any of the data half-words passed to the core an error is flagged to the core. if such an error condition is detected an asynchronous die trap is raised. the trap handler is then responsible for correcting the memory entry, or for taking alternative action (such as system soft reset) if correction of the data is not possible. for dspr read operations from the bus interf ace, either from the pmi module or another bus master agent, an a ccess that results in the detection of an uncorrectable error in the requested data half-words causes a bus error to be returned for the bus transaction. since the tricore cpu may not be involved in the transaction, a separate error is also flagged to the scu module to optionally generate an nmi trap back to the core. for write operations to dspr of half-word size or greater, the ecc bits are pre- calculated and written to the memory in parallel with the data bits. for byte write operations the memory transaction is trans formed into a half-wo rd read-modify-write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-17 v1.1, 2011-03 cpu, v1.0 sequence inside the dmi module. as such, byte write operations may result in the detection of uncorrectable memory integrity errors, which are handled as per standard read operations. data cache (dcache) the data cache stores six ecc bits per half-word. uncorrectable memory integrity error detection in the dcache is enabled by setting miecon.dcmiee to one. when miecon.dcmiee is zero all uncorrectable memory integrity errors are ignored. error correction is enabled by setting the miecon2.dcmsece to one. when the miecon2.dcmsece is zero all errors are treated as uncorrectable. if a correctable error is detected during a memory read and error correction is enabled via the miecon2.dcmsece then the read data will be corrected and the ccpier.ccdie_u counter incremented to record the fact the an unresolved correctable data integrity error has been detected. (the error is considered unresolved as the memory itself is not updated with the corrected value). for data load requests from the tricore cpu to dcache, the ecc bits are read along with the data bits of both cache ways, and an uncorrectable error flag computed for each half-word of each cache way. in the case where an error is detected with any of the requested data half-words in a cache way which has a corresponding tag hit, an error is flagged to the core. if such an error condition is detected an asynchronous die trap is raised. the trap handler is then responsible for correcting the memory entry, or for taking alternative action (such as system soft reset) if correction of the data is not possible. for write operations of half-word size or gr eater, the check bits are pre-calculated and written to the memory in parallel with the da ta bits. for byte write operations the memory transaction is transformed into a half-word read-modify-write sequence inside the dmi module. as such, byte write operations may result in the detection of uncorrectable memory integrity errors as for read operations. for cache line writeback, uncorrectable error detection is performed as dirty data is transferred to the store buffers. in all cases (normal cache line eviction, cachex.xx instruction) where an error condition is detected in a valid cache line a die trap is raised. the trap handler is then responsible for taking corrective action (such as system soft reset) since correction of the data is not possible. data tag (dtag) the data tag stores a 20-bit tag address for each cache way in a set. as such the data tags are written with 20-bit granularity an d six ecc bits are associated with each 20-bit tag address. uncorrectable memory integrity error detection in the dtag is enabled by setting miecon.dtmiee to one. when miecon.dtmiee is zero all uncorrectable memory integrity errors are ignored. error correction is enabled by setting the www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-18 v1.1, 2011-03 cpu, v1.0 miecon2.dtmsece to one. when the miecon2.dtmsece is zero all errors are treated as uncorrectable. if a correctable error is detected during a memory read and error correction is enabled via the mi econ2.dtmsece then t he read data will be corrected and the ccpier.ccdie_u counter incremented to record the fact the an unresolved correctable data integrity error has been detected. (the error is considered unresolved as the memory itself is not updated with the corrected value). for data load or store requests from the tricore cpu to dcache, the data tag ecc bits are read along with the data bits and an uncorrectable error flag is computed. a way hit is triggered only if the tag address comparison succeeds, the tag location is valid and no uncorrectable error in the associated tag way is detected, any other result is considered a miss. in the normal case where no error is detected in either tag way then the cache line is filled/refilled as normal. in the case of a cache miss where an error is detected in one of the tag ways and the cache line does not contain dirty data the cache controller replacement algorithm forces the way indica ting an error to be replaced when the refill operation returns. since such errors are ot herwise transparent to the tricore cpu, the ccdie_r counter is incremented to allow count ing of such error corrections if required. in the case where one cache way flags a cache hit, and the another way detects an uncorrectable error, the error condition is masked and has no effect on the memory integrity error handling mechanisms. if a cache miss occurs, with an uncorrectable error detected on the associated data tag way and dirty data detected, then an asynchronous die trap is signalled to the core and any writeback / refill sequence aborted. the trap handler is responsible for invalidating the cache line and processing any associated dirty data if possible, or taking other corrective action. similar action is taken for forced cache writeback using the cache manipulation instructions. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-19 v1.1, 2011-03 cpu, v1.0 2.5 cpu subsystem registers this section describes the implementation -specific features of the cpu subsystem registers listed in table 2-1 . for complete descriptions of all registers refer to the tricore architecture manual. table 2-1 cpu subsystem registers registers purpose description cpu core special function registers (csfrs) program state information, context and stack management, interrupt and trap control, system control see page 2-20 cpu general purpose registers (gprs) general purpose address and data registers see page 2-30 cpu memory protection registers (csfrs) memory protection control and mode selection see page 2-33 fpu registers (csfrs) support for the standard floating point instructions. see page 2-38 memory integrity registers (csfrs) integrity and protection core special function registers. see page 2-40 cpu slave interface (cps) registers software break control and software service request control see page 2-59 core debug registers (csfrs) debug control see page 2-62 implementation specific reset values reset values for cpu registers not defined in this chapter see page 2-65 program memory interface registers (pmi csfrs) pmi instruction cac he control, status and trap information see page 2-82 data memory interface registers (dmi csfrs) dmi data cache control, status and trap information see page 2-93 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-20 v1.1, 2011-03 cpu, v1.0 2.6 cpu core special function registers (csfr) figure 2-7 shows the csfr registers of the TC1798. figure 2-7 csfr registers table 2-2 core special function registers short name description offset address access mode reset value read write mmu_con mmu configuration register 8000 h u, sv, 32 sv, 32 class 3 reset 0000 8000 h pcxi previous context information register fe00 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h psw program status word register fe04 h u, sv, 32 sv, 32 class 3 reset 0000 0b80 h pc program counter register fe08 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h syscon system configuration register fe14 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpu_id cpu identification register fe18 h u, sv, 32 u, sv, 32, nc class 3 reset 00c0 c003 h biv interrupt vector table pointer register fe20 h u, sv, 32 sv, e, 32 class 3 reset 0000 0000 h btv trap vector table pointer register fe24 h u, sv, 32 sv, e, 32 class 3 reset a000 0100 h mca06073_1 program state information registers interrupt & trap control registers context management registers stack management registers isp system control registers compatibility register syscon mmu_con compat icr biv btv fcx lcx pc psw pcxi www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-21 v1.1, 2011-03 cpu, v1.0 isp interrupt stack pointer register fe28 h u, sv, 32 sv, e, 32 class 3 reset 0000 0100 h icr icu interrupt control register fe2c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h fcx free context list head pointer register fe38 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h lcx free context list limit pointer register fe3c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h pma0 physical memory attributes 801c h u, sv, 32 sv, e, 32 class 3 reset c000 03ff h compat compatibility control register 9400 h u, sv, 32 sv, e, 32 class 3 reset ffff ffff h table 2-2 core special function registers (cont?d) short name description offset address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-22 v1.1, 2011-03 cpu, v1.0 2.6.1 registers the implementation-specific program status word register (psw) is an extension of the psw description in the tricore architecture manual. the status flags used for fpu operations overlay the status flags used fo r arithmetic logic unit (alu) operations. program status word register note: the non-shaded areas in the register description define the implementation- specific bits/bit fields. the shaded areas are defined in the tricore architecture manual.] psw program status word register (f7e1 fe04 h ) reset value: 0000 0b80 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 c or fs v or fi sv or fv av or fz sav or fu fx rm 0 rwhrwhrwhrwhrwhrwh rw r 1514131211109876543210 0 prs io is gw cde cdc r rwh rwh rwh rwh rwh rwh field bits type description rm [25:24] rw fpu rounding mode selection fx 26 rwh fpu inexact flag sav 27 rh sticky advance overflow flag fu rwh fpu underflow flag av 28 rwh advance overflow flag fz fpu divide by zero flag sv 29 rwh sticky overflow flag fv fpu overflow flag v 30 rwh overflow flag fi fpu invalid operation flag c 31 rwh carry flag fs fpu some exception flag www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-23 v1.1, 2011-03 cpu, v1.0 interrupt cont rol register the interrupt control register (icr) is an implementation-specific cfsr. its arbitration cycle control implementation-specific details are defined in bits 24 to 26. note: the non-shaded areas in the register description define the implementation- specific bits/bit fields. the shaded areas are defined in the tricore architecture manual. icr interrupt control register (f7e1 fe2c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 c one cyc carbcyc pipn rrwrw rh 1514131211109876543210 0 ie ccpn r rwh rwh field bits type description carbcyc [25:24] rw number of arbitration cycles carbcyc controls the number of arbitration cycles used to determine the request with the highest priority. 00 b 4 arbitration cycles (default) 01 b 3 arbitration cycles 10 b 2 arbitration cycles 11 b 1 arbitration cycles conecyc 26 rw number of clocks per arbitration cycle control the conecyc bit determine s the number of system clocks per arbitration cycle. this bit should be set to 1 only for system designs ut ilizing low system clock frequencies. 0 b 2 clocks per arbitration cycle 1 b 1 clock per arbitration cycle www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-24 v1.1, 2011-03 cpu, v1.0 mmu configuration register the mmu configuration register (mmu_con) register indicates the non-availability of the tricore memory management unit (bit nommu is always set). note: to aid debug the tricore 1.6 im plements the mmu_asi register. note: the non-shaded areas in the register description define the implementation- specific bits/bit fields. the shaded areas are defined in the tricore architecture manual. mmu_con mmu configuration register (f7e1 8000 h ) reset value: 0000 8000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 no mmu 0 tsz szb sza v r r r rw rw rw field bits type description nommu 15 r mmu exists 0 b mmu is available. 1 b mmu is not available. all other bits of mmu_con are undefined. note: the mmu is not available in TC1798. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-25 v1.1, 2011-03 cpu, v1.0 address space identifi er register (mmu_asi) the memory management unit (mmu), address space identifier (asi) register description. mmu_asi address space identifier register (f7e1 8004 h ) reset value: 0000 001f h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res asi rrw field bits type description res [31:5] r reserved asi [4:0] rw address space identifier the asi register contains the address space identifier of the current process. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-26 v1.1, 2011-03 cpu, v1.0 cpu identification register cpu_id cpu identification register (f7e1 fe18 h ) reset value: 00c0 c003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mod_32b mod_rev r r field bits type description mod_rev [7:0] r revision number 03 h reset value mod_32b [15:8] r 32-bit module enable c0 h a value of c0 h in this field indicates a 32-bit module with a 32-bit module id register. mod [31:16] r module identifi cation number 00c0 h for module identification www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-27 v1.1, 2011-03 cpu, v1.0 physical memory attributes register the physical memory attributes pma0 register defines the physical memory attribute for each segment in the physical address space. the register is endinit protected and can be read with the mfcr instruction and written by the mtcr instruction. note that when changing the value of the pma0 register both the instruction and data caches should be invalidated, a dsync should be executed immediately prior to the mtcr with an isync instruction executed immediately following. this is required to maintain coherency of the processors view of memory. the physical memory attribute of a segment n in the physical address space, is defined by the bit field att[1:0][n]. for example, the segment f h has the physical attributes defined by bit field att[1:0][f h ]. this refers to bit 15 of the att[1][n] bit field, and bit 15 of the att[0][n] bit field; i.e. a value of 10 b . all segments are freely programmable with the following restrictions:- ? segment-f is constrained to be peripheral space ? segment-d is constrained to be either cacheable or non-cacheable memory. data fetches to the lower half segment and to the global address of the local data scratch memory are always non-cacheable irrespective of the programmed attributes. ? segment-c is constrained to be either cacheable or non-cacheable memory. code fetches to the lower half segment and to the global address of the local data scratch memory are always non-cacheable irrespective of the programmed attributes. ? segment-a is constrained to be non-cacheable memory note: this register is endinit protected. pma0 physical memory attributes (f7e1 801c h ) reset value: c000 03ff 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 att[ 1:0][ 15] att[ 1:0][ 14] att[ 1:0][ 13] att[ 1:0][ 12] att[ 1:0][ 11] att[ 1:0][ 10] att[1][n] r rw r r rw r rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 att[ 1:0][ 15] att[ 1:0][ 14] att[ 1:0][ 13] att[ 1:0][ 12 att[ 1:0][ 11] att[ 1:0][ 10] att[0][n] r rw rw rw rw r rw rw rw rw rw rw rw rw rw rw field bits type description att[1:0] [15] 31, 15 r segment f h physical memory attribute = 10 b . segment f h is constrained to always be peripheral space. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-28 v1.1, 2011-03 cpu, v1.0 att[1:0] [14] 30, 14 rw segment e h physical memory attribute. att[1:0] [13] 29, 13 rw segment d h physical memory attribute = 0x b . segment d h is constrained to never be peripheral space att[1:0] [12] 28, 12 rw segment c h physical memory attribute = 0x b . segment c h is constrained to never be peripheral space att[1:0] [11] 27, 11 rw segment b h physical memory attribute. att[1:0] [10] 26, 10 r segment a h physical memory attribute = 00 b . segment a h is constrained to be non-cached memory att[1:0] [9:0] [25:16], [9:0] rw segment 9 h - 0 h physical memory attributes. table 2-3 att[1:0][n] bit field encoding att[1:0][n] segment attributes 11 reserved. 10 peripheral space. 01 cacheable memory. 00 non-cacheable memory. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-29 v1.1, 2011-03 cpu, v1.0 compatibility control register the compatibility control register (compat) is an implementation-specific csfr which allows certain elements of backwards compatibility with tric ore 1.3.x behavior to be forced. the reset va lue of the compat re gister ensures that backwards compatibility with tricore 1.3 is enabled by default. compat compatibility control register (f7e1 9400 h ) reset value: ffff ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res int rm pro t res r rw rw rw r field bits type description res [1:0] r reserved read as 1; should be written with 1. prot 2rw range table to set mapping 0 b mapping enabled. 1 b fixed mapping (tc1.3 behavior). rm 3rw rounding mode compatibility 0 b psw.rm not restored by ret. 1 b psw.rm restored by ret (tc1.3 behavior). int 4r interrupt mode 0 b safe interrupt operation, software acknowledge 1 b standard interrupt operation, hardware acknowledge res [31:5] r reserved read as 1; should be written with 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-30 v1.1, 2011-03 cpu, v1.0 2.7 cpu general purpose registers figure 2-8 shows the general purpose registers (gprs) of the TC1798. figure 2-8 gpr registers table 2-4 gpr registers short name description offset address access mode reset read write d0 data register 0 ff00 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d1 data register 1 ff04 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d2 data register 2 ff08 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d3 data register 3 ff0c h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d4 data register 4 ff10 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h mca0607 5 a15 (implicit address) d15 (implicit data) address general purpose registers (agpr) data general purpose registers (dgpr) a14 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 e14 e12 e10 e8 e6 e4 e2 e0 64-bit extende d data register s a13 a12 a11 (return address) a10 (stack pointer) a9 (global address) a8 (global address) a7 a6 a5 a4 a3 a2 a1 (global address) a0 (global address) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-31 v1.1, 2011-03 cpu, v1.0 d5 data register 5 ff14 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d6 data register 6 ff18 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d7 data register 7 ff1c h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d8 data register 8 ff20 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d9 data register 9 ff24 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d10 data register 10 ff28 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d11 data register 11 ff2c h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d12 data register 12 ff30 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d13 data register 13 ff34 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d14 data register 14 ff38 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h d15 data register 15 ff3c h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a0 address register 0 (global address register) ff80 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a1 address register 1 (global address register) ff84 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a2 address register 2 ff88 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a3 address register 3 ff8c h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a4 address register 4 ff90 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h table 2-4 gpr registers (cont?d) short name description offset address access mode reset read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-32 v1.1, 2011-03 cpu, v1.0 a5 address register 5 ff94 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a6 address register 6 ff98 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a7 address register 7 ff9c h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a8 address register 8 (global address register) ffa0 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a9 address register 9 (global address register) ffa4 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a10 address register 10 (stack pointer) ffa8 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a11 address register 11 (return address) ffac h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a12 address register 12 ffb0 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a13 address register 13 ffb4 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a14 address register 14 ffb8 h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h a15 address register 15 ffbc h u, sv, 32 sv, 32 class 3 reset xxxx xxxx h table 2-4 gpr registers (cont?d) short name description offset address access mode reset read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-33 v1.1, 2011-03 cpu, v1.0 2.8 cpu memory protection registers there are four memory protection register sets in the TC1798. the sets specify memory protection ranges and permissions for code and data. the psw.prs bit field determines which of these sets is currentl y in use by the cpu. the tc1.6 implements 16 data and 8 code range comparators. thes e may be flexibly shared amongst the of protection sets to provide a maximum of 8 data ranges and four code ranges per set. the memory protection registers are core spec ial function registers, they are described in detail in the tricore architecture manual. table 2-5 memory protection registers short name description offset address access mode reset read write dpr0_0l data protection range 0.0, lower bound register c000 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr0_0u data protection range 0.0, upper bound register c004 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr0_1l data protection range 0.1, lower bound register c400 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr0_1u data protection range 0.1, upper bound register c404 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr1_0l data protection range 1.0, lower bound register c800 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr1_0u data protection range 1.0, upper bound register c804 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr1_1l data protection range 1.1, lower bound register cc00 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr1_1u data protection range 1.1, upper bound register cc04 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr2_0l data protection range 2.0, lower bound register c008 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr2_0u data protection range 2.0, upper bound register c00c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr2_1l data protection range 2.1, lower bound register c408 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr2_1u data protection range 2.1, upper bound register c40c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-34 v1.1, 2011-03 cpu, v1.0 dpr3_0l data protection range 3.0, lower bound register c808 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr3_0u data protection range 3.0, upper bound register c80c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr3_1l data protection range 3.1, lower bound register cc08 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr3_1u data protection range 3.1, upper bound register cc0c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr4_0l data protection range 4.0, lower bound register c010 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr4_0u data protection range 4.0, upper bound register c014 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr4_1l data protection range 4.1, lower bound register c410 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr4_1u data protection range 4.1, upper bound register c414 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr5_0l data protection range 5.0, lower bound register c810 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr5_0u data protection range 5.0, upper bound register c814 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr5_1l data protection range 5.1, lower bound register cc10 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr5_1u data protection range 5.1, upper bound register cc14 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr6_0l data protection range 6.0, lower bound register c018 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr6_0u data protection range 6.0, upper bound register c01c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr6_1l data protection range 6.1, lower bound register c418 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr6_1u data protection range 6.1, upper bound register c41c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h table 2-5 memory protection registers (cont?d) short name description offset address access mode reset read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-35 v1.1, 2011-03 cpu, v1.0 dpr7_0l data protection range 7.0, lower bound register c818 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr7_0u data protection range 7.0, upper bound register c81c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr7_1l data protection range 7.1, lower bound register cc18 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dpr7_1u data protection range 7.1, upper bound register cc1c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr0_0l code protection range 0.0, lower bound register d000 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr0_0u code protection range 0.0, upper bound register d004 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr0_1l code protection range 0.1, lower bound register d400 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr0_1u code protection range 0.1, upper bound register d404 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr1_0l code protection range 1.0, lower bound register d800 u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr1_0u code protection range 1.0, upper bound register d804 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr1_1l code protection range 1.1, lower bound register dc00 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr1_1u code protection range 1.1, upper bound register dc04 u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr2_0l code protection range 2.0, lower bound register d008 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr2_0u code protection range 2.0, upper bound register d00c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr2_1l code protection range 2.1, lower bound register d408 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr2_1u code protection range 2.1, upper bound register d40c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h table 2-5 memory protection registers (cont?d) short name description offset address access mode reset read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-36 v1.1, 2011-03 cpu, v1.0 cpr3_0l code protection range 3.0, lower bound register d808 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr3_0u code protection range 3.0, upper bound register d80c u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr3_1l code protection range 3.1, lower bound register dc08 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpr3_1u code protection range 3.1, upper bound register dc0c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dps0 data protection set configuration register 0 e000 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dps1 data protection set configuration register 1 e080 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dps2 data protection set configuration register 2 e100 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h dps3 data protection set configuration register 3 e180 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cps0 code protection set configuration register 0 e200 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cps1 code protection set configuration register 1 e280 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cps2 code protection set configuration register 2 e300 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cps3 code protection set configuration register 3 e380 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h table 2-5 memory protection registers (cont?d) short name description offset address access mode reset read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-37 v1.1, 2011-03 cpu, v1.0 2.9 temporal protection registers to guard against task runtime overrun the tricore1.6 implements a temporal protection system. this system consists of two independent decrementing counters arranged to generate a temporal asynchronous error trap (tae - class-4, tin-7) on decrement to zero. the temporal protection registers are core special function registers, they are described in detail in the tricore architecture manual. table 2-6 temporal protection system registers short name description offset address access mode reset read write tps_con tps contro l register e400 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h tps_timer0 tps timer 0 register e404 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h tps_timer1 tps timer 1 register e408 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-38 v1.1, 2011-03 cpu, v1.0 2.10 fpu registers a number of fpu special function regist ers (csfrs) have been introduced to the tricore 1.6 architecture in order to fully support functional enhancements. figure 2-9 tricore 1.6 csfr registers table 2-7 floating point special function registers short name description offset address access mode reset read write fpu_trap _con trap control register a000 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h fpu_trap _pc trapping instruction program counter register a004 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h fpu_trap _opc trapping instruction opcode register a008 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h fpu_trap _src1 trapping instruction operand register a010 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h fpu_trap _src2 trapping instruction operand register a014 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h fpu_trap _src3 trapping instruction operand register a018 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h fpu_id trapping identification register a020 h u, sv, 32 sv, 32 class 3 reset 00c2 c003 h fpu trap registers fpu_trap_con fpu_trap_pc fpu_trap_opc fpu_trap_srcn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-39 v1.1, 2011-03 cpu, v1.0 2.10.1 registers fpu identifica tion register fpu_id trapping identification register (f7e1 a020 h ) reset value: 00c2 c003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mod_32b mod_rev r r field bits type description mod_rev [7:0] r revision number 03 h reset value mod_32b [15:8] r 32-bit module enable c0 h a value of c0 h in this field indicates a 32-bit module with a 32-bit module id register. mod [31:16] r module identifi cation number 00c2 h for module identification. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-40 v1.1, 2011-03 cpu, v1.0 2.11 memory integrity registers to monitor and debug the integrit y of the memory subsystems the following registers are introduced. figure 2-10 tricore 1.6 csfr registers table 2-8 memory integrity registers short name description offset address access mode reset read write miecon memory integrity error control register 9044 h u, sv, 32 sv, e, 32 class 3 reset 0000 0000 h miecon2 memory integrity error control register 2 9048 h u, sv, 32 sv, e, 32 class 3 reset 0000 0000 h ccpier count of corrected program integrity errors register 9218 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h ccdier count of corrected data integrity errors register 9028 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h piear program integrity error address register 9210 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h pietr program integrity error trap register 9214 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h diear data integrit y error address register 9020 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h mca06073-3 miecon integrity registers ccpier ccdier piear pietr diear dietr smacon www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-41 v1.1, 2011-03 cpu, v1.0 dietr data integrity error trap register 9024 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h smacon sist mode access control register 900c h u, sv, 32 sv, e, 32 class 3 reset 0000 0000 h table 2-8 memory (cont?d) integrity registers short name description offset address access mode reset read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-42 v1.1, 2011-03 cpu, v1.0 2.11.1 register descriptions memory integrity error control register the memory integrity error co ntrol register (miecon) allows software to control the handling of uncorrectable memory integrity errors. miecon memory integrity error control register (f7e1 9044 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res ptie e res dtie e r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res pbm iee pcm iee psmi ee res dcm iee dsm iee r rw rw rw r rw rw field bits type description dsmiee 0rw data scratch memory integrity error enable enables handling of uncorrect able integrit y errors for the dspr memories. 0 b uncorrectable integrity error handling disabled - all memory accesses interpreted as error free. 1 b uncorrectable integrity error handling enabled. dcmiee 1rw data cache memory integrity error enable enables handling of uncorrect able integrit y errors for the data cache memories. 0 b uncorrectable integrity error handling disabled - all memory accesses interpreted as error free. 1 b uncorrectable integrity error handling enabled. res [7:2] r reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-43 v1.1, 2011-03 cpu, v1.0 psmiee 8rw program scratch memory integrity error enable enables handling of uncorrect able integrit y errors for the program scratch memories. 0 b uncorrectable integrity error handling disabled - all memory accesses interpreted as error free. 1 b uncorrectable integrity error handling enabled. pcmiee 9rw program cache memory integrity error enable enables handling of uncorrect able integrit y errors for the program cache memories. 0 b uncorrectable integrity error handling disabled - all memory accesses interpreted as error free. 1 b uncorrectable integrity error handling enabled. pbmiee 10 rw program bus memory integrity error enable enables handling of uncorrect able integrit y errors for instructions fetched directly from the bus system. 0 b uncorrectable integrity error handling disabled - all memory accesses interpreted as error free. 1 b uncorrectable integrity error handling enabled. res [15:11] r reserved dtiee 16 rw data tag integrity error enable enables handling of uncorrect able integrit y errors for the data tag. 0 b uncorrectable integrity error handling disabled - all memory accesses interpreted as error free. 1 b uncorrectable integrity error handling enabled. res 17 r reserved ptiee 18 rw program tag integr ity error enable enables handling of uncorrect able integrit y errors for the program tag. 0 b uncorrectable integrity error handling disabled - all memory accesses interpreted as error free. 1 b uncorrectable integrity error handling enabled. res [31:19] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-44 v1.1, 2011-03 cpu, v1.0 memory integrity erro r control register 2 the memory integrity error c ontrol register 2 (miecon2) allows software to control the handling of correctable memory integrity errors. miecon2 memory integrity erro r control register 2 (f7e1 9048 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res pts ece res dts ece r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res pbm sec e pcm sec e psm sec e res dcm sec e dsm sec e r rw rw rw r rw rw field bits type description dsmsece 0rw data scratch memory si ngle error correction enable enables single bit error correction for the dspr memories. dcmsece 1rw data cache memory single error correction enable enables single bit error correction for the data cache memories. res [7:2] r reserved psmsece 8rw program scratch memory single error correction enable enables single bit error correction for the program memories. pcmsece 9rw program cache memory si ngle error correction enable enables single bit error correction for the program memories. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-45 v1.1, 2011-03 cpu, v1.0 function although the xxiee and xxsece bits for a given memory type exist in different registers (miecon and miecon2 respectively) due to different protection requirements for these csfr bits, the bits interact to perform the following general functions. pbmsece 10 rw program bus memory single error correction enable enables single bit error corre ction for the instructions fetched directly from the bus system. res [15:11] r reserved dtsece 16 rw data tag single error correction enable enables single bit error correction for the data tag res 17 r reserved ptsece 18 rw program tag single e rror correction enable enables single bit error correction for the program tag. res [31:19] r reserved read as 0; should be written with 0. table 2-9 functions xxsece xxiee description 00 no memory integrity handling all single and double-bit memory integrity errors ignored. 01 error detection mode single and double-bit errors treated as uncorrectable errors. 10 sec only mode single-bit errors corrected by ecc, double-bit errors ignored 11 secded mode single-bit errors corrected by ecc, double-bit errors treated as uncorrectable errors. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-46 v1.1, 2011-03 cpu, v1.0 program integrity error information registers two architecturally visible registers (pietr, piear) allow software to localise the source of the last detected uncorrectable program memory integrity error. these registers are updated when an uncorrectable program integrity error condition is detected and the pietr.ied bit is zero. on update the pietr.ied bit is set to one and remains set until cleared by software. whilst pietr.ied is set further hardware updates of pietr and piear are inhibited. pietr and piear are updated on any uncorrectable program memory integrity error condition detected, either during a bus access or a cpu instruction pre-fetch. since instruction pre-fetches are speculative, the pietr and piear registers may be updated without a corresponding pie trap. the program integrity error trap register (pietr) contains flags to support software in localising the source of the last detected uncorrectable program memory integrity error. where an uncorrectable integrity error condition is detected during an instruction pre- fetch, the ie_s, ie_c and ie_t bits are updated to denote in which memory structure the error was detected, whilst bus_id and ie_b are cleared. where the error is detected during an external bus access to a core memory, ie_b is set and bus_id updated to denote the master tag id of the initiating bus master, whilst ie_s, ie_c and ie_t are cleared. if the error detected in the address the ie_addr bit is set. if the error detected is a dual bit error the ie_dual bit is set. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-47 v1.1, 2011-03 cpu, v1.0 program integrity error trap register (pietr) pietr program integrity error trap register (f7e1 9214 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res ie_d ual ie_a ddr res e_info ie_b ie_s ie_c ie_t ied r rh rh r rh rh rh rh rh rwh field bits type description ied 0rwh integrity error detected read operation: 0 b no program integrity error condition occurred. 1 b program integrity error condition detected. pietr and piear contents valid, further pietr and piear updates disabled. write operation: 0 b clear ied bit, re-enable pietr and piear updates. 1 b no effect. ie_t 1rh integrity error - tag memory ie_c 2rh integrity error - cache memory ie_s 3rh integrity error - scratchpad memory ie_b 4rh integrity error - bus access e_info [8:5] rh error information if ie_b = 1 : bus master tag id of requesting master if ie_c = 1 : cache way . res 9r reserved read as 0; should be written with 0. ie_addr 10 r integrity error - address error detected ie_dual 11 r integrity error - dual error detected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-48 v1.1, 2011-03 cpu, v1.0 res [31:12] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-49 v1.1, 2011-03 cpu, v1.0 program integrity error address register this register contains the physical address accessed by the operation that encountered a uncorrectable program memory integrity error. this register is only updated if pietr.ied is zero. piear program integrity error address register (f7e1 9210 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ta rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta rh field bits type description ta [31:0] rh transaction address physical address being accessed by operation that encountered program integrity error. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-50 v1.1, 2011-03 cpu, v1.0 data integrity error information registers two architecturally visible registers (dietr , diear) allow software to localise the source of the last detected uncorrectable dat a memory integrity error. these registers are updated when an uncorrectable data integrity error condition is detected and the dietr.ied bit is zero. on update the dietr.ied bit is set to one and remains set until cleared by software. whilst dietr.ied is set further hardware updates of dietr and diear are inhibited. the data integrity error trap register (dietr) contains flags to support software in localising the source of the last detected uncorrectable data memory integrity error. where an uncorrectable data memory integrity error condition is detected during a cpu load/store access, the ie_s, ie_c, ie_t and e_info fields are updated to denote where the error was detected and the nature of the die trap. whilst bus_id and ie_b are cleared. where the error is detected during an external bus access to a core memory the ie_b is set and e_info updated to denote the master tag id of the initiating bus master, whilst ie_s, ie_c, ie_t are cleared. whether a single or dual error is detected is indicated by the ie_dual bit. when a data integrity error is detected which causes an update of the die information registers and results in an asynchronous die trap the ied bit is set and further asynchronous die traps are disabled until dietr.ied is cleared by software. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-51 v1.1, 2011-03 cpu, v1.0 data integrity error trap register (dietr) dietr data integrity error trap register (f7e1 9024 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res ie_d ual res e_info ie_b ie_s ie_c ie_t ied r rh rh rh rh rh rh rh rwh field bits type description ied 0rwh integrity error detected read operation: 0 b no data integrity error condition occurred. 1 b data integrity error condition detected. dietr and diear contents valid, further dietr and diear updates disabled. write operation: 0 b clear ied bit, re-enable dietr and diear update. 1 b no effect. ie_t 1rh integrity error - tag memory ie_c 2rh integrity error - cache memory ie_s 3rh integrity error - scratchpad memory ie_b 4rh integrity error - bus access e_info [8:5] rh error information if ie_b = 1 : bus master tag id of requesting master if ie_c = 1 : cache way. res [10:9] r reserved read as 0; should be written with 0. ie_dual 11 rh ie_dual dual bit error detected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-52 v1.1, 2011-03 cpu, v1.0 res [31:12] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-53 v1.1, 2011-03 cpu, v1.0 data integrity error address register this register contains the physical address accessed by the operation that encountered a uncorrectable data memory integrity error. this register is only updated if dietr.ied is zero. diear data integrity error address register (f7e1 9020 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ta rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta rh field bits type description ta [31:0] rh transaction address physical address being accessed by operation that encountered data integrity error. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-54 v1.1, 2011-03 cpu, v1.0 sist (software in-system) test support the tricore 1.6 core protects against memory integrity errors by ecc protection of the on-core memories. this has the side-effect of requiring memory blocks wider than the normal data access path to the memory. the additional ecc storage bits are not easily accessible via the existing data paths, causing problems where sist based testing of the memories is required. the tricore 1.6 core also includes embedded memory arrays, such as the tag memories, which are not ordinarily accessible by the usual cpu datapaths. in order to address this problem , the tricore 1.6 core includes improved sist support, allowing all on-core memory arrays to be accessed, both as a backup for mbist based memory test and to allow the test and debug of the new fault tolerant memory systems. the mapping of embedded memory arrays into the tricore address space and the enabling of other sist related features is controlled by the setting of bits within the sist mode access control register (smacon). the embedded memory arrays are mapped into the program and data scratch areas (segments c h and d h ) of the address map by setting bits in the smacon register. program side embedded memories are mapped into the pspr area and located in the address range c01c0000 h - c01fffff h .data side embedded memories are mapped into the dspr area and located in the address range d01c0000 h - d01fffff h . a memory that has been mapped into the scratch memory area using the smacon register may not be accessed in its normal operational mode. in general no bits of the smacon register should be set during normal operation. the only exception to this is the mapping of cache to sram in hard real time systems in which cache operation is not desired. in such systems the cache memories may be mapped to sram for normal operation by setting the smacon.pc and/or the smacon.dc bits to ?11?. note: when the flash read protection (otp protec tion) mechanism is active, the value of smacon.pc is overridden and treated as 00 b 'normal operating mode'; however the field can still be read and written normally. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-55 v1.1, 2011-03 cpu, v1.0 sist mode access control register smacon sist mode access control register (f7e1 900c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res iodt res r rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res ds dt dc 0 ps pt pc r rw rw rw r rw rw rw field bits type description pc [1:0] rw instruction cache memory sist mode access control note: when the flash read protection mechanism is active, the value of smacon.pc is overridden and treated as 00 b 'normal operating mode'; however the field can still be read and written normally. 00 b normal operation, no mapping. 01 b data array mapping, no error detection/correction. 10 b check array mapping, no error detection/correction. 11 b data array mapping, error detection/correction enabled. pt [3:2] rw program tag memory sist mode access control 00 b normal operation, no mapping. 01 b data array mapping, no error detection/correction. 10 b check array mapping, no error detection/correction. 11 b reserved. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-56 v1.1, 2011-03 cpu, v1.0 ps [5:4] rw program scratch memory sist mode access control 00 b normal operation, no mapping. 01 b data array mapping, no error detection/correction. 10 b check array mapping, no error detection/correction. 11 b data array mapping, error detection/correction enabled. res [7:6] r reserved read as 0; should be written with 0. dc [9:8] rw data cache memory sist mode access control 00 b normal operation, no mapping. 01 b data array mapping, no error detection/correction. 10 b check array mapping, no error detection/correction. 11 b data array mapping, error detection/correction enabled. dt [11:10] rw data tag memory sist mode access control 00 b normal operation, no mapping. 01 b data array mapping, no error detection/correction. 10 b check array mapping, no error detection/correction. 11 b reserved. ds [13:12] rw data scratch memory sist mode access control 00 b normal operation, no mapping, performance optimised. 01 b data array mapping, no error detection/correction. 10 b check array mapping, no error detection/correction. 11 b data array mapping, error detection/correction enabled. res [23:14] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-57 v1.1, 2011-03 cpu, v1.0 iodt 24 rw in-order data transactions 0 b normal operation, non-dependent loads bypass stores. 1 b in-order operation, loads always flush preceding stores, processor store buffer disabled. res [31:25] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-58 v1.1, 2011-03 cpu, v1.0 control fields the control fields within the smacon register allow individual control of the local memories. each memory may be mapped to operate in a number of different modes. normal operation, no mapping no mapping of the memories is performed and normal operation is possible. embedded memories not usually directly addressable are not accessible in the system address map. performance optimisations are enabled su ch that loads may read from the physical memory or associated write buffers. data array mapping, no error detection/correction the data array (only) of the memory is made visible in the address map. writes to the memory will not affect the check bits. e rror correction/detection for the memory is disabled. performance optimisations are di sabled such that memory accesses are guaranteed to be performed to the actual memory. check array mapping, no error detection/correction the check bit array (only) of the memory is made visible in the address map. writes to the memory will not affect the data bits. error correction/detection for the memory is disabled. performance optimisations are di sabled such that memory accesses are guaranteed to be performed to the actual memory. data array mapping, error detection/correction enabled the data array of the memory is made visible in the address map. writes to the memory will update the check bits as per normal operation. error correction/detection for the memory is enabled. performance optimisations are disabled such that memory accesses are guaranteed to be performed to the actual memory. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-59 v1.1, 2011-03 cpu, v1.0 2.12 cpu slave interface (cps) registers the cpu slave interface (cps) of the tricore cpu directly accesses the interrupt service request registers in the cpu from th e system peripheral bus. the cps registers are described in detail in the tricore architecture manual. figure 2-11 cps registers note: the registers cpu_sbsrc and cpu_src[3:0] are not bit-addressable. table 2-10 cps registers short name description offset address access mode reset read write cpu_sbsrc cpu software breakpoint service request control register ffbc h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpu_src3 cpu service request control 3 register fff0 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpu_src2 cpu service request control 2 register fff4 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpu_src1 cpu service request control 1 register fff8 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h cpu_src0 cpu service request control 0 register fffc h u, sv, 32 sv, 32 class 3 reset 0000 0000 h mca06074 cpu_sbsrc software breakpoint service request control register cpu service request contro l registers (n = 0-3) cpu_srcn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-60 v1.1, 2011-03 cpu, v1.0 2.12.1 register descriptions this registers have a specific implementati on detail, the type of service control (tos) bit/bit field. cpu service request control register note: the non-shaded areas in the register description define the implementation- specific bits/bit fields. the shaded areas are defined in the tricore architecture manual. cpu_srcn (n = 0-3) cpu service request control register n (f7e0 fffc h -n*4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre res tos 0 srpn w w rh rw r rw r rw field bits type description tos 10 rw type of service control 0 b service provider = cpu 1 b service provider = pcp2 res 11 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-61 v1.1, 2011-03 cpu, v1.0 cpu software breakpoint service request control register note: the non-shaded areas in the register description define the implementation- specific bits/bit fields. the shaded areas are defined in the tricore architecture manual. cpu_sbsrc cpu software breakpoint service request control register (f7e0 ffbc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre res tos 0 srpn w w rh rw r rw r rw field bits type description tos 10 rw type of service control 0 b service provider = cpu 1 b reserved res 11 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-62 v1.1, 2011-03 cpu, v1.0 2.13 core debug and performance counter registers the core debug and performance counter re gisters are available for debug purposes. for a complete description of all registers, refer to the tricore architecture manual. figure 2-12 core debug registers table 2-11 core debug and performance counter registers short name description offset address access mode reset read write cctrl counter control register fc00 h u, sv, 32 sv, 32 class 1 reset 0000 0000 h ccnt cpu clock count register fc04 h u, sv, 32 sv, 32 class 1 reset 0000 0000 h icnt instruction count register fc08 h u, sv, 32 sv, 32 class 1 reset 0000 0000 h m1cnt multi-count register 1 fc0c h u, sv, 32 sv, 32 class 1 reset 0000 0000 h m2cnt multi-count register 2 fc10 h u, sv, 32 sv, 32 class 1 reset 0000 0000 h m3cnt multi-count register 3 fc14 h u, sv, 32 sv, 32 class 1 reset 0000 0000 h dbgsr debug status register fd00 h u, sv, 32 sv, 32 debug reset 0000 0000 h mca06076-1 dbgsr core debug registers exevt crevt swevt tr0evt tr1evt dms dcx cpu_sbsrc dbgtcr cctrl performance counter registers ccnt icnt m1cnt m2cnt m3cnt www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-63 v1.1, 2011-03 cpu, v1.0 exevt external event register fd08 h u, sv, 32 sv, 32 debug reset 0000 0000 h crevt core register access event register fd0c h u, sv, 32 sv, 32 debug reset 0000 0000 h swevt software debug event register fd10 h u, sv, 32 sv, 32 debug reset 0000 0000 h dms debug monitor start address register fd40 h u, sv, 32 sv, 32 debug reset a000 0200 h dcx debug context save area pointer register fd44 h u, sv, 32 sv, 32 debug reset a000 0400 h cpu_sbsr c0 central processing unit software breakpoint service request control 0 register ffbc h u, sv, 32 sv, 32 debug reset 0000 0000 h tr0evt trigger event 0 configuration register f000 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr0adr trigger event 0 address register f004 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr1evt trigger event 1 configuration register f008 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr1adr trigger event 1 address register f00c h u, sv, 32 sv, 32 debug reset 0000 0000 h tr2evt trigger event 2 configuration register f010 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr2adr trigger event 2 address register f014 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr3evt trigger event 3 configuration register f018 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr3adr trigger event 3 address register f01c h u, sv, 32 sv, 32 debug reset 0000 0000 h tr4evt trigger event 4 configuration register f020 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr4adr trigger event 4 address register f024 h u, sv, 32 sv, 32 debug reset 0000 0000 h table 2-11 core debug and performance counter registers (cont?d) short name description offset address access mode reset read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-64 v1.1, 2011-03 cpu, v1.0 tr5evt trigger event 5 configuration register f028 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr5adr trigger event 5 address register f02c h u, sv, 32 sv, 32 debug reset 0000 0000 h tr6evt trigger event 6 configuration register f030 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr6adr trigger event 6 address register f034 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr7evt trigger event 7 configuration register f038 h u, sv, 32 sv, 32 debug reset 0000 0000 h tr7adr trigger event 7 address register f03c h u, sv, 32 sv, 32 debug reset 0000 0000 h table 2-11 core debug and performance counter registers (cont?d) short name description offset address access mode reset read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-65 v1.1, 2011-03 cpu, v1.0 2.14 implementation specific reset values this section summarizes the im plementation specific reset values of the cpu registers not defined in this chapter. table 2-12 implementation specific reset values register address reset value pcxi f7e1 fe00 h 0000 0000 h cpu_id f7e1 fe18 h 00c0 c003 h fcx f7e1 fe38 h 0000 0000 h lcx f7e1 fe3c h 0000 0000 h compat f7e1 9400 h ffff ffff h isp f7e1 fe28 h 0000 0100 h biv f7e1 fe20 h 0000 0000 h btv f7e1 fe24 h a000 0100 h fpu_id f7e1 a020 h 00c2 c003 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-66 v1.1, 2011-03 cpu, v1.0 2.15 cpu instruction timing this section gives information on cpu instruction timing by execution unit. the integer pipeline and load/store pipeline are always present, and the floating point unit (fpu) is optional. the load/store unit implements the optional tlb instructions. definition of terms: ? repeat rate assuming the same instruction is being issued sequentially, repeat is the minimum number of clock cycles between two consecut ive issues. there may be additional delays described elsewhere due to internal pipeline effects when issuing a different subsequent instruction. ? result latency the number of clock cycles fr om the cycle when the instruct ion is issued to the cycle when the result value is available to be used as an operand to a subsequent instruction or written into a gpr. result latency is not meaningful for instructions that do not write a value into a gpr. ? address latency the number of clocks cycles fr om the cycle when the instruct ion is issued to the cycle when the addressing mode updated value is available as an operand to a subsequent instruction or written into an address register. ? flow latency the number of clock cycles fr om the cycle when the instruct ion is issued to the cycle when the next instruction (located at the target location or the next sequential instruction if the control change is conditional) is issued. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-67 v1.1, 2011-03 cpu, v1.0 2.15.1 integer-pipeline instructions these are the integer-pipeline instruction timings for each instruction. 2.15.1.1 simple arithmetic instruction timings each instruction is single issued. table 2-13 simple arithmetic instruction timing instruction result latency repeat rate instruction result latency repeat rate integer pipeline arithmetic instructions abs 11 max.h 11 abs.b 11 max.hu 11 abs.h 11 max.u 11 absdif 11 min 11 absdif.b 11 min.b 11 absdif.h 11 min.bu 11 absdifs 21 min.h 11 absdifs.h 21 min.hu 11 abss 21 min.u 11 abss.h 21 rsub 11 add 11 rsubs 21 add.b 11 rsubs.u 21 add.h 11 sat.b 11 addc 11 sat.bu 11 addi 11 sat.h 11 addih 11 sat.hu 11 adds 21 sel 11 adds.h 21 seln 11 adds.hu 21 sub 11 adds.u 21 sub.b 11 addx 11 sub.h 11 cadd 11 subc 11 caddn 11 subs 21 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-68 v1.1, 2011-03 cpu, v1.0 csub 11 subs.h 21 csubn 11 subs.hu 21 max 11 subs.u 21 max.b 11 subx 11 max.bu 11 compare instructions eq 11 lt.b 11 eq.b 11 lt.bu 11 eq.h 11 lt.h 11 eq.w 11 lt.hu 11 eqany.b 11 lt.u 11 eqany.h 11 lt.w 11 ge 11 lt.wu 11 ge.u 11 ne 11 lt 11 count instructions clo 11 cls.h 11 clo.h 11 clz 11 cls 11 clz.h 11 extract instructions dextr 21 ins.t 11 extr 21 insn.t 11 extr.u 21 insert 21 imask 21 logical instructions and 11 or.eq 11 and.and.t 11 or.ge 11 and.andn.t 11 or.ge.u 11 and.eq 11 or.lt 11 and.ge 11 or.lt.u 11 table 2-13 simple arithmetic instruction timing (cont?d) instruction result latency repeat rate instruction result latency repeat rate www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-69 v1.1, 2011-03 cpu, v1.0 and.ge.u 11 or.ne 11 and.lt 11 or.nor.t 11 and.lt.u 11 or.or.t 11 and.ne 11 or.t 11 and.nor.t 11 orn 11 and.or.t 11 orn.t 11 and.t 11 xnor 11 andn 11 xnor.t 11 andn.t 11 xor 11 nand 11 xor.eq 11 nand.t 11 xor.ge 11 nor 11 xor.ge.u 11 nor.t 11 xor.lt 11 or 11 xor.lt.u 11 or.and.t 11 xor.ne 11 or.andn.t 11 xor.t 11 move instructions cmov 11 mov.u 11 cmovn 11 movh 11 mov 11 shift instructions sh 11 sh.ne 11 sh.and.t 11 sh.nor.t 11 sh.andn.t 11 sh.or.t 11 sh.eq 11 sh.orn.t 11 sh.ge 11 sh.xnor.t 11 sh.ge.u 11 sh.xor.t 11 sh.h 11 sha 11 sh.lt 11 sha.h 11 sh.lt.u 11 shas 21 table 2-13 simple arithmetic instruction timing (cont?d) instruction result latency repeat rate instruction result latency repeat rate www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-70 v1.1, 2011-03 cpu, v1.0 the latency and repeat rate values listed for the div and div.u instructions are the minimum and maximum values.the algorithm used allows for early termination of the instruction once the full result is available. sh.nand.t 11 coprocessor 0 instructions bmerge 21 ixmin 21 bsplit 21 unpack 21 parity 21 ixmax 21 pack 21 ixmax.u 21 ixmin.u 21 integer divide instructions dvadj 21 dvstep 64 dvinit 21 dvstep.u 64 dvinit.u 21 div 4-11 3-9 dvinit.b 21 div.u 4-11 3-9 dvinit.h 21 dvinit.bu 21 dvinit.hu 21 table 2-13 simple arithmetic instruction timing (cont?d) instruction result latency repeat rate instruction result latency repeat rate www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-71 v1.1, 2011-03 cpu, v1.0 2.15.1.2 multiply instruction timings each instruction is single issued. table 2-14 multiply instruction timing instruction result latency repeat rate instruction result latency repeat rate mul 21 mul.q 31 mul.u 21 mulm.h 31 muls 31 mulr.h 31 muls.u 31 mulr.q 31 mul.h 31 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-72 v1.1, 2011-03 cpu, v1.0 2.15.1.3 multiply accumulate (mac) instruction timing each instruction is single issued. for all madd, msub and mul type instructions the result latency is reduced to 1 for accumulator forwarding between similar instructions. table 2-15 multiply accumulate instruction timing instruction result latency repeat rate instruction result latency repeat rate madd 31 msub 31 madd.u 31 msub.u 31 madds 31 msubs 31 madds.u 31 msubs.u 31 madd.h 31 msub.h 31 madd.q 31 msub.q 31 maddm.h 31 msubm.h 31 maddms.h 31 msubms.h 31 maddr.h 31 msubr.h 31 maddr.q 31 msubr.q 31 maddrs.h 31 msubrs.h 31 maddrs.q 31 msubrs.q 31 madds.h 31 msubs.h 31 madds.q 31 msubs.q 31 maddsu.h 31 msubad.h 31 maddsum.h 31 msubadm.h 31 maddsums.h 31 msubadms.h 31 maddsur.h 31 msubadr.h 31 maddsurs.h 31 msubadrs.h 31 maddsus.h 31 msubads.h 31 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-73 v1.1, 2011-03 cpu, v1.0 for madd.q, madds.q, msub.q, msubs.q instructions: 2.15.1.4 control flow instruction timing control flow instruction timing for tricore1.6 is complicated by the use of branch target buffers and fetch fifos. ? incorrectly predicted ls instructions incur a three cycle branch recovery penalty. ? incorrectly predicted ip instructions in cur a four cycle branch recovery penalty. ? correctly predicted not taken breaches incur no penalty ? correctly predicted taken branch incur a penalty of up to two cycles depending on the state of the fetch fifos and the branch target buffer. ? loop instructions incur the same penalty as an ls conditional jump instruction. assumptions ? all target locations yield a full instruction in one access (i.e. not 16-bits of a 32-bit instruction). ? all code fetches take a single cycle. ? timing is best case; no cache misses for context operations, no pending stores. madd.q, madds.q, msub.q, msubs.q result latency repeat rate 16 16 3 1 16 32 3 1 32 32 3 1 table 2-16 control flow timing prediction-result flow latency (ls, lp) repeat rate (ls,lp) flow latency (ip) repeat rate (ip) correct not-taken 1 1 1 1 correct taken 1-2 1-2 1-2 1-2 incorrect not-taken 3 4 3 4 incorrect taken 3 4 3 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-74 v1.1, 2011-03 cpu, v1.0 2.15.2 load-store pipeline instructions this section summarizes the load-store pipeline instructions. 2.15.2.1 address arithmetic timing each instruction is single issued. table 2-17 address arithmetic instruction timing instruction result latency repeat rate instruction result latency repeat rate load store arithmetic instructions add.a 11 ge.a 11 addih.a 11 lt.a 11 addsc.a 21 ne.a 11 addsc.at 21 nez.a 11 eq.a 11 sub.a 11 eqz.a 11 nop 11 trap and interrupt instructions debug ?1 trapsv 1) 1) execution cycles when no trap is taken. the execution ti ming in the case of raising these traps is the same as other traps such as syscall. ?1 disable ?1 trapv 1) ?1 enable ?1 rstv ?1 restore ?1 move instructions mfcr 21 mov.a 11 mtcr 11 mov.aa 11 movh.a 11 mov.d 11 sync instructions dsync 2) 2) repeat rate assumes that no shadow register writeback is pending, otherwise the repeat rate will depend upon the time for all delayed memory operation to occur. ?1 isync 3) 3) repeat rate assumes that code refetch takes a single cycle. ?1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-75 v1.1, 2011-03 cpu, v1.0 2.15.2.2 csa control flow instruction timing this section summarizes the timing of csa control flow instructions. ? all targets yield a full instruction in one access (not 16-bits of a 32-bit instruction). ? all code fetches take a single cycle. timing is best case; no cache misses for context operations, no pending stores. access to dspr require 4 cycles, accesses to cached external memory require 8 cycles. 2.15.2.3 load instruction timing load instructions can produce two results if they use the pre-increment, post-increment, circular or bit-reverse addressing modes. hence, in those cases there are two latencies that must be specified, the result latency for the value loaded from memory and the address latency for using the updated address register result. ? each instruction is single issued. ? the memory references is naturally aligned. ? the memory accessed takes a sing le cycle to return a data item. ? timing is best case; no cache misses, no pending stores. table 2-18 csa control flow instruction timing instruction flow latency repeat rate instruction flow latency repeat rate call 4-8 4-8 syscall 4-8 4-8 calla 4-8 4-8 svlcx 4-8 4-8 calli 4-8 4-8 rslcx 4-8 4-8 ret 4-8 4-8 rfe 4-8 4-8 bisr 4-8 4-8 rfm 4-8 4-8 fcall 11 fcalla 11 fcalli 11 fret 11 table 2-19 load instruction timing instruction address latency result latency repeat rate instruction address latency result latency repeat rate load instructions ld.a 131 ld.q 121 ld.b 121 ld.w 121 ld.bu 121 ldlcx 4-8 4-8 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-76 v1.1, 2011-03 cpu, v1.0 ld.d 121 lducx 4-8 4-8 4 ld.da 131 swap.w 232 ld.h 121 lea 1) ?11 ld.hu 121 1) the addressing mode returning an updated address is not relevant for this instruction. table 2-19 load instruction timing (cont?d) instruction address latency result latency repeat rate instruction address latency result latency repeat rate www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-77 v1.1, 2011-03 cpu, v1.0 2.15.2.4 store instruction timing cache and store instructions si milar to load instructions w ill have a result for the pre- increment, post-increment, circular or bit-reverse addressing modes, but do not produce a ?memory? result. ? each instruction is single issued. ? the memory references is naturally aligned. ? the memory accessed takes a sing le cycle to accept a data item. ? timing is best case; no cache misses, no pending stores. table 2-20 cache and store instruction timing instruction address latency repeat rate instruction address latency repeat rate cache instructions cachea.i 11 cachea.wi 1) 1) repeat rate assumes that no memory writeback operation occurs. otherwise the repeat rate will depend upon the time for the castout buffers to clear. 11 cachea.w 1) 11 cachei.w 11 cachei.wi 11 cachei.i 11 store instructions st.a 11 st.t 12 st.b 11 st.w 11 st.d 11 stlcx 14-8 st.da 11 stucx 14-8 st.h 11 ldmst 12 st.q 11 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-78 v1.1, 2011-03 cpu, v1.0 2.15.3 floating point pipeline timing these instructions are only valid if the optional floating point unit is implemented. each instruction is single issued. table 2-21 floating point instruction timing instruction result latency repeat rate instruction result latency repeat rate floating point instructions addf 21 itof 21 cmp.f 11 madd.f 31 div.f 86 msub.f 31 ftoi 21 mul.f 21 ftoiz 21 q31tof 21 ftoq31 21 qseed.f 11 ftoq31z 21 sub.f 21 ftou 21 updfl ?1 ftouz 21 utof 21 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-79 v1.1, 2011-03 cpu, v1.0 2.16 program memory interface (pmi) figure 2-13 shows the block diagram of the program memory interface (pmi) of the TC1798. figure 2-13 pmi block diagram 2.16.1 pmi features the program memory interface (pmi) has the following features: ? 16 kbyte program cache (icache) ? four-way set associative cache ? plru (pseudo least-recently used) replacement algorithm ? cache line size: 256 bits (4 double-words) ? validity granularity: one valid bit per cache line ? icache can be globally invalidated to provide support for software cache coherency (to be handled by the programmer) icache pspr plb cps from sri master interface to/from sri slave interface to cpu fetch pipeline to/from cpu sfr registers www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-80 v1.1, 2011-03 cpu, v1.0 ? icache can be bypassed to provide a direct fetch from the cpu to on-chip and off-chip resources ? icache refill mechanism: critical word first, line wrap around, streaming to cpu ? 32 kbyte program scratchpad memory (pspr) ? cpu interface ? supporting 64bit aligned fetches. ? cpu slave interface (cps) ? shared resource interconnect bus (sri) master interface ? shared resource interconnect bus (sri) slave interface to scratchpad ram and cps. ? all pmi srams (pspr, icache, and ca che tag sram) ar e ecc protected ? ecc is calculated on address and data for the pspr and icache 2.16.2 scratchpad ram the TC1798 contains 32 kbyte of program scratchpad ram. scratchpad ram provides a fast, deterministic program fetch access from the cpu for use by performance critical code sequences. ? cpu program fetch accesses to scratchpad ram are never cached in the instruction cache and are always directly targeted to the scratchpad ram. the cpu fetch interface will gen erate aligned accesse s (64-bit), which will result in 64- bits of instruction being returned to the cpu. note that the cpu fetch unit can only read from the scratchpad ram and can never write to it. the scratchpad ram may also be accessed from the sri slave interface by another bus master, such as the data memory interface (dmi). the scratchpad ram may be both read and written from the sri. in the TC1798, the sri slave interface supports all sri transaction types. the scratchpad ram is ecc protected across both address and data. 2.16.3 instruction cache the TC1798 contains up to 16 kbyte of instruction cache (icache). the icache is a four-way set-associative cache with a pseudo least-recently-used (plru) replacement algorithm. each icache line contains 256 bits of instruction along with a single associated valid bit and associated ecc bits. cpu program fetch accesses which target a cacheable memory segment (and where the icache is not bypassed) target the icache. if the requested address and its associated instruction are found in the cache (cache hit), the instruction is passed to the cpu fetch unit without incurring any wait states. if the address is not found in the cache (cache miss), the pmi cache controller iss ues a cache refill sequ ence and wait states www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-81 v1.1, 2011-03 cpu, v1.0 are incurred whilst the cache line is refilled. the fetch request always returns an aligned 64bit packet to the cpu. the instruction cache is ecc protected on both address and data. the instruction tag ram is ecc protected on data. instruction cache refill sequence instruction cache refills are performed using a critical double-word first strategy with cache line wrapping such that the refill size is always 4 double-words. icache refills are always performed in 64-bit quant ities. a refill seque nce will always affect only one cache line. there is no prefetching of the next cache line. icache refills are therefore implemente d using an sri burst transfer 4 (btr4) transfers. the instruction cache supports instruction streaming, meaning that it can deliver available instruction half-words to the cpu fetch unit whilst the refill operation is ongoing. instruction cache bypass the instruction cache may be bypassed, under control of pcon0.pcbyp, to provide a direct instruction fetch path for the cpu fetch unit. the default value of pcon0.pcbyp is such that the icache is bypassed after reset. icache bypass should be disabled during initialization to enable the icache. whilst icache bypass is enabled, a fetch request by the cpu to a cacheable address will result in a forced cache miss, such that the cache controller issues a standard refill sequence and supplies instruction half-words to the cpu using instruction streaming, without updating the cache contents. any valid cache lines within the icache will remain valid and unchanged whilst the icache is bypassed. as such, instruction fetch requests to cacheable addresses with icache bypass enabled behave identically to instruction fetch requests to non-cacheable addresses. instruction cache invalidation the pmi does not have automatic cache cohe rency support. changes to the contents of memory areas external to the pmi that may have already been cached in the icache are not detected. software must provide the cache coherency in such a case. the pmi supports this via the cache invalidation f unction. the icache contents may be globally invalidated by writing a ?1? to pcon1.pcinv. the icache invalidation is performed over 128 cycles by a hardware st ate machine which cycles th rough the icache entries marking each as invalid. during an invalidate sequence the cpu may continue to fetch instructions from non-cacheable memory. any attempt to fetch instructions from a cacheable memory location during an invalidation sequence will result in the cpu stalling until the sequence completes. the status of the icache invalidation sequence may be determined by reading the pcon1.pcinv bit. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-82 v1.1, 2011-03 cpu, v1.0 2.16.4 program line buffer the pmi module contains a 256-bit program li ne buffer (plb). program fetch requests to non-cacheable addresses (or to cacheable addresses with the cache in bypass) utilize the plb as a single line cache. a single valid bit is associated with the plb, denoting that the plb contents are valid. as such all fetch requests resulting in an update of the plb, whether to a cacheable address or no t, are implemented as sri burst transfer 4 (btr4) transactions, with the critical double-word of the plb line being fetched first size. the plb may be invalidated by writing pcon1.pbinv. the plb is ecc protected on both address and data. 2.16.5 cpu slave interface (cps) the cpu slave interface provides access fr om the sri bus to the core csfr and sfr registers. 2.16.6 pmi registers three control registers are control the o peration of the program memory interface. these registers and their bits are described in this section. table 2-22 pmi registers short name description offset address access mode reset read write pcon0 pmi control register 0 920c h u, sv, 32 sv, 32 class 3 reset 0000 0002 h pcon1 pmi control register 1 9204 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h pcon2 pmi control register 2 9208 h u, sv, 32 sv, e, 32 class 3 reset 0020 0010 h pmi_str pmi synchronous trap register 9200 h u, sv, 32 sv, 32 class 3 reset 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-83 v1.1, 2011-03 cpu, v1.0 2.16.6.1 pmi register descriptions pmi control register 0 pcon0 program memory control register 0 (f7e1 920c h ) reset value: 0000 0002 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res pc byp res rrwr field bits type description res 0r reserved read as 0; should be written with 0. pcbyp 1rw instruction cache bypass 0 b cache enabled 1 b cache bypassed (disabled) res [31:2] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-84 v1.1, 2011-03 cpu, v1.0 pmi control register 1 pcon1 program memory control register 1 (f7e1 9204 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res pb inv pc inv rrwrwh field bits type description pcinv 0rwh instruction cache invalidate write operation: 0 b no effect. normal instruction cache operation. 1 b initiate invalidation of entire instruction cache. read operation: 0 b normal operation. instruction cache available. 1 b instruction cache invalidation in progress. instruction cache unavailable. pbinv 1rw program buffer invalidate write operation: 0 b no effect. normal program line buffer operation. 1 b invalidate the program line buffer. this field returns 0 when read. res [31:2] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-85 v1.1, 2011-03 cpu, v1.0 pmi control register 2 pcon2 contains size informatio n for the program memory system. pcon2 program memory control register 2 (f7e1 9208 h ) reset value: 0020 0010 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pscratch_sze r 1514131211109876543210 pcache_sze r field bits type description pcache _sze [15:0] r program cache (icache) size in kbytes pscrat ch_sze [31:16] r program scratch size in kbytes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-86 v1.1, 2011-03 cpu, v1.0 program memory interface synchronous trap register (pstr) pstr contains synchronous trap information for the program memory system. the register is updated with trap information for pse traps to aid the localisation of faults. the register is only set whenever a trap is detected and the register has no bits already set. it is cleared by a csfr write (independent of data value). fetch range error a fetch range error occurs whenever an access to the program scratch is outside the range of the sram. fetch global address error pstr program synchronous trap register (f7e1 9200 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res fme res fpe res fbe fga e fre r rwh r rwh r rwh rwh rwh field bits type description fre 0rwh fetch range error fgae 1rwh fetch global address error fbe 2rwh fetch bus error res [11:3] r reserved fpe 12 rwh fetch peripheral error res 13 r reserved fme 14 rwh fetch msist error res [31:15] r reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-87 v1.1, 2011-03 cpu, v1.0 a fetch global address error occurs whenever an there is access to an address that cannot be translated to a valid global address.this will occur for accesses in the range d1000000 to d7ffffff fetch bus error a fetch bus error will be set whenever the sri flags an error due a fetch from external memory. this will be set for both direct fetches from the bus and for cache refills. fetch peripheral error a fetch peripheral error will be flagged whenever a fetch is attempted to peripheral space. fetch msist error during sist mode, a fetch from the ptag will cause a pse trap to occur. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-88 v1.1, 2011-03 cpu, v1.0 2.17 data memory interface (dmi) this figure shows the block diagram of the data memory interface (dmi) of the TC1798. figure 2-14 dmi block diagram 2.17.1 dmi features the data memory interface (dmi) has the following features: ? 128 kbyte data scratchpad ram (dspr) ? supporting unaligned access (16-bit aligned) with no penalty. ? 16 kbyte data memory (dcache): ? four-way set associative cache, pseudo least recently used (plru) replacement algorithm ? cache line size: 256 bits ? validity granularity: one valid bit per cache line ? write-back cache: writeback granularity: 256 bits ? refill mechanism: fu ll cache line refill dcache dspr from sri master interface to/from sri slave interface to cpu memory pipeline www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-89 v1.1, 2011-03 cpu, v1.0 ? cpu interface ? shared resource interface bus (sri) master interface ? shared resource interface (sri) slave interface to dspr ? ? all dmi srams (dspr, dcache, and ca che tag sram) are ecc protected 2.17.2 data scratchpad ram (dspr) the TC1798 contains 128 kbyte of dspr. dspr provides fast, deterministic data access to the cpu for use by performance critical code sequences. the dspr is organised as multiple memory ?towers?. this organisation allow the cpu to access 64bits of data from any 16bit aligned address the dspr may also be accessed from the sr i slave interface by another bus master, with both read and write transactions supported. the dspr may be accessed by the sri slave interface using any sri transaction type, including burst transfers. in accordance with the sri protocol, accesses to the sri slave interface must be naturally aligned. 2.17.3 data cache the TC1798 contains 16 kbyte of data cache (dcache). the dcache is a four-way set- associative cache with a pseudo least-rece ntly-used (plru) replacement algorithm. each line contains 256 bits of data along with ecc bits. a single valid bit and a single dirty bit are associated with each line. cpu data accesses to a cacheable memory segment target the dcache. if the requested address and its associated data are found in the cache (cache hit), the data is passed to/from the cpu load-store unit without incurring any wait states. if the address is not found in the cache (cache miss), the dmi cache controller issues a cache refill sequence and wait states are incurred whilst the cache line is refilled. the cpu load-store interface will generate unaligned accesses (16-bit aligned), which will result in up to 64-bits of data being transferred to or from the cpu (for non-context operations). if the data access is made within a dcache line, no matter the alignment, and a cache hit is detected then the requested data is return ed to the cpu in a single cycle. if the data access is made to the end of a dcache line, such that the requested data would span two dcache lines, a single wait cycle is incurred (if both cache lines are present in the cache, otherwise a refill sequence is required for the missing cache line(s)). the TC1798 data cache is of the writeback type. when the cpu writes to a cacheable location the data is merged with the corresponding cache line and not written to main memory immediately. associated with each cache line is a single ?dirty? bit, to denote that the data in the cache line has been modified. whenever a cpu load-store access results in a cache miss, and each of the potential cache ways that could hold the requested cache line are valid, one of the cache lines is chosen for eviction based upon the plru replacement algorithm. the line selected for ev iction is then checked to determine if it www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-90 v1.1, 2011-03 cpu, v1.0 has been modified using its dirty bit. if the line has not been modified the line is discarded and the refill sequence started immediately. if the line has been modified then the dirty data is first written back to main memory before the refill is initiated. due to the single dirty bit per cache line, 256 bits of data will always be written back, resulting in a sri burst-4 transfer (btr4) transactions. data cache refills always resu lt in the full cache line bei ng refilled, with the critical double-word of the dcache line being fetched first. a refill sequence will always affect only one cache line. there is no prefetching of the next cache line. due to the uniform size of dcache refill sequences, such refills are always implemented using sri burst transfer 4 (btr4) transactions. 2.17.4 dmi trap generation cpu data accesses to the dmi may encounter one of a number of potential error conditions, which result in one of the following trap conditions being reported by the dmi. aln trap an aln trap is raised for the following conditions: ? an access whose effective address does not conform to the alignment rules ? an access where the length, size or index of a circular buffer is incorrect whenever an aln trap occurs, the dstr (data synchronous trap register) and the deadd (data error address register) csfrs are updated. mem trap a mem trap is raised for the following conditions: ? an access whose effective address has a different segment to that of the base address (segment difference error) ? an access whose effective address causes the data to span two segments (segment crossing error) ? a memory address is used to acce ss a csfr area (csfr access error) whenever a mem trap occurs, the dstr (data synchronous trap register) and the deadd (data error address register) csfrs are updated. dse trap a dse trap is raised for the following conditions: ? an access outside the range of the dspr (scratch range error) ? an access to the lower half of segment c which cannot be translated into a global address, i.e. from c1000000 to c7ffffff (global address error) ? an error on the bus for an external accesses due to a load (load bus error) ? an error from the bus during a cache refill (cache refill error) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-91 v1.1, 2011-03 cpu, v1.0 ? an error during a load whilst in sist mode (load msist error) ? an error generated by the overlay system during a load. whenever a dse trap occurs, the dstr (data synchronous trap register) and the deadd (data error address register) csfrs are updated. dae trap a dae trap is raised for the following conditions: ? an error on the bus for an external accesses due to a store (store bus error) ? an error on the bus due to a cache writeback (cache writeback error) ? an error from the bus due to a cache flush (cache flush error) ? an error due to a store whilst in sist mode (store msist error) ? an error generated by the overlay system during a store. whenever a dae trap occurs, the datr (data synchronous trap register) and the deadd (data error address register) csfrs are updated. data memory protection traps data memory protection traps (mpw, mpr, mpp, mpn) are raised by the memory protection system when a protection vi olation occurs. whene ver a data memory protection trap occurs the dstr (data synchronous trap register) and the deadd (data error address register) are updated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-92 v1.1, 2011-03 cpu, v1.0 2.18 memory configuration the tc1.6 memories are configured as follows:- the cache and tag memories may be mapped into the cpus address space using the smacon register. when mapped the locations of these memories is as follows. the cachei.* instructions require a way and index value to be supplied in a valid address. the location of these bits in the 32bit address is as follows. table 2-23 memory configuration processor program cache program scratchpad data cache data scratchpad tc1.6 16k bytes 32 kbytes 16 kbytes 128 kbytes table 2-24 way and index location function address bits way [1:0] index [11:5] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-93 v1.1, 2011-03 cpu, v1.0 2.18.1 dmi registers two control registers and three trap flag regi sters control the operation of the dmi. these registers and their bits are described in this section. . table 2-25 dmi registers short name description offset address access mode reset read write dcon0 dmi control register 0 9040 h u, sv, 32 sv, e, 32 class 3 reset 0000 0002 h dcon2 dmi control register 2 9000 h u, sv, 32 sv, e, 32 class 3 reset 0800 0010 h dstr dmi synchronous trap flag register 9010 h u, sv, 32 1) 1) writing these registers clears the contents independent of the data value. sv, 32 class 3 reset 0000 0000 h datr dmi asynchronous trap flag register 9018 h u, sv, 32 1) sv, 32 class 3 reset 0000 0000 h deadd dmi data error address register 901c h u, sv, 32 sv, 32 class 3 reset 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-94 v1.1, 2011-03 cpu, v1.0 2.18.1.1 dmi register descriptions note: there is no dcon1 register in this implementation. data memory control register 0 (dcon0) the dcon0 register allows the data cache to be bypassed. dcon0 data memory control register (f7e1 9040 h ) reset value: 0000 0002 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res dcb yp res r rw r field bits type description res 0- reserved dcbyp 1rw data cache bypass 0 b cache enabled 1 b cache bypass (disabled) res [31:2] - reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-95 v1.1, 2011-03 cpu, v1.0 data control register 2 (dcon2) dcon2 contains size information for the data memory system. dcon2 data control register 2 (f7e1 9000 h ) reset value: 0080 0010 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dscratch_sze r 1514131211109876543210 dcache_sze r field bits type description dcache _sze [15:0] r data cache size in kbytes dscrat ch_sze [31:16] r data scratch size in kbytes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-96 v1.1, 2011-03 cpu, v1.0 dmi synchronous trap flag register the dstr contains synchro nous trap information for th e data memory system. the register is updated with trap source info rmation to aid the localisation of faults. the register is updated whenever a valid trap is detected and the register has no bits already set. it is cleared by a write (independent of data value). dstr data synchronous trap register (f7e1 9010 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res aln res cac sce sde r rwh r rwh rwh rwh 1514131211109876543210 loe dtm e res cre res lbe gae sre rwh rwh r rwh r rwh rwh field bits type description sre 0rwh scratch range error gae 1rwh global address error lbe 2rwh load bus error res [5:3] r reserved cre 6rwh cache refill error res [13:7] r reserved dtme 14 rwh dtag msist error loe 15 rwh load overlay error sde 16 rwh segment difference error sce 17 rwh segment crossing error cac 18 rwh csfr access error res [23:19] r reserved aln 24 rwh alignment error res [31:25] r reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-97 v1.1, 2011-03 cpu, v1.0 dmi asynchronous trap flag register the datr contains asynchronous trap information for the data memory system. the register is updated with trap information for dae traps to aid the localisation of faults. the register is updated whenever a valid trap is detected and the register has no bits already set. it is cleared by a write (independent of data value). datr data asynchronous trap register(f7e1 9018 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 sme soe res cfe cwe res sbe res rwh rwh r rwh rwh r rwh r field bits type description res [2:0] r reserved sbe 3rwh store bus error res [8:4] r reserved cwse 9rwh cache writeback error cfse 10 rwh cache flush error res [14:11] r reserved soe [14] rwh store overlay error sme 15 rwh store mist error res [31:16] r reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-98 v1.1, 2011-03 cpu, v1.0 data error address register deadd contains trap address information for the data me mory system. the register is updated with trap information for mem, aln, dse or dae traps to aid the localisation of faults. the register is only set whenever a trap is detected and either the datr or dstr registers have no bits already set. deadd data error address register (f7e1 901c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 error_address rh 1514131211109876543210 error_address rh field bits type description error_ addres s [31:0] rh error address www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-99 v1.1, 2011-03 cpu, v1.0 2.19 safety features the TC1798 implements a number of safety co ncepts. as part of this the tricore1.6 core implements the following features:- ? sri address phase error injection ? sri data phase error capture ? safety interrupt acknowledge decoupling 2.19.1 sri address phase error injection to allow the sri address phase error detection system to be tested it is necessary to inject errors during the read phase of an sri address transaction. this is done by selectively inverting individual bits of the sri read or write phase ecc packet and is controlled using the sfagen register. the sf agen register contains two fields:- an enable (ae) and a bit flip (adflip) field. when enabled the address ecc bits indicated by the flip field are inverted for the next sri data read or write bus transaction performed by the dmi. following the transaction the enable bit is cleared by hardware. this mechanism allows selected bits of the sri address ecc to be corrupted for a single transaction. 2.19.2 sri data phase error capture error information detected during the sri read data phase as the result of a pmi fetch is captured in the sferr0 and sferr1 registers. such an error will typically result in a pie trap. on detection of an error the error information is captured and the sferr0.e_val bit is set. no further error information is captured until this bit is cleared by software. 2.19.3 safety interrupt acknowledge decoupling in standard operation a successfully requesting interrupt node is automatically acknowledged and cleared down by hardware. this is done as part of the interrupt entry sequence performed by the tricor e and before the start of the interrupt service routine (isr). an isr is therefore unable to verify that the interrupt node corresponding to its level is active. in safety systems such verifica tion is desirable. the tric ore1.6 may be operated in a ?safe interrupt? mode in which the acknowledgment and clearing of the requesting node is decoupled from the interrupt entry seq uence hence allowing an isr to inspect the requesting node to verify correct operation. this mode is enabled by clearing the compat.int bit. the isr is responsible for acknowledging and clearing down the interrupt node by clearing the safeint.int bit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-100 v1.1, 2011-03 cpu, v1.0 2.19.4 registers implementing safety features safe fetch address error generation register the sfagen register controls the injection of sri address phase errors from the dmi. safe fetch error register 0 the sferr0 register captures read data phase error information on safe fetch errors from the pmi. sfagen safe fetch address error generation register (f7e1 1030 h ) reset value: 0000 000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res ae rwh r 1514131211109876543210 res adflip r rw field bits type description adflip [7:0] rw address ecc bit flip sri address ecc bits to be flipped on the next read or write transaction from the dmi when enabled by ae. 0 b no flip 1 b flip res [30:8] r reserved ae 31 rwh address error enable enabled the selective inverting of sri address phase ecc packet bits defined by adflip. this bit will be cleared by hardware after the next sri read or write transaction from the dmi. 0 b not enabled 1 b enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-101 v1.1, 2011-03 cpu, v1.0 safe fetch error register 1 sferr0 safe fetch error register 0 (f7e1 1000 h ) reset value: 0000 000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res e_v al rwh r 1514131211109876543210 res err_ecc res rwh field bits type description err_ecc [7:0] rwh error ecc the err information of the erroneous sri packet res [30:8] - reserved e_val 31 rwh error valid an error has been detected since the register was last cleared sferr1 safe fetch error register 1 (f7e1 1004 h ) reset value: 0000 000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 err_add rwh 1514131211109876543210 err_add rwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-102 v1.1, 2011-03 cpu, v1.0 field bits type description err_ecc [31:0] rwh err_add the address of the erroneous sri packet www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-103 v1.1, 2011-03 cpu, v1.0 safe interr upt register in order to improve plausibility checks on interrupt service routines (isr) the acknowledgement of interrupts may be decoupled from interrupt entry. when interrupt entry occurs the safeint.int bit is set. the interrupt acknowledge is delayed until the register is written to zero. safeint safe interrupt register (0xfe30) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res int rrwh field bits type description int 0rwh interrupt active read: 0 = interrupt inactive read: 1 = interrupt active write: 0 = clear safe interrupt write: 1 = no effect res [31:1] r reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 cpu subsystem users manual 2-104 v1.1, 2011-03 cpu, v1.0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-1 v1.1, 2011-03 32-bit scu, v1.0 3 system control unit (scu) the system control unit (s cu) of the TC1798 handles all system control tasks beside the debug related tasks which are co ntrolled by the ocds/cerberus. the scu contains the following func tional sub-blocks: ? clock control (see section 3.1 ) ? reset operation (see section 3.2 ) ? external interface (see section 3.3 ) ? power management (see section 3.4 ) ? software boot support (see section 3.5 ) ? sram ecc control (see section 3.6 ) ? die temperature measurement (see section 3.7 ) ? watchdog timer (see section 3.8 ) ? emergency stop control (see section 3.9 ) ? interrupt generation (see section 3.10 ) ? nmi trap generation (see section 3.11 ) ? scu registers and address map (see section 3.12 ) ? scu register overview table (see table 3-22 ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-2 v1.1, 2011-03 32-bit scu, v1.0 3.1 clock system overview this section describes the TC1798 clock system. topics covered include clock generation and the operation of clock circuitry. the TC1798 clock system prov ides the following functions: ? acquires and buffers incoming clock sign als to create a master clock frequency ? distributes in-phase synchronized clock signals throughout the TC1798?s entire clock tree ? divides the master clock frequency into lower frequencies required by the different modules for operation ? reduces electromagnetic interference (emi) by switching off unused modules figure 3-1 shows the structure of the TC1798 clock system. the master clock f pll is generated by the oscillator circuit and the pll (phase-locked loop) unit (see section 3-2 ). the functionality of the control blocks shown in figure 3-1 varies depending on the functional unit being controlled. some functional units such as the watchdog timer, are directly driven by the system clock. the impl emented clock control register options are described for each module in the module chapter itself. all clock control registers clc and the frac tional divider registers fdr are endinit- protected. features of the TC1798 clock system ? pll operation for multiplying clock source by different factors ? direct drive capability for direct clocking ? comfortable state machine for secure switching between freerunning mode / normal mode and prescaler mode www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-3 v1.1, 2011-03 32-bit scu, v1.0 figure 3-1 TC1798 clocking system sri-bus domain ebu sfi scu dmi pmi tricore tm cpu icu f sr i f fpi f mcds f ebu dma mcds eray ports pcp2 f sr i pcp2 domain eray domain fpi-bus domain TC1798 toplevel _ clock_ 1798 . f refclk2 f refclk1 f pc p f pc p xtal1 xtal2 extclk1 extclk0 cgu f fsi cpu subsystem pmu f bbb sbcu asc0 asc1 ssc0 ssc1 ssc2 sent stm gpta0 gpta1 ltca2 fadc adc0 adc1 adc2 adc3 msc0 msc1 mli0 mli1 multican sdma she fce bmu gpt120 gpt121 ccu 6061 ccu 6263 xbar sscg ssc3 f er ay www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-4 v1.1, 2011-03 32-bit scu, v1.0 3.1.1 clock generation unit the clock generation unit (cgu) allows a very flexible clock generation for the TC1798. during user program execution the frequency can be programmed for an optimal ratio between performance and power consumption. 3.1.1.1 overview the cgu in the TC1798 consists of one oscillator circui t (osc), two phase-locked loop modules (pll and pll_eray) and a clock c ontrol unit (ccu). the cgu can convert a low-frequency external clock signal to a high-speed internal clock. the cgu provides clock signals for the different parts of the device that can be configured depending on the application needs within certain limits. figure 3-2 clock generation unit block diagram the following sections describe the different parts of the cgu. xtal1 xtal2 cgu cgu_block ccu pll pllcon1 pllcon0 osc pll ma f osc pll_ eray pll _eray ccucon0/1 pll _eray f f f f osccon plleraycon0 plleraycon1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-5 v1.1, 2011-03 32-bit scu, v1.0 3.1.1.2 oscillator circuit (osc) the oscillator circuit, a pierce oscillator, is designed to work with both an external crystal / resonator or an external stable clock source, consists of an inverting amplifier with xtal1 as input, and xtal2 as output with an integrated feedback resistor. external input clock mode when supplying the clock signal directly, not using an external crystal / ceramic resonator and bypassing the oscillator, the input frequency needs to be equal or greater than pll vco input frequency (the value is listed in the data sheet). when using an external clock signal it must be connected to xtal1. xtal2 is left open (unconnected). figure 3-3 TC1798 direct clock input external crystal / ceramic resonator mode figure 3-4 shows the recommended external circuitries for both operating modes, external crystal / ceramic resonator m ode with and without external components. ext_clk_inl_mode osc xtal1 xtal2 external clock signal f osc v ss v ddp www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-6 v1.1, 2011-03 32-bit scu, v1.0 figure 3-4 external circuitry for crystal / ceramic resonator operation when using an external crystal / ceramic resonator, its frequency can be within the allowed range (the values ar e listed in the data sheet). an external oscillator load circuitry must be used, connected to both pins, xtal1 and xtal2. additionally are necessary, two load capacitances c 1 and c 2 , and depending on the crystal / ceramic resonator type, a series resistor r 2 to limit the current. a test resistor r q may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. r q values are typically specified by the crystal / ceramic resonator vendor. the c 1 and c 2 values shown in the data sheet can be used as starting points for the negative resistance evaluation and for non-productive systems. the exact values and related operating range are dependent on the crystal / ceramic resonator frequency and have to be determined and optimized together with the crystal / ceramic resonator vendor using the negative resistance method. oscillation measurement with the final target system is strongly recommended to verify the input amplitude at xtal1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator- crystal / ceramic resonator system. the oscillator c an also be used in combination with a ceramic resonator. the final circuitry must be also verified by the resonator vendor. oscillator run detection see . ext_crystal_mode osc c 1 c 2 xtal1 xtal2 with external components v ddp f osc v ss r 2 r q osc xtal1 xtal2 without external components v ddp f osc v ss www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-7 v1.1, 2011-03 32-bit scu, v1.0 3.1.1.3 phase-locked loop (pll) module the pll can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. the pll also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. it can execute emergency actions if it loses its lock on the external clock. this module is a phase locked loop for integer frequency synthesis. it allows the use of input and output frequencies of a wide range by varying the different divider factors. features ? vco lock detection ? 4-bit input divider p: (divide by pdiv+1) ? 7-bit feedback divider n : (multiply by ndiv+1) ? 7-bit output divider k1 or k2: (divide by either by k1div+1 or k2div+1) ? oscillator watchdog ? detecting too low input frequencies ? detecting too high input frequencies ? spike detection for the osc input frequency ? different operating modes ? prescaler mode ? freerunning mode ? normal mode ? vco power down ? glitchless switching between both k-dividers ? glitchless switching between normal mode and prescaler mode ? frequency modulation ? jitter reduction for modulation jitter pll functional description the pll consists of a voltage controlled oscillator (vco) with a feedback path. a divider in the feedback path (n-divider) divides the vco frequency down. the resulting frequency is then compared with the externally provided and divided frequency (p- divider). the phase detection logic determines the difference between the two clocks and accordingly controls the frequency of the vco ( f vco ). a pll lock detection unit monitors and signals this condition. the phas e detection logic continues to monitor the two clocks and adjusts the vco clock if required. the pll output clock f pll is derived from the vco clock by the k2-divider or fr om the oscillator cloc k and the k1-divider. the following figure shows the pll block structure. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-8 v1.1, 2011-03 32-bit scu, v1.0 figure 3-5 pll block diagram clock source control the pll clock f pll is generated from f osc in one of three software selectable modes: ? normal mode ? prescaler mode ? freerunning mode normal mode in normal mode the input frequency f osc is divided down by a factor p, multiplied by a factor n and then divided down by a factor k2. the output frequency is given by (3.1) fmpll_block p- divider vco f osc n- divider lock- detection osc wdg k1- divider k2- divider m u x f pll f div f k2 f k1 pllcon0. vcobyp pllstat. findisc f vco f ref osccon. plllv osccon. pllhv osccon. pllsp pllstat. vcolock pllstat. k1rdy pllstat. k2rdy m u x modulator pllcon2. modamp pllcon2. mo df req pllcon0. ndiv pllcon0. moden f pll n pk2 ? --------------- f osc ? = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-9 v1.1, 2011-03 32-bit scu, v1.0 prescaler mode in prescaler mode the reference frequency f osc is only divided down by a factor k1. the output frequency is given by (3.2) freerunning mode in freerunning mode the base frequency output of the voltage controlled oscillator (vco) f vcobase is only divided down by a factor k2. the output frequency is given by (3.3) oscillator watchdog (osc_wdt) the oscillator wa tchdog monitors the in coming clock frequency f osc from osc. a stable and defined input frequency is a mandatory requirement for operation in both prescaler mode and normal mode. for operation in freerunning mode no f osc input frequency is required. therefore this mode is selected automatically after each system reset. in addition for the normal mode it is required that the input frequency f osc is in a certain frequency range to obtain a stabile master clock from the vco part. the expected input frequency is selected via the bit field osccon.oscval. the osc_wdt checks for too low frequencies and for too high frequencies. the frequency that is monitored is f oscref which is derived for f osc . (3.4) the divider value osccon.oscval has to be selected in a way that f oscref is 2.5 mhz. note: f oscref has to be within the range of 2 mhz to 3 mhz and should be as close as possible to 2.5 mhz. before configuring the osc_wdt function all the trap options should be disabled in order to avoid unintended traps. thereaft er the value of osccon.oscval can be changed. then the osc_wdt should be reset by setting osccon.oscres. this requests the start of osc_wdt monitoring with the new configuration. when the f pll f osc k1 -------------- = f pll f vcobase k2 --------------------------- = f oscref f osc oscval 1 + ---------------------------------- - = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-10 v1.1, 2011-03 32-bit scu, v1.0 expected positive monitoring results of osccon.plllv and / or osccon.pllhv are set the input frequency is within the expected range. as setting osccon.oscres clears all three bits osccon.pllsp, osccon.plllv, and osccon.pllhv all three trap status flags will be set. therefore all three flags shoul d be cleared be fore the trap generation is enabled again. the trap dis abling-clearing-enabling sequence should also be used if only bit osccon.oscres is set without any modification of osccon.oscval. configuration and operation of the freerunning mode in freerunning mode, the pll is running at its vco base frequency and f pll is derived from f vco only by the k2-divider. the freerunning mode is entered after each system reset. figure 3-6 pll free-running mode diagram the output frequency is given by (3.5) the freerunning mode is selected by the following settings ? pllcon0.vcobyp = 0 ? pllcon0.setfindis = 1 the freerunning mode is entered when ? pllstat.findis = 1 ?and ? pllstat.vcobyst = 0 pll _fr eerunning _ m ode .vsd pll block vco k2- divider n- divider lock detect. f pll f k2 f vco f div f ref pllcon 0 . vcoby p m u x 0 1 pllstat .findis '1' f pll f vcobase k2 --------------------------- = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-11 v1.1, 2011-03 32-bit scu, v1.0 operation on the freerunning mode does not require an input clock frequency of f osc . the freerunning mode is automatically ente red on a pll vco loss-of-lock event if bit pllcon0.oscdiscdis is cleared. this mechanism allows a fail-safe operation of the pll as in emergency cases still a clock is available. the frequency of the freerunning mode f vcobase is listed in the data sheet. note: changing the system operation frequency by changing the value of the k2-divider has a direct coupling to the power consum ption of the device. therefore this has to be done carefully. depending on the selected divi der value of the k2-divider the duty cycle of the clock is selected. this can have an impact for the operation with an external communication interface. the duty cycles values for the diffe rent k2-divider values are defined in the data sheet. configuration and operation of the prescaler mode in prescaler mode, the pll is running at the external frequency f osc and f pll is derived from f osc only by the k1-divider. figure 3-7 pll prescaler mode diagram the output frequency is given by: (3.6) the prescaler mode is select ed by the following settings ? pllcon0.vcobyp = 1 the prescaler mode is entered when the following requirements are all together valid: pll block osc. wdg k1- divider f pll f k1 pllcon 0 . vcoby p m u x 0 1 f os c osccon.plllv osccon.pllhv f pll f osc k1 -------------- = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-12 v1.1, 2011-03 32-bit scu, v1.0 ? pllstat.vcobyst = 1 ? osccon.plllv = 1 operation on the prescaler mode does require an input clock frequency of f osc . therefore it is recommended to check and monitor if an input frequency f osc is available at all by checking osccon.plllv. for a better monitoring also the upper frequency can be monitored via osccon.pllhv. for the prescaler mode there are no r equirements regarding the frequency of f osc . the system operation frequency is controlled in the prescaler mode by the value of the k1-divider. when the value of pllcon1.k1div was changed the next update of this value should not be done before bit pllstat.k1rdy is set. note: changing the system operation frequency by changing the value of the k1-divider has a direct coupling to the power consum ption of the device. therefore this has to be done carefully. depending on the selected divi der value of the k1-divider the duty cycle of the clock is selected. this can have an impact for the operation with an external communication interface. the duty cycles values for the diffe rent k1-divider values are defined in the data sheet. the prescaler mode is requested from the fr eerunning or normal mode by setting bit pllcon.vcobyp. the prescaler mode is entered when the status bit pllstat.vcobyst is set. before the prescaler mode is requested the k1-divider should be configured with a value generating a pll output frequency f pll that matches the one generated by the freerunning or normal mode as much as possible. in this way the frequency change resulting out of the mode change is reduced to a minimum. the prescaler mode is requested to be left by clearing bit pllcon.vcobyp. the prescaler mode is left when the st atus bit pllstat.vcobyst is cleared. configuration and operation of the normal mode in normal mode, the pll is running at the external frequency f osc and f pll is divided down by a factor p, multiplied by a factor n and then divided down by a factor k2. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-13 v1.1, 2011-03 32-bit scu, v1.0 figure 3-8 pll normal mode diagram the output frequency is given by: (3.7) the normal mode is selected by the following settings ? pllcon0.vcobyp = 0 ? pllcon0.clrfindis = 1 the normal mode is entered when the following requirements are all together valid: ? pllstat.findis = 0 ? pllstat.vcobyst = 0 ? pllstat.vcolock = 1 ? osccon.plllv = 1 ? osccon.pllhv = 1 for the nomal mode operation it is recommanded to clear bit pllcon0.oscdiscdis. operation on the normal mode does require an input clock frequency of f osc . therefore it is recommended to check and monitor if an input frequency f osc is available at all by checking osccon.plllv. for a better monitoring also the upper frequency can be monitored via osccon.pllhv. the system operation frequency is controlled in the normal mode by the values of the three dividers: p, n, and k2. a modification of the two dividers p and n has a direct influence to the vco frequency and lead to a loss of the vco lock status. a modification pll _norm al_m ode . vsd pll block f os c osc. wdg p- divider vco k2- divider n- divider lock detect. f pll f k2 f vco f div f ref f p pllstat .findis pllcon 0 . vcoby p m u x 0 1 0 f pll n pk2 ? --------------- f osc ? = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-14 v1.1, 2011-03 32-bit scu, v1.0 of the k2-divider has no impact on the vco lock status but still changes the pll output frequency. note: changing the system operation frequency by changing the value of the k2-divider has a direct coupling to the power consum ption of the device. therefore this has to be done carefully. when the frequency of the normal mode should be modified or entered the following sequence should be followed: first the prescaler mode should be configured and entered. for more details see the prescaler mode. the nmi trap generation for the vco lock should be disabled. while the prescaler mode is used the normal mode can be configured and checked for a positive vco lock status. the first target frequency of the normal mode should be selected in a way that it matches or is only slightly higher as the one used in the prescaler mode. this avoi ds big changes in the syst em operation frequency and therefore power consumption when switching later from prescaler mode to normal mode. the p and n divider should be selected in the following way: ? selecting p and n in a way that f vco is in the lower area of its allowed values leads to a slightly reduced power consumption but to a slightly increased jitter ? selecting p and n in a way that f vco is in the upper area of its allowed values leads to a slightly increased power consumption but to a slightly reduced jitter after the p, n, and k2 dividers are updated for the first configuration the indication of the vco lock status should be await (pllstat.vcolock = 1). note: it is recommended to reset the vco lock detection (pllcon0.resld = 1) after the new values of the dividers are conf igured to get a defined vco lock check time. when this happens the switch from prescaler mode to normal mode can be done. normal mode is requested by clearing pllcon.vcobyp. th e normal mode is entered when the status bit plls tat.vcobyst is cleared. now the normal mode is entered. the nmi status flag for the vco lock trap should be cleared and then enabled again. the intended pll output target frequency can now be configured by changing only the k2-divider. depending on the selected divi der value of the k2-divider the duty cycle of the clock is selected. this can have an impact for the operation with an external communication interface. the duty cycles values for the diffe rent k2-divider values are defined in the data sheet. this can result in multiple changes of the k2-divider to avoid to big frequency changes. between the update of two k2-divider values 6 cycles of f pll should be waited. pll vco lock detection www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-15 v1.1, 2011-03 32-bit scu, v1.0 the pll has a lock detection that supervises the vco part of the pll in order to differentiate between stable and instable vco circuit behavior. the lock detector marks the vco circuit and therefore the output f vco of the vco as instable if the two inputs f ref and f div differ too much. changes in one or both input frequencies below a level are not marked by a loss of lock because the vco can handle such small changes without any problem for the system. pll vco loss-of-lock event the pll may become unlocked, caused by a break of the crystal or the external clock line. in such a case, an nmi trap is generated if the according nmi trap is enabled. additionally, the osc clock input f osc is disconnected from the pll vco to avoid unstable operation due to noise or sporadic clock pulses coming from the oscillator circuit. without a clock input f osc , the pll gradually slows down to its vco base frequency and remains there. this automatic feature can be disabled by setting bit pllcon0.oscdiscdis. if this bit is set the osc clock remains connected to the vco. vco power down mode the pll offers a vco power down mode. this mode can be entered to save power within the pll. the vco power down mode is entered by setting bit pllcon0.vcopwd. while the pll is in vco power down mode only the prescaler mode is operable. please note that selecting the vco power down mode does not automatically switch to the prescaler mode. so before the vco power down mode is entered the prescaler mode must be active. pll power down mode the pll offers a power down mode. this mode can be entered to save power if the pll is not needed at all. the power down mode is entered by setting bit pllcon0.pllpwd. while the pll is in power down mode no pll output frequency is generated. frequency modulation if the pll operates in normal mode the output frequency f pll can additionally be modified by a low-frequency modulation. a triangle waveform is generated and fed to a noiseshaper. the noiseshaper ge nerate a stream of values for the n-divider that are used there to modify (modulate) the n-divider value. due to the low pass function of the pll (vco part) non integer frequencies can be generated by switching fast enough between different values of the n-divider. the modulation is enabled via bit pllcon0.moden. the modulation itself is a triangle- shaped function with an amplitude that can be configured via bit field pllcon2.modamp. setting bit field modamp to zero disables the modulation synchronously. the modulation frequency itself is configurable by bit field pllcon2.modfreq. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-16 v1.1, 2011-03 32-bit scu, v1.0 3.1.1.4 eray phase-locked loop (pll_eray) module the pll_eray can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. the pll_eray also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. it can execute emergency actions if it loses its lock on the external clock. this module is a phase locked loop for integer frequency synthesis. it allows the use of input and output frequencies of a wide range by varying the different divider factors. features ? vco lock detection ? 6-bit feedback divider n : (multiply by ndiv+1) ? 5-bit output divider k1 or k2: (divide by either by k1div+1 or k2div+1) ? different operating modes ? prescaler mode ? freerunning mode ? normal mode ? vco power down (sleep mode) ? glitchless switching between both k-dividers ? glitchless switching between normal mode and prescaler mode pll_eray functional description the pll_eray consists of a voltage controlled oscillator (vco) with a feedback path. a divider in the feedback path (n-divider) divides the vco frequency down. the resulting frequency is then compared with the externally provided frequency. the phase detection logic determines the difference between the two clocks and accordingly controls the frequency of the vco ( f vco ). a pll_eray lock detection unit monitors and signals this condition. the pha se detection logic continues to monitor the two clocks and adjusts the vco clock if required. the pll_eray output clock f pll_eray is derived from the vco clock by the k2-divider or from the oscillator clock and the k1-divider. the following figure shows the pll_eray block structure. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-17 v1.1, 2011-03 32-bit scu, v1.0 figure 3-9 pll_eray block diagram clock source control the pll_eray clock f pll_eray is generated from f osc in one of three software selectable modes: ? bypassing n and both k dividers; this defines the bypass mode ? normal mode ? prescaler mode ? freerunning mode normal mode in normal mode the input frequency f osc is multiplied by a factor n and then divided down by a factor k2. the output frequency is given by (3.8) prescaler mode plleray _ block vco f osc n- divider lock- detection k1- divider m u x f pll_eray f div pller ayc on 0. vcobyp pller ayc on 0. findis f vco f ref plleraystat. vcolock plleraystat. k1rdy pller ayc on 0. vcoldres k2- divider plleraystat. k1rdy pll_eray block f pll n k2 ------- f osc ? = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-18 v1.1, 2011-03 32-bit scu, v1.0 in prescaler mode the reference frequency f osc is only divided down by a factor k1. the output frequency is given by (3.9) freerunning mode in freerunning mode the base frequency output of the voltage controlled oscillator (vco) f vcobase is only divided down by a factor k2. the output frequency is given by (3.10) configuration and operation of the freerunning mode in freerunning mode, the pll_eray is running at its vco base frequency and f pll_eray is derived from f vco only by the k2-divider. the freerunning mode is entered after each system reset. figure 3-10 pll_eray free-running mode diagram f pll f osc k1 -------------- = f pll f vcobase k2 --------------------------- = plleray _freerunning _ m ode .vsd pll_eray block vco k2- divider n- divider lock detect. f pll_eray f vco f div f ref plleraycon 0. vcoby p m u x 0 1 plleraycon 0 .findis '1' www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-19 v1.1, 2011-03 32-bit scu, v1.0 the output frequency is given by (3.11) the freerunning mode is selected by the following settings ? plleraycon0.vcobyp = 0 ? plleraycon0.setfindis = 1 the freerunning mode is entered when ? plleraystat.findis = 1 ?and ? plleraystat.vcobyst = 0 operation on the freerunning mode does not require an input clock frequency of f osc . the freerunning mode is automatically entered on a pll_eray vco loss-of-lock event if bit plleraycon0.oscdiscdis is clea red. this mechanism allows a fail-safe operation of the pll_eray as in emerge ncy cases still a clock is available. the frequency of the freerunning mode f vcobase is listed in the data sheet. depending on the selected divi der value of the k2-divider the duty cycle of the clock is selected. this can have an impact for the operation with an external communication interface. the duty cycles values for the diffe rent k2-divider values are defined in the data sheet. configuration and operation of the prescaler mode in prescaler mode, the pll_eray is running at the external frequency f osc and f pll_eray is derived from f osc only by the k1-divider. f pll f vcobase k2 --------------------------- = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-20 v1.1, 2011-03 32-bit scu, v1.0 figure 3-11 pll_eray prescaler mode diagram the output frequency is given by: (3.12) the prescaler mode is select ed by the following settings ? plleraycon0.vcobyp = 1 the prescaler mode is entered when the following requirements are all together valid: ? plleraystat.vcobyst = 1 ? osccon.plllv = 1 operation on the prescaler mode does require an input clock frequency of f osc . therefore it is recommended to check and monitor if an input frequency f osc is available at all by checking osccon.plllv. for a better monitoring also the upper frequency can be monitored via osccon.pllhv. for the prescaler mode there are no r equirements regarding the frequency of f osc . the system operation frequency is controlled in the prescaler mode by the value of the k1-divider. when the value of plleraycon1.k1div was changed the next update of this value should not be done befo re bit plleraystat.k1rdy is set. depending on the selected divi der value of the k1-divider the duty cycle of the clock is selected. this can have an impact for the operation with an external communication interface. the duty cycles values for the diffe rent k1-divider values are defined in the data sheet. plleray _ n_prescaler _m ode . vsd pll_eray block k1- divider f pll_eray plleraycon0. vcoby p m u x 0 1 f os c f pll f osc k1 -------------- = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-21 v1.1, 2011-03 32-bit scu, v1.0 the prescaler mode is requested from the fr eerunning or normal mode by setting bit plleraycon.vcobyp. the prescaler mode is entered when the status bit plleraystat.vcobyst is set. before the prescaler mode is requested the k1- divider should be configured with a value generating a pll_eray output frequency f pll_eray that matches the one generated by the freerunning or normal mode as much as possible. in this way the frequency change resulting out of the mode change is reduced to a minimum. the prescaler mode is requested to be left by clearing bit plleraycon.vcobyp. the prescaler mode is left when the stat us bit plleraystat.vcobyst is cleared. configuration and operation of the normal mode in normal mode, the pll_eray is running at the external frequency f osc and f pll_eray is multiplied by a factor n and then divided down by a factor k2. figure 3-12 pll_eray normal mode diagram the output frequency is given by: (3.13) the normal mode is selected by the following settings ? plleraycon0.vcobyp = 0 ? plleraycon0.clrfindis = 1 the normal mode is entered when the following two requirements are all together valid: ? plleraystat.findis = 0 plleray _ n_norm al_m ode . vsd pll_eray block f os c vco core k2- divider n- divider lock detect. f pll_eray f vco f div f ref pll eraycon0 .findis pll eraycon 0. vcoby p m u x 0 1 0 f pll n k2 ------- f osc ? = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-22 v1.1, 2011-03 32-bit scu, v1.0 ? plleraystat.vcobyst = 0 ? plleraystat.vcolock = 1 ? osccon.plllv = 1 ? osccon.pllhv = 1 operation on the normal mode does require an input clock frequency of f osc . therefore it is recommended to check and monitor if an input frequency f osc is available at all by checking osccon.plllv. for a better monitoring also the upper frequency can be monitored via osccon.pllhv. the system operation frequency is controlled in the normal mode by the values of the two dividers: n and k2. a modification of the divider n has a direct influence to the vco frequency and lead to a loss of the vco lock status. a modification of the k2-divider has no impact on the vco lock status but still changes the pll_eray output frequency. when the frequency of the normal mode should be modified or entered the following sequence should be followed: first the prescaler mode should be configured and entered. for more details see the prescaler mode. the nmi trap generation for the vco lock should be disabled. while the prescaler mode is used the normal mode can be configured and checked for a positive vco lock status. the first target frequency of the normal mode should be selected in a way that it matches or is only slightly higher as the one used in the prescaler mode. this avoi ds big changes in the syst em operation frequency and therefore power consumption when switching later from prescaler mode to normal mode. the n divider should be selected in the following way: ? selecting n in a way that f vco is in the lower area of its allowed values leads to a slightly reduced power consumption but to a slightly increased jitter ? selecting n in a way that f vco is in the upper area of its allowed values leads to a slightly increased power consumption but to a slightly reduced jitter after the n and k2 dividers are updated for the first configuration the indication of the vco lock status should be aw ait (plleraystat.vcolock = 1). note: it is recommended to reset the vco lock detection (pll eray con0.resld = 1) after the new values of the dividers are configured to get a defined vco lock check time. when this happens the switch from prescaler mode to normal mode can be done. normal mode is requested by clearing plleraycon.vcobyp. the normal mode is entered when the status bit plleraystat.vcobyst is cleared. now the normal mode is entered. the nmi status flag for the vco lock trap should be cleared and then enabled again. the intended pll_eray output target frequency can not be configured by changing only the k2-divider. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-23 v1.1, 2011-03 32-bit scu, v1.0 depending on the selected divi der value of the k2-divider the duty cycle of the clock is selected. this can have an impact for the operation with an external communication interface. the duty cycles values for the diffe rent k2-divider values are defined in the data sheet. this can result in multiple changes of the k2-divider to avoid to big frequency changes. between the update of two k2-divider values 6 cycles of f pll_eray should be waited. pll_eray vco lock detection the pll_eray has a lock detection that supervises the vco part of the pll_eray in order to differentiate between stable and instable vco circuit behavior. the lock detector marks the vco circuit and therefore the output f vco of the vco as instable if the two inputs f ref and f div differ too much. changes in one or both input frequencies below a level are not marked by a loss of lock because the vco can handle such small changes without any proble m for the system. pll_eray vco lo ss-of-lock event the pll_eray may become unlocked, caused by a break of the crystal or the external clock line. in such a case, an nmi trap is generated if the according nmi trap is enabled. additionally, the osc clock input f osc is disconnected from the pll_eray vco to avoid unstable operation due to noise or sporadic clock pulses coming from the oscillator circuit. without a clock input f osc , the pll_eray gradually slows down to its vco base frequency and remains there. this automatic feature can be disabled by setting bit plleraycon0.oscdiscdis. if this bit is cleared the osc clock remains connected to the vco. vco power down mode the pll_eray offers a vco power down mode. this mode can be entered to save power within the pll_eray. the vco power down mode is entered by setting bit pllcon0.vcopwd. while the pll_eray is in vco power down mode only the prescaler mode is operable. please note that selecting the vco power down mode does not automatically switch to the prescaler mode. so before the vco power down mode is enter the prescaler mode must be active. pll_eray power down mode the pll_eray offers a power down mode. this mode can be entered to save power if the pll_eray is not needed at all. the power down mode is entered by setting bit pllcon0.pllpwd. while the pll_eray is in power down mode no pll_eray output frequency is generated. 3.1.1.5 clock control unit the clock control unit (ccu) receives the clock that is created by the two plls f pll and f pll_eray . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-24 v1.1, 2011-03 32-bit scu, v1.0 figure 3-13 clock control unit the clocking system of the tc 1798 consists of the clock control unit (ccu) and the clock generation unit. there is also a fix reference clock refclk1 for the mcds block which divides the master clock f pll by 24. this allows the mcds to generate time stamps independent of the selected sri-bus and fpi-bus clock speeds. clock divider limitations the following table defines the allowed clock ratios for the application relevant clocks. the values given in the table define values for the bit fields of register ccucon0. f pll ccu f pll fpidiv sridiv mcdsdiv pcpdiv f fpi f mcds f sri f pcp ccu_block . f pll _eray f pll _ eray refclk f refclk2 refclk f refclk1 edbbbdiv f bbb fsidiv f fsi eraydiv f eray ebudiv f ebu www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-25 v1.1, 2011-03 32-bit scu, v1.0 note: ccucon1.edbbbdiv and ccucon1.mcdsdiv should always be set to sri / cpu speed divided by two. for changing the clock frequencies it is recommanded to follow the sequence described in figure 3-14 . table 3-1 allowed clock ratios register name option 1 option 2 option 3 option 4 sridiv 0010 fsidiv 0131 pcpdiv 0021 fpidiv 0153 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-26 v1.1, 2011-03 32-bit scu, v1.0 figure 3-14 clock changing sequence 3.1.1.6 external clock output two external clock outputs are provided via pins extclk0 and extclk1. these external clocks can be enabled/disabled via bits extcon.en0 for extclk0 and startup flow setup pll lock operation f pll <= f _fpi_max configure target divider settings by single write access to ccucon0 and ccucon1 (optional) subsequently increase f pll using k2 divider pllconx activate fm feature of pll speed-up re-configure (slow down first) subsequently decrease f pll using k2 divider pllconx de-activate fm feature of pll configure 1:1:1 divider settings by single write access to ccucon0 and ccucon1 (optional) return to ramp up (optional) ready for clock configuration optional porst startup flow configures system clock to freerunning mode TC1798 clock setup/re-configuration sequence 1 reset requests will be stored either via trap routines and processed after the clock setup procedure or mapped to an applicatio n reset. traps are allowed (valid trap handler system available, rampup sequence not reentrant). optional deactivate reset execution 1. re-route esr0 request to trap 2. deactivate system reset execution in rstcon re-activate reset execution 1. re-activate reset execution in rstcon 2. issue reset in case of a pending request application reset ? reconfigure clock system to initial state no application reset system reset yes startup flow leaves clock system untouched context restrictions: - no interrupts - no immediate system reset execution (porst and application reset are allowed ) 1 - only p-flash read - no d-flash activity - no sleep mode - peripheral activity should be reduced to minimum (timing of protocols unreliable ) - pcp inactive (no bus transactions, no memory access) trap handler any trap www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-27 v1.1, 2011-03 32-bit scu, v1.0 extcon.en1 for extclk1. each of the cl ocks that defines a clock domain can individually be selected to be seen at pins extclk0 or extclk1, this is configured via bit field extcon.sel0/1. changing the content of bit field extcon.sel0/1 can lead to spikes at pins extclk0/1. note: only the burst flash clock of the ebu is not included as the ebu provides a separate pin here. additionally a connection to the gpta modul e is implemented to support the start-up control of an external crystal for the device clock generation. the first time before the master clock is generated based on a external crystal 1000 cycles of the crystal clock f osc should be waited before the clock control system is changed to external crystal mode. the 1000 cycles can be co unted with the gpta using f osc as count input for the counter. programmable frequency output for extclk0 this section describes the external clock generation using the fractional divider. figure 3-15 extclk0 generation extclk . extcon.en0 f ma m u x p1.12 extcon.sel0 f out to gpta [in0] f fpi reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved p2.8 mux extcon. gptainsel f osc fractional divider fdr f mt eray mt f pll _eray www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-28 v1.1, 2011-03 32-bit scu, v1.0 overview the fractional divider makes it possible to generate a external clock from the fpi-bus clock using a programmable divider. the fr actional divider divides the input clock f fpi either by the factor 1/n or by a fraction of n/1024 for any value of n from 0 to 1023. this clock is thereafter divider additionally by a factor of two to guarantee a 50% duty cycle and outputs the clock, f out . the fractional divider is c ontrolled by the fdr register. figure 3-16 shows the fractional divider block diagram. the adder logic of the fractional divider can be configured for two operating modes: ? reload counter (addition of +1), generating an output clock pulse on counter overflow ? adder that adds a step value to the result value and generates an output clock pulse on counter overflow figure 3-16 fractional divider block diagram the adder logic of the fractional divider can be configured for two operating modes: ? normal mode: reload counter (result = result + 1), generating an output clock pulse on counter overflow. ? fractional divider mode: adder that adds a step value to the result value and generates an output clock pulse on counter overflow. fractional divider operating modes the fractional divider has two operating modes: mcb05604 m f fpi f out result (10-bit) step (10-bit) mux adder mux 1 external clock enable reset external divider control f out enable & fractional divider 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-29 v1.1, 2011-03 32-bit scu, v1.0 ? normal divider mode ? fractional divider mode normal divider mode in normal divider mode (fdr.dm = 01 b ), the fractional divider behaves as a reload counter (addition of +1) that generates an output clock pulse on the transition from 3ff h to 000 h . fdr.result represents the counter value and fdr.step determines the reload value. the output frequencies in normal divider mode are defined according to the following formulas: (3.14) in order to get f out = f fpi /2 step must be programmed with 3ff h . fractional divider mode when the fractional divider mode is selected (fdr.dm = 10 b ), the output is derived from the input clock f fpi by division of a fraction of n/1024 for any value of n from 0 to 1023 followed by the division of two. in general, the fractional divider mode makes it possible to program the average output clock frequency with a higher accuracy than in normal divider mode. in fractional divider mode, a pulse is generated depending on the result of the addition fdr.result + fdr.step. if the addition leads to an overflow over 3ff h , a pulse is generated for the divider by two. note that in fractional divider mode the clock f out can have a maximum period jitter of one f fpi clock period. the output frequencies in fractional divider mode are defined according to the following formulas: , with n = 0-1023 (3.15) external cl ock enable when the external clock generation with t he fractional divider has been disabled by software (setting fdr.disclk = 1), the disable state can be exited (hardware controlled) when the external clock enable input = 1. f out f fpi 1 n -- - 2 ------------------ - = , with n = 1024 - step f out f fpi n 1024 ------------ - 2 ---------------------------- - = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-30 v1.1, 2011-03 32-bit scu, v1.0 programmable frequency output for extclk1 figure 3-17 extclk1 generation clock f out is generated via a counter, so the output frequency can be selected in small steps. f out always provides complete output periods. register extcon provides control over t he output generation (frequency, activation). extclk . extcon.en1 f ma m u x p1.0 extcon.sel1 f out extcon.div1 f fpi reserved reserved 1 m u x reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved extcon.nsel f osc f pll _eray www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-31 v1.1, 2011-03 32-bit scu, v1.0 3.1.1.7 cgu registers system oscillator register this register controls the settings of osc. osccon osc control register (010 h ) reset value: 0000 021a h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 oscval rrw 1514131211109876543210 0 x1d en x1d pll sp pll hv 0 mode gainsel osc res pll lv 0 r rwrhrhrhrw rw rh wrh field bits type description plllv 1rh oscillator for pll valid low status bit this bit indicates if the frequency output of osc is usable for the vco part of the pll. this is checked by the oscillator watchdog of the pll. 0 b the osc frequency is not usable. frequency f ref is too low. 1 b the osc frequency is usable oscres 2w oscillator watchdog reset 0 b the oscillator watchdog of the pll is not cleared and remains active 1 b the oscillator watchdog of the pll is cleared and restarted gainsel [4:3] rw oscillator gain selection 00 b reserved, do not use this combination 01 b the gain control is configured for frequencies from 8 mhz to 16 mhz 10 b the gain control is configured for frequencies from 8 mhz to 20 mhz 11 b the gain control is configured for frequencies from 8 mhz to 25 mhz www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-32 v1.1, 2011-03 32-bit scu, v1.0 mode [6:5] rw oscillator mode this bit field defines which mode can be used and if the oscillator entered the power-s aving mode or not. 00 b external crystal mode and external input clock mode. the oscillator power-saving mode is not entered. 01 b osc is disabled. the oscillator power-saving mode is not entered. 10 b external input clock mode and the oscillator power-saving mode is entered 11 b osc is disabled. the oscillator power-saving mode is entered. pllhv 8rh oscillator for pll valid high status bit this bit indicates if the frequency output of osc is usable for the vco part of the pll. this is checked by the oscillator watchdog of the pll. 0 b the osc frequency is not usable. frequency f osc is too high. 1 b the osc frequency is usable pllsp 9rh oscillator for pll valid spike status bit this bit indicates if the frequency output of osc is usable for the vco part of the pll. this is checked by the oscillator watchdog of the pll. 0 b the osc frequency is not usable. spikes are detected that disturb a locked operation 1 b the osc frequency is usable x1d 10 rh xtal1 data value this bit monitors the value (level) of pin xtal1. if xtal1 is not used as clock input it can be used as gpi pin. this bit is only upda ted if x1den is set. x1den 11 rw xtal1 data enable 0 b bit x1d is not updated 1 b bit x1d can be updated field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-33 v1.1, 2011-03 32-bit scu, v1.0 pll registers these registers control the setting of the pll. oscval [20:16] rw osc frequency value this bit field defines the divider value that generates the reference clock that is supervised by the oscillator watchdog. f osc is divided by oscval + 1 in order to generate f oscref . 0 7rw reserved should be written with 0. 0 0, [15:12] , [31:21] r reserved read as 0; should be written with 0. pllstat pll status register (014 h ) reset value: 0000 0038 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 mod run 0 k2r dy k1r dy fin dis vco loc k pwd sta t vco by st r rh r rh rh rh rh rh rh field bits type description vcobyst 0rh vco bypass status 0 b freerunning / normal mode is entered 1 b prescaler mode is entered pwdstat 1rh pll power-saving mode status 0 b pll power-saving mode was not entered 1 b pll power-saving mode was entered field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-34 v1.1, 2011-03 32-bit scu, v1.0 vcolock 2rh pll vco lock status 0 b the frequency difference of f ref and f div is greater than allowed. the vco part of the pll can not lock on a target frequency. 1 b the frequency difference of f ref and f div is small enough to enable a stable vco operation. note: in case of a loss of vco lock the f vco goes to the upper boundary of the vco frequency if the reference clock input is greater than expected. note: in case of a loss of vco lock the f vco goes to the lower boundary of the vco frequency if the reference clock input is lower than expected. findis 3rh input clock disconnect select status 0 b the input clock from the oscillator is connected to the vco part 1 b the input clock from the oscillator is disconnected from the vco part note: this bit can be set by setting bit pllcon0.setfindis. note: this bit can be cleared by setting bit pllcon0.clrfindis. k1rdy 4rh k1 divider ready status this bit indicates if the k1-divider operates on the configured value or not. this is of interest if the values is changed. 0 b k1-divider is not ready to operate with the new value 1 b k1-divider is ready to operate with the new value field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-35 v1.1, 2011-03 32-bit scu, v1.0 k2rdy 5rh k2 divider ready status this bit indicates if the k2-divider operates on the configured value or not. this is of interest if the values is changed. 0 b k2-divider is not ready to operate with the new value 1 b k2-divider is ready to operate with the new value modrun 7rh modulation run this bit indicates if the frequency modulation of the pll is activated or not. 0 b frequency modulation is not active 1 b frequency modulation is active 0 6, [31:8] r reserved read as 0; should be written with 0. pllcon0 pll configuration 0 register (018 h ) reset value: 0001 c600 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0pdiv 0 res ld 01 rw rw r w r rw 1514131211109876543210 ndiv 0 0 osc disc dis clr fin dis set fin dis 0 mod en vco pwd vco byp rw rw r rw w w rwrwrwrw field bits type description vcobyp 0rw vco bypass 0 b normal operation, vco is not bypassed 1 b prescaler mode; vco is bypassed field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-36 v1.1, 2011-03 32-bit scu, v1.0 vcopwd 1rw vco power saving mode 0 b normal behavior 1 b the vco is put into a power saving mode and can no longer be used. only prescaler mode are active if previously selected. moden 2rw modulation enable this bit controls the activation of the frequency modulation of the pll. 0 b frequency modulation is not activated 1 b frequency modulation is activated setfindis 4w set status bit pllstat.findis 0 b bit pllstat.findis is left unchanged 1 b bit pllstat.findis is set. the input clock from the oscillator is disconnected from the vco part. clrfindis 5w clear status bit pllstat.findis 0 b bit pllstat.findis is left unchanged 1 b bit pllstat.findis is cleared. the input clock from the oscillato r is connec ted to the vco part. oscdiscdis 6rw oscillator disconnect disable this bit is used to disable the control pllstat.findis in a pll loss-of-lock case. 0 b in case of a pll loss-of-lock bit pllstat.findis is set 1 b in case of a pll loss-of-lock bit pllstat.findis is cleared ndiv [15:9] rw n-divider value the value the n-divider operates is ndiv+1. resld 18 w restart vco lock detection setting this bit will clea r bit pllstat.vcolock and restart the vco lock detection. reading this bit returns always a zero. pdiv [27:24] rw p-divider value the value the p-divider operates is pdiv+1. 0 3, 8, [31:28] rw reserved have to be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-37 v1.1, 2011-03 32-bit scu, v1.0 1 16 rw reserved should be written with 1. 0 7, 17, [23:19] r reserved read as 0; should be written with 0. pllcon1 pll configuration 1 register (01c h ) reset value: 0002 000f h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0k1div rrw 1514131211109876543210 0k2div rrw field bits type description k2div [6:0] rw k2-divider value the value the k2-divider operates is k2div+1. k1div [22:16] rw k1-divider value the value the k1-divider operates is k1div+1. 0 [15:7], [31:23] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-38 v1.1, 2011-03 32-bit scu, v1.0 pll_eray registers these registers controls the setting of the pll_eray. pllcon2 pll configuration 2 register (020 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 modfreq rw 1514131211109876543210 modamp rw field bits type description modamp [15:0] rw modulation amplitude this bit field defines the amplitude of the modulation. modfreq [31:16] rw modulation frequency this bit field defines the modulation frequency. plleraystat pll_eray status register (024 h ) reset value: 0000 0038 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 k2r dy k1r dy fin dis vco loc k pwd sta t vco by st r rhrhrhrhrhrh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-39 v1.1, 2011-03 32-bit scu, v1.0 field bits type description vcobyst 0rh vco bypass status 0 b freerunning / normal mode is entered 1 b prescaler mode is entered pwdstat 1rh pll_eray power-saving mode status 0 b pll_eray power-saving mode was not entered 1 b pll_eray power-saving mode was entered vcolock 2rh pll vco lock status 0 b the frequency difference of f ref and f div is greater than allowed. the vco part of the pll_eray can not lock on a target frequency. 1 b the frequency difference of f ref and f div is small enough to enable a stable vco operation. note: in case of a loss of vco lock the f vco goes to the upper boundary of the vco frequency if the reference clock input is greater than expected. note: in case of a loss of vco lock the f vco goes to the lower boundary of the vco frequency if the reference clock input is lower than expected. findis 3rh input clock disconnect select status 0 b the input clock from the oscillator is connected to the vco part 1 b the input clock from the oscillator is disconnected from the vco part note: this bit can be set by setting bit pll eraycon0 .setfindis. note: this bit can be cleared by setting bit pll eraycon0 .clrfindis. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-40 v1.1, 2011-03 32-bit scu, v1.0 k1rdy 4rh k1 divider ready status this bit indicates if the k1-divider operates on the configured value or not. this is of interest if the values is changed. 0 b k1-divider is not ready to operate with the new value 1 b k1-divider is ready to operate with the new value k2rdy 5rh k2 divider ready status this bit indicates if the k2-divider operates on the configured value or not. this is of interest if the values is changed. 0 b k2-divider is not ready to operate with the new value 1 b k2-divider is ready to operate with the new value 0 [31:6] r reserved read as 0; should be written with 0. plleraycon0 pll_eray configuration 0 register (028 h ) reset value: 0001 2e00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 res ld 01 rwrrw 1514131211109876543210 00 ndiv 0 osc disc dis clr fin dis set fin dis 0 vco pwd vco byp rrw rw r rwww r rwrw field bits type description vcobyp 0rw vco bypass 0 b normal operation, vco is not bypassed 1 b prescaler mode; vco is bypassed field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-41 v1.1, 2011-03 32-bit scu, v1.0 vcopwd 1rw vco power saving mode 0 b normal behavior 1 b the vco is put into a power saving mode and can no longer be used. setfindis 4w set status bit pl leraystat.findis 0 b bit plleraystat.findis is left unchanged 1 b bit plleraystat.findis is set. the input clock from the oscillato r is disconnected from the vco part. clrfindis 5w clear status bit plleraystat.findis 0 b bit plleraystat.findis is left unchanged 1 b bit plleraystat.findi s is cleared. the input clock from the oscillator is connected to the vco part. oscdiscdis 6rw oscillator disconnect disable this bit is used to disable the control plleraystat.findis in a pll_eray loss-of-lock case. 0 b in case of a pll loss-of-lock bit plleraystat.findis is set 1 b in case of a pll loss-of-lock bit plleraystat.findi s is cleared ndiv [13:9] rw n-divider value the value the n-divider operates is (ndiv+1). resld 18 w restart vco lock detection setting this bit will clear bit plleraystat.vcolock a nd restart the vco lock detection. reading this bit returns always a zero. 0 14 rw reserved should be written with 0. 1 16 rw reserved should be written with 1. 0 [3:2], [8:7], 15, 17, [31:19] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-42 v1.1, 2011-03 32-bit scu, v1.0 ccu control registers plleraycon1 pll_eray configuration 1 register (02c h ) reset value: 000f 000f h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0k1div rrw 1514131211109876543210 0k2div rrw field bits type description k2div [6:0] rw k2-divider value the value the k2-divider operates is k2div+1. k1div [22:16] rw k1-divider value the value the k1-divider operates is k1div+1. 0 [15:7], [31:23] r reserved read as 0; should be written with 0. ccucon0 ccu clock control register 0 (030 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lck 0 pcpdiv 0 fsidiv rh r rw r rw 1514131211109876543210 0 sridiv 0 fpidiv rrwrrw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-43 v1.1, 2011-03 32-bit scu, v1.0 field bits type function fpidiv [3:0] rw fpi-bus divider reload value 0000 b f fpi = f pll 0001 b f fpi = f pll /2 0010 b f fpi = f pll /3 0011 b f fpi = f pll /4 0100 b f fpi = f pll /5 0101 b f fpi = f pll /6 0110 b f fpi = f pll /7 0111 b f fpi = f pll /8 1000 b f fpi = f pll /9 1001 b f fpi = f pll /10 1010 b f fpi = f pll /11 1011 b f fpi = f pll /12 1100 b f fpi = f pll /13 1101 b f fpi = f pll /14 1110 b f fpi = f pll /15 1111 b f fpi = f pll /16 sridiv [11:8] rw sri-bus divider reload value 0000 b f sri = f pll 0001 b f sri = f pll /2 0010 b f sri = f pll /3 0011 b f sri = f pll /4 0100 b f sri = f pll /5 0101 b f sri = f pll /6 0110 b f sri = f pll /7 0111 b f sri = f pll /8 1000 b f sri = f pll /9 1001 b f sri = f pll /10 1010 b f sri = f pll /11 1011 b f sri = f pll /12 1100 b f sri = f pll /13 1101 b f sri = f pll /14 1110 b f sri = f pll /15 1111 b f sri = f pll /16 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-44 v1.1, 2011-03 32-bit scu, v1.0 fsidiv [19:16] rw fsi divider reload value 0000 b f fsi = f pll 0001 b f fsi = f pll /2 0010 b f fsi = f pll /3 0011 b f fsi = f pll /4 0100 b f fsi = f pll /5 0101 b f fsi = f pll /6 0110 b f fsi = f pll /7 0111 b f fsi = f pll /8 1000 b f fsi = f pll /9 1001 b f fsi = f pll /10 1010 b f fsi = f pll /11 1011 b f fsi = f pll /12 1100 b f fsi = f pll /13 1101 b f fsi = f pll /14 1110 b f fsi = f pll /15 1111 b f fsi = f pll /16 pcpdiv [27:24] rw pcp divider reload value 0000 b f pcp = f pll 0001 b f pcp = f pll /2 0010 b f pcp = f pll /3 0011 b f pcp = f pll /4 0100 b f pcp = f pll /5 0101 b f pcp = f pll /6 0110 b f pcp = f pll /7 0111 b f pcp = f pll /8 1000 b f pcp = f pll /9 1001 b f pcp = f pll /10 1010 b f pcp = f pll /11 1011 b f pcp = f pll /12 1100 b f pcp = f pll /13 1101 b f pcp = f pll /14 1110 b f pcp = f pll /15 1111 b f pcp = f pll /16 lck 31 rh lock status this bit indicates if the register can be updated with a new value or if the register is locked and a write action from the bus side has no effect. 0 b the register is unlocked and can be updated 1 b the register is locked and can not be updated field bits type function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-45 v1.1, 2011-03 32-bit scu, v1.0 0 [7:4], [15:12] , [23:20] , [30:28] r reserved read as 0; should be written with 0. ccucon1 ccu clock control register 1 (034 h ) reset value: 0005 0b03 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lck 0 edbbbdiv rh r rw 1514131211109876543210 0 refclkdiv 0 mcdsdiv rrrrw field bits type function mcdsdiv [3:0] rw mcds divider reload value 0000 b f mcds = f pll 0001 b f mcds = f pll /2 0010 b f mcds = f pll /3 0011 b f mcds = f pll /4 0100 b f mcds = f pll /5 0101 b f mcds = f pll /6 0110 b f mcds = f pll /7 0111 b f mcds = f pll /8 1000 b f mcds = f pll /9 1001 b f mcds = f pll /10 1010 b f mcds = f pll /11 1011 b f mcds = f pll /12 1100 b f mcds = f pll /13 1101 b f mcds = f pll /14 1110 b f mcds = f pll /15 1111 b f mcds = f pll /16 field bits type function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-46 v1.1, 2011-03 32-bit scu, v1.0 refclkdiv [11:8] r reference clock for mcds divider reload value 0000 b f refclk2 = f pll_eray /2 and f refclk1 = f pll /2 0001 b f refclk2 = f pll_eray /4 and f refclk1 = f pll /4 0010 b f refclk2 = f pll_eray /6 and f refclk1 = f pll /6 0011 b f refclk2 = f pll_eray /8 and f refclk1 = f pll /8 0100 b f refclk2 = f pll_eray /10 and f refclk1 = f pll /10 0101 b f refclk2 = f pll_eray /12 and f refclk1 = f pll /12 0110 b f refclk2 = f pll_eray /14 and f refclk1 = f pll /14 0111 b f refclk2 = f pll_eray /16 and f refclk1 = f pll /16 1000 b f refclk2 = f pll_eray /18 and f refclk1 = f pll /18 1001 b f refclk2 = f pll_eray /20 and f refclk1 = f pll /20 1010 b f refclk2 = f pll_eray /22 and f refclk1 = f pll /22 1011 b f refclk2 = f pll_eray /24 and f refclk1 = f pll /24 1100 b f refclk2 = f pll_eray /26 and f refclk1 = f pll /26 1101 b f refclk2 = f pll_eray /28 and f refclk1 = f pll /28 1110 b f refclk2 = f pll_eray /30 and f refclk1 = f pll /30 1111 b f refclk2 = f pll_eray /32 and f refclk1 = f pll /32 edbbbdiv [19:16] rw ed part backbone bus divider reload value 0000 b f bbb = f pll 0001 b f bbb = f pll /2 0010 b f bbb = f pll /3 0011 b f bbb = f pll /4 0100 b f bbb = f pll /5 0101 b f bbb = f pll /6 0110 b f bbb = f pll /7 0111 b f bbb = f pll /8 1000 b f bbb = f pll /9 1001 b f bbb = f pll /10 1010 b f bbb = f pll /11 1011 b f bbb = f pll /12 1100 b f bbb = f pll /13 1101 b f bbb = f pll /14 1110 b f bbb = f pll /15 1111 b f bbb = f pll /16 lck 31 rh lock status this bit indicates if the register can be updated with a new value or if the register is locked and a write action from the bus side has no effect. 0 b the register is unlocked and can be updated 1 b the register is locked and can not be updated field bits type function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-47 v1.1, 2011-03 32-bit scu, v1.0 0 [7:4], [15:12], [30:20] r reserved read as 0; should be written with 0. ccucon2 ccu clock control register 2 (044 h ) reset value: 0000 0001 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lck 0 rh r 1514131211109876543210 0 ebudiv 0 eraydiv rrwrrw field bits type function eraydiv [3:0] rw eray-bus divider reload value 0000 b f eray = f pll_eray 0001 b f eray = f pll_eray /2 0010 b f eray = f pll_eray /3 0011 b f eray = f pll_eray /4 0100 b f eray = f pll_eray /5 0101 b f eray = f pll_eray /6 0110 b f eray = f pll_eray /7 0111 b f eray = f pll_eray /8 1000 b f eray = f pll_eray /9 1001 b f eray = f pll_eray /10 1010 b f eray = f pll_eray /11 1011 b f eray = f pll_eray /12 1100 b f eray = f pll_eray /13 1101 b f eray = f pll_eray /14 1110 b f eray = f pll_eray /15 1111 b f eray = f pll_eray /16 field bits type function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-48 v1.1, 2011-03 32-bit scu, v1.0 clock output control register this register controls the setting of external clock for pin 1.0 and 1.12 (extclk0 and extclk1). ebudiv [11:8] rw ebu-bus divider reload value 0000 b f ebu = f pll_eray 0001 b f ebu = f pll_eray /2 0010 b f ebu = f pll_eray /3 0011 b f ebu = f pll_eray /4 0100 b f ebu = f pll_eray /5 0101 b f ebu = f pll_eray /6 0110 b f ebu = f pll_eray /7 0111 b f ebu = f pll_eray /8 1000 b f ebu = f pll_eray /9 1001 b f ebu = f pll_eray /10 1010 b f ebu = f pll_eray /11 1011 b f ebu = f pll_eray /12 1100 b f ebu = f pll_eray /13 1101 b f ebu = f pll_eray /14 1110 b f ebu = f pll_eray /15 1111 b f ebu = f pll_eray /16 lck 31 rh lock status this bit indicates if the register can be updated with a new value or if the register is locked and a write action from the bus side has no effect. 0 b the register is unlocked and can be updated 1 b the register is locked and can not be updated 0 [7:4], [30:12] r reserved read as 0; should be written with 0. field bits type function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-49 v1.1, 2011-03 32-bit scu, v1.0 extcon external clock control register (03c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 div1 0 sel1 n sel en1 rw r rw rw rw 1514131211109876543210 0 gpt ains el sel0 0 en0 rrwrwrrw field bits type description en0 0rw external clock en able for extclk0 0 b no external clock is provided 1 b the configured external clock is provided sel0 [5:2] rw external clock se lect for extclk0 this bit field defines the clock source that is selected as output for pin extclk0. 0000 b f out is selected for the external clock 0001 b f pll is selected for the external clock 0010 b reserved, do not use this combination ... 0110 b reserved, do not use this combination 0111 b f pll_eray is selected for the external clock signal 1000 b f osc is selected for the external clock signal 1001 b reserved, do not use this combination ... 1110 b reserved, do not use this combination 1111 b f mt from the eray module is selected for the external clock www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-50 v1.1, 2011-03 32-bit scu, v1.0 gptainsel 6rw gpta input select this value defines if either the input from p2.8 or the configured output frequency for extclk0 is used as input for in0 of the gpta module. 0 b p2.8 is selected as input for in0 of the gpta 1 b extclk0 output is selected as input for in0 of the gpta en1 16 rw external clock en able for extclk1 0 b no external clock is provided 1 b the configured external clock is provided nsel 17 rw negation selection 0 b the external clock is inverted 1 b the external clock is not inverted sel1 [21:18] rw external clock se lect for extclk1 this bit field defines the clock source that is selected as output for pin extclk1. 0000 b f out is selected for the external clock 0001 b f pll is selected for the external clock 0010 b reserved, do not use this combination ... 0110 b reserved, do not use this combination 0111 b f pll_eray is selected for the external clock signal 1000 b f osc is selected for the external clock signal 1001 b reserved, do not use this combination ... 1111 b reserved, do not use this combination div1 [31:24] rw external clock divider for extclk1 this value defines the reload value of the divider that generates f out out of f fpi ( f out = f fpi /(div1+1)). the divider itself is cleared each time bit en1 is cleared. 0 1, [15:7], [23:22] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-51 v1.1, 2011-03 32-bit scu, v1.0 fdr fractional divider register (038 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dis clk 0result rwh r rh 1514131211109876543210 dm 0 step rw r rw field bits type description step [9:0] rw step value in normal divider mode, step contains the reload value for result. in fractional divider mode, this bit field determines the 10-bit value that is added to result with each input clock cycle. dm [15:14] rw divider mode this bit fields determines the functionality of the fractional divider block. 00 b fractional divider is switched off; no output clock is generated. the reset external divider signal is 1. result is not updated (default after system reset). 01 b normal divider mode selected. 10 b fractional divider mode selected. 11 b fractional divider is switched off; no output clock is generated. result is not updated. result [25:16] rh result value in normal divider mode, result acts as reload counter (addition +1). in fractional divider mode, this bit field contains the result of the addition result + step. if dm is written with 01 b or 10 b , result is loaded with 3ff h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-52 v1.1, 2011-03 32-bit scu, v1.0 disclk 31 rwh disable clock 0 b clock generation of f out is enabled according to the setting of bit field dm. 1 b fractional divider is stopped. no change except when writing bit field dm. this bit is cleared when external clock enable input is asserted. in case of a conflict between hardware clear and software set of disclk, th e software set wins. any write or read-modify-write action leads to the described behavior. as a result, read-modify-write operations should be avoided. 0 [13:10], [30:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-53 v1.1, 2011-03 32-bit scu, v1.0 3.1.2 module clock generation the TC1798 on-chip modules have two registers for clock control: ? clock control register clc ? fractional divider register fdr the following sections describes the general functionality of clc and fdr. the module- specific implementation details are desc ribed in the corresponding module chapters. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-54 v1.1, 2011-03 32-bit scu, v1.0 3.1.2.1 clock control register clc all clc registers have basically the same bit and bit field layout. however, not all clc register functions are implemen ted for each peripheral module. table 3-2 defines in detail which bits and bit fields of the clc registers are implemented for each clock control register. the clc register controls the generation of the peripheral module clock which is derived from the system clock. the fo llowing functions for the modu le are associ ated with the clc register: ? peripheral clock static on/off control ? module clock behavior in sleep mode ? operation during suspend mode ? fast shut-off mode control module enable/disable control if a module is not used at all by an application, it can be completely shut off by setting bit disr in its clc register. for peripheral modules with a run mode clock divider field rmc, a second option to completely switch off the module is to set bit field rmc to 00 h . this also disables the module?s operation. the status bit diss always indicates whether a module is currently switched off (diss = 1) or switched on (diss = 0). write operations to the non clc registers of disabled modules are not allowed. however, the clc of a disabled module can be written. an attempt to write to any of the other writable registers of a disabled module except clc will cause the corresponding bus control unit (bcu) to generate a bus error. a read operation of registers of a disabled module is allowed and does not generate a bus error. when a disabled module is switched on by writing an appropriate value to its mod_clc register (disr = 0 and rmc (if implemented) > 0), status bit diss changes from 1 to 0. during the phase in which the module becomes active, any write access to corresponding module registers (when diss is still set) will generate a bus error. therefore, when enabling a disabled module, application software should check after activation of the module once (read back of the clc register) to find out whether diss is already cleared, before a module register (including the clc register) will be written to. sleep mode control the edis bit in the clc register controls whether or not a module is stopped during sleep mode. if edis is 0, a sleep mode request can be recognized by the module and, when received, its clock is shut off. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-55 v1.1, 2011-03 32-bit scu, v1.0 if edis is set to 1, a sleep mode request is disregarded by the module and the module continues its operation. suspend mode control during emulation and debugging of TC1798 applications, the execution of an application program can be suspended. when an application is suspended, normal operation of the application?s program is halted, and the tc 1798 begins (or resumes) executing a special debug monitor program. if bit spen is set, the operation of the peripheral module is stopped when the suspend mode request is generated. if spen is cleared, the module does not react to the suspend mode request and continues its normal operation. this feature allows each peripheral module to be adapted to the unique requirements of the application being debugged. setting spen bits is usually performed by a debugger. this feature is necessary because applicat ion requirements typically determine whether on-chip modules should be stopped or left running when an application is suspended for debugging. for example, a peripheral unit that is controlling the motion of an external device through motors in most cases must not be stopped so as to prevent damage of the external device due to the loss of control through the peripheral. on the other hand, it makes sense to stop the system timer while the debugger is actively controlling the chip because it should only count the time when the user?s application is running. note that it is never appropriate for application software to set the spen bit. the suspend mode should only be set by a debug software. to guard against application software accidently setting spen, bit spen is specially protec ted by the mask bit sbwe. the spen bit can only be written if, during the same write operation, sbwe is set, too. application software should never set sbwe. in this way, user software can not accidentally alter the va lue of the spen bit that has been set by a debugger. entering disabled mode software can request that a peripheral unit be put into disabled mode by setting disr. a module will also be put into disabled mode if the sleep mode is requested and the module is configured to allow sleep mode. in secure shut-off mode, a module firs t finishes any operation in progress, then proceeds with an orderly shut down. when al l sub-components of the module are ready to be shut down, the module signals its clock control unit, that turns off the clock to this peripheral unit, that it is now ready for shut down. the status bit diss is updated by the peripheral unit accordingly. during emulation and debugging, it may be necessary to monitor the instantaneous state of the machine ? including all or most of its modules ? at the moment a software breakpoint is reached. in such cases, it ma y not be desired that the kernel of a module finish whatever transaction is in progress before stopping, because that might cause important states in this module to be lost. fast shut-off mode, controlled by bit fsoe, is available for this situation. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-56 v1.1, 2011-03 32-bit scu, v1.0 if fsoe = 0, modules are stopped as describ ed above. this is called secure shut-off mode. the module is allowed to finish whatever operation is in progress. if fast shut-off mode is selected (fsoe = 1), clock generatio n to the unit is stopped as soon as any outstanding bus operation is finished. the clock control unit does not wait until the module has finished its transaction. this option stops the unit?s clock as fast as possible, and the state of the unit will be the closest possible to the time of the occurrence of the software breakpoint. note: in all TC1798 modules except multican and dma, the only shut down operating mode that is available is th e fast shut-off modeTC1798, regardless of the state of the fsoe bit. whether secure shut-off mode or fast shut-off mode is required depends on the application, the needs of the debugger, and the type of unit. for example, the analog-to- digital converter might allow the converter to finish a running analog conversion before it can be suspended. otherwise the conver sion might be corrupted and a wrong value could be produced when suspend mode is exit ed and the unit is enabled again. this would affect further emulation and debugging of the application?s program. on the other hand, if a problem is observed to relate to the operation of the external analog-to-digital converter itself, it might be necessary to stop the unit as fast as possible in order to monitor its current instantaneous state. to do this, the fast shut-off mode option would be selected. although proper continuation of the application?s program might not be possible after such a step, this would most likely not matter in such a case. note that it is never appropriate for application software to set the fsoe bit. fast shut- off mode should only be set by debug software. to guard against application software accidently setting fsoe, bit fsoe is specially protected by the mask bit sbwe. the spen bit can only be written if, during the same write operation, sbwe is set, too. application software should never set sbwe. in this way, user software can not accidentally alter the value of the fsoe bit. note that this is the same guard mechanism used for the spen bit. module clock divider control peripheral modules of the TC1798 can have a rmc control bit field in their clc registers. this run mode clock control bit field makes it possible to slow down the clc clock via a programmable clock divider circuit. a value of 00 h in rmc disables the clock signals to these modules (clc clock is switched off). if rmc is not equal to 00 h , the clock for a module register ( f clc ) accesses is generated as (3.16) f clc f fpi rmc ------------- - = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-57 v1.1, 2011-03 32-bit scu, v1.0 where rmc is the content of its clc register rmc field with a range of 1 to 255. if rmc is not available in a clc register, the clc clock frequency f clc is always equal to the frequency of f fpi . note: the number of module clock cycles (w ait states) that are required for a ?destructive read? access (means: flags/bits are set/cleared by a read access) to a module register of a peripheral un it depends on the selected clc clock frequency. therefore, a slower clc clock (selected vi a bit field rmc in the clc register) may result in a longer read cycle access time on the fpi-bus for peripheral units with ?destructive read? access (e.g. the asc). module clock register implementations table 3-2 shows which of the clc register bits/bit fields are implemented for each peripheral module in the TC1798 and which modules are equipped with a fractional divider. table 3-2 clock generation implementation of the TC1798 peripheral modules module disr bit 0 diss bit 1 spen bit 2 edis bit 3 sbwe bit 4 fsoe bit 5 rmc fract. divider 1) adc0 adc1 adc2 adc3 ?????? ?? fadc ?????? ? ? asc0 and asc1 ?????? 8-bit ? ssc0 ?????? ? ? ssc1 ?????? ? ? ssc2 ?????? ? ? ssc3 ?????? ? ? gpt120 ?????? ?? gpt121 ?????? ?? multican ?????? ? ? dma ?????? ?? sdma ?????? ?? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-58 v1.1, 2011-03 32-bit scu, v1.0 fractional divider operation the fractional divider divides the input clock f clc either by the factor 1/n or by a fraction of n/1024 for any value of n from 0 to 1023, and outputs the clock signal, f mod . the fractional divider is controll ed by the mod_fdr register. the fractional divider can be co nfigured for two operating modes: ? normal divider mode: reload counter (result = result + 1), generating an output clock pulse on counter overflow. ? fractional divider mode: add a step value to the result value and generates an output clock pulse on counter overflow. normal divider mode in normal divider mode (mod_fdr.dm = 01 b ), the fractional divider behaves as a reload counter (addition of +1) that generates an output clock pulse at f mod on the transition from 3ff h to 000 h . mod_fdr.result represen ts the counter value and mod_fdr.step determines the reload value. gpta0 gpta1 ltca2 ?????? ? ? mli0 not implemented, mli is connected to dma_clc ? mli1 not implemented, mli is connected to dma_clc ? msc0 ?????? ? ? msc1 ?????? ? ? pcp2 different bit definitions 2) stm ?????? 3-bit ? eray ?????? 3-bit ? she ?????? ?? bmu ?????? ?? fce ?? ?????? lmu ?? ?????? 1) further info on fdr implementations see table 3-4 . 2) automatic clock switch-off capability if pcp is idle. table 3-2 clock generation implementation of the TC1798 peripheral modules module disr bit 0 diss bit 1 spen bit 2 edis bit 3 sbwe bit 4 fsoe bit 5 rmc fract. divider 1) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-59 v1.1, 2011-03 32-bit scu, v1.0 the output frequencies in normal divider mode are defined according to the following formulas: , with n = 1024 - step (3.17) note: each write to register fdr with bit field dm = 01 b or 10 b sets bit field result to 3ff h . in order to get f mod = f clc mod_fdr.step must be programmed with 3ff h . figure 3-18 shows the operation of the normal divider mode with a reload value of mod_fdr.step = 3fd h . figure 3-18 normal divider mode fractional divider mode when the fractional divider mode is selected (mod_fdr.dm = 10 b ), the module clock f mod is derived from the bus clock f clc by division of a fraction of n/1024 for any value of n from 0 to 1023. in general, the fractional divider mode makes it possible to program the average module clock frequency with a higher accuracy than in normal divider mode. in fractional divider mode, an clock pulse at f mod is generated depending on the result of the addition mod_fdr.result + mod_fdr.step. if the addition leads to an overflow over 3ff h , a pulse is generated at f mod . note that in fractional divider mode the clock f mod can have a maximum period jitter of one f clc clock period. the frequencies in fractional divider mode are defined according to the following formula: , with n = 0-1023 (3.18) f mod f clc 1 n -- - = mct05605_m result 3ff f clc 3fe 3fd 3ff 3fd 3fd 3fe 3ff 3fd 3fe step reload 3fd reload 3fd reload f mod f mod f clc n 1024 ------------ - = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-60 v1.1, 2011-03 32-bit scu, v1.0 note: each write to register fdr with bit field dm = 01 b or 10 b sets bit field result to 3ff h . suspend mode the operation of the fractional divider can be controlled by the suspend mode request input. this input is activated in suspend mode by the on-chip debug control logic. in suspend mode, module registers are acce ssible for read and write actions, but other module internal functions are frozen. the state of the suspend mode request and suspend mode acknowledge is latched in two status flags of register mod_fdr, susreq and susack. suspend mode request and (suspend mode acknowledge or bit sm) must remain set both to maintain the suspend mode. the kernel disable request becomes alwa ys active when the module disable request signal is activated, independently of the su spend mode settings in the fractional divider. external cl ock enable when the module clock generation has been disabled by software (setting mod_fdr.disclk = 1), the disable state can be exited when the external clock enable input = 1. this feature is enabled when mod_fdr.enhw = 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-61 v1.1, 2011-03 32-bit scu, v1.0 fractional divider register implementations table 3-4 shows the implementations specific differences of the fractional divider functionality. table 3-3 fractional divider function table mode sc dm result f mod operation of fractional divider normal mode ? 00 b unchanged inactive switched off 01 b continuously updated active normal divider mode 10 b fractional divider mode 11 b unchanged inactive switched off suspend mode 00 b 00 b unchanged inactive switched off 01 b continuously updated active normal divider mode 10 b fractional divider mode 11 b unchanged inactive switched off 01 b 00 b unchanged switched off 01 b loaded with 3ff h halted 10 b 11 b unchanged inactive switched off 10 b 00 b loaded with 3ff h inactive switched off 01 b halted 10 b 11 b switched off 11 b ? loaded with 3ff h inactive switched off www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-62 v1.1, 2011-03 32-bit scu, v1.0 table 3-4 fdr register implementations fdr register suspend mode acknowledge operation 1) enhw 2) can_fdr acknowledge depends on module state ? fadc_fdr acknowledge depends on module state ? gpta0_fdr always immediately acknowledged; independently from module states from multican mli0_fdr acknowledge depends on module state ? mli1_fdr acknowledge depends on module state ? msc0_fdr acknowledge depends on module state from multican msc1_fdr acknowledge depends on module state from multican ssc0_fdr always immediately acknowledged; independently from module state from multican ssc1_fdr always immediately acknowledged; independently from module state from multican ssc2_fdr always immediately acknowledged; independently from module state from multican ssc3_fdr always immediately acknowledged; independently from module state from multican sent_fdr always immediately acknowledged; independently from module state from multican sscg0_fdr sscg1_fdr sscg2_fdr sscg3_fdr always immediately acknowledged; independently from module state from multican 1) this column shows whether a suspend acknowledge from a fdr controlled module depends on the module?s state or not. if a suspend acknowledge depends from the module state, typically module operations such as serial transmissions are terminated before a suspend reque st is acknowledged back to the fractional divider. note that bit fdr.sm must be cleared (granted suspend mode selected) when using the suspend mode acknowledge/grant functionality. if immediate suspend mode is selected (fdr.sm = 1), suspend mode is entered at once (if fdr.sc not equal 00 b ) independently from the suspend acknowledge answer from the module. 2) this column shows whether the external clock enable input of a fractional divider is controlled by on-chip hardware (source module see comment) or not (???). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-63 v1.1, 2011-03 32-bit scu, v1.0 module clc register mod_clc clock control register (00 h ) reset value: module-specific 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 rmc 0 fs oe sb we e dis sp en dis s dis r rw r rwwrwrwrhrw field bits type description disr 0rw module disable request bit used for enable/disable control of the module. 0 b module disable is not requested 1 b module disable is requested diss 1rh module disable status bit bit indicates the current status of the module 0 b module is enabled 1 b module is disabled if the rmc field is implemented and if it is 0, diss is set automatically. spen 2rw module suspend enable used for enabling the suspend mode. 0 b module cannot be suspended (suspend is disabled) 1 b module can be suspended (suspend is enabled) this bit can be written only if sbwe is set during the same write operation. edis 3rw sleep mode en able control used for module sleep mode control. 0 b sleep mode request is regarded. module is enabled to go into sleep mode. 1 b sleep mode request is disregarded: sleep mode cannot be entered on a request. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-64 v1.1, 2011-03 32-bit scu, v1.0 sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. 0 b bits spen and fsoe are write-protected 1 b bits spen and fsoe are overwritten by respective value of spen or fsoe reading this bit returns always 0. fsoe 5rw fast switch off enable used for fast clock switch-off in suspend mode. 0 b clock switch-off in suspend mode via disable control feature (secure clock switch off) selected 1 b fast clock switch off in suspend mode selected this bit can be written only if sbwe is set during the same write operation. rmc [15:8] rw 8-bit clock divider value in run mode this is a maximum 8-bit divider value for clock f fpi . if rmc is set to 0 the module is disabled. 0 7, 6, [31:16] r reserved read as 0; should be written with 0. mod_fdr fractional divider register reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dis clk en hw sus req sus ack 0result rwh rw rh rh r rh 1514131211109876543210 dm sc sm fdis step rw rw rw rw rw field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-65 v1.1, 2011-03 32-bit scu, v1.0 field bits type description step [9:0] rw step value in normal divider mode, step contains the reload value for result. in fractional divider mode, this bit field determines the 10-bit value that is added to result with each input clock cycle. fdis 10 rw freeze disable this bit controls the freeze function for this module. 0 b module operates on co rrected clock, with reduced modulation jitter 1 b module operates on uncorrected clock with full modulation jitter sm 11 rw suspend mode sm selects between granted or immediate suspend mode. 0 b granted suspend mode selected 1 b immediate suspend mode selected sc [13:12] rw suspend control this bit field determines the behavior of the fractional divider in suspend mode (bit susreq and susack set). 00 b clock generation continues. 01 b clock generation is stopped and the clock output signal is not generated. result is not changed except when writing bit field dm with 01 b or 10 b . 10 b clock generation is stopped and the clock output signal is not generated. result is loaded with 3ff h . 11 b same as sc = 10 b but signal reset external divider is 1 (independently of bit field dm). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-66 v1.1, 2011-03 32-bit scu, v1.0 dm [15:14] rw divider mode this bit fields determines the functionality of the fractional divider block. 00 b fractional divider is switched off; no output clock is generated. the reset external divider signal is 1. result is not updated. 01 b normal divider mode selected. 10 b fractional divider mode selected. 11 b fractional divider is switched off; no output clock is generated. result is not updated. result [25:16] rh result value in normal divider mode, result acts as reload counter (addition +1). in fractional divider mode, this bit field contains the result of the addition result + step. if dm is written with 01 b or 10 b , result is loaded with 3ff h . susack 28 rh suspend mode acknowledge 0 b suspend mode is not acknowledged. 1 b suspend mode is acknowledged. suspend mode is entered when susack and susreq are set. susreq 29 rh suspend mode request 0 b suspend mode is not requested. 1 b suspend mode is requested. suspend mode is entered when susreq and susack are set. enhw 30 rw enable hardware clock control 0 b bit disclk cannot be cleared by a high level of the external clock enable input 1 b bit disclk is cleared while the external clock enable input is at high level. disclk 31 rwh disable clock 0 b clock generation of f mod is enabled according to the setting of bit field dm. 1 b fractional divider is stopped. signal f mod becomes inactive. no change except when writing bit field dm. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-67 v1.1, 2011-03 32-bit scu, v1.0 0 [27:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-68 v1.1, 2011-03 32-bit scu, v1.0 3.2 reset operation this section describes the conditions under which the TC1798 will be reset and the reset operation configuration and control. 3.2.1 overview the following reset request triggers are available: ? 1 external power-on hardware reset request trigger; porst , (cold reset) ? 2 external system request reset triggers; esr0 , and esr1 ,(warm reset) ? watchdog timer (wdt) reset request trigger, (warm reset) ? software reset (sw), (warm reset) ? debug (ocds) reset request trigger, (warm reset) ? resets via the jtag interface ? flash tuning protection (tp) (warm reset) ? jtag reset (special reset) note: the jtag and ocds resets ar e described in the ocds chapter. there are two basic types of reset request triggers: ? trigger sources that do not depend on a clock, such as the porst . this trigger force the device into an asynchronous reset assertion independently of any clock. the activation of an asynchronous reset is asynchronous to the system clock, whereas its de-assertion is synchronized. ? trigger sources that need a clock in order to be asserted, such as the input signals esr0 ,esr1 , the wdt trigger, tp trigger, or the sw trigger. note: a porst reset should only triggered for power related issue and not for pure functional purpose. 3.2.2 reset types the following summary shows the different reset types. ? power-on reset: this reset leads to a initia lization into a defin ed state of the complete system. this reset should only be requested on a real power-on event and can not by any non power related event. a power-on reset also generates a system reset and an application reset. ? system reset: this reset leads to a initialization into a defined state of the complete system without the following parts: reset control, power control. a system reset also generates an application reset. ? debug reset: this reset leads to a initialization into a defined state of t he complete debug system. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-69 v1.1, 2011-03 32-bit scu, v1.0 ? application reset: this reset leads to a initialization into a defined state of the complete application system with the following parts: all peripherals, the cpu and partially the scu and the flash memory. 3.2.3 reset sources overview the connection of the reset sources and the activated reset signals/domains are shown in table 3-5 . 3.2.4 module reset behavior table 3-6 lists how the various functions of the TC1798 are affected through a reset depending on the reset type. a ?x? means that this block has at least some register/bits that are affected by this reset. table 3-5 effects of resets for reset signal activation reset request trigger application reset debug reset system reset porst activated activated activated esr0 configurable not activated configurable esr1 configurable not activated configurable wdt configurable not activated configurable sw configurable not activated configurable ocds reset not activated activated not activated cbs_ojconf.rstcl 0 activated not activated activated cbs_ojconf.rstcl 1 not activated activated not activated cbs_ojconf.rstcl 3 activated not activated not activated table 3-6 effect of reset on device functions module / function application reset debug reset system reset power-on reset cpu core xxxx peripherals (except scu) xxxx scu x not affected x x www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-70 v1.1, 2011-03 32-bit scu, v1.0 3.2.5 general reset operation a reset is generated if an enabled reset request trigger is asserted. most reset request trigger can configured for the reset type that should initiated by it. no action (disabled) is one possible configuration and can be selected for a reset request trigger by setting the adequate bit field in a reset configuration register to 00 b . the debug reset can only on-chip static rams 1) ovram not affected, reliable not affected, reliable affected, un-reliable affected, un-reliable dspr not affected, reliable not affected, reliable affected, un-reliable affected, un-reliable dcache not affected, reliable not affected, reliable affected, un-reliable affected, un-reliable pspr not affected, reliable not affected, reliable affected, un-reliable affected, un-reliable pram not affected, reliable not affected, reliable affected, un-reliable affected, un-reliable cmem not affected, reliable not affected, reliable affected, un-reliable affected, un-reliable icache not affected, reliable not affected, reliable affected, un-reliable affected, un-reliable lmu not affected, reliable not affected, reliable affected, un-reliable affected, un-reliable flash memory x 2) not affected, reliable xx jtag interface not affected not affected not affected affected ocds not affected x not affected x mcds not affected x not affected x oscillators, pll not affected not affected x x port pins x not affected x x pins esrx not affected not affected x x 1) reliable here means that also the redundancy is not affected by the reset. 2) parts of the flash memory block are only reset by a class 0 reset. for more detail see the flash chapter. table 3-6 effect of reset on device functions (cont?d) module / function application reset debug reset system reset power-on reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-71 v1.1, 2011-03 32-bit scu, v1.0 be requested by dedicated reset request triggers and can not be selected via a reset configuration register. for more information see also register rstcon. the duration of a reset is defined by two independent counters. one counter for the power-on, system, and application reset types and one separate counter for the debug reset. a separate counter for the debug reset was implemented to allow a non- intrusive adaptation of the reset length to the debugger needs without modification of the application setting. 3.2.6 reset state machine there is one central reset state machine (rsm) controlling the reset generation for the complete device beside the jtag reset domain. note: the jtag reset domain is controlled by the trst pin. the rsm is composed of a control block responsible for the operation flow, two counters with a reload register, and a distribution logic that controls the generation of the three dedicated resets. figure 3-19 reset state machine block diagram reset_stm_its porst rstcnta rstcntcon. relsa control dist ff ff system reset application rese t reset request triggers rstcntd rstcntcon. reld dist ff debug reset eec reset dist ocds enable ff ff power-on reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-72 v1.1, 2011-03 32-bit scu, v1.0 3.2.7 reset counters (rstcnta and rstcntd) there are two reset counters implemented. rstcnta is the reset counter that controls the reset length for all non debug relevant resets (system reset and application reset). rstcntd is the reset counter that controls the reset length for the debug reset. the reset counters can be used for the following purposes: ? first to control the length of the internal resets. ? second to configure the reset length in a way that the reset outputs via the esrx pins match with the reset input requirements of external blocks connected with the reset outputs. a reset counter rstcnt is an 16-bit counter counting down from the reload value defined by rstcntcon.relx (x = sa or d). t he counter is started by the control block as soon as a reset request trigger condition becomes active (for more information see table 3-7 and table 3-8 ). whether the counter has to be started or not depends on the reset request trigger and whether the counter is already active or not. in case that the counter is inactive, not counting down, it is always started. while the counter is already active it depends on the reset of the new reset request trigger that was asserted anew if the counter is restarted or not. this behavior is summarized in table 3-7 and table 3-8 . rstcntx ensures that a reset request trigger generates a reset of a minimum length which is configurable. but if a reset request trigger is asserted continuously longer than the counter needs for the complete count-down process the reset cannot be deasserted before the reset request trigger is also deasserted. anyway the counter is not started again, instead the control block informs the distribution logic (dist) that the reset still has to be asserted until the reset request trigger is deasserted. table 3-7 restart of rstcnta reset active new reset request power-on system debug application power-on reset restart no restart no restart no restart system restart no restart no restart no restart application restart restart no restart no restart table 3-8 restart of rstcntd reset active new reset / reset type request power-on system debug application debug restart no restart no restart no restart www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-73 v1.1, 2011-03 32-bit scu, v1.0 the reset state of the control block is implemented such that the rstcnta is started and two reset types (system and application) have to be asserted by the distribution logic. the reset state of the control block is implemented such that the rstcntd is started and the debug reset has to be asserted by the distribution logic. note: the reset counter should not be configured with a value lower than 20 h due to the implementation. 3.2.8 de-assertion of a reset the reset is de-asserted when all of the following conditions are fulfilled. ? the reset counter has expired (reached zero) ? no reset request trigger that is configured to generate the same reset is currently asserted 3.2.8.1 example1: reset request trigger a is asserted and leads to an application reset. if the reset request trigger is de-asserted before rstcnta r eached zero the application reset is de- asserted when rstcnta reaches zero. if the reset request trigger is de-asserted after rstcnta reached zero the application reset is de-asserted when the reset request trigger is de-asserted. 3.2.8.2 example2: reset request trigger a is asserted and leads to an application reset. reset request trigger a is de-asserted before rstcnta reached zero. reset request trigger b is asserted after reset request trigger a but before rstcnta reaches zero. reset request trigger b is also configured to result in an application reset. if the reset request trigger b is de-asserted before rstcnta reached zero the application reset is de-asserted when rstcnta reaches zero. if the reset request trigger b is de-asserted after rstcnta reached zero the application reset is de-asserted when the reset request trigger b is de-asserted. 3.2.8.3 example3: reset request trigger a is asserted and leads to a system reset. reset request trigger a is de-asserted before rstcnta reached zero. reset request trigger b is asserted after reset request trigger a but before rstcnta reaches zero. reset request trigger b is configured to result in an application rese t. if the reset request trigger b is de-asserted before rstcnta reached zero the system and application resets are de-asserted when rstcnta reaches zero. if the reset request trigger b is de-asserted after www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-74 v1.1, 2011-03 32-bit scu, v1.0 rstcnta reached zero the application reset is de-asserted when the reset request trigger b is de-asserted. 3.2.9 reset triggers there are two types of reset triggers for the reset control logic: ? triggers that lead to a specific reset ? triggers that lead to a configurable reset 3.2.9.1 specific reset triggers these triggers lead to a predefined reset if the trigger is asserted. additionally these triggers can not be enabled / disabled. all specific reset are listed in table 3-9 . 3.2.9.2 configurable reset triggers these triggers lead to a selectable reset if the trigger is asserted. additionally these triggers can be enabled / disabled. the behavior of the reset triggers action is defined by the configuration of the dedicated bit field for this trigger in register rstcon. 3.2.10 debug specific behavior for safety reasons it is required by the debugg er that if the ocds system is disabled a debug reset is also asserted every time an application reset is asserted. 3.2.11 eec reset specific behavior the complete eec part is reset with the power-on reset. for safety reasons it is required by the de bugger that if the o cds system is disabled a eec reset is also asserted every time an application reset is asserted. table 3-9 specific reset triggers reset trigger reset type request debug (ocds from cerberus) debug reset cerberus 0 (cb0) system reset cerberus 1 (cb1) debug reset cerberus 3 (cb3) application reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-75 v1.1, 2011-03 32-bit scu, v1.0 3.2.12 reset controller registers 3.2.12.1 status registers after a reset has been executed, the reset status registers provide information on the source of the last reset(s). the reset stat us registers are updat ed upon each reset cycle. a reset cycle is finished when all resets ar e de-asserted. within a reset cycle the status flags are used as sticky flags. rststat reset status register (050 h ) reset value: 0001 0001 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 tp cb3 cb1 cb0 ocd s por st r rhrhrhrhrhrh 1514131211109876543210 0swwdt0 esr 1 esr 0 rrhrhrrhrh field bits type description esr0 0rh reset request trigger reset status for esr0 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger note: this bit is set if the esr0 pin is configured as open drain for output characteristics (iocr.pc0 = 1101 h or 1110 h ) and esr0 is configured to generate a reset (rstcon.esr0 = 01 b or 10 b ) and a reset is signaled by the esr0 pin to the outside. that this bit is set under this condition can be avoided by either setting iocr.pc0 = 1001 h or 1010 h or rstcon.esr0 = 00 b . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-76 v1.1, 2011-03 32-bit scu, v1.0 esr1 1rh reset request trigger reset status for esr1 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger note: this bit is set if the esr1 pin is configured as open drain for output characteristics (iocr.pc1 = 1101 h or 1110 h ) and esr1 is configured to generate a reset (rstcon.esr1 = 01 b or 10 b ) and a reset is signaled by the esr1 pin to the outside. that this bit is set under this condition can be avoided by either setting iocr.pc1 = 1001 h or 1010 h or rstcon.esr1 = 00 b . wdt 3rh reset request trigger reset status for wdt 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger sw 4rh reset request trigger reset status for sw 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger porst 16 rh reset request trigger reset status for porst 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger this bit is also set if the bits cb0, cb1, and cb3 are set in parallel. ocds 17 rh reset request trigger reset status for ocds 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-77 v1.1, 2011-03 32-bit scu, v1.0 3.2.12.2 configuration registers reset counter control register this register controls the reset length settings for the three resets. cb0 18 rh reset request trigger reset status for cerberus system reset 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger cb1 19 rh reset request trigger reset status for cerberus debug reset 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger cb3 20 rh reset request trigger reset status for cerberus application reset 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger tp 21 rh reset request trigger reset status for tp 0 b the last reset was not requested by this reset trigger 1 b the last reset was reque sted by this reset trigger 0 2, [15:5], [31:22] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-78 v1.1, 2011-03 32-bit scu, v1.0 rstcntcon reset counter control register (054 h ) reset value: 05be 05be h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reld rw 1514131211109876543210 relsa rw field bits type description relsa [15:0] rw system application reset counter reload value this bit field defines the reload value of rstcnta. this value is always used when counter rstcnta is started. reld [31:16] rw debug 1 reset counter reload value this bit field defines the reload value of rstcntd. this value is always used when counter rstcntd is started. rstcon reset configuration register (058 h ) reset value: 0000 02a2 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 rw 1514131211109876543210 0 sw wdt 1 0 esr1 esr0 rw rw rw rw rw rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-79 v1.1, 2011-03 32-bit scu, v1.0 field bits type description esr0 [1:0] rw esr0 reset request trigger reset configuration this bit field defines which reset is generated by a reset request trigger from esr0 reset. 00 b no reset is generated for a trigger of esr0 01 b a system reset is generated for a trigger of esr0 reset 10 b an application reset is generated for a trigger of esr0 reset 11 b reserved, do not use this combination esr1 [3:2] rw esr1 reset request trigger reset configuration this bit field defines which reset is generated by a reset request trigger from esr1 reset. 00 b no reset is generated for a trigger of esr1 01 b a system reset is generated for a trigger of esr1 reset 10 b an application reset is generated for a trigger of esr1 reset 11 b reserved, do not use this combination wdt [7:6] rw wdt reset request trigger reset configuration this bit field defines which reset is generated by a reset request trigger from wdt reset. 00 b no reset is generated for a trigger of wdt 01 b a system reset is generated for a trigger of wdt reset 10 b an application reset is generated for a trigger of wdt reset 11 b reserved, do not use this combination sw [9:8] rw sw reset request trigger reset configuration this bit field defines which reset is generated by a reset request trigger from software reset. 00 b no reset is generated for a trigger of software reset 01 b a system reset is generated for a trigger of software reset 10 b an application reset is generated for a trigger of software reset 11 b reserved, do not use this combination www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-80 v1.1, 2011-03 32-bit scu, v1.0 sw reset configuration register this register controls the sw reset operation. 1 5rw reserved should be written with 1. 0 4, [31:10] rw reserved should be written with 0. arstdis application reset disable register (05c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 00 stm dis rrwrw field bits type description stmdis 0rw stm disable reset this bit field defines if an application reset leads to an reset for the stm. 0 b an application reset resets the stm 1 b an application reset has no effect for the stm 0 [7:1] rw reserved should be written with 0. 0 [31:8] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-81 v1.1, 2011-03 32-bit scu, v1.0 swrstcon software reset configuration register (060 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 swcfg 0 sw rst req sw boo t rw r w rw field bits type description swboot 0rw software boot configuration selection 0 b bit field ststat.hwcfg is not updated with the content of swcfg upon an application reset 1 b bit field ststat.hwcfg is updated with the content of swcfg upon an application reset swrstreq 1w software reset request 0 b no sw reset is requested 1 b a sw reset request trigger is generated this bit is automatically cleared and read always as zero. swcfg [15:8] rw software boot configuration a software boot configuration different from the external applied hardware configuration can be specified with these bits. the configuration encoding is equal to the hwcfg encoding in register ststat. 0 [7:2], [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-82 v1.1, 2011-03 32-bit scu, v1.0 3.3 external interface the scu provides inte rface pads for system purpose. various functions are covered by these pins. due to the different tasks some of the pads can not be shared with other functions but most of them can. the fo llowing functions are covered by the scu controlled pads: ? reset request triggers ? reset indication ? trap request triggers ? interrupt request triggers ? non scu module triggers the first three points are covered by the esr pads and the last two points by the eru pads. 3.3.1 external service requests (esrx ) the esr pins can be used to trigger either a reset, a trap (nmi), as reset output, or as data pin. figure 3-20 esr operation 3.3.1.1 esrx as reset request trigger an esr0 /esr1 reset request trigger leads to a system or application reset. the type of the reset can be configured via rstcon.esrx. rsm esrx esr _block . edge detection df trapstat .esrxt to trap to m odules esrcfgx. edcon esrcfgx. dfen reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-83 v1.1, 2011-03 32-bit scu, v1.0 in order to be safely recognized esr0 /esr1 has to be active for a minimum of 2 f fpi clock cycles. the input signal esr0 /esr1 have digital filters (3-stage median filters), that can be disabled. a 3-stage median filter samples with f fpi three consecutive clock cycles and the output is defined by the majority of the three sampled values. the behavior of all three esr0 /esr1 pins can be configured by programming the registers esrcfgn. the pad control functionality can be configured independently for each pin, comprising: ? a selection of the driver type (open-drain or push-pull) ? an enable function for the output driver (input and/or output capability) ? an enable function for the pull-up/down resistance 3.3.1.2 esrx as reset output the external pins esr0 /esr1 can serve as an reset output (open drain) for the application reset. note: the reset output is only asserted for the duration the reset counter rstcnta is active. during a possible reset extension the reset output is not longer asserted. if the pin esr0 /esr1 is enabled as reset output and the input level is low while the output stage is disabled (indicating that it is still driven low externally), the reset circuitry holds the chip in reset until a high level is detected on esr0 /esr1 . the internal output stage drives a low level during reset only wh ile rstcnta is active. it deactivates the output stage when the time defined by rstcntcon.relsa has passed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-84 v1.1, 2011-03 32-bit scu, v1.0 3.3.1.3 esr registers input/output control registers the input/output control registers select the digital output and input driver functionality and characteristics of the pin. direction (input or output), pull-up or pull-down devices for esrcfg0 esr0 configuration register (070 h ) reset value: 0000 0110 h esrcfg1 esr1 configuration register (074 h ) reset value: 0000 0090 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 edcon 0 df en 0 rrwrrwr field bits type description dfen 4rw digital filter enable this bit defines if the 3-stage median filter of the esr0 is used or bypassed. 0 b the filter is bypassed 1 b the filter is used edcon [8:7] rw edge detection control this bit field defines the edges that lead to an esr0 trigger of the synchronous path. 00 b no trigger is generated 01 b a trigger is generated upon a rising edge 10 b a trigger is generated upon a falling edge 11 b a trigger is generated upon a rising or falling edge 0 [3:0], [6:5], [31:9] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-85 v1.1, 2011-03 32-bit scu, v1.0 inputs, and push-pull or open-drain functionality for outputs can be selected by the corresponding bit fields pcx (x = 0-1). iocr input/output control register (0a0 h ) reset value: 0020 10e0 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 000 rrwr 1514131211109876543210 pc10pc00 rw r rw r field bits type description pc0 [7:4] rw control for esr 0 pin this bit field defines the esr0 pin functionality according to the coding table (see table 3-10 ). pc1 [15:12] rw control for esr 1 pin this bit field defines the esr1 pin functionality according to the coding table (see table 3-11 ). 0 [23:20] rw reserved have to be written with 0010 b . 0 [3:0], [11:8], [19:16], [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-86 v1.1, 2011-03 32-bit scu, v1.0 pad control coding table 3-10 describes the coding of the pc0 bit field that determine the port line functionality. table 3-10 pc0 coding pc0[3:0] i/o output characteristics selected pull-up/pull-down/ selected output function 0x00 b input is active and not inverted; output is inactive no input pull device connected 0x01 b input pull-down device connected 0x10 b input pull-up device connected 0x11 b no input pull device connected 1000 b input is active and not inverted; output is active push-pull general-purpose output 1001 b output drives a 0 for system resets, a weak pull-up is active otherwise 1010 b output drives a 0 for application resets, a weak pull-up is active otherwise 1011 b reserved, do not use this combination 1100 b the input is active and not inverted; output is active open-drain general-purpose output 1101 b output drives a 0 for system resets, a weak pull-up is active otherwise 1110 b output drives a 0 for application resets, a weak pull-up is active otherwise 1111 b reserved, do not use this combination www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-87 v1.1, 2011-03 32-bit scu, v1.0 pad control coding table 3-11 describes the coding of the pc1 bit field that determine the port line functionality. output register the output register determines the value of a gpio pin when it is selected by iocr as output. writing a 0 to a out.px (x = 0-1) bit position delivers a low level at the corresponding output pin. a high level is output when the corresponding bit is written with a 1. note that each single bit or group of bi ts of out.px can be set/cleared by writing appropriate values into the out put modification register omr. table 3-11 pc1 coding pc1[3:0] i/o output characteristics selected pull-up/pull-down/ selected output function 0x00 b input is active and not inverted; output is inactive no input pull device connected 0x01 b input pull-down device connected 0x10 b input pull-up device connected 0x11 b no input pull device connected 1000 b input is active and not inverted; output is active push-pull general-purpose output 1001 b output drives a 0 for system resets, a ?z? otherwise 1010 b output drives a 0 for application resets, a ?z? otherwise 1011 b reserved, do not use this combination 1100 b the input is active and not inverted; output is active open-drain general-purpose output 1101 b output drives a 0 for system resets, a ?z? otherwise 1110 b output drives a 0 for application resets, a ?z? otherwise 1111 b reserved, do not use this combination www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-88 v1.1, 2011-03 32-bit scu, v1.0 output modifica tion register the output modification register contains control bits that make it possible to individually set, clear, or toggle the logic state of a single pad by manipulating the output register. out output register (0a4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 0 p1 p0 rrwhrwhrwh field bits type description px (x = 0-1) xrwh output bit x this bit determines the level at the output pin esr x if the output is selected as gpio output. 0 b the output level of esr x is 0 1 b the output level of esr x is 1 px can also be set/cleared by control bits of the omr register. 0 2rwh reserved have to be written with 0. 0 [31:3] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-89 v1.1, 2011-03 32-bit scu, v1.0 omr output modificati on register (0a8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 pr 1 pr 0 r www 1514131211109876543210 00 ps 1 ps 0 r www field bits type description psx (x = 0-1) xw set bit x setting this bit will set or toggle the corresponding bit in the output register out. the function of this bit is shown in table 3-12 . prx (x = 0-1) x + 16 w clear bit x setting this bit will clear or toggle the corresponding bit in the port output register out. the function of this bit is shown in table 3-12 . 0 2, 18 w reserved read as 0; have to be written with 0. 0 [15:3], [31:19] r reserved read as 0; should be written with 0. table 3-12 function of the bits prx and psx prx psx function 0 0 bit out.px is not changed 0 1 bit out.px is set 1 0 bit out.px is cleared 1 1 bit out.px is toggled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-90 v1.1, 2011-03 32-bit scu, v1.0 input register the logic level of a gpio pin can be read via the read-only port input register in. reading the in register always returns the current logical value at the gpio pin independently whether the pin is selected as input or output. in input register (0ac h ) reset value: 0000 000x h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0p1p0 rrhrh field bits type description px (x = 0-1) xrh input bit x this bit indicates the level at the input pin esr x. 0 b the input level of esr x is 0 1 b the input level of esr x is 1 0 [31:2] r reserved read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-91 v1.1, 2011-03 32-bit scu, v1.0 3.3.2 external request unit (eru) the external request unit (eru) is a versat ile event and pattern detection unit. its major task is the generation of interrupts based on sel ectable trigger events at different inputs , e.g. to generate external interrupt req uests if an edge occurs at an input pin. the detected events can also be used by ot her modules to trigger or to gate module- specific actions. 3.3.2.1 introduction the eru of the TC1798 can be split in three main functional parts: ? 4 independent input channels x for input selection and conditioning of trigger or gating functions ? event distribution: a connecting matrix defines the events of the input channel x that lead to a reaction of an output channel y. ? 4 independent output channels y for combination of events, definition of their effects and distribution to the system (interrupt generation, ...) figure 3-21 external request unit overview these tasks are handled by the following building blocks: ?an external request select unit (ersx) per input channel allows the selection of one input vector out of the 4 possible inputs available. ?an event trigger logic (etlx) per input channel allows the definition of the transition (edge selection, or by software) that lead to a trigger event and can also store this status. here, the input levels of the selected signals are translated into external re quest in puts mcb05613_mm external request selection unit (ers) external trigger logic unit (etl) output gating unit (ogu) output channel 0 output channel 1 output channel 3 output channel 2 external request unit (eru) external request outputs 4 input channel 0 input channel 1 input channel 2 input channel 3 4 4 4 connecting m atrix www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-92 v1.1, 2011-03 32-bit scu, v1.0 events (event detected = event flag becomes set, independent of the polarity of the original input signals). ?the connecting matrix distributes the events and status flags generated by the input channels to the output channels. ?an output gating unit (oguy) per output channel that combines the available trigger events and status information from the input channels. an event of one input channel can lead to reactions of several output channels, or also events of several input channels can be combined to a reaction of one output channel (pattern detection). different types of reactions are possible, e.g. interrupt generation (based on signals eru_iouty). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-93 v1.1, 2011-03 32-bit scu, v1.0 3.3.2.2 eru pin connections figure 3-22 shows the eru input connections. figure 3-22 eru inputs overview the inputs to the eru can be selected from a large number of input signals. while some of the inputs come directly from a pin, other inputs use signals from various peripheral modules. usually, such signals would be selected for an eru function when the input function to the other module is not used otherwise, or the module is not used at all. however, it is also possible to select a input which is actually needed in the other module, and to use it also in the eru to provide for certain trigger functions, eventually combined with other signals (e.g. to generate an interrupt trigger in case a start of frame is detected at a selected communication). 3.3.2.3 external request select unit (ers) each ers combines four inputs to the one input signal of the respective input channel. figure 3-23 shows the structure of this block. in addition to the direct choice of either input ax or bx or their inverted values, the possible logical combinations for two selected inputs are a logical and or a logical or. ers0 input 00 input 01 input 02 input 03 p1 .0 gpta0_trig01 msc0_fclp p7 .0 ers1 input 10 input 11 input 12 input 13 p1 .1 p7 .1 gpta 0_trig03 msc1_fclp ers2 input 20 input 21 input 22 input 23 p1 .2 p7 .4 ers3 input 30 input 31 input 32 input 33 p1 .3 p7 .5 gpta 0_trig07 gpta 0_trig 05 not connected not connected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-94 v1.1, 2011-03 32-bit scu, v1.0 figure 3-23 external request select unit overview the ers unit for channel x is controlled via bit field erciy.exisx. 3.3.2.4 event trigger logic (etl) for each input channel x, an event trigger l ogic etlx derives a trigger event and a status from the input channel x delivered by the a ssociated ersx unit. each etlx is based on an edge detection block, where the detection of a rising or a falling edge can be individually enabled. both edges lead to a trigger event if both enable bits are set (e.g. to handle a toggling input). each pair of the four etl units has an associated eicry register, that controls all options of an etl (the register also holds control bits for the associated ers unit pair, e.g. eicr0 to control esr0 and esr1 plus and etl0 and etl1). eru_ers_block m u x input channel x eicry.exisx input x0 input x1 input x2 input x3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-95 v1.1, 2011-03 32-bit scu, v1.0 figure 3-24 event trigger logic overview when the selected event (edge) is detected, the status flag eifr.intfx becomes set. the status flag is cleared automatically if the ?opposite? event is detected if enabled so via bit eicry.ldenx = 1. for example, if only the falling edge detection is enabled to set the status flag, it is cleared when the rising edge is detected. in this mode, it can be used for pattern detection where the actual status of the input is important (enabling both edge detections is not useful in this mode). the output of the status flag is connected to all following output gating units (oguz) in parallel (see figure 3-25 ) to provide pattern detection capability of all oguz units based on different or the same status flags. in addition to the modification of the status flag, a trigger pulse output trxz of etlx can be enabled (by bit eicry.eienx) and selected to trigger actions in one of the oguz units. the target oguz for the trigger is selected by bit field eicry.inpx. the trigger becomes active when the selected edge event is detected, independently from the status flag eifr.intfx. eru_etl.vsd set clear event trigger logic x (etlx) trx0 to ogu0 eifr.intfx to all ogu y input channel x ersx detect event (edge) eicrm. fenx eicrm. renx tr igger pulse status flag eifr.intfx modify status flag eicrm. ldenx eicrm. eienx select trigger output eicrm. inpx enable trigger pulse trx1 to ogu1 trx2 to ogu2 trx3 to ogu3 edge event set fmr. fcx fmr. fsx clear www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-96 v1.1, 2011-03 32-bit scu, v1.0 3.3.2.5 connecting matrix the connecting matrix distributes the trig ger signals (trxy) and status signals (eifr.inpfx) from the different etlx units between the oguy units. figure 3-25 provides a complete overview of the connec tions between the etlx and the oguz units. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-97 v1.1, 2011-03 32-bit scu, v1.0 figure 3-25 connecting matrix between etlx and oguy ogu0 eru_ connection _m atr ix.vsd etl0 etl1 etl2 etl3 tr00 tr01 tr02 tr03 eifr .intf0 tr10 tr11 tr12 tr13 eifr .intf1 tr20 tr21 tr22 tr23 eifr .intf2 tr30 tr31 tr32 tr33 eifr .intf3 pattern detection inputs trigger inputs trx0 ogu1 pattern detection inputs trigger inputs trx1 ogu3 pattern detection inputs trigger inputs trx3 ogu2 pattern detection inputs trigger inputs trx2 eru_ iout3 eru_ tout3 eru_pdout3 eru_ iout2 eru_ tout2 eru_pdout2 eru_ iout1 eru_ tout1 eru_pdout1 eru_ iout0 eru_ tout0 eru_pdout0 eru_gout0 eru_gout1 eru_gout2 eru_gout3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-98 v1.1, 2011-03 32-bit scu, v1.0 3.3.2.6 output gating unit (ogu) each oguy unit combines the available trigger events and status flags from the input channels and distributes the results to the system. figure 3-26 illustrates the logic blocks within an oguy unit. all functions of an oguy unit are controlled by the associated igcrm registers, one for each pair of output channels e.g. igcr1 for ogu2 and ogu3. the function of an oguy unit can be split into two parts: ? trigger combination : all trigger signals trxy from the input channels that are enabled and directed to oguy and a pattern change event (if enabled) are logically or-combined. ? pattern detection : the status flags eifr.intfx of the input channels can be enabled to take part in the pattern detection. a pattern match is detected while all enabled status flags are set. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-99 v1.1, 2011-03 32-bit scu, v1.0 figure 3-26 output gating un it for output channel y each oguy units generates 4 output signa ls that are distributed to the system. ? eru_pdouty to directly output the pattern match information for gating purposes in other modules (pattern match = 1). ? eru_gouty to output the pattern match or pattern miss information (inverted pattern match), or a permanent 0 or 1 under software control for gating purposes in other modules. ? eru_touty as combination of a peripheral trigger, a pattern detection result change event, or the etlx trigger outputs trxy to trigger actions in other modules. ? eru_iouty as gated trigger output (eru_ gouty logical and-combined with eru_touty) to trigger interrupts (e.g. the interrupt generation can be gated to allow interrupt activation during a certain time window). eru_ogu _13 xx .vsd output gating unit y (oguy) eru_oguy1 tr0y tr1y tr2y tr3y eru_pdouty detect pattern ei fr. intf0 igcrm. ipeny0 pdrr. pdry igcrm. geeny combine ogu triggers (or) select periph. triggers eru_oguy2 eru_oguy3 igcrm. issy select gating scheme igcrm. igpy eru_gouty eru_iouty eru_touty peripheral triggers triggers from input channels status flags interrupt gating (and) igcrm. ipeny1 igcrm. ipeny2 igcrm. ipeny3 ei fr. intf1 ei fr. intf2 eifr.intf3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-100 v1.1, 2011-03 32-bit scu, v1.0 trigger combination the trigger combination logically or-combines different trigger inputs to form a common trigger eru_touty. possible trigger inputs are: ? in each etlx unit of the input channels , the trigger output trxy can be enabled and the trigger event can be directed to one of the oguy units. ? one out of three peripheral trigger signals per oguy can be selected as additional trigger source. these peripheral triggers are generated by on-chip peripheral modules, such as capture/compare or timer units. the selection is done by bit field exocony.iss. ? in the case that at least one pattern detection input is enabled (igcrm.ipenxy) and a change of the pattern detection result from pattern match to pattern miss (or vice- versa) is detected, a trigger event is gener ated to indicate a pattern detection result event (if enabled by igcrm.geeny). the trigger combination offers the possibility to program different trigger criteria for several input signals (independently for each input channel) or peripheral signals, and to combine their effects to a single output, e.g. to generate an interrupt or to start e.g. an adc conversion. this combination capability a llows the generation of an interrupt per ogu that can be triggered by several inputs (multitude of request sources -> one reaction). the following table describes the peripheral trigger connections for the oguy stages. the selection is defined by the bit fields iss in registers igcr0 (for ogu0 and ogu1) and igcr1 (for ogu2 and ogu3). table 3-13 oguy peripheral trigger connections in TC1798 input from/to module i/o to oguy can be used to/as ogu0 inputs eru_ ogu01 ccu60_sr1 i peripheral triggers for ogu0 eru_ ogu02 reserved i eru_ ogu03 reserved i ogu1 inputs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-101 v1.1, 2011-03 32-bit scu, v1.0 pattern detection the pattern detection logic allows the combination of the status flags of all etlx units. each status flag can be individually included or excluded from the pattern detection for each oguy, via control bits igcrm.ipenxy. the pattern detection block outputs the following pattern detection results: ? pattern match (pdrr.pdry = 1 and eru_pdouty = 1): a pattern match is indicated while all status flags that are included in the pattern detection are 1. ? pattern miss (pdrr.pdry = 0 and eru_pdouty = 0): a pattern miss is indicated while at least one of the status flags that are included in the pattern detection is 0. eru_ ogu11 ccu61_sr1 i peripheral triggers for ogu1 eru_ ogu12 reserved i eru_ ogu13 reserved i ogu2 inputs eru_ ogu21 ccu62_sr1 i peripheral triggers for ogu2 eru_ ogu22 reserved i eru_ ogu23 reserved i ogu3 inputs eru_ ogu31 ccu63_sr1 i peripheral triggers for ogu3 eru_ ogu32 reserved i eru_ ogu33 reserved i table 3-13 oguy peripheral trigger connections in TC1798 (cont?d) input from/to module i/o to oguy can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-102 v1.1, 2011-03 32-bit scu, v1.0 in addition, the pattern detection can deliver a trigger event if the pattern detection result changes from match to miss or vice-versa (if enabled by igcrm.geeny = 1). the pattern result change event is logically or-combined with the other enabled trigger events to support interrupt generation or to trigger other module functions (e.g. in an adc). the event is indicated when the pattern detection result changes and pdrr.pdry becomes updated. the interrupt generation in the oguy is ba sed on the trigger eru_touty that can be gated (masked) with the pattern detection result eru_pdouty. this allows an automatic and reproducible generation of interrupts during a certain time window, where the request event is elaborated by the trigger combination block and the time window information (gating) is given by the pattern detection. for example, interrupts can be issued on a regular time base while a combination of input signals occurs (pattern detection based on etlx status bits). a programmable gating scheme introduces flexibility to adapt to application requirements and allows the generation of interrupt requests eru_iouty under different conditions: ? pattern match (igcrm.igpy = 10 b ): an interrupt request is issued when a trigger event occurs while the pattern detection shows a pattern match. ? pattern miss (igcrm.igpy = 11 b ): an interrupt request is issued when the trigger event occurs while the pattern detection shows a pattern miss. ? independent of pattern detection (igcrm.igpy = 01 b ): in this mode, each occurring trigger event leads to an interrupt request. the pattern detection output can be used independently from the trigger combination for gating purposes of other peripherals (independe nt use of eru_touty and eru_pdouty with interrupt requests on trigger events). ? no interrupts (igcrm.igpy = 00 b , default setting) in this mode, an occurring trigger event does not lead to an interrupt request. the pattern detection output can be used independently from the trigger combination for gating purposes of other peripheral s (independent use of eru_touty and eru_pdouty without interrupt requests on trigger events). 3.3.2.7 eru output connections this section describes the connections of the eru output signals for gating or triggering other module functions, as well as the conne ctions to the interrupt control registers. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-103 v1.1, 2011-03 32-bit scu, v1.0 table 3-14 eru output connections in TC1798 output from/to module i/o to oguy can be used to/as ogu0 outputs eru_ pdout0 eray input stpw0 o pattern detection output eru_ gout0 not connected o gated pattern detection output eru_ tout0 not connected o trigger output eru_ iout0 interrupt generation dma channel 00 dma channel 04 o interrupt output ogu1 outputs eru_ pdout1 eray input stpw1 o pattern detection output eru_ gout1 not connected o gated pattern detection output eru_ tout1 not connected o trigger output eru_ iout1 interrupt generation dma channel 01 dma channel 05 gpta0 input int1 gpta1 input int1 ltca2 input int1 o interrupt output ogu2 outputs eru_ pdout2 eray input stpw2 adc gating input fadc input fadc_gsc o pattern detection output eru_ gout2 not connected o gated pattern detection output eru_ tout2 not connected o trigger output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-104 v1.1, 2011-03 32-bit scu, v1.0 3.3.2.8 external request unit registers the external input channel register eicr0 and eicr1 for the external input channels 0 to 3 contain bits to configure the external request selection ers and the event trigger logic etl. eru_ iout2 interrupt generation dma channel 02 dma channel 06 adc trigger input fadc input fadc_tsc gpta0 input int2 gpta1 input int2 ltca2 input int2 o interrupt output ogu3 outputs eru_ pdout3 eray input stpw3 adc gating input fadc input fadc_gsd o pattern detection output eru_ gout3 not connected o gated pattern detection output eru_ tout3 not connected o trigger output eru_ iout3 interrupt generation dma channel 03 dma channel 07 adc trigger input fadc input fadc_tsd gpta0 input int3 gpta1 input int3 ltca2 input int3 o interrupt output table 3-14 eru output connections in TC1798 (cont?d) output from/to module i/o to oguy can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-105 v1.1, 2011-03 32-bit scu, v1.0 eicr0 external input channel register 0 (080 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0inp1 ei en1 ld en1 r en1 f en1 0 exis1 0 r rw rwrwrwrw r rw r 1514131211109876543210 0inp0 ei en0 ld en0 r en0 f en0 0 exis0 0 r rw rwrwrwrw r rw r field bits type description exis0 [5:4] rw external input selection 0 this bit field determines which input line is selected for input channel 0. 00 b input 00 is selected 01 b input 01 is selected 10 b input 02 is selected 11 b input 03 is selected fen0 8rw falling edge enable 0 this bit determines if the falling edge of input channel 0 is used to set bit intf0. 0 b the falling edge is not used 1 b the detection of a falling edge of input channel 0 generates a trigger event (intf0 becomes set) ren0 9rw rising edge enable 0 this bit determines if the rising edge of input channel 0 is used to set bit intf0. 0 b the rising edge is not used 1 b the detection of a rising edge of input channel 0 generates a trigger event (intf0 becomes set) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-106 v1.1, 2011-03 32-bit scu, v1.0 lden0 10 rw level detection enable 0 this bit determines if bit intf0 is cleared automatically if an edge of the input input channel 0 is detected, which has not been selected (rising edge with ren0 = 0 or falling edge with fen0 = 0). 0 b bit intf0 will not be cleared 1 b bit intf0 will be cleared eien0 11 rw external input enable 0 this bit enables the generation of a trigger event for request channel 0 (e.g. for interrupt generation) when a selected edge is detected. 0 b the trigger event is disabled 1 b the trigger event is enabled inp0 [14:12] rw input node pointer this bit field determines the destination (output channel) for trigger event 0 (if enabled by eien0). 000 b the event of input channel 0 triggers output channel 0 (signal int00) 001 b the event of input channel 0 triggers output channel 1 (signal int01) 010 b the event of input channel 0 triggers output channel 2 (signal int02) 011 b the event of input channel 0 triggers output channel 3 (signal int03) 100 b reserved, do not use this combination 101 b reserved, do not use this combination 110 b reserved, do not use this combination 111 b reserved, do not use this combination exis1 [21:20] rw external input selection 1 this bit field determines which input line is selected for input channel 1. 00 b input 10 is selected 01 b input 11 is selected 10 b input 12 is selected 11 b input 13 is selected field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-107 v1.1, 2011-03 32-bit scu, v1.0 fen1 24 rw falling edge enable 1 this bit determines if the falling edge of input channel 1 is used to set bit intf1. 0 b the falling edge is not used 1 b the detection of a falling edge of input channel 1 generates a trigger event (intf1 becomes set) ren1 25 rw rising edge enable 1 this bit determines if the rising edge of input channel 1 is used to set bit intf1. 0 b the rising edge is not used 1 b the detection of a rising edge of input channel 1 generates a trigger event (intf1 becomes set) lden1 26 rw level detection enable 1 this bit determines if bit intf1 is cleared automatically if an edge of the input input channel 1 is detected, which has not been selected (rising edge with ren1 = 0 or falling edge with fen1 = 0). 0 b bit intf1 will not be cleared 1 b bit intf1 will be cleared eien1 27 rw external input enable 1 this bit enables the generation of a trigger event for request channel 1 (e.g. for interrupt generation) when a selected edge is detected. 0 b the trigger event is disabled 1 b the trigger event is enabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-108 v1.1, 2011-03 32-bit scu, v1.0 inp1 [30:28] rw input node pointer this bit field determines the destination (output channel) for trigger event 1 (if enabled by eien1). 000 b the event of input channel 1 triggers output channel 0 (signal int10) 001 b the event of input channel 1 triggers output channel 1 (signal int11) 010 b the event of input channel 1 triggers output channel 2 (signal int12) 011 b the event of input channel 1 triggers output channel 3 (signal int13) 100 b reserved, do not use this combination 101 b reserved, do not use this combination 110 b reserved, do not use this combination 111 b reserved, do not use this combination 0 [3:0], [7:6], [19:15], [23:22], 31 r reserved read as 0; should be written with 0. eicr1 external input channel register 1 (084 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0inp3 ei en3 ld en3 r en3 f en3 0 exis3 0 r rw rwrwrwrw r rw r 1514131211109876543210 0inp2 ei en2 ld en2 r en2 f en2 0 exis2 0 r rw rwrwrwrw r rw r field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-109 v1.1, 2011-03 32-bit scu, v1.0 field bits type description exis2 [5:4] rw external input selection 2 this bit field determines which input line is selected for input channel 2. 00 b input 20 is selected 01 b input 21 is selected 10 b input 22 is selected 11 b input 23 is selected fen2 8rw falling edge enable 2 this bit determines if the falling edge of input channel 2 is used to set bit intf2. 0 b the falling edge is not used 1 b the detection of a falling edge of input channel 2 generates a trigger event (intf3 becomes set) ren2 9rw rising edge enable 2 this bit determines if the rising edge of signal input channel 2 is used to set bit intf2. 0 b the rising edge is not used 1 b the detection of a rising edge of input channel 2 generates a trigger event (intf2 becomes set) lden2 10 rw level detection enable 2 this bit determines if bit intf2 is cleared automatically if an edge of the input input channel 2 is detected, which has not been selected (rising edge with ren2 = 0 or falling edge with fen2 = 0). 0 b bit intf2 will not be cleared 1 b bit intf2 will be cleared eien2 11 rw external input enable 2 this bit enables the generation of a trigger event for request channel 2 (e.g. for interrupt generation) when a selected edge is detected. 0 b the trigger event is disabled 1 b the trigger event is enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-110 v1.1, 2011-03 32-bit scu, v1.0 inp2 [14:12] rw input node pointer this bit field determines the destination (output channel) for trigger event 2 (if enabled by eien2). 000 b the event of input channel 2 triggers output channel 0 (signal int20) 001 b the event of input channel 2 triggers output channel 1 (signal int21) 010 b the event of input channel 2 triggers output channel 2 (signal int22) 011 b the event of input channel 2 triggers output channel 3 (signal int23) 100 b reserved, do not use this combination 101 b reserved, do not use this combination 110 b reserved, do not use this combination 111 b reserved, do not use this combination exis3 [21:20] rw external input selection 3 this bit field determines which input line is selected for input channel 3. 00 b input 30 is selected 01 b input 31 is selected 10 b input 32 is selected 11 b input 33 is selected fen3 24 rw falling edge enable 3 this bit determines if the falling edge of input channel 3 is used to set bit intf3. 0 b the falling edge is not used 1 b the detection of a falling edge of input channel 3 generates a trigger event (intf3 becomes set) ren3 25 rw rising edge enable 3 this bit determines if the rising edge of signal input channel 3 is used to set bit intf3. 0 b the rising edge is not used 1 b the detection of a rising edge of input channel 3 generates a trigger event (intf3 becomes set) field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-111 v1.1, 2011-03 32-bit scu, v1.0 the external input flag register eifr contains all status flags for the external input channels. the bits in this register can be cl eared by software by setting fmr.fcx, and set by setting fmr.fsx. lden3 26 rw level detection enable 3 this bit determines if bit intf3 is cleared automatically if an edge of the input input channel 3 is detected, which has not been selected (rising edge with ren3 = 0 or falling edge with fen3 = 0). 0 b bit intf3 will not be cleared 1 b bit intf3 will be cleared eien3 27 rw external interrupt enable 3 this bit enables the generation of a trigger event for request channel 3 (e.g. for interrupt generation) when a selected edge is detected. 0 b the trigger event is disabled 1 b the trigger event is enabled inp3 [30:28] rw interrupt node pointer this bit field determines the destination (output channel) for trigger event 3 (if enabled by eien3). 000 b the event of input channel 3 triggers output channel 0 (signal int30) 001 b the event of input channel 3 triggers output channel 1 (signal int31) 010 b the event of input channel 3 triggers output channel 2 (signal int32) 011 b the event of input channel 3 triggers output channel 3 (signal int33) 100 b reserved, do not use this combination 101 b reserved, do not use this combination 110 b reserved, do not use this combination 111 b reserved, do not use this combination 0 [3:0], [7:6], [19:15], [23:22], 31 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-112 v1.1, 2011-03 32-bit scu, v1.0 eifr external input flag register (088 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 int f3 int f2 int f1 int f0 r rhrhrhrh field bits type description intfx (x = 0-3) xrh external interrupt flag of channel x this bit monitors the status flag of the event trigger condition for the input channel x. this bit is automatically cleared when the selected condition (see renx, fenx) is no longer met (if ldenx = 1) or remains set until it is cleared by software (if ldenx = 0). 0 [31:4] r reserved read as 0; should be written with 0. fmr flag modificatio n register (08c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 fc 3 fc 2 fc 1 fc 0 r wwww 1514131211109876543210 0 fs 3 fs 2 fs 1 fs 0 r wwww www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-113 v1.1, 2011-03 32-bit scu, v1.0 the pattern detection result register monitors the combinatorial output status of the pattern detection units. field bits type description fsx (x = 0-3) xw set flag intfx for channel x setting this bit will set the corresponding bit intfx in register eifr. reading this bit always delivers a 0. 0 b the bit x in register eifr is not modified 1 b the bit x in register eifr is set fcx (x = 0-3) 16 + x w clear flag intfx for channel x setting this bit will clear the corresponding bit intfx in register eifr. reading this bit always delivers a 0. 0 b the bit x in register eifr is not modified 1 b the bit x in register eifr is cleared 0 [15:4], [31:20] r reserved read as 0; should be written with 0. pdrr pattern detection result register (090 h ) reset value: 0000 000f h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 pdr 3 pdr 2 pdr 1 pdr 0 r rhrhrhrh field bits type description pdry (y = 0-3) yrh pattern detection result of channel y this bit monitors the output status of the pattern detection for the output channel y. 0 [31:4] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-114 v1.1, 2011-03 32-bit scu, v1.0 the interrupt gating control registers igcr0 and igcr1 contain bits to enable the pattern detection and to control the gating for output channel 0 to 3. igcr0 interrupt gating register 0 (094 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 igp1 ge en1 0 iss1 0 ipen 13 ipen 12 ipen 11 ipen 10 rw rw r rw r rw rw rw rw 1514131211109876543210 igp0 ge en0 0 iss0 0 ipen 03 ipen 02 ipen 01 ipen 00 rw rw r rw r rw rw rw rw field bits type description ipen0x (x = 0-3) xrw interrupt pattern en able for channel 0 bit ipen0x determines if the flag intfx of channel x takes part in the pattern detection for the gating of the requests for the output signals gouty and iouty. 0 b the bit intfx does not take part in the pattern detection 1 b the bit intfx is taken into consideration for the pattern detection iss0 [9:8] rw internal trigger source selection this bit field defines which input is selected as peripheral trigger input fo r ogu0. the possible input signals are given in table 3-13 . 00 b the peripheral trigger function is disabled 01 b input eru_ogu01 is selected 10 b input eru_ogu02 is selected 11 b input eru_ogu03 is selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-115 v1.1, 2011-03 32-bit scu, v1.0 geen0 13 rw generate event enable 0 bit geen0 enables the generation of a trigger event for output channel 0 when the result of the pattern detection changes. when using this feature, a trigger (e.g. for an interrupt) is generated during the first clock cycle when a pattern is detected or when it is no longer detected. 0 b the trigger generation at a change of the pattern detection result is disabled 1 b the trigger generation at a change of the pattern detection result is enabled iss1 [25:24] rw internal trigger source selection this bit field defines which input is selected as peripheral trigger input fo r ogu1. the possible input signals are given in table 3-13 . 00 b the peripheral trigger function is disabled 01 b input eru_ogu11 is selected 10 b input eru_ogu12 is selected 11 b input eru_ogu13 is selected igp0 [15:14] rw interrupt gating pattern 0 bit field igp0 determines how the pattern detection influences the output lines gout0 and iout0. 00 b the detected pattern is not taken into account. an activation of iout0 is always possible due to a trigger event. 01 b the detected pattern is not taken into account. an activation of iout0 is not possible. 10 b the detected pattern is taken into account. an activation of iout0 is only possible due to a trigger event while the pattern is detected. 11 b the detected pattern is taken into account. an activation of iout0 is only possible due to a trigger event while the pattern is not detected. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-116 v1.1, 2011-03 32-bit scu, v1.0 ipen1x (x = 0-3) 16+x rw interrupt pattern en able for channel 1 bit ipen1x determines if the flag intfx of channel x takes part in the pattern detection for the gating of the requests for the output signals gouty and iouty. 0 b the bit intfx does not take part in the pattern detection 1 b the bit intfx is taken into consideration for the pattern detection geen1 29 rw generate event enable 1 bit geen1 enables the generation of a trigger event for output channel 1 when the result of the pattern detection changes. when using this feature, a trigger (e.g. for an interrupt) is generated during the first clock cycle when a pattern is detected, or when it is no longer detected. 0 b the trigger generation at a change of the pattern detection result is disabled 1 b the trigger generation at a change of the pattern detection result is enabled igp1 [31:30] rw interrupt gating pattern 1 bit field igp1 determines how the pattern detection influences the output lines gout1 and iout1. 00 b the detected pattern is not taken into account. an activation of iout1 is always possible due to a trigger event. 01 b the detected pattern is not taken into account. an activation of iout1 is not possible. 10 b the detected pattern is taken into account. an activation of iout1 is only possible due to a trigger event while the pattern is detected. 11 b the detected pattern is taken into account. an activation of iout1 is only possible due to a trigger event while the pattern is not detected. 0 [7:4], [12:10], [23:20],[ 28:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-117 v1.1, 2011-03 32-bit scu, v1.0 igcr1 interrupt gating register 1 (098 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 igp3 ge en3 0 iss3 0 ipen 33 ipen 32 ipen 31 ipen 30 rw rw r rw r rw rw rw rw 1514131211109876543210 igp2 ge en2 0 iss2 0 ipen 23 ipen 22 ipen 21 ipen 20 rw rw r rw r rw rw rw rw field bits type description ipen2x (x = 0-3) xrw interrupt pattern en able for channel 2 bit ipen2x determines if the flag intfx of channel x takes part in the pattern detection for the gating of the requests for the output signals gouty and iouty. 0 b the bit intfx does not take part in the pattern detection 1 b the bit intfx is taken into consideration for the pattern detection iss2 [9:8] rw internal trigger source selection this bit field defines which input is selected as peripheral trigger input for ogu2. the possible input signals are given in table 3-13 . 00 b the peripheral trigger function is disabled 01 b input eru_ogu21 is selected 10 b input eru_ogu22 is selected 11 b input eru_ogu23 is selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-118 v1.1, 2011-03 32-bit scu, v1.0 geen2 13 rw generate event enable 2 bit geen2 enables the generation of a trigger event for output channel 2 when the result of the pattern detection changes. when using this feature, a trigger (e.g. for an interrupt) is generated during the first clock cycle when a pattern is detected, or when it is no longer detected. 0 b the trigger generation at a change of the pattern detection result is disabled 1 b the trigger generation at a change of the pattern detection result is enabled igp2 [15:14] rw interrupt gating pattern 2 bit field igp2 determines how the pattern detection influences the output lines gout2 and iout2. 00 b the detected pattern is not taken into account. an activation of iout2 is always possible due to a trigger event. 01 b the detected pattern is not taken into account. an activation of iout2 is not possible. 10 b the detected pattern is taken into account. an activation of iout2 is only possible due to a trigger event while the pattern is detected. 11 b the detected pattern is taken into account. an activation of iout2 is only possible due to a trigger event while the pattern is not detected. ipen3x (x = 0-3) 16+x rw interrupt pattern en able for channel 3 bit ipen3x determines if the flag intfx of channel x takes part in the pattern detection for the gating of the requests for the output signals gouty and iouty. 0 b the bit intfx does not take part in the pattern detection 1 b the bit intfx is taken into consideration for the pattern detection field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-119 v1.1, 2011-03 32-bit scu, v1.0 iss3 [25:24] rw internal trigger source selection this bit field defines which input is selected as peripheral trigger input for ogu13. the possible input signals are given in table 3-13 . 00 b the peripheral trigger function is disabled 01 b input eru_ogu31 is selected 10 b input eru_ogu32 is selected 11 b input eru_ogu33 is selected geen3 29 rw generate event enable 3 bit geen3 enables the generation of a trigger event for output channel 3 when the result of the pattern detection changes. when using this feature, a trigger (e.g. for an interrupt) is generated during the first clock cycle when a pattern is detected, or when it is no longer detected. 0 b the trigger generation at a change of the pattern detection result is disabled 1 b the trigger generation at a change of the pattern detection result is enabled igp3 [31:30] rw interrupt gating pattern 3 bit field igp3 determines how the pattern detection influences the output lines gout3 and iout3. 00 b the detected pattern is not taken into account. an activation of iout3 is always possible due to a trigger event. 01 b the detected pattern is not taken into account. an activation of iout3 is not possible. 10 b the detected pattern is taken into account. an activation of iout3 is only possible due to a trigger event while the pattern is detected. 11 b the detected pattern is taken into account. an activation of iout3 is only possible due to a trigger event while the pattern is not detected. 0 [7:4], [12:10], [23:20], [28:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-120 v1.1, 2011-03 32-bit scu, v1.0 3.4 power management this section describes the power managem ent system of the TC1798. topics covered here include the internal system interfaces, ex ternal interfaces, and the operations of the cpu and peripherals. 3.4.1 power management overview the TC1798 power-management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. as shown in table 3-15 , there are three power management modes available: ? run mode ? idle mode ? sleep mode the power-management modes provide flexible reduction of power consumption through a combination of techniques, including: ? stopping the cpu ? stopping other system components individually ? clock-speed reduction of some peripheral components individually the power management controls the power mode of all system components during run mode, idle mode, and sleep mode. this flexibility in power management provides minimum power consumption for any application. in typical operation, idle mode and sleep mode may be entered and exited frequently during the run time of an application. for example, syst em software will typically cause table 3-15 power management mode summary mode description run mode the system is fully operational. cp u and peripherals are enabled, as determined by software. idle mode the cpu is disabled, waiting for a condition to return it to run mode. idle mode can be entered by software when the processor has no active tasks to perform. processor memory is accessible to peripherals. an application reset, watchdog timer event, an nmi trap, or any interrupt for the cpu will return the system to run mode. sleep mode only those peripherals programmed to operate in sleep mode are active. the other peripheral module will be shut down. interrupts for the cpu, a watchdog timer event, an nmi trap, or an application reset will return the system to run mode. entering th is state requires an orderly shut- down controlled by the power management state machine. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-121 v1.1, 2011-03 32-bit scu, v1.0 the cpu to enter idle mode each time it has to wait for an interrupt before continuing its tasks. in sleep mode and idle mode, wake-up is performed automatically when any interrupt is detected or if an nmi trap is activated. 3.4.2 power management modes this section describes in more detail the power management modes, their operations, and how power management modes are entered and exited. it also describes the behavior of TC1798 system components in all power management modes. 3.4.2.1 idle mode the idle mode is requested by software when writing to register pmcsr.reqslp = 01 b . the cpu finishes its current operation, sends an acknowledge to the power management, and then enters an inactive state in which the cpu and the dmi and pmi memory units are shut off. other system components that are able to write to register pmcsr can also request the idle mode. for example, the pcpdma controller can request idle mode by writing to the pmcsr register. during idle mode, memory accesses to the dmi and pmi cause these units to awaken automatically to handle the transactions. when memory transactions are complete, the dmi and pmi return to idle mode again. the system will return to run mode through the occurrence of any of the following conditions: ? an interrupt is received from an interrupt source of the cpu ? an nmi trap request is received ? an application reset is generated if any of these conditions arise, the TC1798 immediately awakens and returns to run mode. if it is awakened by a reset, the TC1798 system begins its reset sequence. if it is awakened by a watchdog timer overflow event, it executes the instruction following the one that was last executed before idle mode was entered. if it is awakened by an nmi or interrupt, the cpu will immediately vector to the appropriate handler. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-122 v1.1, 2011-03 32-bit scu, v1.0 3.4.2.2 sleep mode the sleep mode is requested by software when writing to register pmcsr.reqslp = 10 b . entering sleep mode sleep mode is entered in two steps: 1. the cpu is put into idle mode as described in the previous section. when the power management receives the idle acknowledge back from the cpu, it proceeds with the second step. 2. each fpi bus unit is requested to ent er the sleep mode. the response of each fpi bus unit to the sleep request is deter mined by its clock control register. these clock control registers must have been previously configured by software. TC1798 state during sleep mode sleep mode is disabled for a unit if mod_clc. edis is set. the sleep request is ignored in this case and the corresponding unit continues normal operation. if mod_clc.edis is cleared, sleep mode is enabled for this unit and the unit enters sleep mode. two actions then occur: ? the unit finishes whatever bus transaction was in progress when the signal was received ? the unit functions are suspended depending on bit mod_clc.fsoe, the module is either immediately stopped (mod_clc.fsoe = 1), or the unit is allowed to finish ongoing operations (mod_clc.fsoe = 0) before the sleep mode is entered. for example, setting mod_clc.fsoe to 1 for a serial port will stop all actions in the serial port immediately when the sleep request is received. ongoing transmissions or receptions will be aborted. if mod_clc.fsoe is cleared, ongoing transmissions or receptions will be completed, before sleep mode is entered. the purpose of setting mod_clc.fsoe = 1 is to allow a debugger to observe the internal state of a peripheral unit immediately. exiting sleep mode the system will be returned to run mode by th e same events that exit idle mode. the response of the cpu to being awakened is also the same as for idle mode. peripheral units that have entered sleep mode will switch back to their selected run mode operation. 3.4.3 power management control and status register, pmcsr the set of registers used for power management is divided between central TC1798 components and peripheral components. the pmcs r register provides software control www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-123 v1.1, 2011-03 32-bit scu, v1.0 and status information for the central part. t here are individual clock control registers for peripheral components because the sleep mode behavior of each peripheral component is programmable. when entering idle mode and sleep mode, the power management directly controls TC1798 components such as the cpu, but indirectly controls peripheral components through their clock control registers. pmcsr power management control and status register (0b0 h ) reset value: 0000 0100 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0pmst 0reqslp rrh rrwh field bits type function reqslp [1:0] rwh idle mode and sleep mode request 00 b normal run mode 01 b request idle mode 10 b request sleep mode 11 b reserved; do not use this combination in idle mode or sleep mode, these bits are cleared in response to an interrupt for the cpu, or when bit 15 of the watchdog timer count register (the wdt_sr.tim[15] bit) changes from 0 to 1. pmst [10:8] rh power management status 000 b waiting for pll lock condition 001 b normal run mode 010 b idle mode requested 011 b idle mode acknowledged 100 b sleep mode 101 b reserved, do not use this combination 110 b reserved, do not use this combination 111 b reserved, do not use this combination www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-124 v1.1, 2011-03 32-bit scu, v1.0 0 [7:2], [31:11] r reserved read as 0; should be written with 0. field bits type function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-125 v1.1, 2011-03 32-bit scu, v1.0 3.5 software boot support in order to determine the correct starting point of operation for the software a minimum of hardware support is requir ed. as much as possible is done via software. some decisions have to be done in hardware because they must be known before any software is operational. for a startup operation there are two general cases that have to be handled: ? differentiation between test mode and normal mode for each power-on reset event (see section 3.5.1 ) ? configuration of the boot option for each application reset event (see section 3.5.2 ) 3.5.1 configuration done with start-up with the device power-on some basic operating mode selection has to be made. the first decision that has to be made is if the device should operate in test mode or in normal (customer) mode. the test mode is only for infineon internal usage not for any customer and has nothing to do with debugging. if the normal mode was selected the next decision is which debug interface type issued for debugging for this session (until the next power-on event). after these two decisions were made the detailed decision has to be made to define the real startup configuration. most is made via the software and can be supported by some hardware selections depending on the startup configuration that should be selected. 3.5.2 start-up configuration options for the support of the start-up pins p0.0 to p0.7 are latched with the rising edge of the application reset and stored in register ststat.hwcfg. the update of bit field ststat.hwcfg with the latched value is only done if bit ststat.ludis is cleared. if bit ststat.ludis is set the value of ststat.hwcfg is not updated. table 3-16 normal mode / test mode input selection field description testl latched test signal 0 a test mode can be selected 1 normal mode is selected trstl latched trst signal 0 the jtag interface is active 1 the dap interface is active www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-126 v1.1, 2011-03 32-bit scu, v1.0 3.5.3 start-up registers 3.5.3.1 start-up status register register ststat contains the information required by the boot software to identify the different start-up settings that can be selected. ststat start-up status register (0c0 h ) reset value: 0008 80xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 spd en trs tl ext ben lu dis fcb ae r rhrhrhrhrh 1514131211109876543210 mod e 0hwcfg rh r rh field bits type description hwcfg [7:0] rh hardware configuration setting this bit field contains the value that is used by the boot software. this bit field is updated in case of an application reset with the content by register swrstcon.swcfg if bit swrstcon.swboot and rststat.sw are set. this bit field is updated in case of an application reset with the content of the latches of p0.0 to p.0.7 if bit swrstcon.swboot or rststat.sw are cleared and bit ststat.ludis is cleared. this bit field is left unchanged in case of an application reset and is not updated with the content of the latches of p0.0 to p.0.7 if bit swrstcon.swboot or rststat.sw are cleared and bit ststat.ludis is set. this bit field is updated with the value written to bit field stcon.hwcfg on a software write action. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-127 v1.1, 2011-03 32-bit scu, v1.0 mode 15 rh mode this bit indicates if the test mode is entered or not. 0 b a test mode can be selected 1 b normal mode is selected fcbae 16 rh flash config. sector access enable 0 b flash config sector is not accessible. instead the flash memory area is accessed. 1 b flash config sector is accessible. the flash memory area can not be accessed. this bit can be cleared by setting bit stcon.cfcbae. this bit can be set by setting bit stcon.sfcbae. ludis 17 rh latch update disable 0 b bit field ststat.hwcfg is automatically updated with the latched value of pins p0.0 to p0.7 1 b bit field ststat.hwcfg is not updated with the latched value of pins p0.0 to p0.7 this bit can be set by setting bit syscon.setludis. extben 18 rh external boot enable 0 b no boot configuration value is fetched by the ebu 1 b a boot configuration value is fetched by the ebu this bit can be set by setting bit syscon.setextben. trstl 19 rh trstl status this bit simply displa ys the value of trstl. spden 20 rh single pin dap mode enable 0 b single pin dap mode is disabled 1 b single pin dap mode is enabled 0 [14:8], [31:21] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-128 v1.1, 2011-03 32-bit scu, v1.0 stcon start-up configuration register (0c4 h ) reset value: 0000 8000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 stp cfc bae sfc bae 0hwcfg rw w w r w field bits type description hwcfg [7:0] w hardware configuration setting writing to this bit field updates bit field ststat.hwcfg. reading this bit field returns zero. sfcbae 13 w set flash config. sector access enable setting this bit sets bit ststat.fcbae. reading this bit returns always a zero. note: this bit may not be set in parallel with bit cfcbae. cfcbae 14 w clear flash config. sector access enable setting this bit clears bit stcon.fcbae. reading this bit returns always a zero. note: this bit may not be set in parallel with bit sfcbae. stp 15 rw start-up protection setting 0 b start-up code is executed. start-up protection is disabled. 1 b start-up code protection is active this bit is also cleared by an application reset. 0 [12:8], [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-129 v1.1, 2011-03 32-bit scu, v1.0 3.6 ecc error handling the on-chip ram and flash modules check ecc information during read accesses and in case of an error a signal is generated. these signals are combined and trigger a trap. figure 3-27 ecc erro r control logic 3.6.1 ecc software testing support this can be done for each module individually by simply disabling the ecc protection in the module change the content of a memory address enable ecc again and read the memory address again. for more information see the different module chapters. ecc _error mem0 > ecc_trap ecc error eccstat. mem0 eccclr. mem0 clear set mem1 ecc error eccstat. mem1 eccclr. mem1 clear set mem15 ecc error eccstat. mem15 eccclr. mem15 clear set ecccon. eccen0 ecccon. eccen1 ecccon. eccen15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-130 v1.1, 2011-03 32-bit scu, v1.0 3.6.2 ecc registers ecccon ecc control register (0d0 h ) reset value: 0000 ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 1 ecc enb mu ecc ene bu ecc ens ri ecc ene ray ecc enc an ecc enc mem ecc enp ram ecc en lmu 1 ecc enp spr 1 ecc end spr rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description eccendspr 0rw ecc error trap enable for dspr and dcache memory this bit determine whether a trap is requested if an uncorrected ecc error is detected in the dspr / dcache memory. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested eccenpspr 2rw ecc error trap enable for pdpr and icache memory this bit determine whether a trap is requested if an uncorrected ecc error is detected in the pspr / icache memory. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested eccenlmu 4rw ecc error trap enable for lmu memory this bit determine whether a trap is requested if an uncorrected ecc error is detected in the lmu memory. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-131 v1.1, 2011-03 32-bit scu, v1.0 eccenpram 5rw ecc error trap enable for pcp pram this bit determine whether a trap is requested if an uncorrected ecc error is de tected in the pcp pram memory. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested eccencmem 6rw ecc error trap enable for pcp cmem this bit determine whether a trap is requested if an uncorrected ecc error is detected in the pcp cmem memory. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested eccencan 7rw ecc error trap enable for can memory this bit determine whether a trap is requested if an uncorrected ecc error is detected in the can memory. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested ecceneray 8rw ecc error trap enable for eray memory this bit determine whether a trap is requested if an uncorrected ecc error is detected in the eray memories. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested eccensri 9rw ecc error trap enable for sri-bus this bit determine whether a trap is requested if an uncorrected ecc error is detected by the sri-bus protocol. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested eccenebu 10 rw ecc error trap enable for ebu this bit determine whether a trap is requested if an uncorrected ecc error is detected by the ebu. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-132 v1.1, 2011-03 32-bit scu, v1.0 note: register ecccon is endinit- protected for wr ite operations. eccenbmu 11 rw ecc error trap enable for bmu this bit determine whether a trap is requested if an uncorrected ecc error is detected by the bmu. 0 b no ecc error trap trigger is requested 1 b a ecc error trap trigger is requested 1 1, 3, [15:12] rw reserved should be written with 1. 0 [31:16] r reserved read as 0; should be written with 0. eccstat ecc status register (0d4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0bmuebusri era y can c mem p ram lmu 0 psp r 0 dsp r r rhrhrhrhrhrhrhrh r rh r rh field bits type description dspr 0rh ecc error flag for dspr and dcache memory this bit indicate whether an ecc error has been detected in the dspr / dcache memory. 0 b no ecc error detected 1 b ecc error is detected pspr 2rh ecc error flag for pspr and icache memory this bit indicate whether an ecc error has been detected in the pspr / icache memory. 0 b no ecc error detected 1 b ecc error is detected field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-133 v1.1, 2011-03 32-bit scu, v1.0 lmu 4rh ecc error flag for lmu memory this bit indicate whether an ecc error has been detected in the lmu memory. 0 b no ecc error detected 1 b ecc error is detected pram 5rh ecc error flag for parameter ram memory this bit indicate whether an ecc error has been detected in the parameter ram memory. 0 b no ecc error detected 1 b ecc error is detected cmem 6rh ecc error flag for code memory this bit indicate whether an ecc error has been detected in the code memory. 0 b no ecc error detected 1 b ecc error is detected can 7rh ecc error flag for can memory this bit indicate whether an ecc error has been detected in the can memory. 0 b no ecc error detected 1 b ecc error is detected eray 8rh ecc error flag for eray memory this bit indicate whether an ecc error has been detected in the eray memory. 0 b no ecc error detected 1 b ecc error is detected sri 9rh ecc error flag for sri-bus this bit indicate whether an ecc error has been detected by the sri-bus. 0 b no ecc error detected 1 b ecc error is detected ebu 10 rh ecc error flag for ebu this bit indicate whether an ecc error has been detected in the ebu. 0 b no ecc error detected 1 b ecc error is detected field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-134 v1.1, 2011-03 32-bit scu, v1.0 bmu 11 rh ecc error flag for bmu this bit indicate whether an ecc error has been detected in the bmu. 0 b no ecc error detected 1 b ecc error is detected 0 1,3, [31:12] r reserved read as 0; should be written with 0. eccclr ecc clear register (0d8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0bmuebusri era y can c mem p ram lmu 0 psp r 0 dsp r r wwwwwwww r w r w field bits type description dspr 0w clear dspr and dcache eec error status 0 b no action 1 b setting this bit clears bit eecstat.dspr this bit always read as 0. pspr 2w clear pspr and pcache eec error status 0 b no action 1 b setting this bit clears bit eecstat.pspr this bit always read as 0. lmu 4w clear lmu memory eec error status 0 b no action 1 b setting this bit clears bit eecstat.lmu this bit always read as 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-135 v1.1, 2011-03 32-bit scu, v1.0 pram 5w clear parameter ram memory eec error status 0 b no action 1 b setting this bit clears bit eecstat.pram this bit always read as 0. cmem 6w clear parameter code memory eec error status 0 b no action 1 b setting this bit clears bit eecstat.cmem this bit always read as 0. can 7w clear can memory eec error status 0 b no action 1 b setting this bit clears bit eecstat.can this bit always read as 0. eray 8w clear eray memory eec error status 0 b no action 1 b setting this bit clears bit eecstat.eray this bit always read as 0. sri 9w clear sri-bus eec error status 0 b no action 1 b setting this bit clears bit eecstat.sri this bit always read as 0. ebu 10 w clear ebu eec error status 0 b no action 1 b setting this bit clears bit eecstat.ebu this bit always read as 0. bmu 11 w clear bmu eec error status 0 b no action 1 b setting this bit clears bit eecstat.bmu this bit always read as 0. 0 1, 3, [31:12] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-136 v1.1, 2011-03 32-bit scu, v1.0 3.7 die temperature measurement the die temperature sensor (dts) generates a measurement result that indicates directly the current temperature. the result of the measurement is displayed via bit field dtsstat.result. in order to start one measurement bit dtscon.start needs to be set. the dts has to be enabled before it can be used via bit dtscon.pwd. when the dts is powered after the start-up time of the dts (defined in the data sheet) a temperature measurement can be started. note: if bit field dtsstat.result is read before the first measurement was finished it will return 0x000. when a measurement is started the result is available after the measurement time passed. if the dts is ready to start a measurement can be checked via bit dtsstat.rdy. if a started meas urement is finished or still in progress is indicated via the status bit dtsstat.busy. the measurement time is also defined in the data sheet. in order to adjust production variations bit field dtscon.cal should be programmed with a predefined value. the value is located at address 0xd0000018 for the complete register dtscon with bit dtscon.pwd cleared. note: the first measurement after the dts was powered delivers a result without calibration adjustment and should be ignored therefore. the formula to calculate the die temperature is defined in the data sheet. note: the maximum resolution is only achieved for a measurement that is part of multiple continuos measurements. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-137 v1.1, 2011-03 32-bit scu, v1.0 3.7.1 die temperature sensor register dtscon die temperature sensor control register(0e4 h ) reset value: 0000 0001 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0cal rrw 1514131211109876543210 cal 0 sta rt pwd rw r w rw field bits type description pwd 0rw sensor power down this bit defines the dts power state. 0 b the dts is powered 1 b the dts is not powered start 1w sensor measurement start this bit starts a measurement of the dts. 0 b no dts measurement is started 1 b a dts measurement is started if set this bit is automatically cleared. this bit always reads as zero. cal [23:4] rw calibration value this bit field interfaces the calibration values to the dts. 0 [3:2], [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-138 v1.1, 2011-03 32-bit scu, v1.0 dtsstat die temperature sensor status register(0e0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 bus y rdy 0 result rh rh r rh field bits type description result [9:0] rh result of the dts measurement this bit field shows the result of the dts measurement. the value given is directly related to the die temperature. only the bit [9:2] have to be evaluated. the formula for mapping the result to a temperature will follow later. rdy 14 rh sensor ready status this bit indicate the dts is ready or not. 0 b the dts is not ready 1 b the dts is ready busy 15 rh sensor busy status this bit indicate the dts is currently busy or not. if the sensor is busy curr ently a measurement is running and the result should not be used. 0 b the dts is not busy 1 b the dts is busy note: this bit is updated 2 cycles after bit dtscon.start is set. 0 [13:10] , [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-139 v1.1, 2011-03 32-bit scu, v1.0 3.8 watchdog timer this section describes the TC1798 watchdog timer (wdt). topics include an overview of the wdt function and descriptions of the registers, the password-protection scheme, accessing registers, mo des, and initialization. 3.8.1 watchdog timer overview the wdt provides a highly reliable and secure way to detect and recover from software or hardware failure. the wdt helps to abort an accidental malfunction of the TC1798 in a user-specified time period . when enabled, the wdt c an cause the TC1798 system to be reset if the wdt is not serviced within a user-programmable time period. the cpu must service the wdt within this time interval to prevent the wdt from causing a TC1798 system or application reset. hence, routine service of the wdt confirms that the system is functioning properly. in addition to this standard ?watchdog? function, the wdt incorporates the end-of- initialization (endinit) feature and monitors its modifications. because servicing the watchdog and modifications of the endinit bit are critical functions that must not be allowed in case of a system malfunction, a sophisticated scheme is implemented that requires a password and guard bits during accesses to the wdt control register. any write access that does not deliver the correct password or the correct value for the guard bits is regarded as a malfunction of the system, and a watchdog reset is requested. in addition, even after a valid access has been performed and the endinit bit has been cleared to provide access to the critical registers, the watchdog imposes a time limit for this access window. if bit endinit has not been properly set again before this limit expires, the system is assumed to have malfunctioned, and a watchdog reset is requested. these stringent requirements, although not guaranteed, nonetheless provide a high degree of assurance of the robustness of system operation. a further enhancement in the TC1798?s wdt is its reset prewarning operation. instead of immediately resetting the device on the detection of an error (the way that standard watchdogs do), the wdt first issues a non-maskable interrupt (nmi) to the cpu before finally resetting the device at a specified time period later. 3.8.2 features of the watchdog timer the main features of the wdt are summarized here. ? 16-bit watchdog counter ? selectable input frequency: f fpi /256 or f fpi /16384 ? 16-bit user-definable reload value for normal watchdog operation, fixed reload value for time-out and prewarning modes ? incorporation of the endinit bit and monitoring of its modifications www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-140 v1.1, 2011-03 32-bit scu, v1.0 ? sophisticated password access mechanism with fixed and user-definable password fields ? access error detection: inva lid password (during first access) or invalid guard bits (during second access) trigger the watchdog reset generation ? overflow error detection: an overflow of the counter triggers the watchdog reset generation ? watchdog function can be disabled; access protection and endinit bit monitor function remain enabled ? double reset detection 3.8.3 the endinit function it is a prerequisite to understand the endinit bit and its function for better understanding of the descriptions in the following sections. hence, its function is explained first. there are a number of registers in the tc 1798 that are usually programmed only once during the initialization sequence of the application. modification of such registers during normal application run can have a severe impact on the overall operation of modules or the entire system. while the supervisor mode, that allows writes to registers only when it is active, provides a certain level of protection against unintentional modifications, it may not provide enough security for system-critical registers. the TC1798 provides one more level of protection for such registers via the endinit feature. this is a highly secure write-protection scheme that makes unintentional modifications of registers protected by this feature nearly impossible. the endinit feature consists of an endinit bi t incorporated in the wdt control register, wdt_con0. registers protected via endini t determine whether or not writes are enabled. writes are only enabled if bit endinit = 0 and supervisor mode is active. write attempts if this condition is not true will be discarded and the register contents will not be modified in this case. the bcu controls the further operation following a discarded write access. to get the highest level of security, this bit is incorporated in the highly secure access protection scheme implemented in the wdt. th is is a complex procedure, that makes it nearly impossible for the endinit bit to be modified unintentionally. in addition, the wdt monitors endinit bit modifications by starting a time-out sequence each time software opens access to the critical registers through clearing bit endinit. if the time out period ends before bit endinit is set again, a malfunction of the software is assumed and a reset request is generated. the access-protection scheme and the endinit time-out operation of the wdt is described in the following sections. table 3-17 lists the registers that are protected via the endinit feature in the TC1798. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-141 v1.1, 2011-03 32-bit scu, v1.0 note: the clearing of the endinit bit take s some time. accesses to endinit-protected registers after the clearing of the endint bit must only be done when bit endinit is really cleared. as a solution, wdt_co n0 (the register with the endinit bit) should be read back once before endinit-pr otected registers are accessed the first time after bit endinit has been cleared. table 3-17 TC1798 registers prot ected via the endinit feature register name description mod_clc all clock control registers of the individual peripheral modules are endinit-protected mod_fdr all clock fractional divider registers of the individual peripheral modules are endinit-protected btv, biv, isp trap and interrupt vector table pointer as well as the interrupt stack pointer are endinit-protected miecon smacon compat cpu control registers flash0_fcon flash1_fcon flash0_rdwcfg0 flash0_rdwcfg1 flash0_rdwcfg2 flash1_rdwcfg0 flash1_rdwcfg1 flash1_rdwcfg2 flash0_marp flash1_marp flash0_eccw flash1_eccw flash0_eccr flash1_eccr flash configuration registers wdt_con1 the watchdog timer control register 1, which controls the disabling and the input frequency of the watchdog timer, is endinit-protected. in addition, its bits will only have an effect on the wdt when endinit is properly set to 1 again. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-142 v1.1, 2011-03 32-bit scu, v1.0 3.8.3.1 password access to wdt_con0 a correct password must be written to register wdt_con0 in order to unlock it for modifications. software must either know t he correct password in advance or compute it at runtime. the password required to unlo ck the register is formed by a combination of bits in registers wdt_con0 and wdt_ con1, plus a number of guard bits. table 3-18 summarizes the requirements for the password. scu_osccon scu_pllcon0 scu_pllcon1 scu_ccucon0 fdr scu_ccucon1 all clock control registers are protected scu_rstcntcon scu_rstcon scu_arstdis scu_swrstcon all reset control registers are protected scu_esrcfg0 scu_esrcfg1 all esr control registers are protected scu_emsr the emergency stop register scu_trapset scu_trapdis the trap set and disable register she_mprts she_mprte she memory protection p17_pdisc px_esr px_pdr port control registers dma_mexarr dma_mexaenr dma_ocdsr dma_suspmr dma control registers pcp_cs pcp control registers dmi_con dmi control registers table 3-17 TC1798 registers prot ected via the endinit feature (cont?d) register name description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-143 v1.1, 2011-03 32-bit scu, v1.0 the password is designed such that it is not possible to just read the contents of a register and use this as the password. the password is never identical to the contents of wdt_con0 or wdt_con1, it is always required to modify the read value (at least bits 1 and [7:4]) to get the correct password. this prevents a malfunction from accidentally reading a wdt register?s contents and writing it to wdt_con0 as an unlocking password. if the password matches the requirements, wdt_con0 will be unlocked as soon as the password access is completed. the unlocked condition will be indicated by wdt_con0.lck = 0. if an improper password value is written to wdt_con0 during the password access, a watchdog access error condition exists. bit wdt_sr.ae is set and the prewarning mode is entered. the user-definable password, wdt_con0.pw, provides additional options for adjusting the password requirements to the application?s needs. it can be used, for instance, to detect unexpected software loops, or to monitor the execution sequence of routines. 3.8.3.2 modify access to wdt_con0 if wdt_con0 is successfully unlocked, the following write access to wdt_con0 can modify it. however, this access must also meet certain requirements in order to be accepted and regarded as valid. table 3-19 lists the required bit patterns. if the access does not follow these rules, a watchdog access error condition is detected, bit wdt_sr.ae is set, and the prewarning mode is entered. table 3-18 password access bit pattern requirements bit position required value 0 current state of bit wdt_con0.endinit 1 fixed; must be written with 0 2 current state of bit wdt_con1.ir 3 current state of bit wdt_con1.dr [7:4] fixed; must be written to 1111 b [15:8] current value of user.definable password field wdt_con0.pw [31:16] current value of user-definable reload value, wdt_con0rel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-144 v1.1, 2011-03 32-bit scu, v1.0 after the modify access has completed, wdt_con0.lck is set again, automatically re- locking wdt_con0. before the register can be modified again, a valid password access must be executed again. 3.8.3.3 access to endinit-protected registers if some or all of the system?s endinit-pr otected registers must be changed during run time of an application, access can be re-opened. to do this, wdt_con0 must first be unlocked with a valid password access. in the subsequent valid modify access, endinit can be cleared. access to endini t-protected registers is now open again. however, when wdt_con0 is unlocked, th e wdt is automatically switched to time- out mode. thus, the access window is time-limited. time-out mode is only terminated after endinit has been set again, requiring another valid password and valid modify access to wdt_con0. if the wdt is not used in an application and is therefore disabled (wdt_sr.ds = 1), the above described case is the only occasion when wdt_con0 must be accessed again after the system is initialized. if there are no further changes to crit ical system registers needed, no further accesses to wdt_con0, wdt_con1, or wdt_sr are necessary. however, it is recommended that the wdt be used in an application for safety reasons. for debugging support the cerberus module can override the endinit control to ease the debug flow. if bit cbs_ostate.enidis is set the endinit protection is disabled independent of the current status configured by the wdt. if cbs_ostate.enidis is cleared the complete control is within the wdt. table 3-19 modify access bit pattern requirements bit position value 0 user-definable; desired value for bit wdt_con0.endinit. 1 fixed; must be written with 1. 2 fixed; must be written with 0. 3 fixed; must be written with 0. [7:4] fixed; must be written with 1111 b . [15:8] user-definable; desired value of user-definable password field, wdt_con0.pw. [31:16] user-definable; desired value of user-definable reload value, wdt_con0.rel. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-145 v1.1, 2011-03 32-bit scu, v1.0 3.8.4 timer operation the timer is automatically active after an application reset. the 16-bit counter implementing the timer functionality is either triggered with f fpi / 256 or f fpi / 16384. the two possible counting rates are controlled via bit wdt_con1.ir. determining wdt periods the wdt uses the fpi-bus clock f fpi . a clock divider in front of the wdt provides two output frequencies, f fpi / 256 and f fpi / 16384. the general formula to calculate a watchdog period is: (3.19) the parameter start value represents the fixed value fffc h for the calculation of the time-out period, and the user-programmable reload value wdt_con0.rel for the calculation of the normal period. 3.8.4.1 timer modes the watchdog timer can operate in on e of four different operating modes: ?time-out mode ? normal mode ? disable mode ? prewarning mode the following overview describes these modes and how the wdt changes from one mode to the other. time-out mode the time-out mode is entered after an application reset or when a valid password access to register wdt_con0 is performed (see section 3.8.3.1 ). the time-out mode is indicated by bit wdt_sr.to = 1. the timer is set to fffc h and starts counting upwards. time-out mode can only be exited properly by setting endinit = 1 with a correct access sequence. if an improper access to the wdt is performed, or if the timer overflows before endinit is set, a wdt_nmi is requested, and prewarning mode is entered. a proper exit from time-out mode can ei ther be to the normal or the disable mode, depending on the state of the disable request bit wdt_con1.dr. period 2 16 startvalue ? () 256 2 1ir ? () 6 ? ?? f fpi ---------------------------------------------------------------------------------------------------------------------------- = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-146 v1.1, 2011-03 32-bit scu, v1.0 normal mode in normal mode (dr = 0), the wdt operates in a standard watchdog fashion. the timer is set to wdt_con0.rel, and begins counting up. it has to be serviced before the counter overflows. servicing is performed through a proper access sequence to the control register wdt_con0. this enters the time-out mode. if the wdt is not serviced before the timer overflows, a system malfunction is assumed. normal mode is terminated, a wdt_nmi is r equested, and prewarning mode is entered. disable mode disable mode is provided for applications whic h truly do not require the wdt function. it can be requested from time-out mode when the disable request bit wdt_con1.dr is set. the disable mode is entered when was requested and bit wdt_con0.endinit is set. the timer is stopped in this mode. however, disabling the wdt only stops it from performing the standard watchdog function, eliminating the need for timely service of the wdt. it does not disable time-out and prewarning mode. if an access to register wdt_con0 is performed in disable mode, ti me-out mode is entered if the access was valid, and prewarning mode is entered if the access was invalid. thus, the endinit monitor function as well as (a part of) the system malfunction detection will still be active. prewarning mode prewarning mode is entered always when a watchdog error is detected. this can be due to an overflow of the timer in normal or time-out mode, or an invalid access to register wdt_con0. instead of immediately requesting a reset of the device, the wdt enables the system to enter a secure state by a prewarning before the reset occurs. in prewarning mode, after having generated the nmi request, the wdt counts up from fffc h , and then generates a watchdog reset request on the overflow. this reset request cannot be avoided in this mode; the wdt does not react anymore to accesses to its registers, nor will it change its state unless reset by an application reset. this is to prevent a malfunction from falsely terminating this mode, disabling the reset, and letting the device to continue to f unction improperly. register wdt_con0 can still be accessed by a valid password access. note: in prewarning mode, it is not required for the part to wait for the end of this mode and the reset. after having saved required state in the nmi routine, software can execute an application reset to shorten the time. note: the prewarning mode is only left by an application reset and not only on the reset request. therefore if bit field rstcon.wdt is set to 00 b the prewarning mode is not left. 3.8.4.2 wdt reset behavior wdt reset requests are generated for three cases: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-147 v1.1, 2011-03 32-bit scu, v1.0 ? invalid password access to register wdt_con0 ? not finishing a password access before a timer overflow occurs in the time-out mode ? not serving the wdt before a timer overflow occurs in the normal mode if a reset is generated on a wdt reset request and the kind of the reset can be configured via bit field rstcon.wdt. note: the wdt itself is reset by any application reset. before a reset is requested the prewarning mode is entered, for more details see section 3.8.4.1 . double wdt reset if the watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1798 is held in reset until a system reset occurs. this prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed. if the wdt is configured to request an application reset the second reset request will be permanently asserted resulting (without any change in the reset configuration) resulting in a permanent application reset. the information about the first wdt reset request is stored in an internal flag which is reset with the system reset. this flag is set when the prewarning mode is finished and t he reset request is generated. if a new reset is requested and the internal flag is already set a double reset event has occurred and a permanent request is generated. this internal flag is cleared by any system reset or when bit wdt_con1.clrirf is set and bit wdt_con0.endinit is set too. please note that a correct service of the wdt does not clear this internal flag. bit wdt_con1.clrirf can only be set when bit wdt_con0.endinit is cleared. note: it does not matter whether a reset wa s generated on a wdt reset request or if the reset configuration was changed between the two reset requests. note: if for any reason random code is executed bit field rstcon.wdt can be updated unintentional. this can result that a wdt error does not lead to an reset. to avoid this after the ssw is finished this bi t field should be checked and the endinit protection enabled. servicing the watchdog timer if the wdt is used in an application and is enabled (wdt_sr.ds = 0), it must be regularly serviced to prevent it from overflowing. service is performed in two steps. a valid password access followed by a valid modify access. the valid password access to wdt_ con0 automatically switches the wdt to time-out mode. thus, the modify access must be performed before the time-out expires or a system reset will result. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-148 v1.1, 2011-03 32-bit scu, v1.0 during the next modify access, the strict requirement is that wdt_con0.endinit as well as bit 1 and bits [7:4] are written wi th 1, while bits [3:2] are written with 0. note: endinit must be written with 1 to perform a proper service, even if it is already set to 1. changes to the reload value wdt_con0.rel, or the user-definable password wdt_con0.pw, are not required. ho wever, changing wdt_con0.pw is recommended so that software can monitor wdt service operations throughout the duration of an application program (see next section). when wdt service is properly executed, time-out mode is terminated, and the wdt switches back to its former mode of operation, and wdt service is complete. 3.8.4.3 wdt operation during power-saving modes if the cpu is in idle mode or sleep mode, it cannot service the wdt because no software is running. excluding the ca se where the system is runnin g normally, a strategy for managing the wdt is needed while the cpu is in idle or sleep mode. there are two ways to manage the wdt in these cases. first, the watchdog can be disabled before idling the cpu. the disadvanta ge of this is that the system will no longer be monitored during the idle period. a better approach to this problem relies u pon a wake-up feature of the wdt. whenever the cpu is put in idle or sleep mode and the wdt is not disabled, it causes the cpu to be awakened at regular intervals. when the wdt changes its count value (wdt_sr.tim) from 7fff h to 8000 h , the cpu is awakened and continues to execute the instruction following the instruction that was last executed before entering the idle or sleep mode. note: before switching into a non-running power-management mode, software should perform a watchdog service sequence. at the modify access, the watchdog reload value, wdt_con0.rel, should be programmed such that the wake-up occurs after a period which best meets application requirements. the maximum period between two cpu wake-ups is one-half of the maximum wdt period. 3.8.4.4 suspend mode support in an enabled and active debug session the watchdog functionality can lead to unintended resets. therefore to avoid these resets the ocds can control if the wdt is enabled or disabled (default after application reset) via bit cbs_ostate.wdtsus if it is not already stopped. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-149 v1.1, 2011-03 32-bit scu, v1.0 3.8.5 watchdog timer registers 3.8.5.1 watchdog timer control register 0 register wdt_con0 manages password access to the watchdog timer. it also stores the timer reload value, a user-definable password field, a lock bit, and the end-of- initialization (endinit) control bit. table 3-20 ocds behavior of wdt stcon. stp wdt_ sr.ds cbs_ostate. oen cbs_ostate. sus cbs_mcdssg. sos wdt action 0 x x x x stopped 1 1 x x x stopped 1 0 0 x x running 1 0 1 0 x stopped 1 0 1 1 0 running 1 0 1 1 1 stopped wdt_con0 wdt control register 0 (f000 05f0 h ) reset value: fffc 0002 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rel rw 1514131211109876543210 pw hpw1 hpw0 lck end init rw w w rwh rwh field bits type description endinit 0rwh end-of-initialization control bit 0 b access to endinit-protected registers is permitted (default after application reset) 1 b access to endinit-protected registers is not permitted www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-150 v1.1, 2011-03 32-bit scu, v1.0 lck 1rwh lock bit to control access to wdt_con0 0 b register wdt_con0 is unlocked 1 b register wdt_con0 is locked (default after application reset) the actual value of lck is controlled by hardware. it is cleared after a va lid password access to wdt_con0, and automatically set again after a valid modify access to wdt_con0. during a write to wdt_con0, the value written to this bit is only used for the password-protection mechanism and is not stored. this bit must be cleared during a password access to wdt_con0, and set during a modify access to wdt_con0. that is, the inverted value read from lck always must be written to itself. hpw0 [3:2] w hardware password 0 this bit field must be written with the value of the bits wdt_con1.dr and wdt_con1.ir during a password access. this bit field must be written with 0s during a modify access to wdt_con0. when read, these bits always return 0. hpw1 [7:4] w hardware password 1 this bit field must be written with 1111 b during both password access and modify access to wdt_con0. when read, these bits always return 0. pw [15:8] rw user-definable password field for access to wdt_con0 this bit field must be written with its current contents during a password access. it can be changed during a modify access to wdt_con0. rel [31:16] rw reload value for the wdt if the watchdog timer is enabled and in normal timer mode, it will start counting from this value after a correct watchdog service. this bit field must be written with its current contents during a password access. it can be changed during a modify access to wdt_con0 (fffc h = default after application reset). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-151 v1.1, 2011-03 32-bit scu, v1.0 3.8.5.2 watchdog timer control register 1 wdt_con1 manages operation of the wdt. it includes the disable request and frequency selection bits. it is endinit-protected. wdt_con1 wdt control register 1 (f000 05f4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0drir0 clr irf rrwrwrrwh field bits type description clrirf 0rwh clear internal reset flag this bit is used to request a clear of the internal flag storing the information about the first wdt reset request. 0 b no action 1 b request to clear the internal flag this bit can only be modified if wdt_con0.endinit is cleared. the internal flag is cleared when endinit is set again. as long as endinit is cleared, the internal flag is unchanged and controls the current past error status of the wdt. when endinit is set again with a valid modify access, the internal flag is cleared together with this bit. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-152 v1.1, 2011-03 32-bit scu, v1.0 3.8.5.3 watchdog timer status register register wdt_sr shows the current state of the wdt. status include bits indicating reset prewarning, time-out, enable/disable status, input clock status, and access error status. ir 2rw input frequency request control bit 0 b request to set input frequency to f fpi /16384. 1 b request to set input frequency to f fpi /256. this bit can only be modified if wdt_con0.endinit is cleared. wdt_sr.is is updated by this bit only when endinit is set again. as long as endinit is cleared, wdt_sr.is controls the current input frequency of the watchdog timer. when endinit is set again, wdt_sr.is is updated with the state of ir. dr 3rw disable request control bit 0 b request to enable the wdt 1 b request to disable the wdt this bit can only be modified if wdt_con0.endinit is cleared. wdt_sr.ds is updated when endinit is set again. as long as endinit is cleared, bit wdt_sr.ds controls the current enable/disable status of the wdt. when endinit is set again with a valid modify access, wdt_sr.ds is updated with the state of dr. 0 1, [31:4] r reserved read as 0; should be written with 0. wdt_sr wdt status register (f000 05f8 h ) reset value: fffc 0010 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 tim rh 1514131211109876543210 0prtodsisoeae r rhrhrhrhrhrh field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-153 v1.1, 2011-03 32-bit scu, v1.0 field bits type description ae 0rh watchdog access error status flag 0 b no watchdog access error 1 b a watchdog access error has occurred this bit is set when an illegal password access or modify access to register wdt_con0 was attempted. this bit is only cleared when wdt_con0.endinit is set during a valid modify access however, it is not possible to clear this bit if the wdt is in prewarning mode. oe 1rh watchdog overflow error status flag 0 b no watchdog overflow error 1 b a watchdog overflow error has occurred this bit is set when the wdt overflows from ffff h to 0000 h . this bit is only cleared when wdt_con0.endinit is set to 1 during a valid modify access. however, it is not possible to clear this bit if the wdt is in prewarning mode. is 2rh watchdog input clock status flag 0 b the timer operation clock is f fpi /16384 (default after application reset) 1 b the timer operation clock is f fpi /256 this bit is updated with the state of bit wdt_con1.ir after wdt_con0.endinit is written with 1 during a valid modify access to register wdt_con0. ds 3rh watchdog enable/disable status flag 0 b wdt is enabled (default after application reset) 1 b wdt is disabled this bit is updated with the state of bit wdt_con1.dr after wdt_con0.endinit is set during a valid modify acce ss to register wdt_con0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-154 v1.1, 2011-03 32-bit scu, v1.0 to 4rh watchdog time-out mode flag 0 b the watchdog is not operating in time-out mode 1 b the watchdog is operating in time-out mode (default after application reset) this bit is set when time-out mode is entered. it is automatically cleared when time-out mode is left. pr 5rh watchdog prewarning mode flag 0 b the watchdog is not operating in prewarning mode 1 b the watchdog is operating in prewarning mode this bit is set when a watchdog error is detected. the wdt has issued a trap trigger and is in prewarning mode. a reset of the chip occurs after the prewarning period has expired if it is enabled in bit field rstcon.wdt. tim [31:16] rh timer value reflects the current content of the wdt. 0 [15:6] r reserved read as 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-155 v1.1, 2011-03 32-bit scu, v1.0 3.9 emergency stop output control the emergency stop feature of the TC1798 allows for a fast emergency reaction on an external event without the intervention of software. in an emergency case, the outputs can be selectively put immediately to a well-defined logic state (for more information see the port chapter). the emergency case is indicated by an emergency input signal with selectable polarity that has to be connected to input p9.10. figure 3-28 shows a diagram of the emergency stop input logic. this logic is controlled by the scu emergency stop register emsr. figure 3-28 emergency stop input control the emergency stop control logic for the ports can basically operate in two modes: ? synchronous mode (default after reset): emergency case is activated by hardware and released by software. ? asynchronous mode: emergency case is activated and released by hardware. in synchronous mode (selected by emsr.m ode = 0), the port signal is sampled for a inactive-to-active level transition, and an emergency stop flag emsr.emsf is set if the transition is detected. the setting of emsr.emsf activates the emergency stop signal. an emergency case can only be terminated by clearing emsr.emsf via software. the synchronous control logic is cl ocked by the system bus clock f fpi . this results in a small delay between the port signal and emergency stop signal generation. mca05624_mo d p9.10 1 0 1 0 1 emsf & synchronous control pol mode enon emsfm set clear set asynchronous control system control unit emergency stop www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-156 v1.1, 2011-03 32-bit scu, v1.0 in asynchronous mode (selected by emsr .mode = 1), the occurrence of an active level at the port input immediately activates the emergency stop signal. of course, a valid-to-invalid transition of the port input (e mergency case is released) also immediately deactivates the emergency stop signal. the emsr.pol bit determines the active level of the input signal. the emsr.mode bit selects synchronous or asynchronous mode for emergency stop signal generation. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-157 v1.1, 2011-03 32-bit scu, v1.0 3.9.1 emergency stop register the emergency stop register emsr contains control and status bits/flags of the emergency stop input logic. emsr emergency stop register (100 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0emsfm 0 ems f rw rrh 1514131211109876543210 0 en on mo de pol r rwrwrw field bits type description pol 0rw input polarity this bit determines the polarity of the input line. 0 b input is high active 1 b input is low active mode 1rw mode selection this bit determines the operating mode of the emergency stop signal. 0 b synchronous mode selected; emergency stop is derived from the state of flag emsf 1 b asynchronous mode selected; emergency stop is directly derived from the state of the input signal enon 2rw enable on this bit enables the setting of flag emsf by an inactive-to-active level transition of input signal. 0 b setting of emsf is disabled 1 b setting of emsf is enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-158 v1.1, 2011-03 32-bit scu, v1.0 emsf 16 rh emergency stop flag this bit indicates if an emergency stop condition has occurred. 0 b an emergency stop has not occurred 1 b an emergency stop has occurred and signal emergency stop becomes active (if mode = 0) emsfm [25:24] w emergency stop flag modification this bit field set or clear flag emsf via software. 00 b emsf remains unchanged 01 b emsf becomes set 10 b emsf becomes cleared 11 b emsf remains unchanged emsfm is always read as 00 b . 0 [15:3], [23:17], [31:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-159 v1.1, 2011-03 32-bit scu, v1.0 3.10 interrupt generation the interrupt structure is shown in figure 3-29 . the interrupt request or the corresponding interrupt set bit (in register intset) can trigger the interrupt generation at the selected interrupt node x. the service request pulse is generated independently from the interrupt flag in register intstat. the interrupt flag can be cleared by software by writing to the corresponding bit in register intclr. if more than one interrupt source is connected to the same interrupt node pointer (in register intnp), the requests are combined to one common line. figure 3-29 interrupt generation int _struct o r interrupt_event a n d intstat.x intnp.x o r other interrupt sources on the same intnp o r o r o r other interrupt sources intclr.x intset.x intdis.x example for interrupt source x www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-160 v1.1, 2011-03 32-bit scu, v1.0 3.10.1 interrupt control registers intstat interrupt status register (110 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 dtsi fl1i fl0i erui 3 erui 2 erui 1 erui 0 wdt i rh rh rh rh rh rh rh rh rh field bits type description wdti 0rh watchdog timer interrupt request flag this bit is set if the wdt prewarning mode is entered and bit is intdis.wdti = 0. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclr.wdti. this bit can be set by bit intset.wdti. erui0 1rh eru channel 0 interrupt request flag this bit is set if the eru channel 0 is active and bit is intdis.erui0 = 0. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclr.erui0. this bit can be set by bit intset.erui0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-161 v1.1, 2011-03 32-bit scu, v1.0 erui1 2rh eru channel 1 interrupt request flag this bit is set if the eru channel 1 is active and bit is intdis.erui1 = 0. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclr.erui1. this bit can be set by bit intset.erui1. erui2 3rh eru channel 2 interrupt request flag this bit is set if the eru channel 2 is active and bit is intdis.erui2 = 0. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclr.erui2. this bit can be set by bit intset.erui2. erui3 4rh eru channel 3 interrupt request flag this bit is set if the eru channel 3 is active and bit is intdis.erui3 = 0. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclr.erui3. this bit can be set by bit intset.erui3. fl0i 5rh flash 0 interrupt request flag this bit is set if the flash interrupt trigger is active and bit is intdis.fl0i = 0. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclr.fl0i. this bit can be set by bit intset.fl0i. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-162 v1.1, 2011-03 32-bit scu, v1.0 fl1i 6rh flash 1 interrupt request flag this bit is set if the flash interrupt trigger is active and bit is intdis.fl1i = 0. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclr.fl1i. this bit can be set by bit intset.fl1i. dtsi 7rh dts interrupt request flag this bit is set if the dts busy indication changes from 1 b to 0 b and bit is intdis.dtsi = 0. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclr.dtsi. this bit can be set by bit intset.dtsi. 0 [15:8] rh reserved read as 0. this bit can be cleared by bit intclr.[x]. this bit can be set by bit intset.[x]. note: x = 6, [13:8], 15. 0 [31:16] r reserved read as 0; should be written with 0. intset interrupt set register (114 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 dtsi fl1i fl0i erui 3 erui 2 erui 1 erui 0 wdt i w wwwwwwww field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-163 v1.1, 2011-03 32-bit scu, v1.0 field bits type description wdti 0w set interrupt request flag wdti setting this bit set bit intstat.wdti. clearing this bit has no effect. reading this bit re turns always zero. erui0 1w set interrupt request flag erui0 setting this bit set bit intstat.erui0. clearing this bit has no effect. reading this bit re turns always zero. erui1 2w set interrupt request flag erui1 setting this bit set bit intstat.erui1. clearing this bit has no effect. reading this bit re turns always zero. erui2 3w set interrupt request flag erui2 setting this bit set bit intstat.erui2. clearing this bit has no effect. reading this bit re turns always zero. erui3 4w set interrupt request flag erui3 setting this bit set bit intstat.erui3. clearing this bit has no effect. reading this bit re turns always zero. fl0i 5w set interrupt request flag fl0i setting this bit set bit intstat.fl0i. clearing this bit has no effect. reading this bit re turns always zero. fl1i 6w set interrupt request flag fl1i setting this bit set bit intstat.fl1i. clearing this bit has no effect. reading this bit re turns always zero. dtsi 7w set interrupt request flag dtsi setting this bit set bit intstat.dtsi. clearing this bit has no effect. reading this bit re turns always zero. 0 [15:8] w reserved read as 0; have to be written with 0. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-164 v1.1, 2011-03 32-bit scu, v1.0 intclr interrupt clear register (118 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 dtsi fl1i fl0i erui 3 erui 2 erui 1 erui 0 wdt i w wwwwwwww field bits type description wdti 0w clear interrupt request flag wdti setting this bit clears bit intstat.wdti. clearing this bit has no effect. reading this bit re turns always zero. erui0 1w clear interrupt request flag erui0 setting this bit clears bit intstat.erui0. clearing this bit has no effect. reading this bit re turns always zero. erui1 2w clear interrupt request flag erui1 setting this bit clears bit intstat.erui1. clearing this bit has no effect. reading this bit re turns always zero. erui2 3w clear interrupt request flag erui2 setting this bit clears bit intstat.erui2. clearing this bit has no effect. reading this bit re turns always zero. erui3 4w clear interrupt request flag erui3 setting this bit clears bit intstat.erui3. clearing this bit has no effect. reading this bit re turns always zero. fl0i 5w clear interrupt request flag fl0i setting this bit clears bit intstat.fl0i. clearing this bit has no effect. reading this bit re turns always zero. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-165 v1.1, 2011-03 32-bit scu, v1.0 fl1i 6w clear interrupt request flag fl1i setting this bit clears bit intstat.fl1i. clearing this bit has no effect. reading this bit re turns always zero. dtsi 7w clear interrupt request flag dtsi setting this bit clears bit intstat.dtsi. clearing this bit has no effect. reading this bit re turns always zero. 0 [15:8] w reserved read as 0; have to be written with 1. 0 [31:16] r reserved read as 0; should be written with 0. intdis interrupt disable register (11c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 dtsi fl1i fl0i erui 3 eru ti2 erui 1 erui 0 wdt i rw rw rw rw rw rw rw rw rw field bits type description wdti 0rw disable interrupt request wdt 0 b an interrupt request can be generated for this source 1 b no interrupt request can be generated for this source erui0 1rw disable interrupt request eru0 0 b an interrupt request can be generated for this source 1 b no interrupt request can be generated for this source field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-166 v1.1, 2011-03 32-bit scu, v1.0 erui1 2rw disable interrupt request eru1 0 b an interrupt request can be generated for this source 1 b no interrupt request can be generated for this source erui2 3rw disable interrupt request eru2 0 b an interrupt request can be generated for this source 1 b no interrupt request can be generated for this source erui3 4rw disable interrupt request eru3 0 b an interrupt request can be generated for this source 1 b no interrupt request can be generated for this source fl0i 5rw disable interrupt request flash 0 0 b an interrupt request can be generated for this source 1 b no interrupt request can be generated for this source fl1i 6rw disable interrupt request flash 1 0 b an interrupt request can be generated for this source 1 b no interrupt request can be generated for this source dtsi 7rw disable interrupt request dts 0 b an interrupt request can be generated for this source 1 b no interrupt request can be generated for this source 0 [15:8] rw reserved have to be written with 1. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-167 v1.1, 2011-03 32-bit scu, v1.0 intnp interrupt node poin ter register (120 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 rw 1514131211109876543210 dts fl1 fl0 eru3 eru2 eru1 eru0 wdt rw rw rw rw rw rw rw rw field bits type description wdt [1:0] rw interrupt node pointe r for interrupt wdt this bit field defines the interrupt node, that is requested due to the set condition for bit intstat.wdti (if enabled by bit intdis.wdti). 00 b interrupt node 0 is selected 01 b interrupt node 1 is selected 10 b interrupt node 2 is selected 11 b interrupt node 3 is selected eru0 [3:2] rw interrupt node pointer for interrupt eru0 this bit field defines the interrupt node, that is requested due to the set condition for bit intstat.erui0 (if enabled by bit intdis.erui0). 00 b interrupt node 0 is selected 01 b interrupt node 1 is selected 10 b interrupt node 2 is selected 11 b interrupt node 3 is selected eru1 [5:4] rw interrupt node pointer for interrupt eru1 this bit field defines the interrupt node, that is requested due to the set condition for bit intstat.erui1 (if enabled by bit intdis.erui1). 00 b interrupt node 0 is selected 01 b interrupt node 1 is selected 10 b interrupt node 2 is selected 11 b interrupt node 3 is selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-168 v1.1, 2011-03 32-bit scu, v1.0 eru2 [7:6] rw interrupt node pointer for interrupt eru2 this bit field defines the interrupt node, that is requested due to the set condition for bit intstat.erui2 (if enabled by bit intdis.erui2). 00 b interrupt node 0 is selected 01 b interrupt node 1 is selected 10 b interrupt node 2 is selected 11 b interrupt node 3 is selected eru3 [9:8] rw interrupt node pointer for interrupt eru3 this bit field defines the interrupt node, that is requested due to the set condition for bit intstat.erui3 (if enabled by bit intdis.erui3). 00 b interrupt node 0 is selected 01 b interrupt node 1 is selected 10 b interrupt node 2 is selected 11 b interrupt node 3 is selected fl0 [11:10] rw interrupt node pointe r for interrupt fl0 this bit field defines the interrupt node, that is requested due to the set condition for bit intstat.fl0i (if enabled by bit intdis.fl0i). 00 b interrupt node 0 is selected 01 b interrupt node 1 is selected 10 b interrupt node 2 is selected 11 b interrupt node 3 is selected fl1 [13:12] rw interrupt node pointe r for interrupt fl1 this bit field defines the interrupt node, that is requested due to the set condition for bit intstat.fl1i (if enabled by bit intdis.fl1i). 00 b interrupt node 0 is selected 01 b interrupt node 1 is selected 10 b interrupt node 2 is selected 11 b interrupt node 3 is selected dts [15:14] rw interrupt node pointe r for interrupt dts this bit field defines the interrupt node, that is requested due to the set condition for bit intstat.dtsi (if enabled by bit intdis.dtsi). 00 b interrupt node 0 is selected 01 b interrupt node 1 is selected 10 b interrupt node 2 is selected 11 b interrupt node 3 is selected field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-169 v1.1, 2011-03 32-bit scu, v1.0 0 [31:16] rw reserved should be written with 0. src0 service request control 0 register (1fc h ) reset value: 0000 0000 h src1 service request control 1 register (1f8 h ) reset value: 0000 0000 h src2 service request control 2 register (1f4 h ) reset value: 0000 0000 h src3 service request control 3 register (1f0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number 00 h service request is never serviced 01 h service request is on lowest priority ... ff h service request is on highest priority tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp request is initiated sre 12 rw service request enable 0 b service request is disabled 1 b service request is enabled srr 13 rh service request flag 0 b no service request is pending 1 b a service request is pending field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-170 v1.1, 2011-03 32-bit scu, v1.0 clrr 14 w request clear bit clrr is required to clear srr. 0 b no action 1 b clear srr; bit value is not stored; read always returns 0; no action if setr is set also. setr 15 w request set bit setr is required to set srr. 0 b no action 1 b set srr; bit value is not stored; read always returns 0; no action if clrr is set also. 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-171 v1.1, 2011-03 32-bit scu, v1.0 3.11 nmi trap generation the nmi trap structure is shown in figure 3-30 . the trap request trigger or the corresponding trap set bit (in register trapset) can trigger the nmi trap generation. the trap flag can be cleared by software by writing to the corresponding bit in register trapclr. a nmi request is only generated if the trap source was not disabled. otherwise only the trap status flag is set but no nmi request is generated. figure 3-30 nmi trap generation handling nmi traps as an nmi trap is generated while the trap s ource is enable and the trap status flag is set it is recommended to clear the trap status flag before the trap source is enabled. the trap status flag can be set before the trap source is enabled and simply enabling the trap source can result in unintended nmi traps. at the end of a nmi trap handing routine the trap status flag should be cleared. trap _struct o r trap_event a n d trapdis.x trapstat.x other trap sources o r to cpu trapclr.x trapset.x example for trap source x www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-172 v1.1, 2011-03 32-bit scu, v1.0 3.11.1 trap control registers trapstat trap status register (124 h ) reset value: 0000 0100 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 era yvc olc kt sys vco lck t osc spw dtt osc hwd tt osc lwd tt ecc t wdt t 0 esr 1t esr 0t rh rh rh rh rh rh rh rh rh rh rh field bits type description esr0t 0rh esr0 trap request flag this bit is set if an esr0 event is triggered and bit is trapdis.esr0t is cleared. 0 b no trap was requested since this bit was cleared the last time 1 b a trap was requested since this bit was cleared the last time this bit can be cleared by setting bit trapclr.esr0t. this bit can be set by setting bit trapset.esr0t. esr1t 1rh esr1 trap request flag this bit is set if an esr1 event is triggered and bit is trapdis.esr1t is cleared. 0 b no trap was requested since this bit was cleared the last time 1 b a trap was requested since this bit was cleared the last time this bit can be cleared by setting bit trapclr.esr1t. this bit can be set by setting bit trapset.esr1t. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-173 v1.1, 2011-03 32-bit scu, v1.0 wdtt 3rh wdt trap request flag this bit is set if a wdt trap is indicated and bit is trapdis.wdtt is cleared. 0 b no trap was requested since this bit was cleared the last time 1 b a trap was requested since this bit was cleared the last time this bit can be cleared by setting bit trapclr.wdtt. this bit can be set by setting bit trapset.wdtt. ecct 4rh ecc error trap request flag this bit is set if a memory ecc error is indicated and bit is trapdis.ecct is cleared. 0 b no trap was requested since this bit was cleared the last time 1 b a trap was requested since this bit was cleared the last time this bit can be cleared by setting bit trapclr.ecct. this bit can be set by setting bit trapset.ecct. osclwdtt 5rh oscwdt low trap request flag this bit is set if a oscillator wdt of the pll detects a low event and bit is trapdis.osclwdtt cleared. 0 b no trap was requested since this bit was cleared the last time 1 b a trap was requested since this bit was cleared the last time this bit can be cleared by setting bit trapclr.osclwdtt. this bit can be set by setting bit trapset.osclwdtt. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-174 v1.1, 2011-03 32-bit scu, v1.0 oschwdtt 6rh oscwdt high trap request flag this bit is set if a oscillator wdt of the pll detects a high event and bit is trapdis.oschwdtt cleared. 0 b no trap was requested since this bit was cleared the last time 1 b a trap was requested since this bit was cleared the last time this bit can be cleared by setting bit trapclr.oschwdtt. this bit can be set by setting bit trapset.oschwdtt. oscspwdtt 7rh oscwdt spike trap request flag this bit is set if a oscillator wdt of the pll detects a spike event and bit is trapdis.oscspwdtt cleared. 0 b no trap was requested since this bit was cleared the last time 1 b a trap was requested since this bit was cleared the last time this bit can be cleared by setting bit trapclr.oscspwdtt. this bit can be set by setting bit trapset.oscspwdtt. sysvcolck t 8rh sysvcowdt trap request flag this bit is set if a pll vco loss-of-lock event is triggered and bit is trapdis.sysvcolckt cleared. 0 b no trap was requested since this bit was cleared the last time 1 b a trap was requested since this bit was cleared the last time this bit can be cleared by setting bit trapclr.sysvcolckt. this bit can be set by setting bit trapset.sysvcolckt. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-175 v1.1, 2011-03 32-bit scu, v1.0 erayvcolc kt 9rh erayvcowdt trap request flag this bit is set if a pll_eray vco loss-of oscillator lock event is triggered and bit is trapdis.erayxvcolckt cleared. 0 b no trap was requested since this bit was cleared the last time 1 b a trap was requested since this bit was cleared the last time this bit can be cleared by setting bit trapclr.erayvcolckt. this bit can be set by setting bit trapset.erayvcolckt. 0 2, [15:10] rh reserved read as 0. this bit can be cleared by bit trapclr.[x]. this bit can be set by bit trapset.[x]. note: x = 2, [15:10]. 0 [31:16] r reserved read as 0. trapset trap set register (128 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 era yvc olc kt sys vco lck t osc spw dtt osc hwd tt osc lwd tt ecc t wdt t 0 esr 1t esr 0t w wwwwwwwwww field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-176 v1.1, 2011-03 32-bit scu, v1.0 field bits type description esr0t 0w set trap request flag esr0t setting this bit set bit trapstat.esr0t. clearing this bit has no effect. reading this bit re turns always zero. esr1t 1w set trap request flag esr1t setting this bit set bit trapstat.esr1t. clearing this bit has no effect. reading this bit re turns always zero. wdtt 3w set trap request flag wdtt setting this bit set bit trapstat.wdtt. clearing this bit has no effect. reading this bit re turns always zero. ecct 4w set trap request flag ecct setting this bit set bit trapstat.ecct. clearing this bit has no effect. reading this bit re turns always zero. osclwdtt 5w set trap request flag osclwdtt setting this bit set bit trapstat.osclwdtt. clearing this bit has no effect. reading this bit re turns always zero. oschwdtt 6w set trap request flag oschwdtt setting this bit set bit trapstat.oschwdtt. clearing this bit has no effect. reading this bit re turns always zero. oscspwdtt 7w set trap request flag oscspwdtt setting this bit set bit trapstat.oscspwdtt. clearing this bit has no effect. reading this bit re turns always zero. sysvcolck t 8w set trap request flag sysvcolckt setting this bit set bit trapstat.sysvcolckt. clearing this bit has no effect. reading this bit re turns always zero. erayvcolc kt 9w set trap request flag erayvcolckt setting this bit set bit trapstat.erayvcolckt. clearing this bit has no effect. reading this bit re turns always zero. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-177 v1.1, 2011-03 32-bit scu, v1.0 0 2, [15:10] w reserved read as 0; have to be written with 0. 0 [31:16] r reserved read as 0; should be written with 0. trapclr trap clear register (12c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 era yvc olc kt sys vco lck t osc spw dtt osc hwd tt osc lwd tt ecc t wdt t 0 esr 1t esr 0t w wwwwwwwwww field bits type description esr0t 0w clear trap request flag esr0t setting this bit clear s bit trapstat.esr0t. clearing this bit has no effect. reading this bit re turns always zero. esr1t 1w clear trap request flag esr1t setting this bit clear s bit trapstat.esr1t. clearing this bit has no effect. reading this bit re turns always zero. wdtt 3w clear trap request flag wdtt setting this bit clears bit trapstat.wdtt. clearing this bit has no effect. reading this bit re turns always zero. ecct 4w clear trap request flag ecct setting this bit clears bit trapstat.ecct. clearing this bit has no effect. reading this bit re turns always zero. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-178 v1.1, 2011-03 32-bit scu, v1.0 osclwdtt 5w clear trap request flag osclwdtt setting this bit clears bit trapstat.osclwdtt. clearing this bit has no effect. reading this bit re turns always zero. oschwdtt 6w clear trap request flag oschwdtt setting this bit clears bit trapstat.oschwdtt. clearing this bit has no effect. reading this bit re turns always zero. oscspwdtt 7w clear trap request flag oscspwdtt setting this bit clears bit trapstat.oscspwdtt. clearing this bit has no effect. reading this bit re turns always zero. sysvcolck t 8w clear trap request flag sysvcolckt setting this bit clears bit trapstat.sysvcolckt. clearing this bit has no effect. reading this bit re turns always zero. erayvcolc kt 9w clear trap request flag erayvcolckt setting this bit clears bit trapstat.erayvcolckt. clearing this bit has no effect. reading this bit re turns always zero. 0 2, [15:10] w reserved read as 0; should be written with 0. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-179 v1.1, 2011-03 32-bit scu, v1.0 trapdis trap disable register (130 h ) reset value: 0000 ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 era yvc olc kt sys vco lck t osc spw dtt osc hwd tt osc lwd tt ecc t wdt t 0 esr 1t esr 0t rw rw rw rw rw rw rw rw rw rw rw field bits type description esr0t 0rw disable trap request esr0t 0 b a trap request can be generated for this source 1 b no trap request can be generated for this source esr1t 1rw disable trap request esr1t 0 b a trap request can be generated for this source 1 b no trap request can be generated for this source wdtt 3rw disable trap request wdtt 0 b a trap request can be generated for this source 1 b no trap request can be generated for this source ecct 4rw disable trap request ecct 0 b a trap request can be generated for this source 1 b no trap request can be generated for this source osclwdtt 5rw disable trap request osclwdtt 0 b a trap request can be generated for this source 1 b no trap request can be generated for this source www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-180 v1.1, 2011-03 32-bit scu, v1.0 oschwdtt 6rw disable trap request oschwdtt 0 b a trap request can be generated for this source 1 b no trap request can be generated for this source oscspwdtt 7rw disable trap request oscspwdtt 0 b a trap request can be generated for this source 1 b no trap request can be generated for this source sysvcolck t 8rw disable trap request sysvcolckt 0 b a trap request can be generated for this source 1 b no trap request can be generated for this source erayvcolc kt 9rw disable trap request erayvcolckt 0 b a trap request can be generated for this source 1 b no trap request can be generated for this source 0 2, [15:10] rw reserved have to be written with 1. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-181 v1.1, 2011-03 32-bit scu, v1.0 3.12 miscellaneous system control register this section collects different register that serve various system aspects. 3.12.1 gpta input in1 control in the TC1798, the input line in1 of the gpta module can be used to measure the baud rate of an asc0 or asc1 receiver input signal with gpta. this feature is controlled by syscon.gptais. figure 3-31 gpta0/gpta1/ltca2 input in1 control 3.12.2 system control register this register controls various functionality used by the scu but that are located outside of the module. additionally some functions for other modules are included. table 3-21 gpta0/gpta1/ltca2 input line in1 connections syscon.gptais gpta0/gpta1/lt ca2 input in1 connected to 00 b p2.9 / in1 (default after application reset) 01 b p5.0 / rxd0a 10 b p6.8 / rxd0b 11 b p6.10 / rxd1b mca05622_m m u x p2.9 / in1 p5.0 / rxd0a p6.8 / rxd0b p6.10 / rxd1b gpta0/ gpta1/ ltca2 in1 syscon.gptais www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-182 v1.1, 2011-03 32-bit scu, v1.0 syscon system control register (040 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 set ext ben set lu dis gptais cct rig1 cct rig0 rw w w rw rw rw field bits type description cctrigx (x = 0-1) xrw capture compare trigger x this bit is used to tri gger the synchronous start feature of the capcoms in the system. gptais [3:2] rw gpta input select this bit field selects the input that is used for in1 of the gpta module. for more information see either section 3.12.1 or the gpta chapter. 00 b in0 is selected 01 b in1 is selected 10 b in2 is selected 11 b in3 is selected setludis 4w set latch update disable setting this bit sets bit ststat.ludis. clearing this bit has no effect. this bit reads always as zero. setextben 5w set external boot enable setting this bit sets bit ststat.extben. clearing this bit has no effect. this bit reads always as zero. 0 [15:6] rw reserved should be written with 0. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-183 v1.1, 2011-03 32-bit scu, v1.0 3.12.3 identification registers chipid chip identificati on register (140 h ) reset value: xxxx xxxx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cub m 0 sp fsize ucode eea rw rw rw rw rw rh 1514131211109876543210 chid chrev rw r field bits type description chrev [7:0] r chip revision number this bit field indicates the revision number of the TC1798 device. the value of this bit field is defined in the TC1798 data sheet. chid [15:8] rw chip identification number this bit field defines the product by a unique number. 98 h = 1798 eea 16 rh emulation extension available indicates if the emulation extension is available or not. 0 b eec is not available 1 b eec is available ucode [23:17] rw code version this bit field displays the version x.y of the flash code. fsize [27:24] rw program flash size this bit field indicates available program flash size for this device. detailed information is shown in the data sheet. sp [29:28] rw speed this bit field indicates the maximum allowed speed for the cpu of this device. detailed information is shown in the data sheet. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-184 v1.1, 2011-03 32-bit scu, v1.0 cubm 31 rw copper bond material this bit indicates if copper was used for the bond wires. 0 b no copper was used 1 b copper was used 0 30 rw reserved have not to be written at all. id identification register (008 h ) reset value: 0052 c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 modnumber r 1514131211109876543210 modtype modrev rr field bits type description modrev [7:0] r module revision number this bit field indicates the revision number of the TC1798 module (01 h = first revision). modtype [15:8] r module type this bit field is c0 h . it defines a 32-bit module modnumb er [31:16] r module number this bit field defines the module identification number. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-185 v1.1, 2011-03 32-bit scu, v1.0 the redesign tracing register rtid prov ides a means of si gnalling mino r redesigns that are not reflected in the chipid.chrev bit field. manid manufacturer identifi cation register (144 h ) reset value: 0000 1820 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 manuf dept rr field bits type description dept [4:0] r department identi fication number =00 h : indicates the automotive & industrial microcontroller department within infineon technologies. manuf [15:5] r manufacturer iden tification number this is a jedec normalized manufacturer code. manuf = c1 h stands for infineon technologies. 0 [31:16] r reserved read as 0. rtid redesign tracing id entification register (148 h ) reset value: 0000 xxxx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 rt 15 rt 14 rt 13 rt 12 rt 11 rt 10 rt 9 rt 8 rt 7 rt 6 rt 5 rt 4 rt 3 rt 2 rt 1 rt 0 r r r r r r r r r r r r r r r r www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-186 v1.1, 2011-03 32-bit scu, v1.0 note: the rtid reset value for a major design step (without modifications) is 0000 h . field bits type description rtx (x = 0-15) xr redesign trace bit x 0 b no change indicated 1 b a change has been made (without changing bit field chipid.chrev). rtx can be used, e.g., for minor redesign stepping identification purposes. 0 [31:16] r reserved read as 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-187 v1.1, 2011-03 32-bit scu, v1.0 3.12.4 memory test register 3.12.4.1 register memtest 3.12.5 scu kernel registers this section describes the kernel registers of the 32-bit scu module. most of 32-bit scu kernel register names described in this section will be referenced in other parts of the TC1798 users manual by the module name prefix ?scu_?. memtest memory test register (160 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mca ndr a 0 rw rw 1514131211109876543210 0 rw field bits type description mcandra 31 rw mcan direct ram access 0 b direct ram access for the mcan is not possible 1 b direct ram access for the mcan is possible 0 [30:0] r reserved has to be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-188 v1.1, 2011-03 32-bit scu, v1.0 scu kernel register overview table 3-22 register overview of scu short name long name offset addr. 1) access mode reset description see read write ? reserved 000 h - 00c h be be ? ? osccon osc control register 010 h u, sv sv, e system reset page 3-31 pllstat pll status register 014 h u, sv be system reset page 3-33 pllcon0 pll configuration 0 register 018 h u, sv sv, e system reset page 3-35 pllcon1 pll configuration 1 register 01c h u, sv sv, e system reset page 3-37 ? reserved 020 h be be ? ? plleray stat pll_eray status register 024 h u, sv be system reset page 3-38 plleray con0 pll_eray configuration 0 register 028 h u, sv sv, e system reset page 3-40 plleray con1 pll_eray configuration 1 register 02c h u, sv sv, e system reset page 3-42 ccucon0 ccu control register 0 030 h u, sv sv, e system reset page 3-42 ccucon1 ccu control register 1 034 h u, sv sv, e system reset page 3-45 fdr fractional divider register 038 h u, sv sv, e system reset page 3-51 extcon external clock control register 03c h u, sv u, sv system reset page 3-49 syscon system control register 040 h u, sv u, sv system reset page 3-182 ccucon2 ccu control register 2 044 h u, sv sv, e system reset page 3-47 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-189 v1.1, 2011-03 32-bit scu, v1.0 ? reserved 048 h - 04c h be be ? ? rststat reset status register 050 h u, sv be power-on reset page 3-75 rstcntc on reset counter control register 054 h u, sv sv, e power-on reset page 3-78 rstcon reset con register 058 h u, sv sv, e power-on reset page 3-78 arstdis application reset disable register 05c h u, sv sv, e power-on reset page 3-80 swrstc on software reset configuration register 060 h u, sv sv, e power-on reset page 3-81 ? reserved 064 h - 068 h be be ? ? esrcfg0 esr0 configuration register 070 h u, sv sv, e system reset page 3-84 esrcfg1 esr1 configuration register 074 h u, sv sv, e system reset page 3-84 ? reserved 078 h - 07c h be be ? ? eicr0 external input channel register 0 080 h u, sv u, sv application reset page 3-105 eicr1 external input channel register 1 084 h u, sv u, sv application reset page 3-108 eifr external input flag register 088 h u, sv u, sv application reset page 3-112 fmr flag modification register 08c h u, sv u, sv application reset page 3-112 pdrr pattern detection result register 090 h u, sv u, sv application reset page 3-113 table 3-22 register overview of scu (cont?d) short name long name offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-190 v1.1, 2011-03 32-bit scu, v1.0 igcr0 interrupt gating register 0 094 h u, sv u, sv application reset page 3-114 igcr1 interrupt gating register 1 098 h u, sv u, sv application reset page 3-117 ? reserved 09c h be be ? ? iocr input/output control register 0a0 h u, sv u, sv system reset page 3-85 out output register 0a4 h u, sv u, sv system reset page 3-88 omr output modification register 0a8 h u, sv u, sv system reset page 3-89 in input register 0ac h u, sv be system reset page 3-90 pmcsr power management control and status register 0b0 h u, sv u, sv application reset page 3-123 ?reserved0b4 h - 0bc h be be ? ? ststat start-up status register 0c0 h u, sv be power-on reset page 3-126 stcon start-up configuration register 0c4 h u, sv st power-on reset page 3-128 ?reserved0c8 h - 0cc h be be ? ? ecccon ecc control register 0d0 h u, sv sv, e application reset page 3-130 eccstat ecc status register 0d4 h u, sv be application reset page 3-132 eccclr ecc clear register 0d8 h u, sv u, sv application reset page 3-134 table 3-22 register overview of scu (cont?d) short name long name offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-191 v1.1, 2011-03 32-bit scu, v1.0 dtsstat die temperature sensor status register 0e0 h u, sv be application reset page 3-138 dtscon die temperature sensor control register 0e4 h u, sv u, sv application reset page 3-137 ?reserved0e8 h - 0ec h be be ? ? wdt_ con0 wdt control register 0 0f0 h u, sv u, sv application reset page 3-149 wdt_ con1 wdt control register 1 0f4 h u, sv sv, e application reset page 3-151 wdt_ sr wdt status register 0f8 h u, sv be application reset page 3-152 ?reserved0fc h be be ? ? emsr emergency stop register 100 h u, sv sv, e application reset page 3-157 ? reserved 104 h - 10f h be be ? ? intstat interrupt status register 110 h u, sv be application reset page 3-160 intset interrupt set register 114 h u, sv u, sv application reset page 3-162 intclr interrupt clear register 118 h u, sv u, sv application reset page 3-164 intdis interrupt disable register 11c h u, sv u, sv application reset page 3-165 intnp interrupt node pointer register 120 h u, sv u, sv application reset page 3-167 trapsta t trap status register 124 h u, sv be system reset page 3-172 trapset trap set register 128 h u, sv sv, e system reset page 3-175 table 3-22 register overview of scu (cont?d) short name long name offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-192 v1.1, 2011-03 32-bit scu, v1.0 trapclr trap clear register 12c h u, sv u, sv system reset page 3-177 trapdis trap disable register 130 h u, sv sv, e application reset page 3-179 ? reserved 134 h - 13f h be be ? ? chipid chip identification register 140 h u, sv st system reset page 3-183 manid manufacture identification register 144 h u, sv be system reset page 3-185 rtid redesign trace identification register 148 h u, sv be system reset page 3-185 ? reserved 14c h - 15f h be be ? ? memtest memory test register 160 h u, sv sv, e system reset page 3-187 ? reserved 164 h - 1ef h be be ? ? src3 service request control register 3 1f0 h u, sv sv application reset page 3-169 src2 service request control register 2 1f4 h u, sv sv application reset page 3-169 src1 service request control register 1 1f8 h u, sv sv application reset page 3-169 src0 service request control register 0 1fc h u, sv sv application reset page 3-169 1) the absolute register address is calculated as follows: module base address + offset address (shown in this column) table 3-22 register overview of scu (cont?d) short name long name offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-193 v1.1, 2011-03 32-bit scu, v1.0 3.12.6 scu address area table 3-23 registers address space - scu kernel registers module base address end address note scu f000 0500 h f000 06ff h - www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system control unit (scu) users manual 3-194 v1.1, 2011-03 32-bit scu, v1.0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-1 v1.1, 2011-03 interrupt, v1.6 4 on-chip system buses and bus bridges the TC1798 has two independent on-chip buses: ? shared resource interconnect (sri) ? system peripheral bus (spb) figure 4-1 on chip buses in TC1798 processor subsystem the sri connects the tricore cpu to its local resources for instruction fetches and data accesses. the spb is accessible by the cpu via the sri to fpi bridge (sfi). 4.1 what is new major differences of the TC1798 on chip bus system architecture compared to audof/audos and other tc1.3.x based products: ? the TC1798 is based on two on chip busses (sri, spb). the local memory bus (lmb) was replaced by an shared resour ce interconnect (sri / sri crossbar, chapter 4.2 ) ? the lbcu functionality is now covered by the sri crossbar (xbar_sri) pmi ebu tricore cpu bridge (sfi) dmi ldram dcache pmu1 2 mb pflash 32 kb pspr 16 kb icache 128 kb dspr 16 kb dcache fpu dma 16 channels (memcheck ) cross bar interconnect (sri) 2 mb pflash 192 kb dflash 16 kb brom keyflash pmu0 128 kb sram xbar s m/s m/s m m/s m/s m/s s s s lmu abbreviations: icache: instruction cache dcache data cache pspr: program scratch-pad ram dspr: data scratch-padl data ram brom: boot rom s m pflash: program flash dflash: data flash xbar: sri cross bar (xbar_sri) : on chip bus slave interface : on chip bus master interface www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-2 v1.1, 2011-03 interrupt, v1.6 ? the lmb to fpi bridge (lfi) was replaced by the sri to fpi bridge (sfi, chapter 4.3 ) ? the sfi is fully transparent regarding address and master tag id ? the on chip bus architecture was adapted to the tc1.6 (cps registers are now accessed via pmi sri slave, additional lmu peripheral connected to sri) ? the table on chip bus master tag assignments was adapted (sdma tag added, lfi tags removed, page 4-103 ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-3 v1.1, 2011-03 interrupt, v1.6 4.2 sri crossbar (xbar_sri) 4.2.1 introduction the shared resource interconnection (sri) is the new high speed system bus for tricore1.6 cpu. the central module of the interconnect is the xbar_sri which connects all components in one sri system. the xbar_sri handles, arbitrates and forwards the communication between all connected sri-master and sri-slave peripherals. the xbar_sri supports parallel transaction between different sri-master and sri- slave peripherals. it supports also pipelined requests from the sri-master interfaces and pipelined address phases to the connected sri-slave interfaces. figure 4-2 xbar_sri point to point connection scheme the xbar_sri provides sri slave interfaces (scix) to connect sri slave modules and sri master interfaces (mcix) to connect sri master models to the xbar_sri. the xbar_sri includes an default sri slave that provides access to the xbar_sri control registers and that takes over all sri transactions to address outside the connected sri sri slave sri slave sri slave mci0 mci2 sci0 mci1 sci 1 sci2 sci15 sri default slave sri master sri master sri master www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-4 v1.1, 2011-03 interrupt, v1.6 slave address ranges. the xbar_sri includes also one arbiter module per connected sri slave module and the infrastructure for the enabled read/write data paths. each connected sri slave module as well as the default slave have an related arbiter module within the xbar_sri. please note that only these sri-master <- > sri-slave connections are implemented that are required for the system functionality (example: connection between pmi master and pmi slave is not implemented, see also table 4-8 ). for performance optimization the xbar_sri incl udes arbitration schemes that allows to configure sri master priorities for each sri slave individually (arbiter functionality). for debug support on system level the xbar_sri includes debug support for sri-error and sri-transaction id errors (local sri slave module support in the related arbiter, global control in the default slave) . table 4-1 sri bus terms term description agent an sri agent is any master or slave device which is connected to the sri bus. master an sri master device is an sri agent which is able to initiate transactions on the sri. slave an sri slave device is an sri agent which is not able to initiate transactions on the sri. it is only able to handle operations that are dedicated to it by sri crossbar (xbar_sri). xbar_sri the sri crossbar (xbar_sr i) provides the interconnects between connected master and slaves. the xbar_sri includes arbitration mechanisms and debug capabilities. the xbar_sri has 16 master connection interfaces (mci0 - mci15) to connect sri master devices to it and 15 slave connection interfaces (sci0 - sci14) to connect sr i slave devices to it. mci each master is connected via one master connection interface (mci x, x = 0 ...15). the xbar_sri control registers include control and debug informations related to the master connection interfaces mci x (x = 0 ... 15). sci each slave is connected via one slave connection interface (sci x, x = 0 ...14). the xbar_sri control registers include control and debug informations related to the slave connection interfaces sci x (x = 0 ... 14). the xbar_sri default slave is connected to sci 15. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-5 v1.1, 2011-03 interrupt, v1.6 4.2.1.1 xbar_sri features xbar_sri feature overview: ? single/block data read transaction support (8/16/32/64 bit) ? single/block data write transactions support (8/16/32/64 bit) ? read modify write support ? supports pipelined requests from sri master peripherals ? supports pipelined address phases to sri slave peripherals ? single arbiter module for each connected slave device ? arbitration priority scheme can be configured for each slave device individually ? flexible arbitration schemes (priority, tw o round robin groups, starvation prevention) ? breakpoint signal generation based on sri transactions (ocds level 1) ? configurable mcds trace interface ? information integrity support for sri address phase and read data path through the sri interconnect. 4.2.2 sri transactions each sri transaction consists of: ? one request phase ? one or multiple data phases if not finished with error acknowledge due to the point to point nature master/slave connections of the xbar a master that is requesting for access to one sir slave peripher al is providing all tr ansaction information in parallel with the request. this means that there are no separate on chip bus request and on chip bus address phases. an sri request/address phase consists of: ? request signal ? lock signal (indicating a read modify write transaction) ? 32-bit address ? 4-bit sri op-code (kind of single data or burst transaction) ? read/write signal (read, write or read modify transaction) ? supervisor mode signal ? transaction id (consists of a unique 6-bi t master tag id and a 2 bit running number increased for each new transaction of this master) ? 8-bit address phase ecc (covering all address phase signals with the exception of request and grant) ? one or multiple data phases if not finished with error acknowledge after the request for a slave access was granted by the related xbar_sri arbiter module, the transaction can be either finished with error acknowledge or with the read/write data phases as defined during the request/address phase. each data phase ends with the transmission of data phase informations including: ? read or write transaction id (must be equal to the related transaction id otherwise the address phase is invalid) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-6 v1.1, 2011-03 interrupt, v1.6 ? 8-bit read/write data ecc (covering the 64-bit read/write data and the bits [23:3] of the related address. ? 64 bit read or write data. in case of an 8-bi t, 16-bit or 32-bit read/write transaction the unused bits are filled with don't care data. the read/write data ecc covers the 64 data bits as transferred (incl. the possible don't care data). 4.2.3 sri op-codes the sri op-code defines for a sri transaction the number of data phases, the addressing mode in case of a multi beat transaction and valid bytes in case of a single data transaction. table 4-2 operation code encoding sri_opc[3:0] identifier description 0000 sdtb single data transfer byte (8 bit) 0001 sdth single data transfer half-word (16 bit) 0010 sdtw single data transfer word (32 bit) 0011 sdtd single data transfer double-word (64 bit) 0100 - reserved 0101 - reserved 0110 - reserved 0111 - reserved 1000 btr2 block transfer request (2 transfers) wrap around address mode is used. 1001 btr4 block transfer request (4 transfers) wrap around mode is used. 1010 btrl2 1) 1) the sri implementation in the TC1798 does no t support bursts with linear addressing modes. block transfer request (2 transfers) linear address mode is used. 1011 btrl4 1) block transfer request (4 transfers) linear address mode is used. 1100 - reserved 1101 - reserved 1110 - reserved 1111 - reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-7 v1.1, 2011-03 interrupt, v1.6 4.2.4 sri error conditions the sri_err_n signal is used by the slave during a transaction to signal the corresponding master that an error has happened which results in an immediate termination of the current transaction. errors during transaction are tracked by the xbar_sri and are signalled to via an interrupt and directly to the smu. only the following error conditions are supported and recognized by sri slaves: ? access level is incorrect (user/supervisor) ? unmapped address access from an sri master 1) ? unsupported op-code ? reserved op-code an sri error can be generated by the application sw e.g. with an access to a reserved address (see chapter memory map): 4.2.5 sri transaction id error conditions transaction id is an identifier connected to all phases of a transaction in order to make the transaction unique in the sri system during the transactions live time. the transaction id is used by sri masters and slaves to identify problems in the sri system that results in data pa ckets received by a master or slave that do not match the corresponding arbitration/address phase. if the read/write transaction identifier doesn?t match with the previous send transaction identi fier in the address phase, this is identified as a transaction id error and tracked by the xbar_sri. in situations where at the data source side (master for write transactions, slave for read transactions) a data phase has to be invalidated (e.g. detection of an not correctable sram ecc error) and invalid transaction id is send in order to invalidate the data phase. an sri transaction id error condition can be generated by injecting an non correctable error into one of the srams (e.g. cpu instruction scratch pad sram) and than reading the corrupted data by a cpu. 1) the accesses to unmapped slaves is checked by a default slave. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-8 v1.1, 2011-03 interrupt, v1.6 4.2.6 operational overview this chapter describes the functionality of the xbar_sri module in order to enable the user to configure the xbar_sri control registers and to use the xbar_sri debug resources. figure 4-3 xbar_sri connections between sri master and sri slaves m u x request phase signals (req/gnt/addr etc.) sri master m1 xbar sri m u x sri slave s1 m u x sri slave s2 arbiter s1 arbiter s2 addr ess pha se sign als sri_master_slave_2 data phase (ctrl. signals & write data) data phase (ctrl. signals and read data) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-9 v1.1, 2011-03 interrupt, v1.6 figure 4-4 xbar_sri connectio ns between sri slave and sri master modules 4.2.6.1 functional blocks the xbar_sri represents the highest level of the hierarchical sri-bus system. since, it is closest to the tc1.6 core, peripherals critical to cpu performance can be attached to it. the xbar_sri module is partitioned into bl ocks for arbitration and data path control which are necessary for each xbar_sri master- or slave interface and one block that covers the default slave - and debug functionality. the xbar_sri module can handle and process several transaction of different master in parallel if the masters requests different slaves. xbar_sri master conn ection interface (mci) each sri master module in the system is mapped to one or more xbar_sri master connection interfaces (mci). each mci is related with in the xbar_sri module to a default arbitration priority and to register control bits and register control bit fields. so each sri master in the system is mapped to an xbar_sri in ternal default arbitration priority and to master related control register bits and bit fields via its mci number (see also see also table 4-4 and table 4-6 ). arbiter for s 1 m u x m u x data phase (ctrl. signals & write data) data phase (ctrl. signals and read data) sri master m1 sri slave s1 xbar sri from other sri slaves from other sri masters sri_master_slave_1 address phase signals request phase signals (req/gnt/addr etc.) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-10 v1.1, 2011-03 interrupt, v1.6 xbar_sri slave connection interface (sci) each sri slave module in the system is mapped to one xbar_sri slave connection interfaces (scix). each sci is related within the xbar_sri module to one arbiter module with its arbiter module control register and to register control bits and register control bit fields related to this scix. so each sri slave module in the system is mapped to an xbar_sri internal arbiter module and to slave related control register bits and bit fields via its sci number (see also see also table 4-7 ). xbar_sri arbiter each xbar_sri slave connection interface is mapped to exactly one dedicated instantiation of the slave arbiter module in the xbar_sri. this module includes all required functionality for the following tasks: ? arbitration: the module includes all required functionality for the arbitration. this includes sri address decoding, sri requ est arbitration, sri request starvation algorithm, sri address phase generation and control registers for the priority of the connected master connection interfaces and an fsm to detect the end of the current sri transaction. ? debugging: the module tracks t he sri transactions to th e dedicated slave connection interface for sri errors. the transaction information of the first transaction where the sri protocol error is captured in arbiter internal control registers. the module tracks the requ ests from all masters to detect starvation of masters in the arbitration rounds. ? error signalling: the first sri error or starvation error is signalled to the default slave module via two sideband signals. ? xbar_sri control bus interface: the module has a slave interface to the xbar_sri control bus. the slave arbiter decodes the address of each new control bus transaction and, if addressed, processes the read/write transaction to the module internal control registers. default slave the xbar_sri default slave module is a xbar_sri internal sri slave module with its own, dedicated arbiter module inside the xbar_sri. for accesses to the xbar_sri control registers only sri single data transacti ons of word size are supported. any other op-code that is sri protocol legal is not supported by the default slave module. such transactions are acknowledged with an error by the default slave to the sif_sri. the default slave module includes all requir ed functionality for the following tasks: ? as a sri default slave, it deals with all transactions that are directed to a nonexisting slave in the sri system as it is described in the sri protocol. the purpose of the sri default slave in that situation is to guarantee a defined behavior by terminating these sri transactions with an error. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-11 v1.1, 2011-03 interrupt, v1.6 ? the xbar_sri default slave module is the sri interface to all xbar_sri internal diagnostic- and control registers. ? the xbar_sri default slave module samples the mci_id_err_n and sci_id_err_n signals from all xbar_sri master and slave connection interface modules. if the default slave module detects mci_id_err_n and sci_id_err_n pulses it generates an interrupt to the system. the sampling of each mci_id_err_n and sci_id_err_n signal from an arbiter can be disabled via the default slave interrupt control register idinten. ? the xbar_sri default slave module includes the interrupt node control structure and the corresponding control register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-12 v1.1, 2011-03 interrupt, v1.6 4.2.7 functional overview 4.2.7.1 arbitration block the arbiter has access to all arbitration-/address phase signals from the master connector interfaces he is enabled for, therefore he sees requests from all master connector interfaces in parallel. in order to check if a master request is addressed to ?its? slave connector interface for the next transaction the arbiter checks if the address transmitted together with the request from the master matches with the allocat ed address area of this slave via address decoding. due to the fact that a master can access any slave for a transaction all arbiters of the xbar_sri are checking the requested address from a requesting master in parallel. due to the fact that multiple masters can request for one slave in parallel, each slave has to decode the addresses from all the master connector interfaces it is enabled for in parallel. figure 4-5 xbar_sri arbiter scheme address map checking the arbiter performs the address comparison for all pending requests from the connected sri master modules to its slave module in parallel. register stage 3 mux16:1 mci 0 mci 1 mci x address decoder address decoder address decoder round robin & mux 16:1 mux16:1 mux16:1 req prio 0 req prio 1 req prio 15 priority driven arbitration req prio 2 starvation prevention address phase signals to sci grant signals to mci's m u x 16:1 request phase signals from mci's map of mci requests to priorities / rr groups xbar-sri arbiter module register stage 1 (optional) register stage 3 register stage 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-13 v1.1, 2011-03 interrupt, v1.6 arbitration a transaction request from a master that matches the address area of a slave connection interface takes part in the next arbitration cycle. the arbitration is divided into two levels: ? priority driven arbitration ? arbitration within round robing groups (priority 2 and 8) after reset each enabled master connector interface has a unique priority for the arbiters by default see (also see also table 4-4 ). the priorities and the priority algorithm of the master connection interfaces can be programmed for each arbiter individually. the programming of the master priorities can be done by sri read/write transaction via the default slave module. the highest priority for an arbiter is 0 and the lowest is 15. according to the transaction rules described in the sri protocol specification the arbiter asserts the sri_gnt_x signal to grant the slave to this winning master. in parallel - or after granting the master, the arbiter sends the address phase for the next transaction to the slave by propagating all necessary informations via the slave connection interface to the slave. the arbiter sends the address phase in parallel with the grant or delayed depending on the address phase pipeline status of the corresponding sri slave. for debug purposes, the arbiter samples all necessary transaction informations and provides them to the xbar_sri default slave module if an sri error happened and the protocol error feature was enabled. arbitration algorithms the arbiter related to a slave connection interface (sci) can be connected to all master connection interfaces (mci), see also chapter 4.2.8.3 . the priority of each mci can be controlled via the arbiter priority registers (pri ox). the priority of a master is defined by 4 bit field in the priol / prioh register that is related to this master / its mci number. this can be configured individually for eac h arbiter so the same master can be handled with different priorities for accesses to differ ent slaves. after reset, each priority register has a default value, which means that each mci has a unique default priority. please note: it must be ensured that two enabled masters don?t have the same priority, with the exception of priority 2 and priority 8 (round robin group priorities). for changing the priorities during runtime (swi tching the priorities), all master connection interfaces that should be remapped have to be mapped to the round robin group priorities (2 / 8) before mapping them to their new priorities can be don e. this will prevent situations where two masters have the sa me priority but not a round robin one. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-14 v1.1, 2011-03 interrupt, v1.6 priority driven arbitration the general arbitration algorithm is priority dr iven where priority 0 is the highest priority and 15 the lowest one. if multiple masters are requesting for one slave, the master with the highest priority will win the next arbitrat ion round (see also ?s tarvation prevention?). round robin groups the arbiter arbitrates in general priority driv en, where priority 2 and priority 8 contain a second ?arbitration? layer. both priorities ca n be used as round robin priorities for a group of max. 8 mci?s each. if only one master is mapped to a round robin group priority, the master?s request will be treated as normal master request with the priority of the round robin group. if more than one master is mapped to the priority of a round robin group, the requests of the mapped masters will be handled by the round robin algorithm, the winning request of the round robin group arbitration has the priority of the round robin group within the priority driven arbitration. after the winner of a round robin group is gr anted, the round robin group starts with a new arbitration round which means the requ esting mci?s of the round robin group with the next highest mci id number will win the ne xt round robin arbitration round. if there is no requesting mci with a higher id number in the round robin group, the algorithm will start with the mci with the lowest mci id number that is mapped to the group, going to the next higher mci id number and so on. request latency if no other request is pendi ng, a request from an mci ha s a latency of 1 clock cycle, starting with the detection of the sri master request on the bus, ending with the sri grant to the requesting mci and the sri address phase to the addressed sci. usually address decoding, round robin arbi tration, priority driven arbitration and starvation prevention will be done in one clock cycle. table 4-3 xbar_sri request latency clock cycle nr.: task(s) 0 (default slave) sri_req_n is sampled at xbar_sri mci (only valid for access to the xbar_sri control registers) 1 address decoding, mapping of mci?s to priorities / round robin groups and starvation prevention. ro und robin arbitrations, priority driven arbitration, mux request phase signals to the address phase registers masking sri_req_n from mcix after granting the mcix 2 sri_gnt_n to the requesting mci, sri address phase to sci. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-15 v1.1, 2011-03 interrupt, v1.6 grant -> new request latency (request dead time) after an mci was granted, it takes 2 clock cycles before a new request from the same mci will participate in a new arbitration round even when the sri master has requested permanently. this request dead time is a result of the synchronous sri_req_n de- assertion and the xbar_sri request latency. default mci x priori ties after reset after reset each master has a default priority which is equal to the number of the master connection interface (mci x, x = 0 ... 15) it is connected to. mci0 is configured with the highest priority and mci15 with the lowest priority. table 4-4 shows the default priority of the mci with the related coding in the xbar_priolx (x = 3-6) registers. after reset, the priority scheme of the mcis can be re-configured via the xbar_priolx (x = 3-6) registers, for each sci (accesses to the slave connected to an sci) individually. table 4-4 default mci priority in the xbar_sri arbiters priority coding round robin group default mapping: comments 0 0000 - mci 0 1 0001 - mci 1 2 0010 yes, max 8 master mci 2 maximal 8 mci can be mapped to the priority 1 e.g. can have the prio ?0001?. 3 0011 - mci 3 4 0100 - mci 4 5 0101 - mci 5 6 0110 - mci 6 7 0111 - mci 7 8 1000 yes, max. 8 master mci 8 maximal 8 mci can be mapped to the priority 8 e.g. can have the prio ?1000?. 9 1001 - mci 9 10 1010 - mci 10 11 1011 - mci 11 12 1100 - mci 12 13 1101 - mci 13 14 1110 - mci 14 15 1111 - mci 15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-16 v1.1, 2011-03 interrupt, v1.6 starvation prevention starvation can occur when masters with high priority continuously request a dedicated slave, preventing other masters with lower priority from getting access to this slave. to prevent such a situation, a starvation counter has been implemented in each arbiter. this mechanism allows the promotion of weak masters. each time the starvation counter in a slave module has and underflow, all pending requests to this arbiter will be entered in th e arbiters request list. this even applies to all masters mapped to a round robin group. next time when the starvation counter has an underflow, the masters of this request list will be entered in the arbiters request promotion list if: ? the request was not granted during the last starvation period the masters in that request promotion list will be the next to be granted independent of their priorities. the masters in the request promotion list will be granted one after the other, starting with the master which has the lo west mci number in this list if there are more than one. the master promotion list has the highest priority within the arbiters main arbitration algorithm, therefore all masters in the promotion list will be granted before the arbiter switches back to its ?normal? arbitration. a master is removed from both lists when it is granted. if several masters are mapped to a round robin priority, all masters of that round robin arbitration round will be entered in the request list/request promotion list when not granted. the value controlling the counter period is programmable. after reset the starvation counter is disabled and has a value of zero. on a starvation counter underflow it is reloaded with the content of the arbiter control register arbcon.spc. an underflow occurs in the clock cycle when the counter tries to count down from zero. the number of arbitration cycles a master must wait for the slave varies. but it?s guaranteed to be no more than 2 arbcon.spc until the master is promoted to the request promotion list. each time there is an underflow it is checked if there are any masters in the request promotion list that were not granted since the last underflow. this can happen if there are to many/to long transactions to be promoted compared to arbcon.spc value. in this case an error is generated via the xcb_sc_err_n signal to the default slave if the feature was enabled (bit arbconx.scerren set). if currently a rmw transaction is processed the starvation counter is stopped before the next overflow. the starvation counter is released again after the address phase of the write part is generated or an error for the rmw transaction was received. if currently a read-modify-write (rmw) tr ansaction is processed by the slave the starvation protection counter is stopped until this rmw is finished. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-17 v1.1, 2011-03 interrupt, v1.6 4.2.7.2 default slave the default slave serves three features in the xbar_sri implementation: control and configuration registers interface the xbar_sri default slave module handles all read and write transactions to the debug- and control registers of the xbar_sri. for this purpose, the default slave module has its own address space which must be mapped into the system address space by an address decoder, provided by the customer. for a detailed description of the registers see chapter 4.2.9 . non existing addresses the xbar_sri internal default slave module has its own arbiter module. if an sri master sends a request with a non existing address 1) to the xbar_sri, the transaction will be directed to the default slave. the default slave finishes the transaction with error following the sri protocol rules, which activates the error tracking mechanism of the arbiter. as a result of the error, the default slave module signals this incorrect behavior to the system by generating an interrupt. a write from an sri master to a non existing address on the system peripheral bus (spb) will be handled by the bus control unit on the spb only. a read from an sri master to a non existing address on the spb will be handled by the by the bus control unit on the spb and also capt ured by the xbar_sri arbiter as it will see the transaction as read transaction finished with error acknowledge. error handling if an arbiter detects an sri protocol error during a transaction with a corresponding slave the involved arbiter samples all relevant information of the transaction in the arbiter internal diagnostic registers (erraddr x and errx) and signals this event via xcb_sri_err_n or xcb_sri_err_d_n sideband signal to the default slave module. note: the two error registers errx and er raddrx in each arbiter are updated with the content of the currently processed trans action in the data phase. the registers are only updated if they are not locked due to a pending protocol error and sri_ready_n was asserted in parallel with sri_err_n deasserted. the error capture registers in the arbiter can?t be changed until the interrupt was acknowledged to the slave arbiter module (set the arbcon.intack) via the default slave. 1) non existing address = all reserved address ranges described in the memory map chapter www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-18 v1.1, 2011-03 interrupt, v1.6 the stored informations can be read from the default slave module with sri single data read transactions, the acknowledge can be sent to the default slave via a write to a specific address. this can result in a loss of interrupt data information of the same source beyond the first until the write was processed but as all sri errors must be analyzed and fixed before the product will work, these kind of errors can be analyzed one after the other. in case that a master or a slave signals an id error to the xbar_sri the default slave marks the source of the id error by setting the according bit in register idintsat if this feature was enabled for that specific master and/or slave interface. as a result, the default slave gener ates an interrupt to the system. note: while a status bit for a error source is set in either the intsat or idintsat register a new error from this particular source doesn?t generate a new interrupt. 1. each participant in the sri-bus system ha s three interrupt sources; protocol errors, id errors and time-out due to starvation. all error from the sri-bus components are combined in the single srn of the xbar_sri. each arbiter has two 32 bit registers containing the error information. this registers are accessed as all other registers, via the default slave module. the default slave module has one service re quest node (srn) to start interrupts for detected sri errors. protocol errors, starvation errors as well as id errors are handled together by this node. 4.2.7.3 sri ecc error handling the sri protocol provides ecc protection for the: ? address phase of an sri transaction ? read data transmitted during read data phases if an sri slave detects an sri address phase ecc error it finishes the transaction with sri error acknowledge and does not further process it (see also chapter 4.2.7.4 ). it can happen that a data during a transaction shows an ecc error inside the data source peripheral (master during write, slave during read). example: a burst read transaction from a memory slave peripheral where the second, third or forth data taken from the sram shows inside the slave/master an ecc error. in this situation a slave can finish a read transaction with error acknowledge (if the error is detected before the first data phase) or a slave / master can invalidate the related data phase with an invalid read / write transaction id error (see also chapter 4.2.7.4 ). a master that detects an sri read data ecc error is free to decide how it handles the situation: ? pmi and dmi: a bus error tr ap will be gener ated but only if and when a received 64 bit read data is really used by the cpu. this as pmi / dmi can read complete cache www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-19 v1.1, 2011-03 interrupt, v1.6 lines (4x64 bit) where the critical 64 bit is used, the other 3 x 64 bit are speculative reads and might not be used by the cpu later. ? dma: the dma ignores read data ecc in this product. background is that the sri ecc was introduced for the safe instruction fetch path. ? sfi: the sfi sri master ignores the read data ecc. background is that the sri ecc was introduced for the safe instruction fetch path. most of the sri peri pherals are signa lling detected sri ecc erro rs also to the scu: ? pmi and dmi: detected sri ecc errors are signalled to the scu via the still available ecc error signals (to the scu). more deta ils (sri address phas e ecc error or sri ecc read data error) can be found in the pmi / dmi control registers. ? ebu: signals detected sri address phase ecc errors to the scu. ? lmu: signals detected sri address phase ecc errors to the scu. more details (sri address phase ecc error or sram ecc error) can be found in the lmu control registers. ? pmu and sfi sri slave: no signalling of detected sri address phase ecc errors to the scu. 4.2.7.4 error tracking capability the xbar_sri tracks all sri transactions for sr i protocol errors. additionally it tracks informations about starvation errors and sri transaction id errors. this is done by all arbiters and the default slave in parallel as the xbar_sri supports the processing of multiple transactions from master and slaves in parallel which can result in parallel events at different slave connector interfaces. for this purpose, each arbiter has two error/debug registers where it samples the transaction informations of the transaction where the first protocol error happened. note: protocol errors and debug trigger events can lock the error/debug registers. only the first event of both sources can lock the registers. all other events are not captured with this two error/debug registers unless the lock was released in the meantime. further protocol errors will be ignored by an arbiter that has detected an protocol error until the tracking mechanism is re-activated via the arbiter internal control register. a detected protocol error or starvation error is signalled by the arbiter to the default slave module via two separate sideband signals for sri- and starvation error. the default slave samples the sideband signals pulses in an error status register intsat. as each slave has its own sideband signals, the default slave has the information which arbiter has detected an sri protocol or starvation error. each error signal can be masked individually by control registers in the arbiter modules. all debug registers are accessible via the sri-bus interface of the default slave. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-20 v1.1, 2011-03 interrupt, v1.6 for transaction id errors of write transactions the sci propagates the sci_id_err_n signal via the sri_wr_tr_id_err signal from the slave to the default slave module. the default slave sets the assigned bit in register idintsat. for transaction id error of read transactions the mcis propagate the sri_id_err_n signal via the sri_rd_tr_id_err signal from the ma ster to the default slave module. the default slave sets the assigned bit in register idintsat. once an error was signalled from an arbiter or an mci/sci to the default slave, the default slave module sends an interrupt requ est to the system. the system can read out the error status registers in the default sl ave module to find out which arbiter(s) or master/slave have detected an error, then the system can start with more detailed diagnostics by reading out the error/debug registers in the arbiter for a protocol error. the error informations captured for an sri protocol error allows the identification of the master via the sampled master tag id and the final destination via the sampled target address. additionally the arbiter samples the op-code and the sri_rd_n, sri_wr_n and sri_svm control signals of the transaction. in addition to the sri transaction information, the xbar_sri captures sideband signal informations ( xbar_errx (x = 0-6) .mci_sbs and xbar_errd .mci_sbs). in the TC1798 these sideband signals are used by th e dma sri master interface to provide informations about the requestor of a transaction, in parallel to the sri request phase. table 4-5 shows the encoding of the mci_sbs bit field for the encodi ng of the TC1798. after reading all relevant error informations, the error/debug tracking mechanism can be reactivated. table 4-5 encoding of errx.mci_sbs in the TC1798 mci_sbs[7:0] bit field encoding mci_sbs[2:0] 000 b dma channel 0 001 b dma channel 1 . . . 110 b dma channel 6 111 b dma channel 7 this bit field is only valid if mci_sbs[7:3] shows the move engine 0 or move engine 1 encoding. mci_sbs[7:3] 00000 b reserved 00001 b move engine 0 00010 b move engine 1 00011 b mli 0 00100 b mli 1 00101 b cerberus others -> reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-21 v1.1, 2011-03 interrupt, v1.6 4.2.7.5 debug trigger event generation (ocds level 1) the goal is to generate breakpoints on sele ctable and configurable events in the sri- bus traffic. inside the tricore breakpoint s are generated by the cerberus module based in debug trigger event signals created by the several decentralized debug blocks in system. the xbar_sri module uses the xbar_brk_out_n signal for this purpose. the generation of any debug trigger event signal has to be enabled by an asserted input signal ocds_enable. if this signal is deassert ed no arbiter generate a debug trigger event independent of the selected configurations . the xbar_brk_out_n is driven with the default value in this case. to enable the user to gain advantage of this feature in the needed way the debug event trigger selection and configuration is done via the three debug registers dbcon, dbadd and dbmadd and the three status registers dbsat, err and erraddr. all dbxxx registers reset only with the ocds_rst_n signal. the register dbsat collects al l debug trigger events from a ll arbiters in the xbar_sri module. when an arbiter generates a debug trigger event the according bit in register dbsat is set. an arbiter signals a debug tr igger event to the default slave via the xcb_db_evt_n signal. the dbcon register defines the debug trigger event conditions for each arbiter individually. several individual break cond itions can be combined by enabling them in parallel. possible break conditions are: ? write transactions ? if bit dbcon.wren is set only transactions with an asserted sri_wr_n signal can generate a debug event. note: only if dbcon.wren and dbcon. rden are set together a rmw transaction generate a debug trigger event. ? read transactions ? if bit dbcon.rden is set only transactions with an asserted sri_rd_n signal can generate a debug event. note: only if dbcon.wren and dbcon. rden are set together a rmw transaction generate a debug trigger event. ? supervisor mode transactions ? if bit dbcon.svmen is set only transacti ons with an asserted sri_svm signal can generate a debug event. ? transactions from a dedicated master ? if bit dbcon.masen is set only transactions initiated by master dbcon.master can generate a debug event. ? transactions accessing a defined address area www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-22 v1.1, 2011-03 interrupt, v1.6 ? if bit dbcon.adden is set only transactions accessing an address in the selected address area can generate a debug event. the selected address area is defined by the registers dbadd and dbmadd. register dbadd defines one global 32- bit address that is compared with sri_addr [31:0] for all bits where dbmaddr is set to ?1?. all enabled debug trigger conditions are combined by a logical and. example: if dbcon.wren and dbcon.svmen are set and all other enables are cleared a debug trigger event is only generat ed for a write transaction operating in the supervisor mode. additionally a debug trigger event is gener ated if dbcon.erren is set and an error occurs. please note that an error occurs only when the generation for this source is enabled in the linked registers arbcon or idinten. the result of the logical and of the first five debug trigger event options is combined with the result of the error debug trigger event by a logical or. a debug event is signaled to the default sl ave. the default slave combines all xbar arbiter debug event signals with its own and generates the debug event signal that is sent to the cerberus module. the minimum length of debug event signal that is send out to the cerberus module is adapted to the frequency of the cerberus module. the debug event signal to the cerberus will be asserted for as long as one at least one condition inside an xbar master module or the xbar default slave module is met at least. debug trigger events inside the xbar_sri are sampl ed in the register dbsat. additionally an interrupt can be generated for debug trigger events by the xbar_sri. when debug condition is reached in one of the xbar_sri arbiter modules, informations of the transaction that matched to the debug condition is captured in the two error/debug capture registers errx and erraddrx. if t he two registers are already locked due to an earlier action the capturing is not performed. writing to dbcon.rearm will rearm the feature, this also sets dbcon.arm. 4.2.7.6 interrupt and debug events of the xbar_sri module there are some interactions between interrupt them self and debug events. in general due to the nature of the crossbar concept several interrupts from the same or a different source (arbiter, mci or sci) can occur. one interrupt could occur several times before a service request routine is initiate. additionally can all interrupts occur in parallel to one or more debug trigger events. all following examples assume a time interval without any acknowledge either from a service routine or a debug routine and all consecutive interrupts/events come from the same source. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-23 v1.1, 2011-03 interrupt, v1.6 two consecutive protocol errors the first protocol error is captured as nor mal together with a generation of an interrupt to the system. the second protocol error is not captured as the two registers err and erradd are already locked and no interrupt is generated. two consecutive starvation errors the first starvation error ge nerate an interrupt to the system . the second starvation error will not generate an interrupt to the system. two consecutive transaction id errors the first transaction id error generate an interrupt to the system. the second transaction id error will not generate an interrupt to the system. two consecutive debug trigger events the first debug trigger event is captured as normal together with a generation of debug trigger event signal to the system. the sec ond debug trigger event is not captured as the two registers err and erradd are already lo cked and a debug trigger event signal is generated. protocol error followed by a debug trigger event the first protocol error is captured as nor mal together with a generation of an interrupt to the system. the later debug trigger event is not captured as the two registers err and erradd are already locked and a debug trigger event signal is generated to the system. debug trigger event followed by a protocol error the first debug trigger event is captured as normal together with a generation of debug trigger event signal to the system. the later protocol error is not captured as the two registers err and erradd are already locked and no interrupt is generated. starvation/transaction id error followed by a debug trigger event the first starvation/transactio n id error generate an interr upt to the system. the later debug trigger event is captured to the two registers err and erradd and a debug trigger event signal is generated to the system. debug trigger event followed by a starvation/transaction id error the first debug trigger event is captured as normal together with a generation of debug trigger event signal to the syst em. the later starva tion/transaction id error generates an interrupt to the system. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-24 v1.1, 2011-03 interrupt, v1.6 releasing the lock from registers err and erradd if the err and erradd registers are locked only from one even only (protocol error or debug trigger event) the lock can be releasing by: ? writing a one to arbconx.intack when the registers are locked by a protocol error ? writing a one to dbconx.rearm when the registers are locked by a debug trigger event if both, a protocol error and a debug trigger event occurred since the lock was released the last time both locks have to be released ? writing a one to dbconx.rearm and writing and to arbconx.intack when the registers are locked by a debug trigger event and a protocol error 4.2.8 implementation of the cross bar (xbar_sri) in the TC1798 this chapter describes the sri interconnect implementation in the TC1798. the knowledge of the specific implementation (e.g. the connection of the sri master / slave devices to the interconnect) is necessary in order to: ? map error informations to the connected slave devices ? define the arbitration scheme for accesses to the connected slave devices ? map xbar_sri (arbiter) control registers to connected slave devices this chapter includes three tables that ar e describing: the relationship (mapping) of ? the relationship (mapping) of TC1798 sri master devices to the xbar_sri master connection interfaces mci 0 - mci 15 ( table 4-6 ) ? the relationship (mapping) of TC1798 sri slave devices to the xbar_sri slave connection interfaces sci 0 - sci 15 ( table 4-7 ) ? the point to point connections between TC1798 sri master and slave devices ( table 4-8 ) 4.2.8.1 mapping of sri master modules to xbar_sri master interfaces table 4-6 shows the mapping of master devices to the xbar_sri master interfaces (mci 0 - mci 15). most of the xbar_sri control registers are related to the xbar_sri slave interfaces (sci 0 - sci 15) or the xbar_sri master interfaces. therefore it is important to know which TC1798 sri master device relates to which xbar_sri slave interface. example 1: the xbar_sri includes error registers where each mci is represented with 1 bit, showing if during the transfers requested by the master devices connected to the mcis an error situation occurred (e.g. xbar_idintsat ). example 2: the xbar_sri includes one arbiter module per connected sri slave device. each arbiter module includes a four bit field where the priority requests from connected mci can be www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-25 v1.1, 2011-03 interrupt, v1.6 defined. if the access priority of the dmi sri master to one sri slave device has to be changed, this can be done via the bit field related to mci 4 in the arbiter control register related to this sri slave ( xbar_priolx (x = 3-6) , xbar_priold ). 4.2.8.2 mapping of sri slave modules to xbar_sri slave interfaces table 4-7 shows the mapping of slave modules to the xbar_sri slave interfaces (sci 0 - sci 15). most of the xbar_sri control registers are related to the xbar_sri slave interfaces (sci 0 - sci 15) or the xbar_sri master interfaces. therefore it is important to know which TC1798 sri slave device relates to which xbar_sri slave interface or arbiter module. example 1 : the xbar_sri includes error registers where each sci is represented with 1 bit, showing if during the transfers requested by the master devices connected to the mcis an error situation occurred (e.g. xbar_dbsat , xbar_idintsat , xbar_idinten ). example 2: the xbar_sri includes one arbiter module per connected sri slave device. each arbiter module includes error capturing resources and breakpoint capabilities. these can be used e.g. to analyze accesses to the connected slave device that where answered with error acknowledge by the slave device (e.g. xbar_errx (x = 0-6) , xbar_erraddrd ). table 4-6 mapping of TC1798 sri master devices to mci xbar_sri master connection interface priority after reset connected sri master device mci 0 0 dma sri master interface, high priority mci 1 1 dma sri master interface, medium priority mci 2 2 dma sri master interface, low priority mci 3 3 sfi (pcp / sdma access to sri) mci 4 4 dmi mci 5 5 pmi mci 6 - mci 15 6 - www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-26 v1.1, 2011-03 interrupt, v1.6 4.2.8.3 TC1798 sri master / slave interconnection matrix table 4-8 shows the sri master to sri slave interconnects that are implemented in the TC1798. the not implemented sri master / slave connections are redundant as they would not be used by the device and does therefore not restrict the functionality. 4.2.8.4 connection master-slave in xbar_sri table 4-7 mapping of TC1798 sri slave devices to sci xbar_sri slave connection interface (sci) connected sri master device sci 0 pmi (pspr, pcache ram) sci 1 dmi (dspr, dcache ram) sci 2 sfi (dmi access to devices on spb) sci 3 pmu0 sci 4 pmu1 sci 5 lmu sci 6 ebu sci 7 - sci 14 - sci 15 xbar_sri default slave table 4-8 TC1798 sri master / slave interconnection matrix xbar_sri master connection interface dma (mci 0-2) sfi (mci 3) dmi (mci 4) pmi (mci 5) pmi (sci 0) yes yes yes - dmi (sci 1) yes yes - yes sfi (sci 2) - - yes - pmu0 (sci 3) yes yes yes yes pmu1 (sci 4) yes yes yes yes lmu (sci 5) yes yes yes yes ebu (sci 6) yes yes yes yes xbar_sri (sci 15) yes yes yes yes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-27 v1.1, 2011-03 interrupt, v1.6 as the sri-bus protocol is a point to point based bus implementation multiplexer inside the data paths in front of the mcis and arbiter/scis are required (see figure 4-3 and figure 4-4 ). the write data path multiplexer in front of the scis are controlled by the related arbiter modules. the read data path multiplexers in front of the mcis are controlled by all arbiters. master - and slave side mux during an sri transaction, the corresponding arbiter has to establish the data path connection from his slave connection interface to the corresponding master connection interface in order to enable the master to receive the sci control signals , if it is a read transaction the read data, send by the slave. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-28 v1.1, 2011-03 interrupt, v1.6 4.2.9 sri crossbar registers figure 4-6 and table 4-9 are showing the address maps with all registers of the sri crossbar (xbar_sri) module. xbar_sri unit register overview figure 4-6 TC1798 control registers (x = 0 ... 6, y = 2) note: addresses listed in colu mn ?offset address? of table 4-9 are word (32-bit) addresses. note: xbar_sri registers can be accessed only with sdtw (32 bit) transactions. 8, 16 bit and rmw transactions are not supported. table 4-9 registers address space - xbar_sri register address space module base address end address note xbar f870 0000 h f870 04ff h table 4-10 registers overview - xbar module control registers short name description offset addr. 1) access mode reset class descriptio n see read write - reserved 400 h - 404 h be be - - id identification register 2) 408 h u, sv be - page 4-34 dbsat debug trigger event status register 2) 40c h u, sv u, sv 1 page 4-35 xbar _reg_ its default slave register arbiter register default slave arbiter register scix xbar_dbsat xbar_intsat xbar_idintsat xbar_id identification register xbar_src xbar_idinten xbar_extcony xbar_arbconx xbar_priohx xbar_priolx xbar_erraddrx xbar_errx xbar_dbconx xbar_dbaddx xbar_dbmaddx xbar_arbcond xbar_priohd xbar_priold xbar_erraddrd xbar_errd xbar_dbcond xbar_dbaddd xbar_dbmaddd www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-29 v1.1, 2011-03 interrupt, v1.6 intsat arbiter interrupt status register 2) 410 h u, sv u, sv 3 page 4-36 idintsat id interrupt status register 2) 414 h u, sv u, sv 3 page 4-37 idinten id interrupt enable register 2) 418 h u, sv u, sv 3 page 4-39 - reserved 41c h - 4f8 h be be - - src xbar_sri service request control register 2) 4fc h u, sv sv 3 page 4-63 - reserved 01c h - 020 h be be - - - reserved 000 h be be - - arbcond arbiter control register default slave 004 h u, sv u, sv 3 page 4-42 - reserved 008 h u, sv u, sv - - priold arbiter priority register low default slave 00c h u, sv u, sv 3 page 4-44 erraddrd arbiter address error/debug capture register default slave 010 h u, sv u, sv 3 page 4-50 errd arbiter error/debug capture register default slave 014 h u, sv u, sv 3 page 4-51 dbcon arbiter x debug control register 018 h u, sv u, sv 3 page 4-52 dbadd arbiter x debug address register 01c h u, sv u, sv 3 page 4-55 dbmadd arbiter x debug mask address register 020 h u, sv u, sv 3 page 4-59 - reserved 024 h - 040 h be be - - table 4-10 registers overview - xbar module control registers (cont?d) short name description offset addr. 1) access mode reset class descriptio n see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-30 v1.1, 2011-03 interrupt, v1.6 arbcon0 arbiter 0 control register 044 h u, sv u, sv 3 page 4-42 - reserved 048 h u, sv u, sv - - priol0 arbiter 0 priority register low 04c h u, sv u, sv 3 page 4-44 erraddr0 arbiter 0 address error/debug capture register 050 h u, sv u, sv 3 page 4-50 err0 arbiter 0 error/debug capture register 054 h u, sv u, sv 3 page 4-51 dbcon0 arbiter 0 debug control register 058 h u, sv u, sv 3 page 4-52 dbadd0 arbiter 0 debug address register 05c h u, sv u, sv 3 page 4-55 dbmadd0 arbiter 0 debug mask address register 060 h u, sv u, sv 3 page 4-59 - reserved 064 h - 080 h be be - - arbcon1 arbiter 1 control register 084 h u, sv u, sv 3 page 4-42 - reserved 088 h u, sv u, sv - - priol1 arbiter 1 priority register low 08c h u, sv u, sv 3 page 4-44 erraddr1 arbiter 1 address error/debug capture register 090 h u, sv u, sv 3 page 4-50 err1 arbiter 1 error/debug capture register 094 h u, sv u, sv 3 page 4-51 dbcon1 arbiter 1 debug control register 098 h u, sv u, sv 3 page 4-52 dbadd1 arbiter 1 debug address register 09c h u, sv u, sv 3 page 4-60 table 4-10 registers overview - xbar module control registers (cont?d) short name description offset addr. 1) access mode reset class descriptio n see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-31 v1.1, 2011-03 interrupt, v1.6 dbmadd1 arbiter 1 debug mask address register 0a0 h u, sv u, sv 3 page 4-60 - reserved 0a4 h - 0bf h be be - - extcon2 external slave 2 control (sfi contro l registers) 0c0 h u, sv u, sv 3 page 4-40 arbcon2 arbiter 2 control register 0c4 h u, sv u, sv 3 page 4-42 - reserved 0c8 h u, sv u, sv - - priol2 arbiter 2 priority register low 0cc h u, sv u, sv 3 page 4-44 erraddr2 arbiter 2 address error/debug capture register 0d0 h u, sv u, sv 3 page 4-50 err2 arbiter 2 error/debug capture register 0d4 h u, sv u, sv 3 page 4-51 dbcon2 arbiter 2 debug control register 0d8 h u, sv u, sv 3 page 4-52 dbadd2 arbiter 2 debug address register 0dc h u, sv u, sv 3 page 4-55 dbmadd2 arbiter 2 debug mask address register 0e0 h u, sv u, sv 3 page 4-59 - reserved 0e4 h - 100 h be be - - arbcon3 arbiter 3 control register 104 h u, sv u, sv 3 page 4-42 - reserved 108 h u, sv u, sv - - priol3 arbiter 3 priority register low 10c h u, sv u, sv 3 page 4-44 erraddr3 arbiter 3 address error/debug capture register 110 h u, sv u, sv 3 page 4-50 table 4-10 registers overview - xbar module control registers (cont?d) short name description offset addr. 1) access mode reset class descriptio n see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-32 v1.1, 2011-03 interrupt, v1.6 err3 arbiter 3 error/debug capture register 114 h u, sv u, sv 3 page 4-51 dbcon3 arbiter 3 debug control register 118 h u, sv u, sv 3 page 4-52 dbadd3 arbiter 3 debug address register 11c h u, sv u, sv 3 page 4-55 dbmadd3 arbiter 3 debug mask address register 120 h u, sv u, sv 3 page 4-59 - reserved 124 h - 140 h be be - - arbcon4 arbiter 4 control register 144 h u, sv u, sv 3 page 4-42 - reserved 148 h u, sv u, sv - - priol4 arbiter 4 priority register low 14c h u, sv u, sv 3 page 4-44 erraddr4 arbiter 4 address error/debug capture register 150 h u, sv u, sv 3 page 4-50 err4 arbiter 4 error/debug capture register 154 h u, sv u, sv 3 page 4-51 dbcon4 arbiter 4 debug control register 158 h u, sv u, sv 3 page 4-52 dbadd4 arbiter 4 debug address register 15c h u, sv u, sv 3 page 4-55 dbmadd4 arbiter 4 debug mask address register 160 h u, sv u, sv 3 page 4-59 - reserved 164 h - 180 h be be - - arbcon5 arbiter 5 control register 184 h u, sv u, sv 3 page 4-42 - reserved 188 h u, sv u, sv - - priol5 arbiter 5 priority register low 18c h u, sv u, sv 3 page 4-44 table 4-10 registers overview - xbar module control registers (cont?d) short name description offset addr. 1) access mode reset class descriptio n see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-33 v1.1, 2011-03 interrupt, v1.6 erraddr5 arbiter 5 address error/debug capture register 190 h u, sv u, sv 3 page 4-50 err5 arbiter 5 error/debug capture register 194 h u, sv u, sv 3 page 4-51 dbcon5 arbiter 5 debug control register 198 h u, sv u, sv 3 page 4-52 dbadd5 arbiter 5 debug address register 19c h u, sv u, sv 3 page 4-55 dbmadd5 arbiter 5 debug mask address register 1a0 h u, sv u, sv 3 page 4-59 - reserved 1a4 h - 1c0 h be be - - arbcon6 arbiter 6 control register 1c4 h u, sv u, sv 3 page 4-42 - reserved 1c8 h u, sv u, sv - - priol6 arbiter 6 priority register low 1cc h u, sv u, sv 3 page 4-44 erraddr6 arbiter 6 address error/debug capture register 1d0 h u, sv u, sv 3 page 4-50 err6 arbiter 6 error/debug capture register 1d4 h u, sv u, sv 3 page 4-51 dbcon6 arbiter 6 debug control register 1d8 h u, sv u, sv 3 page 4-52 dbadd6 arbiter 6 debug address register 1dc h u, sv u, sv 3 page 4-55 dbmadd6 arbiter 6 debug mask address register 1e0 h u, sv u, sv 3 page 4-59 - reserved 1e4 h - 3ff h be be - - 1) the absolute register address is calculated as follows: module base address ( table 4-10 ) + offset address (shown in this column) 2) this register is located inside the default slave table 4-10 registers overview - xbar module control registers (cont?d) short name description offset addr. 1) access mode reset class descriptio n see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-34 v1.1, 2011-03 interrupt, v1.6 4.2.9.1 TC1798 control registers the identification register allows the progra mmer version-tracking of the module. the table below shows the identification register which is implemented in the lbcu module. xbar_id module identificat ion register (408 h ) reset value: 0004 d0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). mod_type [15:8] r module type the bit field is set to c0 h which defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines a module identification number. the value for the lbcu module is 000f h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-35 v1.1, 2011-03 interrupt, v1.6 note: this register is not reset with the normal system reset as all other registers in the xbar_sri. this register is only reset with the special debug reset. xbar_dbsat debug trigger event status register (40c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 scid 0 sci 6 sci 5 sci 4 sci 3 sci 2 sci 1 sci 0 rwh rw rwh rwh rwh rwh rwh rwh rwh field bits type description scin (n = 0-6) nrwh sci debug trigger event status 0 b no debug trigger event was detected for scin by its arbiter. 1 b a debug trigger event was detected for scin by its arbiter. writing a ?1? to this bit clears the bit. scid 15 rwh default slave debug trigger event status 0 b no debug trigger event was detected for the default slave by its arbiter. 1 b a debug trigger event was detected for the default slave by its arbiter. writing a ?1? to this bit clears the bit. 0 [14:7] rw reserved read as 0; must be written with 0. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-36 v1.1, 2011-03 interrupt, v1.6 xbar_intsat arbiter interrupt st atus register (410 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pr sci d 0 pr sci 6 pr sci 5 pr sci 4 pr sci 3 pr sci 2 pr sci 1 pr sci 0 rwh r rwh rwh rwh rwh rwh rwh rwh 1514131211109876543210 sc sci d 0 sc sci 6 sc sci 5 sc sci 4 sc sci 3 sc sci 2 sc sci 1 sc sci 0 rwh r rwh rwh rwh rwh rwh rwh rwh field bits type description scscin (n = 0-6) nrwh starvation error from scin status 0 b no starvation error is pending from scin 1 b a starvation error is pending from scin writing a zero to the bit leaves the content unchanged. writing a one to the bit clears it. in case of a parallel clearing via software and an error from the hardware the bit remains set and is not cleared. scscid 15 rwh starvation error from default slave status 0 b no starvation error is pending from default slave 1 b a starvation error is pending from default slave writing a zero to the bit leaves the content unchanged. writing a one to the bit clears it. in case of a parallel clearing via software and an error from the hardware the bit remains set and is not cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-37 v1.1, 2011-03 interrupt, v1.6 note: only the bits assigned to configured scis are implemented. not implemented bits treated as reserved bits, read as 0, should be written with 0. prscin (n = 16-22) nrwh protocol error from scin status 0 b no protocol error is pending from scin 1 b a protocol error is pending from scin writing a zero to the bit leaves the content unchanged. writing a one to the bit clears it. in case of a parallel clearing via software and an error from the hardware the bit remains set and is not cleared. prscid 31 rwh protocol error from default slave status 0 b no protocol error is pending from default slave 1 b a protocol error is pending from default slave writing a zero to the bit leaves the content unchanged. writing a one to the bit clears it. in case of a parallel clearing via software and an error from the hardware the bit remains set and is not cleared. 0 [30:23], [14:7] r reserved read as 0; should be written with 0. xbar_idintsat transaction id interrupt status register(414 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 id mci 5 id mci 4 id mci 3 id mci 2 id mci 1 id mci 0 r rwh rwh rwh rwh rwh rwh 1514131211109876543210 id sci d 0 id sci 6 id sci 5 id sci 4 id sci 3 id sci 2 id sci 1 id sci 0 rwh r rwh rwh rwh rwh rwh rwh rwh field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-38 v1.1, 2011-03 interrupt, v1.6 note: only the bits assigned to configured scis are implemented. not implemented bits treated as reserved bits, read as 0, should be written with 0. field bits type description idscin (n = 0-6) nrwh transaction id error from scin status 0 b no transaction id error is pending from scin 1 b a transaction id error is pending from scin writing a zero to the bit leaves the content unchanged. writing a one to the bit clears it. note: in case of a parallel clearing via software and an error from the hard ware the bit remains set and is not cleared. idscid 15 rwh transaction id error from default slave status 0 b no transaction id error is pending from default slave 1 b a transaction id error is pending from default slave writing a zero to the bit leaves the content unchanged. writing a one to the bit clears it. in case of a parallel clearing via software and an error from the hardware the bit remains set and is not cleared. idmcin (n = 16-21) nrwh transaction id error from mcin status 0 b no transaction id error is pending from mcin 1 b a transaction id error is pending from mcin writing a zero to the bit leaves the content unchanged. writing a one to the bit clears it. note: in case of a parallel clearing via software and an error from the hard ware the bit remains set and is not cleared. 0 [31:22], [14:7] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-39 v1.1, 2011-03 interrupt, v1.6 note: only the bits assigned to configured scis are implemented. not implemented bits treated as reserved bits, read as 0, should be written with 0. note: reset values for bits/bitfields coupled to masters or slaves that are not configured or enabled are zero. xbar_idinten transaction id interrupt enable register(418 h ) reset value: 003f 807f h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 en mci 5 en mci 4 en mci 3 en mci 2 en mci 1 en mci 0 r rwrwrwrwrwrw 1514131211109876543210 en sci d 0 en sci 6 en sci 5 en sci 4 en sci 3 en sci 2 en sci 1 en sci 0 rw r rwrwrwrwrwrwrw field bits type description enscin (n = 0-6) nrw enable id error from scin 0 b no transaction id error from scin are sampled 1 b a transaction id error from scin are sampled enscid 15 rw enable id error fr om default slave 0 b no transaction id error from the default slave is sampled 1 b a transaction id error from the default slave is sampled enmcin (n = 16-21) nrw enable id error from mcin 0 b no transaction id error from mcin are sampled 1 b a transaction id error from mcin are sampled 0 [31:22], [14:7] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-40 v1.1, 2011-03 interrupt, v1.6 xbar_extcon2 external control register 2 (0c0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 nop dis retry_cnt 0 rw rw rw rw 1514131211109876543210 maxws 0 no rm w no del tr 0 fre qdis f 0 fre qdis s wf wd 0 rw rw rw rw rw rw rw rw rw rw field bits type description wfwd 3rw wait for fpi write data for fpi-bus block write transfers the transaction request can be delayed until all write data arrived from the fpi-bus in the sfi. as on thew fpi-bus side very slow masters c an resident sri-bus slaves can blocked for many sri-bus cycles if the write transaction is started with the first write data 0 b write transactions on the sri-bus are requested with the first received write data from the fpi-bus (default) 1 b write transactions on the sri-bus are requested with the last received write data from the fpi-bus freqdiss 4rw disable fast request feature for sri to fpi transactions 0 b fast request feature is enabled (default) 1 b fast request feature is disabled ffreqs 5rw disable fast request feature for sri to fpi transactions 0 b fast request feature is used normally (default) 1 b or all transaction au tomatically the fast request feature is used this bit is not used in TC1798 and is not connected to the sfi. writing is possible and will change the bit nomal but has no impact to the sfi configuration www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-41 v1.1, 2011-03 interrupt, v1.6 note: only the bits assigned to configured scis are implemented. not implemented bits treated as reserved bits, read as 0, should be written with 0. note: reset values for bits/bitfields coupled to masters or slaves that are not configured or enabled are zero. freqdisf 6rw disable fast request feature for fpi to sri transactions 0 b fast request feature is enabled (default) 1 b fast request feature is disabled nodeltr 9rw control signal for deferred transactions 0 b deferred tranactions are generated (default) 1 b deferred tranactions are not generated normw 10 rw control signal for deferred transactions 0 b deferred tranactions are generated for rmw (default) 1 b deferred tranactions are not generated for rmw max_ws [19:13] rw fpi-bus waitstait retry ratio sif-fpi retry after the programed value delayed transactions from the fpi-bus. the value should be greater than 32, otherwise all transactions will be retired retry_cnt [23:20] rw mif_fpi retry idle count number of clock cycles be fore mif2_fpi repeats a transaction after a retry nopdis 24 rw nop-inclusion disable 0 b nop inclusion is used by sif_fpi (default) 1 b nop inclusion is disabled for sif_fpi 0 [31:25], [19:16], 11, [8:7], 5, [2:0] rw reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-42 v1.1, 2011-03 interrupt, v1.6 xbar_arbconx (x = 0-6) arbiter control register x (044 h +x*40 h ) reset value: 0000 0003 h xbar_arbcond arbiter control register d (004 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 spc sm en 0 rw rw r 1514131211109876543210 0 int ack set sc int set pr int sc err en pr err en r rwh rwh rwh rw rw field bits type description prerren 0rw sri protocol error enable 0 b protocol errors are not recognized and no information is captured. 1 b protocol errors are recognized and information is captured. scerren 1rw sri starvation error enable 0 b starvation based errors are not recognized and no information is captured. 1 b starvation based errors are recognized and information is captured. setprint 2rwh set sri protocol interrupt 0 b no protocol interrupt is generated 1 b a protocol interrupt is generated after the interrupt is generated by set the bit it?s automatically cleared by the hardware setscint 3rwh set sri starvation interrupt 0 b no starvation interrupt is generated 1 b a starvation interrupt is generated after the interrupt is generated by set the bit it?s automatically cleared by the hardware www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-43 v1.1, 2011-03 interrupt, v1.6 note: only the bits assigned to configured scis are implemented. bits for non configured scis are treated as reserved bits. note: the d at arbcond stands for default slave. intack 4rwh interrupt acknowledge 0 b default value 1 b an error for this arbiter is pending. the erraddr and err registers are not updated for new errors. writing a one to this bitfield while it?s set have the following results: the error lock of registers erraddr and err are released and the register could be updated with the next interrupt request detected (see chapter 4.2.7.4 ). in the cycle after the write action the hardware automatically clears the bit. smen 19 rw starvation mode enable 0 b starvation mode is disabled 1 b starvation mode is enabled spc [31:20] rw starvation protection counter reload value the reload value defines the period for the starvation protection. 0 [18:5] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-44 v1.1, 2011-03 interrupt, v1.6 xbar_priolx (x = 3-6) arbiter priority register x (04c h +x*40 h ) reset value: 0054 3210 h xbar_priold arbiter priority register d (00c h ) reset value: 0054 3210 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 master5 master4 rrwrw 1514131211109876543210 master3 master2 master1 master0 rw rw rw rw field bits type description master0 [3:0] rw master 0 priority (priority of dma high priority access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master1 [7:4] rw master 1 priority (priority of dma medium priority access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master2 [11:8] rw master 2 priority (priority of dma low priority access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-45 v1.1, 2011-03 interrupt, v1.6 note: only the bits assigned to configured mcis are implemented. bits for non configured scis are treated as reserved bits. note: the d at xbar_priold stands for default slave. note: reset values for bits/bitfields coupled to masters or slaves that are not configured or enabled are zero. master3 [15:12] rw master 3 priority (priority of sfi access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master4 [19:16] rw master 4 priority (priority of dmi access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master5 [23:20] rw master 5 priority (priority of pmi access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. 0 [31:24] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-46 v1.1, 2011-03 interrupt, v1.6 xbar_priol0 arbiter priority register 0 (04c h ) reset value: 0004 3210 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0master4 rrw 1514131211109876543210 master3 master2 master1 master0 rw rw rw rw field bits type description master0 [3:0] rw master 0 priority (priority of dma high priority access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master1 [7:4] rw master 1 priority (priority of dma medium priority access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master2 [11:8] rw master 2 priority (priority of dma low priority access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-47 v1.1, 2011-03 interrupt, v1.6 master3 [15:12] rw master 3 priority (priority of sfi access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master4 [19:16] rw master 4 priority (priority of dmi access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. 0 [31:20] r reserved read as 0; should be written with 0. xbar_priol1 arbiter priority register 1 (08c h ) reset value: 0050 3210 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 master5 0 rrwr 1514131211109876543210 master3 master2 master1 master0 rw rw rw rw field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-48 v1.1, 2011-03 interrupt, v1.6 field bits type description master0 [3:0] rw master 0 priority (priority of dma high priority access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master1 [7:4] rw master 1 priority (priority of dma medium priority access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master2 [11:8] rw master 2 priority (priority of dma low priority access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. master3 [15:12] rw master 3 priority (priority of sfi access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-49 v1.1, 2011-03 interrupt, v1.6 master5 [23:20] rw master 5 priority (priority of pmi access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. 0 [31:24], [19:16] r reserved read as 0; should be written with 0. xbar_priol2 arbiter priority register 2 (0cc h ) reset value: 0004 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0master4 rrw 1514131211109876543210 0 r field bits type description master4 [19:16] rw master 4 priority (priority of dmi access) this bitfield contains the master priority for the arbitration used by the arbiter of slave x. for each master a unique number for this slave has to be used. a lower number has a higher priority in the arbitration round than a higher one. 0 [31:20], [15:0] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-50 v1.1, 2011-03 interrupt, v1.6 note: the default value can differ from t he one shown here because a constant can be used to reduce the number of compared bi ts in the arbitration if a slave occupies only a limited address area. for more deta ils see the design specification of the xbar_sri. note: the d at xbar_erraddrd stands for default slave. xbar_erraddrd error/debug address capture register d(010 h ) reset value: 0000 0000 h xbar_erraddr0 error/debug address capture register 0(050 h ) reset value: c000 0000 h xbar_erraddr1 error/debug address capture register 1(090 h ) reset value: d000 0000 h xbar_erraddr2 error/debug address capture register 2(0d0 h ) reset value: f000 0000 h xbar_erraddrx (x = 3-6) error/debug address capture register x(050 h +x*40 h ) reset value: 8000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 addr rh 1514131211109876543210 addr rh field bits type description addr [31:0] rh transaction address this biffield contains the address of the erroneous transaction from the address phase www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-51 v1.1, 2011-03 interrupt, v1.6 xbar_errx (x = 0-6) error/debug capture register x (054 h +x*40 h ) reset value: 0000 0000 h xbar_errd error/debug capture register d (014 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mci_sbs[7:0] addr_ecc rh rh 1514131211109876543210 0 trid opc 0 svm wr rd r rh rh r rh rh rh field bits type description rd 0rh read indication status 0 b the read indication sri-bus signal line was asserted 1 b the read indication sri-bus signal line was deasserted wr 1rh write indication status 0 b the write indication sri-bus signal line was asserted 1 b the write indication sri-bus signal line was deasserted svm 2rh supervisor mode indication status 0 b the supervisor mode indication sri-bus signal line was deasserted 1 b the supervisor mode indication sri-bus signal line was asserted opc [7:4] rh operation code this bitfield contains the op-code of the erroneous transaction. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-52 v1.1, 2011-03 interrupt, v1.6 note: the d at xbar_errd stands for default slave. tr_id [13:8] rh transaction id this bitfield contains the transaction id of the erroneous transaction from the address phase. the transaction id is build out of an 4 bit unique tag id tr_id[3:0] and a 2 bit running number tr_id[5:4] (see also chapter 4.6 ). addr_ecc [23:16] rh sri address phase error detection information this bitfield contains the address phase error detection information of the erroneous transaction mci_sbs [31:24] rh mci sideband signals [7:0] this bitfield contains the mci sideband signals [7:0] that are related to the address phase informations captured by the errd/erraddr registers. in the TC1798 the sideband signals are used by the dma sri master interface to provide information about the dma requestor of a dma transaction (for the encoding see table 4-5 ). 0 [15:14], 3 r reserved read as 0; should be written with 0 xbar_dbconx (x = 0-6) debug control register x (058 h +x*40 h ) reset value: 0000 0000 h xbar_dbcond debug control register d (018 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0master mas en 0 err en add en svm en wr en rd en r rw rw r rw rw rw rw rw 1514131211109876543210 0 set db evt re arm db sat db en rwwrhr field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-53 v1.1, 2011-03 interrupt, v1.6 field bits type description dben 0r status of ocds enable signal displays the value of the ocds enable signal from cerberus. dbsat 1rh debug (ocds) trigger status 0 b the debug (ocds) trigger was used and has to be rearmed 1 b the debug (ocds) trigger is armed rearm 2w rearm debug (ocds) trigger 0 b read back value 1 b writing a one to this bit arms sets bit dbcon.dbsat. writing a one to this bitfield while it?s set have the following results: the debug lock of registers erraddr and err are released and the register could be updated with the next debug event request detected (see chapter 4.2.7.4 ). in the cycle after the write action the hardware automatically clears the bit. note: this bit is automatically reset by the hardware after dbcon.dbsat was set. setdbevt 3w set debug event 0 b default value 1 b a debug trigger event will be generated by this arbiter if the debug feature is enabled (dbcon.enst is set). the registers err and erradd capture the status if not locked already. note: this bit is automatically reset by the hardware. rden 16 rw read trigger enable 0 b read transaction are not used to trigger the debug trigger event (ocds) 1 b read transaction are used to trigger the debug trigger event (ocds) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-54 v1.1, 2011-03 interrupt, v1.6 wren 17 rw write trigger enable 0 b write transaction are not used to trigger the debug trigger event (ocds) 1 b write transaction are used to trigger the debug trigger event (ocds) svmen 18 rw svm trigger enable 0 b svm transaction are not used to trigger the debug trigger event (ocds) 1 b svm transaction are used to trigger the debug trigger event (ocds) adden 19 rw address trigger enable 0 b transaction addresses are not used to trigger the debug trigger event (ocds) 1 b transaction address defined by the registers dbadd and dbmadd are used to trigger the debug trigger event (ocds) erren 20 rw error trigger enable 0 b errored transaction are not used to trigger the debug trigger event (ocds) 1 b errored transaction are used to trigger the debug trigger event (ocds) reading this bit return always zero. note: protocol errors, starvation errors and transaction id errors can be used where, but have to enabled before as usual in registers arbcon or idinten depending on the error type. masen 23 rw master trigger enable 0 b the master tag id as defined in the bitfield master is not used to trigger the debug trigger event (ocds) 1 b the master tag id as defined in the bitfield master is used to trigger the debug trigger event (ocds) field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-55 v1.1, 2011-03 interrupt, v1.6 note: this register is not reset with the normal system reset as all other registers in the xbar_sri. this register is only reset with the special debug reset. note: the d at xbar_dbcond stands for default slave. note: this register is reset with the debug reset (class 1 reset). note: the last d at xbar_dbaddd stands for default slave. master [27:24] rw master tag id trigger selector the value of this bitfield define the master tag id within the address phase of an sri transaction to the related sri slave module that triggers the debug trigger event (ocds). the master tag ids are defined here: table 4-17 . 0 [31:28], [22:21], [15:4] r reserved read as 0; should be written with 0. xbar_dbaddd debug address register d (01c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 address rw 1514131211109876543210 address 0 rw r field bits type description upper [31:2] rw debug address boundary 0 [1:0] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-56 v1.1, 2011-03 interrupt, v1.6 note: this register is reset with the debug reset (class 1 reset). xbar_dbadd0 debug mask address register 0 (05c h ) reset value: c000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 address rrw 1514131211109876543210 address 0 rw r field bits type description address [29:2] rw debug address boundary one [31:30] r reserved read as 1; should be written with 0. 0 [1:0] r reserved read as 0; should be written with 0. xbar_dbadd1 debug mask address register 1 (09c h ) reset value: d000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 1 0 address rrw 1514131211109876543210 address 0 rw r www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-57 v1.1, 2011-03 interrupt, v1.6 note: this register is reset with the debug reset (class 1 reset). note: this register is reset with the debug reset (class 1 reset). field bits type description address [21:2] rw debug address boundary one [31:30], 28 r reserved read as 1; should be written with 0. 0 29, [27:22], [1:0] r reserved read as 0; should be written with 0. xbar_dbadd2 debug mask address register 2 (0dc h ) reset value: f000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 address rrw 1514131211109876543210 address 0 rw r field bits type description address [21:2] rw debug address boundary one [31:28] r reserved read as 1; should be written with 0. 0 [27:22], [1:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-58 v1.1, 2011-03 interrupt, v1.6 note: this register is reset with the debug reset (class 1 reset). xbar_dbadd3 debug mask address register 3 (11c h ) reset value: 8000 0000 h xbar_dbadd4 debug mask address register 4 (15c h ) reset value: 8000 0000 h xbar_dbadd6 debug mask address register 6 (1dc h ) reset value: 8000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 address rrw 1514131211109876543210 address 0 rw r field bits type description address [30:2] rw debug address boundary one 31 r reserved read as 1; should be written with 0. 0 [1:0] r reserved read as 0; should be written with 0. xbar_dbadd5 debug mask address register 5 (19c h ) reset value: 8000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 address rrw 1514131211109876543210 address 0 rw r www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-59 v1.1, 2011-03 interrupt, v1.6 note: this register is reset with the debug reset (class 1 reset). note: this register is reset with the debug reset (class 1 reset). note: the last d at xbar_dbm addd stands for default slave. field bits type description address [29:2] rw debug address boundary one 31 r reserved read as 1; should be written with 0. 0 30, [1:0] r reserved read as 0; should be written with 0. xbar_dbmaddd debug mask address register d (020 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 address rw 1514131211109876543210 address 0 rw r field bits type description address [31:2] rw debug address boundary 0 [1:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-60 v1.1, 2011-03 interrupt, v1.6 note: this register is reset with the debug reset (class 1 reset). xbar_dbmadd0 debug mask address register 0 (060 h ) reset value: c000 0000 h xbar_dbmadd5 debug mask address register 5 (1a0 h ) reset value: c000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 address rrw 1514131211109876543210 address 0 rw r field bits type description address [29:2] rw debug address boundary one [31:30] r reserved read as 1; should be written with 0. 0 [1:0] r reserved read as 0; should be written with 0. xbar_dbmadd1 debug mask address register 1 (0a0 h ) reset value: f7c0 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 0 1 address rrw 1514131211109876543210 address 0 rw r www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-61 v1.1, 2011-03 interrupt, v1.6 note: this register is reset with the debug reset (class 1 reset). note: this register is reset with the debug reset (class 1 reset). field bits type description address [21:2] rw debug address boundary one [31:28], [26:22] r reserved read as 1; should be written with 0. 0 27, [1:0] r reserved read as 0; should be written with 0. xbar_dbmadd2 debug mask address register 2 (0e0 h ) reset value: ffc0 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 address rrw 1514131211109876543210 address 0 rw r field bits type description address [21:2] rw debug address boundary one [31:22] r reserved read as 1; should be written with 0. 0 [1:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-62 v1.1, 2011-03 interrupt, v1.6 note: this register is reset with the debug reset (class 1 reset). xbar_dbmadd3 debug mask address register 3 (120 h ) reset value: 8000 0000 h xbar_dbmadd4 debug mask address register 4 (160 h ) reset value: 8000 0000 h xbar_dbmadd6 debug mask address register 6 (1e0 h ) reset value: 8000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 address rrw 1514131211109876543210 address 0 rw r field bits type description address [30:2] rw debug address boundary one 31 r reserved read as 1; should be written with 0. 0 [1:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-63 v1.1, 2011-03 interrupt, v1.6 xbar_src xbar_sri service request control register (4fc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre tos 0 srpn w w rh rw rw r rw field bits type description srpn [7:0] rw service request priority number tos [11:10] rw type-of-service state if written, register must be set to 00 b . this means type-of-service is associated with interrupt bus 0 (cpu interrupt arbitration bus). sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request flag clear bit setr 15 w request flag set bit 0 [9:8], [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-64 v1.1, 2011-03 interrupt, v1.6 4.3 shared resource interconnect to fpi bus interface (sfi bridge) this section describes the basic functionality of the sfi bridge. 4.3.1 functional overview the sfi bridge is a bi-directional bus bridge between the sri interconnect and the system peripheral fpi bus (spb). the bridge s upports all transactions types of both the sri bus and fpi bus. the bridge is transparent, this means that the address of a transaction and the master tag of a bus master is forwarded to the other side of the bridge. addresses are only changed by the bridge where it is required by the transaction conversion from the 64 bit sri interconnect to the 32 bit spb. in order to avoid deadlocks, priority is given to transactions initiated by the dma on spb or the pcp. bus errors at writes via the sfi bridge write transactions are handled as posted writes. the sfi is able to buffer multiple posted writes. this means that a write operation from the spb through the sfi bridge to the sri interconnect can be finished on spb and than generated on the sri autonomously by the sfi. if this write operation results in a bus error on the sri the error information is not passed back to the spb bus. this is also valid for transactions from sri to spb via sfi bridge. the bus error is detected by the on chip bus control logic of the target on chip bus system (bcu_fpi on the spb, xbar_sri on the sri) which can generate an interrupt. note that this behavior occurs only at write operations via the sfi bridge. it can also be triggered by an erroneous write cycle of a read-modify-write bus transaction. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-65 v1.1, 2011-03 interrupt, v1.6 4.4 system peripheral bus the TC1798 has one on-chip fpi bus: ? system peripheral bus (spb) ? system bus for on-chip peripherals this section gives an overview of the on-chip fpi bus. it describes its bus control units, the bus characteristics, bus arbitration, scheduling, prioritizing, error conditions, and debugging support. 4.4.1 overview the fpi bus interconnects the on-chip peripheral functional units with the TC1798 processor subsystem. the fpi bus is designed to be quick to be ac quired by on-chip functional units, and quick to transfer data. the low setup overhead of the fpi bus access protocol guarantees fast fpi bus acquisition, which is required for time-critical applications. the fpi bus is designed to sustain high transfer rates. for example, a peak transfer rate of up to 320 mbyte/s can be achieved with the 32-bit data bus at 80 mhz bus clock. multiple data transfers per bus arbitration cycle allow the fpi b us to operate close to its peak bandwidth. additional features of the fpi bus include: ? optimized for high speed and high performance ? support of multiple bus masters and pipelined transactions ? 32-bit wide address and data buses ? 8-, 16-, and 32-bit data transfers ? 64-, 128-, and 256-bit block transfers ? central simple per-cycle arbitration ? slave-controlled wa it state insertion ? support of atomic operatio ns ldmst, st.t and swap.w the functional units of the TC1798 are connected to the fpi bus via fpi bus interfaces. an fpi bus interfaces acts as bus agents, re questing bus transactions on behalf of their functional unit, or responding to bus transaction requests. there are two types of bus agents: ? fpi bus master agents can initiate fpi bus transactions and can also act as slaves. ? slave agents can only react and respond to fpi bus transaction requests in order to read or write internal registers of slave modules as for example memories. when an fpi bus master attempts to initiate a transfer on the fpi bus, it first signals a request for bus ownership to the bus cont rol unit (sbcu). when bus ownership is granted by the sbcu, an fpi bus read or writ e transaction is initia ted. the unit targeted by the transaction becomes the fpi bus sl ave, and responds with the requested action. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-66 v1.1, 2011-03 interrupt, v1.6 some functional units operate only as slaves, while others can operate as either masters or slaves on the fpi bus. in the TC1798, dmi and pmi (via the sfi bridge), pcp, dma (including cerberus and mlis) and sdma operate as fpi bus masters. on-chip peripheral units are typically fpi bus slaves. fpi bus arbitration is performed by the bus control unit (sbcu) of the fpi bus. in case of bus errors, the sbcu generates an interrupt request to the cpu and provides debugging information about the actual bus error to the cpu. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-67 v1.1, 2011-03 interrupt, v1.6 4.4.2 bus transaction types this section describes the spb transaction types. single transfers single transfers are byte, half-word, and word transactions that target any slave connected to spb. note that the sfi bridge operates as an spb master. block transfers block transfers operate in principle in the same way as single transfers do, but one address phase is followed by multiple data phases. block transfers can be composed of 2 word, 4 word, or 8 word transfers. note: in general, block transfers (2 word, 4 word, or 8 word) cannot be executed in the TC1798 with peripheral units that opera te as fpi bus slaves during an fpi bus transaction. block transfers are initiated by the following cpu instructions: ld.d, ld.da, mov.d, st.d and st.da. the bcopy instruction of the pcp also initiates a block transfer transaction on the fpi bus. atomic transfers atomic transfers are generated by ldmst, st.t and swap.w instructions that require two single transfers. the read and write tr ansfer of an atomic transfer are always locked and cannot be interrupted by another bus mast ers. atomic transfers are also referenced as read-modify-write transfers. note: see also table 4-13 for available fpi bus transfer types. 4.4.3 reaction of a busy slave if an fpi bus slave is busy at an incoming fpi bus transaction request, it can delay the execution of the fpi bus transaction. the requesting fpi bus master releases the fpi bus for one cycle after the fpi bus transaction request, in order to allow the fpi bus slave to indicate if it is ready to handle the requested fpi bus transaction. this sequence is repeated as long as the slave indicates that it is busy. note: for the fpi bus default master, the on e cycle gap does not resu lt in a performance loss because it is granted the fpi bus in th is cycle as default master if no other master requests the fpi bus for some other reasons. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-68 v1.1, 2011-03 interrupt, v1.6 4.4.4 address alignment rules fpi bus address generation is compliant with the following rules: ? half-word transactions must have a half-word aligned address (a0 = 0). half-word accesses on byte lanes 1 and 2 addresses are illegal. ? word transactions must always have word-aligned addresses (a[1:0] = 00 b ). ? block transactions must always ha ve block-type aligned addresses. 4.4.5 fpi bus basic operations this section describes some basic transactions on the fpi bus. the example in figure 4-7 shows the three cycles of an fpi bus operation: 1. request/grant cycle: the fpi bus master attempts to perform a read or write transfer and requests for the fpi bus. if the fpi bus is available, it is granted in the same cycle by the fpi bus controller. 2. address cycle: after the request/grant cycle, the master puts the address on the fpi bus, and all fpi bus slave devices check whether they are addressed for the following data cycle. 3. data cycle: in the data cycle, eith er the master puts writ e data on the fpi bus which is read by the fpi bus slave (write cycle) or vice versa (read cycle). transfers 2 and 3 show the conflict when two master try to use the fpi bus and how the conflict is resolved. in the example, the fpi b us master of transfer 2 has a higher priority than the fpi bus master of transfer 3. figure 4-7 basic fpi bus transactions at a block transfer, the address cycle of a se cond transfer is extended until the data cycles of the block transfer ar e finished. in the example of figure 4-8 , transfer 1 is a block transfer, while transfer 2 is a single transfer. request/ grant data cycle address cycle bus cycle 1 2 3 4 request/ grant address cycle data cycle data cycle address cycle request/grant 5 mca06109 transfer 1 transfer 2 transfer 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-69 v1.1, 2011-03 interrupt, v1.6 figure 4-8 fpi bus block transactions request/ grant data cycle address cycle b us cycle 1 2 3 4 request/ grant address cycle 5 mca06110 t ransfer 1 t ransfer 2 6 data cycle 7 data cycle data cycle data cycle www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-70 v1.1, 2011-03 interrupt, v1.6 4.5 fpi bus control unit (sbcu) the TC1798 incorporates one bcu for the spb, called sbcu. 4.5.1 fpi bus arbitration the arbitration unit of the bcu determines w hether it is necessary to arbitrate for fpi bus ownership, and, if so, which available bus requestor gets the fpi bus for the next data transfer. during arbitration, the bus is granted to the requesting agent with the highest priority. if no request is pending, the bus is granted to a default master. if no bus master takes the bus, the bcu itself will drive the fpi bus to prevent it from floating electrically. 4.5.1.1 arbitration on the system peripheral bus the TC1798 spb has four bus agents that can become a spb bus master (dma, sfi, pcp, sdma). each agent is supplied an arbitration priority as shown in table 4-11 . dma controller agent can be assigned to low, medium or high priority by software (via dma channel and ocds control registers). table 4-11 priority of TC1798 spb bus agents priority agent comment highest lowest any bus requestor meeting the starvation protection criteria is assigned this priority highest priority, used only for starvation protection dma, high priority dma requests from module: - ocds high priority 1) - dma channel with high priority 2) 1) priority of cerberus transaction at the on chip buss es is defined by the register bit ioconf.fpi_prio. the register is defined in the ocds chapter. 2) priority of a dma channel is defined by the corresponding chcrmn.dmaprio bits. the registers are defined in the dma chapter. sdma peripheral control processor (pcp) default master 0 dma, medium priority dma requests from module: - dma channels with med. priority sfi bridge default master 1 dma, low priority dma requests from modules: - cerberus low priority 1) - dma channels low priority 2) - mli www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-71 v1.1, 2011-03 interrupt, v1.6 if there is no request from an spb bus mast er, the spb is granted to a default master (sfi bridge or pcp) which has been at last the active master. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-72 v1.1, 2011-03 interrupt, v1.6 4.5.1.2 starvation prevention starvation prevention is a feature of the sbcu that can take care that even requesting low priority master agents will be granted after a period, where the period length can be controlled by sbcu control registers. because the priority assignment of the spb agents is fixed, it is possible that a lower-priori ty bus requestor may never be granted the bus if a higher-priority bus requestor continuously asks for, and receives, bus ownership. to protect against bus starvation of lower-pr iority masters, the starvation prevention mechanism of the sbcu will dete ct such cases and momentarily raise the priority of the lower-priority requestor to the highest priority (above all other priorities), thereby guaranteeing it access. starvation protection employs a counter that is decremented each time an arbitration is performed on the connected fpi bus. the coun ter is re-loaded with the starvation period value in the sbcu_con.spc bi t field as long it is en abled sbcu_con.spe. when this counter is counted down to zero, for each active bus request a request flag is stored in the bcu. this flag is cleared automatic ally when a master is granted the bus. when the next period is finished, an active request of a master from which the request flag was set, a starvation event happened. this master will now be set to the highest priority and will be granted service. if there are several masters to which this starvation condition applies, they are served in the order of their hard-wired priority ranking. if a master that is processing its transaction under starvation condition is retried, its corresponding request flag is automatically again. starvation protection can be enabled and disabled through bit sbcu_con.spe. the sample period of the counter is programmed through bit field sbcu_con.spc. spc should be set to a value at least greater than or equal to the number of masters. its reset value is 40 h . 4.5.2 fpi bus error handling when an error occurs on an fpi bus, its bcu captures and stores data about the erroneous condition and generates a service request if enabled to do so. the error conditions that force an error-capture are: ? error acknowledge: an fpi bus slave responds with an error to a transaction. ? un-implemented address: no fpi bus slave responds to a transaction request. ? time-out: a slave does not respond to a transaction request within a certain time window. the number of bus clock cycles that can el apse until a bus time-out is generated is defined by bit field sbcu_con.tout. when a transaction causes an error, the address and data phase signals of the transaction causing the error are captured and stored in registers. ? the error address capture register (sbcu_eadd) stores the 32-bit fpi bus address that has been captured during the erroneous fpi bus transaction. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-73 v1.1, 2011-03 interrupt, v1.6 ? the error data capture registers (sbcu_edat) stores the 32-bit fpi bus data bus information that has been captured during the erroneous fpi bus transaction. ? the error control capture register (sbcu_econ) stores status information of the bus error event. if more than one fpi bus transaction generates a bus error, only the first bus error is captured. after a bus error has been captured, the capture mechanism must be released again by software. if a write transaction from tricore causes an error on the spb, the originating master is not informed about th is error as it is not an spb ma ster agent. with each bus error- capture event, a service request is gener ated, and an interrupt can be generated if enabled and configured in the corresponding service request register. interpreting the bcu control register error information although the address and data values captured in registers sbcu_eadd and sbcu_edat, respectively, are self-expl anatory, the captured fpi bus control information needs some more explanation. register sbcu_econ captures the state of the read (rdn), write (wrn), supervisor mode (svm), acknowledge (ack), ready ( rdy), abort (abt), time-out (tout), bus master identification lines (tag) and transaction operation code (opc) lines of the fpi bus. the svm signal is set to 1 for an access in supervisor mode and set to 0 for an access in user mode. the time-out signal indicates if there was no response on the bus to an access, and the programmed time (via sbcu_ tout) has elapsed. tout is set to 1 in this case. an acknowledge code has to be dr iven by the selected slave during each data cycle of an access. thes e codes are listed in table 4-12 . transactions on the fpi bus are classified via a 4-bit operation code (see table 4-13 ). note that split transactions (opc = 1000 b to 1110 b ) are not used in the TC1798. table 4-12 fpi bus acknowledge codes code (ack) description 00 b nsc: no special condition. 01 b spt: split transaction (not used in the TC1798). 10 b rty: retry. slave can currently not respond to the access. master needs to repeat the access later. 11 b err: bus error, last data cycle is aborted. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-74 v1.1, 2011-03 interrupt, v1.6 table 4-13 fpi bus operation codes (opc) opc description 0000 b single byte transfer (8-bit) 0001 b single half-word transfer (16-bit) 0010 b single word transfer (32-bit) 0100 b 2-word block transfer 0101 b 4-word block transfer 0110 b 8-word block transfer 1111 no operation 0011 b , 0111 b , 1000 b -1110 b reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-75 v1.1, 2011-03 interrupt, v1.6 4.5.3 bcu debug support for debugging purposes, the bcu has the capa bility for breakpoint generation support. this ocds debug capability is controlled by the cerberus module and must be enabled by it (indicated by bit sbcu_dbcntl.eo). when bcu debug support has been enabl ed (eo = 1), any breakpoint request generated by the bcu to the cerberus disarms the bcu breakpoint logic for further breakpoint requests. in order to rearm the bcu breakpoint logic again for the next breakpoint request generation, bit sbcu_db cntl.ra must be set. the status of the bcu breakpoint logic (armed or disarm ed) is indicated by bit sbcu_dbcntl.oa. there are three types of trigger events: ? address triggers ? signal triggers ? grant triggers 4.5.3.1 address triggers the address debug trigger event conditi ons are defined by the contents of the sbcu_dbadr1, sbcu_dbadr2, and sbcu_dbcntl registers. a wide range of possibilities arise for the creation of debug trigger events based on addresses. the following debug trigger events can be selected: ? match on one signal address ? match on one of two signal addresses ? match on one address area ? mismatch on one address area each pair of dbadrx registers and dbcntl.onax bits determine one possible debug trigger event. the combination of these two possible debug trigger events defined by dbcntl.concom1 determine the address debug trigger event condition. figure 4-9 address trigger generation mca06114 ona2 sbcu_dbadr1 compare logic 1 (equal, greater equal) sbcu_dbcntl ona1 sbcu_dbadr2 compare logic 2 (equal, less equal) f pi bus a ddress address 1 trigger address 2 trigger control control adr1 adr2 2 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-76 v1.1, 2011-03 interrupt, v1.6 4.5.3.2 signal status triggers the signal status debug trigger event conditions are defined by the contents of the sbcu_dbbos and sbcu_dbcntl registers. depending on the selected configuration a wide range of possibilities arise for the creation of a debug trigger event based on fpi bus status signals. possible combinations are: ? match on a single signal status ? match on a multiple signal status with the multiple signal match conditions, all single signal match conditions are combined with a logical and to the signal status debug trigger event signal. the selection whether or not a single match condition is selected can be enabled/disabled selectively for each condition vi a the sbcu_dbcntl.onbosx bits. figure 4-10 signal status trigger generation mca06115 on bos3 sbcu_dbcntl fpi bus signals signa l statu s trigge r on bos2 on bos1 on bos0 1 = sbcu_dbbos opc svm wr rd equal compare = = 0 1 0 4 4 rd wr svm opc 0 0 0 1 0 1 0 1 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-77 v1.1, 2011-03 interrupt, v1.6 4.5.3.3 combination of triggers the combination of the four debug trigger si gnals to the single bcu breakpoint trigger event is defined via the bits conco m[2:0] of register sbcu_dbcntl (see figure 4-11 ). the two address triggers are combined to one address trigger that is further combined with signal status and grant trigger signals. a logical and or or combination can be selected for the bcu breakpoint trigger generation. figure 4-11 bcu breakpoint tr igger combination logic 4.5.3.4 bcu breakpoint generation examples this section gives three examples of ho w bcu debug trigger events are programmed. ocds debug example 1 ? task: generation of a bcu debug trigger event on any spb write access to address 00002004 h or 000020a0 h by spb master of the sfi bridge or the pcp. for this task, the following programming settings for the bcu breakpoint logic must be executed: 1. writing sbcu_dbadr1 = 0000 2004 h 2. writing sbcu_dbadr2 = 0000 20a0 h 3. writing sbcu_dbcntl = c1115010 h : a) onbos[3:0] = 1100 b means that no signal status trigger is generated (disabled) for a read signal match and write signal match condition according to the settings of bits rd and wr in register sbcu_dbbos. debug trigger event generation for supervisor mode signal match and opcode signal match condition is disabled. b) ona2 = 01 b means that the equal match condition for debug address 2 register is selected. mca06117 address 1 trigger signal status trigger concom2 concom1 concom0 and/or selection address 2 trigger grant trigger and/or selection and/or selection address trigger sbcu_dbcntl bcu breakpoint trigger www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-78 v1.1, 2011-03 interrupt, v1.6 c) ona1 = 01 b means that the equal match condition for debug address 1 register is selected. d) ong = 1 means that the grant debug trigger is enabled. e) concom[2:0] = 101 b means that the address trigger is created by address trigger 1 or address trigger 2 (concom1 = 0), and that the grant trigger is anded with the address trigger (concom0 = 1), and that the signal status trigger is anded with the address trigger (concom2 = 1). f) ra = 1 means that the bcu breakpoint logic is rearmed. 4. writing sbcu_dbgrnt = ffffffd7 h : means that the grant trigger for the spb master of the pcp and sfi bridge is enabled. 5. writing sbcu_dbbos = 00001000 h : means that the signal status trigger is generated on a write transfer and not on a read transfer. ocds debug example 2 ? task: generation of a bcu debug trigger event on any half-word access in user mode to address area 01ffffff h to 02ffffff h by any master. for this task, the following programming settings for the bcu breakpoint logic must be executed: 1. writing sbcu_dbadr1 = 01ffffff h 2. writing sbcu_dbadr2 = 02ffffff h 3. writing sbcu_dbcntl = 32206010 h : a) onbos[3:0] = 0011 b means that the signal status trigger is disabled for a read or for write signal status match but enabled for supervisor mode match and opcode match conditions according to the settings of bit svm and bit field opc in register sbcu_dbbos. b) ona2 = 10 b means that the address 2 trigger is generated if the fpi bus address is greater or equal to sbcu_dbadr2. c) ona1 = 10 b means that the address 1 trigger is generated if the fpi bus address is greater or equal to sbcu_dbadr1. d) ong = 0 means that the grant debug trigger is disabled. e) concom[2:0] = 110 b means that the address trigger is created by address trigger 1 and address trigger 2 (concom1 = 1), and that the grant trigger is or- ed with the address trigger (concom0 = 0), and that the signal status trigger is and-ed with the address trigger (concom2 = 1). f) ra = 1 means that the bcu breakpoint logic is rearmed. 4. writing sbcu_dbgrnt = ffffffff h : means that no grant trigger for spb masters is selected (?don?t care? because also disabled by ong = 0). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-79 v1.1, 2011-03 interrupt, v1.6 5. writing sbcu_dbbos = 00000001 h : means that the signal status trigger is generated for read (rd = 0) and write (wr = 0) half-word transfers (opc = 0001 b ) in user mode (svm = 0). ocds debug example 3 ? task: generation of a bcu debug trigger event on any access into address area 01ffffff h to ffffffff h by the pcp. for this task the following programming settings for the bcu breakpoint logic must be executed: 1. writing sbcu_dbadr1 = 01ffffff h 2. writing sbcu_dbadr2 = don?t care 3. writing sbcu_dbcntl = 00215010 h : a) onbos[3:0] = 0000 b means that a signal status trigger is generated for all fpi bus opcodes not equal to a ?no operation? opcode. b) ona2 = 00 b means that no address 2 trigger is generated. c) ona1 = 10 b means that the address 1 trigger is generated if the fpi bus address is greater or equal to sbcu_dbadr1. d) ong = 1 means that the grant debug trigger is enabled. e) concom[2:0] = 101 b means that the address trigger is created by address trigger 1 or address trigger 2 (concom1 = 0 ), and that the grant trigger is and- ed with the address trigger (concom0 = 1), and that the signal status trigger is anded with the address trigger (concom2 = 1). f) ra = 1 means that the bcu breakpoint logic is rearmed. 4. writing sbcu_dbgrnt = fffffff7 h : means that the grant trigger for the spb bus master of the pcp is enabled. 5. writing sbcu_dbbos is ?don?t care?. no signal trigger for svm, wr, or rd is generated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-80 v1.1, 2011-03 interrupt, v1.6 4.5.4 system bus control unit registers figure 4-12 and table 4-15 are showing the address maps with all registers of the system bus control unit (sbcu) module. sbcu control regi sters overview figure 4-12 sbcu registers table 4-14 registers address space - sbcu address space module base address end address note sbcu f000 0100 h f000 01ff h table 4-15 registers overview - sbcu control registers short name description offset addr. 1) access mode reset class description see read write ? reserved 000 h - 004 h be be - - sbcu_id sbcu module identification register 008 h u, sv be - page 4-82 ? reserved 00c h be be - - sbcu_ con sbcu control register 010 h u, sv sv 3 page 4-83 ? reserved 014 h - 01c h be be 3 - sbcu_reg_its sbcu_con control registers interrupt registers address/data register sbcu_econ sbcu_eadd sbcu_src sbcu_edat debug registers sbcu_dbcntl sbcu_dbgrnt sbcu_dbadr1 sbcu_dbadr2 sbcu_dbbos sbcu_dbgntt sbcu_dbadrt sbcu_dbbost sbcu_id identification register sbcu_dbdat www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-81 v1.1, 2011-03 interrupt, v1.6 sbcu_ econ sbcu error control capture register 020 h u, sv sv 3 page 4-84 sbcu_ eadd sbcu error address capture register 024 h u, sv sv 3 page 4-86 sbcu_ edat sbcu error data capture register 028 h u, sv sv 3 page 4-87 ? reserved 02c h be be - - sbcu_ dbcntl sbcu debug control register 030 h u, sv sv 1 page 4-88 sbcu_ dbgrnt sbcu debug grant mask register 034 h u, sv sv 1 page 4-91 sbcu_ dbadr1 sbcu debug address register 1 038 h u, sv sv 1 page 4-93 sbcu_ dbadr2 sbcu debug address register 2 03c h u, sv sv 1 page 4-93 sbcu_ dbbos sbcu debug bus operation signals register 040 h u, sv sv 1 page 4-94 sbcu_ dbgntt sbcu debug trapped master register 044 h u, sv be 1 page 4-95 sbcu_ dbadrt sbcu debug trapped address register 048 h u, sv be 1 page 4-97 sbcu_ dbbost sbcu debug trapped bus operation signals register 04c h u, sv be 1 page 4-98 sbcu_ dbdat sbcu debug data status register 050 h u, sv be 1 page 4-100 ? reserved 054 h - 0f8 h be be - - sbcu_ src sbcu service request control register 0fc h u, sv sv 3 page 4-102 1) the absolute register address is calculated as follows: module base address ( table 4-14 ) + offset address (shown in this column) table 4-15 registers overview - sbcu control registers (cont?d) short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-82 v1.1, 2011-03 interrupt, v1.6 4.5.4.1 sbcu id register description the identification register allows the progra mmer version-tracking of the module. the table below shows the identification register which is implemented in the sbcu module. sbcu_id module identificat ion register (008 h ) reset value: 0000 6axx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 mod_number mod_rev rr field bits type description mod_rev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). mod_number [15:8] r module number value this bit field defines a module identification number. the value for the lbcu module is 006ah. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-83 v1.1, 2011-03 interrupt, v1.6 4.5.4.2 sbcu control registers descriptions the sbcu control register controls the overall operation of the sbcu, including setting the starvation sample period, the bus time-out period, enabling starvation-protection mode, and error handling. sbcu_con sbcu control register (010 h ) reset value: 4009 ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 spc 0 spe 0 dbg rw r rwrwrw 1514131211109876543210 tout rw field bits type description tout [15:0] rw sbcu bus time-out value the bit field determines the number of system peripheral bus time-out cycles . default after reset is ffff h (= 65536 bus cycles). pls. note: tout value must be >= 5. dbg 16 rw sbcu debug trace enable 0 b sbcu debug trace disabled 1 b sbcu debug trace enabled (default after reset) spe 19 rw sbcu starvation protection enable 0 b sbcu starvation protection disabled 1 b sbcu starvation protection enabled (default after reset) spc [31:24] rw starvation period control determines the sample period for the starvation counter. must be larger than the number of masters. the reset value is 40 h . 0 [18:17], [23:20] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-84 v1.1, 2011-03 interrupt, v1.6 4.5.4.3 sbcu error registers descriptions the capture of bus error conditions is enabled by setting sbcu_con.dbg to 1. in case of a bus error, information about the condition will then be stored in the sbcu error capture registers. the sbcu error capture r egisters can then be examined by software to determine the cause of the fpi bus error. if enabled and an fpi bus error occurs, the sbcu_econ register holds the captured fpi bus control information and an error count of the number of bus errors. the sbcu_eadd register stores the captured fpi bus address. the sbcu_edat register stores the captured fpi bus data. if the capture of fpi bus error conditions is disabled (sbcu_con.dbg = 0), the sbcu error capture registers remain untouched. note: the sbcu error capture registers store only the parameters of the first error. in case of multiple bus errors, an error counter sbcu_econ.errcnt shows the number of bus errors since the first error occurred. an application reset clears this bit field to zero, but the counter can be set to any value through software. this counter is prevented from over flowing, so a value of 2 16 - 1 indicates that at least this many errors have occurred, but there may have been more. after sbcu_econ has been read, the sbcu_econ, sbcu_eadd and sbcu_edat registers are re-enabled to trace fpi bus error conditions. sbcu_econ sbcu error control capture register(020 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 opc tag rdn wrn svm ack abt rdy t out rwh rwh rwh rwh rwh rwh rwh rwh rwh 1514131211109876543210 errcnt rwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-85 v1.1, 2011-03 interrupt, v1.6 field bits type description errcnt [15:0] rwh fpi bus error counter errcnt is incremented on every occurrence of an fpi bus error. errcnt is reset to 0000 h after the sbcu_econ register is read. 1) tout 16 rwh state of fpi bus time-out signal this bit indicates the state of the time-out signal at an fbi bus error. 0 b no time-out occurred 1 b time-out has occurred rdy 17 rwh state of fpi bus ready signal this bit indicates the state of the ready signal at an fbi bus error. 0 b wait state(s) have been inserted. ready signal was active 1 b ready signal was inactive abt 18 rwh state of fpi bus abort signal this bit indicates the state of the abort signal at an fbi bus error. 0 b master has aborted an fpi bus transfer. abort signal was active 1 b abort signal was inactive ack [20:19] rwh state of fpi bus acknowledge signals this bit field indicates the acknowledge code that has been output by the selected slave at an fpi bus error. coding see table 4-12 . svm 21 rwh state of fpi bus supervisor mode signal this bit indicates whether the fpi bus error occurred in supervisor mode or in user mode. 0 b transfer was initiated in user mode 1 b transfer was initiated in supervisor mode wrn 22 rwh state of fpi bus write signal this bit indicates whether the fpi bus error occurred at a write cycle (see table 4-16 ). rdn 23 rwh state of fpi bus read signal this bit indicates whether the fpi bus error occurred at a read cycle (see table 4-16 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-86 v1.1, 2011-03 interrupt, v1.6 tag [27:24] rwh fpi bus master tag number signals this bit field indicates the fpi bus master tag number (definitions see table 4-17 ). opc [31:28] rwh fpi bus operation code signals the fpi bus operation codes are defined in table 4-13 . 1) in the TC1798, aborted accesses to a 0 wait stat e spb slave may also increment errcnt when the slave generates an error acknowledge. table 4-16 fpi bus read/w rite error indication rd wr fpi bus cycle 0 0 fpi bus error occurred at the read transfer of a read-modify-write transfer. 0 1 fpi bus error occurred at a read cycle of a single transfer. 1 0 fpi bus error occurred at a write cycle of a single transfer or at the write cycle of a read-modify-write transfer. 1 1 does not occur. sbcu_eadd sbcu error address capture register (024 h ) reset value: 0000 0000 h 31 0 fpiadr rwh field bits type description fpiadr [31:0] rwh captured fpi bus address this bit field holds the 32-bit fpi bus address that has been captured at an fpi bus error. note that if multiple bus errors occurred, only the address of the first bus error is captured. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-87 v1.1, 2011-03 interrupt, v1.6 sbcu_edat sbcu error data capture register (028 h ) reset value: 0000 0000 h 31 0 fpidat rwh field bits type description fpidat [31:0] rwh captured fpi bus data this bit field holds the 32-bit fpi bus data that has been captured at an fpi bus error. note that if multiple bus errors occurred, only the data of the first bus error is captured. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-88 v1.1, 2011-03 interrupt, v1.6 4.5.4.4 sbcu ocds re gisters descriptions sbcu_dbcntl sbcu debug control register (030 h ) reset value: 0000 7003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 on bos 3 on bos 2 on bos 1 on bos 0 0 ona2 0 ona1 0 ong rw rw rw rw r rw r rw r rw 1514131211109876543210 0 con com 2 con com 1 con com 0 0ra0oaeo r rwrwrw r w r r r field bits type description eo 0r status of sbcu debug support enable this bit is controlled by the cerberus and enables the sbcu debug support. 0 b sbcu debug support is disabled 1 b sbcu debug support is enabled (default after reset) oa 1r status of sbcu breakpoint logic 0 b the sbcu breakpoint logic is disarmed. any further breakpoint activation is discarded 1 b the sbcu breakpoint logic is armed the oa bit is set by writing a 1 to bit ra. when oa is set, registers sbcu_dbgntt, sbcu_dbadrt, and sbcu_dbbost are reset. ra 4w rearm sbcu breakpoint logic writing a 1 to this bit rearms sbcu breakpoint logic and sets bit oa = 1. ra is always reads as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-89 v1.1, 2011-03 interrupt, v1.6 concom0 12 rw grant and address trigger relation 0 b the grant phase trigger condition and the address trigger condition (see concom1) are combined with a logical or for further control 1 b the grant phase trigger condition and the address trigger condition (see concom1) are combined with a logical and for further control (see figure 4-11 ) concom1 13 rw address 1 and address 2 trigger relation 0 b address 1 trigger condition and address 2 trigger condition are combined with a logical or to the address trigger condition for further control 1 b address 1 trigger condition and address 2 trigger condition are combined with a logical and to the address trigger condition for further control (see figure 4-11 ) concom2 14 rw address and signal trigger relation 0 b address trigger condition (see concom1) and signal status trigger conditions are combined with a logical or for further control 1 b address phase trigger condition (see concom1) and the signal status trigger conditions are combined with a logical and for further control (see figure 4-11 ) ong 16 rw grant trigger enable 0 b no grant debug event trigger is generated 1 b the grant debug event trigger is enabled and generated according the settings of register sbcu_dbgrnt (see figure 4-11 ) ona1 [21:20] rw address 1 trigger control 00 b no address 1 trigger is generated 01 b an address 1 trigger event is generated if the fpi bus address is equal to sbcu_dbadr1 10 b an address 1 trigger event is generated if fpi bus address is greater or equal to sbcu_dbadr1 11 b same as 00 b (see also figure 4-9 ). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-90 v1.1, 2011-03 interrupt, v1.6 ona2 [25:24] rw address 2 trigger control 00 b no address 2 trigger is generated 01 b an address 2 trigger event is generated if the fpi bus address is equal to sbcu_dbadr2 10 b an address 2 trigger event is generated if fpi bus address is greater or equal to sbcu_dbadr2 11 b same as 00 b see also figure 4-9 . onbos0 28 rw opcode signal status trigger condition 0 b a signal status trigger is generated for all fpi bus opcodes except a ?no operation? opcode 1 b a signal status trigger is generated if the fpi bus opcode matches the opcode as defined in dbbos.opc (see figure 4-10 ) onbos1 29 rw supervisor mode signal trigger condition 0 b the signal status trigger generation for the fpi bus supervisor mode signal is disabled 1 b a signal status trigger is generated if the fpi bus supervisor mode signal state is equal to the value of dbbos.svm (see figure 4-10 ) onbos2 30 rw write signal trigger condition 0 b the signal status trigger generation for the fpi bus write signal is disabled 1 b a signal status trigger is generated if the fpi bus write signal state is equal to the value of dbbos.wr (see figure 4-10 ) onbos3 31 rw read signal trigger condition 0 b the signal status trigger generation for the fpi bus read signal is disabled 1 b a signal status trigger is generated if the fpi bus read signal state is equal to the value of dbbos.rd (see figure 4-10 ) field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-91 v1.1, 2011-03 interrupt, v1.6 0 [3:2], [11:5], 15, [19:17], [23:22], [27:26] r reserved read as 0; should be written with 0. sbcu_dbgrnt sbcu debug grant mask register (034 h ) reset value: 0000 ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 ones dma l one sfi dma m pcp sdm a one dma h rw rw rw rw rw rw rw rw rw field bits type description dmah 0rw cerberus grant trigger enable, high priority 1) 0 b fpi bus transactions with high-priority dma as bus master are enabled for grant trigger event generation 1 b fpi bus transactions with high-priority dma as bus master are disabled for grant trigger event generation sdma 2rw sdma grant trigger enable 0 b fpi bus transactions requested by the sdma bus master are enabled for grant trigger event generation 1 b fpi bus transactions requested by the sdma bus master are disabled for grant trigger event generation field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-92 v1.1, 2011-03 interrupt, v1.6 pcp 3rw pcp grant trigger enable 0 b fpi bus transactions with pcp as bus master are enabled for grant trigger event generation 1 b fpi bus transactions with pcp as bus master are disabled for grant trigger event generation dmam 4rw dma grant trigger enable, medium priority 2) 0 b fpi bus transactions with medium-priority dma channels as bus master are enabled for grant trigger event generation 1 b fpi bus transactions with medium-priority dma channels as bus master are disabled for grant trigger event generation sfi 5rw sfi bridge grant trigger enable 0 b fpi bus transactions with sfi bridge as bus master are enabled for grant trigger event generation 1 b fpi bus transactions with sfi bridge as bus master are disabled for grant trigger event generation dmal 7rw dma grant trigger enable, low priority 3) 0 b fpi bus transactions with low-priority dma channels as bus master are enabled for grant trigger event generation 1 b fpi bus transactions with low-priority dma channels as bus master are disabled for grant trigger event generation one, ones 1, 6, [15:8] rw reserved read as 1 after reset; reading these bits will return the value last written. 0 [31:16] r reserved read as 0; should be written with 0. 1) including dma transactions from dma channels with high priority and from cerberus with high priority. 2) including dma transactions from dma channels with medium priority. 3) including dma transactions from dma channels with low priority, mli and from cerberus with low priority. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-93 v1.1, 2011-03 interrupt, v1.6 sbcu_dbadr1 sbcu debug address 1 register (038 h ) reset value: 0000 0000 h 31 0 adr1 rw field bits type description adr1 [31:0] rw debug trigger address 1 this register contains the address for the address 1 trigger event generation. sbcu_dbadr2 sbcu debug address 2 register (03c h ) reset value: 0000 0000 h 31 0 adr2 rw field bits type description adr2 [31:0] rw debug trigger address 2 this register contains the address for the address 2 trigger event generation. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-94 v1.1, 2011-03 interrupt, v1.6 sbcu_dbbos sbcu debug bus operation signals register (040 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0rd0wr0svm opc rrwrrwrrw rw field bits type description opc [3:0] rw opcode for signal status debug trigger this bit field determines the type (opcode) of an fpi bus transaction for which a signal status debug trigger event is generated (if enabled by dbcntl.onbos0 = 1). 0000 b trigger on single byte transfer selected 0001 b trigger on single half-word transfer selected 0010 b trigger on single word transfer selected 0100 b trigger on 2-word block transfer selected 0101 b trigger on 4-word block transfer selected 0110 b trigger on 8-word block transfer selected 1111 b trigger on no operation selected other bit combinations are reserved. svm 4rw svm signal for status debug trigger this bit determines the mode of an fpi bus transaction for which a signal status debug trigger event is generated (if enabled by dbcntl.onbos1 = 1). 0 b trigger on user mode selected 1 b trigger on supervisor mode selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-95 v1.1, 2011-03 interrupt, v1.6 wr 8rw write signal for status debug trigger this bit determines the state of the wr signal of an fpi bus transaction for which a signal status debug trigger event is generated (if enabled by dbcntl.onbos2 = 1). 0 b trigger on a singl e write transfer or write cycle of an atomic transfer selected 1 b no operation or read transaction selected rd 12 rw write signal for status debug trigger this bit determines the state of the rd signal of an fpi bus transaction for which a signal status debug trigger event is generated (if enabled by dbcntl.onbos3 = 1). 0 b trigger on a single read tr ansfer or read cycle of an atomic transfer selected 1 b no operation or write transfer selected 0 [7:5], [11:9], [31:13] r reserved read as 0; should be written with 0. sbcu_dbgntt sbcu debug trapped master register (044 h ) reset value: 0000 ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 ch nr 07 ch nr 06 ch nr 05 ch nr 04 ch nr 03 ch nr 02 ch nr 01 ch nr 00 r rhrhrhrhrhrhrhrh 1514131211109876543210 ones dma l one sfi dma m pcp sdm a one dma h r rhrhrhrhrhrh r rh field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-96 v1.1, 2011-03 interrupt, v1.6 field bits type description dmah 0rh high-priority dma fpi bus master status 1) this bit indicates whether the dma with a high priority request was fpi bus master when the break trigger event occurred. 0 b the high-priority dma was not the fpi bus master. 1 b the high-priority dma was the fpi bus master. sdma 2rh sdma fpi bus master status this bit indicates whether the sdma was fpi bus master when the break trigger event occurred. 0 b the sdma was not the fpi bus master. 1 b the sdma was the fpi bus master. pcp 3rh pcp fpi bus master status this bit indicates whether the pcp was fpi bus master when the break trigger event occurred. 0 b the pcp was not an fpi bus master. 1 b the pcp was fpi bus master at the break trigger event. dmam 4rh medium-priority dma fpi bus master status 2) this bit indicates whether the dma with a medium priority request was fpi bus master when the break trigger event occurred. 0 b the medium-priority dma was not the fpi bus master. 1 b the medium-priority dma was the fpi bus master. sfi 5rh sfi bridge fpi bus master status this bit indicates whether the sfi bridge was fpi bus master when the break trigger event occurred. 0 b the sfi bridge was not an fpi bus master. 1 b the sfi bridge was fpi bus master. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-97 v1.1, 2011-03 interrupt, v1.6 dmal 7rh low-priority dma fpi bus master status 3) this bit indicates whether the dma with a low- priority request was the fpi bus master when the break trigger event occurred. 0 b the low-priority dma was not the fpi bus master. 1 b the low-priority dma was the fpi bus master. chnr0y (y = 0-7) 16+y rh dma channel number status these bits indicate which dma channel with number 0y was active when a dma break trigger event occurred. 0 b dma channel 0y was not active at a dma break trigger event. 1 b dma channel 0y was active at a dma break trigger event. one, ones 1, 6, [15:8] r reserved read as 1; should be written with 0. 0 [31:24] r reserved read as 0; should be written with 0. 1) including dma transactions from dma channels with high priority and from cerberus with high priority. 2) including dma transactions from dma channels with medium priority. 3) including dma transactions from dma channels with low priority, mli and from cerberus with low priority. sbcu_dbadrt sbcu debug trapped address register (048 h ) reset value: 0000 0000 h 31 0 fpiadr rh field bits type description fpiadr [31:0] rh fpi bus address status this register contains the fpi bus address that was captured when the ocds break trigger event occurred. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-98 v1.1, 2011-03 interrupt, v1.6 sbcu_dbbost sbcu debug trapped bus op eration signals register (04c h ) reset value: 0000 3180 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 fpi tag rrh 1514131211109876543210 0 fpi t out fpi abo rt fpi rd fpi ops fpi rst fpi wr fpi rdy fpi ack fpi svm fpi opc r rhrhrhrh rh rhrh rh rh rh field bits type description fpiopc [3:0] rh fpi bus opcode status this bit field indicates the type (opcode) of the fpi bus transaction captured from the fpi bus signal lines when the bcu break trigger event occurred. 0000 b single byte transfer 0001 b single half-word transfer 0010 b single word transfer 0100 b 2-word block transfer 0101 b 4-word block transfer 0110 b 8-word block transfer 1111 b no operation other bit combinations are reserved. fpisvm 4rh fpi bus supervisor mode status this bit indicates the state of the supervisor mode signal captured from the fpi bus signal lines when the bcu break trigger event occurred. 0 b user mode 1 b supervisor mode www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-99 v1.1, 2011-03 interrupt, v1.6 fpiack [6:5] rh fpi bus acknowledge status this bit field indicates the acknowledge signal status captured from the fpi bus signal lines when the bcu break trigger event occurred. 00 b no special case 01 b error 10 b reserved 11 b retry, slave did not respond fpirdy 7rh fpi bus ready status this bit indicates the ready signal status captured from the fpi bus signal lines when the bcu break trigger event occurred. 0 b last cycle of transfer 1 b not last cycle of transfer fpiwr 8rh fpi bus write indication status this bit indicates the write signal status captured from the fpi bus signal lines when the bcu break trigger event occurred. 0 b single write transfer or write cycle of an atomic transfer 1 b no operation or read transfer fpirst [10:9] rh fpi bus reset status this bit field indicates the reset signal status captured from the fpi bus signal lines when the bcu break trigger event occurred. 00 b reset of all fpi bus components 11 b no reset others reserved fpiops 11 rh fpi bus ocds suspend status this bit indicates the ocds suspend signal status captured from the fpi bus signal lines when the bcu break trigger event occurred. 0 b no ocds suspend request is pending 1 b an ocds suspend request is pending field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-100 v1.1, 2011-03 interrupt, v1.6 fpird 12 rh fpi bus read indication status this bit indicates the read signal status captured from the fpi bus signal lines when the bcu break trigger event occurred. 0 b single read transfer or read cycle of an atomic transfer 1 b no operation or write transfer fpiabort 13 rh fpi bus abort status this bit indicates the abort signal status captured from the fpi bus signal lines when the bcu break trigger event occurred. 0 b a transfer that has already started was aborted 1 b normal operation fpitout 14 rh fpi bus time-out status this bit indicates the time-out signal status captured from the fpi bus signal lines when the bcu break trigger event occurred. 0 b normal operation 1 b a time-out event was generated fpitag [19:16] rh fpi bus master tag status this bit field indicates the master tag captured from the fpi bus signal lines when the bcu break trigger event occurred (see table 4-17 ). the master tag identifies the master of the transfer which generated bcu break trigger event. 0 15, [31:20] rh reserved read as 0; should be written with 0. sbcu_dbdat sbcu debug data status register (050 h ) reset value: 0000 0000 h 31 0 fpidata rh field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-101 v1.1, 2011-03 interrupt, v1.6 field bits type description fpidata [31:0] rh fpi bus data status this register contains the fpi bus data that was captured when the ocds break trigger event occurred. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-102 v1.1, 2011-03 interrupt, v1.6 4.5.4.5 sbcu service request co ntrol register description in case of a bus error, the sbcu generates an interrupt request to the selected service provider (usually the cpu). this interr upt request is controlled through a standard service request control register. note: further details on interrupt handling and processing are described in the interrupt chapter of this TC1798 users manual. sbcu_src sbcu service request control register (0fc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp request is initiated sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-103 v1.1, 2011-03 interrupt, v1.6 4.6 on chip bus master tag assignments each master interface on the fpi bus and on the sri bus is assigned to a 4-bit identification number, the master tag number (see table 4-17 ). this makes it possible for software debug and mcds purposes to distinguish which master has performed the current transaction (see ?xbar_errx (x = 0-6)? on page 4-51 1) and ?sbcu_dbadrt? on page 4-97 ). 1) pls. note that the transaction id bit field in the register ?xbar_errx (x = 0-6)? on page 4-51 includes the tag id on the 4 msb (trid[3:0]). table 4-17 on chip bus master tag assignments tag-number module location description 0000 b --reserved 0001 b --reserved 0010 b pmi sri program memory interface 0011 b --reserved 0100 b dmi sri data memory interface 0101 b --reserved 0110 b --reserved 0111 b dma sri dma controller master interface on sri 1000 b sdma spb safe dma controller master interface on spb 1001 b pcp spb control processor 1010 b dma spb dma controller master interface on spb 1011 b --reserved 1100 b --reserved 1101 b --reserved 1110 b --reserved 1111 b --reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip system buses and bus bridges users manual 4-104 v1.1, 2011-03 interrupt, v1.6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-1 v1.1, 2011-03 pmu, v1.7 5 program memory unit (pmu) the program memory unit ?pmu? is part of the processor subsystem. the pmus control the flash memory and the bootrom and connect these to the sri bus system. the devices of the audomax and audo-s fa milies have at leas t one program memory unit. this is named ?pmu0?. with incr easing flash memory more pmus are added which are named ?pmu1?, and so on. all pmus are independent from each other. throughout this document a generic pmu is specified. the chapter 5.2 lists the configuration parameters of a pmu and their values in the TC1798. when pmu functionality depends on a parameter this is indicated in the text. this chapter has the following structure: ? generic feature list and block diagram ( chapter 5.1 ). ? pmu configuration of the TC1798 ( chapter 5.2 ). ? functionality of the bootrom ( chapter 5.3 ). ? functionality of the tuning protection ( chapter 5.4 ). ? functionality of the flash memory ( chapter 5.5 ). ? register set ( chapter 5.6 ). ? application hints ( chapter 5.7 ). 5.1 generic feature list a pmu has dependent on its configuration the following features: ? bootrom (?brom?). ? up to 4 mbytes of program flash (?pflash?). ? up to 256 kbyte of data flash (?dflash?). ? security flash for she (?keyflash?). ? sri slave interface for all assigned flash memories and registers. ? flash command control. ? flash and brom access control. ? tuning protection. ? interface to security module she. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-2 v1.1, 2011-03 pmu, v1.7 figure 5-1 pmu basic block diagram 5.2 pmu configuration of TC1798 the following table defines the pmu configuration of TC1798. table 5-1 configuration of pmu parameter value description n_pmu 2 number of pmus n_brom0 1 number of brom in pmu0 s_brom0 16 kbyte size of the brom in pmu0 ac_brom0 8fff c000 h base address of the brom of pmu0 (cached) an_brom0 afff c000 h base address of the brom of pmu0 (non-cached) n_pflash0 1 number of pflash in pmu0 s_pflash0 2 mbyte size of the pflash of pmu0 ac_pflash0 8000 0000 h base address of the pflash of pmu0 (cached) an_pflash0 a000 0000 h base address of the pflash of pmu0 (non-cached) pmu crossbar interconnect (sri) bootrom flash standard interface (fsi) flash array pflash dflash she keyflash www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-3 v1.1, 2011-03 pmu, v1.7 5.2.1 features of the bootrom the bootrom contains firmware: ? startup software ?ssw?: this software is executed at every reset. ? test firmware: factory test routines for ifx purposes. additionally the bootrom and its control logic support the tuning protection. an_ucb0 a000 0000 h base address of the ucb area of pmu0 (non- cached) n_dflash0 1 number of dflash in pmu0 s_dflash0 192 kbyte size of the dflash of pmu0 an_dflash0_b0 af00 0000 h base address of bank 0 of dflash of pmu0 (non- cached). s_dflash0_b0 96 kbyte size of bank 0 of dflash of pmu0. an_dflash0_b1 af08 0000 h base address of bank 1 of dflash of pmu0 (non- cached) s_dflash0_b1 96 kbyte size of bank 1 of dflash of pmu0. n_keyflash0 1 number of keyflash in pmu0 n_rdb0 3 number of pflash read buffers in pmu0 n_brom1 0 number of brom in pmu1 n_pflash1 1 number of pflash in pmu1 s_pflash1 2 mbyte size of the pflash of pmu1 ac_pflash1 8080 0000 h base address of the pflash of pmu1 (cached) an_pflash1 a080 0000 h base address of the pflash of pmu1 (non-cached) an_ucb1 a080 0000 h base address of the ucb area of pmu1 (non- cached) n_dflash1 0 number of dflash in pmu1 n_keyflash1 0 number of keyflash in pmu1 n_rdb1 3 number of pflash read buffers in pmu1 table 5-1 configuration of pmu (cont?d) parameter value description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-4 v1.1, 2011-03 pmu, v1.7 5.2.2 features of program and data flash depending on the pmu configuration the following flash features are implemented. timing and reliability figures are just indicative. binding data can be found in the ?data sheet?. program flash ?pflash? ? consists of one bank. ? commonly used for instructions and constant data. ? high throughput burst read based on a 256-bit flash access. ? application optimized sector structure with sectors ranging from 16 kbytes to 256 kbytes. ? write protection separately configurable for groups of sectors. ? hierarchical write protection control with 3 levels of which 2 are password based and 1 is a one-time programmable one. ? password based read protection combined wi th write protection for the whole flash. ? separate configuration sector containing the protection configuration and ifx specific data. ? high throughput programming of a 256 byte page (see data sheet t prp ). ? erase time per sector: see data sheet t erp . ? all flash operations initiated by co mmand sequences as protection against unintended operation. ? erase and program performed by a flash specific control logic independent of the cpu. ? end of erase and program operations reported by interrupt. ? dynamic correction of single-bit errors and detection of double-bit errors (?sec- ded?). ? error reporting by bus error, interrupts and status flags. ? ?safe read path? ensuring detection of transient and permanent errors. ? margin reads for quality assurance. ? delivery in the erased state. ? configurable wait-state configuration of optimum read performance depending on fsi frequency (see data sheet ws pf ). ? endurance and retention figures are documented in the data sheet separately for physical sectors (t ret ), logical sectors (t retl ) and ucbs (t rtu ). ? pad supply voltage used for program and erase. data flash ?dflash? as for pflash but with the following differences: ? consists of two banks. ? one sector per bank. ? commonly used for eeprom emulation (data storage at application run-time). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-5 v1.1, 2011-03 pmu, v1.7 ? burst read is not supported. ? high throughput programming of a 128 byte page (see data sheet t prd ). ? erase time per sector: see data sheet t erd . ? dynamic correction of single-bit and double-bi t errors and detection of triple-bit errors (?dec-ted?). ? the high endurance (see data sheet n e ) is granted under the condition of a robust eeprom emulation algorithm (see chapter 5.7.3 ). ? configurable wait-state configuration of optimum read performance depending on fsi frequency (see data sheet ws df ). she keyflash ? only usable by the she module (see corresponding chapter). ? the retention/endurance figure for keys is documented as t retkf in the data sheet. 5.3 bootrom the content of the brom is described in a separate chapter. the brom is readable and executable for user software but its functions shall only be executed when especially advised by ifx. all write accesses to the bootrom are refused with a bus error. in the sri address range it is mapped to the following start addresses: ? ac_brom0 (cached address range). ? an_brom0 (non-cached address range). 5.4 tuning protection the special tuning protection support represents a security function provided additionally to flash read/write/otp protection. for details on the tuning protection pleas e contact your infineon representative. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-6 v1.1, 2011-03 pmu, v1.7 5.5 flash this chapter introduces the flash memory of the TC1798. it is split into the following sections: ? definition of terms ( chapter 5.5.1 ): what means ?program ?, ?erase?, ?sector?, ?pages?, ? ? structure of a flash module ( chapter 5.5.2 ): separation into ?banks?, ?sectors?, ?word-lines?, ?pages?, ? ? reading flash ( chapter 5.5.3 ). ? command sequences for flash ( chapter 5.5.4 ): programming, erasing, handling protection. ? flash protection ( chapter 5.5.5 ): read and write protection. ? data integrity and safety ( chapter 5.5.6 ): ecc and margin checks. ? interrupt and traps ( chapter 5.5.7 ). ? reset and startup ( chapter 5.5.8 ). ? power reduction by sleep and idle ( chapter 5.5.9 ). 5.5.1 definition of terms the description of flash memories uses a specific terminology for operations and the hierarchical structure. flash operation terms ? erasing : the erased state of a flash cell is logi cal ?0?. forcing a cell to this state is called ?erasing?. depending on the flash area always complete physical sectors, logical sectors or word-lines are erased. all flash cells in this area incur one ?cycle? that counts for the ?endurance?. ? programming : the programmed state of a cell is logical ?1?. changing an erased flash cell to this state is called ?progra mming?. the 1-bits of a page are programmed concurrently. ? retention : this is the time during which the data of a flash cell can be read reliably. the retention time is a statistical figure that depends on the operating conditions of the device (e.g. temperature profile) and is affected by operations on other flash cells in the same word-line and physical sector. with an increasing number of program/erase cycles (see enduran ce) the retention is lowered. ? endurance : as described above the data retention is reduced with an increasing number of program/erase cycles. the maxi mum number of program/erase cycles of each flash cell is called ?endurance?. as said for the retention it is a statistical figure that depends on operating conditions and the use of the flash cells and not to forget on the required quality level. the endurance is documented in the data sheet separately for pflash physical sectors, pflash logical sectors, ucbs, dflash and she keys. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-7 v1.1, 2011-03 pmu, v1.7 flash structure terms ? flash module : a pmu contains one ?flash module? with its own operation control logic. ? bank : a ?flash module? contains separate ?banks?, one for pflash and two for dflash. ?banks? support concurrent opera tions (read, program, erase) with some limitations due to common logic (see chapter 5.5.4.4 ). ? physical sector : a flash ?bank? consists of ?physical sectors? ranging from 64 kbytes to 256 kbytes. the flash cells of different ?physical sectors? are isolated from each other. therefore cycling flash cell s in one physical sectors does not affect the retention of flash cells in other physical sectors. a ?physical sector? is the largest erase unit. ? logical sector : a ?logical sector? is a group of word-lines of one physical sector. they can be erased with a single operation but other flash cells in the same physical sector are slightly disturbed. ? sector : the plain term ?sector? means ?logical sector? when a physical sector is divided in such, else it means the complete physical sector. ? user configuration block ?ucb? : a ?ucb? is a specific logical sector contained in the configuration sector. it contains the protection settings and other data configured by the user. the ?ucbs? are the only part of the configuration sector that can be programmed and erased by the user. ? configuration sector : the ?configuration sector? is a separate physical sector of the pflash. because of its protection relevant c ontent it is not directly accessible to the user. ? keyflash : the keyflash is used by she for storage of keys. it is a separate range of physical sectors in the dflash bank only accessible to the she module. ? word-line : a ?word-line? consists of two pages, an even one and an odd one. in the pflash area a word-line contains aligned 512 bytes and in the dflash area 256 bytes. ? page : a ?page? is a part of a word-line that is programmed at once. in pflash a page is an aligned group of 256 bytes and in dflash 128 bytes. 5.5.2 flash structure the pmu contains the following flash banks. the offset address of each sector is relative to the base address of its bank which is given in table 5-1 . in devices of the same family the flash banks keep the same base address. derived devices (see data sheet) can have less flash memory. the pflash bank shrinks by cutting-off higher numbered physical sector s. the dflash banks shrink by reducing the size of their (single) sectors. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-8 v1.1, 2011-03 pmu, v1.7 pflash all offset addresses based on ax_pflashx (see table 5-1 ). all sectors from s9 on have a size of 256 kbyte. dflash all offset addresses are based on an_dflashx_b0 (see table 5-1 ). all offset addresses are based on an_dflashx_b1 (see table 5-1 ). table 5-2 sector structure of pflash sector phys. sector size offset address s0 ps0 16 kb 00?0000 h s1 16 kb 00?4000 h s2 16 kb 00?8000 h s3 16 kb 00?c000 h s4 ps4 16 kb 01?0000 h s5 16 kb 01?4000 h s6 16 kb 01?8000 h s7 16 kb 01?c000 h s8 ? 128 kb 02?0000 h s9 ? 256 kb 04?0000 h s10 ? 256 kb 08?0000 h s11 ? 256 kb 0c?0000 h s12 ? 256 kb 10?0000 h s13 ? 256 kb 14?0000 h s14 ? 256 kb 18?0000 h s15 ? 256 kb 1c?0000 h table 5-3 sector structure of dflash bank 0 sector size offset address ds0 s_dflashx_b0 00?0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-9 v1.1, 2011-03 pmu, v1.7 the dflash contains also the she keyflash. it can be only used by the she module. ucb all offset addresses are based on an_ucbx (see table 5-1 ). as explained before the ucbx are logical sectors. 5.5.3 flash read access flash banks that are active and in read mode can be directly read as rom. the wait cycles for the flash access must be configured as defined in the data sheet or in the chapter ?electrical parameters?. the pflash allows sri bursts btr4 and btr2 and single transfers. the tricore uses btr4 for code fetches from the cached address range in order to fill one cache line. code fetches from the non-cached area are also performed with btr4. data reads from the cached range are performed with btr4. data reads from the non- cached address range are performed with single transfers. the dflash allows only single transfers. therefore they are only accessible in the non- cached address range and tricore can? t fetch instructions from them. read accesses from flash can be blo cked by the read protection (see chapter 5.5.5 ). read accesses to the dflash can be blocked by she operations (see chapter 5.5.4.4 and sema on page 5-49 ). ecc errors can be detected and corrected (see chapter 5.5.6 ). read buffers the pmu contains n_rdbx read buffers. each of these read buffers is assigned by configuration (see chapter 5.6.2.3 ) to one bus master. additionally all read data passes table 5-4 sector structure of dflash bank 1 sector size offset address ds1 s_dflashx_b1 00?0000 h table 5-5 structure of ucb area sector size offset address ucb0 1 kb 00?0000 h ucb1 1 kb 00?0400 h ucb2 1 kb 00?0800 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-10 v1.1, 2011-03 pmu, v1.7 through a pipeline stage in the fsi called ?global read buffer?. the read buffers can be filled with a single pflash read which delivers 256 data bits. read accesses to the dflash are always serv iced by reading the flash. buffer hits are not supported. 5.5.4 flash operations the flash memory knows operations for reading, changing data (program/erase) and handling protection settings. this section and the following describe only the features as such. how to use them is described in the application notes ( chapter 5.7 ). 5.5.4.1 modes of operation a flash module can be in one of the following states: ? active (normal) mode. ? sleep mode (see chapter 5.5.8 ). in sleep mode write and read accesses to all flash ranges of this pmu are refused with a bus error. when the flash module is in normal mode each flash bank can be separately in one of these modes: ? read mode. ? command mode. in read mode a flash bank can be read and command sequences are interpreted. in read mode a flash bank can additionally enter page mode which enables it to receive data for programming. in command mode an operation is performed. during its execution the flash bank reports busy in fsr. in this mode read accesses to this flash bank are refused with a bus error. at the end of an operation the flash bank returns to read mode and busy is cleared. only operations with a signi ficant duration (shown in the command documentation) set busy. register read and write accesses are not affected by these modes. 5.5.4.2 command sequences all flash operations except read are performed with command sequences. when a flash bank is in read mode or page mode all write accesses to its reserved address range are interpreted as command cycle belonging to a command sequence. write accesses to a busy bank cause sqer. command sequences consist of 1 to 6 command cycles. the command interpreter checks that a command cycle is correct in t he current state of co mmand interpretation. else a sqer is reported. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-11 v1.1, 2011-03 pmu, v1.7 when the command sequence is accepted the last command cycle finishes read mode and the flash bank transitions into command mode. these write accesses must be single transfers (thus they should address the non- cached address range). all write accesses transferring write data shall address the flash bank that will execute the program operation. this flash bank must be in page mode. all write accesses of one command sequence must address the same flash bank. command sequences can be blocked by the flash reservation semaphore (see chapter 5.5.4.4 and sema on page 5-49 ). generally when the command interpreter detects an error it reports a sequence error by setting fsr.sqer. then the command interpreter is reset and a page mode is left. the next command cycle must be the 1st cycle of a command sequence. the only exception is ?enter page mode? when a bank is already in page mode (see below). 5.5.4.3 command sequence definitions the command sequence descriptions use the following nomenclature (symbolic assembly language): st addr, data : symbolic representation of a co mmand cycle moving ?data? to ?addr?. the parameter ?addr? can be one of the following: ? cccc h : the ?addr? must point into the bank that performs the operation. the last 16 address bits must match cccc h . it is recommended to use as address the base address of the bank incremented by cccc h . ? pa : absolute start address of the flash page. ? ucpa : absolute start address of a user configuration block page. ? sa : absolute start address of a flash sector. allowed are the pflash sectors sx. ? psa : absolute start address of a physical se ctor. allowed are the pflash physical sectors psx and the dflash sectors dsx. ? ucba : absolute start address of a user configuration block. the parameter ?data? can be one of the following: ? wd : 64-bit or 32-bit write data to be loaded into the page assembly buffer. ? xxyy : 8-bit write data as part of a comma nd cycle. only the byte ?yy? is used for command interpretation. the higher order bytes ?xx? are ignored. ? xx5y : specific case for ?yy?. the ?y? can be ?0 h ? for selecting the pflash bank or ?d h ? to select the dflash banks. ? ul : user protection level (xxx0 h or xxx1 h for user levels 0 and 1). ? pwx : 32-bit password. when using for command cycles 64-bit transfers the ?data? is expected in the correct 32- bit word as indicated by the address ?addr?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-12 v1.1, 2011-03 pmu, v1.7 command sequence overview table the table 5-6 summarizes all commands sequences. the following sections describe each command sequence in detail. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-13 v1.1, 2011-03 pmu, v1.7 reset to read calling: ? st 5554 h , xxf0 h function: this function resets the command interpreter to its initial state (i.e. the next command cycle must be the 1st cycle of a sequence). a page mode is aborted. this command is the only that is accepted without sqer when the command interpreter has already received command cycles of a different sequence but is still not in command table 5-6 command sequences for flash control command sequence 1. cycle 2. cycle 3. cycle 4. cycle 5. cycle 6. cycle reset to read address data .5554 ..xx f0 enter page mode address data .5554 ..xx 5y load page address data .55f0 wd write page address data .5554 ..xx aa .aaa8 ..xx 55 .5554 ..xx a0 pa ..xx aa write uc page address data .5554 ..xx aa .aaa8 ..xx 55 .5554 ..xx c0 ucpa ..xx aa erase sector address data .5554 ..xx aa .aaa8 ..xx 55 .5554 ..xx 80 .5554 ..xx aa .aaa8 ..xx 55 sa ..xx 30 erase phys sector address data .5554 ..xx aa .aaa8 ..xx 55 .5554 ..xx 80 .5554 ..xx aa .aaa8 ..xx 55 sa ..xx 40 erase uc block address data .5554 ..xx aa .aaa8 ..xx 55 .5554 ..xx 80 .5554 ..xx aa .aaa8 ..xx 55 ucba ..xx c0 disable write protection address data .5554 ..xx aa .aaa8 ..xx 55 .553c ul .aaa8 pw 0 .aaa8 pw 1 .5558 ..xx 05 disable read protection address data .5554 ..xx aa .aaa8 ..xx 55 .553c ..xx 00 .aaa8 pw 0 .aaa8 pw 1 .5558 ..xx 08 resume protection address data .5554 ..xx 5e clear status address data .5554 ..xx f5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-14 v1.1, 2011-03 pmu, v1.7 mode. thus ?reset to read? can cancel every command sequence before its last command cycle has been received. the error flags of fsr (pfoper, dfoper, sqer, proer, dfsber, dfcber, pfdber, pfmber, orier, ver) and the xfsr are cleared. the flags can be also cleared in the status registers without command sequence. if any flash bank is busy this command is executed but the flag sqer is set. enter page mode calling: ? st 5554 h , xx5y h function: the pflash or the addressed dflash bank enter page mode. the selection of the pflash assembly buffer (256 bytes) or the dflash assembly buffer (128 bytes) is additionally done by the parameter ?y h ?. the write pointer of the page assembly buffer is set to 0, its previous content is maintained. the page mode is signalled by the flag pagex in the fsr separately for pflash and dflash. if a new ?enter page mode? command s equence is received while any flash bank is already in page mode sqer is set but this sequence is correctly executed (i.e. in this case the command interpreter is not reset). load page calling: ? st 55f0 h , wd (note: offset 55f4 h is used for the higher order 32-bit transfers). function: loads the data ?wd? into the page assembly buffer and increments the write pointer to the next position 1) . all wd transfers for one page must have the same width (either all 32-bit or all 64-bit). else the transfer is refused with sqer. the addressed bank must be in page mode, else sqer is issued. if ?load page? is called more often than necessary for filling the page sqer is issued and if configured an interrupt is triggered . the overflow data is discarded. the page mode is not left. 1) more specifically: after ?load page? has transferred 64 bits (i.e. two command with 32-bit wd or one command with one 64-bit wd) the ecc is calculated and the result is transferred to the assembly buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-15 v1.1, 2011-03 pmu, v1.7 write page calling: ? st 5554 h , xxaa h ? st aaa8 h , xx55 h ? st 5554 h , xxa0 h ? st pa, xxaa h function: this function starts the programming process for one page with the data transferred previously by ?load page? commands. upon entering command mode the page mode is finished (indicated by clearing the corresponding page flag) and the busy flag of the bank is set. this command is refused wi th sqer when the addressed flash bank is not in page mode. sqer is also issued when pa addresses an unavailable flash range or when pa does not point to a legal page start address. if after ?enter page mode? too few data or no data was transferred to the assembly buffer with ?load page? then ?write page? progra ms the page but sets sqer. the missing data is programmed with the previous content of the assembly buffer. when the page ?pa? is located in a sector with active write protection or the flash module has an active global read protection the execution fails and proer is set. write user configuration page calling: ? st 5554 h , xxaa h ? st aaa8 h , xx55 h ? st 5554 h , xxc0 h ? st ucpa, xxaa h function: as for ?write page?, except that the page ?ucpa? is located in a user configuration block. this changes the flash module?s protection configuration. when the page ?ucpa? is located in an ucb wi th active write protection or the flash module has an active global read protecti on the execution fails and proer is set. when ucpa is not the start address of a page in a valid ucb the command fails with sqer. erase sector calling: ? st 5554 h , xxaa h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-16 v1.1, 2011-03 pmu, v1.7 ? st aaa8 h , xx55 h ? st 5554 h , xx80 h ? st 5554 h , xxaa h ? st aaa8 h , xx55 h ? st sa, xx30 h function: the sector ?sa? is erased. sqer is returned when sa does not point to the base address of a correct sector (as specified at the beginning of this se ction) or to an unavailable sector. when sa has an active write protection or the flash module has an active global read protection the execution fails and proer is set. erase physical sector calling: ? st 5554 h , xxaa h ? st aaa8 h , xx55 h ? st 5554 h , xx80 h ? st 5554 h , xxaa h ? st aaa8 h , xx55 h ? st psa, xx40 h function: the physical sector ?psa? is erased. sqer is returned when psa does not point to the base addr ess of a correct sector (as specified at the beginning of this section) or an unavailable sector. when psa has an active write prot ection or the flash module has an active global read protection the execution fails and proer is set. erase user configuration block calling: ? st 5554 h , xxaa h ? st aaa8 h , xx55 h ? st 5554 h , xx80 h ? st 5554 h , xxaa h ? st aaa8 h , xx55 h ? st ucba, xxc0 h function: the addressed user configurat ion block ?ucb? is erased. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-17 v1.1, 2011-03 pmu, v1.7 when the ucb has an active write protection or the flash module has an active global read protection the execution fails and proer is set. the command fails with sqer when ucba is not the start address of a valid ucb. disable sector write protection calling: ? st 5554 h , xxaa h ? st aaa8 h , xx55 h ? st 553c h , ul ? st aaa8 h , pw0 ? st aaa8 h , pw1 ? st 5558 h , xx05 h function: the sector write protection belonging to user le vel ?ul? is temporarily disabled by setting fsr.wprodis when the passwords pw0 and pw1 match their configured values in the corresponding ucb. the command fails by setting proer when any of pw0 and pw1 does not match. in this case until the next application reset all further calls of ?disable sector write protection? and ?disable read protection? fa il with proer independent of the supplied password. disable read protection calling: ? st 5554 h , xxaa h ? st aaa8 h , xx55 h ? st 553c h , xx00 h ? st aaa8 h , pw0 ? st aaa8 h , pw1 ? st 5558 h , xx08 h function: the flash module read protection including th e derived module wide write protection are temporarily disabled by setting fsr.rprodis when the passwords pw0 and pw1 match their configured values in the ucb0. the command fails by setting proer when any of pw0 and pw1 does not match. in this case until the next application reset all further calls of ?disable sector write protection? and ?disable read protection? fa il with proer independent of the supplied password. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-18 v1.1, 2011-03 pmu, v1.7 resume protection calling: ? st 5554 h , xx5e h function: this command clears all fsr.wprodisx and the fsr.rprodis effectively enabling again the flash protection as it was configured. a fsr.wprodisx is not cleared when corresponding ucbx is not in the ?confirmed? state (see chapter 5.5.5.3 ). clear status calling: ? st 5554 h , xxf5 h function: the flags fsr.prog and fsr.erase and the error flags of fsr (pfoper, dfoper, sqer, proer, dfsber, dfcber, pf dber, pfmber, orier, ver) and xfsr are cleared. these flags can be also cleared in the status registers without command sequence. when any flash bank is busy this command fails by setting additionally sqer. 5.5.4.4 concurrent operations each pmu of a device is independent of the other. therefore they can be operated concurrently without limitation. thus also flash operations in different pmus can be performed concurrently. the flash banks of one flash module use common resources in flash and in the pmu. therefore the concurrent operations are restricted. these are the general rules: ? when the pflash is not busy reads of all not-busy banks are allowed. this includes margin reads ( chapter 5.5.6.2 ). ? when the pflash is busy read accesses to dflash banks shall not be performed but do not cause a bus error. ? read accesses to busy banks return generally a bus error. ? when any flash bank is busy with programming the command sequence ?enter page mode? must not be executed. the results are unpredictable. thus at most one programming process can be active. the following table shows an overview of the allowed combinations. it uses the abbreviations: ? r: read. including margin reads (see chapter 5.5.6.2 ). ? p: program. ? e: erase. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-19 v1.1, 2011-03 pmu, v1.7 ? she: dflash reserved for the she module. a ?/? indicates that both operations are allowed and ??? that no operation is allowed. please note that even if a table row contains more than one ?r? the pmu performs only one flash read access at a time. the table indicates which reads are possible. in all other cases not contained in the table command sequences are forbidden when any flash bank is busy. this is not automatically prevented by hardware! the ?erase suspend? feature: for eeprom emulation ?enter page mode?, ?load page? and ?write page? are accepted for a dflash page when the other dflash bank is busy with an erase operation. suspending the erase operation does typically not exceed t fl_ersusp . after that the programming is performed and finally the erase operation is automatically resumed. the ?delayed erase? feature: when on one dflash bank a programming is ongoing an ?erase sector? or ?erase physical sector? sequence is accepted by the pmu. it sets immediately busy but internally the executi on of the erase process starts after the programming has finished. 5.5.5 flash protection the flash memory can be read and write prot ected. the protection is configured by programming the user c onfiguration blocks ?ucb?. advice how to use the flash protection can be found in chapter 5.7.5 . this chapter contains only the terse facts. the she module offers a separate possibility to protect flash content from unauthorized modification or use. table 5-7 concurrent flash processes pflash dflash0 dflash1 comment rrr p/e ? ? read of dflash not supported but does not return a bus error. rp/er rrp/e r p e when erase started first: ?erase suspend?, when program started first: ?delayed erase?. rep r she she reserves complete dflash and prohibits all command sequences. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-20 v1.1, 2011-03 pmu, v1.7 5.5.5.1 effective flash read protection the effectiveness of flash read protection is selected per master. a read access to pflash or dflash fails with bus error under the following conditions: ? tricore pmi (code fetch): fcon.dcf and fcon.rpa. ? tricore dmi (data read): fcon.ddf and fcon.rpa. ? dma, sdma and their submasters: (fcon.ddf and fcon.rpa) or fcon.ddfdma. ? pcp: (fcon.ddf and fcon.rpa) or fcon.ddfpcp. ? she: (fcon.ddf and fcon.rpa) or fcon.ddfshe. the read protection bit fcon.rpa is determined during startup by the protection configuration of ucb0. it can be tem porarily modified by the command sequences ?disable read protection? and ?resume protection? which modify fsr.rprodis. fcon.rpa is determined by the following equation: ? fcon.rpa = procon0.rpro and not fsr.rprodis. the she module has always fu ll access to its keyflash. the bits fcon.ddfx and fcon.dcfx are initialized by the startup software depending on the configured protection and the startup mode. they can also be directly modified by the user software under conditions noted in the description of fcon . 5.5.5.2 effective flash write protection a range of flash can be write protected by several means: ? the complete pflash and optionally the complete dflash can be write protected by the read protection. ? groups of sectors of pflash can be write-protected by three different ?users?, i.e. ucbs: ? ucb0: write protection that can be disabled with the password of ucb0. ? ucb1: write protection that can be disabled with the password of ucb1. ? ucb2: write protection that can not be disabled anymore (rom or otp function: ?one-time programmable?). the write protection is effective independent of the master. an active write protection causes the pr ogram and erase command sequences to fail with a proer. this was described in the command sequence documentation ( chapter 5.5.4.3 ). a range ?x? (i.e. a group of sectors, see procon0 ) of the pflash is write protected if any of the following conditions is true: ? fcon.rpa ? procon2.sxrom ? procon0.sxl and not(fsr.wprodis0) ? procon1.sxl and not(procon0.sxl) and not(fsr.wprodis1) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-21 v1.1, 2011-03 pmu, v1.7 thus with the password of ucb0 the write protection of sectors protected by user 0 and user 1 can be disabled, however with the password of ucb1 only those sectors that are only protected by user 1. the write protec tion of user 2 (otp) can be obviously not disabled. the global write protection caused by the read protection can be disabled as described above by using the password of ucb0 to disable the read protection. the dflash is write protected if any of the following conditions is true: ? fcon.rpa and not(p rocon0.dfexpro). thus the dfexpro bit can be used to excl ude the dflash from an otherwise global write protection. 5.5.5.3 configuring flash protection in the ucb as indicated above the effective protection is determined by the content of the procon0?2 registers. these are loaded dur ing startup from the ucb0?2. each ucb comprises 1 kbyte of flash organized in 4 uc pages of 256 bytes. the ucbs have the following structure: if the confirmation code field is programmed with 8afe 15c3 h the ucb content is ?confirmed? otherwise it is ?unconfirmed?. the status flags fsr.proin, fsr.rproin and fsr.wproin0?2 indicate this confirmation state: table 5-8 ucb content uc page bytes ucb0 ucb1 ucb2 0 0?3 procon0 procon1 procon2 4?7 sheboot0 sh eboot1 sheboot2 8?11 procon0 (copy) procon1 (copy) procon2 (copy) 12?15 sheboot0 (copy) shebo ot1 (copy) sheboot2 (copy) 16?19 pw0 of user 0 pw0 of user 1 unused 20?23 pw1 of user 0 pw1 of user 1 unused 24?27 pw0 of user 0 (copy) pw0 of user 1 (copy) unused 28?31 pw1 of user 0 (copy) pw1 of user 1 (copy) unused 1 unused unused unused unused 2 0?3 confirmation code confirmation code confirmation code 8?11 confirmation code (copy) confirmation code (copy) confirmation code (copy) other unused unused unused 3 unused unused unused unused www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-22 v1.1, 2011-03 pmu, v1.7 ? fsr.proin: set when any ucb is in the confirmed state. ? fsr.rproin: set when procon0.rpro is ?1? and the ucb0 is in ?confirmed? state. ? fsr.wproin0?2: set when their ucb0?2 is in ?confirmed? state. an ucb can be erased with the command ?erase user configuration block?. an ucb page can be programmed with the command ?wri te user configuration page?. these commands fail with proer when the ucb is write-protected. an ucb is write-protected if: ? ucb0: (fsr.rproin and not fsr.rprodis) or (fsr.wproin0 and not fsr.wprodis0) ? ucb1: fsr.wproin1 and not fsr.wprodis1. ? ucb2: fsr.wproin2 so when the ucb2 is in the ?confirmed? state its protection can not be changed anymore. therefore this realizes a one- time programmable protection. 5.5.5.4 system wide effects of flash protection an active flash read protection needs to be respected in the complete system. the ssw checks if the flash read protecti on is active in any pmu, if yes: ? if the selected boot mode executes from internal pflash. ? the ssw clears the dcf, ddf and the ddfx. ? the ssw leaves the debug interface locked (ostate.if_lck stays 1). ? if the selected boot mode does not execute from internal pflash: ? the ssw either leaves dcf and ddf set or actively sets them again in each pmu after evaluating the configuration sector. ? additionally the master individual ddfx flags (ddfdma, ddfpcp, and ddfshe) are set. ? the debug interface is unlocked. if the read protection is inactive in all pmus the dcf, ddf and ddfx flags are cleared by the ssw and the debug interface is unlocked. only depending on the flash read protection of pmu0 are: ? if the read protection of pmu0 is active the cpu allows only one write access to pmi_con2 effectively allowing only one instruction cache configuration change. the field pc of the register smacon which affects the instruction cache is ignored and the value 00 b is used. full flash analysis of an far device is only possible when the customer has removed all installed protections or delivers the necessary passwords with the device. as the removal of an otp protection in ucb2 is not possible the otp protection inevitably limits analysis capabilities. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-23 v1.1, 2011-03 pmu, v1.7 5.5.6 data integrity and safety the data in flash is stored with error correct ing codes ?ecc? in order to protect against data corruption. the healthiness of flash data can be checked with margin checks. 5.5.6.1 ecc the data in flash is stored with ecc codes. these are automatically generated when the data is programmed. when data is r ead these codes are evaluated. depending on the flash bank different algorithms with different error correction capabilities are used: ? data in pflash uses an ecc code with sec-ded (single error correction, double error detection) capabilities. each block of 64 data bits is accompanied with 8 ecc bits. two different algorithms can be selected: ? standard ecc as used in previous product generations (default). ? ?safety ecc? or ?address ecc?: this al gorithm calculates the ecc not only over the data bits but additionally over address bits. ? data in dflash uses an ecc code with dec-ted (double error correction, triple error detection) capabilities. each block of 64 data bits is accompanied with 16 ecc bits. the selection of the standard pflash ecc or the ?address ecc? for generation and evaluation is done by the register bit fcon.a ddecc. this is set by the startup software depending on the procon0.addecc but can also be modified by software. standard pflash ecc in the standard pflash ecc the 8-bit ecc value is calculated over 64 data bits. an erased data block (all bits ?0?) has an ecc value of 00 h . therefore an erased sector is free of ecc errors. a data block with all bits ?1? has an ecc value of ff h . the ecc is automatically generated when pr ogramming the pflash when this is not disabled with eccw.pecencdis. the ecc is automatically evaluated when reading data. this algorithm has t he following capabilities: ? single-bit error: ? is noted in fsr.pfsber. ? data and ecc value are corrected if this is not disabled with eccr.pecdecdis. ? interrupt is triggered if enabled with fcon.pfsberm. ? double-bit error: ? is noted in fsr.pfdber. ? is noted in xfsr.pfdber. ? causes a bus error if not disabled by marp.trapdis. ? interrupt is triggered if enabled with fcon.pfdberm. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-24 v1.1, 2011-03 pmu, v1.7 address errors are not detected. safety pflash ecc the standard ecc can not detect addressing errors, i.e. delivery of a correct data block from an incorrect address. the sri bus ensures that addressing errors are detected between master and pmu. but addressing errors in the pmu and flash can not be detected. this missing capability is added by the ?address ecc?. an 8-bit ecc value is calculated over 64 data bit and the address bits 23:3. the detection and correction features of t he standard ecc are kept as described above. additionally the pmu can detect single-bit address corruptions: ? it is noted in fsr.pfdber 1) . ? it is noted in xfsr.pfader. ? causes a bus error if not disabled by marp.trapdis. ? interrupt is triggered if enabled with fcon.pfdberm. as side effect of this ecc algorithm an erased sector (containing 0 data and 0 ecc) can not be read without detecting ecc errors. thus when this algorithm is enabled data must be programmed before the flash range may be read. dflash ecc in the dflash a 16-bit ecc value is calculat ed over 64 data bits. an erased data block has an ecc value 0000 h . therefore an erased sector is free of ecc errors. a data block with all bits ?1? has an ecc value of ffff h . the algorithm has the following capabilities: ? single-bit error and double-bit error: ? is noted in fsr.dfcber. ? data and ecc value are corrected if this is not disabled with eccr.decdecdis. ? interrupt is triggered if enabled with fcon.dfcberm. ? triple-bit error: ? is noted in fsr.dfmber. ? causes a bus error if not disabled by mard.trapdis. ? interrupt is triggered if enabled with fcon.dfmberm. address errors are not detected. 5.5.6.2 margin checks the flash memory offers a ?margin check feat ure?: the limit which defines if a flash cell is read as logic ?0? or logic ?1? can be shifted. this is controlled by the registers marp and mard . 1) this bit is set because it is used in the fsr to notify uncorrectable errors. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-25 v1.1, 2011-03 pmu, v1.7 the margin selection of pflash and dflash is independent. the margin selected with mard is effective for the complete dflash. after changing the read margin at least t fl_margindel have to be waited before reading the affected flash module. 5.5.7 interrupts and traps generally the pmu reports fatal errors by issuing a bus error which is translated by the cpu into a trap (pmi sets pse trap and dmi the dse trap). this is a list of conditions for reporting a bus error: ? uncorrectable ecc error (if not disabled by marp or mard). ? write access to read-only register. ? not allowed write access to protected register (e.g. sv or endinit). ? not allowed flash read access with active read protection. ? read access to not available flash memory. ? read-modify-write access to the flash memory. ? read accesses to a busy flash bank. ? read accesses to a flash bank reserved by she. furthermore selected events can trigger interrupts. the service request node is documented in the scu. it is controlled by the scu registers intset, intclr, intdis, intnp, and intstat. the selection of the events for interrupt triggering is done by fcon . the following events can trigger an interrupt when enabled: ? end of busy: any transition of any of pbusy, d0busy or d1busy from ?1? to ?0? triggers the interrupt (program and erase sequences, wake-up). ? operational error: see oper flag. ? verify error: see ver flag. ? protection error: see proer flag. ? sequence error: see sqer flag. ? correctable bit-error: read access delivered corrected data. ? uncorrectable bit-error: read access had an uncorrectable bit error. the event that triggered the interrupt can be determined from the fsr register. an interrupt event it also triggered when the event appears again and the corresponding status flag is still set. 5.5.8 reset and startup all pmu and flash functionality is reset with the application reset with the exception of the register bits: fsr.prog, fsr.erase, fsr.pfoper, fsr.dfoper. these bits are reset with the power-on reset. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-26 v1.1, 2011-03 pmu, v1.7 during flash startup the logical sectors are checked for an over-erased state (caused by an aborted sector erase) which could prevent read access to all logical sectors of the same physical sector. this feature is configured with procon1 and further described in chapter 5.7.8.3 . during startup after each reset the protection setting is installed from the ucbs. if a protection field has a double-bit error its copy is used. this is indicated by setting fsr.orier. if a copy has also a double-bit error the startup software does not enter the user code. 5.5.9 power reduction the flash module can enter sleep mode to reduce its power consumption. the sleep request can have two sources: ? global sleep mode requested by the scu (see ?power management?). only executed by the flash when fcon.esldis = 0. ? programming ?1? to the bit fcon.sleep. after receiving a sleep request the flash starts the ramp down when the flash becomes idle, i.e. none of the banks is in command mode and no reads are executed anymore. an ongoing read burst is finished completely. during ramp down to sleep mode all fsr.busyx are set. the sleep mode is indicated in fsr.slm. the fsr.busyx stay set. the flash module can be woken up by releasing the sleep request. it enters read mode again after t wu . during the wake-up phase the fsr.busyx are set. note: it is not recommended to use the scu controlled sleep mode with fcon.esldis = 0. because software had to ensure that upon wake-up the flash is only read after it has returned to read mode. ear lier reads cause bus errors! therefore the reset value of fcon.esldis is 1. note: requesting sleep mode does not disabl e automatically an enabled end-of-busy interrupt. when requesting sleep mode during an ongoing flash operation with enabled end-of-busy interrupt, the operation finishes, the interrupt is issued and then the flash enters sleep mode. however this end-of-busy interrupt will wake- up the cpu again. an additional power reduction feature is enabled by setting fcon.idle. in this case the pflash read path is switched off when no read access is pending and the read buffers are filled. system performanc e is slightly reduced becaus e a flash line hit can not be exploited. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-27 v1.1, 2011-03 pmu, v1.7 5.6 register set the register set consists of some gener al pmu registers which are partly only implemented for pmu0 because they control its specific functionality ( chapter 5.6.1 ). the other registers control flash functionality ( chapter 5.6.2 ). register fields related to dflash, keyflash and she are implemen ted also when these flash banks or functionalities are not available but they are without function. the register access conditions use the following abbreviations: ? ?u?: access permitted in user mode 0 or 1 (applicable to write and read). ? ?sv?: access permitted in supervisor mode (applicable to write and read). ? ?e?: endinit protected write. ?e? means a write access is only allowed before endinit or after disabling this protection with a password as described in the scu chapter. ? ??? or ?be?: access not permitted. the pmu and flash use the following combinations (see table 5-10 and table 5-12 ): ? u, sv: access always allowed (i.e. in user mode or supervisor mode). ? be: access never allowed, causing a bus error. ? sv, e: access only in supervisor mode with disabled endinit protection. all accesses prevented due to these restrictions fail with a bus error. also accesses to unoccupi ed register addresses fail with a bus error. note: it is convention to use short register names (e.g. ?fcon?) in the chapter that defines these register s. in all other chapters and in the development tools long register names are used that are a conc atenation of the module instance (e.g. ?pmu0? or ?flash0?), an underscore and the short register name, i.e. ?flash0_fcon?. this document uses for clarification also mostly the long names. 5.6.1 pmu registers non-flash related registers for the pmu. they have the prefix ?pmux_?. table 5-9 registers address space module base address end address note pmu0 f800 0500 h f800 052b h pmu1 f800 0600 h f800 062b h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-28 v1.1, 2011-03 pmu, v1.7 5.6.1.1 pmu identification the pmu_id register identifies the pmu and its version. table 5-10 registers overview short name description offset addr. 1) 1) the absolute register address is calculated as follows: module base address ( table 5-9 ) + offset address (shown in this column) access mode reset class page number read write id module identification 08 h u, sv be 3 5-28 pmu0_id pmu0 identification register (f800 0508 h ) reset value: 0081 c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number mod_rev defines the module revision number. the value of a module revision starts with 01 h (first rev.). mod_type [15:8] r module type this bit field is c0 h . it defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines the module identification number for pmu0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-29 v1.1, 2011-03 pmu, v1.7 pmu1_id pmu1 identification register (f800 0608 h ) reset value: 0082 c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number mod_rev defines the module revision number. the value of a module revision starts with 01 h (first rev.). mod_type [15:8] r module type this bit field is c0 h . it defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines the module identification number for pmu1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-30 v1.1, 2011-03 pmu, v1.7 5.6.2 flash registers the absolute address of a flash register is calculated by the base address from table 5-11 plus the offset address of this register from table 5-12 . table 5-11 registers address space module base address end address note flash0 f800 1000 h f800 23ff h flash registers of pmu0 flash1 f800 3000 h f800 43ff h flash registers of pmu1 table 5-12 registers overview short name description offset addr. 1) access mode reset class page number read write id flash module identification register 1008 h u, sv be 3 5-47 fsr flash status register 1010 h u, sv u, sv 3 2) 5-32 fcon flash configuration register 1014 h u, sv sv, e 3 5-41 marp margin control register pflash 1018 h u, sv sv, e 3 5-50 mard margin control register dflash 101c h u, sv u, sv 3 5-51 procon0 flash protection config. user 0 1020 h u, sv be 3 5-52 procon1 flash protection config. user 1 1024 h u, sv be 3 5-55 procon2 flash protection config. user 2 1028 h u, sv be 3 5-58 xfsr extended flash status register 102c h u, sv u, sv 3 5-39 sema flash access semaphore 1030 h u, sv u, sv 3 5-49 sheboot0 she secure boot configuration 0 1034 h u, sv be 3 5-62 sheboot1 she secure boot configuration 1 1038 h u, sv be 3 5-62 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-31 v1.1, 2011-03 pmu, v1.7 5.6.2.1 flash status the flash status register fsr reflects the overall status of the flash module after reset and after reception of the different commands. the error flags and the two status flags (prog, erase) are affected by the ?clear status? command. the error flags are also cl eared with the ?reset to read? command. some error flags are marked as writable. these flags can be cleared by writing a ?1? to this bit. sheboot2 she secure boot configuration 2 103c h u, sv be 3 5-62 rdbcfg0 read buffer configuration 0 1040 h u, sv sv, e 3 5-46 rdbcfg1 read buffer configuration 1 1044 h u, sv sv, e 3 5-46 rdbcfg2 read buffer configuration 2 1048 h u, sv sv, e 3 5-46 eccw ecc write register 10e0 h u, sv sv, e 3 5-60 eccr ecc read register 10e4 h u, sv sv, e 3 5-61 1) the absolute register address is calculated as follows: module base address ( table 5-11 ) + offset address (shown in this column) 2) some bits are not reset with the application reset but only with the power-on reset. table 5-12 registers overview (cont?d) short name description offset addr. 1) access mode reset class page number read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-32 v1.1, 2011-03 pmu, v1.7 flash status register fsr flash status register (1010 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ver ori er 0slm0 w pro dis1 w pro dis0 0 w pro in2 w pro in1 w pro in0 0 r pro dis r pro in 0 pro in rwh rh r rh r rh rh r rh rh rh r rh rh r rh 1514131211109876543210 df mb er pf db er df cb er pf sb er pro er sq er df op er pf op er df pag e pf pag e era se pro g d1 bus y d0 bus y fa bus y p bus y rwh rwh rwh rwh rwh rwh rwh rwh rh rh rwh rwh rh rh rh rh field bits type description pbusy 0rh program flash busy 1) hw-controlled status flag. 0 b pflash ready, not busy; pflash in read mode. 1 b pflash busy; pflash not in read mode. indication of busy state of pflash because of active execution of program or erase operation; pflash busy state is also indicated during flash startup after reset or in sleep mode; while in busy state, the pflash is not in read mode. fabusy 1rh flash array busy 1) internal busy flag for testing purposes. must be ignored by application software. this may only use pbusy, d0busy and d1busy. d0busy 2rh data flash bank 0 busy 1) hw-controlled status flag. 0 b dflash0 ready, not busy; dflash0 in read mode. 1 b dflash0 busy; dflash0 not in read mode. indication of busy state of dflash bank 0 because of active execution of program or erase operation; dflash0 busy state is also indicated during flash startup after reset or in sleep mode; while in busy state the dflash0 is not in read mode. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-33 v1.1, 2011-03 pmu, v1.7 d1busy 3rh data flash bank 1 busy 1) hw-controlled status flag. 0 b dflash1 ready, not busy; dflash1 in read mode. 1 b dflash1 busy; dflash1 not in read mode. indication of busy state of dflash bank 1 because of active execution of program or erase operation; dflash1 busy state is also indicated during flash startup after reset or in sleep mode; while in busy state the dflash0 is not in read mode. prog 4rwh programming state 2)3) hw-controlled status flag. 0 b there is no program operation requested or in progress or just finished. 1 b programming operation (write page) requested (from fim) or in action or finished. set with last cycle of write page command sequence, cleared with clear status command (if not busy) or with power-on reset. if one busy flag is coincidently set, prog indicates the type of busy state. if xoper is coincide ntly set, prog indicates the type of erroneous operation. otherwise, prog indicates, that operation is still requested or finished. can be also cleared by writing ?1? to it. erase 5rwh erase state 2)3) hw-controlled status flag. 0 b there is no erase operation requested or in progress or just finished 1 b erase operation requested (from fim) or in action or finished. set with last cycle of erase command sequence, cleared with clear status command (if not busy) or with power-on reset. indications are analogous to prog flag. can be also cleared by writing ?1? to it. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-34 v1.1, 2011-03 pmu, v1.7 pfpage 6rh program flash in page mode 1)4) hw-controlled status flag. 0 b program flash not in page mode 1 b program flash in page mode; assembly buffer of pflash (256 byte) is in use (being filled up) set with enter page mode for pflash, cleared with write page command note: concurrent page and read modes are allowed dfpage 7rh data flash in page mode 1)4) hw-controlled status flag. 0 b data flash not in page mode 1 b data flash in page mode; assembly buffer of dflash (128 byte) is in use (being filled up) set with enter page mode for dflash, cleared with write page command. note: concurrent page and read modes are allowed pfoper 8rwh program flash operation error 2)3)4) 0 b no operation error reported by program flash 1 b flash array operation aborted, because of a flash array failure, e.g. an ecc error in microcode. this bit is not cleared with application reset, but with power-on reset. registered status bit; must be cleared per command or by writing ?1?. dfoper 9rwh data flash operation error 2)3)4) function analogous to program flash oper sqer 10 rwh command sequence error 1)2)4) 0 b no sequence error 1 b command state machine operation unsuccessful because of improper address or command sequence. a sequence error is not indicated if the reset to read command aborts a command sequence. registered status bit; must be cleared per command or by writing ?1?. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-35 v1.1, 2011-03 pmu, v1.7 proer 11 rwh protection error 1)2)4) 0 b no protection error 1 b protection error. a protection error is reported e.g. because of a not allowed command, for example an erase or write page command addressing a locked sector, or because of wrong password(s) in a protected command sequence such as ?disable read protection? registered status bit; must be cleared per command or by writing ?1?. pfsber 12 rwh pflash single-bit error and correction 1)2)4) 0 b no single-bit error detected during read access to pflash 1 b single-bit error detected and corrected the error is set when in a 256-bit block read from flash at least one 64-bit block contained a single-bit error. this is independent of cached/non-cached addressing. registered status bit; must be cleared per command or by writing ?1?. dfcber 13 rwh dflash correctable bit error and correction 1)2)4) 0 b no correctable bit error detected during read access to dflash. 1 b correctable bit error detected and corrected. registered status bit; must be cleared per command or by writing ?1?. pfdber 14 rwh pflash double-bit error 1)2)4) 0 b no double-bit error or address error detected during read access to pflash 1 b double-bit error or address error detected in pflash the error is set when in a 256-bit block read from flash at least one 64-bit block contained a double-bit error. this is independent of cached/non-cached addressing. registered status bit; must be cleared per command or by writing ?1?. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-36 v1.1, 2011-03 pmu, v1.7 dfmber 15 rwh dflash multi-bit error 1)2)4) 0 b no uncorrectable multi-bit error detected during read access to dflash 1 b uncorrectable multi-bit error detected in dflash registered status bit; must be cleared per command or by writing ?1?. proin 16 rh protection installed 0 b no protection is installed 1 b read or/and write protection for one or more users is configured and correctly confirmed in the user configuration block(s). hw-controlled status flag rproin 18 rh read protection installed 0 b no read protection installed 1 b read protection and global write protection (with or without data flash) is configured and correctly confirmed in the user configuration block 0. supported only for the master user (user zero). hw-controlled status flag rprodis 19 rh read protection disable state 1)5) 0 b read protection (if installed) is not disabled 1 b read and global write protection is temporarily disabled. flash read with instructions from other memory, as well as program or eras e on not separately write protected sectors is possible. hw-controlled status flag wproin0 21 rh sector write protection installed for user 0 0 b no write protection installed for user 0 1 b sector write protection for user 0 is configured and correctly confirmed in the user configuration block 0. hw-controlled status flag field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-37 v1.1, 2011-03 pmu, v1.7 wproin1 22 rh sector write protection installed for user 1 0 b no write protection installed for user 1 1 b sector write protection for user 1 is configured and correctly confirmed in the user configuration block 1. hw-controlled status flag wproin2 23 rh sector otp protection installed for user 2 0 b no otp write protection installed for user 2 1 b sector otp write protection with rom functionality is configured and correctly confirmed in the ucb2. the protection is locked for ever. hw-controlled status flag wprodis0 25 rh sector write protection disabled for user 0 1)5) 0 b all protected sectors of user 0 are locked if write protection is installed 1 b all write-protected sectors of user 0 are temporarily unlocked, if not coincidently locked by user 2 or via read protection. hierarchical protection control: user-0 sectors are also unlocked, if coincidently protected by user 1. but not vice versa. hw-controlled status flag wprodis1 26 rh sector write protection disabled for user 1 1)5) 0 b all protected sectors of user 1 are locked if write protection is installed 1 b all write-protected sectors of user 1 are temporarily unlocked, if not coincidently locked by user 0 or user 2 or via read protection. hw-controlled status flag slm 28 rh flash sleep mode 1) hw-controlled status flag. indication of flash sleep mode taken because of global or individual sleep request; additionally indicates when the flash is in shut down mode. 0 b flash not in sleep mode 1 b flash is in sleep or shut down mode field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-38 v1.1, 2011-03 pmu, v1.7 note: the xbusy flags as well as the protec tion flags cannot be cleared with the ?clear status? command or with the ?reset to read? command. these flags are controlled by hw. note: the reset value above is indicated after correct execution of flash startup. additionally, errors are possible after startup (see chapter 5.7.7.2 ). extended flash status register the extended flash status contains additional information about error conditions. all bits can be cleared by writing a ?1? to it. additionally the complete register is cleared by the command sequences ?reset to read? and ?clear status?. orier 30 rh original error 1)2)4) 0 b no original error detected during startup. 1 b original data replaced by its copy. ver 31 rwh verify error 1)2)4) 0 b the page is correctly programmed or the sector correctly erased. all programmed or erased bits have full expected quality. 1 b a program verify error or an erase verify error has been detected. full quality (retention time) of all programmed (?1?) or erased (?0?) bits cannot be guaranteed. see chapter 5.7.7.1 and chapter 5.7.7.2 for proper reaction. this flag is set when either pflash, d0flash, or d1flash reported ver. registered status bit; must be cleared per command or writing ?1?. 0 17,20, 24, 27, 29 r reserved read zero, no write 1) cleared with application reset (class 3 reset) 2) cleared with command ?clear status? 3) cleared with power-on reset (porst) 4) cleared with command ?reset to read? 5) cleared with command ?resume protection? field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-39 v1.1, 2011-03 pmu, v1.7 xfsr extended flash status register (102c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 res 11 d1v er d0v er pve r 0 sem vio sria dde r res 4 res 3 res 2 pfa der pfd ber r rwh rwh rwh rwh r rwh rwh rwh rwh rwh rwh rwh field bits type description pfdber 0rwh pflash dber a dber was noted when decoding the ecc of data read from pflash. the error is set when in a 256-bit block read from flash at least one 64-bit block contained a double-bit error. this is independent of cached/non-cached addressing. pfader 1rwh pflash address ecc error an address ecc error was noted when decoding the address ecc of data read from pflash. the error is set when in a 256-bit block read from flash at least one 64-bit block contained an address ecc error. this is independent of cached/non- cached addressing. res2 2rwh reserved status information for internal use. res3 3rwh reserved status information for internal use. res4 4rwh reserved status information for internal use. sriadderr 5rwh sri bus address ecc error this flag is set when the pmu detects an ecc error in the address phase bus transaction on the sri bus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-40 v1.1, 2011-03 pmu, v1.7 5.6.2.2 flash configuration control the flash configuration register fcon reflects and controls the following general flash configuration functions: ? number of wait states for flash accesses. ? indication of installed and active read protection. ? instruction and data access control for read protection. ? interrupt mask bits. ? power reduction and shut down control. semvio 6rwh semaphore violation when the flash is reserved by the she module command cycles received by any other master set this bit. pver 8rwh pflash verify error a ver was reported during a pflash operation (see ver in fsr). d0ver 9rwh d0flash verify error a ver was reported during a d0flash operation (see ver in fsr). d1ver 10 rwh d1flash verify error a ver was reported during a d1flash operation (see ver in fsr). res11 11 rwh reserved status information for internal use. 0 [31:12 ], 7 r reserved; always read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-41 v1.1, 2011-03 pmu, v1.7 fcon flash configuration register (1014 h ) reset value: 0007 4f08 h 1) 1) after flash startup and execution of the startup sw in bootrom (after firmware exit), the initial value is 000x 4f08 h . the initial value of addecc depends on procon0.addecc. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 eob m df mb erm pf db erm df cb erm pf sb erm pro erm sq erm vop erm add ecc ddf she ddf pcp ddf dma 0 ddf dcf rpa rw rw rw rw rw rw rw rw rw rw rw rw r rwh rwh rh 1514131211109876543210 sl eep esl dis idle ws ec df ws dflash 000 ws ec pf ws pflash rw rw rw rw rw r r r rw rw field bits type description wspflash [3:0] rw wait states for read access to pflash this bitfield defines the number of wait states in number of fsi clock cycles (see scu chapter ccucon0), which are used for an initial read access to the program flash memory area. 0000 b pflash access with one wait state 0001 b pflash access with one wait state 0010 b pflash access with two wait states 0011 b pflash access with three wait states 0100 b pflash access with four wait states 0101 b pflash access with five wait states 0110 b pflash access with six wait states 0111 b pflash access with seven wait states. .... pflash access with eight up to fourteen wait states. 1111 b pflash access with fifteen wait states. wsecpf 4rw wait state for error correction of pflash 0 b no additional wait state for error correction 1 b one additional wait state for error correction during read access to program flash. if enabled, this wait state is only used for the first transfer of a burst transfer. set this bit only when requested by infineon. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-42 v1.1, 2011-03 pmu, v1.7 wsdflash [11:8] rw wait states for read access to dflash this bitfield defines the number of wait states in number of fsi clock cycles (see scu chapter ccucon0), which are used for a read access to the data flash memory area. 0000 b dflash access with one wait state 0001 b dflash access with one wait state 0010 b dflash access with two wait states 0011 b dflash access with three wait states 0100 b dflash access with four wait states 0101 b dflash access with five wait states 0110 b dflash access with six wait states 0111 b dflash access with seven wait states. 1000 b dflash access with eight wait states. .... dflash access with nine up to fourteen wait states. 1111 b dflash access with fifteen wait states. wsecdf 12 rw wait state for error correction of dflash 0 b no additional wait state for error correction 1 b one additional wait state for error correction during read acce ss to data flash set this bit only when requested by infineon. idle 13 rw dynamic flash idle 0 b normal/standard flash read operation 1 b dynamic idle of program flash enabled for power saving; static prefetching disabled note: in data flash, dynamic idle is always enabled (prefetching not supported). esldis 14 rw external sleep request disable 0 b external sleep request signal input is enabled 1 b externally requested flash sleep is disabled the ?external? signal input is connected with a global power-down/sleep request signal from scu. sleep 15 rw flash sleep 0 b normal state or wake-up 1 b flash sleep mode is requested, wake-up from sleep is started with clearing of the sleep-bit. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-43 v1.1, 2011-03 pmu, v1.7 rpa 16 rh read protection activated this bit monitors the status of the flash-internal read protection. this bit can only be ?0? when read protection is not installed or while the read protection is temporarily disabled with password sequence. 0 b the flash-internal r ead protection is not activated. bits dcf, ddf are not taken into account. bits dcf, ddfx can be cleared 1 b the flash-internal read protection is activated. bits dcf, ddf are enabled and evaluated. dcf 17 rwh disable code fetch from flash memory this bit enables/disables the code fetch from the internal flash memory area. once set, this bit can only be cleared when rpa=?0?. this bit is automatically set with reset and is cleared during startup, if no rp installed, and during startup (bootrom sw) in case of internal start out of flash. 0 b code fetching from the flash memory area is allowed. 1 b code fetching from the flash memory area is not allowed. this bit is not taken into account while rpa=?0?. ddf 18 rwh disable any data fetch from flash this bit enables/disables the data read access to the flash memory area (program flash and data flash). once set, this bit can only be cleared when rpa=?0?. this bit is automatically set with reset and is cleared during startup, if no rp installed, and during startup (bootrom sw) in case of internal start out of flash. 0 b data read access to the flash memory area is allowed. 1 b data read access to the flash memory area is not allowed. this bit is not taken into account while rpa=?0?. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-44 v1.1, 2011-03 pmu, v1.7 ddfdma 20 rw disable data fetch from dma controller this bit enables/disables the data read access to pflash and dflash memory from the dma controller, the sdma controller and other bus masters that access the sri bus via the dma peripheral interfaces ? these are, dependent on the device: cerberus, mli and memcheck. once set, this bit can only be cleared when rpa=?0?. 0 b the data read access by the dma, sdma controller and its peripheral interfaces to the flash memory area is allowed. 1 b the data read access to the flash memory area is not allowed for the dma, sdma controller and its peripheral interfaces. ddfpcp 21 rw disable data fetch from pcp controller this bit enables/disables the data read access to pflash and dflash memory via the lfi bridge from pcp controller. once set, this bit can only be cleared when rpa=?0?. 0 b the data read access by the pcp controller to the flash memory area is allowed. 1 b the data read access to the flash memory area is not allowed for the pcp controller. ddfshe 22 rw disable data fetch from she module this bit enables/disables the data read access to pflash and dflash memory via the lfi bridge from the she module. once set, this bit can only be cleared when rpa=?0?. 0 b the data read access by the she module to the flash memory area is allowed. 1 b the data read access to the flash memory area is not allowed for the she module. addecc 23 rw address ecc in pflash this bit selects if the data in pflash is written and read with an ecc code that is calculated over address bits (see chapter 5.5.6 ). 0 b standard ecc is used. 1 b address ecc is used. attention: this bit must not be changed while accessing flash (reading , programming, erasing). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-45 v1.1, 2011-03 pmu, v1.7 note: the default numbers of wait states re present the slow cases. this is a general proceeding and additionally opens the possibility to execute higher frequencies without changing the configuration. voperm 24 rw verify and operation error interrupt mask 0 b interrupt not enabled 1 b flash interrupt because of verify error or operation error in flash array (fsi) is enabled sqerm 25 rw command sequence error interrupt mask 0 b interrupt not enabled 1 b flash interrupt because of sequence error is enabled proerm 26 rw protection erro r interrupt mask 0 b interrupt not enabled 1 b flash interrupt because of protection error is enabled pfsberm 27 rw pflash single-bit error interrupt mask 0 b no single-bit error interrupt enabled 1 b single-bit error interrupt enabled for pflash dfcberm 28 rw dflash correctable bit error interrupt mask 0 b no correctable bit error interrupt enabled 1 b correctable bit error interrupt enabled for dflash pfdberm 29 rw pflash double-bit error interrupt mask 0 b double-bit error interru pt for pflash not enabled 1 b double-bit error interrupt for pflash enabled. especially intended for margin check dfmberm 30 rw dflash multi-bit error interrupt mask 0 b multi-bit error interrupt for dflash not enabled 1 b multi-bit error interrupt for dflash enabled. especially intended for margin check eobm 31 rw end of busy interrupt mask 0 b interrupt not enabled 1 b eob interrupt is enabled 0 [7:5], 19 r reserved read/write zero field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-46 v1.1, 2011-03 pmu, v1.7 note: after reset and execution of bootrom startup sw, the read protection control bits are coded as follows: ddf, dcf, rpa = ?110?: no r ead protection installed ddf, dcf, rpa = ?001?: read protection installed; start in internal flash ddf, dcf, rpa = ?111?: read protection in stalled; start not in internal flash. 5.6.2.3 flash read buffer configuration the rdbcfg0?2 registers define the assignm ent of read buffers to masters. the functionality of the read buffers is described in chapter 5.5.3 . it is forbidden to assign more than one read buffer to the same master. the resulting behavior is unpredictable. 5.6.2.4 flash identification register the register identifies the flash module which can have a different version from the pmu. rdbcfg0 read buffer cfg 0 (1040 h ) reset value: 0000 0002 h rdbcfg1 read buffer cfg 1 (1044 h ) reset value: 0000 0004 h rdbcfg2 read buffer cfg 2 (1048 h ) reset value: 0000 000d h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0tag rrw field bits type description tag [3:0] rw master tag this read buffer is assigned to the master with sri tag = tag. 0 [31:4] r reserved write 0, read 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-47 v1.1, 2011-03 pmu, v1.7 flash0 identification flash1 identification the second flash array (flash1) controlled by pmu1 can have a different feature set from the flash0 at pmu0, e.g. it typically does not contain a dflash. therefore it has another id number than the flash0 array. flash0_id flash module identification register (1008 h ) reset value: 0083 c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number mod_rev defines the module revision number. the value of a module revision starts with 01 h (first revision). mod_type [15:8] r module type this bit field is c0 h . it defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines a module identification number. for the TC1798 flash0 this number is 0083 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-48 v1.1, 2011-03 pmu, v1.7 5.6.2.5 flash reservation semaphore the flash banks use common resources which limits the concurrency of flash processes (see chapter 5.5.4.4 ). this is especially an issue when the she module and a flash eeprom emulation dr iver both need access to the dflash. the flash user interface is not suitable for multi-master op eration. therefore this semaphore enables different masters or sw threads to reserve the flash interface. the bit ?she? can be set and cleared exclusively by the she module using a separate communication path. this is done by the she module when it executes commands that need flash access. the bits sx can be set by writing a ?1? to this bit. no bit is changed to ?1? when already she or any sx is ?1? or if the write access contains more than one ?1?-bit in the sx positions. a bit can be cleared by writing a ?1? to the corresponding clear bit sxc. flash1_id flash module identification register (1008 h ) reset value: 0084 c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number mod_rev defines the module revision number. the value of a module revision starts with 01 h (first revision). mod_type [15:8] r module type this bit field is c0 h . it defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines a module identification number. for the TC1798 flash1 this number is 0084 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-49 v1.1, 2011-03 pmu, v1.7 when the she bit is set: ? command cycles are only accepted from the she module. all others are rejected with a bus error and set xfsr.semvio. ? read accesses from dflash and keyflash by any other bus master than she fail with a bus error. ? command cycles addressing the pflash fail with sqer. ? further protections (especially of registers) are not activated. the application is responsible to configure the flash so that it can be operated by the she module. this is not security risk because the she module verifies all operations. when an other sx bit is set the she module can not request flash access. the sx bits do not affect the hardware operation any furt her. flash drivers can use them to organize competing flash accesses. this register is also existing in pmu1 and higher. in these the bit she is not connected to the she module and stays always at ?0?. sema flash access semaphore (1030 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 s7c s7 s6c s6 s5c s5 s4c s4 s3c s3 s2c s2 s1c s1 0 she wrwhwrwhwrwhwrwhwrwhwrwhwrwh r rh field bits type description she 0rh she semaphore if set only the she module has full flash access (see chapter 5.5.4.4 ) sx (x=1-7) 2*x rwh semaphore x this bit can be written to ?1? if no other sx or the she bit is ?1?. this bit can be cleared by writing a ?1? to the corresponding sxc. sxc (x=1-7) 2*x+1 w semaphore x clear writing a ?1? clears the corresponding sx. read 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-50 v1.1, 2011-03 pmu, v1.7 5.6.2.6 margin check control note: although double-bit error traps are dis abled with reset, the traps are enabled by the startup sw (firmware) in boot rom before boot rom exit. margin check control pflash 0 [31:16] , 1 r reserved write 0, read 0. marp margin control register pflash (1018 h ) reset value: 0000 8000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 tr ap dis 0margin rw r rw field bits type description margin [3:0] rw pflash margin selection 0000 b default , standard (default) margin. 0001 b tight0 , tight margin for 0 (low) level. suboptimal 0-bits are read as 1s. 0100 b tight1 , tight margin for 1 (high) level. suboptimal 1-bits are read as 0s. ? reserved. trapdis 15 rw pflash double-bit error trap disable 0 b if a double-bit error occurs in pflash, a bus error trap is generated 1) . 1 b the double-bit error trap is disabled. shall be used only during margin check 1) after boot rom exit, double-bit error traps are enabled (trapdis = 0). 0 [14:4], [31:16] r reserved; always read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-51 v1.1, 2011-03 pmu, v1.7 margin check control dflash mard margin control register dflash (101c h ) reset value: 0000 8000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 tr ap dis 0 ctr l margin rw r rw rw field bits type description margin [3:0] rw dflash margin selection 0000 b default , standard (default) margin. 0001 b tight0 , tight margin for 0 (low) level. suboptimal 0-bits are read as 1s. 0100 b tight1 , tight margin for 1 (high) level. suboptimal 1-bits are read as 0s. ? reserved. ctrl 4rw margin control enable 0 b the active read margin for both dflash banks is determined by margin. 1 b both dflash banks are read with standard (default) margin independently of margin. trapdis 15 rw dflash multiple-bit error trap disable 0 b if an uncorrectable mult i-bit error occurs in dflash, a bus error trap is generated 1) . 1 b the multi-bit error trap is disabled. shall be used only during margin check 1) after boot rom exit, multi-bit error traps are enabled (trapdis = 0). 0 [14:5], [31:16] r reserved; always read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-52 v1.1, 2011-03 pmu, v1.7 5.6.2.7 protection configuration indication the configuration of read/write/otp protec tion is indicated with registers procon0, procon1 and procon2, thus separately for every user, and it is generally indicated in the status register fsr. the three proconx registers are read-only registers. they are defined as follows: protection configuration for user 0 procon0 flash protection config. user 0 (1020 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rpr o dfe xpr o add ecc res s22/ s23l rh rh rh rh rh 1514131211109876543210 s20/ s21l s18/ s19l s16/ s17l s14/ s15l s12/ s13l s10/ s11l s9l s8l s7l s6l s5l s4l s3l s2l s1l s0l rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description snl (n=0-9) nrh sector n locked for write protection by user 0 these bits indicate whether pflash sector n is write-protected by user 0 or not. 0 b no write protection is configured for sector n. 1 b write protection is configured for sector n. s10/s11l 10 rh sectors 10 and 11 locked for write protection by user 0 this bit indicates whether pflash sectors 10+11 (together 512 kb) are write- protected by user 0 or not. 0 b no write protection is configured for sectors 10+11. 1 b write protection is configured for sectors 10+11. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-53 v1.1, 2011-03 pmu, v1.7 s12/s13l 11 rh sectors 12 and 13 locked for write protection by user 0 this bit indicates whether pflash sectors 12+13 (together 512 kb) are write- protected by user 0 or not. 0 b no write protection is configured for sectors 12+13. 1 b write protection is configured for sectors 12+13. s14/s15l 12 rh sectors 14 and 15 locked for write protection by user 0 this bit indicates whether pflash sectors 14+15 (together 512 kb) are write- protected by user 0 or not. 0 b no write protection is configured for sectors 14+15. 1 b write protection is configured for sectors 14+15. s16/s17l 13 rh reserved: sectors 16 and 17 locked for write protection by user 0 this bit indicates whether pflash sectors 16+17 (together 512 kb) are write- protected by user 0 or not. 0 b no write protection is configured for sectors 16+17. 1 b write protection is configured for sectors 16+17. s18/s19l 14 rh reserved: sectors 18 and 19 locked for write protection by user 0 this bit indicates whether pflash sectors 18+19 (together 512 kb) are write- protected by user 0 or not. 0 b no write protection is configured for sectors 18+19. 1 b write protection is configured for sectors 18+19. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-54 v1.1, 2011-03 pmu, v1.7 s20/s21l 15 rh reserved: sectors 20 and 21 locked for write protection by user 0 this bit indicates whether pflash sectors 20+21 (together 512 kb) are write- protected by user 0 or not. 0 b no write protection is configured for sectors 20+21. 1 b write protection is configured for sectors 20+21. s22/s23l 16 rh reserved: sectors 22 and 23 locked for write protection by user 0 this bit indicates whether pflash sectors 22+23 (together 512 kb) are write- protected by user 0 or not. 0 b no write protection is configured for sectors 22+23. 1 b write protection is configured for sectors 22+23. addecc 29 rh address ecc configuration this bit is evaluated by ssw to initialize fcon.addecc. dfexpro 30 rh data flash excluded from read protection when read protection is configured this bit determines whether the dflash shall be excluded from read protection and gl obal write protection or not. 0 b dflash not excluded from read protection and global write protection. 1 b dflash is excluded from read/write protection; read protection and global write protection is configured by user 0 only for the pflash rpro 31 rh read protection configuration this bit indicates whether read protection is configured for pflash and dflash by user 0. 0 b no read protection configured 1 b read protection and global write protection is configured by user 0 (master user) field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-55 v1.1, 2011-03 pmu, v1.7 protection configuration for user 1 res [28:17] rh reserved deliver the corresponding content of ucb0. procon1 flash protection config. user 1 (1024 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 alsedis spr ec res s22/ s23l rh rh rh rh 1514131211109876543210 s20/ s21l s18/ s19l s16/ s17l s14/ s15l s12/ s13l s10/ s11l s9l s8l s7l s6l s5l s4l s3l s2l s1l s0l rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description snl (n=0-9) nrh sector n locked for write protection by user 1 these bits indicate whether pflash sector n is write-protected by user 1 or not. 0 b no write protection is configured for sector n. 1 b write protection is configured for sector n. s10/s11l 10 rh sectors 10 and 11 locked for write protection by user 1 this bit indicates whether pflash sectors 10+11 (together 512 kb) are write- protected by user 1 or not. 0 b no write protection is configured for sectors 10+11. 1 b write protection is configured for sectors 10+11. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-56 v1.1, 2011-03 pmu, v1.7 s12/s13l 11 rh sectors 12 and 13 locked for write protection by user 1 this bit indicates whether pflash sectors 12+13 (together 512 kb) are write- protected by user 1 or not. 0 b no write protection is configured for sectors 12+13. 1 b write protection is configured for sectors 12+13. s14/s15l 12 rh sectors 14 and 15 locked for write protection by user 1 this bit indicates whether pflash sectors 14+15 (together 512 kb) are write- protected by user 1 or not. 0 b no write protection is configured for sectors 14+15. 1 b write protection is configured for sectors 14+15. s16/s17l 13 rh reserved: sectors 16 and 17 locked for write protection by user 1 this bit indicates whether pflash sectors 16+17 (together 512 kb) are write- protected by user 1 or not. 0 b no write protection is configured for sectors 16+17. 1 b write protection is configured for sectors 16+17. s18/s19l 14 rh reserved: sectors 18 and 19 locked for write protection by user 1 this bit indicates whether pflash sectors 18+19 (together 512 kb) are write- protected by user 1 or not. 0 b no write protection is configured for sectors 18+19. 1 b write protection is configured for sectors 18+19. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-57 v1.1, 2011-03 pmu, v1.7 s20/s21l 15 rh reserved: sectors 20 and 21 locked for write protection by user 1 this bit indicates whether pflash sectors 20+21 (together 512 kb) are write- protected by user 1 or not. 0 b no write protection is configured for sectors 20+21. 1 b write protection is configured for sectors 20+21. s22/s23l 16 rh reserved: sectors 22 and 23 locked for write protection by user 1 this bit indicates whether pflash sectors 22+23 (together 512 kb) are write- protected by user 1 or not. 0 b no write protection is configured for sectors 22+23. 1 b write protection is configured for sectors 22+23. sprec 23 rh sprec soft-programming recover. 0 b program 1-data. 1 b soft recover. see chapter 5.7.8.3 . alsedis [31:24] rh alse disable each bit of alsedis[7:0] corresponds to one of the logical sectors s[7:0]. if a bit is set the logical sector is not checked for an aborted erase nor is any of the repair algorithms performed. see chapter 5.7.8.3 . res [22:17] rh reserved deliver the corresponding content of ucb1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-58 v1.1, 2011-03 pmu, v1.7 protection configuration for user 2 procon2 flash protection config. user 2 (1028 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res 31 dat m res s22/ s23 rom rh rh rh rh 1514131211109876543210 s20/ s21 rom s18/ s19 rom s16/ s17 rom s14/ s15 rom s12/ s13 rom s10/ s11 rom s9 rom s8 rom s7 rom s6 rom s5 rom s4 rom s3 rom s2 rom s1 rom s0 rom rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description snrom (n=0- 9) nrh sector n locked forever by user 2 these bits indicate whether pflash sector n is an otp protected sector with read-only functionality, thus if it is locked for ever. 0 b no rom functionality configured for sector n. 1 b rom functionality is configured for sector n. re-programming of this sector is no longer possible. s10/s11rom 10 rh sectors 10 and 11 locked forever by user 2 this bit indicates whether pflash sectors 10+11 (together 512 kb) are read-only sectors or not. 0 b no rom functionality is configured for sectors 10+11. 1 b rom functionality is configured for sectors 10+11. s12/s13rom 11 rh sectors 12 and 13 locked forever by user 2 this bit indicates whether pflash sectors 12+13 (together 512 kb) are read-only sectors or not. 0 b no rom functionality is configured for sectors 12+13. 1 b rom functionality is configured for sectors 12+13. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-59 v1.1, 2011-03 pmu, v1.7 s14/s15rom 12 rh sectors 14 and 15 locked forever by user 2 this bit indicates whether pflash sectors 14+15 (together 512 kb) are read-only sectors or not. 0 b no rom functionality is configured for sectors 14+15. 1 b rom functionality is configured for sectors 14+15. s16/s17rom 13 rh reserved: sectors 16 and 17 locked forever by user 2 this bit indicates whether pflash sectors 16+17 (together 512 kb) are read-only sectors or not. 0 b no rom functionality is configured for sectors 16+17. 1 b rom functionality is configured for sectors 16+17. s18/s19rom 14 rh reserved: sectors 18 and 19 locked forever by user 2 this bit indicates whether pflash sectors 18+19 (together 512 kb) are read-only sectors or not. 0 b no rom functionality is configured for sectors 18+19. 1 b rom functionality is configured for sectors 18+19. s20/s21rom 15 rh reserved: sectors 20 and 21 locked forever by user 2 this bit indicates whether pflash sectors 20+21 (together 512 kb) are read-only sectors or not. 0 b no rom functionality is configured for sectors 20+21. 1 b rom functionality is configured for sectors 20+21. s22/s23rom 16 rh reserved: sectors 22 and 23 locked forever by user 2 this bit indicates whether pflash sectors 22+23 (together 512 kb) are read-only sectors or not. 0 b no rom functionality is configured for sectors 22+23. 1 b rom functionality is configured for sectors 22+23. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-60 v1.1, 2011-03 pmu, v1.7 5.6.2.8 flash ecc access ecc write register the error correction code write register eccw contains bits for disabling the ecc encoding separately for pflash and dflash. when disabling the ecc encoding for pflash with pecencdis = ?1? the 8-bit ecc code for the next 64-bit data block transferred from pmu to the flash assembly buffer is taken from eccw.wcodel. when disabling the ecc encoding for dflash with decencdis = ?1? the 16-bit ecc code for the next 64-bit data block transferred from pmu to the flash assembly buffer is taken from eccw.wcodeh (bits 15 :8) and eccw.wcodel (bits 7:0). because of internal dependencies only one of pecencdis or decencdis may be set to ?1?. datm 30 rh disable atm this bit indicates if the atm ?application test mode? is disabled or not. 0 b atm is enabled. 1 b atm is disabled. this bit is only used in pmu0. res31 31 rh reserved deliver the corresponding content of ucb2. res [29:17] rh reserved deliver the corresponding content of ucb2. eccw ecc write register (10e0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pec enc dis dec enc dis 0 rw rw r 1514131211109876543210 wcodeh wcodel rw rw field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-61 v1.1, 2011-03 pmu, v1.7 ecc read register the error correction code read register eccr allows to disable the ecc correction. the ecc decoding (i.e. the error detection) is not influenced. if necessary the trap generation has to be separately disabled by marp.trapdis and mard.trapdis. further on this register allows to read the uncorrected ecc code. the ecc code of the last read access is stored in eccr.rcodex. for pflash reads the 8-bit ecc code is stored in eccr.rcodel and for dflash the 16-bit ecc code is stored in eccr.rcodeh and eccr.rcodel. field bits type description wcodel [7:0] rw error correction write code low 8-bit ecc code for the current 64-bit write buffer to be written into the assembly buffer instead of generated ecc. wcodeh [15:8] rw error correction write code high 8-bit ecc code for the current 64-bit write buffer to be written into the assembly buffer instead of generated ecc. decencdis 30 rw dflash ecc encoding disable 0 b the ecc code is automatically calculated. 1 b the ecc code is taken from wcodeh and wcodel. pecencdis 31 rw pflash ecc encoding disable 0 b the ecc code is automatically calculated. 1 b the ecc code is taken from wcodel. 0 [29:16] r reserved; always read as 0. eccr ecc read register (10e4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pec dec dis dec dec dis 0 rw rw r 1514131211109876543210 rcodeh rcodel rh rh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-62 v1.1, 2011-03 pmu, v1.7 5.6.2.9 she secure internal flash boot the sheboot0?2 registers supply the bytes 4?7 of the user configuration blocks 0?2. as documented in the she chapter these fields can be used to configure a secure boot from internal flash. field bits type description rcodel [7:0] rh error correction read code low 8-bit ecc code, read from the flash read buffer with last data read operation. for pflash this is the complete ecc value. for df lash this is the lower half of the 16-bit ecc value. rcodeh [15:8] rh error correction read code high 8-bit ecc code, read from the flash read buffer with last data read operation. unused for pflash reads. for dflash this is the upper half of the 16-bit ecc value. decdecdis 30 rw dflash ecc decoding disable 0 b ecc correction for dflash enabled. 1 b ecc correction for dflash disabled. pecdecdis 31 rw pflash ecc deco ding disable 0 b ecc correction for pflash enabled. 1 b ecc correction for pflash disabled. 0 [29:16] r reserved; always read as 0. shebootx (x=0-2) she secure boot cfg (1034 h +4*x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 she bgd size rh rh rh 1514131211109876543210 size rh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-63 v1.1, 2011-03 pmu, v1.7 field bits type description she 31 rh secure boot enable as documented in the she chapter this bit enables the secure boot from internal flash with size taken as size of the boot loader. bgd 30 rh background secure boot as documented in the she chapter the secure boot can be performed in background or foreground. 0 b fgd , foreground secure boot. 1 b bgd , background secure boot. size [29:0] rh she bootloader size byte length of the she bootloader. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-64 v1.1, 2011-03 pmu, v1.7 5.7 application hints the following application hints should support the user in using the pmu and flash optimally. 5.7.1 changes with respect to audo-ng and audo-f the following changes of the pmu with re spect to audo-ng and audo-f products are highlighted: ? changed bus interface from lmb to sri. ? no bus ?retry? anymore in case of reading busy flash banks. always a bus error is triggered. ? the wait-state settings in fcon don?t relate to the bus clock as in audo-f (i.e. the lmb clock) but to the fsi clock. this cl ock has its own divider from the pll clock which needs to be configured in scu_ccucon0.fsidiv. it must be configured to have a relation f sri /f fsi or 2/1 or 1/1. ? enhanced flash read buffer concept with master specific read buffers. ? the ovram and the emem were moved to a different module ?lmu?. ? support of she ? software handling flash memory should negotiate flash access with she module using the sema semaphore. ? different content of ucbs supporting she secure boot function. new shebootx registers. ? ddfshe flag in fcon. ? handling key storage for she in additional private sectors of the dflash. ? configuration of alse with ucb1: possibility to disable alse for selected logical sectors. ? dfexpro set independent of rproin. ? tp: changed address rtpwt. changed configuration. see separate documentation. ? programming and reading data with disabled ecc generation and correction allows customers to program data with invalid ecc. ? error flags in fsr can be selectively cleared to enable easier flag handling for concurrent operations. ? new extended status register xsfr. ? reorganization of procons due to extended memory range. ? changed base addresses of all flash modules. ? dec-ted ecc algorithm in dflash. ? address ecc and normal sec-ded ecc in pflash. attention: this feature can cause incompatib ility of audo-ng/f flash drivers with this device. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-65 v1.1, 2011-03 pmu, v1.7 5.7.2 performing flash operations this section offers advice for programming command sequences. general advice ? code that performs pflash programming or erasing must not be executed from the same pflash. ? the command cycles shall address the non-cached address range of the flash (otherwise the data may stay in the cache or could be received by the pmu in an incorrect order). ? the non-cached flash range is not regar ded as peripheral address space by the tricore. this means that a read (notably reading the fsr for checking the flags) placed behind the last command cycle write in program order might be executed before this last write. the fsr flags page, prog , erase can be used to en sure that polling for a cleared busy starts only after the command was accepted by the pmu. additionally it is recommended to place a ?dsync? instruction between a command sequence and read accesses to depending data including affected registers. ? the caches (data cache in dmi ?dcache? and instruction cache in pmi ?icache?) as well as the data line buffer in the dmi ?dlb? are not automatically invalidated nor updated after changing flash content by er asing or programming. it is therefore recommended to either invalidate them actively or read the flash content via the non- cached address range. otherwise old data might be delivered from these buffers. the dmi cache and line buffer can be invalidated by writing ovc_ocon.dcinval to ?1?. the icache can be invalidated by writing pcon1.pcinv to ?1?. all buffers are invalidated by a reset. ? the pmu and flash work with the sri and fsi clocks. when changing the divider values of these clocks in scu_ccucon0 the following rules apply: ? the only allowed pmu/flash ?operation? when switching is reading from flash memory. programming or erasing the flash is forbidden. ? it must be ensured that before, during and after the divider change the configured number of flash wait-cycles is suffici ent for the selected clock frequency. remember that the wait- cycles are counted with f fsi . sequence for programming the following sequence is the most defensiv e one for programming a page. it is however acceptable to skip some checks because the programmed data should be verified anyhow afterwards: ? ?clear status? to clear flags. ? ?enter page mode?. ? dsync. ? wait until fsr.xfpage = ?1? or fail if fsr.sqer = ?1? or fsr.proer = ?1?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-66 v1.1, 2011-03 pmu, v1.7 ? repeat ?load page? until the page is filled. ? ?write page?. ? dsync. ? wait until fsr.prog = ?1? or fail if fsr.sqer = ?1? or fsr.proer = ?1?. ? wait until fsr.xbusy = ?0? or enable the interrupt. ? while fsr.xbusy is ?1? the flags fsr.xfoper can be checked for ?1? as abort criterion to protect against hardware failures causing busy to stay ?1?. ? check for fsr.ver flag (see handling advice in chapter 5.7.7.1 ). ? fail if fsr.xfoper = ?1?. ? check programmed content, evaluate fsr.xdber and possibly count single-bit errors. ? clear error flags and fsr.prog either with ?clear status? or by directly writing to fsr. sequence for erasing the following sequence is the most defensive one for erasing a sector. it is however acceptable to skip some checks because the programmed data should be verified anyhow after programming: ? ?clear status? to clear flags. ? ?erase sector?. ? dsync. ? wait until fsr.erase = ?1? or fail if fsr.sqer = ?1? or fsr.proer = ?1?. ? wait until fsr.xbusy = ?0? or enable the interrupt. ? while fsr.xbusy is ?1? the flags fsr.xfoper can be checked for ?1? as abort criterion to protect against hardware failures causing busy to stay ?1?. ? check for fsr.ver flag (see handling advice in chapter 5.7.7.1 ). ? fail if fsr.xfoper = ?1?. ? clear error flags and fsr.erase either with ?clear status? or by directly writing to fsr. concurrent use of d0flash and d1flash the dflash supports concurrent operatio ns, notably programming in one bank and erasing in the second bank (see chapter 5.5.4.4 ). this feature was already available in previous product generations audo-ng and audo-f. in these product generations the flash driver faced some challenges because error flags were not separated for each bank and flags could not be easily cleared while an operation was ongoing. with this product generation flag handling for concurrent operations was significantly enhanced. the following depicts the flow for a programming routine on d0flash which can be executed while an erase is already ongoing in d1flash: ? ?enter page mode? ? dsync. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-67 v1.1, 2011-03 pmu, v1.7 ? wait until fsr.dfpage = ?1? or fail if fsr.sqer = ?1? or fsr.proer = ?1? (development time check). ? repeat ?load page? until the page is filled. ? ?write page?. ? dsync. ? wait until fsr.prog = ?1? or fail if fsr.sqer = ?1? or fsr.proer = ?1? (development time check). ? wait until fsr.d0busy = ?0? or enable the interrupt. ? while fsr.d0busy is ?1? the flags fsr.dfoper can be checked for ?1? as abort criterion to protect against hardware failures causing busy to stay ?1?. ? check for xfsr.d0ver (see handling advice in chapter 5.7.7.1 ). clear flag by writing xfsr.d0ver = ?1?. ? fail if fsr.dfoper = ?1? (could have been caused by programming or erasing). ? check programmed content and evaluate fsr.dfmber. clear flag by writing fsr.dfmber = ?1?. ? clear fsr.prog by directly writing to fsr. endinit register protection as described in chapter 5.6 many registers are write protec ted. the write protection ?e? is changed by an spb write acce ss. the user should be awar e that this spb write access changing the protection and preceding or following sri accesses to registers affected by this protection can incur diff erent system delays. thus they may not become effective in program order. as remedy it is recommended to read back the protection register (wdt_con0) before performing the depending sri accesses. 5.7.3 eeprom emulation with dflash the term ?eeprom emulation? designates an algorithm with the following features: ? it increases the effective endurance by spreading the eeprom write accesses over a larger range of flash memory. ? it ensures that all flash cells incur a similar number of cycles independent of the update frequency of the eeprom data (?wear levelling?). ? it manages the allocation of eeprom data to flash ranges so that stale data can be erased. as the dflash of the TC1798 contains 2 sectors (one in each bank) and only complete sectors can be erased all eeprom emulation al gorithms follow th e same general idea: ? the eeprom writes are performed in one sector, the ?active? one. the other sector stays erased. ? the data is stored so that several writes of the same eeprom address can be performed in one dflash sector. the position of the latest data version and the original eeprom address can be determi ned from the address in flash and www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-68 v1.1, 2011-03 pmu, v1.7 additional administrative data (e.g. all data is pushed to a stack and the pushed data contains the eeprom address). ? at a certain sector fill level a sector switch is performed. this mo ves all active data to the erased sector. after that the active sector is erased and the other sector becomes the active one. one specific requirement for an eeprom emulation algorith m is the resistance against aborts during its operation. in any case the algorithm must be able after device startup to recover without data loss, determine the active sector and resume operation. in many applications even resistance agai nst aborted flash processes (program, erase) is needed. see details in chapter 5.7.8.2 . 5.7.3.1 robust eeprom emulation a key requirement for an eeprom emulation algorithm is t he reliability of the stored data. the dflash with its dec-ted ecc algorit hm protects perfectly against bit or bit- line oriented failures. however word-line oriented failures need to be handled by the eeprom emulation algorithm. the following hints shall be followed to achieve highest possible robustness: ? before programming a page save the content of the other page on the same word- line in sram. ? program the new page and compare the cont ent of this page and of the saved page with their reference data. this can be done with normal read margins. ignore correctable errors and the ver flag. ? if the data comparison fails program this page and the saved content of the other page to a different word-line. ? this procedure can be repeated if the da ta comparison fails again. the number of repetitions should be limited (e.g. to 3) in case the programming fails because of out- of-spec operating conditions. ? word-line oriented fails can also have the effect that the affected word-lines can not be erased anymore (other word-lines stay fully functional). a robust eeprom emulation is immune against such word-lines (e.g. by identifying old data by version counters). for the TC1798 this robust eepr om algorithm is required fo r the usage of the dflash. due to the specificity of each application the appropriate usage and implementation of these measures (together with the more elaborate ver handling) must be chosen according to the context of the application. 5.7.4 performance considerations this section contains advice for optimizing the performance of flash accesses. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-69 v1.1, 2011-03 pmu, v1.7 dflash performance the features of the dflash were optimized for the requirements of an eeprom emulation. as side effect the access time is significantly higher as in the pflash. additionally it can?t be read with burst access es. therefore it is not recommended to use the dflash directly memory mapped in the application. in its typical use scenario the active eeprom data is retrieved from th e dflash once during application startup and is copied to sram from where it is used by t he application. further read accesses are only done by the emulation driver when performing updates. read buffers as described in chapter 5.5.3 the pmu contains a set of configurable read buffers. each of them is assigned to one bus master. it is filled by pre-fetching an incremental following address. for optimum performance a read buffer should be assigned to each master with a high number of pflash reads. after reset one read buffer is assigned to the she module for optimum performance of the secure boot. when the she module is not needed or after finishing the secure boot it is advisable to change this buffer tag depending on application needs (e.g. dma). as the pre-fetching is done with increa sing addresses reading pflash ranges with decreasing addresses (e.g. reading an array from a high index to low indices) doesn?t benefit from the read buffers. 5.7.5 handling flash protection failing to use the flash protection correctly can on one hand lock the device forever, even damage it or on the other hand leave the protection ineffective. effective use of flash protection for an effective ip protection the flash read protection must be activated. as described in chapter 5.5.5.4 this ensures system wide that the flash cannot be read from external or changed without authorization. with the default setting of procon0.dfexpro (= ?0?) an ac tive flash read protection causes a global write protection of pf lash and dflash in this pmu. thus for programming the dflash at application run-time the read protection would have to be disabled with the correct password. this means the password needs to be installed in the flash. by programming dfexpro to ?1? the dflash is excluded from the global write protection. now the application can program the dflash without disabling the read protection and the password doesn?t need to be known to the application. attention: full flash analysis of an far device is only possible when the customer has removed all installed protections or delivers the necessary passwords with the device. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-70 v1.1, 2011-03 pmu, v1.7 as the removal of an otp protection in ucb2 is not possible the otp protection inevitably limits analysis capabilities. changing ucbs the protection installation is modified by erasing and programming the ucbs (see chapter 5.5.5.3 ). these operations need to be performed with care as described in the following. aborting an ?erase uc block? operation (e.g. due to reset or power failure) must be avoided at all means. as an ucb is a logical sector of the configuration sector an aborted erase can affect readability of the complete configuration sector content. with an unreadable configuration sector the device is unusable. an automatic repair (as for the logical sectors, see chapter 5.7.8.3 ) is not implemented. for the same reason the allo wed number of program/erase cycles of the ucbs must not be exceeded. over-cycling the ucbs can disturb data in the configuration sector which finally leads to an unusable device. the installation of the protection and its confirmation on different pages of the ucb offers the possibility to check the installation befo re programming the confirmation. first the protection needs to be programmed, then an application reset must be triggered to trigger the reading of the ucbs by the pmu and after that the protection can be verified (e.g. ?disable ? protection? to check the password and by checking procons, sheboots and fcon). the application reset is inevitable because the pmu reads the ucbs only during the startup phase. 5.7.6 cooperation with she as described in chapter 5.5.4.4 the she module stores its keys in the keyflash. as this keyflash has common resources with the pflash and dflash the she module blocks the dflash (completely) and the pflash (only program/erase) by setting its semaphore bit she_sema.she when it accesses the keyflash. therefore in all applications supporting she functionality the flash drivers should cooperate with the she module by setting an other she_sema bit before doing a program/erase access to pflash or dflash and before reading the dflash. after finishing their access they have to release the semaphore bit again to enable the she module access to its keyflash. when flash drivers don?t set the semaphore bit it might happen that their command sequences are disturbed due to an interception by the she module. when flash driver don?t release their semapho re bit in time they can prevent the she module from performing key updates. please note that the she su broutines she::load_key and she::debug_authorizat ion call ?clear status? before programming the keys, effectively clearing fsr. but she never calls ?clear status? when finishing a subroutine www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-71 v1.1, 2011-03 pmu, v1.7 (either reading keys or programming keys). t hus errors reported by a she subroutine can be analyzed by reading fsr. 5.7.7 handling errors the earlier sections described shortly the functionality of ?error indicating? bits in the flash status registers fsr and xfsr . this section elaborates on this with more in-depth explanation of the error conditions and recommendations how these should be handled by customer software. 5.7.7.1 handling errors during operation this first part handles error conditions occurring during operation (i.e. after issuing command sequences) and the second part ( section 5.7.7.2 ) error conditi ons detected during startup. sqer ?sequence error? fault conditions: ? improper command cycle address or data , i.e. incorrect command sequence. ? write access to busy flash bank. ? new ?enter page? in page mode. ? ?load page? and not in page mode. ? ?load page? results in buffer overflow. ? ?load page? with mixed 32/64 transfers. ? first ?load page? addresses 2. word. ? ?write page? with buffer underflow. ? ?write page? and not in page mode. ? ?write page? to unavailable flash range. ? command sequence with address not pointing to a legal start address (e.g. page, ucb or sector). ? byte transfer to password or data. ? ?erase sector? command to dflash. ? erase ucb with wrong ucba. new state: read mode is entered with following exceptions: ? ?enter page? in page mode re-enters page mode. ? ?write page? with buffer underflow is executed. ? after ?load page? causing a buffer overflow the page mode is not left, a following ?write page? is executed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-72 v1.1, 2011-03 pmu, v1.7 proposed handling by software: usually this bit is only set due to a bug in the software. therefore in development code the responsible error tracer should be notified. in production code this error will not occur. it is however possible to clear this flag with ?clear status? or ?reset to read? and simply issue the corrected command sequence again. pfoper/dfoper ?o peration error? fault conditions: ecc double-bit error detected in flash microcode sram during a program or erase operation in pflash or dflash. this can be a transient event due to alpha-particles or illegal operating conditions or it is a per manent error due to a hardware defect. this situation will practically not occur. attention: these bits can also be set during startup (see chapter 5.7.7.2 ). new state: the flash operation is aborted, the busy flag is cleared and read mode is entered. it is however possible that an ecc failure in the flash sram prevents the busy flag from being cleared. proposed handling by software: the flag should be cleared with ?clear stat us?. the last operation can be determined from the prog and erase flags 1) . in case of an erase operation the affected physical sector must be assumed to be in an invalid state, in case of a program operation only the affected page. other physic al sectors can still be r ead. new program or erase commands must not be issued before the next reset. consequently a reset must be performed (please note that an application reset is sufficient but it does not automatically cl ear the pfoper/dfoper flags). this performs a new flash startup with initialization of the microcode sram. the application must determine from the context which operation fa iled and react accordingly. mostly erasing the addressed sector and re-programming its data is most appropriate. if a ?program page? command was affected and the sector can not be erased (e.g. in flash eeprom emulation) the word-line could be invalidated if needed by marking it with all-one data and the data could be programmed to another empty word-line. only in case of a defective microcode sram the next program or erase operation will incur again this error. as protection against an endless busy a fl ash driver can check for pfoper/dfoper during flash operation. 1) only when both dflash banks were busy, one with program and the other with erase the affected bank and operation can not be determined. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-73 v1.1, 2011-03 pmu, v1.7 note: although this error indicates a failed operat ion it is possible to ignore it and rely on a data verification step to determine if the flash memory has correct data. before re-programming the flash the flow must ensure that a new reset is applied. note: even when the flag is ignored it is recommended to clear it. otherwise all following operations ? including ?sleep? ? could trigger an interrupt even when they are successful (see chapter 5.5.7 , interrupt because of operational error). proer ?protection error? fault conditions: ? password failure. ? erase/write to protected sector. ? erase ucb and protection active. ? write uc-page to protected ucb. attention: a protection violation can even occur when a protection was not explicitly installed by the user. this is the case when the flash startup detects an error and starts the user software with read-only flash (see chapter 5.7.7.2 ). trying to change the flash memory will then cause a proer. new state: read mode is entered. the protection violating command is not executed. proposed handling by software: usually this bit is only set during runtime due to a bug in the software. in case of a password failure a reset must be performed in the other cases the flag can be cleared with ?clear status? or ?reset to read?. after that the corrected sequence can be executed. ver ?verification error? fault conditions: this flag is a warning indication and not an error. it is set when a program or erase operation was completed but with a suboptimal result. this bit is already set when only a single bit is left over-erased or weak ly programmed which would be corrected by the ecc anyhow. however excessive ver occurrence can be caused by operating the flash out of the specified limits, e.g. incorrect voltage or temperature. a ver after programming can also be caused by programming a page whose sect or was not erased correctly (e.g. aborted erase due to power failure). under correct operating conditions a ver afte r programming will practically not occur. a ver after erasing is not unusual. attention: this bit can also be set during startup (see chapter 5.7.7.2 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-74 v1.1, 2011-03 pmu, v1.7 new state: no state change. just the bit is set. proposed handling by software: this bit can be ignored. it should be cleared with ?clear status? or ?reset to read?. in- spec operation of the flash memory must be ensured. if the application allows (timing and data logistics), a more elaborate procedure can be used to get rid of the ver situation: ? ver after program: erase the sector and program the data again. this is only recommended when there are more than 3 program vers in the same sector. when programming the dflash in field (eepr om emulation) igno ring program ver is normally the best solution because its most likely cause are violated operating conditions. take care that never a sector is programmed in which the erase was aborted. in the eeprom emulation the algorithm must ensure this e.g. by programming a marker after finishing successfully the erase. ? ver after erase: the erase operation can be repeated until ver disappears. repeating the erase more than 3 times consecutively for the same sector is not recommended. after that it is better to ignore the ver, program the data and check its readability. again for eeprom emulation its most likely cause are violated operating conditions. therefore it is recommended to repeat the erase at most once or ignore it altogether. for optimizing the quality of flash programming see the following section about handling single-bit ecc errors. note: even when this flag is ignored it is recommended to clear it. otherwise all following operations ? including ?sleep? ? could trigger an interrupt even when they are successful (see chapter 5.5.7 , interrupt because of verify error). pfsber/dfsber ?single-bit error? fault conditions: when reading data or fetching code from pf lash or dflash the ecc evaluation detected a single-bit error (? sbe?) which was corrected. this flag is a warning indication and not an error. a certain amount of single-bit errors must be expected because of known physical effects. new state: no state change. just the bit is set. proposed handling by software: this flag can be used to analyze the stat e of the flash memory. during normal operation it should be ignored. in order to count single-bit errors it must be cleared by ?clear status? or ?reset to read? after each occurrence 1) . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-75 v1.1, 2011-03 pmu, v1.7 usually it is sufficient after programming da ta to compare the programmed data with its reference values ignoring the sbe bits. when there is a comparison error the sector is erased and programmed again. when programming the pflash (end-of-line programming or sw updates) customers can further reduce the probability of future read errors by performing the following check after programming: ? change the read margin to ?high margin 0?. ? verify the data and count the number of sbes. ? when the number of sbes exceeds a certain limit (e.g. 10 in 2 mbyte) the affected sectors could be erased and programmed again. ? repeat the check for ?high margin 1?. ? each sector should be reprogrammed at most once, afterwards sbes can be ignored. in case of eeprom emulation using dflash the verification of programmed data should be done with the normal read level and sbes should be ignored. further advice can be found in chapter 5.7.3 . 5.7.7.2 handling errors during startup the fsr flags are not only used to inform about the success of flash command sequences but they are also used to inform (1) the startup software and (2) the user software about special situations incurred during startup. in order to react on this information these flags must be evaluated after reset before performing any flag clearing sequence as ?clear status? or ?reset to read?. the following two levels of situations are separated: ? fatal level: the user software is not started. a wdt reset is performed. ? error level: the user software is started but the flash memory must not be programmed or erased. ? warning level: the user software is started but a warning is issued. fatal level (wdt reset) these error conditions are evaluated by the startup software which decides that the flash is not operable and thus waits for a wdt reset. the application sees only a longer startup time followed by a wdt reset. the reason for a failed flash startup can be a hardware error or damaged configuration data. 1) further advice: the ecc error flags of the pflash in fsr and xfsr represent the errors found in an aligned block of 256 bits independent of the read data width of the cpu. this is also independent of the addressed range (cached or non-cached). thus errors can?t be counted exactly. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-76 v1.1, 2011-03 pmu, v1.7 error level (flash read-only) in this condition the user software is started but the flash memory must not be programmed or erased. if writability of the flash is mandatory the user software itself has to perform a reset. flash microcode error: fsr bits set: pfoper and dfoper. the user software is started normally but the flash must not be programmed or erased. please note that programming or erasing is not blocked by hardware. issuing program or erase sequences despite this condition is forbidden. warning level these conditions inform the user software about an internally corrected or past error condition. logical sector corrected: fsr bits set: ver. the flash detected that a logical sector er ase was apparently aborted by reset or power failure. in order to maintain re adability of the other logical sectors t he flash tried to repair this state. the aborted erase oper ation must be repeated. see also ?recovery from aborted logical sector erase (?alse?)? on page 5-78 . leftover oper: fsr bits set: pfoper or/and dfoper. the oper flags are only cleared by the command sequence ?clear status? or with a power-on reset. after any other reset a oper flag can still be set when the user software is started. single-bit error in protection: fsr bits set: pfsber. an corrected ecc single-bit error was detected during installation of the protection. 5.7.8 resets during flash operation a reset or power failure during an ongoing fl ash operation (i.e. program or erase) must be considered as violation of stable operating conditions. however the flash was designed to prevent damage to non-addressed flash ranges when the reset is applied as defined in the data sheet. the exceptions are erasing logical sectors and ucbs. aborting an erase process of a logical sector can leave the complete physical sector unreadable. an automatic recovery mechanism is implemented (see chapter 5.7.8.3 ). when an ucb erase is aborted the complete flash can become unusable. there is no recovery implemented because ucbs are usually only erased in a controlled environment. the addressed flash range is left in an undefined state. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-77 v1.1, 2011-03 pmu, v1.7 5.7.8.1 general advice when an erase operation is aborted the addressed logical or physical sector can contain any data. it can even be in a state that doesn?t allow this range to be programmed. when a page programming operation is abort ed the page can still appear as erased (but contain slightly programmed bits), it can a ppear as being correctly programmed (but the data has a lowered retention) or the page contains garbage data. it is also possible that the read data is instable so that depending on the operating conditions different data is read. for the detection of an aborted flash process the flags fsr.prog and fsr.erase could be used as indicator but only when the reset was an application reset. power-on resets can not be determined from any flags. it is not possible to detect an aborted operation simply by reading the flash range. even the margin reads don?t offer a reliable indication. when erasing or programming the pflash usual ly an external instance can notice the reset and simply restart the operation by erasing the flash range and programming it again. 5.7.8.2 advice for eeprom emulation however for the case of eeprom emulation in the dflash this external instance is not existing. a common solution is detecting an abort by performing two operations in sequence and determine after reset from the correctness of the second the completeness of the first operation. e.g. after erasing a dflash sector a page is programmed. after reset the existence of this page proves that the erase process was performed completely. the detection of aborted programming processes can be handled similarly. after programming a block of data an additional page is programmed as marker. when after reset the block of data is readable and the mark er is existent it is ensured that the block of data was programmed without interruption. because often very small amounts of data need to be programmed in eeprom emulation not always a complete page can be spent as marker. the following recipe allows to reduce the marker size to 8 bytes. this recipe violates the rule that a page may be programmed only once. this violation is only allowed for this purpose (eeprom emulation with dflash) and only when the algorithm is robust against disturbed pages (see chapter 5.7.3 ) by repeating a programming step when it detects a failure. robust programming of a page of data with an 8 byte marker: 1. after reset program preferably always first to an even page (?target page?). 2. if the other page on the same word-line contains active data save it to sram (the page can become disturbed because of the 4 programming operations per word- line). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-78 v1.1, 2011-03 pmu, v1.7 3. program the data to the target page (marker bytes of step 5 left as ?0?). 4. perform strict check of the target page and other page (see below). 5. program 8 byte marker to target page (data bytes of step 3 left as ?0?). 6. perform strict check of the target page and other page. 7. in case of any error of the strict check go to the next word-line and program the saved data and the target data again following the same steps. 8. ensure that the algorithm doesn?t repeat unlimited in case of a violation of operating conditions. strict checking of programmed data: 1. ignore correctable errors and the ver flag. 2. switch to tight margin 0. 3. if the data (check the complete page) is not equal to the expected data report an error. 4. if an uncorrectable error is detected report an error. after reset the algorithm has to check the last programmed page if it was programmed completely: 1. read with normal read level. ignore single-bit errors. 2. read 8-byte marker and check for double-bit error. 3. read data part and verify its consistency (e.g. by evaluating a crc). check for double-bit error. 4. if the data part is defective don?t use it (e.g. by invalidating the page). 5. if the data part is ok: a) if the marker is erased the data part could have been programmed incompletely. therefore the data part should not be used or alternatively it could be programmed again to a following page. b) if the marker contains incorrect data the data part was most likely programmed correctly but the marker was programmed incompletely. the page could be used as is or alternatively the data could be programmed again to a following page. c) if the marker is ok the data part was programmed completely and has the full retention. however this is not ensured for the marker part itself. therefore the algorithm must be robust against the ca se that the marker becomes unreadable later. in very specific cases it is allowed to repair data left from an aborted programming operation: if the algorithm can detect that an abort occurred and the algorithm knows which data must be present in the page it is possible to simply redo the programming by programming the same data again. howeve r the previous methods which ?jump? over incorrect data are preferred. 5.7.8.3 recovery from aborted logical sector erase (?alse?) when while erasing one of the logical sectors in pflash a power failure occurs or a reset is triggered the aborted erase process might leave the complete physical sector www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-79 v1.1, 2011-03 pmu, v1.7 unreadable. as often the logical sectors contain important boot code the application might not start anymore. thus the recommended step to repeat the aborted erase after startup can not be realized. the fsi implements two recovery algorithms. the selection between the two is done with the sprec bit (?soft-programming recovery?), i.e. bit 0 of byte 2 in the ucb1 (see ?configuring flash protectio n in the ucb? on page 5-21 ). in both cases the algorithm checks first the sectors ps0 and ps4 for an over-erased state. when this is detected the bit fsr.ver is set to inform the application (see chapter 5.7.7.2 ). after that the algorithm tries to repair this state: ? the default algorithm is selected with sprec = 0. the over-erased logical sector is searched. when finding one this algorithm pr ograms it shortly with all-one data. the other logical sectors become readable again. at least theoretically (especially when operating the device outside of the allowed operating conditions) this algorithm could destroy valid data: when an over-erased logical sector is reported incorrectly during normal startup without a preceding sector erase the data of a logical sector would be overwritten with all-one. ? an alternative algorithm is selected when sprec = 1. this algorithm searches also for the over-erased logical sector as before. for repair a smarter but more time consuming algorithm is performed. the affect ed logical sector is not overwritten with all-one but only the over-erased 0-bits ar e slightly programmed so that they become normal 0-bits again. under all circumstances this algorithm can not destroy any data but when a lot of data has to be repaired the flash startup time can be increased to t fl_sprec . in case this feature is not needed (e.g. because the alternate boot mode ?abm? is used) the execution of the recovery algorithm can be disabled for selected logical sectors with the field ?alsedis? of procon1 . note: if not disabled the alse recovery algorithm is triggered by every reset. however in case of an application reset at high clock frequencies the algorithm ?sprec=1? might not finish before the watchdog is triggered. this can cause a device hang- up. a power-on reset (which switches to a slower clock during startup) lets the repair algorithm finish and the device boot successfully again. attention: the alse repair algorithm was designed to recover the device after a reset during erase in pflash caused by an accidental loss of power. any other possible cause of resets must be prevented by the customer. 5.7.9 ecc for special applications the ecc features need to be considered. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-80 v1.1, 2011-03 pmu, v1.7 using address ecc the address ecc is a vital part of the safe fetch path needed for safety applications. the difference between standard ecc and address (?safety?) ecc is explained in chapter 5.5.6.1 . the calculation of the safety ecc is done over data bits and the address bits 23:3. as side effect erased pflash ranges or pfla sh ranges programmed with the standard ecc will be read with ecc errors. thus the installation of an application using the safety ecc should be done as follows: ? by default the devices starts with the standard ecc enabled. ? the flash loader can enabled the safety ecc by setting fcon.addecc. ? from this point on the data is programmed with the safety ecc to the pflash. erased ranges can not be verified anymore. ? a sector should be programmed completely to ensure that it can be read without ecc errors. ? in order to configure the safety ecc as standard for the next startup the ucb0 shall be programmed so that procon0.addecc is set to ?1?. attention: changing fcon.addecc while accessing the flash (reading, programming, erasing) is forbidden and can cause unpredictable behavior. creating incorrect ecc in safety applications error detection features are usually verified at each startup. in order to verify the detection logic for ecc double-bit errors an address in pflash needs to be programmed with such an error. this can be done by programming a page twice. the data and the calculated ecc bits of both programming steps are effectively or- ed in the flash because only the 1-bits are programmed. with the knowledge of the ecc calculation the data of the first and second programming step can be chosen to create a page containing a double-bit error. programming a page twice is allowed if the other page of this word-line is not programmed because then the word-line is programmed only two times. in the TC1798 the customer can disable automatic ecc generation with eccw.pecencdis. with this feature and with the knowledge of the ecc calculation a page with a double-bit ecc error can be programmed with just one programming step. ready-to-use programming routines for the cr eation of double-bit errors are part of the ifx safety software ?safetcore?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 program memory unit (pmu) users manual 5-81 v1.1, 2011-03 pmu, v1.7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-1 v1.1, 2011-03 lmu, version 1.0 6 local memory unit (lmu) the local memory unit is an sri peripheral providing access to volatile memory resources. it?s primary purpose is to provide 128 kbytes of local memory for general purpose usage but it will also provide access to the separate block of emulation and debug memory (emem) provided in the emulation devices. 6.1 feature list an overview of the features implemented in the lmu follows: ? 128 kbytes of sram ? organised as 64 bit words ? support for byte, half word and word accesses as well as double-word and burst accesses ? interface to the emem of the ed device. ? olda region support. 6.2 local memory the local memory can be used for code execut ion, data storage or overlay memory. the address range of the memory is 90000000 h to 9001ffff h . as well as being accessed via cached (segment 9 h ), the memory can be accessed via non-cached (segment b h ) memory addresses. the memory implements memory integrity checking for error detection and correction. this means that the memory must be initialised before reads are attempted with the integrity checking enabled to avoid generating spurious data corruption errors. initialising before enabling the memory integrity logic allows the local memory to support initialisation using word (32 bit) or smaller writes as well as 64 bit writes. the memory integrity checking is enabled using the lmu_memcon . ded_en bitfield. after a class 3 reset, this is disabled (0 b ). if memory integrity checking is enabled, a read access which fails the integrity check will be terminated with an sri error condition. this behaviour can be changed by setting the lmu_memcon . errdis bit to 1 b . if the bit is set then an sri error will not occur. an ecc error will also be re portedto the scu. the scu w ill use this signal for error indication and triggering of an nmi trap (if enabled). errors will also be flagged using the status bit dberr in the lmu_memcon register. these bits are set when an error condition occurs and can be cleared by a valid write of 0 b to the bit location. this behaviour is not altered by the setting of lmu_memcon . errdis . note that if multiple accesses are occurring to the lmu, it is possible that a write access to clear the error status will be pipelined behind another access which triggers a new error. in this case, the error will be flagged to the scu but not reported in the lmu_memcon register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-2 v1.1, 2011-03 lmu, version 1.0 if the lmu_memcon . ded_en bitfield is set to 0 b after an error has occurred but before and dberr flags ha s been cleared, then the error flag will remain set to allow software to determine the source of the ecc error. local memory performance will be the same as, or better than, the performance of the embedded flash. this applies to both the initial latency of the first word returned and also the incremental latency for each word in the same cache line fetched. if the cpu access can?t be handled by the local memory (e.g. an unsupported sri opcode has been received), an sri bus error is reported by the lmu. this will cause a dse trap. some bitfields of the lmu_memcon register are protected by lmu_memcon . pmic bit. if the data written to the register has the bitfield set to 0 b , no change will be made to bit 23 d to 9 d of the register regardless of the data written to these fields. 6.3 emulation memory (emem) in the emulation device , an emulation memory (emem) of 768 kbytes is provided, which can be used for either calibration via overlay of non-volatile memory or olda (see chapter 6.4 below). the address range of the memory is 9f000000 h to 9f0bffff h (which is identical for all emem sizes in the derivatives). as well as the cached addresses (segment 9 h ), noncached address (segment b h ) accesses can be used for emem accesses via the lmu. the emulation memory interface is a 64-bit wide memory interface that controls the cpu-accesses to the emulation memory in th e emulation device. all widths of write accesses are supported (byte, halfword, word, double-word). cpu-controlled load-modify-store accesses (with ldmst instruction) are supported as separate read and write instructions not as an atomic operation. in the production device, the emem interface is always disabled. a cpu read access from the emulation memory region causes a dse trap by returning an sri bus error. if the emulation memory region read access is initiated by a spb master (e.g. pcp), additionally a spb error inte rrupt can be generated. by default, write accesses to the emulation memory by any master cause an sri bus error trap in the production device. in the emulation device, a sri bus error is returned by the lmu if a read access can?t be handled by the emem, for example, when the cpu accesses a trace memory tile in emem. in this case, the emem access is aborted by the lmu. write accesses which cannot be handled by the emem will fail silently as the write access is completed on the sri bus before being passed to the emem. therefore any error condition encountered by the emem w ill occur after the sri access has completed. the lmu contains a read buffer which is used during emem accesses. the contents of the buffer will be used if a subsequent read access overlaps the address range of the www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-3 v1.1, 2011-03 lmu, version 1.0 data stored in the buffer. coherency with the emem contents is not maintained. if the address stored in the read buffer has been modified in emem by another master on the backbone bus, then invalid data will be returned from the read buffer if the address is then read again via the lmu. 6.4 online data acquisition (olda) and its overlay calibration is additionally supported by an olda memory range of up to 32 kbyte, which is a virtual memory and physically only available, if it is redirected (by the overlay feature of the processor) to internal or external physical memory or to the emem in the emulation device. if olda support is enabled in the lmu, direct write accesses (without redirection) to the olda range are not really executed, and they do not generate a bus error trap 1) . if olda support is not enabled, write accesses will generate a bus error tr ap. olda support is enabled by setting lmu_memcon.oldaen to 1 b . read accesses to the olda range generate a bus error trap, if not redirected to a physically available overlay block. successful accesses to the olda memory range will only take place when the accesses are redirected to real, physical memory. the base address of the virtual olda memory range is a/8fe7 0000 h , the end address is a/8fe7 7fff h . accesses to the olda range are also supported in cached address space. note: in otarx registers, any target address can be selected for redirection, thus also addresses in the olda range. however, the handling of direct accesses to the olda range is completely controlled in the lmu. 6.5 clock control the lmu contains a clock control register, lmu_clc , which allows the lmu to be put into a power saving mode. if lmu_clc.disr is set then the lmu will be disabled and all accesses will be errored unless they are addressed to a register. 1) write accesses to a cached memory address will trigger a read to fill the cache line before the data is written to the cache. this read will trigger a bus error. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-4 v1.1, 2011-03 lmu, version 1.0 6.6 lmu registers the lmu registers are mapped into a 256 byte address space which allows for 64 registers. accesses to unused regist er space will cause an sri bus error. table 6-1 registers address space module base address end address note lmu f870 0800 h f870 08ff h all registers are endinit protected and are accessible in supervisor mode only table 6-2 registers overview short name description offset addr. 1) 1) the absolute register address is calculated as follows: module base address ( table 6-1 ) + offset address (shown in this column) access mode reset class page number read write lmu_clc lmu clock control 0 h sv,be,3 2 sv,e,be ,32 3 6-5 lmu_memcon lmu memory control 4 h sv,be,3 2 sv,e,be ,32 3 6-6 lmu_modid lmu module id 8 h sv, be,32 r,be 3 6-9 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-5 v1.1, 2011-03 lmu, version 1.0 lmu clock control register lmu_clc lmu clock control register (000 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 22 21 20 19 18 17 16 15 res r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res diss disr rrhrw field bits type description disr 0rw lmu disable request bit this bit is used for enable/disable control of the lmu. 0 b lmu disable is not requested 1 b lmu disable is requested diss 1rh lmu disable status bit current state of lmu. 0 b lmu is enabled (default after reset) 1 b lmu is disabled res 31:2 r reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-6 v1.1, 2011-03 lmu, version 1.0 lmu memory control register provides control of the memory integrity error checking, error signalling to the scu and error injection for ecc logic test. also control of the olda function. the register is cleared by a class 3 reset. lmu_memcon lmu memory control register (004 h ) reset value: 0000 0800 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 eccr res4 rh r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dbe rr res 3 res err dis res 2 ded _en res 1 pmi c add err res0 pol dae n old aen rwh r r rw r rw r w rwh r w rw field bits type description oldaen 0rw online data acquisition enabled this bit is used to control trap generation for write accesses to the olda address range. 0 b trap generation on write access to olda memory range is enabled 1 b no trap generated on write access to olda memory range. poldaen 1w protection bit for oldaen 0 b bit protection: bit oldaen remains unchanged after lmu_memcon write. 1 b oldaen can be changed by current write to lmu_memcon res0 6:2 r reserved read and write 0 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-7 v1.1, 2011-03 lmu, version 1.0 adderr 7rwh sri address phase ecc error flag set by hardware when the sri interface detects an ecc error on an incoming transaction. this bit is cleared by writing 0 b but cannot be set by software. 0 b no error has occurred 1 b an ecc error has been observed on an sri transaction addressed to the lmu pmic 8w protection bit for memory integrity control bits will always return 0 b when read 0 b bit protection: bits 23 to 9 remain unchanged after lmu_memcon write. 1 b bits 23 to 9 will be updated by the current write to lmu_memcon res1 9 r reserved read as 0 b . must be written as 0 b ded_en 10 rw memory integrity dual error detection enable 0 b ecc errors in local memory read data do not cause an error indication (interrupt, bus trap, error bits). 1 b ecc errors are enabled. memory errors are flagged to the scu. res2 11 r reserved read as 1 b . must be written as 1 b errdis 12 rw ecc error disable when set sri bus errors caused by ecc errors in data read from the sram will be disabled 0 b normal behaviour. sri error will occur on sram ecc errors if ded_en is set. default after reset 1 b test mode. sri errors will not be generated on an sram ecc error. this does not affect the generation of interrupts. res 13 r reserved res3 14 r reserved read as 0 b field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-8 v1.1, 2011-03 lmu, version 1.0 dberr 15 rwh double bit error status this bit set when a double bit error has occurred when reading from the local memory. the bit is cleared by writing 0 b . writing 1 b has no effect. 0 b read access did not have a double bit error 1 b read access did have a double bit error res4 23:16 r reserved read as 00 h , must be written as 00 h eccr 31:24 rh ecc code for last read access this field contains the ecc code retrieved from the local memory with the last read access. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-9 v1.1, 2011-03 lmu, version 1.0 lmu module id register lmu_modid lmu module id register (008 h ) reset value: 0088 c001 h 31 30 29 28 27 26 25 24 22 21 20 19 18 17 16 15 id_value r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 id_value r field bits type description id_value 31:0 r module identification value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 local memory unit (lmu) users manual 6-10 v1.1, 2011-03 lmu, version 1.0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-1 v1.1, 2011-03 ovc, v1.19 7 data access overlay (ovc) the data overlay functionality provides the capability to redirect data accesses by the tricore to program memory (internal program flash or external memory) to the lmu sram, or to the emulation memory in emulation device ed, or to the external memory. this functionality makes it possible, for example, to modify the application?s test and calibration parameters (which are typically stored in the program memory) during run time of a program. note that read and write data accesses from/to program memory are redirected. attention: as the address translation is implemented in the dmi it is only effective for data accesses by the tricore. instruction fetches by the tricore or accesses by any other master (including the debug interface) are not affected! note: the external memory can be used as overlay memory only in selected devices. please contact infineon sales representative for more information. summary of features and functions ? 16 overlay ranges (?blocks?) configurable for program flash and external memory; ? support redirection to overlay memory located in: ? local memory (lmu) ? emulation memory (emulation device only) ? external ebu space (selected devices only) ? support of up to 2 mb overlay memory address range; ? overlay block size from 32 byte to 128 kbyte; ? support of online data acquisition into range of up to 32 kb and of its overlay; ? overlay memory and block size selected individually for every overlay block; ? all prepared overlay blocks can be enabled with only one register write access; ? programmable flush (invalidate) control for data cache in dmi. 7.1 basic overlay control per overlay block, there are three possibilities for redirection of the original data address, redirection to the lmu sram, redirection to the external memory and redirection to the emulation memory emem, if the chip includes the emulation extension control eec for an emulation device. in all cases, the same overlay mechanism is used. the basic overlay scheme is shown in figure 7-1 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-2 v1.1, 2011-03 ovc, v1.19 figure 7-1 redirection of data accesses to/from code memory to overlay memory in the TC1798, the target memory (program flash, external memory or olda range, see chapter 7.4.1 ) can be divided into a maximum of sixteen memory blocks for redirection into an overlay memory. the base address in target and overlay memory as well as the block size of each overlay block can be individually selected. the possible sizes of overlay blocks depend on the selected over lay memory: blocks in the internal lmu sram are smaller than overlay blocks in emem or external memory. all overlay blocks can be enabled concurrently with one register access. in addition, the data cache may be flushed. the operation of the address translation process is described in figure 7-2 , shown for redirection into the lmu sram. code fetch (unaffected) basicovl_ctr_v0.4 data read/ write data read/ write redirect target block base addresses (otarx) ram program flash overlay memory or emulation device memory or external memory program memory (e.g. flash) redirected block base addresses (rabrx) overlay memory blocks block size (omaskx) olda memory range www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-3 v1.1, 2011-03 ovc, v1.19 figure 7-2 address translation process in each enabled overlay block control logic, three registers hold the information to control the overlay functionality: ? the overlay target address in the overla y target address register otarx, which determines the base address of the program or olda memory data block x to be redirected. ? the base address of the lmu sram, external memory or emem (if emulation device) in the redirected address base register rabrx, and the related enable and control bits. ? a mask in the overlay mask register omaskx , defining the size of the block, the address bits to be checked for an address match, and which bits are used from the redirected address base and which from the original data address. the size of the overlay memory blocks can be 2 n x 32 bytes, with n = 0 to 12. this gives the block size range from 32 bytes to 128 kbytes. the start address of the block can be an integer multiple of the programmed block size (natural page boundary). rabrx omaskx pmu_ovl_ctr_v0.4 seg 4 bits 28 bits 11111..1111111..1000 0000 compare match no match otarx 00000 00000 destination address fixval 00000 obase offset redirected address original data (target) address fixval tbase 5 bits (fix value) overlay memory block x offset address bits overlay memory block x base address bits seg ctrl seg 9/b programmable obase www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-4 v1.1, 2011-03 ovc, v1.19 if the data segment address is a h or 8 h , the segment offset of the original data address is compared with the target base addresses of all overlay blocks which are enabled in rabrx. this bit-wise comparison is qualified by the content of the mask, ignoring the address bits that form the offset into the overlaid block. if there is no match, the original data address is taken to perform the access. if there is a match (see figure 7-2 ): ? the four segment address bits (a h or 8 h ) are either taken directly from the data address (for external overla y memory) or changed to b h and 9 h , respectively (for internal and emulation overlay memory). ? the most significant part of the segment offset, that addresses the base address of the overlay memory, is set to predefined values according to the address map (fixed bits in registers rabrx). ? the part of the target block address, that corresponds to the overlay block base address, is replaced by th e respective overlay block base address bits (bits obase in rabrx, where the corresponding mask bits omask in registers omaskx are set to ?1?). ? the address is completed by the original offset into the block; the number of bits used are determined by the bits set to ?0? in the mask omask. 7.2 online data acquisition (olda) and its overlay calibration is additionally supported by an olda memory range of up to 32 kbyte, which is a virtual memory and physically only avail able, if it is redirected (as described above) to the internal or external overlay memory or to the emem in emulation device. if olda is enabled in pmu, direct write accesses (without redirection) to the olda range are not really executed, and they do not generate a bus error trap. this trap suppression works only for accesses to the non-cached range. read accesses to the olda range generate a bus error trap, if not redirected to a physically available overlay block. the base address of the virtual olda memory range is a/8fe7 0000 h , the end address is a/8fe7 7fff h. accesses to the olda range are also supported in cached address space but there the bus error trap for write accesses is not suppressed. note: in otarx registers, any target address can be selected for redirection, thus also addresses in the olda range. however, the handling of direct accesses to the olda range is completely controlled in the pmu. 7.3 enable control of overlay blocks for basic control of overlay execution, the ocon register is provided with following functionality: ? 16 enable bits (shovenx), one for every overlay block configuration, to support concurrent and parallel switching of up to 16 overlay r anges (blocks); shadow www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-5 v1.1, 2011-03 ovc, v1.19 functionality to the single enable bits in the 16 block control registers (rabrx) provide compatibility to enable-control in tc1766/96. ? one common overlay start bit (ovstrt) to enable all prepared (enabled) overlay configurations by writing all shadow enable bits into the 16 block control registers in parallel (write-only bit); stop-function if all-zeros are written. ? one control flag (dcinval), to be set by the cpu or cerberus, to flush (invalidate) the (clean) data cache lines in the dmi (write-only bit). ? one common overlay stop (ovstp) bit to di sable all overlay configurations in the 16 block control registers (write-only bit), without changing the configuration ? one overlay configured status bit (ovconf), which may be set when overlay registers are configured by the cerberus via jtag interface, and which may be cleared by the cpu after common overlay start (re-direction of all enabled overlay blocks). the control flag in the high byte of the overlay control register ocon (see page 7-14 ) is implemented with additional protection bit, supporting write access to ocon by different users without violation of such control bit which shall remain unchanged. additionally, byte protection is possible by support of byte write accesses to ocon. 7.4 target and overlay memories in the following, the possible target and overlay memories are described. address range of 2 mb is supported for the overlay memori es. the lmu sram and the interface to the emulation memory emem are located in the lmu module. 7.4.1 target memories any data read or write access to the segments 8 h and a h is checked for a valid overlay target address, using all 16 otarx register s concurrently for comparison (if they are enabled for overlay execution). since the otarx registers are writable, any data memory within the segments 8 h and a h may be used for redirection to an overlay memory. thus, the following memories can be selected as target memories: ? program flash ? data flash ? the (virtual) olda memory range ? the external memory. 7.4.2 internal overlay memory the internal lmu sram is available in both the production device and the emulation device. the lmu sram is selected for overlay redirection, if the bits iems and exoms in the block-related rabrx register are zero. the base address of the lmu sram is b/9000 0000 h (non-cached/cached space). during address translation, the upper 9 address bits are set to b/90 h 0 b , respectively. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-6 v1.1, 2011-03 ovc, v1.19 7.4.3 emulation overlay memory the emem can only be selected for overlay bl ocks, if the chip is an emulation device ed. the emulation memory emem is selected for overlay execution, if the block-related rabrx bits iems=1 and exoms=0. the base address of the emulation memory is b/9f00 0000 h . during address translation, the upper 9 address bits are set to bf h 0 b (non-cached) or to 9f h 0 b (cached space). 7.4.4 external overlay memory if an external memory is available in the emulation device system, it can also be used for calibration via program memory or olda overlay. the overlay blocks can be located in the external memory only in selected dev ices.the external memory is selected for overlay execution, if the block-related ra brx bit exoms=1 (iems value is ignored). the base address of the emulation memory is a/8300 0000 h . during address translation, the upper 9 address bits are set to a3 h 0 b (non-cached) or to 83 h 0 b (cached space). 7.5 change of overlay parameters and overlay start when changing the overlay parameters of a block or when switching a block from one overlay memory to another overlay memory, it must be ensured that the respective oven bit in register rabrx is reset, before the block parameters are set properly, and then the overlay block is enabled again. otherwise, unintended access redirections may occur. it is especially supported to enable (start ) all prepared overlay blocks concurrently, when using the shadow mechanism for the oven bits in the one ocon register instead of the single oven bits in the different rabrx registers (see chapter 7.3 ). with this function it is possible to switch directly from one set of overlay blocks to another set of overlay blocks, without any restricti on concerning the block-specific use of (available) overlay memories. note: the overlay control does not prevent configuring the translation logic incorrectly so that memory accesses are translated to not implemented or forbidden memory ranges. 7.6 concurrent matches and access performance concurrent matches in more than one enabled overlay block are not supported. when an address matches two, or mo re, of the enabled overlay bl ocks, an exception is raised and the memory access is not performed. a load operation with multiple matches on overlay ranges, raises a data access sy nchronous error (dse) trap, and a store operation raises data access asynchronous error (dae) trap. in such case, relevant trap information registers: data sy nchronous trap register (dstr), data www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-7 v1.1, 2011-03 ovc, v1.19 asynchronous trap register (datr), and data error address register (deadd) are updated, see dmi registers chapter for more information. the dynamic address translation for redirection to the overlay memory is executed without performance penalty. 7.7 overlay control registers figure 7-3 shows all the overlay control registers associated with control of the overlay memory blocks. overlay control registers overview figure 7-3 overlay control registers the address space for the overlay control registers is as follows: table 7-1 registers address space of ovc registers module base address end address note ovc f87f fb00 h f87f fbff h table 7-2 registers overview register 1) short name register long name offset address access mode 2) descript- ion see read write rabrx redirected address base register x (x = 0-15) 0020 h + x ? c h u, sv, 32 sv, 32 page 7-9 otarx overlay target address register x (x = 0-15) 0024 h + x ? c h u, sv, 32 sv, 32 page 7-11 omaskx ocon rabrx otarx overlay registers ovregs oenable www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-8 v1.1, 2011-03 ovc, v1.19 note: accesses to free/not used register addresses within the ovc address space are not executed and not serv iced with a bus error trap. register descriptions for each of the 16 overlay me mory blocks (indicated by inde x x), three registers control the overlay operation and the memory selection: ? the redirected address base register rabrx, which holds the base address of the overlay memory to be used (with fixed address bits) and of the overlay memory block within the overlay memory, and some control bits. ? the overlay target address register otarx, which holds the base address of the memory block in internal flash, in external memory or in the olda memory being overlaid (and being compared with original data address). ? the overlay mask register omaskx, which determines which bits (from rabrx) are used for the base address (of overla y memory and block) and which bits (of original data address) are directly used as offset within the block (remaining unchanged). additionally, for general overlay control the registers ocon and oenable are provided. all overlay block and control registers are rese t to their default values with the application reset. a special debug reset is not considered. omaskx overlay mask register x (x = 0-15) 0028 h + x ? c h u, sv, 32 sv, 32 page 7-12 ocon overlay control register 00e0 h u, sv, 32 sv, 32 page 7-14 oenable overlay enable register 00e8 h u, sv, 32 sv, e, 32 page 7-16 1) the ovc register short names are extended with the module name prefix ?ovc_?. 2) symbol u: access permitted in user mode 0 or 1 symbol sv: access permitted in supervisor mode symbol e: endinit-protected register symbol 32: only 32-bit word access is permitted table 7-2 registers overview (cont?d) register 1) short name register long name offset address access mode 2) descript- ion see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-9 v1.1, 2011-03 ovc, v1.19 the rabrx register is defined as follows: rabrx (x=0-15) redirected address base register x (20 h +x*c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ov en iems exo ms rc0 fixval obase rwh rw rw r r rw 1514131211109876543210 obase 0 rw r field bits type description obase [22:5] rw overlay block base address this bit field holds the base address of the overlay memory block in the overlay memory. fixval [27:23] r fixed value base address of the selected overlay memory within segment. 00000 b lmu sram base address (when exoms=0 and iems = 0) 11110 b emem base address (when exoms=0 and iems = 1) 00110 b emem base address (when exoms=1) all other values are reserved. should be written with the same value. rc0 28 r reserved control bit reserved for future control expansions. read returns 0. must be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-10 v1.1, 2011-03 ovc, v1.19 exoms 29 rw external overlay memory select if set, the external memory is used as overlay memory. this is only available in selected devices. 0 b overlay memory of block x type is selected by iems. 1 b overlay memory of block x is the external memory. iems 30 rw internal or emulation/external memory select if exoms is not set, iems selects the type of the overlay memory. if exoms is set, iems value is ignored. 0 b internal lmu sram is selected as overlay memory. 1 b emulation memory emem is selected as overlay memory. iems must be written with zero in production device. oven 31 rwh overlay enabled this bit controls whether or not the overlay function of overlay block x is enabled. 0 b overlay function of block x is disabled. 1 b overlay function of block x is enabled. this bit can also be changed via its shadow bit in the ocon register. 0 [4:0] r fixed value read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-11 v1.1, 2011-03 ovc, v1.19 the overlay target address register otarx is defined as follows: otarx (x=0-15) overlay target address register x (24 h +x*c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 tseg tbase rrw 1514131211109876543210 tbase 0 rw r field bits type description tbase [27:5] rw target base this field holds the base address of the overlay memory block in the target memory (program flash or olda memory or external memory). for each tbase bit: if the corresponding bit in omask register is set to one tbase bit value is used in the address match. if the corresponding bit in omask register is set to zero tbase bit value is ignored. tseg [31:28] r target segment (reserved) this bit field is reserved for future use, to select a segment. in TC1798 implementation, any access to segments 8 h , or a h will be checked for a valid base address. returns 0 if read; should be written with 0. 0 [4:0] r reserved reads as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-12 v1.1, 2011-03 ovc, v1.19 the overlay mask register omaskx determines the size of the overlay memory block x (by the number of least significant zero?s). it also determines which address bits will participate in the address compare for the block base address (all high-order one?s), and in case of address match which bits are ta ken from rabrx (as many high order bits as defined in omaskx for address compare) and which bits are used from the original data address as offset within the block (all low order bits related to zero values in omaskx). omaskx (x=0-15) overlay mask register x (28 h +x*c h ) reset value: 0fff ffe0 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0one oma sk rrrw 1514131211109876543210 omask 0 rw r field bits type description omask [16:5] rw overlay address mask this bitfield determines the overlay block size and the bits used for address comparison and translation. 000000000000 b , 128 kbyte block size 100000000000 b , 64 kbyte block size 110000000000 b , 32 kbyte block size [...] 111111111110 b 64 byte block size 111111111111 b 32 byte block size ?zero? bits determine the corresponding address bits which are not used in the address comparison and thus determine the block size; corresponding final address bits are derived from the original data address. ?one? bits determine the corresponding address bits which are used for the address comparison; corresponding final address bits are derived from rabrx register in case of address match. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-13 v1.1, 2011-03 ovc, v1.19 one [27:17] r fixed ?1? values corresponding address bits are participating in the address comparison. corresponding final address bits are taken from rabrx. 0 [4:0], [31:28] r fixed ?0? values corresponding address bits are not used in the address comparison. corresponding final address bits are taken from the original data address. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-14 v1.1, 2011-03 ovc, v1.19 the overlay control register ocon is defined as follows: ocon overlay control register (00e0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 000000 pov con f ov con f 00000 dc in val ov stp ov st rt rrrrrrwrwrrrrrwww 1514131211109876543210 shovenx rw field bits type description shovenx (x=0-15) xrw shadow overlay enable x 0 b overlay block x is disabled with next ovstrt 1 b overlay block x is enabled with next ovstrt for each of the 16 overlay blocks (indicated by index x), one enable (disable) bit is provided. ovstrt 16 w overlay start 0 b no action 1 b all 16 shadow overlay enable bits shoven ar loaded into the related oven bits in rabrx registers in parallel. related to the shoven bits state, the overlay blocks are concurrently enabled or disabled. return 0 if read. ovstp 17 w overlay stop 0 b no action 1 b all 16 oven bits in rabrx registers are cleared in parallel independently of the shoven bits and without changing the shoven bits. return 0 if read. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-15 v1.1, 2011-03 ovc, v1.19 dcinval 18 w data cache invalidate no function in devices without data cache in tricore. 0 b no action 1 b data cache lines in dmi are invalidated (flushed). note: per write modified cache lines are not invalidated. 1) return 0 if read. ovconf 24 rw overlay configured overlay configured status bit 0 b overlay is not configured or it has been already started by cpu 1 b overlay block control registers are configured and ready for overlay start this bit may be used as handshake bit between a debug device (via jtag interface and cerberus) and the cpu. povconf 25 w protection bit for ovconf 0 b bit protection: bit ovconf remains unchanged with register ocon write 1 b ovconf can be changed with actual write access to register ocon this bit enables ovconf-write during ocon write. return 0 if read. 0 [23:19] , [31:26] r reserved read/write 0. 1) because the data cache is a writeback cache (not a wr itethrough cache; therefore saving of modified data in cache has to be performed by the user) it is highly re commended to use only non-cached accesses for overlaid (redirected) accesses to the target memory (normally the program flash), if write accesses are involved. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-16 v1.1, 2011-03 ovc, v1.19 the overlay enable register oenable is defined as follows: this register is endinit-protected. oenable overlay enable register (00e8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ove n rrw field bits type description oven 0rw overlay enable 0 b ovc is disabled. all overlay redirections are disabled. 1 b ovc is enabled. 0 [31:1] r reserved read/write 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 data access overlay (ovc) users manual 7-17 v1.1, 2011-03 ovc, v1.19 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-1 v1.1, 2011-03 boot_TC1798_um, v1.0 8 bootrom content TC1798 bootrom from user point of view consists of two parts: ? startup software (short name ssw); ? software modules implementing additional functions (bootstrap loaders). 8.1 startup software the startup software is the first software executed after a chip reset. this means, the first value loaded into the program counter register pc points to first address inside bootrom - the ssw entry-point. the startup software contains procedures to initialize the device depending on: ? values applied to external (configuration-) pins; ? the type of event which has triggered the ssw-execution (the last reset event); ? information previously stored into the flash configuration sector; ? the current state of special bits/fields in dedicated register/memory locations. the ssw also calls - in case - other firmware modules. 8.1.1 boot options summary this chapter summarizes the TC1798 startup configurations. internal start in this basic startup mode, the first user inst ruction is fetched from the internal program flash of the device. bootloader modes different bootstrap loader routines are used in these modes to download code/data into the program scratchpad memory pspr. alternate boot modes in these modes, program code is started from user-defined address but only if at least one of the two check-conditions is satisfied. if both the conditions are false - a bootstrap loader routine is started to download the code into the device, this code is afterwards started by the ssw. secure booting this startup option is only supported in devices having secure hardware extension (she) implemented and available for the user. when selected, secure booting implements an extension of the startup procedure in internal start and alternate boot modes , using she to check the user code. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-2 v1.1, 2011-03 boot_TC1798_um, v1.0 8.1.2 startup software main flow in next chapters, the ssw functionality is specified, during different execution-steps (refer to figure 8-1 ) and upon various configuration settings. figure 8-1 TC1798 firmware: ssw main flow firmware start prepare to run ssw evaluate the last reset-source set respectively the ssw flags initial ssw settings evaluate the startup configuration (update from pins, sw or keep the last) perform flash rampup (wait for ready) basic flash configuration & settings chip configuration & initialization select & execute startup mode bootloaders alternate boot modes prepare internal start prepare external start error ! invalid startup configuration final chip settings including debug system setup & harr jump to user code firmware end flash handling startup mode processing exiting the ssw am-basic_flow-um.vsd 03.08.10 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-3 v1.1, 2011-03 boot_TC1798_um, v1.0 8.1.2.1 entering the startup software the first ssw instruction is fetched after any reset from address afff?c000 h in bootrom. 8.1.2.2 initial handling of the startup configuration the ssw determines which startup mode to execute based on the configuration coded in scu_ststat.hwcfg bit field. the value in this bit field can be updated in different ways: 1. with values latched at the configuration pins p0[7:0] upon the rising reset-edge this happens when scu_ststat.ludis=0, therefore after any system (class 0) reset, and after other resets - depending on ludis bit. 2. with values from scu_swrstcon.swcfg bit field this happens upon software reset - triggered by writing 1 to scu_swrstcon.swrstreq - if at the same time software boot configuration is selected - scu_swrstcon.swboot=1. due to the way hwcfg-bit field is handled by TC1798 hardware, at this point of its flow the ssw does not need to do some special processing regarding the startup configuration. besides of setting ssw-internal flag: ? ?reset configuration updated? flag ? is set to 1 if - the last reset has been a software-reset with software-configuration ( (scu_rststat.sw=1) and (scu_swrstcon.swboot=1) ) ? if the last reset is of a type not stated in a) - the flag is set to the inverted value of scu_ststat.ludis bit 8.1.2.3 flash rampup the flash rampup is automatically started after every reset by hardware (refer to pmu chapter, program and data flash). therefore the ssw does not initiate the rampup but only observes the flags in flash sfrs and reacts accordingly. the flash rampup is further handled by the ssw. basically the flash ?busy? status is checked as the section below describes. if after the time-out the flash is still ?busy?, then: ? ?flash rampup? error-code is created ? the flash is put into sleep mode ? a jump to the ssw error-pro cessing routine is performed flash rampup flash ?busy? status is continuously checked but no longer than for a defined time-out. once all of the flash array banks are ?ready? (pbusy=0), the startup procedure www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-4 v1.1, 2011-03 boot_TC1798_um, v1.0 continues immediately. as far as the rampup duration varies from device to device and upon operational conditions, the overall startup ti me respectively will be slightly different. 8.1.2.4 basic device settings the target of this functional module is to initialize several TC1798-registers with the values, which will be first seen by the user - or generally available - after exiting the ssw. following device resources are initialized here: ? jtag device identification register (jtagid.jtag_id) ? unique chip id - it is written by the ssw at the beginning of dspr - 4 words starting at d000?0000 h . 8.1.2.5 select and prepare startup modes TC1798 user startup configurations and modes are summarized in table 8-1 . the ssw evaluates the configuration in scu_ststat.hwcfg and device-start is prepared in accordance to the mode currently selected. basically, the user start address is prepared in stadd, as well as additional functions are executed in case - like bootstrap loaders and alternate boot. table 8-1 startup modes supported in TC1798 hwcfg[7:0] startup mode pins used 11xxxxxx b internal start from flash 2 011xxxxx b internal start from flash 3 010xxxxx b bootstrap loader mode, generic bootloader at can pins 3 10101xxx b bootstrap loader mode, asc bootloader 5 10100xxx b alternate boot mode (abm),asc bootloader on fail 5 1011xxxx b alternate boot mode, generic bootloader at can pins on fail 4 1000xxxx b alternate boot mode, generic bootloader at can pins on fail 4 1001c1ax b 1) 1) c bit - pins used for bootloading: 0 - asc (asc bootloader);1 - can (generic bootloader) a bit - ebu arbitration mode: 0 - participant; 1 - arbiter (previously referred as ?external master?) e bit - ebu configuration: 0 - default; 1 - automatic external alternate boot modes 7 0010e1ax b 1) external start modes 7 0001xxxx b reserved 7 000011xx b reserved 6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-5 v1.1, 2011-03 boot_TC1798_um, v1.0 internal start this is the basic TC1798 type of operation in which the user code is started out of the internal flash memory. the user start address stadd is set to the beginning of internal flash memory module at address a000?0000 h . external starts the user start address stadd is set to address a300?0000 h in external ebu space. bootstrap loader modes the selected bootstrap loader (these routines are described in chapter 8.2 ) is executed only if the ssw-flag ?reset configuration updated? is set (refer to chapter 8.1.2.2 ). this is to avoid multiple executions of the bootstrap loader and to start directly the code already downloaded after some - intended to be ?application only? - reset events, for example after a watchdog timer reset which has been configured as class 3 reset. the supported bootloader selections are: ? asc bootloader - asc communication protocol via asc pins ? generic bootloader via can pins - t he communication protocol is automatically selected by the ssw between asc and can after downloading (in case) the code, the user start address stadd is set to the beginning of program scratchpad ram at c000?0000 h . alternate boot modes there are variety of such modes in TC1798, whereas the differences are in: 1. where the headers and (in case being available) the application code is located a) in internal flash memory b) in external memory 2. which bootloader to execute upon an error in abm header a) asc bootloader b) generic bootloader at can pins the ssw flow in these modes is: ? evaluate the startup configuration to decide where are the headers located ? check the headers - refer to the description in chapter 8.1.3.1 - and react accordingly: ? if the check is ok for one of the headers - set the user start address stadd to the respective value from this correct header (stadabmx) and continue www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-6 v1.1, 2011-03 boot_TC1798_um, v1.0 ? if the header-checks fail - start a bootloa der (asc/generic) co rresponding to the startup configuration. after downloading the code, the user start address stadd is set to the beginning of program scratchpad ram at c000?0000 h . secure booting is possible in alternate start mode - see below. secure boot option handling if she-module is available - secure booting is supported for the device. in such a case the ssw performs additional steps in different startup modes, as below described. ?in internal start mode: 1. check the she-bit sequentially in sheboot2, shebo ot0 and sheboot1 registers a) if all the bits are zero - secure booting is not requested, then: -call she_non_secure_boot procedure -continue ssw (executing internal start) b) if bit she=1 is found in a shebootx register - continue with 2. 2. read size from the respective bitfield in shebootx register 3. call she_secure_boot procedure with parameters bl_start=stadd (a000?0000 h ) and bl_size=shebootx.size 4. check the bgd-bit tn the respective shebootx register (with she=1) a) if shebootx.bgd=1 (background secure boot is selected) - continue ssw with user code start without waiting for she-operation finished b) if shebootx.bgd=0 (not background secure boot is selected) - wait until she_secure_boot procedure is finished ?in external and bootstrap loader modes: call she_non_secure_boot procedure. ?in alternate boot modes: there are two cases regarding she- handling in alternate boot mode 1. if one of the header-checks with crc pass ed -secure boot procedure is executed to check the user code by she 2. if both the header-checks wi th crc failed - bootstrap l oader mode is started and she_non_secure_boot pr ocedure called there. 8.1.2.6 final chip settings the last device configuration steps performed by the ssw include: unique chip id installation the unique chip id represents a 16-byte value which is written by the ssw after any reset at the beginning of dspr - starting from address d000?0000 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-7 v1.1, 2011-03 boot_TC1798_um, v1.0 calibration data installation the calibration data (for dts as well as plac eholder for future extensions) represents a 128-byte value which is written after power-on reset by the ssw into dspr starting from address d000?0018 h . flash protection control the ssw processing on flash protecti on differs upon the startup mode currently selected: 1. in modes where the user code is started fr om internal flash - internal start, internal abm with crc ok: a) if read protection is not activated (fcon.rpa=0): - ssw enables all the specific (dma, pcp, debug) data fetches from flash - no ssw action is needed regarding code and data fetches from flash - they are generally enabled by hardware. b) if read protection is activated (fcon.rpa=1): - ssw enables code fetch from flash; - ssw enables data fetch from flash in ge neral as well as in particular for dma (fcon.ddfdma=0) and pcp; - ssw disables data fetch from flash for the debug controller. 2. in modes where the user code is not started from internal flash - all bootstrap loader modes, all abm modes after the crc fails: a) if read protection is not activated (fcon.rpa=0) - the same functionality as upon a start from internal flash - refer to 1.a) above; b) if read protection is activated (fcon.rpa=1): - ssw disables all code and data fetches from flash - ssw disables all the specific (dma, pcp, debug) data fetches from flash. at the end of this module, accesses to configuration sector data are disabled. debug system handling as first point of this processing, the ssw internal flag unlock debug interface is set, with exception of the following case only: ? internal start with active flash protection in any other case, debugging is no security risk as far as either the protection is not activated or reading from flash is not possible. next, halt after reset is prepared if requested. besides a halt itself is no security risk - even the system is stopped but a channel (communicati on/debug) is still needed to access internal resources - this feature is configured and enabled only if the ssw-flag ?unlock debug if? is set. the ssw processing here is as follows: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-8 v1.1, 2011-03 boot_TC1798_um, v1.0 ? check either external (debug) access to the device will be generally granted (ssw_ internal_flag=1) ? if not -> exit this procedure ? check either halt after reset is requested (ostate.harr=1) ? if not -> exit this procedure ? configure a break after make breakpoint at the last ssw instruction ? write the respective address into code segment protection lower bound register mpr_cpr0_0l ? configure signal assertion from memory protection system to core debug controller upon instruction fetch access match with mpr_cpr0_0l (write mpr_cpm0.bl0=1) ? configure debug action in trigger event 0 control register tr0evt as follows: - halt on break - evta := 010 b - break after make - bbm := 0 - suspend output active - susp := 1 ? enable on-chip debug support system. note: the final debug-related operation - unlocking (in case) the debug interface - is performed later - refer to chapter 8.1.2.7 . 8.1.2.7 ending the ssw and starting the user code the last steps executed by the ssw are: ? activate the startup protection - as a result, the watchdog timer starts to run ? if the debug interface is to be unlocked (ssw_unlock_dif=1): ? perform a write to oec with if_lck=0 and if_lck_p=1 (protection bit). with this operation ostate.if_lck gets reset to 0 and the debug interface is unlocked - the ioclient (cerberus) is allowed to enter rw mode and therefore can access potentially all the system resources. ? restore default content of registers modified by ssw ? jump to the first user instruction at address stadd. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-9 v1.1, 2011-03 boot_TC1798_um, v1.0 8.1.3 specific ssw features below some specific procedur es are described, which are us ed at several places during the ssw flow. the definition is given separately here for a more readable form of the complete document. 8.1.3.1 header check in alternate boot modes the alternate boot modes (abm) in TC1798 are intended to start program code already available at arbitrary user-defined address if a check-condition is satisfied. if the check- condition fails - a bootstrap loader routine is invoked in accordance to the current startup mode. the address of the code to be started together with all information needed to verify the check-condition are contained in dedicated memory areas named headers. the address of the code to be started together with all information needed to verify the check-condition are contained in dedicated memory areas named headers. the headers can be located in internal flash memory of the device, whereas the locations are defined: ? header 0 - base address a001?ffe0 h ; end address a001?ffff h ? header 1 - base address a000?ffe0 h ; end address a000?ffff h if external starts are also supported as startup configurations, respectively so-call external alternate boot modes are defined. in such a case, the headers are located in external ebu address space as follows: ? header 0, external - base address a300?ffe0 h ; end address a300?ffff h ? header 1, external - base address a308?ffe0 h ; end address a308?ffff h note: in all the external abm, the ssw first trie s to fetch the configuration word as check for availability of an external memory. if this fetch fails to return valid data - the situation is considered as error in the header and a bootloader is started. in alternate boot mode of TC1798 two headers are defined - header 0 and header 1 (referred as abm.hd0 and abm.hd1), th e user code can be started from: ? up to two different addresses - if secure booting is not selected ? one only address - if secure boot option is activated. the headers are 32 bytes long, containing information in accordance to table 8-2 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-10 v1.1, 2011-03 boot_TC1798_um, v1.0 header 0 is checked first, if failed and secure booting is not selected - header 1 is checked next. where the check gives ok, the full start address is taken from the respective header field stadabmx (index x=0,1 for header 0,1). the validation procedure executes crc calculation based on a 32-bit polynomial: f(x) = x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1 (8.1) if secure booting is activated and the crc calculation pass - the user code is also checked by she module. the check procedure is as follows: 1. check the abm header id (abmhid) at offsets 04 h ..07 h : a) if abmhdid=stdhid or sechid or bsechid - continue with 2. b) else - exit the check-procedure for this header with error. 2. calculate the crc of the first 24 bytes from the abm header (refer to table 8-2 ) - process the fields stadabm...crcrange at offsets 00 h ...17 h a) compare the result with the crchead value (offset 18 h ) - if ok - continue with 2.b) - if not - exit the check-procedure for this header with error. b) inverse the result value and compare with crchead (offset 1c h ) - if ok - continue with 3. - if not - exit the check-procedure for this header with error. table 8-2 abm header structure offset addr. size byte field name description 00 h 4 stadabm user code start address 04 h 4 abmhdid abm header id (confirmation code): standard id = dead beef h (stdhid) secure id = code 0000 h (sechid) 1) background id = code 0001 h (bsechid) 1) 1) only in header 0 08 h 4 chkstart 2) 2) address of the first word to be checked. memory range to be checked - start address 0c h 4chkend 3) 3) address of the last word to be checked. memory range to be checked - end address 10 h 4 crcrange check result for the memory range 14 h 4 crcrange inverted check result for the memory range 18 h 4 crchead check result for the abm header (offset 00h..17h) 1c h 4 crchead inverted check result for the abm header www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-11 v1.1, 2011-03 boot_TC1798_um, v1.0 3. calculate the crc over the memory address range chkstart...chkend (start- and end- addresses taken from offsets 08 h and 0c h respectively) a) compare the result with the crcrange value (offset 10 h ) - if ok - continue with 3. b) - if not - exit the check-procedure for this header with error. b) inverse the result value and compare with crcrange (offset 14 h ) - if ok - continue with 4. - if not - exit the check-procedure for this header with error. 4. check the abm header id (abmhid) at offsets 04 h ..07 h : a) if abmhdid=stdhid - continue ssw to start the user-code from stadabmx address. b) if abmhdid=sechid or bsechid - continue with 5. c) else - exit the check-procedure for this header with error. 5. check are the requested memory addresses correct: a) both chkend and chkstart must be between a000 0000 h and a11f ffff h or between 8000 0000 h and 811f ffff h (cached or not-cached area) occupying only addresses reserved for pflash and not overlapping a ram or external area b) chkstart must be aligned to 128 byte (i.e. the 7 ls bit = zero) - if both the conditions are met - continue with 6. - if not - exit the check-procedure for this header with error. 6. check with which header id the procedure passed till this point: a) if abmhdid=bsechid selecting background secure boot - continue ssw, secure boot will be triggered later by ssw b) if abmhdid=sechid selecting secure boot not background - then: - start secure boot and wait until finished - continue ssw to start the user-code from stadabmx address. note: as seen from the above definitions, both in secure and in standard abm modes only error in header or wrong crc prevents starting the used code. the result from code-check done by she is not relevant for the user code start but affects the further she behavior. in case the check procedure is exited with error: ? if header 0 is currently proce ssed - restart the procedure from 1. using header 1 ? else - jump either to asc- or to generic- (can pins) bootloader according to the startup mode currently configured in hwcfg. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-12 v1.1, 2011-03 boot_TC1798_um, v1.0 8.1.4 startup e rrors handling there are a number of check-points during the startup software execution where errors can be raised (refer to the ssw block-diagrams). the processing upon an error is as follows: ? an exit-code according to the error is stored into cbs_comdata register (refer to table 8-3 ? the watchdog timer reset is configured to class 3 ? all code- and data- fetches from flash are disabled ? access to the flash config sector is disabled ? startup protection is activated, which activation starts the watchdog timer ? the debug interface is unlocked ? an endless loop is executed (jump to itself) as far as the watchdog timer is already enabled, the endless loop is aborted by a wdt reset which triggers a new ssw-execution. if this new startup fails again, the following error-processing will lead to the same endless loop. respectively, a second wdt reset will occur being already a locked reset, which can be aborted only by a next power-on sequence. table 8-3 errors reported by the TC1798 ssw coding in d12/comdata description 00000001 h bootcode wrongly called after exiting startup mode 00000002 h flash error during rampup 00000003 h error in flash configuration sector 00000004 h invalid startup mode selected 00000008 h multican module not available but can bootloader selected 00000018 h can0 node not available (due to atm) but can bootloader selected 00000009 h asc module not available but asc bootloader selected 00000010 h error in bootrom 00000011 h 00000012 h error in she module 00000013 h error in eray module during initialization (no xtal clock) 0000004x h trap of class x (0..7) raised during ssw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-13 v1.1, 2011-03 boot_TC1798_um, v1.0 8.2 bootstrap loaders these routines provide mechanisms to load an user program via selected interface by moving code into program scratchpad ram. the loaded code is started after exiting the bootrom. two interfaces can be utilized for downloading in TC1798 - asc and can. besides two separate procedures are supporting any of these interfaces/protocols, they have a common first part. in other words, there is one entry-point bl_entry for all bootloader procedures. 8.2.1 common procedures for all bootloaders the first such a common procedure is to re configure the clock system in case the last reset is a power-on. this reconfiguration switches from the initial pll freerunning mode (vco base frequency) to prescaler mode with f fpi :f osc =1:2. therefore the fpi-peripherals (including multican and asc modules) run at half the frequency of an external crystal which mu st be connected between xtal1/xtal2 pins if a bootloader mode will be selected upon power- on. this 1:2 relation must be taken into account when selecting the host speed for downloading. for example, when using the multican bootstrap loader f osc should be greater or equal to 20 mhz for a baud rate of 1 mbit/s. attention: this clock-switch to external oscillator upon power-on is overwritten by a switch back to pll freerunning mode at the end of ssw . therefore if it is desi red after downloading to continue communication with the same baudrate, the u ser code must first reinstall: - pll prescaler mode (scu_pllcon0.vcobyp:=0) and - k1 divider 1:1 (scu_pllcon1.kdiv:=00 h ). upon any other reset but not power-on, the clock configuration - respectively the system frequency - remains the same as previously selected. next, depending on the bootloader-type currently configured in hwcfg a pin is selected as receive-data input (rxd) which will be evaluated on the following step. note, that still no further pin-configuration is done here - e. g. no assignment to a specific (asc/can) module functionality - but only the pin input-va lue is directly checked in this procedure. the procedure waits to receive a low-level pul se at rxd and measures its duration - the time between the falling and rising edges - into the bl_meas work variable. then, the ssw checks the startup config uration in hwcfg: ? upon asc bootloader mode - a jump to the respective routine ( chapter 8.2.2 ) is directly executed ? upon generic bootloader mode - the type of interface (asc/can) currently used must be detected by the ssw. for this the rxd pin is checked until: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-14 v1.1, 2011-03 boot_TC1798_um, v1.0 ? low level is found there - then a jump to can bootstrap loader will be executed; or ? no edge is found for a time 6 time longer than the value in bl_meas - then asc bootstrap loader will be executed. this interface-detection procedure is based on the following principles: ? an asc-bootloader host sends one only start byte and then waits for a response from the target system ? a can-bootloader host sends a complete frame, whereas no more than 5 consecutive bits can be sent having equal logical levels - i.e. after two consecutive edges for a given time dt, in any case another edge must follow within the next time- frame of 6*dt. 8.2.2 asc bootstrap loader the asc bootloading routine implements the following steps: ? rxd/txd pins configuration is done in accordance to the TC1798 definitions, as well as depending either the rout ine is invoked upon ?asc bootloader?-startup mode (asc-only pins are used) or following an asc-protocol detection upon ?generic bootloader?-mode (can/asc-shar ed pins are used but co nfigured to asc module) ? baudrate calculation is done based on the value already captured ? asc0 is initialized (without enabling the receiver) to the baudrate as determined, 8 data and 1 stop bit ? acknowledge byte d5 h is sent to the host indicating the device is ready to accept a data transfer ? after the acknowledge byte is transmitted, the receiver is enabled ? the bootloader enters a loop waiting to receive exactly 128 bytes which are stored as 32 words in program scratchpad ram starting from address c000?0000 h once 128 bytes are received, the ssw starts the user code from address c000?0000 h . 8.2.3 can bootstrap loader the can bootstrap loader transfers program code/data via node 0 of the multican module into the program scratchpad ram. data is transferred from the external host to the TC1798 using eight-byte data frames. t he number of data frames to be received is programmable and determined by the 16-bit data message count value dmsgc. the communication between TC1798 and external host is based on the following three can standard frames: ? initialization frame - sent by the external host to the TC1798 ? acknowledge frame - sent by the TC1798 to the external host ? data frame(s) - sent by the external host to the TC1798 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-15 v1.1, 2011-03 boot_TC1798_um, v1.0 the initialization frame is used in the TC1798 for baud rate detection. after a successful baud rate detection is reported to the external host by sending the acknowledge frame, data is transmitted using data frames. initialization phase the first task is to determine the can baud rate at which the external host is communicating. this task requires the external host to send initialization frames continuously to the TC1798. the first two data bytes of the initialization frame include a 2-byte baud rate detection pattern (5555 h ), an 11-bit (2-byte) i dentifier ackid for the acknowledge frame, a 16-bit data message count value dmsgc, and an 11-bit (2-byte) identifier dmsgid to be used by the data frame(s). the can baud rate is determined by analyzing the received baud rate detection pattern (5555 h ) and the baud rate registers of the multican module are set accordingly. the TC1798 is now ready to receive can frames with the baud rate of the external host. acknowledge phase in the acknowledge phase, the bootstrap loader waits until it receives the next correctly recognized initialization frame from the external host, and acknowledges this frame by generating a dominant bit in its ack slot. afterwards, the bootstrap loader transmits an acknowledge frame back to the external host, indicating that it is now ready to receive data frames. the acknowledge frame uses the message identifier ackid that has been received with the initialization frame. data transmission phase in the data transmission phase, data frames are sent by the external host and received by the TC1798. the data frames use the 11- bit data message identifier dmsgid that has been sent with the initialization frame. eight data bytes are transmitted with each data frame. the first data byte is stored in program scratchpad ram starting from address c000?0000 h . consecutive data bytes are stored at incrementing addresses. both communication partners evaluate the data message count dmsgc until the requested number of can data frames has been transmitted. after the reception of the last can data frame, the ssw starts the user code from address c000?0000 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-16 v1.1, 2011-03 boot_TC1798_um, v1.0 8.3 additional informa tion and usage hints the information below is provided to help the customer to use properly the functionality of TC1798 startup software. 8.3.1 conditions upon user code start after ssw, the user code execution starts upon the following basic conditions within TC1798: ? system clock ? after power-on/pors t: pll in freerunning mode, 16.66 mhz system frequency (nominal) note: when in bootloader mode - keep in mind the attention-note at the beginning of chapter 8.2.1 ( common procedures for all bootloaders )! ? otherwise: as previously configured - no change due to the bootcode ? interrupts and traps ? all maskable interrupts are disabled by icr.ie=0 ? all nmi-traps are disabled in scu_trapdis ? watchdog-timer - running in time-out mode 8.3.2 rams handling no ram initialization is performed by the startup software in TC1798. attention: in regard to TC1798 rams after startup the user must consider: ? if ecc will be enabled for a ram module - correct initial content of this memory must be assured ? upon application software start, error detection is disabled in all memories 8.3.3 influencing the next ssw-execution by writing 1 to syscon.setludis (no pr otection), the user software will prevent automatic update of scu_ststat.hwcfg upon the next application reset. if such setting is active when a bootstrap loader mode is configured in ststat.hwcfg bitfield, after the next application reset the bootloader routine will not be executed but directly the application-code will be started from spram. the ludis=1 setting w ill have effect until a system/power -on reset which will force the syscon register to its reset value with ludis=0. therefore, upon system/power-on reset the startup hw-configuration (scu_ststat.hwcfg) is always updated from pins. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-17 v1.1, 2011-03 boot_TC1798_um, v1.0 8.3.4 TC1798 registers modified by ssw TC1798 ssw modifies some registers against their reset value - refer to table 8-4 . additionally to the above, registers can be affected by dynamic conditions/events during ssw execution: 1. asc/can configuration (clock settings, pin usage etc.) registers in bsl modes - depending on the start-up configuration and baudrate. the settings in these registers allow user software generally to continue using the same interface (asc/can) after downloading - for this, keep attention to the note at page 8-13 . 2. pllstat, trapstat registers - flag(s) c an be set due to event /exception(s) during boot phase like loss-of-lock upo n power-on and system reset. this is not critical for the application be cause the traps are generally disabled (in scu_trapdis) afte r any reset. table 8-4 TC1798 registers modified by ssw register value comments scu_ststat[18], [7:0] extben, hwcfg according to the current start-up mode scu_stcon[15] 1 start-up protection activated eray_sedcon 0000 0000 h sed disabled in eray rams eray_dedcon 0000 0000 h ded disabled in eray rams eray_clc 0000 0003 h eray module disabled flashx_marp[15], flash0_mard[15] 0 flash double-bit error traps enabled flashx_fcon [22:17] 000000 b 111111 b if flash is not protected or internal start mode if flash is protected and not internal start mode cbs_oec[17] 1 if flash is not protected or internal start mode www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bootrom content users manual 8-18 v1.1, 2011-03 boot_TC1798_um, v1.0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-1 v1.1, 2011-03 memmaps, v1.4 9 memory maps this chapter gives an overview of the tc 1798 memory map, and describes the address locations and access possibilities for the units, memories, and reserved areas as ?seen? from the two different on-chip buses? point of view. the TC1798 has the following memories ? program memory unit (pmu) with ? 4 mbyte of program flash memory (pflash) ? 192 kbyte of data flash memory (dflash) ? 16 kbyte of boot rom (brom) ? program memory interface (pmi) ? 32 kbyte of instruction scratch-pad sram (pspr) 1) ? 16 kbyte of instruction cache (icache) 2) ? data memory interface (dmi) ? 128 kbyte of data scratch-pad sram (dspr) 1) ? 16 kbyte of data cache (dcache) 2) ? local memory unit (lmu) ? 128 kbyte of sram (lmuram) 1) ? pcp memory ? 32 kbyte of pcp code memory (cmem) 1) ? 16 kbyte of pcp data memory (pram) 1) furthermore, the TC1798 has two on-chip buses: ? system peripheral bus (spb) ? shared resource interconnect (sri) note: after porst the ecc (single bit) correction is enabled, signalling of corrected ecc errors is disabled, signalling of detected non-correctable ecc errors is enabled. 1) before used by the application, the memory has to be initialized by customer sw by overwriting it one time 2) when mapping cache sram into the memory map an d accessing as normal sram : the memory has to be initialized by customer sw before using it as normal sram by overwriting it one time www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-2 v1.1, 2011-03 memmaps, v1.4 9.1 what is new the target for the audomax devices memory map is to keep it compatible to audong and audofuture wherever it is possible. this means to keep memory space/flash segment start addresses and peripheral cont rol register address spaces where they where mapped to in audong and audofuture. major differences of the TC1798 memory map compared to audofuture, tc1784 and tc1387: ? general: ? flash sizes, sram sizes and module instances adapted to the TC1798 requirements ? adaptation of the system address map to the tc1.6 requirements ? some modules shifted (start address / segment) ? segment 8 / a : ? pmu1 pflash start address shifted ? external ebu space start address shifted, size reduced to 192 mb ? ovram removed, lmu sram to be used as overlay memory instead ? emulation memory was shifted into segment 9 / b. ? segment 8 : ? dflash removed from segment 8 ? segment 9: ? added lmu sram ? added emulation memory ? segment a : ? dflash bank0/1 start address shifted, size of dflash bank 0/1 increased ? address ranges for she ke yflash banks 0/1 added ? segment b: ? added lmu sram ? added emulation memory ? segment c : ? segment is reserved for tc1.6 pmi srams (program scratch pad sram, icache 1) sram, ptag sram 1) , image of program scratch pad, ptag 1) and icache srams) ? segment d : ? removed external ebu space ? segment is reserved for tc1.6 dmi srams (data scratch pad sram, dcache 1) and dtag srams 1) , image of data scratch pad, dtag 1) and dcache srams) ? segment c / d: ? renamed spram to pspr (program scratch pad sram) ? renamed ldram to dspr (data scratch pad sram) 1) mapping of cache and tag srams into the memory map is controlled by cpu register smacon. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-3 v1.1, 2011-03 memmaps, v1.4 ? lower half of segment c / d is fixed non-cached bahiour ? physical memory attributes (pma) of upper half can be defined now via tc1.6 control registers (cached, non-cached) ? segment e : ? reserved. there is no fpi->cpu bus a ddress translation any more in sri/tc1.6 systems. ? segment f : ? shifted ssc0, ssc1, ssc2 to keep ssc3 and the ssc guardian together ? lower part of the segment f reserved for fpi peripheral control registers, upper part reserved for sri peripheral control registers ? added ssc2 / ssc3 module ? added ssc guardian instances sscg01 and sscg21 ? added port16 and port17 modules ? added adc3 kernel ? added sdma (safe dma module) ? added bus monitor unit (bmu) ? removed lmbh, lfi and tc1.3 pmi/dmi registers ? added xbar_sri module ? added lmu module ? added flexible crc engine (fce) ? added secure hardware extension module (she) ? replaced tc1.3 against tc1.6 register ranges www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-4 v1.1, 2011-03 memmaps, v1.4 9.2 how to read the address maps the bus-specific address maps describe how the different bus master devices react on accesses to on-chip memories and modules, and which address ranges are valid or invalid for the corresponding buses. the fpi bus address map shows the system addresses from the point of view of the spb master agents. spb master agents are pcp2 and is the dma 1) . the sri address map shows the system addresse s from the point of view of the sri master agents. sri master agents are pmi, dmi and dma 1) . the sfi is a bi-directional bridge between sr i and spb and theref ore not mentioned here as sri or spb master in the address map. the sfi is fully transparen t and does not include an address translation mechanism. 1) dma including: dma move engines and module connected to the dma peripheral interface like mli modules. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-5 v1.1, 2011-03 memmaps, v1.4 table 9-1 defines the acronyms and other term s that are used in the address maps ( table 9-2 and table 9-3 ). table 9-1 definition of acronyms and terms term description ?be means ?bus error? generation. ?bet means ?bus error & trap? generation. spbbe a bus access is terminated with a bus error on the spb. spbbet a bus access is terminated with a bus error on the spb and a dse trap (read access) or dae trap (write access). sribe a bus access is terminated with a bus error on the sri. sribet a bus access is terminated with a bus error on the sri and a dse trap (read access) or dae trap (write access). access a bus access is allowed and is executed. ignore a bus access is ignored and is not executed. no bus error is generated. trap a dse trap (read access) or dae trap (write access) is generated. 32 only 32-bit word bus accesses are permitted to that register/address range. ne a bus access generates no bus error, although the bus access points to an undefined address or address range. this is valid e.g. for cpu accesses (mtcr/mfcr) to undefined addresses in the csfr range. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-6 v1.1, 2011-03 memmaps, v1.4 9.3 contents of the segments this section summarizes the contents of the segments. segments 0-7 these segments are reserved segments in the TC1798. segment 8 this memory segment allows cacheable acce ss to pflash, external ebu space, brom. accesses from the dma move engines, cerberus or mli to this segment are processed by the dma sri master interface on the sri bus. segment 9 this memory segment allows cacheable access to lmu sram and emem (emulation device only). segment 10 this memory segment allows non-cacheabl e access to pflash, dflash, external ebu space, brom. from the dma point of view, move engine, cerberus and mli accesses to this segment are processed by the dma sri master interface on the sri bus. segment 11 this memory segment allows non cacheable access to lmu sram and emem (emulation device only). segment 12 this memory segment allows access to th e program scratch pad sram (pspr), ptag sram and the program cache (icache). icache and ptag sram can be only acce ssed if the program cache is disabled 1) . the attribute of this segment (cached / non-cached) can be partially configured 1) . segment 13 this memory segment allows access to the data scratch pad sram (dspr), dtag sram and the data cache (dcache). dcache and dtag sram can be only accessed if the data cache is disabled 1) . 1) see cpu chapter, register smacon, for details. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-7 v1.1, 2011-03 memmaps, v1.4 the attribute of this segment (cached / non-cached) can be partially configured. segment 14 this memory segment is reserved in the TC1798. segment 15 this memory segment allows accesses to all sfrs, csfrs, the pcp memories and the mli transfer windows. access from dma move engines, cerberus and mli to the lower 128 mb of this segment are processed by the dma fpi master interface on the spb bus, to the upper 128 mb of this segment by the dma sri master interface on the sri bus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-8 v1.1, 2011-03 memmaps, v1.4 9.4 address map of the on chip bus system this chapter describes the system address map as it is seen from the sri and spb bus masters pmi, dmi, pcp, dma, sdma, she, mli and cerberus. 9.4.1 segments 0 to 14 table 9-2 shows the address map of segments 0 to 14. table 9-2 on chip bus address map of segment 0 to 14 seg- ment address range size description access type read 1) write 2) 0-7 0000 0000 h - 0000 0007 h 8 byte reserved (virtual address space) spbbe spbbe 0000 0008 h - 7fff ffff h 8 256 mbyte spbbe spbbe 8 8000 0000 h - 801f ffff h 2 mbyte program flash 0 (pflash0) access access 2) 8020 0000 h - 803f ffff h 2 mbyte reserved sribe sribe 8040 0000 h - 807f ffff h - reserved sribe & spbbe sribe 8080 0000 h - 809f ffff h 2 mbyte program flash 1 (pflash1) access access 2) 80a0 0000 h - 80ff ffff h - reserved sribe sribe 8100 0000 h - 82ff ffff h - reserved sribe sribe 8300 0000 h - 8eff ffff h 192 mbyte external ebu space access access 8f00 0000 h - 8f1f ffff h - reserved sribe sribe 8f20 0000 h - 8fe6 ffff h - reserved sribe sribe 8fe7 0000 h - 8fe7 7fff h 32 kbyte online da ta acquisition (olda) sribe access 3) / sribe 8fe7 8000 h - 8fff bfff h - reserved sribe sribe www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-9 v1.1, 2011-03 memmaps, v1.4 8fff c000 h - 8fff ffff h 16 kbyte boot rom (brom) access sribe 9 9000 0000 h - 9001 ffff h 128 kbyte lmu sram access access 9002 0000 h - 9eff ffff h - reserved sribe sribe 9f00 0000 h - 9f0b ffff h 768 kbyte reserved for TC1798 emulation device memory (emem) sribe sribe 9f0c 0000 h - 9fff ffff h - reserved sribe sribe 10 a000 0000 h - a01f ffff h 2 mbyte program flash 0 (pflash0) access access 2) a020 0000 h - a03f ffff h - reserved sribe sribe a040 0000 h - a07f ffff h - reserved sribe sribe a080 0000 h - a09f ffff h 2 mbyte program flash 1 (pflash1) access access 2) a0a0 0000 h - a0ff ffff h - reserved sribe sribe a100 0000 h - a2ff ffff h - reserved sribe sribe a300 0000 h - aeff ffff h 192 mbyte external ebu space access access af00 0000 h - af01 7fff h 96 kbyte data flash (dflash) bank 0 access access 2) af01 8000 h - af07 ffff h - reserved sribe sribe af08 0000 h - af09 7fff h 96 kbyte data flash (dflash) bank 1 access access 2) af09 8000 h - af0f ffff h - reserved sribe sribe table 9-2 on chip bus address map of segment 0 to 14 (cont?d) seg- ment address range size description access type read 1) write 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-10 v1.1, 2011-03 memmaps, v1.4 af10 0000 h - af1f ffff h ~ 1 mbyte reserved sribe sribe af20 0000 h - af20 1fff h - reserved sribe access 2) s ribe af20 2000 h - af20 3fff h - reserved sribe sribe af20 4000 h - af2f ffff h - reserved sribe sribe af30 0000 h - afe6 ffff h - reserved sribe sribe afe7 0000 h - afe7 7fff h 32 kbyte online da ta acquisition (olda) sribe access 3) / sribe afe7 8000 h - afff bfff h - reserved sribe sribe afff c000 h - afff ffff h 16 kbyte boot rom (brom) access sribe 11 b000 0000 h - b001 ffff h 128 kbyte lmu sram access access b002 0000 h - beff ffff h - reserved sribe sribe bf00 0000 h - bf0b ffff h 768 kbyte reserved for TC1798 emulation device memory (emem) sribe sribe bf0c 0000 h - bfff ffff h - reserved sribe sribe 12 c000 0000 h - c000 7fff h 32 kbyte program scratch-pad sram (pspr) access access c000 8000 h - c01f ffff h - reserved sribe sribe c020 0000 h - c020 3fff h 16 kbyte program cache sram (icache) access 4) / sribe access 4) / sribe c020 4000 h - c02f ffff h - reserved sribe sribe table 9-2 on chip bus address map of segment 0 to 14 (cont?d) seg- ment address range size description access type read 1) write 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-11 v1.1, 2011-03 memmaps, v1.4 c030 0000 h - c030 01ff h 0.5 kbyte program cache tag sram 5) (ptag) access 4) / sribe access 4) / sribe c030 0200 h - c7ff ffff h - reserved sribe sribe c800 0000 h - c800 7fff h 32 kbyte program scratch-pad sram (pspr) access access c800 8000 h - c81f ffff h - reserved sribe sribe c820 0000 h - c820 3fff h 16 kbyte program cache sram (icache) access 4) / sribe access 4) / sribe c820 4000 h - c82f ffff h - reserved sribe sribe c830 0000 h - c830 01ff h 0.5 kbyte program cache tag sram 5) (ptag) access 4) / sribe access 4) / sribe c830 0200 h - cfff ffff h - reserved sribe sribe 13 d000 0000 h - d001 ffff h 128 kbyte data scratch-pad sram (dspr) access access d002 0000 h - d01f ffff h - reserved sribe sribe d020 0000 h - d020 3fff h 16 kbyte data cache sram (dcache) access 4) / sribe access 4) / sribe d020 4000 h - d02f ffff h - reserved sribe sribe d030 0000 h - d030 01ff h 0.5 kbyte data cache tag sram 5) (dtag) access 4) / sribe access 4) / sribe d030 0200 h - d7ff ffff h - reserved sribe sribe d040 0000 h - d7ff ffff h - reserved sribe sribe d800 0000 h - d801 ffff h 128 kbyte data scratch-pad sram (dspr) access access table 9-2 on chip bus address map of segment 0 to 14 (cont?d) seg- ment address range size description access type read 1) write 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-12 v1.1, 2011-03 memmaps, v1.4 d802 0000 h - d81f ffff h - reserved sribe sribe d820 0000 h - d820 3fff h 16 kbyte data cache sram (dcache) access 4) access 4) d820 4000 h - d82f ffff h - reserved sribe sribe d830 0000 h - d830 01ff h 0.5 kbyte data cache tag sram 5) (dtag) access 4) access 4) d830 0000 h - dfff ffff h - reserved sribe sribe 14 e000 0000 h - efff ffff h - reserved sribe sribe 15 f000 0000 h - ffff ffff h 256 mbyte see table 9-3 1) a read transaction through the sri to fpi bridge that is terminated with bus error will result in bus errors on sri and fpi (valid for transactions from fpi to sri and sri to fpi) 2) write access to flash resources are handled by the pmu module (flash command sequence, see pmu chapter for details) 3) online data acquisition address space can be disabled/enabled via pmu control register bit lmu_memcon.oldaen. cpu access to olda address space via segment 8 (cached) results in sribe independent of the lmu_memcon.oldaen bit setting. 4) icache/dcache srams (and the corresponding tag srams) can be only accessed when mapped into the address space (icache / dcache disabled, see cpu chapter for details)via 32 bit access and only with 64 bit aligned address. 5) tag srams are not meant to be used as general srams and can be accessed only with single data access and only with 64 bit aligned address. mapping of tag srams in the address map can be used as additional option for memory testing. table 9-2 on chip bus address map of segment 0 to 14 (cont?d) seg- ment address range size description access type read 1) write 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-13 v1.1, 2011-03 memmaps, v1.4 9.4.2 segment 15 table 9-3 shows the address map of segment 15 as seen from the sri and spb bus masters pmi, dmi, pcp, sh e, dma, sdma and ocds. please note that table 9-3 describes the mapping of modules to segment f. the details of the module address ranges can be found in the module chapters register overview. table 9-3 on chip bus address map of segment 15 unit address range size access type read write reserved f000 0000 h - f000 00ff h ? spbbe spbbe system peripheral bus control unit (sbcu) f000 0100 h - f000 01ff h 256 byte access access system timer (stm) f000 0200 h - f000 02ff h 256 byte access access reserved f000 0300 h - f000 03ff h ? spbbe spbbe on-chip debug support (cerberus) f000 0400 h - f000 04ff h 256 byte access access system control unit (scu) and watchdog timer (wdt) f000 0500 h - f000 06ff h 2 256 byte access access reserved f000 0700 h - f000 07ff h ? spbbe spbbe microsecond bus controller 0 (msc0) f000 0800 h - f000 08ff h 256 byte access access microsecond bus controller 1 (msc1) f000 0900 h - f000 09ff h 256 byte access access async./sync. seri al interface 0 (asc0) f000 0a00 h - f000 0aff h 256 byte access access async./sync. seri al interface 1 (asc1) f000 0b00 h - f000 0bff h 256 byte access access port 0 f000 0c00 h - f000 0cff h 256 byte access access port 1 f000 0d00 h - f000 0dff h 256 byte access access port 2 f000 0e00 h - f000 0eff h 256 byte access access www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-14 v1.1, 2011-03 memmaps, v1.4 port 3 f000 0f00 h - f000 0fff h 256 byte access access port 4 f000 1000 h - f000 10ff h 256 byte access access port 5 f000 1100 h - f000 11ff h 256 byte access access port 6 f000 1200 h - f000 12ff h 256 byte access access port 7 f000 1300 h - f000 13ff h 256 byte access access port 8 f000 1400 h - f000 14ff h 256 byte access access port 9 f000 1500 h - f000 15ff h 256 byte access access port 10 f000 1600 h - f000 16ff h 256 byte access access port 11 f000 1700 h - f000 17ff h 256 byte access access general purpose timer array (gpta0) f000 1800 h - f000 1fff h 8 256 byte access access general purpose timer array (gpta1) f000 2000 h - f000 27ff h 8 256 byte access access local timer cell array (ltca2) f000 2800 h - f000 2fff h 8 256 byte access access capture/compare unit 6 0 (ccu60) f000 3000 h - f000 30ff h 256 byte access access capture/compare unit 6 1 (ccu61) f000 3100 h - f000 31ff h 256 byte access access capture/compare unit 6 2 (ccu62) f000 3200 h - f000 32ff h 256 byte access access capture/compare unit 6 3 (ccu63) f000 3300 h - f000 33ff h 256 byte access access table 9-3 on chip bus address map of segment 15 (cont?d) unit address range size access type read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-15 v1.1, 2011-03 memmaps, v1.4 general purpose timer 12 0 (gpt120) f000 3400 h - f000 34ff h 256 byte access access general purpose timer 12 1 (gpt121) f000 3500 h - f000 35ff h 256 byte access access reserved f000 3600 h - f000 37ff h ? spbbe spbbe safety direct memory access controller (sdma) f000 3800 h - f000 3aff h 3 256 byte access access reserved f000 3b00 h - f000 3bff h ? spbbe spbbe direct memory access controller (dma) f000 3c00 h - f000 3eff h 3 256 byte access access reserved f000 3f00 h - f000 3fff h ? spbbe spbbe multican controller (can) f000 4000 h - f000 7fff h 16 kbyte access access reserved f000 8000 h - f000 ffff h ? spbbe spbbe flexray tm protocol controller (e-ray) f001 0000 h - f001 7fff h 32 kbyte access access reserved f001 8000 h - f003 ffff h ? spbbe spbbe pcp reserved f004 0000 h - f004 3eff h ? spbbe spbbe pcp registers f004 3f00 h - f004 3fff h 256 byte access access reserved f004 4000 h - f004 ffff h ? spbbe spbbe pcp data memory (pram) f005 0000 h - f005 3fff h 16 kbyte ne, 32 ne, 32 reserved f005 4000 h - f005 ffff h ? spbbe spbbe table 9-3 on chip bus address map of segment 15 (cont?d) unit address range size access type read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-16 v1.1, 2011-03 memmaps, v1.4 pcp code memory (cmem) f006 0000 h - f006 7fff h 32 kbyte ne, 32 ne, 32 reserved f006 8000 h - f007 ffff h ? spbbe spbbe reserved f008 0000 h - f010 03ff h ? spbbe spbbe fast analog-to-digital converter (fadc) f010 0400 h - f010 04ff h 256 byte access access reserved f010 0500 h - f010 0fff h ? spbbe spbbe analog-to-digital converter 0 (adc0) f010 1000 h - f010 13ff h 4 256 byte access access analog-to-digital converter 1 (adc1) f010 1400 h - f010 17ff h 4 256 byte access access analog-to-digital converter 2 (adc2) f010 1800 h - f010 1bff h 4 256 byte access access analog-to-digital converter 3 (adc3) f010 1c00 h - f010 1fff h 4 256 byte access access reserved f010 2000 h - f010 bfff h ? spbbe spbbe micro link interface 0 (mli0) f010 c000 h - f010 c0ff h 256 byte access access micro link interface 1 (mli1) f010 c100 h - f010 c1ff h 256 byte access access memory checker (mchk) f010 c200 h - f010 c2ff h 256 byte access access reserved f010 c300 h - f01d ffff h ? spbbe spbbe mli0 small transfer windows f01e 0000 h - f01e 7fff h 4 8 kbyte access access mli1 small transfer windows f01e 8000 h - f01e ffff h 4 8 kbyte access access table 9-3 on chip bus address map of segment 15 (cont?d) unit address range size access type read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-17 v1.1, 2011-03 memmaps, v1.4 reserved f01f 0000 h - f01f ffff h ? spbbe spbbe mli0 large transfer windows f020 0000 h - f023ffff h 4 64 kbyte access access mli1 large transfer windows f024 0000 h - f027 ffff h 4 64 kbyte access access reserved f028 0000 h - f02f ffff h ? spbbe spbbe port 12 f030 0000 h - f030 00ff h 256 byte access access port 13 f030 0100 h - f030 01ff h 256 byte access access port 14 f030 0200 h - f030 02ff h 256 byte access access port 15 f030 0300 h - f030 03ff h 256 byte access access port 16 f030 0400 h - f030 04ff h 256 byte access access port 17 f030 0500 h - f030 05ff h 256 byte access access port 18 f030 0600 h - f030 06ff h 256 byte access access reserved f030 0700 h - f030 ffff h ? spbbe spbbe synchronous serial interface 0 (ssc0) f031 0000 h - f031 00ff h 256 byte access access synchronous serial interface 1 (ssc1) f031 0100 h - f031 01ff h 256 byte access access synchronous serial interface 2 (ssc2) f031 0200 h - f031 02ff h 256 byte access access synchronous serial interface 3 (ssc3) f031 0300 h - f031 03ff h 256 byte access access table 9-3 on chip bus address map of segment 15 (cont?d) unit address range size access type read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-18 v1.1, 2011-03 memmaps, v1.4 reserved f031 0400 h - f031 07ff h ? spbbe spbbe guardian for ssc0 (sscg0) f031 0800 h - f031 09ff h 2x256 byte access access guardian for ssc1 (sscg1) f031 0a00 h - f031 0bff h 2x256 byte access access guardian for ssc2 (sscg2) f031 0c00 h - f031 0dff h 2x256 byte access access guardian for ssc3 (sscg3) f031 0e00 h - f031 0fff h 2x256 byte access access reserved f031 1000 h - f031 ffff h ? spbbe spbbe flexible crc engine (fce) f032 0000 h - f032 00ff h 256 byte access access reserved f032 0100 h - f032 01ff h ? spbbe spbbe secure hardware extension (she) f032 0200 h - f032 02ff h 256 byte access access reserved f032 0300 h - f032 0fff h ? spbbe spbbe sent module (sent) f032 1000 h - f032 19ff h 10x256 byte access access reserved f032 1a00 h - f032 2fff h ? spbbe spbbe bus monitor unit registers (bmu) f032 3000 h - f032 31ff h 2x256 byte access access reserved f032 3200 h - f032 3fff h ? spbbe spbbe bus monitor unit memory (bmuram) f032 4000 h - f032 5fff h 8 kbyte access access reserved f032 6000 h - f7e0 feff h ? spbbe spbbe table 9-3 on chip bus address map of segment 15 (cont?d) unit address range size access type read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-19 v1.1, 2011-03 memmaps, v1.4 cpu cpu slave interface registers (cps) f7e0 ff00 h - f7e0 ffff h 256 byte access access cpu core sfrs & gprs f7e1 0000 h - f7e1 ffff h 64 kbyte access access reserved f7e2 0000 h - f7ff ffff h ? spbbe spbbe external bus unit (ebu) f800 0000 h - f800 03ff h 1 kbyte access access reserved f800 0400 h - f800 04ff h ?sribe& spbbe sribe program memory unit 0 (pmu0) f800 0500 h - f800 05ff h 256 byte access access program memory unit 1 (pmu1) f800 0600 h - f800 06ff h 256 byte access access reserved f800 0700 h - f800 0fff h ?sribe& spbbe sribe flash register (pmu0) f800 1000 h - f800 23ff h 5 kbyte access access reserved f800 2400 h - f800 2fff h ?sribe& spbbe sribe flash register pmu1 f800 3000 h - f800 43ff h 5 kbyte access access reserved f800 4400 h - f801 00ff h ?sribe& spbbe sribe reserved f801 0100 h - f86f ffff h ?sribe& spbbe sribe sri crossbar (xbar_sri) f870 0000 h - f870 04ff h 5x256 byte access access reserved f870 0500 h - f870 07ff h ?sribe& spbbe sribe local memory unit (lmu) f870 0800 h - f870 08ff h 256 byte access access table 9-3 on chip bus address map of segment 15 (cont?d) unit address range size access type read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-20 v1.1, 2011-03 memmaps, v1.4 reserved f870 0900 h - f87f faff h ?sribe& spbbe sribe overlay control unit (ovc) f87f fb00 h - f87f fbff h 256 byte access access reserved f87f fc00 h - ffff ffff h ?sribe& spbbe sribe table 9-3 on chip bus address map of segment 15 (cont?d) unit address range size access type read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-21 v1.1, 2011-03 memmaps, v1.4 9.5 memory module access restrictions table 9-4 describes which type of accesses are possible to the different memories in the TC1798. table 9-4 possible memory accesses 1) 1) y means: supported. - means: not supported memory bit byte half-word word double-word rmw r w r w r w r w pmi 2) 2) the module also supports sri 2-word and 4-word block read and write accesses. pspr y y y y y y y y y ptag 3) 3) tag srams are not meant to be used as general sr ams and can be accessed only via 32 bit single data access and only with 64 bit aligned address. mapping of tag srams in the address map can be used as additional option for memory testing. - ----yy- y pcache y y y y y y y y y dmi 2) dspr y y y y y y y y y dtag 3) - ----yy- - dcache y y y y y y y y y lmu 2) lmuram y y y y y y y y y pmu brom ? y ? y ? y ? y ? pflash ? y ? y ? y y y y dflash ? y ? y ? y y y y pcp 4) 4) the module also supports fpi/spb 4-word and 8-word block read and write accesses. cmem y ????yyy y pram y ? ? ? ? y y y y bmu 4) bmuram ? ? ? ? ? y y y y www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 memory maps users manual 9-22 v1.1, 2011-03 memmaps, v1.4 9.6 side effects from modules to data scratch pad sram (dspr) please note that the dspr is also used by boot routine and can be used by the cpu for system tasks: ? the boot routine copies some devices informations during the startup into the dspr (see chapter bootrom content) ? dspr can be used as context save area (for details see chapter cpu subsystem) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-1 v1.1, 2011-03 ports, v1.11 10 general purpose i/o port s and peripheral i/o lines (ports) the TC1798 has 252 digital general purpose input/output (gpio) port lines which are connected to the on-chip periphera l units. they are divided into: table 10-1 ports overview port pins base address end address note p0 16 f000 0c00 h f000 0cff h +hwcfg, +e-ray, emstop, ccu6/gpt12 p1 16 f000 0d00 h f000 0dff h emstop, ccu6/gpt12 p2 14 f000 0e00 h f000 0eff h emstop, ccu6/gpt12 p3 16 f000 0f00 h f000 0fff h emstop, ccu6/gpt12 p4 16 f000 1000 h f000 10ff h emstop, ssc2, ccu6/gpt12 p5 16 f000 1100 h f000 11ff h extended with lvds, emstop, ccu6/gpt12 p6 12 f000 1200 h f000 12ff h 6.4 to 6.15, ccu6/gpt12 p7 8 f000 1300 h f000 13ff h ssc3 p8 8 f000 1400 h f000 14ff h emstop, sent, ccu6/gpt12 p9 9 -> 15 f000 1500 h f000 15ff h emstop only 6 added. no change to the old ones. brkin , brkout . sent, ttcan, ccu6/gpt12 p10 4 -> 6 f000 1600 h f000 16ff h fully changed, - ebu p11 16 f000 1700 h f000 17ff h - p12 8 f030 0000 h f030 00ff h - p13 16 f030 0100 h f030 01ff h emstop www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-2 v1.1, 2011-03 ports, v1.11 the external bus interface (ebu) has its own set of dedicated signal lines. further details are described in the port-specific sections of this chapter. p14 16 f030 0200 h f030 02ff h emstop, ccu6/gpt12 p15 16 f030 0300 h f030 03ff h ccu6/gpt12 p16 16 f030 0400 h f030 04ff h ddr burst flash p17 16 f030 0500 h f030 05ff h analog / digital sent p18 2 f030 0600 h f030 06ff h ssc2 table 10-1 ports overview (cont?d) port pins base address end address note www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-3 v1.1, 2011-03 ports, v1.11 10.1 basic port operation figure 10-1 is a general block diagram of a TC1798 gpio port slice. figure 10-1 general structure of a port pin each port line has a number of control and data bits, enabling very flexible usage of the line. each port pin (except port 10) can be configured for input or output operation. in input mode (default after reset), the output driver is switched off (high-impedance). the actual voltage level present at the port pin is translated into a logical 0 or 1 via a schmitt- trigger device and can be read via the read-only register pn_in. an input signal can also be connected directly to the various inputs of the peripheral units (altdatain). the pin alt1 pn_out pn_in pn_omr pn_iocr alt2 1 1 pull devices 2 4 2 ac cess to port registers via the fpi bus alternate data signals or other control lines fr om peri pher a ls input stage output stage pad 4 alt3 1 hw_out 1 hw_dir 2 msb af_standard_ebcport_structure_8.vsd con trol 3 hw_en altin enabq pn_esr & emstop altsel0,1 2 od, dir con trol port slice endq1 1 dq1 1 pn_pdrx 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-4 v1.1, 2011-03 ports, v1.11 function of the input line from the pin to the input register pn_in and to altdatain is independent of whether the port pin operates as input or output. this means that when the port is in output mode, the level of the pin can be read by software via pn_in or a peripheral can use the pin level as an input. in output mode, the output driver is activated and drives the value supplied through the multiplexer to the port pin. switching between input and output mode is accomplished through the pn_iocr register, which enabl es or disables the output driver. if a peripheral unit uses a gpio port line as a bi-directional i/o line, register pn_iocr has to be written for input or output selection. the pn_iocr register further controls the driver type of the output driver, and determ ines whether an internal weak pull-up or pull- down device is alternatively connected to the pin when used as an input. this offers additional advantages in an application. the output multiplexer in front of the output driver selects the signal source for the gpio line when used as output. if the pin is used as general-purpose output, the multiplexer is switched by software (pn_iocr register) to the output data register pn_out. software can set or clear the bit in pn_out, and therefore it can directly influence the state of the port pin. if the on-chip peripheral units use the pin for output signals, the alternate output lines alt1 to alt3 can be switched via the multiplexer to the output driver. the data written into the output register pn_out by software can be used as input data to an on- chip peripheral. this enables, for example, peripheral tests via software without external circuitry. when selected as general-purpose output line, the logic state of each port pin can be changed individually by programming the pin-related bits in the output modification register pn_omr. the bits in pn_omr make it possible to set, reset, toggle, or leave the bits in the pn_out register unchanged. when selected as general-purpose output line, the actual logic level at the pin can be examined through reading pn_in and compared against the applied output level (either applied through software via the output register pn_out, or via an alternate output function of a peripheral unit). this can be used to detect some electrical failures at the pin caused through external circuitry. in addition, software-supported arbitration schemes can be implemented in this way using the open-drain configuration and an external wired-and circuitry. collisions on the external communication lines can be detected when a high level (1) is output, but a low level (0) is seen when reading the pin value via the input register pn_in. all gpio lines of the TC1798 that are used by the gpta modules (gpta0, gpta1, ltca2) have an emergency stop logic. this logic makes it possible to individually disconnect gpta outputs from the driving gpta module outputs and to put them onto a well defined logic state in an emergency case. in en emergency case, the content of the port output register pn_out is driven at the output pin instead of the gpta module output. the emergency stop register pn_emr determines whether a gpta output is enabled or disabled in an emergency case. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-5 v1.1, 2011-03 ports, v1.11 10.2 description scheme for the port io functions the following two general building block can be used to describe each gpio pin: or: ?hw_dir: the type alternate direction signal which is needed if hw_en is active: ? out -always output dirx - the pins in one port having the same dirx (x=0, 1, 2, ...), are controlled as a group by a dedicated hw_dir signal. sdir- single dir- the pin is controlled by its own, dedicated, single hw_dir signal. ? grouping indicates if the respective pin is controlled by hardware: table 10-2 port x input/output functions port pin i/o select connected signal(s) from / to module px.y input signal(s) module(s) output gpio signal module alt1 signal module alt2 signal module alt3 signal module hw_dir hw_out signal module; group en table 10-3 port x functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value px.y i gpiot px_in.py px_iocrz. pc0 0xxx b o gpio px_out.py 1x00 b 1x01 b 1x10 b 1x11 b hw_dir module; group en signal hw_dir www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-6 v1.1, 2011-03 ports, v1.11 ? enx - the pins in one port having the same enx (x=0, 1, 2, ...), are controlled as a group by a dedicated hw_en signal. ? sen - single en - the pin is controlled by its own, dedicated, single hw_en signal ? digital port slices with hw_dir defined are the ports described in figure 10-1 . note: hw_en signal has higher priority then emergency stop. emergency stop is functional when the pins are set in the gpio mode . note: hw_dir signal, output case, switches the pad to push-pull output state. hw_dir signal, input case, switches the pad to the input state with pull-up/down setting as defined by the iocr register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-7 v1.1, 2011-03 ports, v1.11 10.3 port register description the individual control and data bits of ea ch gpio port are implemented in a number of registers. the registers are used to configur e and use the port as general-purpose i/o or alternate function input/output. for some ports, not all registers are implemented. the availability of th e registers in the specific ports is described in table 10-10 on page 10-28 up to table 10-28 on page 10-87 . note: all port-registers have control bits im plemented in groups of four (a nibble), starting from the bit position 0. if a port is do not fit to multiple of four without rest, or starts with a bit number other than zero, then some control bits remain unused. these bits behave as standard read-write bits, but do not have any function. the registers of not implemented groups of bits starting on the position 0 are implemented, but do not have any function. for example, port 6 contains control registers and bitfields for the first nibble p6.0 to p6.3, although there are no such pins physically implemented. the not implemented bits appear in the boundary- scan chain, although they do not have an external connection. port register overview figure 10-2 port registers table 10-4 registers address space module base address end address note p0 f000 0c00 h f000 0cff h 16 p1 f000 0d00 h f000 0dff h 16 p2 f000 0e00 h f000 0eff h 14 p3 f000 0f00 h f000 0fff h 16 control register pn_iocr0 pn_iocr1 pn_iocr2 pn_iocr3 pn_pdr0 pn_out pn_pdr1 pn_pdisc pn_in data register mca05654_b pn_omr pn_esr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-8 v1.1, 2011-03 ports, v1.11 p4 f000 1000 h f000 10ff h 16 p5 f000 1100 h f000 11ff h 16 p6 f000 1200 h f000 12ff h 12 p7 f000 1300 h f000 13ff h 8 p8 f000 1400 h f000 14ff h 8 p9 f000 1500 h f000 15ff h 15 p10 f000 1600 h f000 16ff h 6 p11 f000 1700 h f000 17ff h 16 p12 f030 0000 h f030 00ff h 8 p13 f030 0100 h f030 01ff h 16 p14 f030 0200 h f030 02ff h 16 p15 f030 0300 h f030 03ff h 16 p16 f030 0400 h f030 04ff h 13 p17 f030 0500 h f030 05ff h 16 p18 f030 0600 h f030 06ff h 8 table 10-5 registers overview register short name register long name offset address access mode desc. see read write pn_out port n output register 0000 h u, sv u, sv page 10-2 1 pn_omr port n output modification register 0004 h u, sv u, sv page 10-2 2 ? reserved 0008 h - 000c h be be ? pn_iocr0 port n input/output control register 0 0010 h u, sv u, sv page 10-1 1 pn_iocr4 port n input/output control register 4 0014 h u, sv u, sv page 10-1 2 table 10-4 registers address space module base address end address note www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-9 v1.1, 2011-03 ports, v1.11 pn_iocr8 port n input/output control register 8 0018 h u, sv 1) u, sv 1) page 10-1 3 pn_iocr12 port n input/output control register 12 001c h u, sv 1) u, sv 1) page 10-1 4 ? reserved 0020 h be be ? pn_in port n input register 0024 h u, sv u, sv page 10-2 5 ? reserved 0028 h - 003c h be be ? pn_pdr0 port n pad driver mode 0 register 0040 h u, sv sv, e page 10-1 8 pn_pdr1 port n pad driver mode 1 register 0044 h u, sv 1) sv, e 1) page 10-1 9 ? reserved 0048 h - 004c h be be ? pn_esr port n emergency stop register 0050 h u, sv 2) sv, e 2) page 10-2 4 ? reserved 0054 h - 005c h be be ? pn_pdisc port n pin function decision control register 0060 h u, sv sv, e page 10-2 0 ? reserved 0064 h - 00fc h be be ? 1) applicable to n=0-6, 9, 11, 13-18. otherwise, this location is reserved and returns ?be? upon read and write accesses. 2) applicable to n=0-5, 8-9, 13-14. otherwise, this location is reserved and returns ?be? upon read and write accesses. table 10-5 registers overview (cont?d) register short name register long name offset address access mode desc. see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-10 v1.1, 2011-03 ports, v1.11 register access rights and reset class table 10-6 registers access rights and reset classes register short name access rights reset class read write pn_out u,sv u,sv class 3 pn_omr pn_iocr0 pn_iocr4 pn_iocr8 pn_iocr12 pn_in pn_pdisc sv,e pn_pdr0 pn_pdr1 pn_esr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-11 v1.1, 2011-03 ports, v1.11 10.3.1 port input/output control registers the port input/output control registers select the digital output and input driver functionality and characteristics of a gpio port pin. port direction (input or output), pull- up or pull-down devices for inputs, and push- pull or open-drain functionality for outputs can be selected by the corresponding bit fields pcx (x = 0-15). each 32-bit wide port input/output control register controls four gpio port lines: register pn_iocr0 controls the pn.[3:0] port lines register pn_iocr4 controls the pn.[7:4] port lines register pn_iocr8 controls the pn.[11:8] port lines register pn_iocr12 controls the pn.[15:12] port lines the diagrams below show the register layouts of the port input/output control registers with the pcx bit fields. one pcx bit field controls exactly one port line pn.x. pn_iocr0 (n=0-1) port n input/output control register 0 (f000 0c10 h + n*100 h ) reset value: 2020 2020 h pn_iocr0 (n=3-11) port n input/output control register 0 (f000 0c10 h + n*100 h ) reset value: 2020 2020 h pn_iocr0 (n=12-16) port n input/output control register 0 (f02f f410 h + n*100 h ) reset value: 2020 2020 h p18_iocr0 port 18 input/output control register 0 (10 h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc30pc20pc10pc00 rw r rw r rw r rw r field bits type description pc0, pc1, pc2, pc3 [7:4], [15:12], [23:20], [31:28] rw port control for port n pin 0 to 3 this bit field determines the port n line x functionality (x = 0-3) according to the coding table (see table 10-7 ). 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-12 v1.1, 2011-03 ports, v1.11 pn_iocr4 (n=0-11) port n input/output control register 4 (f000 0c14 h + n*100 h ) reset value: 2020 2020 h pn_iocr4 (n=12-16) port n input/output control register 4 (f02f f414 h + n*100 h ) reset value: 2020 2020 h p18_iocr4 port 18 input/output control register 4 (14 h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc70pc60pc50pc40 rw r rw r rw r rw r field bits type description pc4, pc5, pc6, pc7 [7:4], [15:12], [23:20], [31:28] rw port control for port n pin 4 to 7 this bit field determines the port n line x functionality (x = 4-7) according to the coding table (see table 10-7 ). 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-13 v1.1, 2011-03 ports, v1.11 pn_iocr8 (n=0-6) port n input/output control register 8 (f000 0c18 h + n*100 h ) reset value: 2020 2020 h p9_iocr8 port 9 input/output control register 8 (18 h ) reset value: 2020 2020 h p11_iocr8 port 11input/output control register 8 (18 h ) reset value: 2020 2020 h pn_iocr8 (n=13-15) port n input/output control register 8 (f02f f418 h + n*100 h ) reset value: 2020 2020 h p16_iocr8 port 16 input/output control register 8 (18 h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc110pc100 pc9 0 pc8 0 rw r rw r rw r rw r field bits type description pc8, pc9, pc10, pc11 [7:4], [15:12], [23:20], [31:28] rw port control for port n pin 8 to 11 this bit field determines the port n line x functionality (x = 8-11) according to the coding table (see table 10-7 ). 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-14 v1.1, 2011-03 ports, v1.11 depending on the gpio port functionality (number of gpio lines of a port), not all of the port input/output control registers are implemented. the structure with one control bit field for each port pin located in different register bytes offers the possibility to configure the port pin functionality of a single pin with byte- oriented accesses without accessing the other pcx bit fields. port control coding table 10-7 describes the coding of the pcx bit fields that determine the port line functionality. port 4 has a different pcx coding than the other ports (in input mode, no pull devices can be connected). pn_iocr12 (n=0-6) port n input/output control register 12 (f000 0c1c h + n*100 h ) reset value: 2020 2020 h p11_iocr12 port 11 input/output control register 12 (1c h ) reset value: 2020 2020 h pn_iocr12 (n=13-15) port n input/output control register 12 (f02f f41c h + n*100 h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc150pc140pc130pc120 rw r rw r rw r rw r field bits type description pc12, pc13, pc14, pc15 [7:4], [15:12], [23:20], [31:28] rw port control for port n pin 12 to 15 this bit field determines the port n line x functionality (x = 12-15) according to the coding table (see table 10-7 ). 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-15 v1.1, 2011-03 ports, v1.11 table 10-7 pcx coding pcx[3:0] i/o output characteristics selected pull-up / pull-down / selected output function 0x00 b input ? no input pull device connected 0x01 b input pull-down device connected 0x10 b input pull-up device connected 1) 1) this is the default pull-up state after reset. 0x11 b no input pull device connected 1000 b output push-pull general-purpose output 1001 b alternate output function 1 1010 b alternate output function 2 1011 b alternate output function 3 1100 b open-drain general-purpose output 1101 b alternate output function 1 1110 b alternate output function 2 1111 b alternate output function 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-16 v1.1, 2011-03 ports, v1.11 10.3.2 pad driver mode register overview the pad structure of the TC1798 gpio lines offers the possibility to select the output driver strength and the slew rate. these tw o parameters are controlled by the bit fields in the pad driver mode registers pn_pdr0/1, independently from input/output and pull- up/pull-down control functionality as programmed in the pn_iocr register. pn_pdr0 and pn_pdr1 registers are assigned to each port. the gpio pads classes are: ? class a1 pins (low speed 3.3v lvttl outputs) ? class a1+ pins (medium speed 3.3v lvttl outputs) ? class a2 pins (high speed 3.3v lvttl outputs. e.g. for serial outputs) the assignment of each port pin to one of these pad classes is shown in the port configuration figures. further details about pad driver classes that are available in the TC1798 are summarized in the ?electrical specification? chapter. depending on the assigned pad class, the 3-bit wide pad driver mode selection bit fields pdx in the pad driver mode registers pn_pdr make it possible to select the port line functionality as shown in table 10-8 . note that the pad driver mode registers are specific for each port. therefore, the pn_pdr layout is described for each port in the port- specific sections. class a1 pins make it possible to select between medium and weak output drivers. class a1+ pins make it possible to select between strong/medium/weak output drivers. class a2 pins make it possible to select between strong/medium/weak output drivers. class b pins make it possible to select between strong/medium/weak output drivers, however class b pins with a pdx configured to an other value than 000 b have the behavior of class a2 pins. in the case of strong driver type, the signal transition edge can be additionally selected as sharp/medium/soft. table 10-8 pad driver mode selection pad class pdx.2 pdx.1 pdx.0 functionality a1 x x 0 medium driver 1 weak driver a1+ 0 x 0 strong driver soft edge 0 x 1 strong driver slow edge 1 x 0 medium driver 1 x 1 weak driver www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-17 v1.1, 2011-03 ports, v1.11 note: TC1798 data sheet describes the dc characteristics of all pad classes. pad driver mode registers this is the general description of the pdr registers. each port contains its own specific pdr registers, described additionally at each port, that can contain between one and eight pdx fields for pdr0 and pdr1 registers, respectively. each field controls 1 pin. for coding of pdx, see page 10-16 . a2 / b 0 0 0 strong driver, sharp edge 0 0 1 strong driver, medium edge 0 1 0 strong driver, soft edge 0 1 1 strong driver, sharp - edge 1 0 0 medium driver 1 0 1 medium driver 1 1 0 strong driver, medium - edge 1 1 1 weak driver table 10-8 pad driver mode selection (cont?d) pad class pdx.2 pdx.1 pdx.0 functionality www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-18 v1.1, 2011-03 ports, v1.11 pn_pdr0 (n=0-1) port n pad driver mode 0 register(f000 0c40 h +n*100 h ) reset value: 0000 0000 h pn_pdr0 (n=3-5) port n pad driver mode 0 register(f000 0c40 h +n*100 h ) reset value: 0000 0000 h pn_pdr0 (n=7-9) port n pad driver mode 0 register(f000 0c40 h +n*100 h ) reset value: 0000 0000 h p11_pdr0 port 11 pad driver mode 0 register (40 h ) reset value: 0000 0000 h pn_pdr0 (n=12-16) port n pad driver mode 0 register(f02f f440 h +n*100 h ) reset value: 0000 0000 h p18_pdr0 port 18 pad driver mode 0 register (40 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0pd70pd60pd50pd4 rrwrrwrrwrrw 1514131211109876543210 0pd30pd20pd10pd0 rrwrrwrrwrrw field bits type description pd0 [2:0] rw pad driver mode for pn.0 pd1 [6:4] rw pad driver mode for pn.1 pd2 [10:8] rw pad driver mode for pn.2 pd3 [14:12] rw pad driver mode for pn.3 pd4 [18:16] rw pad driver mode for pn.4 pd5 [22:20] rw pad driver mode for pn.5 pd6 [26:24] rw pad driver mode for pn.6 pd7 [30:28] rw pad driver mode for pn.7 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-19 v1.1, 2011-03 ports, v1.11 pn_pdr1 (n=0-6) port n pad driver mode 1 register(f000 0c44 h +n*100 h ) reset value: 0000 0000 h p8_pdr1 port 8 pad driver mode 1 register (44 h ) reset value: 0000 0000 h p11_pdr1 port 11 pad driver mode 1 register (44 h ) reset value: 0000 0000 h pn_pdr1 (n=13-15) port n pad driver mode 1 register(f02f f444 h +n*100 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0pd150pd140pd130pd12 rrwrrwrrwrrw 1514131211109876543210 0pd110pd100pd90pd8 rrwrrwrrwrrw field bits type description pd8 [2:0] rw pad driver mode for pn.8 pd9 [6:4] rw pad driver mode for pn.9 pd10 [10:8] rw pad driver mode for pn.10 pd11 [14:12] rw pad driver mode for pn.11 pd12 [18:16] rw pad driver mode for pn.12 pd13 [22:20] rw pad driver mode for pn.13 pd14 [26:24] rw pad driver mode for pn.14 pd15 [30:28] rw pad driver mode for pn.15 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-20 v1.1, 2011-03 ports, v1.11 10.3.3 pin function decision control register pin function decision control register the pad structure of the TC1798 gpio lines offers the possibility to select the digital sent input or analog adc input functionalities at port 17.this feature can be controlled by individual bits in the p17_pdisc, independently from input/output and pull-up/pull- down control functionality as programmed in the pn_iocr register. p17_pdisc port 17 pin function decision control register(60 h ) reset value: ffff ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 pdis 15 pdis 14 pdis 13 pdis 12 pdis 11 pdis 10 pdis 9 pdis 8 pdis 7 pdis 6 pdis 5 pdis 4 pdis 3 pdis 2 pdis 1 pdis 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description pdisx (x = 0-15) xrw pad disable for port n pin x this bit disables the port pad. 0 b pad pn.x is enabled. 1 b pad pn.x is disabled. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-21 v1.1, 2011-03 ports, v1.11 10.3.4 port output register the port output register determines the value of a gpio pin when it is selected by pn_iocrx as output. writing a 0 to a pn_o ut.px (x = 0-15) bit position delivers a low level at the corresponding output pin. a high level is output when the corresponding bit is written with a 1. note that the bits of pn_out.px can be individually set/reset by writing appropriate values into the port out put modification register pn_omr. note: only port 0, 1, 3, 4, 5, 11, 13, 14, 15and 17 are 16-bit wide ports. the pn_out registers of the ot her ports have a reduced number of px bits (see pn_out register descriptions in the corresponding port sections). pn_out (n=0-11) port n output register (f000 0c00 h + n*100 h ) reset value: 0000 0000 h pn_out (n=12-16) port n output register (f02f f400 h + n*100 h ) reset value: 0000 0000 h p18_out port 18 output register (00 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description px (x = 0-15) xrwh port n output bit x this bit determines the level at the output pin pn.x if the output is selected as gpio output. 0 b the output level of pn.x is 0. 1 b the output level of pn.x is 1. pn.x can also be set/reset by control bits of the pn_omr register. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-22 v1.1, 2011-03 ports, v1.11 10.3.5 port output modification register the port output modification register contains control bits that make it possible to individually set, reset, or toggle the logic state of a single port line by manipulating the output register. note: register pn_omr is virtual and does not contain any flip-flop. a read action delivers the value of 0. one 8 or 16-bits write behaves as a 32-bit write padded with zeros. pn_omr (n=0-11) port n output modification register (f000 0c04 h + n*100 h ) reset value: 0000 0000 h pn_omr (n=12-16) port n output modificat ion register (f02f f404 h + n*100 h ) reset value: 0000 0000 h p18_omr port 18 output modifi cation register (04 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pr 15 pr 14 pr 13 pr 12 pr 11 pr 10 pr 9 pr 8 pr 7 pr 6 pr 5 pr 4 pr 3 pr 2 pr 1 pr 0 wwwwwwwwwwwwwwww 1514131211109876543210 ps 15 ps 14 ps 13 ps 12 ps 11 ps 10 ps 9 ps 8 ps 7 ps 6 ps 5 ps 4 ps 3 ps 2 ps 1 ps 0 wwwwwwwwwwwwwwww field bits type description psx (x = 0-15) xw port n set bit x setting this bit will set or toggle the corresponding bit in the port output register pn_out. the function of this bit is shown in table 10-9 . prx (x = 0-15) x + 16 w port n reset bit x setting this bit will reset or toggle the corresponding bit in the port output register pn_out. the function of this bit is shown in table 10-9 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-23 v1.1, 2011-03 ports, v1.11 table 10-9 function of the bits prx and psx prx psx function 0 0 bit pn_out.px is not changed. 0 1 bit pn_out.px is set. 1 0 bit pn_out.px is reset. 1 1 bit pn_out.px is toggled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-24 v1.1, 2011-03 ports, v1.11 10.3.6 emergency stop register all gpio lines which are used by the gpta modules (gpta0, gpta1, ltca2) have an emergency stop logic implemented (see figure 10-1 ). these gpta related gpio lines are: ? p0.[7:0], p1.[15:8], p2.[15:8], p3.[15:0], p4.[15:0], p5.[15:0], p8.[7:0], p9.[7:0], p13.[15:0], and p14.[15:0] each of these gpio lines has its own emergency stop enable bit enx that is located in the emergency stop register pn_esr of port n. if the emergency stop signal becomes active, one of two states can be selected: ? emergency stop function disabled (enx = 0): a gpta output line remains connected to the gpta module (alternate function). ? emergency stop function enabled (enx = 1): a gpta output line is disconnected from the gpta module (alternate function) and connected to the corresponding bit of the pn_out output register (the content of the corresponding pcx bit fields in register pn_iocr is discarded). pn_esr (n=0-5) port n emergency stop register (f000 0c50 h + n*100 h ) reset value: 0000 0000 h pn_esr (n=8-9) port n emergency stop register (f000 0c50 h + n*100 h ) reset value: 0000 0000 h pn_esr (n=13-14) port n emergency stop register (f02f f450 h + n*100 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 en 15 en 14 en 13 en 12 en 11 en 10 en 9 en 8 en 7 en 6 en 5 en 4 en 3 en 2 en 1 en 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-25 v1.1, 2011-03 ports, v1.11 note: ports 3, 4, 5, 13, and 14 are 16-bit wid e ports entirely used by the gpta modules. the pn_esr registers of the other port s have a reduced number of bits (see pn_esr register descriptions in the corresponding port sections). 10.3.7 port input register the logic level of a gpio pin can be read via the read-only port input register pn_in. reading the pn_in register allways returns the current logical value at the gpio pin independently whether the pin is selected as input or output. field bits type description enx (x = 0-15) xrw emergency stop enable for port n pin x this bit enables the emergency stop function for gpio lines used as gpta outputs. if the emergency stop condition is met and enabled, the output selection is automatically switched from alternate (gpta output) function to gpio output function. 0 b emergency stop function for pn.x is disabled. 1 b emergency stop function for pn.x is enabled. 0 [31:16] r reserved read as 0; should be written with 0. pn_in (n=0-11) port n input register (f000 0c24 h + n*100 h ) reset value: 0000 xxxx h pn_in (n=12-16) port n input register (f02f f424 h + n*100 h ) reset value: 0000 xxxx h pn_in (n=17-18) port n input register (f02f f424 h + n*100 h ) reset value: 0000 xxxx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-26 v1.1, 2011-03 ports, v1.11 note: only port 0, 1, 3, 4, 5, 11, 13, 14, 15and 17 are 16-bit wide ports. the pn_in registers of the other ports have a reduced number of px bits (see pn_in register descriptions in the corresponding port sections). field bits type description px (x = 0-15) xrh port n input bit x this bit indicates the level at the input pinpn.x. 0 b the input level of pn.x is 0. 1 b the input level of pn.x is 1. 0 [31:16] r reserved read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-27 v1.1, 2011-03 ports, v1.11 10.4 port 0 this section describes the port 0 functionality in detail. 10.4.1 port 0 configuration port 0 is a general-purpose 16-bit bi-directi onal port. it serves as gpio lines without secondary functions. table 10-10 summarizes the i/o control selection functions of each port 0 line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-28 v1.1, 2011-03 ports, v1.11 10.4.2 port 0 function table table 10-10 summarizes the i/o control selection functions of each port 0 line. table 10-10 port 0 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p0.0 i general-purpose input p0_in.p0 p0_iocr0.pc0 0xxx b hwcfg0 o general-purpose output p0_out.p0 1x00 b gpta0 output out56 1x01 b gpta1 output out56 1x10 b ltca2 output out80 1x11 b p0.1 i general-purpose input p0_in.p1 p0_iocr0.pc1 0xxx b hwcfg1 o general-purpose output p0_out.p1 1x00 b gpta0 output out57 1x01 b gpta1 output out57 1x10 b ltca2 output out81 1x11 b p0.2 i general-purpose input p0_in.p2 p0_iocr0.pc2 0xxx b hwcfg2 o general-purpose output p0_out.p2 1x00 b gpta0 output out58 1x01 b gpta1 output out58 1x10 b ltca2 output out82 1x11 b p0.3 i general-purpose input p0_in.p3 p0_iocr0.pc3 0xxx b hwcfg3 o general-purpose output p0_out.p3 1x00 b gpta0 output out59 1x01 b gpta1 output out59 1x10 b ltca2 output out83 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-29 v1.1, 2011-03 ports, v1.11 p0.4 i general-purpose input p0_in.p4 p0_iocr4.pc4 0xxx b hwcfg4 o general-purpose output p0_out.p4 1x00 b gpta0 output out60 1x01 b gpta1 output out60 1x10 b mcds event output 0 1) evto0 1x11 b p0.5 i general-purpose input p0_in.p5 p0_iocr4.pc5 0xxx b hwcfg5 o general-purpose output p0_out.p5 1x00 b gpta0 output out61 1x01 b gpta1 output out61 1x10 b mcds event output 1 1) evto1 1x11 b p0.6 i general-purpose input p0_in.p6 p0_iocr4.pc6 0xxx b hwcfg6 o general-purpose output p0_out.p6 1x00 b gpta0 output out62 1x01 b gpta1 output out62 1x10 b mcds event output 2 1) evto2 1x11 b p0.7 i general-purpose input p0_in.p7 p0_iocr4.pc7 0xxx b hwcfg7 o general-purpose output p0_out.p7 1x00 b gpta0 output out63 1x01 b gpta1 output out63 1x10 b mcds event output 3 1) evto3 1x11 b p0.8 i general-purpose input p0_in.p8 p0_iocr8.pc8 0xxx b o general-purpose output p0_out.p8 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b table 10-10 port 0 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-30 v1.1, 2011-03 ports, v1.11 p0.9 i general-purpose input p0_in.p9 p0_iocr8.pc9 0xxx b e-ray rxda0 o general-purpose output p0_out.p9 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b p0.10 i general-purpose input p0_in.p10 p0_iocr8. pc10 0xxx b o general-purpose output p0_out.p10 1x00 b e-ray txena 1x01 b reserved ? 1x10 b reserved ? 1x11 b p0.11 i general-purpose input p0_in.p11 p0_iocr8. pc11 0xxx b gpt120 t5inb gpt121 t5ina o general-purpose output p0_out.p11 1x00 b e-ray txenb 1x01 b reserved ? 1x10 b reserved ? 1x11 b p0.12 i general-purpose input p0_in.p12 p0_iocr12. pc12 0xxx b gpt120 t5euda gpt121 t5eudb o general-purpose output p0_out.p12 1x00 b e-ray txdb 1x01 b reserved ? 1x10 b reserved ? 1x11 b table 10-10 port 0 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-31 v1.1, 2011-03 ports, v1.11 p0.13 i general-purpose input p0_in.p13 p0_iocr12. pc13 0xxx b e-ray rxdb0 gpt120 t5eudb gpt121 t5euda o general-purpose output p0_out.p13 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b p0.14 i general-purpose input p0_in.p14 p0_iocr12. pc14 0xxx b gpt120 t6ina gpt121 t6inb o general-purpose output p0_out.p14 1x00 b e-ray txda 1x01 b reserved ? 1x10 b reserved ? 1x11 b p0.15 i general-purpose input p0_in.p15 p0_iocr12. pc15 0xxx b o general-purpose output p0_out.p15 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b 1) only applicable in TC1798ed table 10-10 port 0 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-32 v1.1, 2011-03 ports, v1.11 10.4.3 port 0 registers the following registers are available on port 0: 10.4.3.1 port 0 emergency stop register the basic p0_esr register functionality is described on page 10-24 . at port 0, only port lines p0.[7:0] have gpta outputs. theref ore, the p0_esr bits en[15:8] are not implemented. they are always read as 0 and should be written with 0. table 10-11 port 0 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p0_out port 0 output register 0000 h page 10-21 p0_omr port 0 output modification register 0004 h page 10-22 p0_iocr0 port 0 input/output control register 0 0010 h page 10-11 p0_iocr4 port 0 input/output control register 4 0014 h page 10-12 p0_iocr8 port 0 input/output control register 8 0018 h page 10-13 p0_iocr12 port 0 input/output control register 12 001c h page 10-14 p0_in port 0 input register 0024 h page 10-25 p0_pdr0 port 0 pad driver mode 0 register 0040 h page 10-18 p0_pdr1 port 0 pad driver mode 1 register 0044 h page 10-19 p0_esr port 0 emergency stop register 0050 h page 10-24 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-33 v1.1, 2011-03 ports, v1.11 10.5 port 1 this section describes the port 1 functionality in detail. 10.5.1 port 1 configuration port 1 is a 16-bit bi-directional general-purpose i/o port that can be alternatively used for the mli0 i/o lines or for the external trigger inputs req[3:0] of the cpu. furthermore, the system clock output sysclk is provided at port 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-34 v1.1, 2011-03 ports, v1.11 10.5.2 port 1 function table table 10-12 summarizes the i/o control selection functions of each port 1 line. table 10-12 port 1 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p1.0 i general-purpose input p1_in.p0 p1_iocr0.pc0 0xxx b scu input req0 o general-purpose output p1_out.p0 1x00 b scu output extclk1 1x01 b reserved ? 1x10 b reserved ? 1x11 b p1.1 i general-purpose input p1_in.p1 p1_iocr0.pc1 0xxx b scu input req1 ccu60 cc60ina ccu61 cc60inb o general-purpose output p1_out.p1 1x00 b ccu60 cc60 1x01 b reserved ? 1x10 b reserved ? 1x11 b p1.2 i general-purpose input p1_in.p2 p1_iocr0.pc2 0xxx b scu input req2 o general-purpose output p1_out.p2 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b p1.3 i general-purpose input p1_in.p3 p1_iocr0.pc3 0xxx b scu input req3 mli0 input tready0b o general-purpose output p1_out.p3 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-35 v1.1, 2011-03 ports, v1.11 p1.4 i general-purpose input p1_in.p4 p1_iocr4.pc4 0xxx b o general-purpose output p1_out.p4 1x00 b mli0 output tclk0 1x01 b reserved ? 1x10 b reserved ? 1x11 b p1.5 i general-purpose input p1_in.p5 p1_iocr4.pc5 0xxx b mli0 input tready0a o general-purpose output p1_out.p5 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b p1.6 i general-purpose input p1_in.p6 p1_iocr4.pc6 0xxx b o general-purpose output p1_out.p6 1x00 b mli0 output tvalid0a 1x01 b ssc1 output slso10 1x10 b ccu60 cout60 1x11 b p1.7 i general-purpose input p1_in.p7 p1_iocr4.pc7 0xxx b ccu60 cc61inb ccu61 cc61ina o general-purpose output p1_out.p7 1x00 b mli0 output tdata0 1x01 b ccu61 cc61 1x10 b gpt120 t3out 1x11 b p1.8 i general-purpose input p1_in.p8 p1_iocr8.pc8 0xxx b mli0 input rclk0a o general-purpose output p1_out.p8 1x00 b gpta0 output out64 1x01 b gpta1 output out64 1x10 b ltca2 output out88 1x11 b table 10-12 port 1 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-36 v1.1, 2011-03 ports, v1.11 p1.9 i general-purpose input p1_in.p9 p1_iocr8.pc9 0xxx b o general-purpose output p1_out.p9 1x00 b mli0 output rready0a 1x01 b ssc1 output slso11 1x10 b gpta0 output out65 1x11 b p1.10 i general-purpose input p1_in.p10 p1_iocr8.pc10 0xxx b mli0 input rvalid0a o general-purpose output p1_out.p10 1x00 b gpta0 output out66 1x01 b gpta1 output out66 1x10 b ltca2 output out90 1x11 b p1.11 i general-purpose input p1_in.p11 p1_iocr8.pc11 0xxx b mli0 input rdata0a ssc3 input slsi 3 o general-purpose output p1_out.p11 1x00 b gpta0 output out67 1x01 b gpta1 output out67 1x10 b ltca2 output out91 1x11 b p1.12 general-purpose input p1_in.p12 p1_iocr12. pc12 0xxx b o general-purpose output p1_out.p12 1x00 b system clock output extclk0 1x01 b gpta0 output out68 1x10 b gpta1 output out68 1x11 b p1.13 i general-purpose input p1_in.p13 p1_iocr12. pc13 0xxx b mli0 input rclk0b o general-purpose output p1_out.p13 1x00 b gpta0 output out69 1x01 b gpta1 output out69 1x10 b ltca2 output out93 1x11 b table 10-12 port 1 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-37 v1.1, 2011-03 ports, v1.11 10.5.3 port 1 registers the following registers are available on port 1: p1.14 i general-purpose input p1_in.p14 p1_iocr12. pc14 0xxx b mli0 input rvalid0b o general-purpose output p1_out.p14 1x00 b gpta0 output out70 1x01 b gpta1 output out70 1x10 b ltca2 output out94 1x11 b p1.15 i general-purpose input p1_in.p15 p1_iocr12. pc15 0xxx b mli0 input rdata0b o general-purpose output p1_out.p15 1x00 b gpta0 output out71 1x01 b gpta1 output out71 1x10 b ltca2 output out95 1x11 b table 10-13 port 1 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p1_out port 1 output register 0000 h page 10-21 p1_omr port 1 output modification register 0004 h page 10-22 p1_iocr0 port 1 input/output control register 0 0010 h page 10-11 p1_iocr4 port 1 input/output control register 4 0014 h page 10-12 p1_iocr8 port 1 input/output control register 8 0018 h page 10-13 p1_iocr12 port 1 input/output control register 12 001c h page 10-14 p1_in port 1 input register 0024 h page 10-25 p1_pdr0 port 1 pad driver mode 0 register 0040 h page 10-18 p1_pdr1 port 1 pad driver mode 1 register 0044 h page 10-19 p1_esr port 1 emergency stop register 0050 h page 10-24 table 10-12 port 1 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-38 v1.1, 2011-03 ports, v1.11 10.5.3.1 port 1 emergency stop register the basic p1_esr register functionality is described on page 10-24 . at port 1, only port lines p1.[15:8] have gpta outputs. therefore, the p1_esr bits en[7:0] are not implemented. they are always read as 0 and should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-39 v1.1, 2011-03 ports, v1.11 10.6 port 2 this section describes the port 2 functionality in detail. 10.6.1 port 2 configuration port 2 is a 14-bit bi-directional general-purpos e i/o port that can be used either for the ssc0/ssc1 chip select output lines or for msc0/msc1 or gpta0/gpta1/ltca2 i/o lines. 10.6.2 port 2 function table table 10-14 summarizes the i/o control selection functions of each port 2 line. table 10-14 port 2 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p2.2 i general-purpose input p2_in.p2 p2_iocr0.pc2 0xxx b o general-purpose output p2_out.p2 1x00 b ssc0 output slso02 1x01 b ssc1 output slso12 1x10 b ssc1 output slsoando12 1x11 b p2.3 i general-purpose input p2_in.p3 p2_iocr0.pc3 0xxx b o general-purpose output p2_out.p3 1x00 b ssc0 output slso03 1x01 b ssc1 output slso13 1x10 b ssc1 output slsoando13 1x11 b p2.4 i general-purpose input p2_in.p4 p2_iocr4.pc4 0xxx b o general-purpose output p2_out.p4 1x00 b ssc0 output slso04 1x01 b ssc1 output slso14 1x10 b ssc1 output slsoando14 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-40 v1.1, 2011-03 ports, v1.11 p2.5 i general-purpose input p2_in.p5 p2_iocr4.pc5 0xxx b o general-purpose output p2_out.p5 1x00 b ssc0 output slso05 1x01 b ssc1 output slso15 1x10 b ssc1 output slsoando15 1x11 b p2.6 i general-purpose input p2_in.p6 p2_iocr4.pc6 0xxx b o general-purpose output p2_out.p6 1x00 b ssc0 output slso06 1x01 b ssc1 output slso16 1x10 b ssc1 output slsoando16 1x11 b p2.7 i general-purpose input p2_in.p7 p2_iocr4.pc7 0xxx b o general-purpose output p2_out.p7 1x00 b ssc0 output slso07 1x01 b ssc1 output slso17 1x10 b ssc1 output slsoando17 1x11 b p2.8 i general-purpose input p2_in.p8 p2_iocr8.pc8 0xxx b gpta0/gpta1/ltca2 input in0 ccu62 ccpos0a ccu63 t12hrb gpt120 t3inb gpt121 t3ina o general-purpose output p2_out.p8 1x00 b gpta0 output out0 1x01 b gpta1 output out0 1x10 b ltca2 output out0 1x11 b table 10-14 port 2 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-41 v1.1, 2011-03 ports, v1.11 p2.9 i general-purpose input p2_in.p9 p2_iocr8.pc9 0xxx b gpta0/gpta1/ltca2 input in1 o general-purpose output p2_out.p9 1x00 b gpta0 output out1 1x01 b gpta1 output out1 1x10 b ltca2 output out1 1x11 b p2.10 i general-purpose input p2_in.p10 p2_iocr8. pc10 0xxx b gpta0/gpta1/ltca2 input in2 ccu60 t12hre ccu60 cc61inc ccu61 ctrapa ccu61 cc60inc ccu63 ctrapb o general-purpose output p2_out.p10 1x00 b gpta0 output out2 1x01 b gpta1 output out2 1x10 b ltca2 output out2 1x11 b p2.11 i general-purpose input p2_in.p11 p2_iocr8. pc11 0xxx b gpta0/gpta1/ltca2 input in3 o general-purpose output p2_out.p11 1x00 b gpta0 output out3 1x01 b gpta1 output out3 1x10 b ltca2 output out3 1x11 b table 10-14 port 2 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-42 v1.1, 2011-03 ports, v1.11 p2.12 i general-purpose input p2_in.p12 p2_iocr12. pc12 0xxx b gpta0/gpta1/ltca2 input in4 ccu62 t12hrb ccu63 ccpos0a gpt120 t2inb gpt121 t2ina o general-purpose output p2_out.p12 1x00 b gpta0 output out4 1x01 b gpta1 output out4 1x10 b ltca2 output out4 1x11 b p2.13 i general-purpose input p2_in.p13 p2_iocr12. pc13 0xxx b gpta0/gpta1/ltca2 input in5 o general-purpose output p2_out.p13 1x00 b gpta0 output out5 1x01 b gpta1 output out5 1x10 b ltca2 output out5 1x11 b p2.14 i general-purpose input p2_in.p14 p2_iocr12. pc14 0xxx b gpta0/gpta1/ltca2 input in6 ccu60 ccpos0a ccu61 t12hrb gpt120 t3ina gpt121 t3inb o general-purpose output p2_out.p14 1x00 b gpta0 output out6 1x01 b gpta1 output out6 1x10 b ltca2 output out6 1x11 b table 10-14 port 2 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-43 v1.1, 2011-03 ports, v1.11 p2.15 i general-purpose input p2_in.p15 p2_iocr12. pc15 0xxx b gpta0/gpta1/ltca2 input in7 o general-purpose output p2_out.p15 1x00 b gpta0 output out7 1x01 b gpta1 output out7 1x10 b ltca2 output out7 1x11 b table 10-14 port 2 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-44 v1.1, 2011-03 ports, v1.11 10.6.3 port 2 registers the following registers are available on port 2: 10.6.3.1 port 2 output register the basic p2_out register functionality is described on page 10-21 . port lines p2.[1:0] are not connected to port lines. therefore, reading the p2_out bits p[1:0] returns the value that was last written (0 after reset). these bits can be also set/reset by the corresponding p2_omr bits. 10.6.3.2 port 2 output modification register the basic p2_omr register functionality is described on page 10-22 . however, port lines p2.0 and p2.1 are not available. ther efore, the p2_omr bits ps[1:0] and pr[1:0] have no direct effect on port lines but only on register bits p2_out.p[1:0]. table 10-15 port 2 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p2_out port 2 output register 0000 h below 2) 2) these registers are listed and noted here in the port 2 section because they differ from the general port register description given in section 10.3 . p2_omr port 2 output modification register 0004 h p2_iocr0 port 2 input/output control register 0 0010 h page 10-45 2) p2_iocr4 port 2 input/output control register 4 0014 h page 10-12 p2_iocr8 port 2 input/output control register 8 0018 h page 10-13 p2_iocr12 port 2 input/output control register 12 001c h page 10-14 p2_in port 2 input register 0024 h page 10-45 2) p2_pdr0 port 2 pad driver mode 0 register 0040 h page 10-46 p2_pdr1 port 2 pad driver mode 1 register 0044 h page 10-19 p2_esr port 2 emergency stop register 0050 h page 10-46 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-45 v1.1, 2011-03 ports, v1.11 10.6.3.3 port 2 input/output control register 0 port lines p2.0 and p2.1 are not available. therefore, the pc0 and pc1 bit fields in register p2_iocr0 are not connected to any port lines. 10.6.3.4 port 2 input register the basic p2_in register functionality is described on page 10-25 . however, port lines p2.0 and p2.1 are not available. therefore, bits p0 and p1 in register p2_in are always read as 0. p2_iocr0 port 2 input/output control register 0 (10 h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc30pc20pc10pc00 rw r rw r rw r rw r field bits type description pc0, pc1 [7:4], [15:12] rw reserved read as 0010 b after reset; returns value that was written. pc2 [23:20] rw port control for port 2.2 (coding see table 10-7 on page 10-15 ) pc3 [31:28] rw port control for port 2.3 (coding see table 10-7 on page 10-15 ) 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-46 v1.1, 2011-03 ports, v1.11 10.6.3.5 port 2 pad driver mode 0 register the basic p2_pdr0 register functionality is described on page 10-18 . however, port lines p2.0 and p2.1 are not available. 10.6.3.6 port 2 emergency stop register the basic p2_esr register functionality is described on page 10-24 . at port 2, only port lines p2.[15:8] are connected to gpta i/o lines . therefore, only these port lines of port 2 p2_pdr0 port 2 pad driver mode 0 register (40 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0pd70pd60pd50pd4 rrwrrwrrwrrw 1514131211109876543210 0pd30pd20pd10pd0 rrwrrwrrwrrw field bits type description pd0 [2:0] rw reserved read as 000 b after reset; returns value that was written. pd1 [6:4] rw reserved read as 000 b after reset; returns value that was written. pd2 [10:8] rw pad driver mode for p2.2 pd3 [14:12] rw pad driver mode for p2.3 pd4 [18:16] rw pad driver mode for p2.4 pd5 [22:20] rw pad driver mode for p2.5 pd6 [26:24] rw pad driver mode for p2.6 pd7 [30:28] rw pad driver mode for p2.7 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-47 v1.1, 2011-03 ports, v1.11 can be controlled for the emergency stop function. the p2_esr bits en[7:0] are not implemented. they are always read as 0 and should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-48 v1.1, 2011-03 ports, v1.11 10.7 port 3 this section describes the port 3 functionality in detail. 10.7.1 port 3 configuration port 3 is a 16-bit bi-directional general-purpose i/o port that can be used for the gpta0/gpta1/ltca2 i/o lines. 10.7.2 port 3 function table table 10-16 summarizes the i/o control selection functions of each port 3 line. table 10-16 port 3 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p3.0 i general-purpose input p3_in.p0 p3_iocr0.pc0 0xxx b gpta0/gpta1/ltca2 input in8 ccu62 ctrapa ccu62 cc60inc ccu63 t12hre ccu63 cc61inc ccu61 ctrapb gpt120 t5ina gpt121 t5inb o general-purpose output p3_out.p0 1x00 b gpta0 output out8 1x01 b gpta1 output out8 1x10 b ltca2 output out8 1x11 b p3.1 i general-purpose input p3_in.p1 p3_iocr0.pc1 0xxx b gpta0/gpta1/ltca2 input in9 o general-purpose output p3_out.p1 1x00 b gpta0 output out9 1x01 b gpta1 output out9 1x10 b ltca2 output out9 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-49 v1.1, 2011-03 ports, v1.11 p3.2 i general-purpose input p3_in.p2 p3_iocr0.pc2 0xxx b gpta0/gpta1/ltca2 input in10 ccu63 t13hre o general-purpose output p3_out.p2 1x00 b gpta0 output out10 1x01 b gpta1 output out10 1x10 b ltca2 output out10 1x11 b p3.3 i general-purpose input p3_in.p3 p3_iocr0.pc3 0xxx b gpta0/gpta1/ltca2 input in11 o general-purpose output p3_out.p3 1x00 b gpta0 output out11 1x01 b gpta1 output out11 1x10 b ltca2 output out11 1x11 b p3.4 i general-purpose input p3_in.p4 p3_iocr4.pc4 0xxx b gpta0/gpta1/ltca2 input in12 ccu62 t12hre ccu62 cc61inc ccu63 ctrapa ccu63 cc60inc ccu60 ctrapb o general-purpose output p3_out.p4 1x00 b gpta0 output out12 1x01 b gpta1 output out12 1x10 b ltca2 output out12 1x11 b table 10-16 port 3 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-50 v1.1, 2011-03 ports, v1.11 p3.5 i general-purpose input p3_in.p5 p3_iocr4.pc5 0xxx b gpta0/gpta1/ltca2 input in13 o general-purpose output p3_out.p5 1x00 b gpta0 output out13 1x01 b gpta1 output out13 1x10 b ltca2 output out13 1x11 b p3.6 i general-purpose input p3_in.p6 p3_iocr4.pc6 0xxx b gpta0/gpta1/ltca2 input in14 ccu62 t13hre gpt120 t6eudb gpt121 t6euda o general-purpose output p3_out.p6 1x00 b gpta0 output out14 1x01 b gpta1 output out14 1x10 b ltca2 output out14 1x11 b p3.7 i general-purpose input p3_in.p7 p3_iocr4.pc7 0xxx b gpta0/gpta1/ltca2 input in15 o general-purpose output p3_out.p7 1x00 b gpta0 output out15 1x01 b gpta1 output out15 1x10 b ltca2 output out15 1x11 b table 10-16 port 3 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-51 v1.1, 2011-03 ports, v1.11 p3.8 i general-purpose input p3_in.p8 p3_iocr8.pc8 0xxx b gpta0/gpta1/ltca2 input in16 ccu61 t13hre o general-purpose output p3_out.p8 1x00 b gpta0 output out16 1x01 b gpta1 output out16 1x10 b ltca2 output out16 1x11 b p3.9 i general-purpose input p3_in.p9 p3_iocr8.pc9 0xxx b gpta0/gpta1/ltca2 input in17 o general-purpose output p3_out.p9 1x00 b gpta0 output out17 1x01 b gpta1 output out17 1x10 b ltca2 output out17 1x11 b p3.10 i general-purpose input p3_in.p10 p3_iocr8. pc10 0xxx b gpta0/gpta1/ltca2 input in18 ccu62 ccpos1a ccu63 t13hrb gpt120 t3eudb gpt121 t3euda o general-purpose output p3_out.p10 1x00 b gpta0 output out18 1x01 b gpta1 output out18 1x10 b ltca2 output out18 1x11 b table 10-16 port 3 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-52 v1.1, 2011-03 ports, v1.11 p3.11 i general-purpose input p3_in.p11 p3_iocr8. pc11 0xxx b gpta0/gpta1/ltca2 input in19 o general-purpose output p3_out.p11 1x00 b gpta0 output out19 1x01 b gpta1 output out19 1x10 b ltca2 output out19 1x11 b p3.12 i general-purpose input p3_in.p12 p3_iocr12. pc12 0xxx b gpta0/gpta1/ltca2 input in20 ccu62 ccpos2a ccu63 t12hrc ccu63 t13hrc gpt120 t4inb gpt121 t4ina o general-purpose output p3_out.p12 1x00 b gpta0 output out20 1x01 b gpta1 output out20 1x10 b ltca2 output out20 1x11 b p3.13 i general-purpose input p3_in.p13 p3_iocr12. pc13 0xxx b gpta0/gpta1/ltca2 input in21 o general-purpose output p3_out.p13 1x00 b gpta0 output out21 1x01 b gpta1 output out21 1x10 b ltca2 output out21 1x11 b table 10-16 port 3 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-53 v1.1, 2011-03 ports, v1.11 p3.14 i general-purpose input p3_in.p14 p3_iocr12. pc14 0xxx b gpta0/gpta1/ltca2 input in22 ccu60 t13hre o general-purpose output p3_out.p14 1x00 b gpta0 output out22 1x01 b gpta1 output out22 1x10 b ltca2 output out22 1x11 b p3.15 i general-purpose input p3_in.p15 p3_iocr12. pc15 0xxx b gpta0/gpta1/ltca2 input in23 o general-purpose output p3_out.p15 1x00 b gpta0 output out23 1x01 b gpta1 output out23 1x10 b ltca2 output out23 1x11 b table 10-16 port 3 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-54 v1.1, 2011-03 ports, v1.11 10.7.3 port 3 registers the following registers are available on port 3: table 10-17 port 3 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p3_out port 3 output register 0000 h page 10-21 p3_omr port 3 output modification register 0004 h page 10-22 p3_iocr0 port 3 input/output control register 0 0010 h page 10-11 p3_iocr4 port 3 input/output control register 4 0014 h page 10-12 p3_iocr8 port 3 input/output control register 8 0018 h page 10-13 p3_iocr12 port 3 input/output control register 12 001c h page 10-14 p3_in port 3 input register 0024 h page 10-25 p3_pdr0 port 3 pad driver mode 0 register 0040 h page 10-18 p3_pdr1 port 3 pad driver mode 1 register 0044 h page 10-19 p3_esr port 3 emergency stop register 0050 h page 10-24 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-55 v1.1, 2011-03 ports, v1.11 10.8 port 4 this section describes the port 4 functionality in detail. 10.8.1 port 4 configuration port 4 is a 16-bit bi-directional general-purpose i/o port that can be used for the gpta0/gpta1/ltca2 i/o lines. 10.8.2 port 4 function table table 10-18 summarizes the i/o control selection functions of each port 4 line. table 10-18 port 4 functions port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value p4.0 i general-purpose input p4_in.p0 p4_iocr0.pc0 0xxx b gpta0/gpta1/ltca2 input in24 ssc2 input a (slave mode) mrst2a o general-purpose output p4_out.p0 1x00 b gpta0 output out24 1x01 b gpta1 output out24 1x10 b ssc2 output (master mode) mrst2 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-56 v1.1, 2011-03 ports, v1.11 p4.1 i general-purpose input p4_in.p1 p4_iocr0.pc1 0xxx b gpta0/gpta1/ltca2 input in25 ssc2 input a (master mode) mtsr2a ssc guardian 2 master receive input a (master mode) mrstg2a o general-purpose output p4_out.p1 1x00 b gpta0 output out25 1x01 b gpta1 output out25 1x10 b ssc2 output (slave mode) mtsr2 1x11 b p4.2 i general-purpose input p4_in.p2 p4_iocr0.pc2 0xxx b gpta0/gpta1/ltca2 input in26 ssc2 input a sclk2a o general-purpose output p4_out.p2 1x00 b gpta0 output out26 1x01 b gpta1 output out26 1x10 b ssc2 output sclk2 1x11 b p4.3 i general-purpose input p4_in.p3 p4_iocr0.pc3 0xxx b gpta0/gpta1/ltca2 input in27 o general-purpose output p4_out.p3 1x00 b gpta0 output out27 1x01 b gpta1 output out27 1x10 b ssc2 output slso20 1x11 b table 10-18 port 4 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-57 v1.1, 2011-03 ports, v1.11 p4.4 i general-purpose input p4_in.p4 p4_iocr4.pc4 0xxx b gpta0/gpta1/ltca2 input in28 o general-purpose output p4_out.p4 1x00 b gpta0 output out28 1x01 b gpta1 output out28 1x10 b ssc2 output slso21 1x11 b p4.5 i general-purpose input p4_in.p5 p4_iocr4.pc5 0xxx b gpta0/gpta1/ltca2 input in29 o general-purpose output p4_out.p5 1x00 b gpta0 output out29 1x01 b gpta1 output out29 1x10 b ssc2 output slso22 1x11 b p4.6 i general-purpose input p4_in.p6 p4_iocr4.pc6 0xxx b gpta0/gpta1/ltca2 input in30 o general-purpose output p4_out.p6 1x00 b gpta0 output out30 1x01 b gpta1 output out30 1x10 b ssc2 output slso23 1x11 b p4.7 i general-purpose input p4_in.p7 p4_iocr4.pc7 0xxx b gpta0/gpta1/ltca2 input in31 gpt120 t6inb gpt121 t6ina o general-purpose output p4_out.p7 1x00 b gpta0 output out31 1x01 b gpta1 output out31 1x10 b ssc2 output slso24 1x11 b table 10-18 port 4 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-58 v1.1, 2011-03 ports, v1.11 p4.8 i general-purpose input p4_in.p8 p4_iocr8.pc8 0xxx b gpta0/gpta1input in32 ccu60 ccpos1a ccu61 t13hrb gpt120 t3euda gpt121 t3eudb o general-purpose output p4_out.p8 1x00 b gpta0 output out32 1x01 b gpta1 output out32 1x10 b ltca2 output out0 1x11 b p4.9 i general-purpose input p4_in.p9 p4_iocr8.pc9 0xxx b gpta0/gpta1input in33 ssc2 input slsi 2 ccu60 ccpos2a ccu61 t12hrc ccu61 t13hrc gpt120 t4ina gpt121 t4inb o general-purpose output p4_out.p9 1x00 b gpta0 output out33 1x01 b gpta1 output out33 1x10 b ltca2 output out1 1x11 b table 10-18 port 4 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-59 v1.1, 2011-03 ports, v1.11 p4.10 i general-purpose input p4_in.p10 p4_iocr8. pc10 0xxx b ccu60 t12hrb ccu61 ccpos0a gpt120 t2ina gpt121 t2inb gpta0/gpta1 input in34 o general-purpose output p4_out.p10 1x00 b gpta0 output out34 1x01 b gpta1 output out34 1x10 b ltca2 output out2 1x11 b p4.11 i general-purpose input p4_in.p11 p4_iocr8. pc11 0xxx b gpta0/gpta1 input in35 o general-purpose output p4_out.p11 1x00 b gpta0 output out35 1x01 b gpta1 output out35 1x10 b ltca2 output out3 1x11 b p4.12 i general-purpose input p4_in.p12 p4_iocr12. pc12 0xxx b gpta0/gpta1 input in36 ccu60 t13hrb ccu61 ccpos1a gpt120 t2euda gpt121 t2eudb o general-purpose output p4_out.p12 1x00 b gpta1 output out36 1x10 b gpta0 output out36 1x01 b ltca2 output out4 1x11 b table 10-18 port 4 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-60 v1.1, 2011-03 ports, v1.11 10.8.3 port 4 registers the following registers are available on port 4: p4.13 i general-purpose input p4_in.p13 p4_iocr12. pc13 0xxx b gpta0/gpta1 input in37 o general-purpose output p4_out.p13 1x00 b gpta0 output out37 1x01 b gpta1 output out37 1x10 b ltca2 output out5 1x11 b p4.14 i general-purpose input p4_in.p14 p4_iocr12. pc14 0xxx b gpta0/gpta1 input in38 ccu60 t12hrc ccu60 t13hrc ccu61 ccpos2a gpt120 t4euda gpt121 t4eudb o general-purpose output p4_out.p14 1x00 b gpta0 output out38 1x01 b gpta1 output out38 1x10 b ltca2 output out6 1x11 b p4.15 i general-purpose input p4_in.p15 p4_iocr12. pc15 0xxx b gpta0/gpta1 input in39 o general-purpose output p4_out.p15 1x00 b gpta0 output out39 1x01 b gpta1 output out39 1x10 b ltca2 output out7 1x11 b table 10-18 port 4 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-61 v1.1, 2011-03 ports, v1.11 table 10-19 port 4 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p4_out port 4 output register 0000 h page 10-21 p4_omr port 4 output modification register 0004 h page 10-22 p4_iocr0 port 4 input/output control register 0 0010 h page 10-11 p4_iocr4 port 4 input/output control register 4 0014 h page 10-12 p4_iocr8 port 4 input/output control register 8 0018 h page 10-13 p4_iocr12 port 4 input/output control register 12 001c h page 10-14 p4_in port 4 input register 0024 h page 10-25 p4_pdr0 port 4 pad driver mode 0 register 0040 h page 10-18 p4_pdr1 port 4 pad driver mode 1 register 0044 h page 10-19 p4_esr port 4 emergency stop register 0050 h page 10-24 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-62 v1.1, 2011-03 ports, v1.11 10.9 port 5 port 5 is an 16-bit gpio port. pins associated to it be used in two ways: ? as a cmos port where each pin outputs one signal, as any other port (only exception - no open drain mode available), and ? as an output lvds port where a pin pair (two pins) outputs one differential msc signal. the switching between the two modes is done via the pdr registers. the swithcing between input/ouput and pull-up/pull-down control is done via the iocr register. attention: in the lvds mode the iocr.pcx bit field of each pin of the lvds pair must be programed as output, that is 1xxx b . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-63 v1.1, 2011-03 ports, v1.11 figure 10-3 port 5 pad connections f f f f port 5_ lvds_ 4. vsd p5.10 p5.11 p5.8 p5.9 sop0 p5_pdr1.pd8(msb) p5. 8 p5. 9 f f f f p5.14 p5.15 p5.12 p5.13 sop1 fclp1 p5 .14 p5 .15 p5 .12 p5 .13 p5_pdr1.pd12(msb) p5 _iocr8 .pc10 p5 _iocr8 .pc11 2 x cmos io lvds in cmos/lvds cmos in/out and pull -up/pull -down cmos in/out and pull -up/pull -down fclp0 p5 .10 p5 .11 2 x cmos io lvds in cmos/lvds cmos in/out and pull -up/pull -down cmos in/out and pull -up/pull -down 2 x cmos io lvds in cmos/lvds cmos in/out and pull -up/pull -down cmos in/out and pull -up/pull -down 2 x cmos io lvds in cmos/lvds cmos in/out and pull -up/pull -down cmos in/out and pull -up/pull -down p5_iocr8.pc8 p5_iocr8.pc9 p5_iocr12.pc14 p5_iocr12.pc15 p5_iocr12.pc12 p5_iocr12.pc13 p5_pdr1.pd10(msb) p5_pdr1.pd14(msb) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-64 v1.1, 2011-03 ports, v1.11 10.9.1 port 5 configuration port 5 is an bi-directional general-purpose i/o port which can be used for the asc0/asc1, msc0/msc1, or mli0 interface i/o lines. 10.9.2 port 5 function table table 10-20 summarizes the i/o control selection functions of each port 5 line. table 10-20 port 5 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p5.0 i general-purpose input p5_in.p0 p5_iocr0.pc0 0xxx b asc0 input rxd0a gpt120 t6euda gpt121 t6eudb o general-purpose output p5_out.p0 1x00 b asc0 output (sync. mode) rxd0a 1x01 b gpta0 output out72 1x10 b gpta1 output out72 1x11 b p5.1 i general-purpose input p5_in.p1 p5_iocr0.pc1 0xxx b o general-purpose output p5_out.p1 1x00 b asc0 output txd0 1x01 b gpta0 output out73 1x10 b gpta1 output out73 1x11 b p5.2 i general-purpose input p5_in.p2 p5_iocr0.pc2 0xxx b asc1 input rxd1a o general-purpose output p5_out.p2 1x00 b asc1 output (sync. mode) rxd1a 1x01 b gpta0 output out74 1x10 b gpta1 output out74 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-65 v1.1, 2011-03 ports, v1.11 p5.3 i general-purpose input p5_in.p3 p5_iocr0.pc3 0xxx b o general-purpose output p5_out.p3 1x00 b asc1 output txd1 1x01 b gpta0 output out75 1x10 b gpta1 output out75 1x11 b p5.4 i general-purpose input p5_in.p4 p5_iocr4.pc4 0xxx b ccu62 t13hrb ccu63 ccpos1a gpt120 t2eudb gpt121 t2euda o general-purpose output p5_out.p4 1x00 b msc0 output en00 1x01 b mli0 output rready0b 1x10 b gpta0 output out76 1x11 b p5.5 i general-purpose input p5_in.p5 p5_iocr4.pc5 0xxx b msc0 input sdi0 ccu62 t12hrc ccu62 t13hrc ccu63 ccpos2a gpt120 t4eudb gpt121 t4euda o general-purpose output p5_out.p5 1x00 b gpta0 output out77 1x01 b gpta1 output out77 1x10 b ltca2 output out101 1x11 b table 10-20 port 5 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-66 v1.1, 2011-03 ports, v1.11 p5.6 i general-purpose input p5_in.p6 p5_iocr4.pc6 0xxx b ccu62 cc60ina ccu63 cc60inb o general-purpose output p5_out.p6 1x00 b msc1 output en10 1x01 b mli0 output tvalid0b 1x10 b ccu62 cc60 1x11 b p5.7 i general-purpose input p5_in.p7 p5_iocr4.pc7 0xxx b msc1 input sdi1 ccu62 cc61ina ccu63 cc61inb o general-purpose output p5_out.p7 1x00 b gpta0 output out79 1x01 b gpta1 output out79 1x10 b ccu62 cc61 1x11 b p5.8 i general-purpose input p5_in.p8 p5_iocr8.pc8 0xxx b ccu62 cc62ina ccu63 cc62inb o general-purpose output p5_out.p8 1x00 b msc0 output son0 1x01 b gpta0 output out80 1x10 b ccu62 cc62 1x11 b p5.9 i general-purpose input p5_in.p9 p5_iocr8.pc9 0xxx b o general-purpose output p5_out.p9 1x00 b msc0 output sop0a 1x01 b gpta0 output out81 1x10 b ccu62 cout60 1x11 b table 10-20 port 5 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-67 v1.1, 2011-03 ports, v1.11 p5.10 i general-purpose input p5_in.p10 p5_iocr8. pc10 0xxx b o general-purpose output p5_out.p10 1x00 b msc0 output fcln0 1x01 b gpta0 output out82 1x10 b ccu62 cout61 1x11 b p5.11 i general-purpose input p5_in.p11 p5_iocr8. pc11 0xxx b o general-purpose output p5_out.p11 1x00 b msc0 output fclp0a 1x01 b gpta0 output out83 1x10 b ccu62 cout62 1x11 b p5.12 i general-purpose input p5_in.p12 p5_iocr12. pc12 0xxx b o general-purpose output p5_out.p12 1x00 b msc1 output son1 1x01 b gpta0 output out84 1x10 b gpta1 output out84 1x11 b p5.13 i general-purpose input p5_in.p13 p5_iocr12. pc13 0xxx b o general-purpose output p5_out.p13 1x00 b msc1 output sop1a 1x01 b gpta0 output out85 1x10 b gpta1 output out85 1x11 b p5.14 i general-purpose input p5_in.p14 p5_iocr12. pc14 0xxx b o general-purpose output p5_out.p14 1x00 b msc1 output fcln1 1x01 b gpta0 output out86 1x10 b gpta1 output out86 1x11 b table 10-20 port 5 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-68 v1.1, 2011-03 ports, v1.11 p5.15 i general-purpose input p5_in.p15 p5_iocr12. pc15 0xxx b o general-purpose output p5_out.p15 1x00 b msc1 output fclp1a 1x01 b gpta0 output out87 1x10 b gpta1 output out87 1x11 b table 10-20 port 5 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-69 v1.1, 2011-03 ports, v1.11 10.9.3 port 5 registers the following registers are available on port 5: 10.9.3.1 port 5 output register the basic p5_out register functionality is described on page 10-21 . 10.9.3.2 port 5 output modification register the basic p5_omr register functionality is described on page 10-22 . 10.9.3.3 port 5 input register the basic p5_in register func tionality is described on page 10-25 . 10.9.3.4 port 5 emergency stop register the basic p5_esr register functionality is described on page 10-24 . at port 5, all port lines p5.[15:0] have gpta outputs and correspondent esr lines. table 10-21 port 5 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p5_out port 5 output register 0000 h below 2) 2) these registers are noted here in the port 5 sectio n because they differ from the general port register description given in section 10.3 . p5_omr port 5 output modification register 0004 h p5_iocr0 port 5 input/output control register 0 0010 h page 10-11 p5_iocr4 port 5 input/output control register 4 0014 h page 10-13 p5_iocr8 port 5 input/output control register 8 0018 h page 10-13 p5_iocr12 port 5 input/output control register 12 001c h page 10-13 p5_in port 5 input register 0024 h below 2) p5_pdr0 port 5 pad driver mode 0 register 0040 h page 10-18 p5_pdr1 port 5 pad driver mode 1 register 0044 h page 10-19 p5_esr port 5 emergency stop register 0050 h page 10-24 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-70 v1.1, 2011-03 ports, v1.11 10.10 port 6 this section describes the port 6 functionality in detail. 10.10.1 port 6 configuration port 6 is a 12-bit bi-directional general-pur pose i/o port which can be used for the ssc1, asc0/asc1, or for the multican controller i/o lines. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-71 v1.1, 2011-03 ports, v1.11 10.10.2 port 6 function table table 10-22 summarizes the i/o control selection functions of each port 6 line. table 10-22 port 6 functions port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value p6.4 i general-purpose input p6_in.p4 p6_iocr4.pc4 0xxx b ssc1 input (slave mode) mtsr1 ssc guardian 1 master receive input (master mode) mrstg1 o general-purpose output p6_out.p4 1x00 b ssc1 output (master mode) mtsr1 1x01 b reserved ? 1x10 b reserved ? 1x11 b p6.5 i general-purpose input p6_in.p5 p6_iocr4.pc5 0xxx b ssc1 input (master mode) mrst1 o general-purpose output p6_out.p5 1x00 b ssc1 output (slave mode) mrst1 1x01 b reserved ? 1x10 b reserved ? 1x11 b p6.6 i general-purpose input p6_in.p6 p6_iocr4.pc6 0xxx b ssc1 input (slave mode) sclk1 o general-purpose output p6_out.p6 1x00 b ssc1 output (master mode) sclk1 1x01 b reserved ? 1x10 b reserved ? 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-72 v1.1, 2011-03 ports, v1.11 p6.7 i general-purpose input p6_in.p7 p6_iocr4.pc7 0xxx b ssc1 input slsi1 o general-purpose output p6_out.p7 1x00 b gpt120 t6ofl 1x01 b reserved ? 1x10 b reserved ? 1x11 b p6.8 i general-purpose input p6_in.p8 p6_iocr8.pc8 0xxx b can node 0 rec. input 0 can node 3 rec. input 1 rxdcan0 asc0 input rxd0b gpt120 capinb gpt121 capina o general-purpose output p6_out.p8 1x00 b reserved ? 1x01 b asc0 output (sync. mode) rxd0b 1x10 b reserved ? 1x11 b p6.9 i general-purpose input p6_in.p9 p6_iocr8.pc9 0xxx b o general-purpose output p6_out.p9 1x00 b can node 0 output txdcan0 1x01 b asc0 output txd0 1x10 b gpt121 t6ofl 1x11 b p6.10 i general-purpose input p6_in.p10 p6_iocr8. pc10 0xxx b can node 1 rec. input 0 can node 0 rec. input 1 rxdcan1 asc1 input rxd1b o general-purpose output p6_out.p10 1x00 b reserved ? 1x01 b asc1 output (sync. mode) rxd1b 1x10 b e-ray output txena 1x11 b table 10-22 port 6 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-73 v1.1, 2011-03 ports, v1.11 p6.11 i general-purpose input p6_in.p11 p6_iocr8. pc11 0xxx b o general-purpose output p6_out.p11 1x00 b can node 1 output txdcan1 1x01 b asc1 output txd1 1x10 b e-ray output txenb 1x11 b p6.12 i general-purpose input p6_in.p12 p6_iocr12. pc12 0xxx b can node 2 rec. input 0 can node 1 rec. input 1 rxdcan2 e-ray input rxda1 o general-purpose output p6_out.p12 1x00 b reserved ? 1x01 b reserved ? 1x10 b ccu60 cout61 1x11 b p6.13 i general-purpose input p6_in.p13 p6_iocr12. pc13 0xxx b o general-purpose output p6_out.p13 1x00 b can node 2 output txdcan2 1x01 b e-ray output txda 1x10 b ccu60 cout62 1x11 b p6.14 i general-purpose input p6_in.p14 p6_iocr12. pc14 0xxx b can node 3 rec. input 0 can node 2 rec. input 1 rxdcan3 e-ray input rxdb1 o general-purpose output p6_out.p14 1x00 b reserved ? 1x01 b reserved ? 1x10 b ccu60 cout63 1x11 b table 10-22 port 6 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-74 v1.1, 2011-03 ports, v1.11 p6.15 i general-purpose input p6_in.p15 p6_iocr12. pc15 0xxx b ccu60 cc60inb ccu61 cc60ina o general-purpose output p6_out.p15 1x00 b can node 3 output txdcan3 1x01 b e-ray output txdb 1x10 b ccu61 cc60 1x11 b table 10-22 port 6 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-75 v1.1, 2011-03 ports, v1.11 10.10.3 port 6 registers the following registers are available on port 6: 10.10.3.1 port 6 output register the basic p6_out register functionality is described on page 10-21 . port lines p6.[3:0] are not connected to port lines. therefore, reading the p6_out bits p[3:0] returns the value that was last written (0 after reset). these bits can be also set/reset by the corresponding p6_omr bits. 10.10.3.2 port 6 output modification register the basic p6_omr register functionality is described on page 10-22 . port lines p6.[3:0] are not available. therefore, they are not implemented. these bits should always be written with 0. 10.10.3.3 port 6 input register the basic p6_in register functionality is described on page 10-25 . port lines p6.[3:0] are not available. therefore, the p6_in bits p[3:0] are always read as 0. table 10-23 port 6 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p6_out port 6 output register 0000 h below 2) 2) these registers are listed and noted here in the port 6 section because they differ from the general port register description given in section 10.3 . p6_omr port 6 output modification register 0004 h p6_iocr4 port 6 input/output control register 4 0014 h page 10-12 p6_iocr8 port 6 input/output control register 8 0018 h page 10-13 p6_iocr12 port 6 input/output control register 12 001c h page 10-14 p6_in port 6 input register 0024 h below 2) p6_pdr0 port 6 pad driver mode 0 register 0040 h page 10-76 p6_pdr1 port 6 pad driver mode 1 register 0044 h page 10-19 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-76 v1.1, 2011-03 ports, v1.11 10.10.3.4 port 6 pad driver mode 0 register the basic p6_pdr0 register functionality is described on page 10-18 . however, port lines p6.[3:0] are not available. p6_pdr0 port 6 pad driver mode 0 register (40 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0pd70pd60pd50pd4 rrwrrwrrwrrw 1514131211109876543210 0pd30pd20pd10pd0 rrwrrwrrwrrw field bits type description pd0 [2:0] rw reserved read as 000 b after reset; returns value that was written. pd1 [6:4] rw reserved read as 000 b after reset; returns value that was written. pd2 [10:8] rw reserved read as 000 b after reset; returns value that was written. pd3 [14:12] rw reserved read as 000 b after reset; returns value that was written. pd4 [18:16] rw pad driver mode for p6.4 pd5 [22:20] rw pad driver mode for p6.5 pd6 [26:24] rw pad driver mode for p6.6 pd7 [30:28] rw pad driver mode for p6.7 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-77 v1.1, 2011-03 ports, v1.11 10.11 port 7 this section describes the port 7 functionality in detail. 10.11.1 port 7 configuration port 7 is an 8-bit bi-directional general-purp ose i/o port that can be used for the external trigger input lines req[7:4] or for the adc0/adc1 external multiplexer control output lines. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-78 v1.1, 2011-03 ports, v1.11 10.11.2 port 7 function table table 10-24 summarizes the i/o control selection functions of each port 7 line. table 10-24 port 7 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p7.0 i general-purpose input p7_in.p0 p7_iocr0.pc0 0xxx b scu input req4 ssc3 input (slave mode) mrst3 o general-purpose output p7_out.p0 1x00 b adc2 output ad2emux2 1x01 b ssc3 output (master mode) mrst3 1x10 b reserved ? 1x11 b p7.1 i general-purpose input p7_in.p1 p7_iocr0.pc1 0xxx b scu input req5 ssc3 input (master mode) mtsr3 ssc guardian 3 master receive input b (master mode) mrstg3b o general-purpose output p7_out.p1 1x00 b adc0 output ad0emux2 1x01 b ssc3 output (slave mode) mtsr3 1x10 b reserved ? 1x11 b p7.2 i general-purpose input p7_in.p2 p7_iocr0.pc2 0xxx b ssc3 input sclk3 o general-purpose output p7_out.p2 1x00 b adc0 output ad0emux0 1x01 b ssc3 output sclk3 1x10 b reserved ? 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-79 v1.1, 2011-03 ports, v1.11 p7.3 i general-purpose input p7_in.p3 p7_iocr0.pc3 0xxx b o general-purpose output p7_out.p3 1x00 b adc0 output ad0emux1 1x01 b ssc3 output slso30 1x10 b reserved ? 1x11 b p7.4 i general-purpose input p7_in.p4 p7_iocr4.pc4 0xxx b scu input req6 o general-purpose output p7_out.p4 1x00 b adc2 output ad2emux0 1x01 b ssc3 output slso31 1x10 b reserved ? 1x11 b p7.5 i general-purpose input p7_in.p5 p7_iocr4.pc5 0xxx b scu input req7 o general-purpose output p7_out.p5 1x00 b adc2 output ad2emux1 1x01 b ssc3 output slso32 1x10 b reserved ? 1x11 b p7.6 i general-purpose input p7_in.p6 p7_iocr4.pc6 0xxx b o general-purpose output p7_out.p6 1x00 b adc1 output ad1emux0 1x01 b ssc3 output slso33 1x10 b reserved ? 1x11 b p7.7 i general-purpose input p7_in.p7 p7_iocr4.pc7 0xxx b o general-purpose output p7_out.p7 1x00 b adc1 output ad1emux1 1x01 b ssc3 output slso34 1x10 b reserved ? 1x11 b table 10-24 port 7 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-80 v1.1, 2011-03 ports, v1.11 10.11.3 port 7 registers the following registers are available on port 7: 10.11.3.1 port 7 output register the basic p7_out register functionality is described on page 10-21 . port lines p7.[15:8] are not available. therefore, the p7_out bits p[15:8] should be written with 0, and are always read as 0. 10.11.3.2 port 7 output modification register the basic p7_omr register functionality is described on page 10-22 . port lines p7.[15:8] are not available. therefore, the p7_omr bits ps[15:8] and pr[15:8] are not implemented. these bits should always be written with 0. 10.11.3.3 port 7 input register the basic p7_in register functionality is described on page 10-25 . port lines p7.[15:8] are not available. therefore, the p 7_in bits p[15:8] are always read as 0. table 10-25 port 7 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p7_out port 7 output register 0000 h below 2) 2) these registers are listed and noted here in the port 7 section because they differ from the general port register description given in section 10.3 . p7_omr port 7 output modification register 0004 h p7_iocr0 port 7 input/output control register 0 0010 h page 10-11 p7_iocr4 port 7 input/output control register 4 0014 h page 10-12 p7_in port 7 input register 0024 h below 2) p7_pdr0 port 7 pad driver mode 0 register 0040 h page 10-18 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-81 v1.1, 2011-03 ports, v1.11 10.12 port 8 this section describes the port 8 functionality in detail. 10.12.1 port 8 configuration port 8 is an 8-bit bi-directional general-purpose i/o port which can be used for the mli1 interface lines or for the gpta0/gpta1 i/o lines. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-82 v1.1, 2011-03 ports, v1.11 10.12.2 port 8 function table table 10-26 summarizes the i/o control selection functions of each port 8 line. table 10-26 port 8 functions port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value p8.0 i general-purpose input p8_in.p0 p8_iocr0.pc0 0xxx b gpta0/gpta1 input in40 sent digital input sent0 o general-purpose output p8_out.p0 1x00 b gpta0 output out40 1x01 b ccu61 cout62 1x10 b mli1 output tclk1 1x11 b p8.1 i general-purpose input p8_in.p1 p8_iocr0.pc1 0xxx b gpta0/gpta1 input in41 mli1 input tready1a sent digital input sent1 ccu60 cc61ina ccu61 cc61inb o general-purpose output p8_out.p1 1x00 b gpta0 output out41 1x01 b ccu60 cc61 1x10 b sent digital output 1) sent1 1x11 b p8.2 i general-purpose input p8_in.p2 p8_iocr0.pc2 0xxx b gpta0/gpta1 input in42 sent digital input sent2 gpt120 capina gpt121 capinb o general-purpose output p8_out.p2 1x00 b ccu61 cout63 1x01 b gpta1 output out42 1x10 b mli1 output tvalid1a 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-83 v1.1, 2011-03 ports, v1.11 p8.3 i general-purpose input p8_in.p3 p8_iocr0.pc3 0xxx b gpta0/gpta1 input in43 sent digital input sent3 ccu60 cc62ina ccu61 cc62inb o general-purpose output p8_out.p3 1x00 b gpta0 output out43 1x01 b ccu60 cc62 1x10 b mli1 output tdata1 1x11 b p8.4 i general-purpose input p8_in.p4 p8_iocr4.pc4 0xxx b gpta0/gpta1 input in44 mli1 input rclk1a sent digital input sent4 ccu60 cc62inb ccu61 cc62ina o general-purpose output p8_out.p4 1x00 b gpta0 output out44 1x01 b ccu61 cc62 1x10 b gpt121 t3out 1x11 b table 10-26 port 8 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-84 v1.1, 2011-03 ports, v1.11 p8.5 i general-purpose input p8_in.p5 p8_iocr4.pc5 0xxx b gpta0/gpta1 input in45 sent digital input sent5 ccu60 ctrapa ccu60 cc60inc ccu61 t12hre ccu61 cc61inc ccu62 ctrapb o general-purpose output p8_out.p5 1x00 b gpta0 output out45 1x01 b gpta1 output out45 1x10 b mli1 output rready1a 1x11 b p8.6 i general-purpose input p8_in.p6 p8_iocr4.pc6 0xxx b gpta0/gpta1 input in46 mli1 input rvalid1a sent digital input sent6 o general-purpose output p8_out.p6 1x00 b gpta0 output out46 1x01 b ccu61 cout60 1x10 b gpt120 t6out 1x11 b p8.7 i general-purpose input p8_in.p7 p8_iocr4.pc7 0xxx b gpta0/gpta1 input in47 mli1 input rdata1a sent digital input sent7 o general-purpose output p8_out.p7 1x00 b gpta0 output out47 1x01 b ccu61 cout61 1x10 b gpt121 t6out 1x11 b 1) the pcx should not be configured as push- pull. only open-drain mode is applicable. table 10-26 port 8 functions (cont?d) port pin i/o pin functionalit y associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-85 v1.1, 2011-03 ports, v1.11 10.12.3 port 8 register the following registers are available on port 8: 10.12.3.1 port 8 output register the basic p8_out register functionality is described on page 10-21 . port lines p8.[15:8] are not available. therefore, the p8_out bi ts p[15:8] should be written with 0 and are always read as 0. 10.12.3.2 port 8 output modification register the basic p8_omr register functionality is described on page 10-22 . port lines p8.[15:8] are not available. therefore, the p8_omr bits ps[15:8] and pr[15:8] are not implemented. these bits should always be written with 0. 10.12.3.3 port 8 input register the basic p8_in register functionality is described on page 10-25 . port lines p8.[15:8] are not available. therefore, the p 8_in bits p[15:8] are always read as 0. 10.12.3.4 port 8 emergency stop register the basic p8_esr register functionality is described on page 10-24 . at port 8, only port lines p8.[7:0] are implemented. therefore, the p8_esr bits en[15:8] are not implemented. they are always read as 0 and should be written with 0. table 10-27 port 8 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p8_out port 8 output register 0000 h below 2) 2) these registers are listed here in the port 8 secti on because they differ from the general port register description given in section 10.3 . p8_omr port 8 output modification register 0004 h p8_iocr0 port 8 input/output control register 0 0010 h page 10-11 p8_iocr4 port 8 input/output control register 4 0014 h page 10-12 p8_in port 8 input register 0024 h below 2) p8_pdr0 port 8 pad driver mode 0 register 0040 h page 10-18 p8_esr port 8 emergency stop register 0050 h below 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-86 v1.1, 2011-03 ports, v1.11 10.13 port 9 this section describes the port 9 functionality in detail. 10.13.1 port 9 configuration port 9 is a 15-bit bi-directional genera l-purpose i/o port which can be used for the msc0/msc1 interface output lines or for the gpta0/gpta1 i/o lines. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-87 v1.1, 2011-03 ports, v1.11 10.13.2 port 9 function table table 10-28 summarizes the i/o control selection functions of each port 9 line. table 10-28 port 9 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p9.0 i general-purpose input p9_in.p0 p9_iocr0.p c0 0xxx b gpta0/gpta1 input in48 o general-purpose output p9_out.p0 1x00 b ccu62 cout63 1x01 b gpta1 output out48 1x10 b msc1 output en12 1x11 b p9.1 i general-purpose input p9_in.p1 p9_iocr0.p c1 0xxx b gpta0/gpta1 input in49 ccu62 cc60inb ccu63 cc60ina o general-purpose output p9_out.p1 1x00 b ccu63 cc60 1x01 b gpta1 output out49 1x10 b msc1 output en11 1x11 b p9.2 i general-purpose input p9_in.p2 p9_iocr0.p c2 0xxx b gpta0/gpta1 input in50 ccu62 cc61inb ccu63 cc61ina o general-purpose output p9_out.p2 1x00 b ccu63 cc61 1x01 b gpta1 output out50 1x10 b msc1 output sop1b 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-88 v1.1, 2011-03 ports, v1.11 p9.3 i general-purpose input p9_in.p3 p9_iocr0.p c3 0xxx b gpta0/gpta1 input in51 ccu62 cc62inb ccu63 cc62ina o general-purpose output p9_out.p3 1x00 b ccu63 cc62 1x01 b gpta1 output out51 1x10 b msc1 output fclp1b 1x11 b p9.4 i general-purpose input p9_in.p4 p9_iocr4.p c4 0xxx b gpta0/gpta1 input in52 o general-purpose output p9_out.p4 1x00 b ccu63 cout60 1x01 b gpta1 output out52 1x10 b msc0 output en03 1x11 b p9.5 i general-purpose input p9_in.p5 p9_iocr4.p c5 0xxx b gpta0/gpta1 input in53 sent digital input sent1 o general-purpose output p9_out.p5 1x00 b ccu63 cout61 1x01 b gpta1 output out53 1x10 b msc0 output en02 1x11 b p9.6 i general-purpose input p9_in.p6 p9_iocr4.p c6 0xxx b gpta0/gpta1 input in54 sent digital input sent3 o general-purpose output p9_out.p6 1x00 b gpta0 output out54 1x01 b sent digital output 1) sent3 1x10 b msc0 output en01 1x11 b table 10-28 port 9 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-89 v1.1, 2011-03 ports, v1.11 p9.7 i general-purpose input p9_in.p7 p9_iocr4.p c7 0xxx b gpta0/gpta1 input in55 sent digital input sent4 o general-purpose output p9_out.p7 1x00 b gpta0 output out55 1x01 b sent digital output 1) sent4 1x10 b msc0 output sop0b 1x11 b p9.8 i general-purpose input p9_in.p8 p9_iocr8.p c8 0xxx b sent digital input sent6 o general-purpose output p9_out.p8 1x00 b ccu63 cout62 1x01 b sent digital output 1) sent6 1x10 b msc0 output fclp0b 1x11 b p9.9 i general-purpose input p9_in.p9 p9_iocr8.p c9 0xxx b sent digital input sent0 o general-purpose output p9_out.p9 1x00 b reserved ? 1x01 b sent digital output 1) sent0 1x10 b reserved ? 1x11 b p9.10 i general-purpose input p9_in.p10 p9_iocr8.p c10 0xxx b scu emgstop sent digital input sent7 o general-purpose output p9_out.p10 1x00 b ccu63 cout63 1x01 b sent digital output 1) sent7 1x10 b reserved ? 1x11 b table 10-28 port 9 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-90 v1.1, 2011-03 ports, v1.11 p9.11 i general-purpose input p9_in.p11 p9_iocr8.p c11 0xxx b sent digital input sent2 o general-purpose output p9_out.p11 1x00 b reserved ? 1x01 b sent digital output 1) sent2 1x10 b reserved ? 1x11 b p9.12 i general-purpose input p9_in.p12 p9_iocr12. pc12 0xxx b sent digital input sent5 o general-purpose output p9_out.p12 1x00 b reserved ? 1x01 b sent digital output 1) sent5 1x10 b reserved ? 1x11 b p9.13 i general-purpose input p9_in.p13 p9_iocr12. pc13 0xxx b ocds brkin ttcan input ectt1 o general-purpose output p9_out.p13 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ocds;sen brkout sdir table 10-28 port 9 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-91 v1.1, 2011-03 ports, v1.11 p9.14 i general-purpose input p9_in.p14 p9_iocr12. pc14 0xxx b ocds brkin ttcan input ectt2 scu input req15 o general-purpose output p9_out.p14 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ocds;sen brkout sdir 1) the pcx should not be configured as push- pull. only open-drain mode is applicable. table 10-28 port 9 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-92 v1.1, 2011-03 ports, v1.11 10.13.3 port 9 registers the following registers are available on port 9: 10.13.3.1 port 9 output register the basic p9_out register functionality is described on page 10-21 . port line p9.15 is not available. therefore, the p9_out bit 15 should be written with 0 and is always read as 0. 10.13.3.2 port 9 output modification register the basic p9_omr register functionality is described on page 10-22 . port line p9.15 is not available. therefore, the p9_omr bits ps15 and pr15 are not implemented. these bits should always be written with 0. table 10-29 port 9 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p9_out port 9 output register 0000 h below 2) 2) these registers are listed and noted here in the port 9 section because they differ from the general port register description given in section 10.3 . p9_omr port 9 output modification register 0004 h p9_iocr0 port 9 input/output control register 0 0010 h page 10-11 p9_iocr4 port 9 input/output control register 4 0014 h page 10-12 p9_iocr8 port 9 input/output control register 8 0018 h page 10-13 p9_iocr12 port 9 input/output control register 12 001c h page 10-93 2) p9_in port 9 input register 0024 h page 10-93 2) p9_pdr0 port 9 pad driver mode 0 register 0040 h page 10-18 p9_pdr1 port 9 pad driver mode 1 register 0044 h page 10-94 p9_esr port 9 emergency stop register 0050 h page 10-95 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-93 v1.1, 2011-03 ports, v1.11 10.13.3.3 port 9 input/out put control register 8 10.13.3.4 port 9 input register the basic p9_in register functionality is described on page 10-25 . port line p9.15 is not available. therefore, the p9_in bit p9.15 is always read as 0. p9_iocr12 port 9 input/output control register 12 (1c h ) reset value: 2020 2020 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pc150pc140 rrwr 1514131211109876543210 pc13 0 pc12 0 rw r rw r field bits type description pc12 [7:4] rw port control for p9.12 this bit field determines the p9.12 functionality. pc13 [15:12] rw port control for p9.13 this bit field determines the p9.13 functionality. pc14 [23:20] rw port control for p9.14 this bit field determines the p9.14 functionality. pc15 [31:28] rw reserved read as 0010 b after reset; returns value that was written. 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-94 v1.1, 2011-03 ports, v1.11 10.13.3.5 port 9 pad driver mode 1 register the basic p9_pdr1 register functionality is described on page 10-18 . however, port lines p9.15 is not available. therefore, bit fields pd7 in p9_pdr1 is always read as 0 and should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-95 v1.1, 2011-03 ports, v1.11 10.13.3.6 port 9 pad driver mode 1 register the basic p9_pdr1 register functionality is described on page 10-18 . however, port lines p9.15 is not available. 10.13.3.7 port 9 emergency stop register the basic p9_esr register functionality is described on page 10-24 . at port 9, only port lines p9.[7:0] have gpta outputs. theref ore, the p9_esr bits en[15:8] are not implemented. they are always read as 0 and should be written with 0. p9_pdr1 port 9 pad driver mode 1 register (44 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0pd150pd140pd130pd12 rrwrrwrrwrrw 1514131211109876543210 0pd110pd100pd90pd8 rrwrrwrrwrrw field bits type description pd8 [2:0] rw pad driver mode for p9.8 pd9 [6:4] rw pad driver mode for p9.9 pd10 [10:8] rw pad driver mode for p9.10 pd11 [14:12] rw pad driver mode for p9.11 pd12 [18:16] rw pad driver mode for p9.12 pd13 [22:20] rw pad driver mode for p9.13 pd14 [26:24] rw pad driver mode for p9.14 pd15 [30:28] rw reserved read as 000 b after reset; returns value that was written. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-96 v1.1, 2011-03 ports, v1.11 10.14 port 10 this section describes the port 10 functionality in detail. 10.14.1 port 10 configuration port 10 is a 6-bit port. 10.14.2 port 10 function table table 10-26 summarizes the i/o control selection functions of each line. table 10-30 port 10 functions port pin i/o pin functionality associated reg./i/o line port i/o control select. reg./bit field value p10.0 i general-purpose input p10_in.p0 p10_iocr0 .pc0 0xxx b ssc0 input, master mode mrst0 o general-purpose output p10_out.p0 1x00 b ssc0 output, slave mode mrst0 1x01 b reserved ? 1x10 b reserved ? 1x11 b p10.1 i general-purpose input p10_in.p1 p10_iocr0 .pc1 0xxx b ssc0 input, slave mode mtsr0 ssc guardian 0 master receive input (master mode) mrstg0 o general-purpose output ? 1x00 b ssc0 output, master mode mtsr0 1x01 b reserved ? 1x10 b reserved 1) ?1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-97 v1.1, 2011-03 ports, v1.11 p10.2 i general-purpose input p10_in.p2 p10_iocr0 .pc2 0xxx b ssc0 input slsi0 o general-purpose output p10_out.p2 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b p10.3 i general-purpose input p10_in.p3 p10_iocr0 .pc3 0xxx b ssc0 input sclk0 o general-purpose output p10_out.p3 1x00 b ssc0 output sclk0 1x01 b reserved ? 1x10 b reserved ? 1x11 b p10.4 i general-purpose input p10_in.p4 p10_iocr4 .pc4 0xxx b o general-purpose output p10_out.p4 1x00 b ssc0 output slso0 1x01 b reserved ? 1x10 b reserved ? 1x11 b p10.5 i general-purpose input p10_in.p5 p10_iocr4 .pc5 0xxx b o general-purpose output p10_out.p5 1x00 b ssc0 output slso1 1x01 b reserved ? 1x10 b reserved ? 1x11 b 1) the port i/o control values p10_iocrx.py that are assigned to this reserved alternate output control selection should not be used. table 10-30 port 10 functions (cont?d) port pin i/o pin functionality associated reg./i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-98 v1.1, 2011-03 ports, v1.11 10.14.3 port 10 registers the following registers are available on port 10: note: register p10_in makes it possible to read the actual logic levels of the port 10 inputs. 10.14.3.1 port 10 output register the basic p10_out register functionality is described on page 10-21 . port lines p10.[15:6] are not connected to port lines. therefore, reading the p10_out bits p[15:6] returns the value that was last written (0 after reset). these bits can be also set/reset by the corresponding p10_omr bits. 10.14.3.2 port 10 output modification register the basic p10_omr register functionality is described on page 10-22 . however, port lines p10.[15:6] are not available. theref ore, the p10_omr bits ps[15:6] and pr[15:6] have no direct effect on port lines but only on register bits p10_out.p[15:6]. table 10-31 port 10 registers register short name register long name offset address 1) 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p10_out port 10 output register 0000 h page 10-98 p10_omr port 10 output modification register 0004 h page 10-98 p10_iocr0 port 10 input/output control register 0 0010 h page 10-11 p10_iocr4 port 10 input/output control register 4 0014 h page 10-99 2) 2) this register is listed here in the port 10 section bec ause it differs from the general port register description given in section 10.3 . p10_in port 10 input register 0024 h page 10-99 2) p10_pdr0 port 10 pad driver mode 0 register 0040 h page 10-100 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-99 v1.1, 2011-03 ports, v1.11 10.14.3.3 port 10 input/output control register 4 port lines p10.[15:6] are not available. ther efore, the pc6 and pc7 bit fields in register p10_iocr4 are not connected to any port lines. 10.14.3.4 port 10 input register the basic p10_in register functionality is described on page 10-25 . port lines p10.[15:6] are not available. therefore, the p10_ in bits p[15:6] are always read as 0. p10_iocr4 port 10 input/output control register 4 (14 h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc70pc60pc50pc40 rw r rw r rw r rw r field bits type description pc4 [7:4] rw port control for port 10.4 (coding see table 10-7 on page 10-15 ) pc5 [15:12] rw port control for port 10.5 (coding see table 10-7 on page 10-15 ) pc6, pc7 [23:20], [31:28] rw reserved read as 0010 b after reset; returns value that was written. 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-100 v1.1, 2011-03 ports, v1.11 10.14.3.5 port 10 pad driver mode 0 register the basic p10_pdr0 register functionality is described on page 10-18 . however, port lines p10.[15:6] are not available. p10_pdr0 port 10 pad driver mode 0 register (40 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0pd70pd60pd50pd4 rrwrrwrrwrrw 1514131211109876543210 0pd30pd20pd10pd0 rrwrrwrrwrrw field bits type description pd0 [2:0] rw pad driver mode for p10.0 pd1 [6:4] rw pad driver mode for p10.1 pd2 [10:8] rw pad driver mode for p10.2 pd3 [14:12] rw pad driver mode for p10.3 pd4 [18:16] rw pad driver mode for p10.4 pd5 [22:20] rw pad driver mode for p10.5 pd6 [26:24] rw reserved read as 000 b after reset; returns value that was written. pd7 [30:28] rw reserved read as 000 b after reset; returns value that was written. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-101 v1.1, 2011-03 ports, v1.11 10.15 port 11 this section describes the port 11 functionality in detail. 10.15.1 port 11 configuration port 11 is a general-purpose 16-bit bi-direc tional port. it serves as gpio lines without secondary functions. table 10-10 summarizes the i/o control selection functions of each port 11 line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-102 v1.1, 2011-03 ports, v1.11 10.15.2 port 11 function table table 10-10 summarizes the i/o control selection functions of each port 11 line. table 10-32 port 11 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p11.0 i general-purpose input p11_in.p0 p11_iocr0. pc0 0xxx b o general-purpose ou tput p11_out.p0 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a0 dir p11.1 i general-purpose input p11_in.p1 p11_iocr0. pc1 0xxx b o general-purpose ou tput p11_out.p1 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a1 dir p11.2 i general-purpose input p11_in.p2 p11_iocr0. pc2 0xxx b o general-purpose ou tput p11_out.p2 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a2 dir p11.3 i general-purpose input p11_in.p3 p11_iocr0. pc3 0xxx b o general-purpose ou tput p11_out.p3 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a3 dir www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-103 v1.1, 2011-03 ports, v1.11 p11.4 i general-purpose input p11_in.p4 p11_iocr4. pc4 0xxx b o general-purpose ou tput p11_out.p4 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a4 dir p11.5 i general-purpose input p11_in.p5 p11_iocr4. pc5 0xxx b o general-purpose ou tput p11_out.p5 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a5 dir p11.6 i general-purpose input p11_in.p6 p11_iocr4. pc6 0xxx b o general-purpose ou tput p11_out.p6 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a6 dir p11.7 i general-purpose input p11_in.p7 p11_iocr4. pc7 0xxx b o general-purpose ou tput p11_out.p7 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a7 dir table 10-32 port 11 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-104 v1.1, 2011-03 ports, v1.11 p11.8 i general-purpose input p11_in.p8 p11_iocr8. pc8 0xxx b o general-purpose ou tput p11_out.p8 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a8 dir p11.9 i general-purpose input p11_in.p9 p11_iocr8. pc9 0xxx b o general-purpose ou tput p11_out.p9 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a9 dir p11.10 i general-purpose input p11_in.p10 p11_iocr8. pc10 0xxx b o general-purpose ou tput p11_out.p10 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a10 dir p11.11 i general-purpose input p11_in.p11 p11_iocr8. pc11 0xxx b o general-purpose ou tput p11_out.p11 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a11 dir table 10-32 port 11 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-105 v1.1, 2011-03 ports, v1.11 p11.12 i general-purpose input p11_in.p12 p11_iocr1 2. pc12 0xxx b o general-purpose ou tput p11_out.p12 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a12 dir p11.13 i general-purpose input p11_in.p13 p11_iocr1 2. pc13 0xxx b o general-purpose ou tput p11_out.p13 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a13 dir p11.14 i general-purpose input p11_in.p14 p11_iocr1 2. pc14 0xxx b o general-purpose ou tput p11_out.p14 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a14 dir p11.15 i general-purpose input p11_in.p15 p11_iocr1 2. pc15 0xxx b o general-purpose ou tput p11_out.p15 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a15 dir table 10-32 port 11 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-106 v1.1, 2011-03 ports, v1.11 10.15.3 port 11 registers the following registers are available on port 11: table 10-33 port 11 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p11_out port 11 output register 0000 h page 10-21 p11_omr port 11 output modification register 0004 h page 10-22 p11_iocr0 port 11 input/output control register 0 0010 h page 10-11 p11_iocr4 port 11 input/output control register 4 0014 h page 10-12 p11_iocr8 port 11 input/output control register 8 0018 h page 10-13 p11_iocr12 port 11 input/output control register 12 001c h page 10-14 p11_in port 11 input register 0024 h page 10-25 p11_pdr0 port 11 pad driver mode 0 register 0040 h page 10-18 p11_pdr1 port 11 pad driver mode 1 register 0044 h page 10-19 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-107 v1.1, 2011-03 ports, v1.11 10.16 port 12 this section describes the port 12 functionality in detail. 10.16.1 port 12 configuration port 12 is an 8-bit bi-directional general-purpose i/o port. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-108 v1.1, 2011-03 ports, v1.11 10.16.2 port 12 function table table 10-26 summarizes the i/o control selection functions of each port 12 line. table 10-34 port 12 functions port pin i/o pin functionality associated reg./i/o line port i/o control select. reg./bit field value p12.0 i general-purpose input p12_in.p0 p12_iocr 0.pc0 0xxx b o general-purpose ou tput p12_out.p0 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a16 dir p12.1 i general-purpose input p12_in.p1 p12_iocr 0.pc1 0xxx b o general-purpose ou tput p12_out.p1 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved 1) ?1x11 b hw_out ebu;en a17 dir p12.2 i general-purpose input p12_in.p2 p12_iocr 0.pc2 0xxx b o general-purpose ou tput p12_out.p2 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a18 dir p12.3 i general-purpose input p12_in.p3 p12_iocr 0.pc3 0xxx b o general-purpose ou tput p12_out.p3 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a19 dir www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-109 v1.1, 2011-03 ports, v1.11 10.16.3 port 12 registers the following registers are available on port 12: p12.4 i general-purpose input p12_in.p4 p12_iocr 4.pc4 0xxx b o general-purpose ou tput p12_out.p4 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a20 dir p12.5 i general-purpose input p12_in.p5 p12_iocr 4.pc5 0xxx b o general-purpose ou tput p12_out.p5 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a21 dir p12.6 i general-purpose input p12_in.p6 p12_iocr 4.pc6 0xxx b o general-purpose ou tput p12_out.p6 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a22 dir p12.7 i general-purpose input p12_in.p7 p12_iocr 4.pc7 0xxx b o general-purpose ou tput p12_out.p7 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en a23 dir 1) the port i/o control values p12_iocrx.py that are assi gned to this reserved alternate output control selection should not be used. table 10-34 port 12 functions (cont?d) port pin i/o pin functionality associated reg./i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-110 v1.1, 2011-03 ports, v1.11 10.16.3.1 port 12 output register the basic p12_out register functionality is described on page 10-21 . port lines p12.[15:8] are not available. therefore, the p12_out bits p[15:8] should be written with 0 and are always read as 0. 10.16.3.2 port 12 output modification register the basic p12_omr register functionality is described on page 10-22 . port lines p12.[15:8] are not available. therefore, the p12_omr bits ps[15:8] and pr[15:8] are not implemented. these bits should always be written with 0. 10.16.3.3 port 12 input register the basic p12_in register functionality is described on page 10-25 . port lines p12.[15:8] are not available. therefore, the p12_ in bits p[15:8] are always read as 0. table 10-35 port 12 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p12_out port 12 output register 0000 h below 2) 2) these registers are listed here in the port 12 sectio n because they differ from the general port register description given in section 10.3 . p12_omr port 12 output modification register 0004 h p12_iocr0 port 12 input/output control register 0 0010 h page 10-11 p12_iocr4 port 12 input/output control register 4 0014 h page 10-12 p12_in port 12 input register 0024 h below 2) p12_pdr0 port 12 pad driver mode 0 register 0040 h page 10-18 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-111 v1.1, 2011-03 ports, v1.11 10.17 port 13 this section describes the port 13 functionality in detail. 10.17.1 port 13 configuration port 13 is a general-purpose 16-bit bi-direc tional port. it serves as gpio lines without secondary functions. table 10-10 summarizes the i/o control selection functions of each port 0 line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-112 v1.1, 2011-03 ports, v1.11 10.17.2 port 13 function table table 10-10 summarizes the i/o control selection functions of each port 13 line. table 10-36 port 13 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p13.0 i general-purpose input p13_in.p0 p13_iocr0. pc0 0xxx b ebu input d0 o general-purpose output p13_out.p0 1x00 b gpta0 output out88 1x01 b gpta1 output out88 1x10 b ltca2 output out80 1x11 b hw_out ebu;en d0 dir p13.1 i general-purpose input p13_in.p1 p13_iocr0. pc1 0xxx b ebu input d1 o general-purpose output p13_out.p1 1x00 b gpta0 output out89 1x01 b gpta1 output out89 1x10 b ltca2 output out81 1x11 b hw_out ebu;en d1 dir p13.2 i general-purpose input p13_in.p2 p13_iocr0. pc2 0xxx b ebu input d2 o general-purpose output p13_out.p2 1x00 b gpta0 output out90 1x01 b gpta1 output out90 1x10 b ltca2 output out82 1x11 b hw_out ebu;en d2 dir www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-113 v1.1, 2011-03 ports, v1.11 p13.3 i general-purpose input p13_in.p3 p13_iocr0. pc3 0xxx b ebu input d3 o general-purpose output p13_out.p3 1x00 b gpta0 output out91 1x01 b gpta1 output out91 1x10 b ltca2 output out83 1x11 b hw_out ebu;en d3 dir p13.4 i general-purpose input p13_in.p4 p13_iocr4. pc4 0xxx b ebu input d4 o general-purpose output p13_out.p4 1x00 b gpta0 output out92 1x01 b gpta1 output out92 1x10 b ltca2 output out84 1x11 b hw_out ebu;en d4 dir p13.5 i general-purpose input p13_in.p5 p13_iocr4. pc5 0xxx b ebu input d5 o general-purpose output p13_out.p5 1x00 b gpta0 output out93 1x01 b gpta1 output out93 1x10 b ltca2 output out85 1x11 b hw_out ebu;en d5 dir p13.6 i general-purpose input p13_in.p6 p13_iocr4. pc6 0xxx b ebu input d6 o general-purpose output p13_out.p6 1x00 b gpta0 output out94 1x01 b gpta1 output out94 1x10 b ltca2 output out86 1x11 b hw_out ebu;en d6 dir table 10-36 port 13 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-114 v1.1, 2011-03 ports, v1.11 p13.7 i general-purpose input p13_in.p7 p13_iocr4. pc7 0xxx b ebu input d7 o general-purpose output p13_out.p7 1x00 b gpta0 output out95 1x01 b gpta1 output out95 1x10 b ltca2 output out87 1x11 b hw_out ebu;en d7 dir p13.8 i general-purpose input p13_in.p8 p13_iocr8. pc8 0xxx b ebu input d8 o general-purpose output p13_out.p8 1x00 b gpta0 output out96 1x01 b gpta1 output out96 1x10 b ltca2 output out88 1x11 b hw_out ebu;en d8 dir p13.9 i general-purpose input p13_in.p9 p13_iocr8. pc9 0xxx b ebu input d9 o general-purpose output p13_out.p9 1x00 b gpta0 output out97 1x01 b gpta1 output out97 1x10 b ltca2 output out89 1x11 b hw_out ebu;en d9 dir p13.10 i general-purpose input p13_in.p10 p13_iocr8. pc10 0xxx b ebu input d10 o general-purpose output p13_out.p10 1x00 b gpta0 output out98 1x01 b gpta1 output out98 1x10 b ltca2 output out90 1x11 b hw_out ebu;en d10 dir table 10-36 port 13 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-115 v1.1, 2011-03 ports, v1.11 p13.11 i general-purpose input p13_in.p11 p13_iocr8. pc11 0xxx b ebu input d11 o general-purpose output p13_out.p11 1x00 b gpta0 output out99 1x01 b gpta1 output out99 1x10 b ltca2 output out91 1x11 b hw_out ebu;en d11 dir p13.12 i general-purpose input p13_in.p12 p13_iocr1 2.pc12 0xxx b ebu input d12 o general-purpose output p13_out.p12 1x00 b gpta0 output out100 1x01 b gpta1 output out100 1x10 b ltca2 output out92 1x11 b hw_out ebu;en d12 dir p13.13 i general-purpose input p13_in.p13 p13_iocr1 2.pc13 0xxx b ebu input d13 o general-purpose output p13_out.p13 1x00 b gpta0 output out101 1x01 b gpta1 output out101 1x10 b ltca2 output out93 1x11 b hw_out ebu;en d13 dir p13.14 i general-purpose input p13_in.p14 p13_iocr1 2.pc14 0xxx b ebu input d14 o general-purpose output p13_out.p14 1x00 b gpta0 output out102 1x01 b gpta1 output out102 1x10 b ltca2 output out94 1x11 b hw_out ebu;en d14 dir table 10-36 port 13 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-116 v1.1, 2011-03 ports, v1.11 p13.15 i general-purpose input p13_in.p15 p13_iocr1 2.pc15 0xxx b ebu input d15 o general-purpose output p13_out.p15 1x00 b gpta0 output out103 1x01 b gpta1 output out103 1x10 b ltca2 output out95 1x11 b hw_out ebu;en d15 dir table 10-36 port 13 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-117 v1.1, 2011-03 ports, v1.11 10.17.3 port 13 registers the following registers are available on port 13: 10.17.3.1 port 13 emergency stop register the basic p13_esr register functionality is described on page 10-24 . at port 13, all port lines p13.[15:0] have gpta outputs and correspondent esr lines. table 10-37 port 13 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding the offset address to the module base address (see table 10-4 ) description see p13_out port 13 output register 0000 h page 10-21 p13_omr port 13 output modification register 0004 h page 10-22 p13_iocr0 port 13 input/output control register 0 0010 h page 10-11 p13_iocr4 port 13 input/output control register 4 0014 h page 10-12 p13_iocr8 port 13 input/output control register 8 0018 h page 10-13 p13_iocr12 port 13 input/output control register 12 001c h page 10-14 p13_in port 13 input register 0024 h page 10-25 p13_pdr0 port 13 pad driver mode 0 register 0040 h page 10-18 p13_pdr1 port 13 pad driver mode 1 register 0044 h page 10-19 p13_esr port 13 emergency stop register 0050 h page 10-24 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-118 v1.1, 2011-03 ports, v1.11 10.18 port 14 this section describes the port 14 functionality in detail. 10.18.1 port 14 configuration port 14 is a general-purpose 16-bit bi-direc tional port. it serves as gpio lines without secondary functions. table 10-10 summarizes the i/o control selection functions of each port 14 line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-119 v1.1, 2011-03 ports, v1.11 10.18.2 port 14 function table table 10-10 summarizes the i/o control selection functions of each port 14 line. table 10-38 port 14 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p14.0 i general-purpose input p14_in.p0 p14_iocr0. pc0 0xxx b ebu input d16 o general-purpose output p14_out.p0 1x00 b ccu60 cc60 1x01 b gpta1 output out96 1x10 b ltca2 output out96 1x11 b hw_out ebu;en d16 dir p14.1 i general-purpose input p14_in.p1 p14_iocr0. pc1 0xxx b ebu input d17 o general-purpose output p14_out.p1 1x00 b ccu60 cc61 1x01 b gpta1 output out97 1x10 b ltca2 output out97 1x11 b hw_out ebu;en d17 dir p14.2 i general-purpose input p14_in.p2 p14_iocr0. pc2 0xxx b ebu input d18 o general-purpose output p14_out.p2 1x00 b ccu60 cc62 1x01 b gpta1 output out98 1x10 b ltca2 output out98 1x11 b hw_out ebu;en d18 dir www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-120 v1.1, 2011-03 ports, v1.11 p14.3 i general-purpose input p14_in.p3 p14_iocr0. pc3 0xxx b ebu input d19 o general-purpose output p14_out.p3 1x00 b ccu60 cout60 1x01 b gpta1 output out99 1x10 b ltca2 output out99 1x11 b hw_out ebu;en d19 dir p14.4 i general-purpose input p14_in.p4 p14_iocr4. pc4 0xxx b ebu input d20 o general-purpose output p14_out.p4 1x00 b ccu60 cout61 1x01 b gpta1 output out100 1x10 b ltca2 output out100 1x11 b hw_out ebu;en d20 dir p14.5 i general-purpose input p14_in.p5 p14_iocr4. pc5 0xxx b ebu input d21 o general-purpose output p14_out.p5 1x00 b ccu60 cout62 1x01 b gpta1 output out101 1x10 b ltca2 output out101 1x11 b hw_out ebu;en d21 dir p14.6 i general-purpose input p14_in.p6 p14_iocr4. pc6 0xxx b ebu input d22 o general-purpose output p14_out.p6 1x00 b ccu60 cout63 1x01 b gpta1 output out102 1x10 b ltca2 output out102 1x11 b hw_out ebu;en d22 dir table 10-38 port 14 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-121 v1.1, 2011-03 ports, v1.11 p14.7 i general-purpose input p14_in.p7 p14_iocr4. pc7 0xxx b ebu input d23 o general-purpose output p14_out.p7 1x00 b ccu61 cc60 1x01 b gpta1 output out103 1x10 b ltca2 output out103 1x11 b hw_out ebu;en d23 dir p14.8 i general-purpose input p14_in.p8 p14_iocr8. pc8 0xxx b ebu input d24 o general-purpose output p14_out.p8 1x00 b ccu61 cc61 1x01 b gpt120 t3out 1x10 b ltca2 output out104 1x11 b hw_out ebu;en d24 dir p14.9 i general-purpose input p14_in.p9 p14_iocr8. pc9 0xxx b ebu input d25 o general-purpose output p14_out.p9 1x00 b ccu61 cc62 1x01 b gpt121 t3out 1x10 b ltca2 output out105 1x11 b hw_out ebu;en d25 dir p14.10 i general-purpose input p14_in.p10 p14_iocr8. pc10 0xxx b ebu input d26 o general-purpose output p14_out.p10 1x00 b ccu61 cout60 1x01 b gpt120 t6out 1x10 b ltca2 output out106 1x11 b hw_out ebu;en d26 dir table 10-38 port 14 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-122 v1.1, 2011-03 ports, v1.11 p14.11 i general-purpose input p14_in.p11 p14_iocr8. pc11 0xxx b ebu input d27 o general-purpose output p14_out.p11 1x00 b ccu61 cout61 1x01 b gpt121 t6out 1x10 b ltca2 output out107 1x11 b hw_out ebu;en d27 dir p14.12 i general-purpose input p14_in.p12 p14_iocr1 2. pc12 0xxx b ebu input d28 o general-purpose output p14_out.p12 1x00 b ccu61 cout62 1x01 b gpta1 output out108 1x10 b ltca2 output out108 1x11 b hw_out ebu;en d28 dir p14.13 i general-purpose input p14_in.p13 p14_iocr1 2. pc13 0xxx b ebu input d29 o general-purpose output p14_out.p13 1x00 b ccu61 cout63 1x01 b gpta1 output out109 1x10 b ltca2 output out109 1x11 b hw_out ebu;en d29 dir table 10-38 port 14 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-123 v1.1, 2011-03 ports, v1.11 p14.14 i general-purpose input p14_in.p14 p14_iocr1 2. pc14 0xxx b ebu input d30 gpt120 t3inc gpt121 t3ind o general-purpose output p14_out.p14 1x00 b gpta0 output out110 1x01 b gpta1 output out110 1x10 b ltca2 output out110 1x11 b hw_out ebu;en d30 dir p14.15 i general-purpose input p14_in.p15 p14_iocr1 2. pc15 0xxx b ebu input d31 gpt120 t3eudc gpt121 t3eudd o general-purpose output p14_out.p15 1x00 b gpta0 output out111 1x01 b gpta1 output out111 1x10 b ltca2 output out111 1x11 b hw_out ebu;en d31 dir table 10-38 port 14 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-124 v1.1, 2011-03 ports, v1.11 10.18.3 port 14 registers the following registers are available on port 14: 10.18.3.1 port 14 emergency stop register the basic p14_esr register functionality is described on page 10-24 . at port 14, all port lines p14.[15:0] have gpta outputs and correspondent esr lines. table 10-39 port 14 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p14_out port 14 output register 0000 h page 10-21 p14_omr port 14 output modification register 0004 h page 10-22 p14_iocr0 port 14 input/output control register 0 0010 h page 10-11 p14_iocr4 port 14 input/output control register 4 0014 h page 10-12 p14_iocr8 port 14 input/output control register 8 0018 h page 10-13 p14_iocr12 port 14 input/output control register 12 001c h page 10-14 p14_in port 14 input register 0024 h page 10-25 p14_pdr0 port 14 pad driver mode 0 register 0040 h page 10-18 p14_pdr1 port 14 pad driver mode 1 register 0044 h page 10-18 p14_esr port 14 emergency stop register 0050 h page 10-24 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-125 v1.1, 2011-03 ports, v1.11 10.19 port 15 this section describes the port 15 functionality in detail. 10.19.1 port 15 configuration port 15 is a general-purpose 16-bit bi-direc tional port. it serves as gpio lines without secondary functions. table 10-10 summarizes the i/o control selection functions of each port 15 line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-126 v1.1, 2011-03 ports, v1.11 10.19.2 port 15 function table table 10-10 summarizes the i/o control selection functions of each port 0 line. table 10-40 port 15 functions port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value p15.0 i general-purpose input p15_in.p0 p15_iocr0. pc0 0xxx b gpt120 t4inc gpt121 t4ind ccu60 ccpos2b o general-purpose output p15_out.p0 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en cs0 dir p15.1 i general-purpose input p15_in.p1 p15_iocr0. pc1 0xxx b gpt120 t4eudc gpt121 t4eudd ccu61 ccpos2b o general-purpose output p15_out.p1 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en cs1 dir p15.2 i general-purpose input p15_in.p2 p15_iocr0. pc2 0xxx b o general-purpose output p15_out.p2 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en cs2 dir www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-127 v1.1, 2011-03 ports, v1.11 p15.3 i general-purpose input p15_in.p3 p15_iocr0. pc3 0xxx b o general-purpose output p15_out.p3 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en cs3 dir p15.4 i general-purpose input p15_in.p4 p15_iocr4. pc4 0xxx b o general-purpose output p15_out.p4 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en bc0 dir p15.5 i general-purpose input p15_in.p5 p15_iocr4. pc5 0xxx b o general-purpose output p15_out.p5 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en bc1 dir p15.6 i general-purpose input p15_in.p6 p15_iocr4. pc6 0xxx b o general-purpose output p15_out.p6 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en bc2 dir table 10-40 port 15 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-128 v1.1, 2011-03 ports, v1.11 p15.7 i general-purpose input p15_in.p7 p15_iocr4. pc7 0xxx b o general-purpose output p15_out.p7 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en bc3 dir p15.8 i general-purpose input p15_in.p8 p15_iocr8. pc8 0xxx b o general-purpose output p15_out.p8 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en rd dir p15.9 i general-purpose input p15_in.p9 p15_iocr8. pc9 0xxx b o general-purpose output p15_out.p9 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en rd/wr dir p15.10 i general-purpose input p15_in.p10 p15_iocr8. pc10 0xxx b o general-purpose ou tput p15_out.p10 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en adv dir table 10-40 port 15 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-129 v1.1, 2011-03 ports, v1.11 p15.11 i general-purpose input p15_in.p11 p15_iocr8. pc11 0xxx b ebu input wait o general-purpose ou tput p15_out.p11 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b p15.12 i general-purpose input p15_in.p12 p15_iocr1 2. pc12 0xxx b o general-purpose ou tput p15_out.p12 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en mr/w dir p15.13 i general-purpose input p15_in.p13 p15_iocr1 2. pc13 0xxx b o general-purpose ou tput p15_out.p13 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en baa dir p15.14 i general-purpose input p15_in.p14 p15_iocr1 2. pc14 0xxx b ebu input bfclki o general-purpose ou tput p15_out.p14 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b table 10-40 port 15 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-130 v1.1, 2011-03 ports, v1.11 p15.15 i general-purpose input p15_in.p15 p15_iocr1 2. pc15 0xxx b o general-purpose ou tput p15_out.p15 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en bfclko dir table 10-40 port 15 functions (cont?d) port pin i/o pin functionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-131 v1.1, 2011-03 ports, v1.11 10.19.3 port 15 registers the following registers are available on port 15: table 10-41 port 15 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding the offset address to the module base address (see table 10-4 ) description see p15_out port 15 output register 0000 h page 10-21 p15_omr port 15 output modification register 0004 h page 10-22 p15_iocr0 port 15 input/output control register 0 0010 h page 10-11 p15_iocr4 port 15 input/output control register 4 0014 h page 10-12 p15_iocr8 port 15 input/output control register 8 0018 h page 10-13 p15_iocr12 port 15 input/output control register 12 001c h page 10-14 p15_in port 15 input register 0024 h page 10-25 p15_pdr0 port 15 pad driver mode 0 register 0040 h page 10-18 p15_pdr1 port 15 pad driver mode 1 register 0044 h page 10-19 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-132 v1.1, 2011-03 ports, v1.11 10.20 port 16 this section describes the port 16 functionality in detail. 10.20.1 port 16 configuration port 16 is an 13-bit bi-directional general-purpose i/o port which can be used for the ebu i/o lines. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-133 v1.1, 2011-03 ports, v1.11 10.20.2 port 16 function table table 10-26 summarizes the i/o control selection functions of each port 16 line. table 10-42 port 16 functions port pin i/o pin functionality associated reg./i/o line port i/o control select. reg./bit field value p16.0 i general-purpose input p16_in.p0 p16_iocr 0.pc0 0xxx b ebu hold o general-purpose output p16_out.p0 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b p16.1 i general-purpose input p16_in.p1 p16_iocr 0.pc1 0xxx b ebu input hlda o general-purpose output p16_out.p1 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en hlda p16.2 i general-purpose input p16_in.p2 p16_iocr 0.pc2 0xxx b o general-purpose output p16_out.p2 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en breq dir p16.3 i general-purpose input p16_in.p3 p16_iocr 0.pc3 0xxx b o general-purpose output p16_out.p3 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en cscomb dir www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-134 v1.1, 2011-03 ports, v1.11 p16.4 i general-purpose input p16_in.p4 p16_iocr 4.pc4 0xxx b o general-purpose output p16_out.p4 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en ras dir p16.5 i general-purpose input p16_in.p5 p16_iocr 4.pc5 0xxx b o general-purpose output p16_out.p5 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en c as dir p16.6 i general-purpose input p16_in.p6 p16_iocr 4.pc6 0xxx b o general-purpose output p16_out.p6 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en ddrclk dir p16.7 i general-purpose input p16_in.p7 p16_iocr 4.pc7 0xxx b o general-purpose output p16_out.p7 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en ddrclkn dir table 10-42 port 16 functions (cont?d) port pin i/o pin functionality associated reg./i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-135 v1.1, 2011-03 ports, v1.11 p16.8 i general-purpose input p16_in.p8 p16_iocr 8.pc8 0xxx b o general-purpose output p16_out.p8 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en cke dir p16.9 i general-purpose input p16_in.p9 p16_iocr 8.pc9 0xxx b ebu input dqs0 o general-purpose output p16_out.p9 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en dqs0 dir p16.10 i general-purpose input p16_in.p10 p16_iocr 8.pc10 0xxx b ebu input dqs1 o general-purpose output p16_out.p10 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en dqs1 dir p16.11 i general-purpose input p16_in.p11 p16_iocr 8.pc11 0xxx b ebu input dqs2 o general-purpose output p16_out.p11 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en dqs2 dir table 10-42 port 16 functions (cont?d) port pin i/o pin functionality associated reg./i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-136 v1.1, 2011-03 ports, v1.11 p16.12 i general-purpose input p16_in.p12 p16_iocr 12.pc12 0xxx b ebu input dqs3 o general-purpose output p16_out.p12 1x00 b reserved ? 1x01 b reserved ? 1x10 b reserved ? 1x11 b hw_out ebu;en dqs3 dir table 10-42 port 16 functions (cont?d) port pin i/o pin functionality associated reg./i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-137 v1.1, 2011-03 ports, v1.11 10.20.3 port 16 registers the following registers are available on port 16: 10.20.3.1 port 16 output register the basic p16_out register functionality is described on page 10-21 . port lines p16.[15:13] are not available. therefore, the p16_out bits p[15:13] should be written with 0 and are always read as 0. 10.20.3.2 port 16 output modification register the basic p16_omr register functionality is described on page 10-22 . port lines p16.[15:13] are not available. therefore, the p16_omr bits ps[15:13] and pr[15:13] are not implemented. these bits should always be written with 0. table 10-43 port 16 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p16_out port 16 output register 0000 h below 2) 2) these registers are listed here in the port 16 sectio n because they differ from the general port register description given in section 10.3 . p16_omr port 16 output modification register 0004 h below 2) p16_iocr0 port 16 input/output control register 0 0010 h page 10-11 p16_iocr4 port 16 input/output control register 4 0014 h page 10-13 p16_iocr8 port 16 input/output control register 8 0018 h page 10-13 p16_iocr12 port 16 input/output control register 12 001c h page 10-138 2) p16_in port 16 input register 0024 h below 2) p16_pdr0 port 16 pad driver mode 0 register 0040 h page 10-18 p16_pdr1 port 16 pad driver mode 1 register 0044 h page 10-140 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-138 v1.1, 2011-03 ports, v1.11 10.20.3.3 port 16 input/output control register 12 10.20.3.4 port 16 input register the basic p16_in register functionality is described on page 10-25 . port lines p16.[15:13] are not available. therefore, th e p16_in bits p16.[15:13] are always read as 0. p16_iocr12 port 16 input/output control register 12 (1c h ) reset value: 2020 2020 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pc150pc140 rrwr 1514131211109876543210 pc13 0 pc12 0 rw r rw r field bits type description pc12 [7:4] rw port control for p16.12 this bit field determines the p16.12 functionality. pc13 [15:12] rw reserved read as 0010 b after reset; returns value that was written. pc14 [23:20] rw reserved read as 0010 b after reset; returns value that was written. pc15 [31:28] rw reserved read as 0010 b after reset; returns value that was written. 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-139 v1.1, 2011-03 ports, v1.11 10.20.3.5 port 16 emergency stop register the p16_esr register is not implemented. nevertheless, access to its address 0xf0300450 does not generate a bus error. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-140 v1.1, 2011-03 ports, v1.11 10.20.3.6 port 16 pad driver mode 1 register the basic p16_pdr1 register functionality is described on page 10-18 . however, port lines p16[15:13] are not available. p16_pdr1 port 16 pad driver mode 1 register (44 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0pd150pd140pd130pd12 rrwrrwrrwrrw 1514131211109876543210 0pd110pd100pd90pd8 rrwrrwrrwrrw field bits type description pd8 [2:0] rw pad driver mode for p16.8 pd9 [6:4] rw pad driver mode for p16.9 pd10 [10:8] rw pad driver mode for p16.10 pd11 [14:12] rw pad driver mode for p16.11 pd12 [18:16] rw pad driver mode for p16.12 pd13 [22:20] rw reserved read as 000 b after reset; returns value that was written. pd13 [26:24] rw reserved read as 000 b after reset; returns value that was written. pd13 [30:28] rw reserved read as 000 b after reset; returns value that was written. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-141 v1.1, 2011-03 ports, v1.11 10.21 port 17 this section describes the port 17 functionality in detail. 10.21.1 port 17 configuration port 17 is a 16-bit input port. table 10-44 summarizes the input control selection functions of each port 17 line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-142 v1.1, 2011-03 ports, v1.11 10.21.2 port 17 function table table 10-44 summarizes the input control selection functions of each port 17 line. table 10-44 port 17 functions port pin i/o pin functionality associated reg./ input line port functionality control select reg./bit field value p17.0 i adc analog input an8 p17_pdisc.pdis0 1 b sent digital input sent0 0 b p17.1 i adc analog input an9 p17_pdisc.pdis1 1 b sent digital input sent1 0 b p17.2 i adc analog input an10 p17_pdisc.pdis2 1 b sent digital input sent2 0 b p17.3 i adc analog input an11 p17_pdisc.pdis3 1 b sent digital input sent3 0 b p17.4 i adc analog input an12 p17_pdisc.pdis4 1 b sent digital input sent4 0 b p17.5 i adc analog input an13 p17_pdisc.pdis5 1 b sent digital input sent5 0 b p17.6 i adc analog input an14 p17_pdisc.pdis6 1 b sent digital input sent6 0 b p17.7 i adc analog input an15 p17_pdisc.pdis7 1 b sent digital input sent7 0 b p17.8 i adc analog input an36 p17_pdisc.pdis8 1 b sent digital input sent0 0 b p17.9 i adc analog input an37 p17_pdisc.pdis9 1 b sent digital input sent1 0 b p17.10 i adc analog input an38 p17_pdisc.pdis10 1 b sent digital input sent2 0 b p17.11 i adc analog input an39 p17_pdisc.pdis11 1 b sent digital input sent3 0 b p17.12 i adc analog input an40 p17_pdisc.pdis12 1 b sent digital input sent4 0 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-143 v1.1, 2011-03 ports, v1.11 p17.13 i adc analog input an41 p17_pdisc.pdis13 1 b sent digital input sent5 0 b p17.14 i adc analog input an42 p17_pdisc.pdis14 1 b sent digital input sent6 0 b p17.15 i adc analog input an43 p17_pdisc.pdis15 1 b sent digital input sent7 0 b table 10-44 port 17 functions (cont?d) port pin i/o pin functionality associated reg./ input line port functionality control select reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-144 v1.1, 2011-03 ports, v1.11 10.21.3 port 17 registers the following registers are available on port 17: table 10-45 port 17 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding t he offset address to the module base address (see table 10-4 ) description see p17_iocr0 port 17 input/output control register 0 0010 h page 10-145 2) 2) these registers are listed here in the port 17 sectio n because they differ from the general port register description given in section 10.3 . p17_iocr4 port 17 input/output control register 4 0014 h page 10-145 2) p17_iocr8 port 17 input/output control register 8 0018 h page 10-145 2) p17_iocr12 port 17 input/output control register 12 001c h page 10-145 2) p17_in port 17 input register 0024 h page 10-25 p17_pdisc port 17 pin function decision control register 0060 h page 10-148 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-145 v1.1, 2011-03 ports, v1.11 10.21.4 port 17 input/output control registers p17_iocr0 port 17 input/output control register 0 (10 h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc30pc20pc10pc00 rw r rw r rw r rw r field bits type description pc0, pc1, pc2, pc3 [7:4], [15:12], [23:20], [31:28] rw port control for port n pin x this bit field defines the port n line x functionality according to table 10-46 . 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-146 v1.1, 2011-03 ports, v1.11 p17_iocr4 port 17 input/output control register 4 (14 h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc70pc60pc50pc40 rw r rw r rw r rw r field bits type description pc4, pc5, pc6, pc7 [7:4], [15:12], [23:20], [31:28] rw port control for port n pin x this bit field defines the port n line x functionality according to table 10-46 . 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. p17_iocr8 port 17 input/output control register 8 (18 h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc110pc100 pc9 0 pc8 0 rw r rw r rw r rw r field bits type description pc8, pc9, pc10, pc11 [7:4], [15:12], [23:20], [31:28] rw port control for port n pin x this bit field defines the port n line x functionality according to table 10-46 . 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-147 v1.1, 2011-03 ports, v1.11 p17_iocr12 port 17 input/output control register 12 (1c h ) reset value: 2020 2020 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 pc150pc140pc130pc120 rw r rw r rw r rw r field bits type description pc12, pc13, pc14, pc15 [7:4], [15:12], [23:20], [31:28] rw port control for port n pin x this bit field defines the port n line x functionality according to table 10-46 . 0 [3:0], [11:8], [19:16], [27:24] r reserved read as 0; should be written with 0. table 10-46 pcx coding for port 17 pcx[3:0] i/o output characteristics selected pull-up / pull-down / selected output function 0x00 b input ? no input pull device connected 0x01 b input pull-down device connected 0x10 b input pull-up device connected 1) 1) this is the default pull-up state after reset. 0x11 b no input pull device connected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-148 v1.1, 2011-03 ports, v1.11 10.21.5 port 17 pin function d ecision control register p17_pdisc port 17 pin function decision control register(60 h ) reset value: ffff ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 pdis 15 pdis 14 pdis 13 pdis 12 pdis 11 pdis 10 pdis 9 pdis 8 pdis 7 pdis 6 pdis 5 pdis 4 pdis 3 pdis 2 pdis 1 pdis 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description pdis0 0rw pad disable for port 17 pin 0 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 0. 1 b pad is disabled, adc analog input 8. pdis1 1rw pad disable for port 17 pin 1 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 1. 1 b pad is disabled, adc analog input 9. pdis2 2rw pad disable for port 17 pin 2 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 2. 1 b pad is disabled, adc analog input 10. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-149 v1.1, 2011-03 ports, v1.11 pdis3 3rw pad disable for port 17 pin 3 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 3. 1 b pad is disabled, adc analog input 11. pdis4 4rw pad disable for port 17 pin 4 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 4. 1 b pad is disabled, adc analog input 12. pdis5 5rw pad disable for port 17 pin 5 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 5. 1 b pad is disabled, adc analog input 13. pdis6 6rw pad disable for port 17 pin 6 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 6. 1 b pad is disabled, adc analog input 14. pdis7 7rw pad disable for port 17 pin 7 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 7. 1 b pad is disabled, adc analog input 15. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-150 v1.1, 2011-03 ports, v1.11 pdis8 8rw pad disable for port 17 pin 8 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 0. 1 b pad is disabled, adc analog input 36. pdis9 9rw pad disable for port 17 pin 9 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 1. 1 b pad is disabled, adc analog input 37. pdis10 10 rw pad disable for port 17 pin 10 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 2. 1 b pad is disabled, adc analog input 38. pdis11 11 rw pad disable for port 17 pin 11 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 3. 1 b pad is disabled, adc analog input 39. pdis12 12 rw pad disable for port 17 pin 12 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 4. 1 b pad is disabled, adc analog input 40. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-151 v1.1, 2011-03 ports, v1.11 pdis13 13 rw pad disable for port 17 pin 13 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 5. 1 b pad is disabled, adc analog input 41. pdis14 14 rw pad disable for port 17 pin 14 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 6. 1 b pad is disabled, adc analog input 42. pdis15 15 rw pad disable for port 17 pin 15 this bit disables or enables the pad. the disabled (default) state of the pad selects the adc analog input. upon enabling, the functionality switches to the sent digital input. 0 b pad is enabled, sent digital input 7. 1 b pad is disabled, adc analog input 43. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-152 v1.1, 2011-03 ports, v1.11 10.22 port 18 this section describes the port 18 functionality in detail. 10.22.1 port 18 configuration port 18 is a general-purpose 8-bit bi-directional port. table 10-47 summarizes the i/o control selection functions of each port 18 line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-153 v1.1, 2011-03 ports, v1.11 10.22.2 port 18 function table table 10-47 summarizes the i/o control selection functions of each port 18 line. table 10-47 port 18 functions port pin i/o pin func tionality associated reg./ i/o line port i/o control select. reg./bit field value p18.0 i general-purpose input p18_in.p0 p1_iocr0.pc0 0xxx b ssc2 input (slave mode) mrst2b o general-purpose output p18_out.p0 1x00 b ssc2 output (master mode) mrst2 1x01 b reserved ? 1x10 b reserved ? 1x11 b p18.1 i general-purpose input p18_in.p1 p1_iocr0.pc1 0xxx b ssc2 input (master mode) mtsr2b ssc guardian 2 master receive input b (master mode) mrstg2b o general-purpose output p18_out.p1 1x00 b ssc2 output (slave mode) mtsr2 1x01 b reserved ? 1x10 b reserved ? 1x11 b p18.2 i general-purpose input p18_in.p2 p1_iocr0.pc2 0xxx b ssc2 input sclk2b o general-purpose output p18_out.p2 1x00 b ssc2 output sclk2 1x01 b reserved ? 1x10 b reserved ? 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-154 v1.1, 2011-03 ports, v1.11 p18.3 i general-purpose input p18_in.p3 p1_iocr0.pc3 0xxx b reserved ? reserved ? o general-purpose output p18_out.p3 1x00 b ssc2 output slso20 1x01 b reserved ? 1x10 b reserved ? 1x11 b p18.4 i general-purpose input p18_in.p4 p1_iocr4.pc4 0xxx b o general-purpose output p18_out.p4 1x00 b ssc2 output slso21 1x01 b reserved ? 1x10 b reserved ? 1x11 b p18.5 i general-purpose input p18_in.p5 p1_iocr4.pc5 0xxx b reserved ? o general-purpose output p18_out.p5 1x00 b ssc2 output slso22 1x01 b reserved ? 1x10 b reserved ? 1x11 b p18.6 i general-purpose input p18_in.p6 p1_iocr4.pc6 0xxx b o general-purpose output p18_out.p6 1x00 b ssc2 output slso23 1x01 b reserved ? 1x10 b reserved ? 1x11 b p18.7 i general-purpose input p18_in.p7 p1_iocr4.pc7 0xxx b o general-purpose output p18_out.p7 1x00 b ssc2 output slso24 1x01 b reserved ? 1x10 b reserved ? 1x11 b table 10-47 port 18 functions (cont?d) port pin i/o pin func tionality associated reg./ i/o line port i/o control select. reg./bit field value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-155 v1.1, 2011-03 ports, v1.11 10.22.3 port 18 registers the following registers are available on port 18 : 10.22.3.1 port 18 output register the basic p18_out register functionality is described on page 10-21 . port lines p18.[15:8] are not available. therefore, the p18_out bits p[15:8] should be written with 0 and are always read as 0. 10.22.3.2 port 18 output modification register the basic p18_omr register functionality is described on page 10-22 . port lines p18.[15:8] are not available. therefore, the p18_omr bits ps[15:8] and pr[15:8] are not implemented. these bits should always be written with 0. 10.22.3.3 port 18 input register the basic p18_in register functionality is described on page 10-25 . port lines p18.[15:8] are not available. therefore, the p18_in bits p18.[15:8] are always read as 0. 10.22.3.4 port 18 emergency stop register the p18_esr register is not implemented. nevertheless, access to its address 0xf0300650 does not generate a bus error. table 10-48 port 18 registers register short name register long name offset 1) address 1) the absolute addresses are calculated by adding the offset address to the module base address (see table 10-4 ) description see p18_out port 0 output register 0000 h page 10-155 2) 2) these registers are listed here in the port 18 sect ion because they differ from the general port register description given in section 10.3 . p18_omr port 0 output modification register 0004 h page 10-155 2) p18_iocr0 port 0 input/output control register 0 0010 h page 10-11 p18_iocr4 port 0 input/output control register 4 0014 h page 10-12 p18_in port 0 input register 0024 h page 10-155 2) p18_pdr0 port 0 pad driver mode 0 register 0040 h page 10-18 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose i/o ports and peripheral i/o lines (ports) users manual 10-156 v1.1, 2011-03 ports, v1.11 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-1 v1.1, 2011-03 pcp, v2.08 11 peripheral control processor (pcp) this chapter describes the peripheral control processor (pcp), its architecture, programming model, registers, and instructions. the TC1798?s pcp is an enhanced version of the tc1767?s and tc1797?s pcp peripheral control processor, which is an enhanced version of the tc1766?s and tc1796?s pcp, which is, in turn, an enhanced version of tc1775?s pcp. section 11.2 of this chapter describes the TC1798?s pcp in general. TC1798 implementation-specific details are described in section 11.22 . 11.1 pcp feature/enhancement history list the following table lists all pcp enhancements sequentially, for all versions of the pcp. the table will therefore list enhancements that may not apply to the pcp version included in TC1798. table 11-1 pcp feature/en hancement history list version enhancement tc1775 first released version of pcp tc1766, tc1796 ? optimised context switching ? support for nested interrupts ? enhanced instruction set ? enhanced instruction execution speed ? enhanced interrupt queueing tc1767, tc1797 ? enhanced pcp core to support higher clock frequencies ? multiple clock ratios pcp:fpi 1:1 and 2:1 ? adaption of pcp trace interface to pal-mcds ? implementation of parity tc1387, tc1784, TC1798, tc172x only enhancements in this row and above are included in TC1798 ? support for high integrity operation (see chapter 11.2.1 ). ? programmable endinit write protection for all registers. ? programmable write protection for cmem. ? programmable write protection for pram. ? programmable limit of fpi addresses than can be written by the pcp. ? implementation of ecc (replacing parity) ? various errata fixes. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-2 v1.1, 2011-03 pcp, v2.08 11.1.1 switchable core clock ratio for shorter interrupt latency, shorter uninterruptible task time and increased computing power the pcp is improved to allow operation with a core clock that is faster than the fpi clock (of the fpi bus to which the pcp is connected). the available clocking ratios (f fpi /f pcp ) are 1:1 and 1:2. the clock is controlled and generated in the scu. the pcp has separate clock inputs for the core and for the fpi-bus related circuits. 11.2 peripheral control processor overview the pcp in the TC1798 performs tasks th at would normally be performed by the combination of a dma controller and its supporting cpu interrupt service routines in a traditional computer system. it could easily be considered as the host processor?s first line of defence as an interrupt-handling engine. the pcp can unload the cpu from having to service time-critical interrupts. this provides many benefits, including: ? avoiding large interrupt-driven task context-switching latencies in the host processor ? reducing the cost of interrupts in terms of processor register and memory overhead ? improving the responsiveness of interrupt service routines to data-capture and data- transfer operations ? easing the implementation of multitasking operating systems. the pcp has an architecture that efficiently supports dma-type transactions to and from arbitrary devices and memory addresses within the TC1798 and also has reasonable stand-alone computational capabilities. 11.2.1 high integrity operation the pcp can be used in high integrity systems to perform various system critical tasks. it follows that, when using the pcp for this function, a fundamental requirement is that the operation of the software running on the pcp must be robust against interference by an external agent (e.g. tricore). otherw ise a system failure outside pcp could impact the operation of the pcp which might, in turn, caus e the system critical task (running on the pcp) to fail. this concept of immunity is further extend ed such the pcp can be configured to operate with a number of ?protected? channel prog rams. these channels are protected not only against failure of external agents but also against software failures in other ?unprotected? channel programs running on the pcp itself. for high integrity systems it is also necessary to prevent the pcp from generating unwanted fpi writes to critical locations in the event of a pcp software malfunction. for this reason a programmable memory protec tion feature is provided to control (in hardware) the address range that can be written to by the pcp. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-3 v1.1, 2011-03 pcp, v2.08 11.3 pcp architecture the pcp is made up of several modular blocks as follows. please refer to figure 11-1 . ? pcp processor core ? code memory (cmem) ? parameter memory (pram) ? pcp interrupt control unit (picu) ? pcp service request nodes (psrn) ? system bus interface to the flexible peripheral interface (fpi bus) figure 11-1 pcp block diagram mcb06135 pcp processor core pcp service req. nodes psrns pcp interrup t control unit picu parameter memory pram code memory cmem fpi-interface pcp interrupt arbitration bus cpu interrupt arbitration bus fpi bus www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-4 v1.1, 2011-03 pcp, v2.08 11.3.1 pcp processor the pcp processor is the main engine of the pcp. it contains an instruction pipeline, a set of gprs, an arithmetic/logic unit (alu), as well as control and status registers and logic. its instruction set is optimized es pecially for the tasks it has to perform. table 11-2 provides an overview of the pcp instruction set. the pcp processor core receives service r equests from peripherals or other modules in the system via its pcp inte rrupt control unit (picu) and executes a channel program (see page 11-8 ) selected via the priority number of each service request. it first restores the channel program?s context from the pram and then starts to execute the channel program?s instructions stored in the code memory (cmem). upon an exit condition, it terminates the channel program and saves its context into pram. it is then ready to receive the next service request. the pcp processor core is capable of suspending execution of a channel program on receipt of a service request with a higher priority than the channel currently being executed. the core will automatically re sume processing of the original channel program once the higher-priority request (or requests) has been processed. a channel that has been suspended in this way is termed as ?suspended channel?. the pcp is fully interrupt-driven, meaning it is only activated through service requests; there is no main program running in the background as with a conventional processor. table 11-2 pcp instruction set overview instruction group description dma primitives efficient dma channel implementation load/store transfer data between pram or fpi memory and the gprs, as well as move or exchange values between registers arithmetic add, subtract, compare and complement divide/multiply divide and multiply logical and, or, exclusive or, negate shift shift right or left, rotate right or left, prioritize bit manipulation set, clear, insert, and test bits flow control jump conditionally, jump long, exit miscellaneous no operation, debug www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-5 v1.1, 2011-03 pcp, v2.08 11.3.2 pcp code memory the code memory (cmem) of the pcp holds the channel programs, consisting of pcp instructions. all instructions of the pcp are 16 bits long; thus, the pcp accesses its cmem in 16-bit (half-word) quantities. with the 16-bit program counter (pc) of the pcp, a maximum of 64 k instructions can be addresse d. this results in a maximum size of the pcp code memory of 128 kbytes. the actual type (flash, rom, sram, etc.) and size of the code memory is im plementation-specific; see page 11-157 for the implemented type and size of the code memory in the TC1798. the pcp cmem is viewed from the fpi bus as a 32-bit wide memory, that must be accessed with 32-bit (word) accesses, and is addressed with byte addresses. thus, care has to be taken when calculating pcp instruction fpi addresses. see page 11-57 for details. note: the pcp has a ?harvard? architecture and therefore cannot directly access the cmem other than reading instructions fr om it. it is recommended that the pcp should not access cmem via the fpi bus. 11.3.2.1 cmem protection to allow the pcp to handle system critical tasks it is nece ssary to ensure that the pcp can operate properly rega rdless of a failure in another part of the system or the pcp itself. this means that it is necessary to protect the content of the cmem from such failures. cmem content can only be modified via the fpi. protection of cmem therefore consists of prevention of unwanted fpi writes to cmem. the normal model of pcp operation is that the program code (i.e. cmem) is loaded at system initialization and remains unchanged for the duration of op eration of the system. thus a simple locking scheme is provided to prevent any write to cmem once the content has been loaded during initialization. when cmem has been loaded (at system initialization) the memory can be locked such that all incoming fpi write accesses are issued with an error response and the cmem content will remain unmodified. regardless of protection the entire cmem remains readable via fpi. this function is controlled by the pcp_cprot register (see page 11-86 ). 11.3.3 pcp parameter ram the pcp parameter ram (pram) is the local holding place for each channel program?s context, and for general data storage. it is also an area that the pcp and the host processor or other fpi bus masters c an use to communicate and share data. while a portion of the pram is always implicitly used for the context save areas (csas) of the channel programs (see chapter 11.4.2.2 ), the remaining area can be used for channel-specific or general data storage. a pr ogrammable 8-bit data pointer (dptr), www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-6 v1.1, 2011-03 pcp, v2.08 concatenated with a 6-bit offset, is provided for arbitrary access to the pram. the effective address is a 14-bit word address, allowing a pram size of up to 64 kbytes. the actual type (sram, dram, etc.) and size of the parameter ram is implementation- specific; see page 11-157 for the implemented size of the pram in this derivative. both the pcp and fpi bus masters address the pram as 32-bit words. there is no concept of half-word or byte accesses to pram. fpi bus masters must, however, use byte addresses in order to access the pram. as for the cmem, care has to be taken when calculating pram fpi addresses. see page 11-57 for details. 11.3.3.1 pram protection to allow the pcp to handle system critical tasks it is nece ssary to ensure that the pcp can operate properly rega rdless of a failure in another part of the system or the pcp itself. this means that it is necessary to protect all or part of the content of the pram from such failures. all or part of pram can be protected from fpi writes using the pcp_pprot register (see page 11-87 ). this register also allows a region of pram to be selected which can only be used by protected pcp channel programs. 11.3.4 fpi bus interface the pcp can access all peripheral units on the fpi bus and other resources through the fpi bus interface. the pcp can become an fp i bus slave, so that other fpi bus master may access cmem and pram and the control and status registers in the pcp. the cmem and pram blocks are visible to fpi bus masters as a block of memory on the fpi bus. if an fpi bus master accesse s cmem or pram memory concurrently with the pcp, the external fpi bus master is given precedence over the pcp to avoid deadlocks. the pcp access is stalled for se veral cycles until the fpi bus master has completed its access. if an fp i bus master performs an atomic read-modify-write access to a pcp memory block, any concurrent pcp access to that block is stalled for the duration of the atomic operation. 11.3.5 pcp interrupt control unit and service request nodes the pcp is activated in response to an interrupt request programmed for pcp service in one of the service reques t nodes (srns) of the system (nodes associated with a peripheral, the cpu, external interrupts, etc.). the pcp interrupt control unit (picu) determines the request with the currently hi ghest priority and routes the request together with its priority number to the pcp processor core. it also acknowledges the requesting source when the pcp starts the service of this interrupt. the pcp itself can generate service requests to either the cpu or itself through a number of pcp service request nodes (psrns ). the psrns are also used to store all information required by the pcp processor core to allow the later restart of a channel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-7 v1.1, 2011-03 pcp, v2.08 program when it is suspended in favor of a higher-priority service request. please refer to section 11.6.3 for more detailed information on the operation of these nodes. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-8 v1.1, 2011-03 pcp, v2.08 11.4 pcp programming model the pcp programming model can be viewed as a set of autonomous programs, or tasks, called channel programs, that share the processing resources of the pcp. channel programs may be short and simple, or very complex; but they can coexist persistently within the pcp. from the programming point of view, the individual parts of a channel program are its instruction sequence in the cmem and its context in the pram. it uses the instruction set and the gprs (r0 - r7) of the pcp processor core to perform the necessary operations, and to communicate with the va rious resources of the on-chip and off-chip system depending on its task in the application. these parts of the programming model are discussed in the following sections (with the obvious exception of the syst em environment outside of the scope of the pcp). 11.4.1 general purpose register set of the pcp the program-accessible register file of the pcp is composed of eight 32-bit general purpose registers (gprs). these registers ar e all accessible by pcp programs directly as part of the pcp instruction set. source and destination registers must be specified in most instructions. these registers are referenced to in this document as rn or r[n], where n is in the range 0 to 7. table 11-3 directly accessible registers register implicit use description r0 accumulator implicit target for some arithmetic and lo gical instructions r1 ? 32-bit general-use register r2 return address 32-bit general-use register r3 ? 32-bit general-use register r4 src (source) source pointer for bcopy/copy instructions r5 dst (destination) destination pointer for bcopy/copy instruction r6 cppn/srpn/ tos/cnt1 cnt1: transfer count for copy tos: type-of-service srpn: 8-bit field used for posting interrupt on exit instruction cppn: current pcp priority number r7 dptr/flags pram data pointe r (dptr) and status flags www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-9 v1.1, 2011-03 pcp, v2.08 r7 is the only one of the eight registers that may not be used as a full gpr. the most significant 16 bits of r7 may not be written, and will always read ba ck as 0. however, no error will occur when writing to the most significant 16 bits. note: the gprs of the pcp are not memory -mapped into the overall address space. they can only be directly accessed throu gh pcp instructions. the contents of all or some of the registers are part of a channel program?s context stored in the pram between executions of the cha nnel program. this context is then accessible from outside the pcp. 11.4.1.1 register r0 r0 is used as an implicit operand destination for some instructions. these are detailed in the individual in struction descriptions. 11.4.1.2 registers r1, r2, and r3 r1, r2, and r3 are general-use registers. it is recommended that, by convention, r2 should be used as a return address register when call and return program structures are used. 11.4.1.3 registers r4 and r5 registers r4 and r5 are also general-use registers. however, the bcopy/copy instructions implicitly use r4 and r5 as full 32-bit address pointers (r4 is used as the source address and r5 as the destination address). as the bcopy/copy instructions use these registers to maintain the address pointers, either or both r4 and r5 values may or may not be modified by the bcopy/copy instructions, depending on the options used in the instructions. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-10 v1.1, 2011-03 pcp, v2.08 11.4.1.4 register r6 register r6 may also be used as a genera l-use register. again however, there are some instructions that use fields within r6. if the copy or exit instructions are used, then the field r6.cnt1 can optionally be used implicitly as a counter. if an exit instruction is used that causes an interrupt, r6.srpn and r6.tos must be configured properly prior to execution of the exit. if interrupt priority management is used, then r6.cppn must be set to the priority level at which the channel shall run at its next invocation, before the exit is executed. the fields for r6 are shown below. pcp register r6 reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cppn srpn rw rw 1514131211109876543210 tos gen gen cnt1 rw rw rw rw field bits type description cppn [31:24] rw general-use/pcp pr iority number posted to picu srpn [23:16] rw general-use/service request priority number for exit interrupt tos [15:14] rw general-use/type-of-service for exit interrupt upper bit of tos is always forced to 0 when transferred into the pcp srns, regardless of the value specifi ed in r6[15]. gen 13 rw general-use gen 12 rw general-use cnt1 [11:0] rw general-use/outer loop count for copy instruction or exit instruction www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-11 v1.1, 2011-03 pcp, v2.08 11.4.1.5 register r7 register r7 is an exception with respect to the other registers in that not all bits within the register can be written, and the implicit use of the remaining bits virtually excludes the use of r7 as a gpr. r7 serves similar purposes as those in the program status word found in traditional processors. r7 holds the flag bits, a channel enable/disable control bit, and the pram data pointer (dptr). the upper 16 bits of r7 are reserved. most instructions of the pcp update the flags (cn1z, v, c, n, z) in r7 according to the result of thei r operation. see table 11-15 on page 11-134 for details on the flag updates of the individual instructions. the values of the flag bits in r7 maintain their state until another instruction that updates their state is executed. note: implicit updates to the flags caused by instruction take precedence over any bits that are explicitly moved to r7. for exampl e, if a mov instruction is used to place 0000ff07 h in r7, then the bit positions for th e c (carry), z (zero) and n (negative) flags are being written with 1. the mov instruction, howeve r, implicitly updates the z and n flag bits in r7 as a result of its operation. because the number is not negative, and not zero, it will update the z and n flags to 0. as a result, the value left in r7 after the mov is complete will be 0000ff04 h (i.e c = 1, z = 0, n = 0). it is recommended that only set and clr instructions should be used to explicitly modify flags in r7. the data pointer, r7.dptr, is the means of accessing pram variables programmatically. it points to a 64-word pram segment that may be addressed by instructions that can use the pram for source or destination operands (xx.p and xx.pi instructions). the 8 bits of the dptr are concatenated with a 6-bit offset value (either specified in the instruction as an immediate value or contained in one of the registers) to give a 14-bit (word) address. a program is able to update the dptr value dynamically, in order to index more than 64 words of pram. note: care must be taken when updating r7.d ptr to ensure that other bits within r7 (e.g. r7.cen) are not in advertently corrupted. the channel enable control bit, r7.cen, allows the enabling or disabling of specific channel programs. if an interrupt request is received for a channel that is disabled an error exit is forced, and an error interrupt to the cpu is activated. the interrupt enable control bit, r7.ien, allows the enabling or disabling of channel interruption on a channel to channel basis. when r7.ien is 0, the channel will continue its execution regardless of the priority of any new service requests. when r7.ien is 1, and conditions allow, the channel will be suspended on receipt of a higher-priority service request. note: see section 11.21.3.1 regarding the use of r7.ien. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-12 v1.1, 2011-03 pcp, v2.08 pcp register r7 reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 dptr res cen ien cnz v c n z rw rw rw rw rw rw rw rw rw field bits type description res [31:16] r reserved read as 0; should be written with 0. dptr [15:8] rw data pointer segment address for pram accesses res 7rw reserved should always be written with 0. cen 6rw channel enable control bit ien 5rw interrupt enable 0 b channel is not interruptible 1 b channel can be suspended in favor of a higher- priority service request cnz 4rw outer loop counter 1 zero flag v 3rw overflow c 2rw carry n 1rw negative z 0rw zero www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-13 v1.1, 2011-03 pcp, v2.08 11.4.2 contexts and context models after initialization, the instruction sequence of a pcp channel program is permanently stored (i.e. usually at least as long as the application is running) in the cmem, and data parameters are held in the pram. these will remain stored regardless of whether a particular channel program is currently idle or is executing (although, of course, the value of data variables in the pram might be modified by the pcp or external fpi bus masters). the contents of the gprs of the pcp (used as address pointers, data variables, intermediate results, etc.) however, are usually only valid for a given channel program as long as it is executing. if another channel program is executed, the channel program will re-use the gprs according to its needs. thus, the state of the gprs of a channel program (termed the ?context? of the channel) needs to be preserved while a channel prog ram is not being executed. the content of the registers needs to be saved when execution of a channel program finishes, and needs to be restored before execution starts again. the pcp implements automatic handling of these context save and restore operations. on termination of a channel program, the state of all or some of the gprs is automatically copied to a defined area in the pram (context save). if the same channel program is re-activated, the contents of the registers are restored by copying the values from the same defined pram area into the appropriate registers (context restore). the defined area in the pram for the context save and restore operations is called the csa. each channel program has its own individual, predefined region in the csa. when a service request is accepted by the pcp, the service request priority number (srpn) associated with the request is used to select the channel program and its respective csa region. 11.4.2.1 context models a context model is a means of selecting whether some or all of the registers are saved and restored when a context switch occurs. in order to serve different application needs in terms of pram space usage, the pcp offers a choice between three different context models: ? full context model: eight registers (8 32-bit words) are saved/restored per channel. ? small context model: four registers (4 32-bit words) are saved/restored per channel. ? minimum context model: two registers (2 32-bit words) are saved/restored. as illustrated in figure 11-2 , the contents of r0 through r7 constitute the full context of a channel program. a small context consists of r4 through r7. use of the small context model allows for correct operation of dma channels, as well as channels which are not required to save large amounts of data in their contexts between invocations. a minimum context saves and restores only r6 and r7. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-14 v1.1, 2011-03 pcp, v2.08 to distinguish the actual register contents fr om the copies stored in the pram context regions, the term crx is used throughout the re st of this document to refer to the register values in the context regions. registers r6 and r7 are always handled in a special way during context save and restore operations, this is described in detail in section 11.4.2.3 . the context model is selected via bit field (pcp_cs.cs), this is a global setting (i.e. the selected context model is used for all channels). once a context model has been selected (during pcp configuration) and the pcp has been started the pcp must continue to use that context model. attempting to change the context model in use during pcp operation will lead to invalid context restore operations which will in turn lead to invalid pcp operation. in the case of small and minimum context models, the unsaved and un-restored registers (shaded in figure 11-2 ) can be thought of as global registers that any channel program can use or change, or reference as constants ? for example as base address pointers (see section 11.20.2 for more detail). note: special care must be taken when using minimum or small context model with nested interrupts (see page 11-151 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-15 v1.1, 2011-03 pcp, v2.08 figure 11-2 pcp context models mca06136 r0 r1 r2 r3 r4 r5 r6 r7 stored context in pram r0 r1 r2 r3 r4 r5 r6 r7 pcp register set restore save 8 words f ull context r0 r1 r2 r3 r4 r5 r6 r7 r4 r5 r6 r7 s mall context restore save 4 words r0 r1 r2 r3 r4 r5 r6 r7 r6 r7 m inimum context restore save 2 words www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-16 v1.1, 2011-03 pcp, v2.08 11.4.2.2 context save area the context save area (csa) is a region in pram reserved for storing the contexts for all channel programs (while any particular channel is not executing). each channel?s context is stored in a region of the csa based on the channel number. the channel number is equal to the priority number (srp n) of the service request. the pcp uses this number to calculate the start address of th e context of the associated channel program. the size of a context is determined by the context model that the pcp has been initialized to use. as all channels use the same context size, the pram address (word address) of the context for a particular channel is simply calculated by multiplying the channel number by the number of registers in the context (8 for full context, 4 for small context and 2 for minimum context). figure 11-3 shows the resulting pram layout, and from this it can be seen that changing t he context model also changes the base address for all regions within the csa. thus, the chosen context model may only be set when the pcp is initialized, and may not be changed during operation. the csa in the pram starts at address 00 h and grows upward. it is partitioned into equally sized regions, where the size of these regions is determined by the selected context model. the priority number (srpn) of a service request is used to access the appropriate context region for the associated channel program. since a request with an srpn of 00 h is not considered as valid request in the tricore architecture, the bottom region (context region 0) of the csa is never used for an actual context. the total size of the csa depends on the context model and the number of service request numbers used in a given system. each priority number used in a service request node which can activate interrupts to the pcp must be represented through a dedicated context region in the pram. the highest address range in the pram used for a context region is determined by the highest priority number presented to the pcp with a service request. the range of usable priority numbers is further determined by the size of the implemented pram and by the space required for other variables and global data located in the pram. see page 11-157 for the implemented size of the pram in the TC1798. as an example, a pram of 2 kbytes, solely used for the csa, can store up to 255 minimum contexts, allowing the highest srpn used for a pcp service request to be 255 (remember, an srpn of 0 and an associated context region is never used; the valid srpns and the context and channel numbers range from 1 to 255). with a small context model, 127 contexts can be stored, resulting in 127 being the highest usable srpn in this configuration. finally, a full context model allows 63 context areas, with 63 being the highest usable srpn. interrupt requests to the pcp with priority numbers that would cause loading of a context from outside the available pram area must not be generated. invalid pcp operation will result should this situation be allowed to occur. the pcp can be optionally configured such that if an interrupt request is received that would cause loading of a context from outside the available pram area then an error exit is forced, and an error interrupt to the cpu is activated (see page 11-44 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-17 v1.1, 2011-03 pcp, v2.08 if portions of the pram are used for other variables and global data, the space available for the csa and the range of valid srpns is reduced by the memory space required for this data. for best utilization of pram, it is advisable to have the csa grow upwards as a contiguous area without any ?holes?, meaning that all srpns in the range 1 ? max. are actually used to place interrupt requests on the pcp. unused regions within the csa (that is, the unused region at the base of the csa and any context regions associated with unused channels) cannot be used for general variable storage. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-18 v1.1, 2011-03 pcp, v2.08 figure 11-3 context storage in pram 4 words not used context #1 pram memory 8 words not used context #1 context #2 mca0613 7 full context srpn = 1 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 00 h 08 h 10 h srpn = 2 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 n 18 h srpn = n1 context #n1 31 0 srpn = 1 00 h 04 h 0c h cr7 cr6 cr5 cr4 cr7 cr6 cr5 cr4 08 h context #2 srpn = 2 context #3 srpn = 3 context #n2 srpn = n2 small context 31 0 minimum context 31 0 00 h 2 words not used srpn = 1 context #1 cr7 cr6 02 h 04 h srpn = 2 context #2 cr7 cr6 06 h context #3 08 h srpn = 3 n32 h context #n3 srpn = n 3 pram memory pram memory note: all addresses in this figure are word addresses n24 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-19 v1.1, 2011-03 pcp, v2.08 when choosing the context model for a given application, the following considerations can be helpful. when choosing the small or the minimum context models, save and restore operations for registers not handled in the automatic context operations can still be handled through explicit load and store instructions under control of the user. this may be advantageous for applications in which the majority of the channels do not need the full context, and only some would require more context to be saved. in this case, a smaller context model can be used, and the channels which would require more register to be saved/restored would do this via explicit load and store instructions. this is especially advantageous if the channel program can be designed such that the initial real-time response operations can be execut ed using only the registers which have been automatically restored. then, as the timing requirements of the service are relaxed, further register contents can be restored from pram through regular load instructions. of course, the contents of these registers needs to be explicitly saved, through regular store instructions, before the exit of the channel program. note: special care must be exercised when using minimum or small context models in conjunction with nested interrupts (see page 11-151 ). the criteria for choosing the context model are listed in the following: ? size of pram implemented in a given derivative ? amount of channels (= srpns) that need to be used in a system ? amount of pram used for general variables and global?s ? amount of context (register content) which need to be saved and restored quickly by most of the most important channels while registers r0 through r5 are always rest ored in a normal manner (according to the context size), registers r6 and r7 merit discussion regarding context restore operations. the memory location cr7 in a context region is used to hold two different pieces of information: the lower part of register r7, and the pc value of the channel. similarly, the memory location cr6 in a context region can also be used to hold two different pieces of information: the value to be restored to register r6, and the operating priority (cppn) value of the channel. this leads to the restore/save operations described in the following two sections. 11.4.2.3 context restore operation for cr6 and cr7 the operation of r6 and r7 context restore varies according to whether the channel program that is starting is a ?new? channel program (i.e. a channel program that is starting in response to the receipt of a new service request) or is a ?suspended? channel program (i.e. a channel program that is re-starting after being suspended in favor of a higher-priority channel program). in additi on, when a ?new? channel program is starting, the context restore operation depends on the channel start mode that has been selected (see page 11-27 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-20 v1.1, 2011-03 pcp, v2.08 channel resume mode figure 11-4 illustrates the operation of a context restore for a ?new? channel program when channel resume mode has been selected (see page 11-28 ). the pc is loaded from cr7[31:16], and the lower half of r7 is loaded from cr7[15:0]. the operating priority of the channel is taken from cr6[31:24] and all of r6 is loaded from cr6. figure 11-4 context restore: channel start in ?channel resume mode? pc mca06138 31 16 0 cppn 0 arb ctl pipn 0 ie 31 16 0 cnt1 cppn srpn tos 31 16 0 cnt1 cppn srpn tos pcp register r 6 31 16 0 cpc cflags stored content cr7 in pram cdptr 31 16 0 0flags cdptr pcp register r 7 16 0 stored content cr6 in pram p cp interrupt c ontrol reg. p cp_icr p cp program c ounter www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-21 v1.1, 2011-03 pcp, v2.08 channel restart mode figure 11-5 illustrates the operation of a context restore for a ?new? channel program when channel restart mode has been selected (see page 11-27 ). the pc is loaded with the channel entry table address, and the lower half of r7 is loaded from cr7[15:0]. the upper half of cr6 is discarded. the operating priority of the channel is taken from cr6[31:24] and all of r6 is loaded from cr6. figure 11-5 context restore: channe l start in channel restart mode 2 * srpn pc mca0613 9 31 16 0 cppn p cp interrupt c ontrol reg. p cp_icr 0 arb ctl pipn 0 ie 31 16 0 cnt1 cppn srpn tos 31 16 0 cnt1 cppn srpn tos pcp register r 6 31 16 0 cpc cflags stored content cr7 in pram cdptr 31 16 0 0flags cdptr pcp register r 7 16 0 p cp program c ounter stored content cr6 in pram 16 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-22 v1.1, 2011-03 pcp, v2.08 suspended channel restart figure 11-6 illustrates the operation of a context restore for a ?suspended? channel program. the pc is loaded from cr7[31:16] (regardless of the channel start mode), and the lower half of r7 is loaded from cr7[15:0]. all of r6 is loaded from cr6. the figure also shows how the operating priority of the channel (pcp_ir.cppn) is restored from the service request node that was used to store the suspended interrupt request (see page 11-96 ). figure 11-6 context restore: suspended channel restart pc mca0614 0 31 16 0 cppn pcp interrupt control reg. pcp_icr 0 arb ctl pipn 0 ie 31 16 0 cnt1 cppn srpn tos 31 16 0 cnt1 cppn srpn tos pcp register r6 31 16 0 cpc cflags stored content cr7 in pram cdptr 31 16 0 0flags dptr pcp register r 7 16 0 p cp program c ounter stored content cr6 in pram 31 16 0 srpn pcp interrupt req node. pcp_srnx 0 r r q srnc 0 0 t o s s r e 0 s r r note: during a context restore for a suspended channel the pcp_srcnx.srnc field (n = 9, 10, 11) is used to determine the channel number. channel number www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-23 v1.1, 2011-03 pcp, v2.08 11.4.2.4 context save operation for cr6 and cr7 the operation of r6 and r7 context save varies according to whether the save operation is the result of a channel exit condition, or whether the channel is being suspended in favor of a higher-priority channel program. channel resume mode figure 11-7 illustrates the operation of a context save for a channel exit when channel resume mode has been selected. the value written to cr7 is created by concatenating the 16-bit pc value with the lower 16 bits of r7. cr6 is written with the value taken from r6. figure 11-7 context save: channel exit in channel resume mode pc mca0614 1 when the context save is due to execution of an exit instruction with ep = 0 the pc is loaded with the appropriate channel entry table address prior to being saved. n ote: 31 16 0 cnt1 cppn srpn tos 31 16 0 cnt1 cppn srpn tos pcp register r6 stored content cr6 in pram 31 16 0 cpc cflags stored content cr7 in pram cdptr 31 16 0 0flags cdptr pcp register r 7 16 0 pcp program counter www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-24 v1.1, 2011-03 pcp, v2.08 channel restart mode figure 11-8 illustrates the operation of a context save for a channel exit when channel restart mode has been selected. this is the same as for channel resume mode except that the pc value is discarded, and the appropriate channel entry table address is written to cr7[31:16]. figure 11-8 context save: channel exit in channel restart mode 2 * srpn mca0614 2 31 16 0 cnt1 cppn srpn tos 31 16 0 cnt1 cppn srpn tos pcp register r6 stored content cr6 in pram 31 16 0 cpc cflags stored content cr7 in pram cdptr 31 16 0 0flags cdptr pcp register r 7 16 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-25 v1.1, 2011-03 pcp, v2.08 channel suspend figure 11-9 illustrates the operation of a context save for a channel that is being suspended. this is the same as for channel resume mode except that an interrupt request is created to allow the channel to be restarted at a later time. this restore operation utilizes one of three specially extended srns (see page 11-96 ) to store the interrupt request. the information stored as part of the interrupt request is the channel number (srpn), and the operating priority (cppn) with which the channel was operating prior to being suspended. this operation in conjunction with the suspended channel restore operation shown in figure 11-6 allows the temporary suspension of a channel in favor of a higher-priority channel. figure 11-9 context save: channel suspend pc srpn 1 1 mca0614 3 31 16 0 cnt1 cppn srpn tos 31 16 0 cnt1 cppn srpn tos stored content cr6 in pram 31 16 0 cpc cflags stored content cr7 in pram cdptr 31 16 0 0flags dptr pcp register r7 16 0 p cp program c ounter pcp register r6 31 16 0 srpn p cp interrupt service r equest node. p cp_srnx ( x = 9, 10, 11) 0 r r q srnc 0 0 t o s s r e 0 s r r 31 16 0 cppn pcp interrup t control reg . pcp_icr 0 arb ctl pipn 0 ie 0 8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-26 v1.1, 2011-03 pcp, v2.08 11.4.2.5 initializati on of the contexts the programmer is responsible for configur ing each channel program?s context before commencing operation. because this must be done by writing to the pcp across the fpi bus, it is important to understand exactly where each channel program?s context is from the fpi bus perspective (see page 11-58 for details). 11.4.2.6 context save optimization the pcp has an optimized context-switching strategy consisting of optimization of both context load and store. during a context load in which the channel that is starting is also the last channel that the pcp was running then the pcp gprs already contain the values appropriate to the channel. in this case there is no need to reload the context (i.e. the pcp can immediately continue operation at the appropriate point in the code without having to perform a context load). during a context store (i.e. the pcp exits a channel as a result of exit or debug instructions or exits in response to a higher-priority channel interrupt), only those registers that have been updated (i.e. written to) since the context was loaded are saved to the csa. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-27 v1.1, 2011-03 pcp, v2.08 11.4.3 channel programs the pcp cmem is used to store the instruction sequences, the channel programs, for each of the pcp channels. the individual channel programs for the individual pcp service requests can usually be viewed as independent and separate programs. there is no background program defined and running for the pcp in TC1798 as there would be with traditional processors. when the pcp receives a service request for a specific channel program, it needs to determine exactly which channel program to activate and where to start its execution. to accommodate different application needs, the pcp architecture allows the selection of two different entry methods into the channel programs: ? channel restart mode ? channel resume mode channel restart mode forces the pcp to begin each channel program from a known fixed point in the cmem that is related to the interrupt number. at the entry point related to the interrupt number in question, there will typically be a jump instruction which vectors the pcp to the main body of the channel pr ogram. this is identical to the traditional interrupt vector jump table. in channel restart mode, channel code execution will always start at the same address in the interrupt entry table each time the channel is requested. channel resume mode allows the pcp to begin execution at the pc address restored as part of the channel program context. th is mode allows code to be contiguous and start at any arbitrary address. it also allows for the implementation of interrupt-driven state machines, and even the sharing of code across multiple programs with different context. the selection of one of the two modes is a global pcp setting, that is, it applies to all channels. selection is made via the pcp_cs.rcb bit in the pcp configuration register pcp_cs (see page 11-69 ). 11.4.3.1 channel restart mode channel restart mode is selected with pcp_cs.rcb = 1. in this mode, the pcp views the cmem as being partitioned into an interrupt entry table at the beginning of the cmem, and a general code storage area above this table. the interrupt entry table consists of two instruction slots (2 16-bit) for each channel. when a pcp service request is received, the pcp calculates the start pc for the requested channel by a simple equation based on the srpn of that request (pc = 2 srpn). it then executes the instruction found on that address. if more than two instructions are required for the operation of the channel program, then one of the instructions within the interrupt entry table must be a jump to the remainder of the channel?s code. the pcp execut es the channel?s code until an exit condition or higher- priority interrupt is detected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-28 v1.1, 2011-03 pcp, v2.08 it is recommended that all exit instructions for all channels should use the ep = 0 setting when the pcp is operated in channel restart mode (see page 11-115 ). note that when channel restart mode is in use a channel entry table must be provided with a valid entry for every channel being used. figure 11-10 shows an example of cmem organization when channel restart mode has been selected. failure to provide a valid entry for all channels that are in use will lead to invalid pcp operation. 11.4.3.2 channel resume mode channel resume mode is selected with pcp_cs.rcb = 0. in this mode, the user can arbitrarily determine the address at which the channel program will be started the next time it is invoked. for this purpose, the pc is saved and restored as part of the context of a pcp channel. additional flexibility is available when channel resume mode is globally selected by configuring each exit instruction to determine the channel start address to be used on the next invocation of a channel (see page 11-115 ). when the ep = 0 setting is used, the pc value saved in the channel?s context (saved in cpc) is the address of the appropriate location in the channel entry table. this forces the channel to start at the appropriate location in the interrupt entry table at next invocation. when the ep = 1 setting is used, the pc value saved in the channel?s context is the address of the instruction immediately following the exit instruction. the use of the ep = x setting with the exit instruction allows the mixture of channels that use a channel restart strategy with others using a channel resume strategy, and also allows individual channels to use either strategy as appropriate on different invocations. note: a valid entry within a channel entry t able must be provided for every channel that uses an exit instruction with the ep = 0 setting when channel resume mode has been selected. failure to provide a valid entry for such channels will lead to invalid pcp operation. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-29 v1.1, 2011-03 pcp, v2.08 figure 11-10 examples of code memory organization for channel restart and channel resume modes note: the cmem address offsets in the above figure are shown as pcp instruction (half- word) offsets. to obtain fpi address offset s (byte offset) multip ly each offset by two. code memory cmem instruction #1 2 half-words not used instruction #2 mca06144 00 h 02 h srpn = 1 channel #1 04 h instruction #2 instruction #1 channel #2 srpn = 2 srpn = 3 06 h instruction #2 instruction #1 channel #3 srpn = n1 n 12 h instruction #1 instruction #2 channel #1 channel #1 main code channel #3 main code channel #n1 main code channel #2 main code channel restart mode 16 0 channel entry table channel resume mode 16 0 channel #1 main code 00 h channel #3 main code channel #n1 main code channel #2 main code code memory cmem www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-30 v1.1, 2011-03 pcp, v2.08 11.5 pcp operation this section describes how to initialize the pcp, how to invoke a channel program, and the general operation of the pcp. 11.5.1 pcp initialization the pcp is placed in a quiescent state when the TC1798 is first powered-on or reset. before a channel program can be enabled, the pcp as a whole must be initialized by some other fpi bus master, typically the cpu. initialization steps include: ? configure global pcp registers. ? initialize pcp control and status register (with pcp_cs.en = 0). ? configure interrupt system via pcp_icr. ? load channel programs into the cmem. ? load initial context (if/as required) of channel programs in pram (r0 - r7 for maximum context, r4 - r7 for small cont ext, r6 - r7 for minimum context). only those registers in each channel whose initial content is required on first invocation of the channel need to be loaded. this may need to include the initial pc, depending on the value of pcp_cs.rcb. ? clear r7 in the context for unused channels. ? enable pcp operation pcp_cs.en = 1. now, the pcp is able to begin accepting interrupts and executing channel programs. 11.5.2 channel invocation and context restore operation a channel program is started when one or other of the following conditions occurs: ? the current round of pcp interrupt arbitration results in a winning interrupt number (srpn) and the pcp is currently quiescent (has exited the previous channel and stored the context for that channel). ? the current round of pcp interrupt arbitration results in a winning interrupt number (srpn) that has to be greater than the current channel priority (srpn > cppn), if suitable service request node space is available in the psrn to store a suspended interrupt request and the current channel allows interrupts (r7.ien = 1). see also page 11-35 ). when this happens the winning srpn becomes the current interrupt, and a context restore operation occurs before the new ch annel program can begin operation, as follows: ? the context of the channel (= winning srpn) is restored from pram into the gprs from the appropriate address within the csa. depending on the value of pcp_cs.cs, a full, small, or minimum context restore is performed. ? the new priority level of the pcp is ta ken from r6.cppn field and is written to pcp_icr.cppn. this value can be useful during debugging, as the cppn of the currently executing or last-executed cha nnel program can be read from pcp_icr. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-31 v1.1, 2011-03 pcp, v2.08 after the channel program starts, the value of r6 may be changed without altering the value of the effective cppn, because updates to the value of r6.cppn have no effect until the next invocation of the channel program. ? if the r7.cen bit is clear (0), then an error has occurred because a disabled channel program has been invoked, the pcp_es.dcr bit is set to flag the error, and the channel program performs an error exit (see page 11-31 ). ? if the r7.cen bit is set (1), then code execution begins at the value of the restored pc or at the address of the interrupt routine in the channel entry table, depending on the value of pcp_cs.rcb. special care needs to be taken regarding the number of clock cycles required to switch context when the last state of the pcp before channel exit was execution of channel ?n? (srpn = ?n?), and the current service request is also srpn = ?n?. in this case, the pcp processor core should not load the context (as the pcp gprs already contain the correct content), but continue operation from the current point and state (noting that the pc value should be set to the appropriate channel entry point if pcp_cs.rcb = 1). 11.5.3 channel exit and context save operation the context of a channel program must be saved when it terminates. three events can cause the termination of a channel program: ? execution of the exit instruction (normal termination) ? occurrence of an error ? execution of the debug instruction (channel termination is optional). the debug instruction must only be used in debug mode; otherwise an ?illegal operation? (iop) error will be generated these channel termination possibilities are described in the next sections. 11.5.3.1 normal exit under normal circumstances, a channel pr ogram finishes by executing an exit instruction. this instruction has several setting fields that allow the user to specify a number of optional actions to be perform ed during the channel exit sequence (see page 11-115 ). these optional actions are: ? decrement counter cnt1 ? set the start pc for the next channel invocation to the next instruction address (channel resume) or to the channel entry address (channel restart) ? disable further invocations of this channel ? generate an interrupt request to the cpu or to the pcp itself when the exit instruction is executed, the following sequence occurs: ? if ec = 1 is specified counter r6.cnt1 is decremented and the cn1z flag is updated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-32 v1.1, 2011-03 pcp, v2.08 ? if st = 1 is specified bit r7.cen (channel enable) is cleared (i.e. the channel is disabled). ? if ep = 0 is specified or pcp_cs.rcb = 1 (channel restart mode has been selected), the pcp program counter to be saved to context location cr7.pc is set to the appropriate channel entry table address. if ep = 1 is specified and pcp_cs.rcb = 1 (channel resume mode has been selected), the pcp program counter to be saved to context location cr7.pc is set to the address of the instruction immediately following the exit instruction. ? if int = 1 is specified and the specified condition cc_b is true, then an interrupt request is raised according to the srpn value held in r6.srpn. the interrupt is asserted via one of the pcp_srcx registers, where x is determined by the combination of the value of r6.tos and the list of free entries. this allows the conditional creation of a service request to the cpu or pcp with the srpn value indicated in register r6.srpn. ? the channel program?s context (including all register modifications caused within this exit sequence) is saved to the appropriat e region in the pram context save area. depending on the value of pcp_cs.cs, either a full, small, or minimum context save is used. special care needs to be taken to optimi ze the number of clock cycles required to perform a context save. during a context save, the pcp processor core needs only to save those registers that have been written since the last context restore was performed. note: particular attention must be paid to the values of r6 and r7 prior to execution of the exit instruction. when posting an inte rrupt request, the user must ensure that r6.srpn and r6.tos contain the correct values to generate the required interrupt request. when using the outer loop counter (cnt1), the user must ensure that the value in r6.cnt1 will prov ide the required function. when using interrupt priority management, the user must ensure that r6.cppn contains the interrupt priority with which the channel is to run on next invocation. if the channel is to be subsequently re-invoked, the user must ensure that the channel enable bit (r7.cen) is set. 11.5.3.2 error condition channel exit pcp error conditions can occur for a variety of reasons (e.g. an invalid operation code was executed by a channel program, or an fpi bus error occurred). when an error condition occurs, the pcp error status register (pcp_es) is updated to reflect the error, and the channel program is aborted. the error exit sequence is as follows: ? the channel enable bit r7 .cen is cleared. this means the channel program will be unable to restart until another fpi bus master has re-configured the channel program?s stored context to set cr7.cen to 1 again. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-33 v1.1, 2011-03 pcp, v2.08 ? the pc of the instruction that was executing when the error occurred is stored in pcp_es.epc. ? the number of the channel program that was executing when the error occurred is stored in pcp_es.epn. ? the error type is set in the appropriate field of register pcp_es. ? the context is saved back to the pram csa. depending on the chosen context size (pcp_es.cs) a full, small, or minimum context save is performed. ? if the error condition was not due to an fpi bus error or a debug instruction, then an interrupt request to the cpu is gener ated with the priority number stored in register pcp_cs.esr. the repetitive posting of pcp error interrupts will not cause an overwhelming number of interrupts to the cpu. in this situation, the pcp?s cpu service request queue (see page 11-35 ) will quickly fill, and force the pcp to stall until the cpu can resolve the situation. note: an error condition (other than an fpi bus error) will result in an interrupt being sent to the cpu. the interrupt r outine that responds to this interrupt must be capable of dealing with the cause as recorded in pcp_es, and it must be able to restore the channel program to operation. the minimum required to restart the channel program is to set the context value of cr7.cen = 1. 11.5.3.3 debug exit if the debug instruction is programmed to stop the channel program execution (sdb = 1 has been specified), the pcp performs an exit sequence that is very similar to the error exit sequence, with the exception that no interrupt request to the cpu is generated. this sequence is: ? if rta = 0, then the channel enable bit r7.cen is cleared. this means the channel program will be unable to restart until another fpi bus master has re-configured the channel program?s stored context to set cr7.cen to 1 again. otherwise, the r7.cen bit remains unchanged, and the pc is decremented (such that it points to the debug instruction) ? if eda = 1, a break-point event is generated ? if dac = 1, then the pcp_cs.en bit is cleared. this means that the pcp will not execute any further channel programs until the pcp_cs.en bit is set by another fpi bus master ? the address of the debug instruction (i.e. the current pc) is stored in register pcp_es.pc ? the current channel number is stored in register pcp_es.pn the execution of the current channel program is stopped at the point of the debug instruction. this instruction only disables the current channel; the pcp will continue to operate, accepting service requests for other channels as they arise. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-34 v1.1, 2011-03 pcp, v2.08 note: the debug instruction must be only used in debug mode; otherwise an ?illegal operation? (iop) error will be generated. 11.6 pcp interrupt operation the picu and the psrns (pcp_src[11:0]) are similar to the cpu?s icu and all other srns in the system. they do, however, have some special characteristics, which are described in the following sections. figure 11-11 shows an overview of the pcp interrupt scheme. figure 11-11 pcp interrupt block diagram mca06145 winning srpn, priority & interrupt type pcp core queue full nesting available cppn srpn tos pcp_src4 select pcp_src2 pcp_src3 pcp_src9 pcp_src10 pcp_src11 pcp_src0 pcp_src1 pcp service request nodes picu suspended interrupt taken pcp queue full pcp queue winner interrupt bus 0 (cpu) interrupt bus 1 (pcp) pcp_src5 select pcp_src6 select pcp_src7 select pcp_src8 select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-35 v1.1, 2011-03 pcp, v2.08 11.6.1 issuing service requests to cpu or pcp the pcp may use one of two mechanisms to raise an interrupt request to the cpu or itself. the first, and most inefficient, method for a pcp channel program is to issue service requests by performing an fpi bus writ e operation to an external service request node (srn). alternately, the pcp can raise a service request using one of its own internal srns. an interrupt can only be ge nerated by the pcp via an internal srn when executing an exit instruction, or when an error condition occurs. in the following descriptions, pcp service requests triggered through an exit instruction or the occurrence of an error are called ?implicit? pcp service requests to distinguish them from the ?explicit? way of generating a service request through an fpi bus write to a service request node external to the pcp. 11.6.2 pcp interrupt control unit the picu operates in a similar manner to the icu of the cpu. the picu manages the pcp service request arbitration bus, and handles the communication of service requests and priority numbers to and from the pcp kernel. the pcp_icr register is provided to control and monitor the arbitration process. when one or more service requests to the pcp are activated, the picu performs an arbitration round to determine the request wi th the highest priority. it then places the priority number of this ?winning? service reque st into the pipn field of register pcp_icr, and generates a service request to the pcp kernel. if the pcp kernel is currently busy proce ssing a channel program, the new request is left pending until the current channel program has finished. when the pcp kernel is ready to accept a new service request, it calculates the context start address from the pending interrupt priority number, pipn, stored in register icr, and begins with the context restore. it notifies the picu of the acceptance of this request, and in turn the picu acknowledges the winner of the last arbitration round. this service request node then resets its service request flag, srr. there is one special condition in which the picu operates differently from the way that the cpu interrupt control unit operates. this special operation is described on page 11-38 . the pcp interrupt arbitration can be adapted to the application?s needs and characteristics through controls in register pcp_icr. bit field pcp_icr.parbcyc controls the number of arbitration cycles pe r arbitration round (one through four cycles), while bit pcp_icr.ponecyc controls whether one arbitration cycle equals one or two system (fpi bus) clock cycles. 11.6.3 pcp service request nodes the pcp contains twelve service request nodes, including twelve service request control registers, pcp_src0 to pcp_src11, whic h are provided for implicit pcp service www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-36 v1.1, 2011-03 pcp, v2.08 requests. the service request control register s differ from standard src registers in that they are fully controlled by the pcp kernel ; they are read-only registers during pcp operation. the user cannot generate interrupts by writing to them. the twelve service request nodes are split into four groups. ? the first group, containing registers pcp_src0 and pcp_src1, handles implicit pcp service requests targeted to the cpu. the type-of-service control fields, tos, of these registers are hard-wired to 00 b , directing the requests to the cpu. ? the second group, registers pcp_src2 and pcp_src3, handles the service requests targeted to the pcp itself. the res pective tos field of these registers are hard-wired to 01 b , directing the requests to the pcp. ? the third group, containing registers pcp_src4 to pcp_src8, have programmable tos fields which allow these registers to be assigned (at configuration time) to any of the available interrupt buses. ? the fourth group, containing registers pcp_src9, pcp_src10 and pcp_src11, are an extended version of a standard se rvice request node. these handle service requests targeted to the pcp itself, including service requests representing a suspended interrupt. the respective tos fi eld of these registers are hard-wired to 01 b , directing the requests to the pcp. the service request enable bits, sre, of t he pcp_srcx registers are hard-wired to 1, meaning these service requests are always enabled. note: the number of interrupt buses is device-dependent. programming a pcp_srcx register (x = 4 to 8) with a tos value representing a non-available interrupt bus (10 b or 11 b in the TC1798) will disable service request node x. the actual service request flag and the service request priority number of the pcp_srcx registers are updated by the pcp when it generates an implicit service request. the way this is performed is described in the following section. the service request nodes in each of the groups described above are implemented as queues with the appropriate number of ent ries. when the pcp generates an implicit service request, it places the request into t he next available free entry of the appropriate queue rather than writing it into a spec ific register. queue management logic automatically ensures proper handling of the queue. if all entries of a queue are filled with pending service requests, the queue managem ent reports this condition to the pcp kernel via a ?queue full? signal. in the following descriptions, the terms ?cpu queue? and ?pcp queue? are used to refer to the queues in the two groups of pcp service request nodes. 11.6.4 issuing pcp service requests the pcp can issue implicit service requests on the execution of an exit instruction, when suspending a channel, or when an error occurs during a channel program execution. while the service request generation for the exit instruction is optional, a www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-37 v1.1, 2011-03 pcp, v2.08 service request is always generated when a channel is suspended or an error occurs. further differences between these three mechanisms are detailed in the following sections. 11.6.4.1 service request on exit instruction an implicit pcp service request is issued when the int field of the exit instruction is set to 1 and the specified condition code, cc_b, of this instruction is true. such a service request can be issued to any of the available interrupt buses, depending on the programmed value in the tos field of register r6. the pcp examines the tos field in register r6 and issues a service request to the appropriate queue of the service request nodes. along with this request, it passes the se rvice request priority number stored in the srpn field of register r6 to the queue. if the queue has a free entry left, the service request flag, srr, of the associated service request register, pcp_srcx, will be set, and the service request priori ty number will be written to the srpn field of the src register. please see page 11-38 for the case where there is no free entry in the queue. because the desired service request is pr ogrammed through the tos and srpn fields in register r6, each channel program can issue its individual service request. note that this register needs to be programmed proper ly if a service request is to be generated by the exit instruction. 11.6.4.2 service request on suspension of interrupt an implicit pcp service request is issued when the pcp suspends execution of the ongoing channel program in favor of a servic e request with a higher priority. such a service request is always issued to the pcp? s own interrupt bus and is stored in one of the three extended service request nodes (pcp_scr9, pcp_src10, pcp_src11). along with this request, it passes the current channel operating priority (cppn) as an srpn and also the channel number (the original srpn). the service request flag, srr, and the restart request flag, rrq, of the associated service request register, pcp_srcx, will be set, the operat ing priority will be written to the srpn fi eld, and the channel number will be written to the srnc field of the src register. use of the operating priority as the srpn for resumption of the channel program ensures that during subsequent arbitration rounds the pcp will resume execution of the suspended channel program at the appropriate time. the pcp treats an interrupt request with the rrq bit set in a special fashion. in this case the pcp clears the interrupt request bit in th e appropriate internal service request node but does not issue an interrupt acknowledge to any external nodes. this prevents the unwanted clearing of external service requests with an srpn that matches the priority of a suspended channel. note: the pcp will only suspend channel operation when there are two or more free srns with the appropriate tos value for the pcp, and one of the free srns is an www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-38 v1.1, 2011-03 pcp, v2.08 extended service request node. this allows for the posting of an interrupt request to the pcp on exit from the new channel program. 11.6.4.3 service request on error while a service request triggered through an exit instruction is optional and can be issued either to the cpu or to the pcp itself, a service request due to an error condition will always be automatically issued and will always be directed to the cpu. the pcp issues a service request to the cpu queue of the service request nodes. along with this request, it passes the srpn stored in the esr field of register pcp_cs to the queue. if the queue has a free entry left, the srr flag of the associated service request register, pcp_srcx, will be set, and the srpn will be written to the srpn field of the src register. see next section for the case wher e there is no free entry in the queue (queue full). due to the fact that the priority number is stored in the global control register pcp_cs, all channel programs share the same service request routine in case of an error. the exact cause of the error and the channel number of the program that was executed when the error occurred can be determined through examination of the contents of the error/debug status register, pcp_es. 11.6.4.4 queue full operation queuing the implicit service requests typically allows the pcp to continue with the next service request without stalling. the depth of the queue and the number of channel programs using them determines the stall rate. depending on the selected service provider (via r6.tos in case of an exit interrupt or always to the cpu in case of an error interrupt), the request is routed to a free entry in the appropriate queue. if no free entries are available in a queue at the time the pcp wants to post a request to that queue, the pcp is forced to stall until an entry becomes clear. this ensures that the pcp does not lose any interrupts. an entry in a queue becomes free when its srr flag, is cleared through an acknowledge from the picu (that is, the cpu or pcp, as appropriate, has started to service this request). one special case needs to be resolved for the pcp-related queue through special operation of the picu. consider the case in which the pcp queue is full, meaning registers pcp_src2, pcp_src3 and pcp_src9 to pcp_src11 are already loaded with pending service requests to the pcp. if the pcp kernel now needed to post an additional service request into that queue, a deadlock situation would be generated: the pcp would stall, since there is not a free entry in the pcp queue in which to place the request. in turn, as the pcp is stalled, it cannot accept new service requests and so the pcp service request queue cannot be emptied. this would result in a deadlock of the pcp. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-39 v1.1, 2011-03 pcp, v2.08 to avoid such a deadlock, the picu performs a special arbitration round as soon as the pcp queue becomes full. in this arbitration round, only the service request nodes assigned to the pcp queue are allowed to participate; all service requests from nodes external to the pcp are excluded, regardless of whether their priorities are higher or lower than those of the pcp queue. in this way, it is guaranteed that one entry in the pcp queue gets serviced, freeing one slot in the queue. the pcp programmer needs to carefully consider this special operation. it ensures that deadlocks are avoided, but it implies that if too many pcp channel programs post service requests to the pcp (self-interrupt), the pcp will have to service these rather than outside interrupt sources. depending on the priority given to these requests, this could undermine an otherwise appropriate use of the interrupt priority scheme. it is recommended that the system be designed such that in most cases, high-priority numbers can be assigned to these self-interrupt s, so that they can win normal arbitration rounds, avoiding the situation where the pcp queue becomes full. note: if the cpu queue is full, the pcp can continue to operate until it needs to post another service request to the cpu queue. 11.7 pram protection to allow the pcp to handle system critical tasks it is nece ssary to ensure that the pcp can operate properly rega rdless of a failure in another part of the system or the pcp itself. this means that it is necessary to prot ect all or part of the content of the pram from such failures. by default, after reset, the pram can be considered to be a single memory space writeable both by fpi masters and by instructions executed by the pcp itself. however the pcp contains a programmable protection scheme allowing the definition of up to four memory regions with different protection from fpi pram writes and internally generated pram writes. this is illustrated in figure 11-12 below:- www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-40 v1.1, 2011-03 pcp, v2.08 figure 11-12 pram regions note: figure 11-12 shows a typical configuration that might be used. configuration is sufficiently flexible, however, that all of, none of, or any combination of the above regions can be implemented and that the region boundaries can be set with a granularity of at least 256 bytes. while figure 11-12 shows four regions, in reality the protection scheme can be seen from two viewpoints:- ? protection from fpi writes (see section 11.7.1 ). ? protection from internally generated pram writes (see section 11.7.2 ). protection of pram is provided to allow running of system critical tasks on the pcp. protection means that such tasks can be made immune from failures outside of the pcp or indeed from software failures in non -critical tasks running on the pcp itself. pram protection is based around the concept of ?protected? and ?unprotected? channel programs. a ?protected? channel program is one that is running a critical system task and is termed ?protected? since it (and any other protected channel programs) have open pram general channel pram protected channel pram context region writable by pcp software? writable by fpi? yes yes no no no yes yes/no (can be limited to writes by protected channels only) yes/no (can be protected against writes by all channels) cs.pps pprot.psize pprot.fbase www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-41 v1.1, 2011-03 pcp, v2.08 write access to an area of pram that cannot be modified by an unprotected channel program. determination of whether a channel is pr otected or unprotected is performed by examination of the channel number against a programmable threshold (programmed via pcp_pprot.pthres). in addition to the threshold the user can select (via pcp_pprot.pcat) whether channel programs above (and including the threshold) are protected or whether channel programs below (and including the threshold) are protected. 11.7.1 protection of pram against fpi writes the pram fpi protection function is provided so that once the pram has been loaded (typically at system initialization) the pram can be partially or totally prot ected against fpi write accesses. this function is controlled by the pcp_pprot register ( ?pram protection register, pc p_pprot? on page 11-87 ). when the protection function is enabled (via pcp_pprot.en) any incoming fpi write access outside a defined pram address range (defined by pcp_pprot.fbase) is issued with an error response and the pram content remains unmodified. the address range can be select such that an ?open window? of pram (based at the top of pram) remains available for incoming fpi write accesses. the ?open window? is provided as pram is often used for implementation of a ?mail-box? to allow communication between the pcp and other on-chip cores. regardless of the enabling of write protection the entire pram content remains readable via fpi. note: the pcp internal pram wr ite instructions (i.e. instru ctions that modify the pram content) are unaffect ed by this protection. 11.7.2 protection of pram against internally generated pram writes protection of pram against internal writes is performed via two regions:- ? context save region ? protected channel pram 11.7.2.1 context save region protection the context save region can be protected by the pram partitioning scheme (see ?pcp control and status register, pcp_cs? on page 11-69 ). this protection is enabled via pcp_cs.ppe and the size of the context area bei ng protected is defined by pcp_cs.pps. when enabled the context regi on is protected from writes by any channel program (i.e. regardless of whether protected or unprotected). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-42 v1.1, 2011-03 pcp, v2.08 note: this scheme also limits the number of channel programs that can be invoked. note: fpi pram write accesses to pram are unaffected by this protection. 11.7.2.2 protected channel pram protection to ensure that an unprotected channel program cannot corrupt the pram assigned to a protected channel program it is necessary to protect the pram space used by the protected channels from instruction exec uted by non-protected channels. the pcp provides a protection scheme which prevent s corruption of a programmable range of locations at the base of pram by writes generated by a non-protected channel. this region is termed the ?protected channel pram?. protection is enabled via pprot.eni and the size of the protected region is controlled by pprot.psize. this function is controlled by the pcp_pprot register ( ?pram protection register, pcp_pprot? on page 11-87 ). whenever a unprotected channel program ex ecutes a pram write instruction (and protection is enabled) the target address will be examined to determine whether it lies within the protected channel pram region. if the address lies within the region then the pram write will not take pl ace and the pcp will exit the channel with an iop (illegal operation) error. note: fpi pram write accesses to pram are unaffected by this protection. 11.8 fpi interface the pcp operates both as an fpi master and an fpi slave. 11.8.1 operation as an fpi master the pcp generates fpi read and write transacti ons in response to execution of pcp fpi instructions. the pcp can generate byte, half-word and word single transactions and bursts of length two, four and eight. all fpi transactions are generated in supervisor mode. for high integrity systems it is necessary to prevent the pcp from generating unwanted fpi writes to critical locations in the event of a pcp malfunction. to address this problem a memory protection feature is provided to control the address range that can be written to by the pcp. the scheme is based around a user definable fpi address window. along with defining the window base address and size the user can select whether:- ? writes are allowed only to addresses that are within the window (limit). ? writes are allowed only to addresses that are outside the window (exclude). whenever the pcp executes an fpi instruction that will result in an fpi write accesses the destination address is checked to ensure that it is to an allowed address. if a write access is to an address that is not allowed then the write will not take place and the pcp will exit the channel with an iop (illegal operation) error. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-43 v1.1, 2011-03 pcp, v2.08 this function is controlled by the pcp_fwwin register (see page 11-91 ). 11.8.2 operation as an fpi slave the pcp is visible to fpi masters as a 256 kbyte r/w block of memory on the system bus. the pcp must be accessed only with word (32 bit) a ccesses. accessing an unassigned address (i.e. an address outside the range of control & status registers, pram and cmem) will generate an fpi bus error. all pcp locations can be read in either user or supervisor modes. all writes must be performed in supervisor mode. attempting to write to any pcp location in user mode will gen erate an fpi error. some control and status registers are endinit protected. there are some additional user selectable fpi write protection options to support high integrity operation:- ? some/all control and status registers can be programmed to be endinit protected. ? cmem can be programmed to be read only. ? pram can be programmed to be partially or wholly read-only. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-44 v1.1, 2011-03 pcp, v2.08 11.9 pcp error handling the pcp contains a number of fail-safe mechanisms to ensure that error conditions are handled gracefully and predictably. in addition to providing an extra level of system robustness suitable for high integrity and safety-critical systems, these mechanisms can often ease the task of finding programming errors during the development process. whenever an error is detected, the channel program that was executing exits and the pcp_es register is updated with information to allow determination of the error that occurred, the instruction address, and the channel program that was executing when the error occurred (see page 11-32 ). 11.9.1 pram protec tion violation pram can be considered as being split into a number of distinct areas (see section 11.7 ). the default configuration of the pcp allows the pcp to use pram as a single area. while this default configuration allows complete flexibility regarding the use of pram, this flexibility also introduces the possibility of invalid pcp operation as a result of the following issues: ? any channel program is allowed to write to any pram location (including any location in the csa). this means that a channel program may be inadvertently programmed to corrupt the context save region or pr am storage belonging to another channel, causing invalid operation of the corrupted channel when it next executes. ? generation of an interrupt request to the pcp with a priority number that would cause loading of a context from outside the csa will cause the spurious execution of a channel program with an invalid context loaded from outside the csa. 11.9.1.1 enforced pram partitioning the lowest of the pram areas is the csa (see page 11-16 ) which is used for storing context information for each active channel while the channel program is not actually executing. to avoid spurious pcp operation as a result of programming errors, the pcp can be optionally configured via the global pcp cont rol and status register (pcp_cs) to enforce strict partitioning of pram between the csa and the remainder of pram. pram partitioning is selected by programming pcp_cs.ppe = 1 and the size of the csa in use is selected via the pcp_cs.pps bit field (see page 11-69 ). when pram partitioning has been enabled, a pcp error will be generated on either one of the following events: ? a channel program executes a pram write instruction with a target area within the csa. this prevents a channel from corrupting the context save region of any other channel. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-45 v1.1, 2011-03 pcp, v2.08 ? an incoming interrupt request causes the pcp to attempt to load a context from outside the csa. this prevents the pcp from running an invalid channel program as a result of an invalid interrupt request. note: enabling pram partitioning (pcp _cs.ppe = 1) with a csa size of zero (pcp_cs.pps = 0) is an invalid setting and will cause a pcp error event whenever any interrupt request is received by the pcp. 11.9.1.2 protected channel pram when a protected channel pram area has been programmed (see section 11.7.2.2 ) then any attempt by an unprotected channel program to write to the protected channel pram area will generate a pcp error. 11.9.2 fpi write window violation when an fpi write window has been programmed (see section 11.8.1 ) then any attempt by a channel program to write to an fpi address that has been disallowed will generate a pcp error. 11.9.3 channel watchdog the channel watchdog is a pcp internal watchdog that optionally allows the user to ensure that the pcp will not become locked into executing a single channel due to an endless loop or unexpected software sequence. as each channel executes, the pcp maintains an internal count of the number of instructions that have been read from cmem since the channel started. if the watchdog function is enabled (by programming pcp_cs.cwe = 1) and the internal instruction fetch counter reaches the threshold programmed by the user (programmed vi a pcp_cs.cwt), a pc p error is generated. the threshold setting (pcp_cs.cwt) is global to all channels. from this it follows that the threshold must be selected to be greater than the maximum number of instructions that can be fetched by any channel program, taking all channels into consideration. it should be noted that the instruction width of the pcp is 16 bits and that therefore execution of an instruction that is encoded into 32 bits (e.g. ldl.il) will generate two cmem instruction reads. that will therefore cause the internal watchdog counter to be incremented twice. note: enabling the channel watchdog function (pcp_cs.cwe = 1) with a threshold of zero (pcp_cs.cwt = 0) is an invalid setting and will cause a pcp error event whenever any interrupt request is received by the pcp. 11.9.4 invalid opcode the pcp includes the invalid opcode mechanism to check that each instruction fetched from cmem is a legal instruction. if the pc p attempts to execute an illegal instruction, then a pcp error is generated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-46 v1.1, 2011-03 pcp, v2.08 note: the debug instruction must be only used in debug mode otherwise it will be considered to be an illegal operation and will generate an iop error. 11.9.5 instruction address error an instruction address error is generated if the pcp attempts to execute an instruction from an illegal address. an address is considered to be illegal if: ? the address is outside the available cmem area (see page 11-157 for the cmem size implemented in this derivative) and/or ? the specified address could not be contained in the 16-bit pc (i.e. an address calculation yielded a 16-bit unsigned overflow). the second of these cases can result from an address calculation either from the execution of a pc relative jump instruction (either a jc, jc.i, or jl instruction), or the pc being incremented following execution of the previous instruction. 11.10 software in-system test support the pcp protects against memory integrit y errors by ecc protection of the pcp memories. this has the unfortunate side-e ffect of requiring memory blocks wider than the normal data access path to the memory. the additional ecc storage bits are not easily accessible via the existing data paths, causing significant problems where sist based testing of the memories is required. in order to address this problem the pcp includes improved sist support, allowing all pcp memory arrays to be accessedto allow the test and d ebug of the fault tole rant memory systems. the mapping of hidden memory ecc bits into the pcp address space is controlled by the setting of bits within the sist mode access control register (smacon). the existence of the smacon register is architecturally defined. however, the fields within smacon and the effect of the fields on the memory map of the pcp are implementation specific. hidden ecc bits are mapped into the cmem and pram areas by setting bits in the smacon register. the smacon register is a sfr which can only be written in supervisor mode and is endinit protected. the definition of the smacon register for the pcp is shown on page 11-81 . the control fields within the smacon register allow individual control of the local memories. each memory may be mapped to operate in a number of different modes. normal operation, no mapping, error detection/correction enabled no mapping of the ecc bits is performed and normal operation is possible. error detection/correction is active. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-47 v1.1, 2011-03 pcp, v2.08 data array mapping, no error detection/correction no mapping of the ecc bits is performed. writes to the memory will not affect the ecc bits. error correction/detection for the memory is disabled. normal operation (with the exception that ecc protection is not operational) is possible. check array mapping, no error detection/correction the ecc bit array (only) of the memory is made visible in the address map (i.e. the memory data array cannot be accessed). writes to the memo ry will not af fect the data bits. error correction/detection for the memory is disabled. the pcp must be disabled before, and remain disabled while, this mode is selected for any of the pcp memories. when this mode is selected the memory ecc bit array replaces the memory data array in the address map. during a read the value of the ecc bits for a location can be determined from bits 6 to 0 of the value read from the location (all other bits read as ?0?). during a write the ecc bits are updated from bits 6 to 0 of the written value. the written value of all bits other than bits 6 to 0 is discarded. data array mapping, error detection/correction enabled. no mapping of the ecc bits is performed and normal operation is possible. note: unlike tricore the pcp has no hidden memory arrays (i.e. all pcp memories reside permanently in the system address map). as a result, for the pcp, this mode is identical to ?normal operation?. this mode is retained for compatibility with tricore sist. 11.11 memory integrity error detection and correction the pcp includes support for memory integrity error detection and correction logic to address the increasing occurrence of me mory errors in deep sub-micron cmos technologies. soft errors are transient errors in state (not permanent) typically caused by alpha particle hits to the die, causing indu ced charge which flips the state of storage elements. in current process geometries sram arrays are most suscept ible to soft error events due to their small size and low stored charge. the detection and deterministic recovery from such memory integrity errors is especia lly important for automotive applications, such as electronic braking systems and engine management. the pcp includes the following sram arrays: ? code memory (cmem) ? parameter memory (pram) each of these memory arrays will be protected from memory integrity errors, with the specific mechanisms described in the following sections. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-48 v1.1, 2011-03 pcp, v2.08 note: before enabling error detection/correc tion on an sram (i.e. cmem or pram) the user must ensure that all locations within the sram have been initialised. if this is not done then unwanted spurious me mory errors can be generated. 11.11.1 definitions in the following sections memory integrity errors are considered to be either correctable or un-correctable. these are defined as follows:- un-correctable memo ry integrity error if on accessing a memory element containing a memory integrity error hardware is not able to provide the expected data to the core, the integrity error is defined as being un- correctable. correctable memory integrity error if on accessing a memory element containing a memory integrity error hardware is able to provide the expected data to the core, the integrity error is defined as being correctable. 11.11.2 architectural extensions - registers a number of additional special function registers (sfrs) have been added to the pcp in order to fully support memory integrity error handling. the function of these registers is explained below while the specific register information is detailed in section 11.15 . 11.11.3 memory integrity error control the miecon register controls whether memory errors generate a notification to the scu or not. miecon may only be written in supervisor mode and is endinit protected. two status registers (miestatp for pram and miestatc for cmem) are provided to allow software to easily identify locations that have generated memory error events. the xxiee bits and the appropriate smacon field settings interact to control the update of these registers. errors are reported and the miestatx regist ers are updated only when data read from the memory is actually being utilized (i.e. th e memory is either being read via fpi or by the core). in the event of error detection being enabled, a pram (double word) location containing an error in both word lanes and the pcp performing a double word read (only during a context restore) the miestatp register will be updated as though the error was in the lower word of pram. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-49 v1.1, 2011-03 pcp, v2.08 11.12 instruction set overview the following sections present an overview of the instruction set and the available addressing modes of the pcp in the TC1798. 11.12.1 dma primitives table 11-3 describes the two dma instructions of the pcp. table 11-4 dma transfer instructions dma transfer bcopy move block of data value from fpi bus source address location to fpi bus destination address location. optionally increment or decrement source and destination pointer registers. optionally repeat instruction until counter cnt1 reaches 0. copy move value from fpi bus sour ce address location to fpi bus destination address location. optionally increment or decrement source and destination pointer registers. optionally repeat instruction until counter cnt1 reaches 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-50 v1.1, 2011-03 pcp, v2.08 11.12.2 load and store table 11-4 describes the load and store instructions of the pcp. note: if a conditional instruction?s condition code is false, the operation will be treated as a ?no operation?. register values will not be changed and the flags will not be updated. table 11-5 load and store instructions load ld.f load value from fpi bus address location into register (fpi bus address = register content) ld.i load immediate value into register ld.if load value from fpi bus address location into register (fpi bus address = register content + immediate offset) ld.p load value from pram address location into register (pram address = dptr + register offset) ld.pi load value from pram address location into register (pram address = dptr + immediate offset) ldl.il load 16-bit immediate value into lower bits [15:0] of register ldl.iu load 16-bit immediate value into upper bits [31:16] of register store st.f store register value to fpi bus address location (fpi bus address = register content) st.if store register value to fpi bus address location (fpi bus address = register content + immediate offset) st.p store register value to pram address location (pram address = dptr + register offset) st.pi store register value to pram address location (pram address = dptr + immediate offset) move mov conditionally move register value to register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-51 v1.1, 2011-03 pcp, v2.08 11.12.3 arithmetic an d logical instructions arithmetic instructions that are fully register-based execute conditionally depending on the specified condition code a (see page 11-99 ). all other arithmetic instructions such as pram (.pi), indirect (.i), and fpi (.f and .if) execute unconditionally. note: if a conditional instruction?s condition code is false, the operation will be treated as a ?no operation?. register values will not be changed and the flags will not be updated. logical instructions that are fully registe r-based execute conditionally as determined by the specified condition code a. all other logical instructions, such as pram (.pi), indirect (.i), and fpi (.f and .if) execute unconditionally. table 11-6 arithmetic instructions add add add register to register (conditionally) add.i add immediate value to register add.f add content of fpi bus address location to register (byte, half-word or word) add.pi add content of pram address location to register subtract sub subtract register from register (conditionally) sub.i subtract immediate value from register sub.f subtract content of fpi bus address location from register (byte, half-word or word) sub.pi subtract content of pram address location from register compare comp compare register to register (conditionally) comp.i compare immediate value to register comp.f compare content of fpi bus address location to register (byte, half-word or word) comp.pi compare content of pram address location to register negate neg negate register (2?s complement, conditionally) table 11-7 logical instructions logical and and register and register (conditionally) and.f content of fpi bus address location and register (byte, half-word or word) and.pi content of pram address location and register mclr.pi clear specified bits within a pram location www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-52 v1.1, 2011-03 pcp, v2.08 note: if a conditional instruction?s condition code is false, the operation will be treated as a ?no operation?. register values will not be changed and the flags will not be updated. logical or or register or register (conditionally) or.f content of fpi bus address location or register (byte, half-word or word) or.pi content of pram address location or register mset.pi set specified bits within a pram location logical exclusive- or xor register xor register (conditionally) xor.f content of fpi bus address location xor register (byte, half-word or word) xor.pi content of pram address location xor register logical not not invert register (1?s complement, conditionally) shift shl shift left register shr shift right register rotate rl rotate left register rr rotate right register prioritize pri calculate position of first set bit (1-bit) in register, from left table 11-7 logical instructions (cont?d) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-53 v1.1, 2011-03 pcp, v2.08 11.12.4 bit manipulation all bit manipulation instructions except in b are executed unconditionally. if conditional bit handling is required, inb should be used. 11.12.5 flow control table 11-8 describes flow control instructions of the pcp in the TC1798. table 11-8 bit manipulation instructions set bit set set bit in register set.f set bit in fpi bus address location clear bit clr clear bit in register clr.f clear bit in fpi bus address location insert bit inb insert carry flag into register (position given by content of a register) inb.i insert carry flag into register (position given by immediate value) check bit chkb set carry flag depending on value of specified register bit table 11-9 flow control instructions jump jc jump conditionally to pc + short immediate offset address jc.a jump conditionally to immediate absolute address jc.i jump conditionally to pc + register offset address jc.ia jump conditionally to register absolute address jl jump unconditionally to pc + long immediate offset address exit channel exit unconditionally exit channel program execution (optionally generate interrupt request and/or inhibit channel) no operation nop low-power no-operation debug debug conditionally generate debug event (optionally stop channel program execution) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-54 v1.1, 2011-03 pcp, v2.08 11.12.6 addressing modes the pcp needs to address locations in memory in different ways, as determined by the type of memory being accessed and the type of action being performed on that location. 11.12.6.1 fpi bus addressing all fpi bus accesses from the pcp are indirect to some extent. the main indirect addressing on the fpi bus uses a 32-bit absolute address located in the gpr indicated in the instruction. this address must be properly aligned for the type of data access ? byte, half-word or word. if it is not aligned, the results are undefined. ? effective target address [31:0] = TC1798 peripheral control processor (pcp) users manual 11-55 v1.1, 2011-03 pcp, v2.08 11.12.6.2 pram addressing the pram is always addressed indirectly by the pcp. the normal address used is the value of the r7.dptr field (8 bits) concatenated with an immediate 6-bit offset value encoded in the instruction, yielding a 14-bit word address. this enables access to 16 kwords (64 kbytes). because r7.dptr is part of a channel program?s context, a channel program may alter the dptr value at any time. ? effective pram address[13:0] = TC1798 peripheral control processor (pcp) users manual 11-56 v1.1, 2011-03 pcp, v2.08 ? effective jump address[15:0] = nextpc + sign-extend(#offset6); +/- 32 instructions the function nextpc indicates the instruction that would be fetched next by the program counter. instructions using this addressing are jl, jc and jc.i. for absolute addressing, the actual address in cmem where program flow is to resume is either an immediate value #imm16 in the cmem location immediately following the jump instruction, or it is contained in the lower 16 bits of a register. if the value is greater than the pc size implemented, an error condition has occurred. ? effective jump address[15:0] = #imm16 ? effective jump ad dress[15:0] = TC1798 peripheral control processor (pcp) users manual 11-57 v1.1, 2011-03 pcp, v2.08 11.13 fpi interface any fpi bus master (on the TC1798?s system peripheral bus) can access the three distinct pcp address ranges from the fpi bus side, on the other hand the pcp master interface can also access any address on the fpi bus. normally, the cpu initializes the control registers via fpi bus access. thereafter, the pcp should not access its control registers itself through pcp instructions. apart from the access via fpi bus, there is no direct way to the pc p control registers. accesses to the pcp control and status register, the pram, and the cmem are detailed in the following sections. 11.13.1 access to the pcp control registers from the fpi bus fpi bus accesses to the pcp control registers must always be performed in supervisor mode with word accesses; byte or half-word accesses will result in a bus error. all pcp control registers can be read at any time. register pcp_cs can be optionally endinit-protected via bit pcp_cs.eie (see page 11-69 ). if cs.eie & endinit = true, then any write access to this register is inhibited. the clock control register pcp_clc is endinit-protected. the software in-system test register is also endinit-protected. additionally (see below) for high integrity appl ications the entire register content can be endinit protected (see below). 11.13.1.1 pcp control register protection to allow the pcp to handle system critical tasks it is nece ssary to ensure that the pcp can operate properly rega rdless of a failure in another part of the system or the pcp itself. this means that it is necessary to protect the control and status registers from such failures. the configuration register content can only be modified via the fpi. protection of the pcp configuration therefore consists of prevention of unwanted fpi writes to the pcp registers. the normal model of pcp operation is that the pcp is configured at system initialization and the configuration remains unchanged fo r the duration of oper ation of the system. protection therefore consists of a simple lock ing scheme to prevent any write to registers once the pcp has been configured. once the pcp has been configured (at system initialization) the registers can be locked such that, unless endinit is clear, all incoming fpi write accesses are issued with an error response and the pcp configuration will remain unmodified. if is required to modify content of the registers once they have been locked it is necessary to clear the endi nit bit (via the system watchdog timer) such that the registers become writeable again. regardless of protection the entire register content remains readable via fpi. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-58 v1.1, 2011-03 pcp, v2.08 this function is controlled by the rprot register ( ?register protection register, pcp_rprot? on page 11-85 ). 11.13.2 access to the pram from the fpi bus fpi bus accesses to the pram must always be performed with word accesses; byte or half-word accesses will re sult in a bus error. attention needs to be paid when accessing the csas and data sections of the pcp channel programs. the location of a specific channel?s csa is dependent on the chosen context model, full, small or minimum context. table 11-10 shows these addresses. note: since channel 0 is not defined (no service request with srpn = 0), the first area is not an actual csa. it is recommended th at this area should not be used by pcp channel programs. the fpi bus address of a word location pointed to by the data pointer r7_dptr is calculated by the following formula: ? effective fpi bus address[31:0] = (pram base address) + ( TC1798 peripheral control processor (pcp) users manual 11-59 v1.1, 2011-03 pcp, v2.08 the fpi bus address of an instruction pointed to by the pcp program counter, pc, is calculated by the following formula: ? effective fpi bus address[31:0] = (cmem base address) + TC1798 peripheral control processor (pcp) users manual 11-60 v1.1, 2011-03 pcp, v2.08 11.14 debugging the pcp for debugging the pcp, a special instruction, debug, is provided. this instruction can only be used when the pcp is in debug mode. it can be placed at important locations inside the code to track and trace program ex ecution. the execution of the instruction depends on a condition code specified with the instruction. the actions programmed for this instruction will only take place if the specified condition is true. the following actions are performed when the debug instruction is executed and the condition code is true: ? store the current pc, i.e. the address of the debug instruction, in register pcp_es.epc ? store the current channel number in register pcp_es.epn in addition, the following operations can be programmed through fields in the debug instruction: ? optionally stop the channel program execution (instruction field sdb) ? optionally generate an external debug event at pin brkout (instruction field eda) ? optionally prevent the pcp from executing any further channel programs (instruction field dac) ? optionally cause the pcp to decrement the pc prior to saving the channel context (instruction field rta) if the debug instruction is programmed to stop the channel program execution, the action taken by the pcp depends on the value of the rta instruction field: ? if rta = 0, the pcp disables further invocations of the current channel through clearing bit r7.cen, and then performs a c ontext save. the execution of this channel is stopped at the point of the debug instruction. if the dac instruction field = 0, the pcp will continue to operate, accepting service requests for other channels as they arise. since the stopped channel was disabled before saving its context, service requests for this channel will result in an error exit (see page 11-32 ). when re- enabling the channel, its enable bit cen in the saved context location cr7 must be set. ? if rta = 1, the pcp does not modify bit r7.cen (i.e. the channel remains enabled), decrements the pc (so that it again points to the debug instruction), and then performs a context save. the execution of this channel is stopped at the point of the debug instruction. if the dac instruction field = 0, the pcp will continue to operate, accepting service requests for channels as they arise. since the stopped channel was not disabled before saving its context, service requests for this channel will not result in an error exit, but will simply cause re-execution of the debug instruction and hence a repeat of the channel exit. note: when a channel is stopped by debug, the context of th e stopped channel will be saved to the appropriate region of the csa before the channel terminates. where a small or minimum context model is being used, the values of the gprs not www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-61 v1.1, 2011-03 pcp, v2.08 included in the context will not be saved, and indeed these register values may be changed by the operation of another acti ve channel. in this case, the required registers should be explicitly saved to pram by store instructions prior to execution of the debug instruction. if the debug instruction is programmed to stop all channel program execution, the pcp disables further invocations of any channel by clearing bit pcp_cs.en. the execution of this channel is only stopped according to the sdb instruction field value. the pcp will only start to reaccept service requests when pcp_cs.en is written to 1. note: the debug instruction must be only used in debug mode; otherwise it will generate an iop error. note: if pcp_cs.rcb = 0 (channel resume mode), then the channel program will begin executing at whichever pc is rest ored from the context location cr7.pc. if pcp_cs.rcb = 1 (channel restart mode), t hen the channel program is forced to always start at its channel entry table locati on, no matter what the restored context value is for the pc. this means that in channel restart mode, it is not possible to restart the channel program from where it was halted by the debug event. it is recommended that when using channel restart mode, the user should also program all exit instructions with the ?ep = 0? setting to allow selection of channel resume mode for debugging without changing operation of the channel programs. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-62 v1.1, 2011-03 pcp, v2.08 11.15 pcp registers the pcp can be viewed as being a peripheral on the fpi bus. as with any other peripheral, there are control registers, normally set by the cpu acting as an external fpi bus master to the pcp during initialization. control registers select the operating modes of the pcp, and status registers provide information about the current state of the pcp to the external fpi bus master. accessing of control registers the control registers are accessible by any ma ster via the fpi bus. the control registers must be configured at initialization and then left unaltered. this is typically done by the cpu. the only setting that can be dynamically modified is the pcp_cs.en bit. all other bits must only be modified when pcp_cs.en = 0 and pcp_cs.rs = 0. the pcp control and status registers are accessible only to the cpu when it is operating in supervisor mode. pcp control and status registers must be accessed with 32-bit read and write operations only. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-63 v1.1, 2011-03 pcp, v2.08 figure 11-13 pcp registers pcp register overview the address map of the pcp starts at its base address as shown in table 11-19 . the address offsets of the pcp registers are described in table 11-11 . table 11-11 register overview of pcp short name description offset addr. 1) access mode reset description see read write pcp_clc clock control register 00 h u, sv, 32 sv, 32, e fpi reset page 11-67 pcp_id module identification register 08 h u, sv, 32 sv, 32 2) fpi reset page 11-68 mca06150 pcp_rprot pcp_cprot pcp_pprot pcp_clc pcp_cs pcp_src0 control registers interrupt registers pcp_src1 pcp_src2 pcp_es pcp_icr pcp_src3 pcp_itr pcp_icon pcp_ssr pcp_src4 pcp_src5 pcp_src6 pcp_src7 pcp_src8 pcp_src9 pcp_src10 pcp_src11 pcp_smacon pcp_miecon pcp_miestatp pcp_miestatc pcp_fwwin www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-64 v1.1, 2011-03 pcp, v2.08 pcp_cs control/status register 10 h u, sv, 32 sv, 32, e 3) fpi reset page 11-69 pcp_es error/debug status register 14 h u, sv, 32 sv, 32 2) fpi reset page 11-71 pcp_icr interru pt control register 20 h u, sv, 32 sv, 32 fpi reset page 11-74 pcp_itr interrupt threshold control register 24 h u, sv, 32 sv, 32 fpi reset page 11-76 pcp_icon interrupt configuration register 28 h u, sv, 32 sv, 32 2) fpi reset page 11-77 pcp_ssr stall status register 2c h u, sv, 32 sv, 32 2) fpi reset page 11-79 pcp_smacon sist mode access control register 40 h u, sv, 32 sv, 32 fpi reset page 11-81 pcp_miecon memory integrity error control register 50 h u, sv, 32 sv, e, 32 fpi reset page 11-82 pcp_miestat p memory integrity error status for pram register 58 h u, sv, 32 sv, 32 fpi reset page 11-83 pcp_miestat c memory integrity error status for cmem register 5c h u, sv, 32 sv, 32 fpi reset page 11-84 pcp_rprot register protection register 70 h u, sv, 32 sv, e, 32 fpi reset page 11-85 pcp_cprot cmem protection register 74 h u, sv, 32 sv, e, 32 fpi reset page 11-86 pcp_pprot pram protection register 78 h u, sv, 32 sv, e, 32 fpi reset page 11-87 pcp_fwwin fpi write window register 7c h u, sv, 32 sv, e, 32 fpi reset page 11-91 table 11-11 register overview of pcp (cont?d) short name description offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-65 v1.1, 2011-03 pcp, v2.08 pcp_src11 service request control register 11 d0 h u, sv, 32 sv, 32 2) fpi reset page 11-96 pcp_src10 service request control register 10 d4 h u, sv, 32 sv, 32 2) fpi reset page 11-96 pcp_src9 service request control register 9 d8 h u, sv, 32 sv, 32 2) fpi reset page 11-96 pcp_src8 service request control register 8 dc h u, sv, 32 sv, 32 fpi reset page 11-95 pcp_src7 service request control register 7 e0 h u, sv, 32 sv, 32 fpi reset page 11-95 pcp_src6 service request control register 6 e4 h u, sv, 32 sv, 32 fpi reset page 11-95 pcp_src5 service request control register 5 e8 h u, sv, 32 sv, 32 fpi reset page 11-95 pcp_src4 service request control register 4 ec h u, sv, 32 sv, 32 fpi reset page 11-95 pcp_src3 service request control register 3 f0 h u, sv, 32 sv, 32 2) fpi reset page 11-94 pcp_src2 service request control register 2 f4 h u, sv, 32 sv, 32 2) fpi reset page 11-94 pcp_src1 service request control register 1 f8 h u, sv, 32 sv, 32 2) fpi reset page 11-92 pcp_src0 service request control register 0 fc h u, sv, 32 sv, 32 2) fpi reset page 11-92 1) the absolute register address is calculated as follows: module base address + offset address (shown in this column) 2) a write access is allowed to this register (i.e. no bus error is generated) but as there are no writable bits the register value is unaffected by the write. 3) endinit protection is controlled by the eie bit. table 11-11 register overview of pcp (cont?d) short name description offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-66 v1.1, 2011-03 pcp, v2.08 11.16 pcp registers address space table 11-12 registers address space module base address end address note pcp f004 3f00 h f004 3fff h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-67 v1.1, 2011-03 pcp, v2.08 11.17 registers 11.17.1 pcp clock control register, pcp_clc pcp_clc pcp clock control register (00 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 pcg dis res rw r field bits type description res [31:16] r reserved read as 0; should be written with 0. pcgdis 15 rw clock gating disable bit allows clock gating to be disabled. 0 b pcp internal clock stops when pcp is idle (default after reset) 1 b pcp internal clock always runs res [14:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-68 v1.1, 2011-03 pcp, v2.08 11.17.2 pcp module identi fication register, pcp_id pcp_id pcp module identification register (08 h ) reset value: 0020 c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 modnum r 1514131211109876543210 id32bit revnum rr field bits type description modnum [31:16] r pcp identification number value = 0020 h id32bit [15:8] r 32-bit module identifi cation number marker value = c0 h revnum [7:0] r pcp revision number implementation specific value = 08 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-69 v1.1, 2011-03 pcp, v2.08 11.17.3 pcp control and status register, pcp_cs this register can be endinit-protected via bit eie. pcp_cs pcp control/status register (10 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 esr cwt cwe rw rw rw 1514131211109876543210 pps ppe cs eie rcb res rs res en rw rw rw rw rw r rh r rw field bits type description esr [31:24] rw error service request number srpn for interrupt to cp u on an error condition. 00 h no interrupt request posted (default) 01 h post an srpn interrupt to cpu on an error condition 10 h post an srpn interrupt to cpu on an error condition cwt [23:17] rw channel watchdog threshold 0 d reserved 1 d threshold = 16 instructions ... b ... 127 d from 1 d up to 127 d (n), the threshold = 16 ?n? instructions cwe 16 rw channel watchdog enable 0 b disable channel watchdog 1 b enable channel watchdog note: when enabled, the channel watchdog counts the number of instructio ns executed since the channel started. if th is number exceeds the channel watchdog threshold, a pcp error is generated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-70 v1.1, 2011-03 pcp, v2.08 pps [15:9] rw pram partition size 0 d default, only allowed with ppe = 0 1 d csa contains 3 context save regions ... b ... 127 d csa contains 1 + 2 127 context save regions note: the actual size of the csa (in words) is given by the formula (2 n+1) m, where m is the number of registers in the selected context model. if ppe = 1 and the pcp attempts to perform a data write to pram addresses below the csa, an error condition has occurred. this setting also controls the maximum channel number (mcn) used in system. the maximum channel number is mcn = 2 n. if the srpn is greater than mcn, an error condition has occurred. for example, setting pps to n = 3 will give a csa containing 7 context save regions. as channel 0 cannot be used and mcn = 6, channels 1 to 6 are allowed. ppe 8rw pram partitioning enable 0 b pram is not partitioned 1 b pram is partitioned note: when partitioned, the pram is divided into two areas (csa and remainder). a pcp error will be generated on an inappropriate action in either region (pcp write operation with a target address in the csa, or context restore from outside the csa). cs [7:6] rw context size selection 00 b use full context for all channels 01 b use small context for all channels 10 b use minimum context for all channels 11 b reserved eie 5rw endinit enable 0 b pcp_cs is not endinit protected. 1 b pcp_cs is endinit protected. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-71 v1.1, 2011-03 pcp, v2.08 11.17.4 pcp error/debug status register, pcp_es this is a read-only register, providing stat e information about error and debug conditions. rcb 4rw channel start mode control 0 b channel resume operation mode selected; channel start pc is taken from restored context 1 b channel restart operation mode selected; channel start pc is derived from the requested channel number (= priority number of service request) note: this is a global control bit and applies to all channels. res 3r reserved read as 0; should be written with 0. rs 2rh pcp run/stop status flag 0 b pcp is stopped or idle (default) 1 b pcp is currently running res 1r reserved read as 0; should be written with 0. en 0rw pcp enable 0 b pcp is disabled for operation (default) 1 b pcp is enabled for operation note: this bit does not enable/disable clocks for power saving. it stops the pcp from accepting new service requests. pcp_es pcp error/debug status register (14 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 epc rh 1514131211109876543210 epn ppc cwd me dbe iae dcr iop ber rh rh rh rh rh rh rh rh rh field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-72 v1.1, 2011-03 pcp, v2.08 field bits type description epc [31:16] rh error pc pc value of the instruction that was executing when an error or debug event occurred. default = 0000 h . epn [15:8] rh error service reques t priority number channel number of the channel that was operating when the last error/debug event occurred. the value stored is the srpn which invoked this channel (= channel number), not the current pcp priority number stored in field cppn in register picr. default = 00 h . ppc 7rh pram partitioning check set if the last error/debug event was an error generated by a channel program attempting to perform a write to a pram address within the csa, or receipt of an interrupt request that would have caused a context restore from outside the csa. cwd 6rh channel watchdog triggered set if the last error/debug event was an error generated by a channel program attempting to execute more instructions than allowed by pcp_cs.cwt. me 5rh memory error this bit is set if a pcp internal memory error has occurred. see table 11.22 ?implementation of the pcp in the TC1798? on page 11-157 for TC1798 specific implementation. dbe 4rh debug event flag set if the last error/debug event was a debug event. note: a debug event does not cause the posting of an interrupt to the cpu. iae 3rh instruction address error set if the last error/debug event was an error generated by the pcp attempting to fetch an instruction from an address outside the implemented cmem range as a result of a jump or branch instruction; otherwise, clear. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-73 v1.1, 2011-03 pcp, v2.08 note: an interrupt request with the srpn hel d in pcp_cs.esr is posted to the cpu whenever a pcp error event, other than an fpi bus error occurs. fpi bus error interrupt generation is automatically handl ed by the fpi bus control logic, rather than by the pcp. the execution of a debug instruction is not classed as an error event and does not therefore generate an in terrupt request to the cpu. the entire contents of the register are updated whenever there is a debug or an error event detected (i.e. all status/error bits, other than the bit representing the last pcp error/debug event, are cleared). this regi ster therefore only provides a record of the last error/debug event encountered. the only way to clear this register is to reset the pcp. 11.17.5 pcp interrupt c ontrol register, pcp_icr this register controls the operation of the pcp interrupt control unit (picu). dcr 2rh disabled channel request flag set if the last error/debug event was an error generated by receipt of an interrupt request with an srpn that attempted to start a disabled pcp channel; otherwise, clear. iop 1rh invalid opcode set if the last error/debug event was an error generated by the pcp attempting to execute an invalid opcode (i.e. the value fetched from cmem for execution by the pcp did not represent a valid instruction), otherwise clear. ber 0rh bus error flag set if the last error/debug event was an error generated by an fpi bus error or an invalid address access; otherwise, clear. note: an fpi bus error event does not cause the pcp to post an error interrupt to the cpu. an fpi bus error interrupt is, however, generated by the fpi control logic. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-74 v1.1, 2011-03 pcp, v2.08 pcp_icr pcp interrupt control register (20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res p one cyc parbcyc pipn rrwrw rh 1514131211109876543210 res ie cppn rrh rh field bits type description res [31:27] r reserved read as 0; should be written with 0. ponecyc 26 rw clocks per arbitration cycle control this bit determines the number of clocks per arbitration cycle. 0 b two clocks per arbitration cycle (default) 1 b one clock per arbitration cycle parbcyc [25:24] rw number of arbitration cycles control this bit field controls the number of arbitration cycles used to determine the request with the highest priority. it follows the same coding scheme as described for the cpu interrupt arbitration. 00 b four arbitration cycles (default) 01 b three arbitration cycles 10 b two arbitration cycles 11 b one arbitration cycle pipn [23:16] rh pending interrupt priority number this read-only field is updated by the picu at the end of each arbitration process, and indicates the priority number of a pending request. pipn is set to 00 h when no request is pending and at the beginning of a new arbitration process. res [15:9] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-75 v1.1, 2011-03 pcp, v2.08 ie 8rh reserved cppn [7:0] rh current pcp priority number this field indicates the current priority level of the pcp and is automatically updated by hardware on entry into an interrupt service routine. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-76 v1.1, 2011-03 pcp, v2.08 11.17.6 pcp interrupt threshold register, pcp_itr pcp_itr pcp interrupt threshold control register (24 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res itl rrw 1514131211109876543210 res itp rrw field bits type description res [31:20] r reserved read as 0; should be written with 0. itl [19:16] rw interrupt threshold level this bit field specifies the number of active interrupt entries at which an warning interrupt should be issued to the interrupt queue associated with interrupt bus 0 (i.e. when the number of active port 0 interrupt requests stored in all srcx registers reaches this value then an interrupt is posted to port 0 with the priority programmed into the itp field). when itl is programmed to 0 or is the number of srcx registers that can contain port 0 interrupt requests, the threshold warning mechanism is disabled). res [15:8] r reserved read as 0; should be written with 0. itp [7:0] rw pcp interrupt threshold service request priority number this field contains the interrupt priority that is to be posted to the interrupt queue associated with interrupt bus 0 when the threshold condition is reached (setting this value to 0 or disables the threshold detection mechanism). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-77 v1.1, 2011-03 pcp, v2.08 11.17.7 pcp interrupt configuration register, pcp_icon pcp_icon pcp interrupt configuration register (28 h ) reset value: 0000 03e4 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res ip3e = 0 ip2e = 0 ip1e = 1 ip0e = 1 p3t =11b p2t = 10b p1t =01b p0t = 00b r rrrr r r r r field bits type description res [31:12] r reserved read as 0. ip3e 11 r pcp interrupt bus 3 enable this bit reflects the status of interrupt bus 3. interrupt bus 3 is always disabled (not implemented in the TC1798). ip2e 10 r pcp interrupt bus 2 enable this bit reflects the status of interrupt bus 2. interrupt bus 2 is always disabled (not implemented in the TC1798). ip1e 9r pcp interrupt bus 1 enable this bit reflects the status of interrupt bus 1 (pcp interrupt arbitration bus). interrupt bus 1 is always enabled. ip0e 8r pcp interrupt bus 0 enable this bit reflects the status of interrupt bus 0 (cpu interrupt arbitration bus). interrupt bus 0 is always enabled. p3t [7:6] r pcp interrupt bu s 3 tos mapping this field reflects the tos associated with interrupt bus 3. note: interrupt bus 3 is not available in the TC1798. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-78 v1.1, 2011-03 pcp, v2.08 p2t [5:4] r pcp interrupt bu s 2 tos mapping this field reflects the tos associated with interrupt bus 2. note: interrupt bus 2 is not available in the TC1798. p1t [3:2] r pcp interrupt bu s 1 tos mapping this field reflects the tos associated with interrupt bus 1 (pcp interrupt arbitration bus). the pcp should use this value in r6.tos when it wishes to raise an interrupt request to itself (the pcp is always connected to interrupt bus 1). p0t [1:0] r pcp interrupt bu s 0 tos mapping this field reflects the tos associated with interrupt bus 0 (cpu interrupt arbitration bus). the pcp should use this value in r6.tos when it wishes to raise an interrupt request via interrupt bus 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-79 v1.1, 2011-03 pcp, v2.08 11.17.8 pcp stall status register, pcp_ssr pcp_ssr pcp stall status register (2c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res schn rrh 1514131211109876543210 st res stos ssrn rh r rh rh field bits type description res [31:24] r reserved read as 0. schn [23:16] rh pcp stalled channel number this field shows the channel number of the channel that was executing when the last (or present) stall condition occurred. this field can only be cleared by a reset. st 15 rh pcp stalled status this bit shows the stalled status of the pcp 0 b pcp is not stalled 1 b pcp is stalled res [14:10] r reserved read as 0. stos [9:8] rh pcp stalled type-of-service this field shows the type-of-service to which an interrupt was being posted that caused the last (or present) stall condition (i.e. the service request queue that was full when the pcp attempted to post a request to it). this field can only be cleared by a reset. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-80 v1.1, 2011-03 pcp, v2.08 ssrn [7:0] rh pcp stalled service request number this field shows the service request number that was being posted when the last (or present) stall condition occurred. this field can only be cleared by a reset. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-81 v1.1, 2011-03 pcp, v2.08 11.17.9 sist mode access control register, pcp_smacon note: please see section 11.10 on page 11-46 for more information regarding the use of this register. this register is endinit protected. pcp_smacon sist mode access control register (40 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res cmem pram rrwrw field bits type description res [31:4] r reserved returns ?0? if read; should be written with ?0?. cmem [3:2] rw cmem sist mode access control 00 b normal operation, no mapping 01 b data array mapping, no error detection/correction 10 b check array mapping, no error detection/correction 11 b data array mapping, error detection/correction enabled pram [1:0] rw pram sist mode access control 00 b normal operation, no mapping 01 b data array mapping, no error detection/correction 10 b check array mapping, no error detection/correction 11 b data array mapping, error detection/correction enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-82 v1.1, 2011-03 pcp, v2.08 11.17.10 memory integrity erro r control register, pcp_miecon note: please see section 11.11 on page 11-47 for more information regarding the use of this register. this register is endinit protected. pcp_miecon sist mode access control register (50 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res ciee piee rrwrw field bits type description res [31:2] r reserved returns ?0? if read; should be written with ?0?. ciee 1rw cmem integrity error enable enables the integrity error handling for cmem. piee 0rw pram integrity error enable enables the integrity error handling for pram. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-83 v1.1, 2011-03 pcp, v2.08 11.17.11 memory integrity error status register for pram, pcp_miestatp note: please see section 11.11 on page 11-47 for more information regarding the use of this register. pcp_miestatp memory integrity error stat us register for pram(58 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 err clr rq res rw r 1514131211109876543210 res addr rr field bits type description err 31 r pram memory integrity error flag set when a memory integrity error is encountered . this bit remains set until the clrrq bit is written with ?1? or the pcp is reset. clrrq 30 w clear status request bit when written with ?1? this causes all other bits within the register to be cleared. res [29:14] r reserved returns ?0? if read; should be written with ?0?. addr [13:0] r pram error address the (word) address of the pram location containing an error which caused the err bit to transition from ?0? to ?1?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-84 v1.1, 2011-03 pcp, v2.08 11.17.12 memory integrity error status register for cmem, pcp_miestatc note: please see section 11.11 on page 11-47 for more information regarding the use of this register. pcp_miestatc memory integrity error stat us register for cmem(5c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 err clr rq res rw r 1514131211109876543210 res addr rr field bits type description err 31 r cmem memory inte grity error flag set when a memory integrity error is encountered. this bit remains set until the clrrq bit is written with ?1? or the pcp is reset. clrrq 30 w clear status request bit when written with ?1? this causes all other bits within the register to be cleared. res [29:15] r reserved returns ?0? if read; should be written with ?0?. addr [14:0] r cmem error address the (word) address of the cmem location containing an error which caused the err bit to transition from ?0? to ?1?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-85 v1.1, 2011-03 pcp, v2.08 11.17.13 register protecti on register, pcp_rprot this register is endinit protected. pcp_rprot register protection register (70 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 en res rw r 1514131211109876543210 res r field bits type description en 31 rw register protection enable 0 b registers are not protected and can be written at any time. 1 b registers are protected and can only be written when endint is ?0?. res [30:0] r reserved returns ?0? if read; should be written with ?0?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-86 v1.1, 2011-03 pcp, v2.08 11.17.14 cmem protection register, pcp_cprot note: please see section 11.13.3 on page 11-58 for more informat ion regarding the use of this register. this register is endinit protected. pcp_cprot cmem protection register (74 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 en res rw r 1514131211109876543210 res r field bits type description en 31 rw register protection enable 0 b cmem is not protected and can be written at any time. 1 b cmem is protected and can not be written. res [30:0] r reserved returns ?0? if read; should be written with ?0?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-87 v1.1, 2011-03 pcp, v2.08 11.17.15 pram protecti on register, pcp_pprot this register is endinit protected. pcp_pprot pram protection register (78 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 en eni res pca t pthres rw rw r rw rw 1514131211109876543210 psize fbase rw rw field bits type description en 31 rw pram protection enable for fpi writes 0 b pram is not protected and can be written via fpi at any time. 1 b all pram outside the open window is protected and can not be written via fpi. pram inside the open window remains writable via fpi. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-88 v1.1, 2011-03 pcp, v2.08 eni 30 rw pram protection enable for internal writes 0 b the entire pram (subject to pram partitioning) is not protected and can be written using pcp pram write instructions. 1 b all pram outside the protected window (and subject to pram partitioning) is not protected and can be written using pcp pram write instructions. pram inside the protected window remains writable using pcp pram write instructions only by a protected channel (subject to pram partitioning). note: pram partitioning (which is enabled/controlled by cs.ppe and cs.pps) takes precedence over pram protection. therefore if pram partitioning is enabled, the entire context region will be protected against pcp pram write instructions, regardless of the protection settings or whether the channel is protected or not. res [29:25] r reserved returns ?0? if read. should be written with ?0?. pcat 24 rw protected channels above threshold when eni (above) is ?0?, this bit has no effect. when eni is ?1?, this bit defines whether the channel number defined in the pthres represents the lowest of the highest protected channel; 0 b the channel with the number defined by pprot.pthres is the highest channel program that is treated as protected. all channel?s with numbers below the value of pprot.pthres are also treated as protected. 1 b the channel with the number defined by pprot.pthres is the lowest channel program that is treated as protected. all channel?s with numbers above the value of pprot.pthres are also treated as protected. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-89 v1.1, 2011-03 pcp, v2.08 pthres [23:16] rw protected channel threshold when pprot.eni is ?0?, this field has no effect. when pprot.eni is ?1?, this field defines the channel number which is used to distinguish between protected and non-protected channels. psize [15:8] rw pram internally protected window size when pprot.eni is ?0?, this field has no effect. when pprot.eni is ?1?, this field defines the size (in multiples of 256 bytes) of the region at the bottom of pram that can only be written (using pram write instructions) by protected channels. note: each value n, from 1 d , up to the maximum 255 d ,is multiplied by 256 bytes 0 d 0 bytes (i.e. there is no protected window; the entire pram (subject to pram partitioning) can be written by the use of pram write instructions by any channel). 1 d 256 bytes (i.e. the lowest 64 words of pram are protected against pram write instructions executed by non-protected channels). .... b ... 255 d 255 * 256 bytes note: use of an eight bit field allows for the maximum pram size currently supported by the architecture (64kbytes). where a pcp is implemented with a smaller pram, setting a protected window size greater than the actual pram size will result in the entire pram being protected against pram write instructions executed by non-protected channels. note: when enabled, the pram partitioning protection scheme (enabled via cs.ppe and cs.ppe) takes precedence and will protect the context save region from modification by pram write instructions (regardless of whether an instruction was executed by a protected channel or not). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-90 v1.1, 2011-03 pcp, v2.08 fbase [7:0] rw pram fpi open window base when pprot.en is ?0?, this field has no effect. when pprot.en is '1' (see above) this field defines the base address (in multiples of 256 bytes and relative to the base of pram) of the region at the top of pram that remains writable by fpi writes. note: from 1 d up to 254 d : base of pram + n * 256 bytes 0 d base of pram (i.e. the entire pram can be written by fpi writes). 1 d base of pram + 256 bytes (i.e. all but the lowest 64 words of pram can be written via the fpi bus, the lowest 64 words of pram are protected against fpi writes) ... b ... 254 d base of pram + 254 * 256 bytes. 255 d the entire pram is protected against fpi writes. note: use of an eight bit field allows for the maximum pram size currently supported by the architecture (64kbytes). where a pcp is implemented with a smaller pram, setting an open window base above the actual top of pram will result in the entire pram being protected against fpi writes. note: there is a small limitation with this scheme in that if a device is implemented with a 64k pram then it will not be possible to protect the entire pram (the top 64 words cannot be protected in this case). if this is a problem then bit 29 could be used as a ?protect entire pram bit). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-91 v1.1, 2011-03 pcp, v2.08 11.17.16 fpi write window register, pcp_fwwin note: please see section 11.8.1 on page 11-42 for more information regarding the use of this register. this register is endinit protected. pcp_fwwin fpi write window register (7c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 en ex res size base rw rw r rw rw 1514131211109876543210 base rw field bits type description en 31 rw fpi protection enable 0 b the addresses of outgoing fpi writes are not checked. 1 b during execution of an instruction that generates an fpi write, a check is performed that the target address within the programmed allowed address range. if the address not to an allowed address then an fpi write is not issued and the pcp exits the current channel with iop error. ex 30 rw window mode 0 b limit mode. the destination address of fpi write instructions must lie within the defined window. 1 b exclude mode. the destination address of fpi write instructions must lie outside the defined window. res 29 r reserved returns ?0? if read. should be written with ?0?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-92 v1.1, 2011-03 pcp, v2.08 11.17.17 pcp service request control registers m, pcp_src[1:0] service request nodes for interrupt bu s 0 (cpu interrupt arbitration bus). size [28:24] rw window size the fpi window size (binary sizing) 0 d 256 bytes 1 d 512 bytes ... b ... 31 d 2 (n+8) bytes base [23:0] rw window base address controls the base address of the fpi window (binary aligned according to the window size. bit 23 maps to the bit 31 of the fpi byte address. the appropriate number of subsequent bits defines the aligned address according to the window size (e.g. when using a 1kbyte window, the lower 2 bits of this field are treated as zero, regardless of their actual value, in order to obtain the base address of the window). pcp_srcm (m = 0-1) pcp service request control register m (fc h -m*4 h ) reset value: 0000 1000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res srr sre = 1 tos = 00 b res srpn rrhr r r rh field bits type description res [31:14] r reserved read as 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-93 v1.1, 2011-03 pcp, v2.08 srr 13 rh pcp node m service request flag 0 b no service requested (default). 1 b valid active service requested. sre 12 r pcp node m service request enable always read as 1 (enabled). tos [11:10] r pcp node m type-of-service state always read as 00 b . this means tos is associated with interrupt bus 0 (cpu interrupt arbitration bus). res [9:8] r reserved read as 0. srpn [7:0] rh pcp node m service request priority number this number is automatically set by the pcp if it needs to place a service request on interrupt bus 0 (cpu interrupt arbitration bus). default after reset is 00 h . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-94 v1.1, 2011-03 pcp, v2.08 11.17.18 pcp service request control registers m, pcp_src[3:2] service request nodes for interrupt bus 1 (pcp interrupt arbitration bus). pcp_srcm (m = 2-3) pcp service request control register m (fc h -m*4 h ) reset value: 0000 1400 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res srr sre = 1 tos = 01b res srpn rrhr r r rh field bits type description res [31:14] r reserved read as 0. srr 13 rh pcp node m service request flag 0 b no service requested (default). 1 b valid active service requested. sre 12 r pcp node m service request enable always read as 1 (enabled). tos [11:10] r pcp node m type-of-service state always read as 01 b . this means tos is associated with interrupt bus 1 (pcp interrupt arbitration bus). res [9:8] r reserved read as 0. srpn [7:0] rh pcp node m service request priority number this number is automatically set by the pcp if it needs to place a service request on interrupt bus 1 (pcp interrupt arbitration bus). default after reset is 00 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-95 v1.1, 2011-03 pcp, v2.08 11.17.19 pcp service request control registers m, pcp_src[8:4] service request nodes programmable for interrupt bus 0 (cpu interrupt arbitration bus) or 1 (pcp interrupt arbitration bus). pcp_srcm (m = 4-8) pcp service request control register m (fc h -m*4 h ) reset value: 0000 1000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res srr sre = 1 tos res srpn rrhrrw r rh field bits type description res [31:14] r reserved read as 0. should be written with 0. srr 13 rh pcp node m service request flag 0 b no service requested (default). 1 b valid active service requested. sre 12 r pcp node m service request enable always read as 1 (enabled). tos [11:10] rw pcp node m type-of-service state/control tos value depends on the interrupt mapping that has been selected (see page 11-151 ). this bit field must be written at pcp configuration time and should not subsequently modified while the pcp is operating. res [9:8] r reserved read as 0. should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-96 v1.1, 2011-03 pcp, v2.08 11.17.20 pcp service request control registers m, pcp_src[11:9] service request nodes for interrupt bus 1 (pcp interrupt arbitration bus) with suspended interrupt capability. srpn [7:0] rh pcp node m service request priority number this number is automatically set by the pcp if it needs to place a service request on interrupt bus 0 (cpu interrupt arbitration bus) or 1 (pcp interrupt arbitration bus). default after reset is 00 h . pcp_srcm (m = 9-11) pcp service request control register m (fc h -m*4 h ) reset value: 0000 1400 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res rrq res srcn rrh r rh 1514131211109876543210 res srr sre = 1 tos = 01b res srpn rrhr r r rh field bits type description res [31:29] r reserved read as 0. rrq 28 rh pcp node m channel restart request set when this service requ est register n contains an active service request that is associated with a suspended interrupt (i.e. a channel that has been interrupted by a higher-priority channel). 0 b the interrupt is not suspended 1 b the interrupt is suspended rrq is always 0 when srr is 0. res [27:24] r reserved read as 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-97 v1.1, 2011-03 pcp, v2.08 srcn [23:16] rh pcp node m service re quest channel number channel number entry (default = 0). when the pcp interrupt request was raised by the pcp processor core when executing an exit instruction, then this bit field contains the srpn value taken from r6 when the exit instruction was executed. when the pcp interrupt request was raised by the pcp processor core when suspending execution of a channel program in order to service a higher-priority interrupt then this bit field contains the channel number of the channel that was suspended. res [15:14] r reserved read as 0. srr 13 rh pcp node m service request flag 0 b no service requested (default) 1 b valid active service requested sre 12 r pcp node m service request enable always read as 1 (enabled). tos [11:10] r pcp node m type-of-service state always read as 01 b . this means tos is associated with interrupt bus 1 (pcp interrupt arbitration bus). res [9:8] r reserved read as 0. srpn [7:0] rh pcp node m service request priority number this number is automatically set by the pcp if it needs to place a service request on interrupt bus 0 (cpu interrupt arbitration bus) or 1 (pcp interrupt arbitration bus). when the pcp interrupt request contained was raised by the pcp processor core when executing an exit instruction then this bit field contains the srpn value taken from r6 when the exit instruction was executed. when the pcp interrupt request was raised by the pcp processor core when suspending execution of a channel program in order to service a higher-priority interrupt then this bit field contains the cppn value of the pcp when the interrupt was suspended. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-98 v1.1, 2011-03 pcp, v2.08 11.18 pcp instruction set details this section describes the instruction set architecture of the pcp in detail. 11.18.1 instruction codes and fields all pcp instructions use a common set of fields to describe such things as the source register, and the state of flags. additionally, many instructions (including arithmetic and many flow control instructions), are conditionally executed. the descriptions of the pcp instructions are based on the following conventions. >>, << shift left or right, respectively. [ ] indirect access based on contents of brackets (de-reference). #immnn immediate value encoded into an instruction with width nn. #offsetnn address offset immediate value with width nn. nextpc the current executing instruction?s address + 1. (the next instruction to be fetched.) cc_a, cc_b condition code condca/condcb. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-99 v1.1, 2011-03 pcp, v2.08 11.18.1.1 conditional codes many pcp instructions have the option of being executed conditionally. the condition code of an instruction is the field that specifies the condition to be tested before the instruction is executed. depending on the type of instruction there are 8 or 16 condition codes available. the set of 8-condition codes is referred to as condca, while the set of 16-condition codes is referred to as condcb. the condition codes are based on an equation of the flags held in r7. see table 11-13 . table 11-13 condition codes description condca/b test (flag bits) code mnemonic unconditional a / b ? 0 h cc_uc zero/equal a / b z = 1 1 h cc_z not zero/not equal a / b z = 0 2 h cc_nz overflow a / b v = 1 3 h cc_v carry/unsigned less than/ check bit true a / b c = 1 4 h cc_c, cc_ult unsigned greater than a / b c or z = 0 5 h cc_ugt signed less than a / b n xor v = 1 6 h cc_slt signed greater than a / b (n xor v) or z = 0 7 h cc_sgt negative b n = 1 8 h cc_n not negative b n = 0 9 h cc_nn not overflow b v = 0 a h cc_nv no carry/unsigned greater than or equal bc = 0 b h cc_nc, cc_uge signed greater than or equal b n xor v = 0 c h cc_sge signed less than or equal b (n xor v) or z = 1 d h cc_sle cnt1 equal zero b cnz1 = 1 e h cc_cnz cnt1 not equal zero b cnz1 = 0 f h cc_cnn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-100 v1.1, 2011-03 pcp, v2.08 11.18.1.2 instr uction fields table 11-14 lists the instruction field definitions of the pcp instruction set architecture. note: the exact syntax for these fields may be different depending on which tool (e.g. assembler) is used. please refer to the respective tool descriptions. table 11-14 instruction field definitions symbol syntax description cc_a, cc_b see table 11-13 condition code specifies conditional execution of instruction according to condca or condcb. cnc cnc = 00 b cnc = 01 b cnc = 10 b cnc = 11 b counter control this field is used by the bcopy/copy instructions to control the number of repetitions of the data transfer. for bcopy operation see figure 11 - 2 on page 11-104 . for copy operation see figure 11 - 1 on page 11-103 . perform the number of transfers specified by cnt0 then proceed to next instruction. perform the number of transfers specified by cnt0 then decrement cnt1 and proceed to next instruction. perform the number of transfers specified by cnt0 then decrement cnt1. repeat until cnt1 = 0, then proceed to next instruction. reserved. cnt0 cnt0 = 001 b ..111 b cnt0 = 000 b cnt0 = 00 b cnt0 = 10 b cnt0 = 11 b others counter reload value (copy) the copy instruction uses an implicit counter to generate multiple data transfers. the cnt0 value given in the instruction specifies how many data transfer s are to be performed by the instruction. see also figure 11 - 1 on page 11-103 . perform 1..7 data transfers perform 8 data transfers block size (bcopy) selects the fpi block size used for a bcopy instruction. use block size of 8 words. use block size of 2 words. use block size of 4 words. reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-101 v1.1, 2011-03 pcp, v2.08 dac dac = 0 dac = 1 stop pcp allow the pcp to continue to execute channel programs in response to service requests. prevent the pcp from executin g further channel programs (pcp_cs.en = 0). dst+- dst (00 b ) dst+ (01 b ) dst- (10 b ) (11 b ) destination address pointer control no change (dst) post increment by size (dst+) post decrement by size (dst-) reserved ec ec = 0 ec = 1 exit count control no action decrement cnt1 eda eda = 0 eda = 1 external debug action no external debug action caused cause an external debug action (breakpoint pin etc.) ep ep = 0 ep = 1 entry point control set the pc to channel program start. ep = 0 assumes that a channel entry table exists in the base of cmem. failure to provide such a table will cause improper operation. set the pc to the address contained in nextpc (next instruction) address. int int = 0 int = 1 interrupt control no interrupt int = 1 and (cc_b = true) means issue interrupt rta rta = 0 rta = 1 action on debug exit stop channel program from accepting new service requests (clear r7.cen) allow further channel program execution and decrement pc (so that debug instruction is re-executed on next invocation) note: this field has no effect if sdb = 0 (see below) s/c s/c = 0 s/c = 1 test bit control check for clear (0) check for set (1) sdb sdb = 0 sdb = 1 stop on debug continue running if debug event triggered stop pcp if debug event triggered table 11-14 instruction field definitions (cont?d) symbol syntax description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-102 v1.1, 2011-03 pcp, v2.08 size size = 00 b size = 01 b size = 10 b size = 11 b data size control byte (8-bit) half-word (16-bit) word (32-bit) reserved src+- src (00 b ) src+ (01 b ) src- (10 b ) (11 b ) source address pointer control no change (src) post increment by size (src+) post decrement by size (src-) reserved st st = 0 st = 1 stop channel continue channel execution, leave channel program enabled stop channel execution, perform actions according to rta setting (see above) table 11-14 instruction field definitions (cont?d) symbol syntax description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-103 v1.1, 2011-03 pcp, v2.08 11.18.2 counter operation for copy instruction figure 11 - 1 shows the flow of a copy instruction. figure 11 - 1 counter operation for copy instruction mca06147 data transfer copy instruction t_count = 0 ? next instruction t_count := cnt0 t_count := t_count - 1 cnc = ? cnt1 := cnt1 - 1 cnt1 := cnt1 - 1 cnt1 = 0 ? no yes 00 10 01 yes no www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-104 v1.1, 2011-03 pcp, v2.08 11.18.3 counter operation for bcopy instruction figure 11 - 2 shows the flow of a bcopy instruction. figure 11 - 2 counter operation for bcopy instruction mca06148 data transfer (block size determined by cnt0 field) bcopy instruction next instruction cnc = ? cnt1 := cnt1 - 1 cnt1 := cnt1 - 1 cnt1 = 0 ? 00 10 01 yes no www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-105 v1.1, 2011-03 pcp, v2.08 11.18.4 divide and multiply instructions the pcp has multiply and divide capabilities (unsigned values only). all multiply and divide instructions operate on 8 bits of data (taken from the dividend for divide, from the multiplicand for multiply). this strategy allows the user to implement the appropriate number of instructions (?steps?) as required for the user?s data format. each execution of a divide instruction (dstep) performs a division which generates 8 bits of result, and also manipulates the registers being used to allow the execution of consecutive divide (dstep) instructions to build divide algorithms in multiples of 8 bits (see page 11-154 for more details). each execution of a multiply instruction (mstep32 and mstep64) performs a multiplication on 8 bits of data (taken from the multiplicand) and also manipulates the registers to allow execution of consecutive multiply instructions to build multiply algorithms in multiples of 8 bits (see page 11-155 for more details). the following restrictions apply to the use of divide and multiply instructions: ? the first instruction of any divide sequence must be the dinit (initialization) instruction. any additional instructions other than minit, mstep32 or mstep64 may also be used within the sequence as long as they do not modify any of the registers used for division (r0, ra and rb). all subsequent divide instructions within the sequence (dstep) must use the same register for dividend and the same register for divisor as used in the preceding dinit instruction. ? the first instruction of any multiply sequence must be the minit (initialization) instruction. any additional instructions other than dinit or dstep may also be used within the sequence as long as they do not modify any of the registers used for multiplication (r0, ra and rb). all subsequent multiply instructions within the sequence (mstep32 and mstep64) must us e the same register for multiplicand and the same register for multiplier as used in the preceding minit instruction. ? neither of the operand registers (ra or rb) may be r0 (which is used implicitly within all the instructions), and the same register may not be supplied as both operand registers of an instruction (e.g. dstep r3, r3 is invalid). note: failure to adhere to these restrictions will yield undefined results. 2. special care must be taken when using multiply and divide sequences when a channel program is interruptible. in this case it must be ensured that a sequence cannot be corrupted by the execution of mult iply or divide instructions executed by a higher-priority channel. the r7.ien bit ca n be used to ensure that a sequence is not interruptible (see page 11-153 ). in the descriptions attached to each multiply and divide instruction, a pseudo-code model is supplied to provide an unambiguous definition of the function of the instruction. the models supplied for the dstep and mstep32 instructions use 32 bit unsigned integer arithmetic, ignoring any possible overflows. the model supplied for the mstep64 uses www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-106 v1.1, 2011-03 pcp, v2.08 a 40-bit unsigned multiply and then shifts this result right by 8 bits (discards the least significant 8 bits of the 40-bit result). the dstep instruction also has some conditions stipulated regarding input values to the instruction. use of the pseudo-code model for the dstep instruction with invalid input values will yield an invalid result. 11.18.5 add, 32-bit addition this section describes the a dd instructions of the pcp. add syntax add rb, ra, cc_a description if the condition condca is true, then add the contents of register ra to the contents of register rb; place the result in rb. if condca is false, no operation is performed. operation if (condca = true) then r[b] = r[b] + r[a] else nop flags n, z, v, c add.i syntax add.i ra, #imm6 description add the zero-extended immediate value imm6 to the contents of register ra; place the result in ra. operation r[a] = r[a] + zero_ext(imm6) flags n, z, v, c add.f syntax add.f rb, [ra], size description add the contents of the address location specified by the contents of register ra to the contents of register rb; place the result in rb. note: byte and half-word values are zero-extended. operation r[b] = r[b] + zero_ext(fpi[r[a]]) flags n, z, v, c add.pi syntax add.pi ra, [#offset6] description add the contents of the pram location specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value offset6 to the contents of register ra; place the result in ra. operation r[a] = r[a] + pram[(dptr<<6) + zero_ext(#offset6)] flags n, z, v, c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-107 v1.1, 2011-03 pcp, v2.08 11.18.6 and, 32-bit logical and this section describes the a nd instructions of the pcp. and syntax and rb, ra, cc_a description if the condition condca is true, then perform a bit-wise logical and of the contents of register ra and the contents of register rb; place the result in rb. if condca is false, no operation is performed. operation if (condca = true) then r[b] = r[b] and r[a] else nop flags n, z and.f syntax and.f rb, [ra], size description perform a bit-wise logical and of the contents of the address location, specified by the contents of register ra, and the contents of register rb; place the result in rb. operation r[b] = r[b] and zero_ext(fpi[r[a]]) flags n, z and.pi syntax and.pi ra, [#offset6] description perform a bit-wise logical and of the contents of the pram location specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value offset6, and the contents of register ra; place the result in ra. operation r[a] = r[a] and pram[(dptr<<6) + zero_ext(#offset6)] flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-108 v1.1, 2011-03 pcp, v2.08 11.18.7 bcopy, dma operation this section describes the bcopy instruction of the pcp in the TC1798. see also page 11-157 for TC1798 specific details of the bcopy instruction. bcopy syntax bcopy dst+-, src+-, cnc, cnt0 description allows the pcp to perform dma type transfers using fpi block transfers. moves the contents of fpi bus source location to fpi bus destination location. source location is pointed to by the contents of register r4; destination location is pointed to by the contents of register r5. options (see also table 11-14 at page 11-100 ): source pointer (src+-): in crement, decrement or unchanged destination pointer (src+-): increment, decrement or unchanged counter control (cnc): see table 11-14 block size value (cnt0): see table 11-14 operation temp = zero_ext(fpi[r[4]]); value loaded and extended depending on size fpi(r[5]) = temp r4 = r4 +/- n; n depending on src+- and cnt0 r5 = r5 +/- n; n depending on dst+- and cnt0 for counter operation see figure 11 - 2 on page 11-104 and table 11-14 on page 11-100 . flags cn1z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-109 v1.1, 2011-03 pcp, v2.08 11.18.8 chkb, check bit this section describes the chkb instruction of the pcp. 11.18.9 clr, clear bit this section describes the clr instructions of the pcp. chkb syntax chkb ra, #imm5, s/c description if bit imm5 of register ra is equal to the specified test value s/c then set the carry flag r7.c, else clear the carry flag. operation if (r[a][imm5] = s/c) then r7_c = 1 else r7_c = 0 flags c clr syntax clr ra, #imm5 description clear bit imm5 of register ra to 0. operation r[a][imm5] = 0 flags none clr.f syntax clr.f [ra], #imm5, size description clear bit imm5 of the address location specified through the contents of register ra to 0. this instruction is executed using a locked read-modify-write fpi bus transaction. operation fpi[(r[a])][imm5] = 0 flags none www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-110 v1.1, 2011-03 pcp, v2.08 11.18.10 comp, 32-bit compare this section describes the comp instructions of the pcp. comp syntax comp rb, ra, cc_a description if the condition condca is true, then subtract the contents of register ra from the contents of register rb; set the flags in register r7 according to the result of the subtraction; discard the subtraction result. if condca is false, no operation is performed. operation if (condca = true) then r7_flags = flags(r[b] - r[a]) flags n, z, v, c comp.i syntax comp.i ra, #imm6 description subtract the immediate value imm6 from the contents of register ra; set the flags in register r7 according to the result of the subtraction; discard the subtraction result. operation r7_flags = flags(r[a] - zero_ext(imm6)) flags n, z, v, c comp.f syntax comp.f rb, [ra], size description subtract the contents of the address location specified by the contents of register ra from t he contents of register rb; set the flags in register r7 according to the result of the subtraction; discard t he subtraction result. operation r7_flags = flags(r[b] - zero_ext(fpi[r[a]])) flags n, z, v, c comp.pi syntax comp.pi ra, [#offset6] description subtract the contents of the pram location specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value offset6, from the contents of register ra; set the flags in register r7 according to the result of the subtraction; discard the subtraction result. operation r7_flags = flags(r[a] - pram[(dptr<<6) + zero_ext(#offset6)]) flags n, z, v, c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-111 v1.1, 2011-03 pcp, v2.08 11.18.11 copy, dma instruction this section describes the comp instruction of the pcp. copy syntax copy dst+-, src+-, cnc, cnt0, size description moves the contents of fpi bus source location to fpi bus destination location. source location is pointed to by the contents of register r4; destination location is pointed to by the contents of register r5. options (see also table 11-14 on page 11-100 ): source pointer (src+-): increment, decrement or unchanged destination pointer (src+-): increment, decrement or unchanged counter control (cnc): see table 11-14 counter 0 reload value (cnt0): see table 11-14 data transfer width (size): byte, half-word, word (pointers are incremented/decremented based upon size). operation temp = zero_ext(fpi[r[4]]); value loaded and extended depending on size fpi(r[5]) = temp r4 = r4 +/- n; n depending on src+- and size r5 = r5 +/- n; n depending on dst+- and size for counter operation see figure 11 - 1 on page 11-103 and table 11-14 on page 11-100 . flags cn1z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-112 v1.1, 2011-03 pcp, v2.08 11.18.12 debug, debug instruction this section describes the debug instruction of the pcp. note: execution of the debug command when not in debug mode will cause the pcp to generate an ?illegal operation? error exit. debug syntax debug eda, dac, rta, sdb, cc_b description conditionally cause a debug event if condition condcb is true. optionally stop channel execution (sdb = 1) and/or generate an external debug event (eda = 1). operation if (condcb = true) then if (eda = 1) then activate brk_out pin if (sdb = 1) then if (rta = 0) then r7_cen = 0; disable further channel invocation else pc = pc - 1 endif save_context idle endif if (dac = 1) pcp_cs>en = 0 endif set es.dbe; indicate debug event es.pc = nextpc es.pn = channel_number endif flags none www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-113 v1.1, 2011-03 pcp, v2.08 11.18.13 dinit, divi de initialization this section describes the dinit instruction of the pcp. dinit syntax dinit TC1798 peripheral control processor (pcp) users manual 11-114 v1.1, 2011-03 pcp, v2.08 11.18.14 dstep, divide instruction this section describes the dstep instruction of the pcp. note: the value in ra must always be greater than the value in r0 prior to execution of the dstep instruction. if the rules specified on page 11-105 are followed, then the above description and operation are co rrect. failure to adhere to these rules will yield undefined results. dstep syntax dstep TC1798 peripheral control processor (pcp) users manual 11-115 v1.1, 2011-03 pcp, v2.08 11.18.15 exit, exit instruction this section describes the exit instruction of the pcp. exit syntax exit ec, st, int, ep, cc_b description unconditionally exit channel program execution. optionally decrement counter cnt1 (ec = 1), disable further channel invocation (st = 1), generate an interrupt request (int = 1) if condition condcb is true. field ep is used to set the channel code entry point in channel resume mode to either the address of the next instruction (ep = 1) or to the start address of the channel (ep = 0). the exit instruction is finished with a context save operation. the ep option is only in effect when channel resume operation is globally selected through pcp_cs.rcb = 0. if pcp_cs.rcb = 1, channel restart mode is selected for all channels, and the ep field of the exit instruction is disregarded. operation if (ec = 1) then cnt1 = cnt1 - 1 if (st = 1) then r7_cen = 0 if ((int = 1) and (cc_b = true)) then activate_interrupt_request if (ep = 1) then r7_pc = nextpc else r7_pc = channel_entry_point save_context flags cn1z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-116 v1.1, 2011-03 pcp, v2.08 11.18.16 inb, insert bit this section describes the inb instructions of the pcp. inb syntax inb rb, ra, cc_a description if condca is true, then insert the carry flag r7.c into register rb at the bit position specified through bits [4..0] of register ra. if condca is false, no operation is performed. operation if (condca = true) then r[b][r[a][4:0]] = r7_c else nop flags none inb.i syntax inb.i ra, #imm5 description insert the carry flag r7.c into register ra at the bit position specified through the immediate value imm5. operation r[a][imm5] = r7_c flags none www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-117 v1.1, 2011-03 pcp, v2.08 11.18.17 jc, jump conditionally this section describes the conditio nal jump instructions of the pcp. jc syntax jc offset6, cc_b description if condcb is true, then add the sign-extended value specified by offset6 to the contents of the pc, and jump to that address. if condcb is false, no operation is performed. operation if (condcb = true) then (pc = pc + sign_ext(offset6)) else nop flags none jc.a syntax jc.a #address16, cc_b description if condcb is true, then load the value specified by address16 into the pc, and jump to that address. if condcb is false, no operation is performed. operation if (condcb = true) then (pc = address16) else nop flags none jc.i syntax jc.i ra, cc_b description if condcb is true, then add the value specified by ra[15:0] to the contents of the pc, and jump to that address. value ra[15:0] is treated as a signed 16-bit number. if condcb is false, no operation is performed. operation if (condcb = true) then (pc = pc + (r[a][15:0])) else nop flags none jc.ia syntax jc.ia ra, cc_b description if condcb is true, then load the value specified by ra[15:0] into the pc, and jump to that address. value ra[15:0] is treated as an unsigned 16-bit number. if condcb is false, no operation is performed. operation if (condcb = true) then (pc = (r[a][15:0])) else nop flags none www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-118 v1.1, 2011-03 pcp, v2.08 11.18.18 jl, jump long unconditional this section describes the long jump instruction jl of the pcp. 11.18.19 ld, load this section describes the ld instructions of the pcp. jl syntax jl offset10 description add the sign-extended value specified by offset10 to the contents of the pc, and jump to that address. operation pc = pc + sign_ext(offset10) flags none ld.f syntax ld.f rb, [ra], size description load the zero-extended contents of the address location specified by the contents of register ra into register rb. operation r[b] = zero_ext(fpi[r[a]]) flags n, z ld.i syntax ld.i ra, #imm6 description load the zero-extended value specified by imm6 into register ra. operation r[a] = zero_ext(imm6) flags n, z ld.if syntax ld.if [ra], #offset5, size description load the zero-extended contents of the address location, specified by the addition of the contents of register ra and the value specified by imm5, into register r0. operation r[0] = zero_ext(fpi[r[a] + zero_ext(imm5)]) flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-119 v1.1, 2011-03 pcp, v2.08 ld.p syntax ld.p rb, [ra], cc_a description if condition condca is true, then load the contents of the pram address location, specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value ra[5:0] into register rb. if condition condca is false, no operation is performed. operation if (condca = true) then r[b] = pram[(dptr<<6) + zero_ext(r[a][5:0])] else nop flags n, z ld.pi syntax ld.pi ra, [#offset6] description load the contents of the pram location specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value offset6 into register ra. operation r[a] = pram[(dptr<<6) + zero_ext(offset6)] flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-120 v1.1, 2011-03 pcp, v2.08 11.18.20 ldl, load 16-bit value this section describes the ldl instructions of the pcp. 11.18.21 minit, multiply initialization this section describes the minit instruction of the pcp. ldl.il syntax ldl.il ra, #imm16 description load the immediate value imm16 into the lower bits of register ra (bits [15:0]). bits [31:16] of register ra are unaffected. value imm16 is treated as an unsigned 16-bit number. operation r[a][15:0] = imm16 flags n, z ldl.iu syntax ldl.iu ra, #imm16 description load the immediate value imm16 into the upper bits of register ra (bits [31:16]). bits [15:0] of register ra are unaffected. operation r[a][31:16] = imm16 flags n, z minit syntax minit TC1798 peripheral control processor (pcp) users manual 11-121 v1.1, 2011-03 pcp, v2.08 11.18.22 mov, move register to register this section describes the mov instruction of the pcp. mov syntax mov rb, ra, cc_a description if condition condca is true, then move the contents of register ra into register rb. if condca is false, no operation is performed. operation if (condca = true) then r[b] = r[a] else nop flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-122 v1.1, 2011-03 pcp, v2.08 11.18.23 multiply instructions this section describes the multiply instructions of the pcp. note: in the case of the mstep64 instructio n above, the ?temp? variable is a 40-bit variable and all calculations are perfor med using 40-bit unsigned arithmetic. all other calculations use 32 -bit unsigned arithmetic. mstep32 syntax mstep32 TC1798 peripheral control processor (pcp) users manual 11-123 v1.1, 2011-03 pcp, v2.08 11.18.24 neg, negate this section describes the neg instruction of the pcp. 11.18.25 nop, no operation this section describes the nop instruction of the pcp. 11.18.26 not, logical not this section describes the not instruction of the pcp. neg syntax neg rb, ra, cc_a description if condition condca is true, then move the 2?s complement of the contents of register ra into register rb. if condca is false, no operation is performed. operation if (condca = true) then r[b] = (- r[a]) else nop flags n, z, v, c nop syntax nop description no operation. the nop instruction puts the pcp in low- power operation. operation no operation flags none not syntax not rb, ra, cc_a description if condition condca is true, then move the 1?s complement of the contents of register ra into register rb. if condca is false, no operation is performed. operation if (condca = true) then r[b] = not(r[a]) else nop flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-124 v1.1, 2011-03 pcp, v2.08 11.18.27 or, logical or this section describes the or instructions of the pcp. or syntax or rb, ra, cc_a description if the condition condca is true, then perform a bit-wise logical or of the contents of register ra and the contents of register rb; place the result in rb. if condca is false, no operation is performed. operation if (condca = true) then r[b] = r[b] or r[a] else nop flags n, z or.f syntax or.f rb, [ra], size description perform a bit-wise logical or of the contents of the address location, specified by the contents of register ra, and the contents of register rb; place the result in rb. operation r[b] = r[b] or zero_ext(fpi[r[a]]) flags n, z or.pi syntax or.pi ra, [#offset6] description perform a bit-wise logical or of the contents of the pram location specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value offset6, and the contents of register ra; place the result in ra. operation r[a] = r[a] or pram[(dptr<<6) + zero_ext(#offset6)] flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-125 v1.1, 2011-03 pcp, v2.08 11.18.28 pram bit operations this section describes the mclr and mset instructions of the pcp. note: mclr and mset are read/modify/writ e operations that cannot be interrupted by an access from another fpi master. they can be used to implement semaphore systems. mclr syntax mclr.pi ra, [#offset6] description perform an ?and? of the contents of the specified register with the contents of the pram location specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value offset. write the result back to the pram location. operation r[a] = r[a].and.pram[dptr<<6 + #offset6] pram[dptr<<6 + #offset6] = r[a] flags n, z mset syntax mset.pi ra, [#offset6] description perform an ?or? of the cont ents of the specified register with the contents of the pram location specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value offset. write the result back to the pram location. operation r[a] = r[a].or.pram[dptr<<6 + #offset6] pram[dptr<<6 + #offset6] = r[a] flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-126 v1.1, 2011-03 pcp, v2.08 11.18.29 pri, prioritize this section describes the pri instruction of the pcp. prid syntax pri rb, ra, cc_a description if condition condca is true, then find the bit position of the most significant 1 in register ra and put the number into register rb. the bit location, 31-0, is encoded as a 5-bit number stored in rb[4:0]. if the contents of ra is zero, bit rb[5] is set, while all other bits in rb are cleared. if condca is false, no operation is performed. operation if (condca = false) then nop else if (r[a] = 0) then r[b] = 0x20 else r[b] = bit_pos(most_significant_1(r[a])) flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-127 v1.1, 2011-03 pcp, v2.08 11.18.30 rl, rotate left this section describes the rl instruction of the pcp. 11.18.31 rr, rotate right this section describes the rr instruction of the pcp. rl syntax rl ra, #imm5 description rotate the contents of register ra to the left by the number of bit positions specified through the 5-bit value imm5. the values defined for imm5 are 1, 2, 4 and 8. the carry flag, r7.c, is set to the last bit shifted out of bit 31 of register ra. operation tmp = r[a] r[a] = r[a] << imm5; imm5 = 1, 2, 4, 8 r7_c = last bit shifted out of r[a] tmp = tmp >> 32 - imm5 r[a] = tmp or r[a] flags n, z rr syntax rr ra, #imm5 description rotate the contents of register ra to the right by the number of bit positions specified through the 5-bit value imm5. the values allowed for imm5 are 1, 2, 4 and 8. operation tmp = r[a] r[a] = r[a] >> imm5; imm5 = 1, 2, 4, 8 tmp = tmp << 32 - imm5 r[a] = tmp or r[a] flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-128 v1.1, 2011-03 pcp, v2.08 11.18.32 set, set bit this section describes the set bit instruction of the pcp. 11.18.33 shl, shift left this section describes the shl instruction of the pcp. set syntax set ra, #imm5 description set bit imm5 of register ra to 1. operation r[a][imm5] = 1 flags none set.f syntax set.f [ra], #imm5, size description set bit imm5 of the address location specified through the contents of register ra to 1. this instruction is executed using a locked read-modify-write fpi bus transaction. operation fpi[(r[a])][imm5] = 1 flags none shl syntax shl ra, #imm5 description shift the contents of register ra to the left by the number of bit positions specified through the 5-bit value imm5. the values allowed for imm5 are 1, 2, 4 and 8. the carry flag, r7.c, is set to the last bit shifted out of bit 31 of register ra. zeros are shifted in from right. operation r[a] = r[a] << imm5; imm5 = 1, 2, 4, 8 r7_c = last bit shifted out of r[a] flags n, z, c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-129 v1.1, 2011-03 pcp, v2.08 11.18.34 shr, shift right this section describes the shr instruction of the pcp. shr syntax shr ra, #imm5 description shift the contents of register ra to the right by the number of bit positions specified through the 5-bit value imm5. the values allowed for imm5 are 1, 2, 4 and 8. zeros are shifted in from left. operation r[a] = r[a] >> imm5; imm5 = 1, 2, 4, 8 flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-130 v1.1, 2011-03 pcp, v2.08 11.18.35 st, store this section describes the st instructions of the pcp. st.f syntax st.f rb, [ra], size description store the contents of register rb to the address location specified by the contents of register ra. when the size is byte or half-word, the data is stored with the internal lsb (bit 0) properly aligned to the correct fpi bus byte or half-word lane. operation fpi[r[a]] = r[b] flags none st.if syntax st.if [ra], #offset5, size description store the contents of r0 to the address location specified by the addition of the contents of register ra and the value specified by imm5. when the size is byte or half-word, the data is stored with the internal lsb (bit 0) properly aligned to the correct fpi bus byte or half-word lane. operation fpi[r[a] + zero_ext(imm5)] = r[0] flags none st.p syntax st.p rb, [ra], cc_a description if condition condca is true, then store the contents of rb to the pram address location specified by the addition of the contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value ra[5:0]. if condition condca is false, no operation is performed. operation if (condca = true) then pram[(dptr<<6) + zero_ext(r[a][5:0])] = r[b] else nop flags none st.pi syntax st.pi rb, [#offset6] description store the contents of register rb to the pram location specified by the addition of the contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value offset6. operation pram[(dptr<<6) + zero_ext(offset6)] = r[b] flags none www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-131 v1.1, 2011-03 pcp, v2.08 11.18.36 sub, 32-bit subtract this section describes the sub instructions of the pcp. sub syntax sub rb, ra, cc_a description if the condition condca is true, then subtract the contents of register ra from the contents of register rb; place the result in rb. if condca is false, no operation is performed. operation if (condca = true) then r[b] = r[b] - r[a] else nop flags n, z, v, c sub.i syntax sub.i ra, #imm6 description subtract the zero-extended immediate value imm6 from the contents of register ra; place the result in ra. operation r[a] = r[a] - zero_ext(imm6) flags n, z, v, c sub.f syntax sub.f rb, [ra], size description subtract the zero-extended contents of the address location specified by the contents of register ra from the contents of register rb; place the result in rb. operation r[b] = r[b] - zero_ext(fpi[r[a]]) flags n, z, v, c sub.pi syntax sub.pi ra, [#offset6] description subtract the contents of the pram location specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero-extended 6-bit value offset6 from the contents of register ra; place the result in ra. operation r[a] = r[a] - pram[(dptr<<6) + zero_ext(#offset6)] flags n, z, v, c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-132 v1.1, 2011-03 pcp, v2.08 11.18.37 xch, exchange this section describes the x ch instructions of the pcp. xch.f syntax xch.f rb, [ra], size description exchange contents of r[b] and fpi[r[a]] when size is byte or half-word, the value is stored with the internal lsb (bit 0) properly aligned to the correct fpi byte or half-word lane. the exchange is done via a locked fpi bus transfer. operation temp = r[b] r[b] = zero_ext(fpi[r[a]]) fpi[r[a]] = temp flags n, z xch.pi syntax xch.pi ra, [#offset6] description exchange contents of r[a] and pram[dptr <<6 + #offset6]. note: the exchange is un-i nterruptible, and locks out external accesses; it will not be interrupted by any external fpi bus master transfer requests. operation temp = r[a] r[a] = pram[(dptr<<6) + zero_ext(#offset6)] pram[(dptr<<6) + zero_ext(#offset6)] = temp flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-133 v1.1, 2011-03 pcp, v2.08 11.18.38 xor, 32-bit logical exclusive or this section describes the xor instructions of the pcp. xor syntax xor rb, ra, cc_a description if the condition condca is true, then perform a bit-wise logical exclusive-or of the contents of register ra and the contents of register rb; place the result in rb. if condca is false, no operation is performed. operation if (condca = true) then r[b] = r[b] xor r[a] else nop flags n, z xor.f syntax xor.f rb, [ra], size description perform a bit-wise logical exclusive-or of the contents of the address location, specified by the contents of register ra, and the contents of register rb; place the result in rb. operation r[b] = r[b] xor zero_ext(fpi[r[a]]) flags n, z xor.pi syntax xor.pi ra, [#offset6] description perform a bit-wise logical exclusive-or of the contents of the pram location specified by the addition of contents of the pram data pointer, shifted left by six bits, and the zero- extended 6-bit value offset6, and the contents of register ra; place the result in ra. operation r[a] = r[a] xor pram[(dptr<<6) + zero_ext(#offset6)] flags n, z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-134 v1.1, 2011-03 pcp, v2.08 11.18.39 flag updates of instructions most instructions update the state flags in r7. in table 11-15 , each instruction is shown with the flags that it updates. table 11-15 flag updates instruction cn1z v c n z add ? yes yes yes yes and ???yesyes bcopy yes 1) ???? chkb ??yes?? clr ????? comp ? yes yes yes yes copy yes 1) ???? debug ????? dinit ?yes??yes dstep ????yes exit yes 1) ???? inb ????? jc ????? jl ????? ld ???yes 2) yes ldl ???yesyes mclr ???yesyes mset ???yesyes mov ???yesyes neg ? yes yes yes yes nop ????? not ???yesyes or ???yesyes pri ???yes 3) yes rr ???yesyes rl ? ? yes yes yes set ????? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-135 v1.1, 2011-03 pcp, v2.08 11.18.40 instruction timing this section gives some information about the duration of pcp instructions. please note that there are various conditions that can further affect the duration of pcp instructions (e.g. external fpi accesses from another fpi bus master to the pcp memories stall the pcp processor core). note: the clock cycles listed in table 11-16 are pcp core clock cycles. when running in 2:1 clocking mode the maximum allowed pcp core clock frequency is 180 mhz (resulting in a minimum pcp core clock cycle time of 5. 6ns). when running in 1:1 clocking mode the maximum pcp core clock frequency is the same as the maximum system peripheral bus fr equency. in the TC1798 the system peripheral bus (which is an fpi bus) is clocked with f fpi , resulting in a minimum pcp core clock cycle time of 11 .1ns (in 1:1 clocking mode). note: where an execution time is stated for an fpi instruction this is always a minimum value. a number of fpi instructions must wait for the completion of an fpi transaction (or transactions). when ru nning in 2:1 mode each fpi clock cycle consists of two core clock frequencie s. where this applies the cycle count is shown with an ?fpi? superscript designation (e.g. ?3 fpi ?). in addition there may be an additional single core cl ock cycle taken according to alignment of execution of an fpi instruction relative to an fpi clock edge. shr ???yes 3) yes shl ? ? yes yes yes st ????? sub ? yes yes yes yes xch ???yesyes xor ???yesyes 1) cn1z is only modified by the bcopy, copy or exit instructions if the instruction has been configured to decrement r6.cnt1 (for bcopy/copy cnc = 1 or cnc = 2, for exit ec = 1). all other instructions have no effect on the cn1z flag. 2) for the ld.i type of instruction, flag n is always cleared, as bit 31 of the result is always 0. 3) flag n is always cleared, as bit 31 of the result is always 0. table 11-16 instruction timing instruction number of clock cycles comments notes control nop 1 ? ? table 11-15 flag updates (cont?d) instruction cn1z v c n z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-136 v1.1, 2011-03 pcp, v2.08 copy ? ? 1) exit f = 9, s = 7, m = 6 ? 2) bcopy ? ? 1) fpi access add.f 8 min. 5 int. + 3 fpi min. for fpi read 3) and.f 8 min. 5 int. + 3 fpi min. for fpi read 3) comp.f 8 min. 5 int. + 3 fpi min. for fpi read 3) ld.f 8 min. 5 int. + 3 fpi min. for fpi read 3) or.f 8 min. 5 int. + 3 fpi min. for fpi read 3) st.f 5 min. 2 int. + 3 fpi min. for fpi write 3) sub.f 8 min. 5 int. + 3 fpi min. for fpi read 3) xch.f 8 min. 4 int. + 4 fpi min. for fpi read and write 3) xor.f 8 min. 5 int. + 3 fpi min. for fpi read 3) pram access add.pi 2 ? ? and.pi 2 ? ? comp.pi 2 ? ? ld.pi 2 ? ? mclr.pi 6 ? ? mset.pi 6 ? ? or.pi 2 ? ? st.pi 4 ? ? sub.pi 2 ? ? xch.pi 5 ? ? xor.pi 2 ? ? arithmetic (conditional) add 1 ? ? and 1 ? ? comp 1 ? ? inb 1 ? ? table 11-16 instruction timing (cont?d) instruction number of clock cycles comments notes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-137 v1.1, 2011-03 pcp, v2.08 ld.p 2 ? ? mov 1 ? ? neg 1 ? ? not 1 ? ? or 1 ? ? pri 1 ? ? st.p 4 ? ? sub 1 ? ? xor 1 ? ? immediate access add.i 1 ? ? chkb 1 ? ? clr 1 ? ? comp.i 1 ? ? inb.i 1 ? ? ld.i 1 ? ? ldl.il 1 ? ? ldl.iu 1 ? ? rl 1 ? ? rr 1 ? ? set 1 ? ? shl 1 ? ? shr 1 ? ? sub.i 1 ? ? fpi + immediate access clr.f 8 min. 4 int. + 4 fpi min. for locked fpi rmw (read, modify, write) 4) ld.if 8 min. 5 int. + 3 fpi min. for fpi read 3) set.f 8 min. 4 int. + 4 fpi min. for locked fpi rmw (read, modify, write) 4) st.if 5 min. 2 int. + 3 fpi min. for fpi write 5) table 11-16 instruction timing (cont?d) instruction number of clock cycles comments notes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-138 v1.1, 2011-03 pcp, v2.08 complex math dinit 1 ? 6) dstep 10 ? 6) minit 1 ? 7) mstep.l 10 ? 7) mstep.u 11 ? 7) jump debug sdb - 0 = 2 sdb - 1 = exit_time ? 8) jc y = 4, n = 2 ? 9) jc.a y = 4, n = 2 ? 8) jc.i y = 4, n = 2 ? 8) jc.ia y = 4, n = 2 ? 8) jl 4 ? ? 1) the number of clock cycles for these instructions depends on several param eters such as the amount of data to be copied, the type of memory, and the effective bus load. 2) f = full context save, s = small context save, m = minimum context save time extended until any previous st.f instruction has completed. 3) cycles = 5 internal + 3 minimum for fpi read (with 0 wa it cycles + 1 cycle for bus arbitration and assuming 1:1 clocking mode) 4) cycles = 4 internal + 4 minimum for fpi read/modify/w rite (with 0 wait cycles + 1 cycle bus arbitration and assuming 1:1 clocking mode) 5) cycles = 2 internal + 3 minimum for fpi write (with 0 wait cycles + 1 cycle for bus arbitration and assuming 1:1 clocking mode) time starts after any previous st.f instruction has completed. 6) 32/32 bit divide requires instruction dinit + jc + 4 dstep = 1 + 4(2) + 4 10 = 45 cycles 8/32 bit divide requires instruction rr + dinit + jc + dstep = 1 + 1 + 4(2) + 10 = 16 cycles 7) 32 8 bit multiply requi res instructions rr + minit + mstep.l = 1 + 1 + 10 = 12 cycles 32 16 bit multiply requires instructions 2 rr + minit + 2 mstep.l = 2 1 + 1 + 2 10 = 23 cycles 32 32 bit multiply requires instructions minit + 4 mstep.u= 1 + 4 11 = 45 cycles 8) sdb - 0 = stop_on_debug bit in instruction = 0 (disabling stop) sdb - 1 = stop_on_debug bit in instruction = 1 (enabling stop) exit_time = same time as for an exit instruction 9) y = jump taken, n = jump not taken table 11-16 instruction timing (cont?d) instruction number of clock cycles comments notes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-139 v1.1, 2011-03 pcp, v2.08 11.19 instruction encoding most instructions are encoded in 16 bits. this allows two instruction to be fetched out of 32 bit instruction memory per access. for example, a copy and an exit instruction can be fetched simultaneously, performing a simple dma transaction. table 11-17 field definitions symbol name description cnc counter control 00: perform the number/type of transfers appropriate to the instruction, and proceed to the next instruction. 01: perform the number/type of transfers appropriate to the instruction, then decrement cnt1 and proceed to next instruction. 10: use cnt1 as an ?outer loop counter?. perform the number/type of transfers appropriate to the instruction, then decrement cnt1. repeat until cnt1 = 0, then proceed to next instruction. if r[7].ien = true (interrupts enabled) the instruction may be interrupted at the end of each iteration of the ?outer loop?. 11: n/a (error) cnt0 internal loop counter /block size control internal loop counter for copy: 000: perform a sequence of 8 read/write transfers n: perform a sequence of n (1 <= n <= 7) read/write transfers block size control for bcopy: 000: 8 words 001: n/a (error) 010: 2 words 011: 4 words 1xx: n/a (error) condca/b condition code condition code for conditional execution of instruction. dac disable all channels control 0: no action 1: clear cs.en which stops the pcp executing and further channel programs. dst+/- destination address increment / decrement 00: no change 01: post increment by size 10: post decrement by size 11: n/a (error) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-140 v1.1, 2011-03 pcp, v2.08 ec exit count control 0: no action 1: decrement cnt1 eda external debug action 0: no external debug action caused 1: cause an external debug action (breakpoint pin etc.) ep entry point entry point on next channel invocation: 0: set the pc to channel start 1: set the pc to the address contained in nextpc (next instruction) address. note: ep=0 assumes that a channel entry table exists in the base of code memory. failure to provide one will cause improper operation. int interrupt issue interrupt 0: no 1: yes if (condcb = true) rta return to this address 0: the channel is disabled (r7.cen=0) and the pc value stored in the context is nextpc. 1: the channel remains enabled and the pc value stored in the context is nextpc - 1. sdb stop on debug 0: continue running if debug event triggered 1: stop pcp channel if debug event triggered set/clr set/clear 0: check for clear (0) 1: check for set (1) size data size 00: byte (8-bit) 01: half word (16-bit) 10: word (32-bit) 11: reserved src+/- source address increment / decrement 00: no change 01: post increment by size 10: post decrement by size 11: n/a (error) st stop channel 0: leave channel enabled 1: stop channel from accepting new service requests (clear r[7].cen) table 11-17 field definitions (cont?d) symbol name description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-141 v1.1, 2011-03 pcp, v2.08 table 11-18 instruction encoding 1514131211109876543210 0 -:control fmt ins tr dst + - src + - cnc cnt0 size nop 0 0 copy 0 1 st int ep ec - - condc b exit 1 0 condition for interrupt fmt ins tr dst + - src + - cnc - cnt0 - bcopy 1 1 1 -:fpi instruction r[b] r[a] - size add.f 0 sub.f 1 comp.f 2 error 3 error 4 and.f 5 error 6 or.f 7 xor.f 8 ld.f 9 st.f a xch.f b error c error d error e error f 2 -:pram instruction r[a] offset 6 - bit add.pi 0 sub.pi 1 comp.pi 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-142 v1.1, 2011-03 pcp, v2.08 error 3 mclr.pi 4 and.pi 5 mset.pi 6 or.pi 7 xor.pi 8 ld.pi 9 st.pi a xch.pi b error c error d error e error f 3 -:arithmetic instruction r[b] r[a] condc a add 0 sub 1 comp 2 neg 3 not 4 and 5 error 6 or 7 xor 8 ld.p 9 st.p a error b mov c inb d pri e error f table 11-18 instruction encoding (cont?d) 1514131211109876543210 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-143 v1.1, 2011-03 pcp, v2.08 4 - immediate instruction r[a] immediate 6 - bit sub.i 1 add.i 0 comp.i 2 error 3 shr 4 shl 5 rr 6 rl 7 ldl.iu 8 following #imm16 instruction ldl.il 9 following #imm16 instruction set a clr b ld.i c inb.i d chkb e s/c error f 5 -:fpi immediate instruction siz e1 r[a] siz e0 immediate 5 - bit error 0 error 1 error 2 set.f 3 clr.f 4 ld.if 5 st.if 6 error 7 6 -:complex maths op2:instruction r[b] r[a] reserved dinit 0 dstep 1 table 11-18 instruction encoding (cont?d) 1514131211109876543210 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-144 v1.1, 2011-03 pcp, v2.08 minit 2 mstep.l 3 mstep.u 4 error 5 error 6 error 7 error 8 error 9 error a error b error c error d error e error f 7 -:jump op2:instr offset 10 - bit jl 0 0 0 op2:instr condc b offset 6 - bit jc 0 0 1 jc.a 0 1 0 absolute destination in next 16 bits error 0 1 1 op2:instr condcb r[a] - - - jc.i 1 0 0 jc.ia 1 0 1 error 1 1 0 op2:instr condcb - - da c rt a ed a sd b debug 1 1 1 table 11-18 instruction encoding (cont?d) 1514131211109876543210 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-145 v1.1, 2011-03 pcp, v2.08 11.20 programming of the pcp in this section, several techniques are outlined to help design channel programs. there are also examples on configuring a channel program?s context. 11.20.1 initial pc of a channel program a channel program can begin operation at the channel entry table location corresponding to the priority of the interrupt. this is much like an interrupt vector location for that channel in a traditional processor architecture. when the channel program is started, the pc is set to two-times the channel number (srpn). since the base of the channel entry table is the bottom of the cmem address range, and since each entry in the table is two instructions long, this addre ss computation results in the first instruction of the channel program for that srpn being fetched from memory for execution. alternately, the channel program can be made to begin executing at whatever address its restored context holds in r7.pc. if pcp_cs.rcb = 1, then the channel program is forced to always start at its channel entry table location regardless of the pc value stored in the csa. if pcp_cs.rcb = 0, then the channel program will simply begin executing at whatever pc value is restored in the context r7.pc. it is important to be aware of the implications of these two approaches on how cmem should be configured, and what the initial value of the pc should be in the channel program?s context that is loaded in the pram csa at boot time. 11.20.1.1 channel entry table when pcp_cs.rcb = 1, the program counter of the pcp is vectored to the appropriate channel entry table each time a channel program is invoked by the receipt of an interrupt. the pcp is forced to start executing from its channel entry table location, regardless of its previous context or pc state. if the exit instruction is executed with ep = 0, the pc saved during the context save operation will be the channel entry table loca tion for that channel. that means that the next time the channel program is started, it will begin operation at the appropriate location in the channel entry table. note: if ep = 0 is set in any channel progra m, or if pcp_cs.rcb = 1, a channel entry table must be provided at the base of cm em. otherwise this table is not needed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-146 v1.1, 2011-03 pcp, v2.08 11.20.1.2 channel resume when pcp_cs.rcb = 0, the program counter of the pcp is vectored to the address that is restored from the channel program?s cont ext. this means that before exiting, a channel program must itself arrange for where it will resume execution by configuring the value of its pc in its save d context so that it restarts at the desired location. in this way, arbitrarily complex interrupt-driven state machines can be created as individual channel programs. channel program s can be constructed that always start at their beginning, pick up where they left off, or pick up elsewhere, or have a mix of these approaches. an example of a restarting channel program is shown below. before exiting, the channel branches back to the address of the start label minus 1 (note that start - 1 = ch16) and then exits. this will leave the next value of the pc in the channel program?s context as the address of the start label. ch16: ;channel program 16 exit ec=1 st=0 int=0 ep=1 cc_uc ;exit, no intr., leave pc @ next start: ;nominal channel start address st.if base #0x8 size=32 ;output note from r0 jc ch16, cc_uc ;loop back before exit note that when the channel program is orig inally configured by the programmer, the pc field in the r7 context of this channel program should also be set to the address of the start label. similarly, an interrupt-driven state machine can be created by exiting with the next pc value pointing to the start of the next state in a state machine implemented by the channel program. the next example below shows a program starting at the address to the state0 label. it proceeds after the first interrupt to state1 - 1, where the channel program is left ready for the next state, state1 in the state machine. after the next interrupt, it executes to address state2 - 1 and the channel program is left ready for the next state, state2. after another inte rrupt, it proceeds through state2. the channel program jumps back to start, which is state0 - 1. the state machine has gone through one cycle and it is ready to restart in state0. ;this program is intended to test the sequence of exit/operate ;just as if you were implementing an interrupt driven ;state machine. ;it requires a periodic sequence of interrupts. start: exit ec=1,st=0,int=0,ep=1,cc_uc;begin exit state0: comp.i r5,#0x0 ;compare to interrupt number ;it should be www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-147 v1.1, 2011-03 pcp, v2.08 jc error,cc_nz ;jump to error routine ;if not correct add.i r5,#0x1 ;increment state number exit ec=1,st=0,int=0,ep=1,cc_uc ;begin exit state1: comp.i r5,#0x1 ;compare to interrupt number ;it should be jc error,cc_nz ;jump to error routine ;if not correct add.i r5,#0x1 ;increment state number exit ec=1,st=0,int=0,ep=1,cc_uc ;begin exit state2: comp.i r5,#0x2 ;compare to interrupt number ;it should be jc error,cc_nz ;jump to error routine if ;not correct ld.i r5,#0x0 ;reset state number jc start,cc_uc ;jump back to start of ;state machine the last state could just as easily have ended with an exit that resets the pc to the channel entry table (ep = 0) rather than jumping back to start. 11.20.2 channel management fo r small and minimum contexts if small or minimum contexts are being used, only some of the registers are saved and restored. the integrity of the gprs that are not included in the context must be handled explicitly by channel programs, since these are not saved and restored with the context of the interrupted channel program. channel programs may still use all registers reliably. channel programs can be so designed that they either ignore the values in unsaved registers, or use those registers to store constants that no channel progra m changes. hence, they never need to be saved and restored. alternately, channel programs can use these unused gprs as temporary variables as long as the values of such registers cannot be corrupted by the interrupt of the channel program by a higher-priority channel (see page 11-151 ). 11.20.3 unused registers as global?s or constants registers r0 through r3 (for the small context model), or r0 through r5 (for the minimum context model) can be used to store constants such as addresses that are available to all channel programs. hence, these registers hold global data, and no channel program is allowed to change them. since the gprs of the pcp are not directly accessible from the fpi bus, there does need to be an initial channel program that sets these values at or near boot time. there are www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-148 v1.1, 2011-03 pcp, v2.08 two choices here. a boot-time interrupt channel program can be invoked once to perform initialization, or there can be a program that routinely loads these values as a matter of course, and is invoked at boot time or as upon receipt of the very first interrupt. 11.20.4 dispatch of low priority tasks a higher-priority channel program may wish to start a low-priority background task, or periodically pause and re-start itself later when there is no other action required at the moment. this can be accomplished in several ways: ? post an srpn to a free srn on the fpi bus, then exit. ? perform an exit, posting the interrupt to the pcp, and indicating the channel number to be started. ? use a single channel program as a list-dr iven or state-driven task dispatcher. the first approach is strai ghtforward to program, but us es a system srn resource. its advantage is that it allows continuous channel operation without using the interrupt queue, or risk blocking other uses of the pcp. the second approach can be implemented by having a looping channel program continue operation in the background. it will also always be superseded by any higher- priority tasks. the third approach uses a channel program to dispatch other non-interrupt-driven channel programs in an arbitrary order deter mined by the channel program dispatcher. in this way, multiple tasks could be contin uously operated without over-using the pcp service-request queue. this approach would be useful when the aim is to poll for service requests in the peripheral srns rather th an having them started by pcp hardware. 11.20.5 code reuse across channels (call and return) a special jump instruction is included in the pcp instruction set to allow subroutines to be called from multiple channel programs. a routine may be jumped to directly, and then returned from using the jc.ia instruction. jc.ia allows a calling channel program to set aside a register for its return address, which will typically be the value of the next pc. the called subprogram can then execute a jc.ia, to the address stored in the register specified, causing a return-from-subroutin e operation. the programmer must adopt and enforce a calling convention to determine which register holds the return address. register r2 is normally used for this purpose. for example: main routine: subroutine: ld.il r2,#return sub: mov... jc.a #sub add... return: mov ... ... ... jc.ia r2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-149 v1.1, 2011-03 pcp, v2.08 11.20.6 case-like code switches (computed go-to) the jc.i instruction can be used to implem ent a multi-way branch for branch-on-bit or branch-on-state conditional branches. this instruction allows a conditional relative jump based on an index held in a register. if this instruction is combined with a table of jump addresses, a switch-type statement can be implemented. the default case, that is when the condition code = false, is the next instruction, as is the jump with register index = 0. the table can be any arbitrary length. the in dex register should be checked for range before the jump into the table is performed. for example: comp r3,#5 ;compare r3 to #5 - the number ;of entries in the table jc.i r3,cc_ule default: jl #case_0 ;destination if r3 = 0 or ;condition = false jl #case_1 ;destination if r3 = 1 jl #case_2 ;destination if r3 = 2 jl #case_3 ;destination if r3 = 3 jl #case_4 ;destination if r3 = 4 jl #case_5 ;destination if r3 = 5 11.20.7 simple dma operation a simple interrupt-driven dma requires at least the small context model to operate properly. its operation is consists of three stages: ? the device interrupts the pcp to indicate it can receive or provide data. ? the pcp moves the amount of data it is programmed to move. ? the pcp eventually finishes and interrupts the cpu to notify it that the dma is complete. there are two options for implementing a si mple dma operation, copy and burst copy. 11.20.7.1 copy instruction a simple dma channel program can consist of only two instructions. in the example below, a device interrupts the pcp to notify it that it has data in its output buffer, which is 4 words deep. the copy instruction copies 4 words to memory at a time. it decrements cnt1 (which is initialized by the cpu in cr6_cnt1 context) after each 4 word transfer. the exit command then executes, and if cnt1 was decremented to 0, the condition code causes it to issue an interrupt with the value held r6_srpn. copy dst+,src,cnc=1,brst=4,size=32 ;do peripheral -> memory dma exit ec=0,st=0,int=1,ep=0,cc_cnz ;transfer done, so exit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-150 v1.1, 2011-03 pcp, v2.08 in the example above, the copy instruction increments the destination held in r5 (dst+), and the source address is left constant in r4 (src). all permutations of decrement, increment or do not modify can be applied to either pointer register (r4 and r5) by use of the src and dst fields (src- , src+ or src and dst-, dst+ or dst). building on this basic dma method, scatter-gather dma channels can be created. 11.20.7.2 bcopy instruction (burst copy) the bcopy instruction is in principle similar to the copy instruction except that it uses the fpi burst mode to perform the transfers rather than performing individual reads/writes. as for the copy instruction, the fpi bus is locked between the burst read and burst write to ensure that a valid set of data is transferred. the bcopy instruction allows support of all burst sizes supported by fpi burst mode except a burst size of 1 (i.e. 2, 4 or 8 words). the cnt0 field is used to control the burst size. both the source and destination addresses (r4 and r5) must be correctly aligned for the burst size being used (see the fpi bus description for details). if either address is incorrectly aligned, the pcp will generate an illegal operat ion error exit. see also page 11-157 for TC1798 specific details of the bcopy instruction. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-151 v1.1, 2011-03 pcp, v2.08 11.21 pcp programming notes and tips this section discusses constraints on the use of the pcp and points out some non- obvious issues. 11.21.1 notes on pcp configuration for configuring of the pcp, some notes should be regarded. ? only one context model may be used at a time for all channels, and the pcp must remain in that context model once started and configured. ? in order for a specific channel program to be enabled, its context must have r7.cen = 1. if r7.cen = 0, the channel program will terminate when invoked, and cause a disabled channel request error. ? the channel context address from the fpi bus as viewed during channel configuration is as follows: ? full context model: pram base + 20 h n ? small context model: pram base + 10 h n ? minimum context model: pram base + 08 h n where n is the channel number. ? pcp_cs.rcb and context must be consistent. if rcb is configured to 0, then each channel program will start at the pc restored from its context. if the wrong address is pre-configured in the context, the channe l program will not operate properly. ? the programmer of the pcp may lock pcp_cs by setting pcp_cs.eie = 1. when the global endinit bit is set, the pcp_cs register will no longer be writable, and attempting to do so will cause an fpi bus error. ? an error condition will result in an interrupt being sent to the local fpi bus master. the targeted interrupt service routine must be capable of dealing with the cause as recorded in pcp_es, and, if required, it must be able to return the halted channel program to operation. the minimum required to do that is to set the context value of r7.cen = 1. ? the only pcp register bit that can be dynamically modified during pcp operation is the pcp_cs.en bit. when writing to any other pcp register bits, the user must ensure that the pcp is disabled (pcp_cs. en = 0) and that the pcp is quiescent (pcp_cs.rs = 0). 11.21.2 general purpose register use when using the general purpose registers of the pcp, some notes should be regarded. ? the most significant 16 bits of r7 may no t be written, and w ill always read back as 0. however, no error will occur if a write to the most significant 16 bits occurs. ? care must be taken with the use of r6 as a general-use register to ensure that r6 contains the correct value prior to execution of the exit command. as r6 contains the cnt1 (counter used in copy and optionally in exit instructions), srpn and www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-152 v1.1, 2011-03 pcp, v2.08 tos (service request number to use during optional interrupt at channel program exit) fields, r6 should not be used to pass values from one invocation of a channel program to the next invocation. ? if pram is to be accessed programmatically, then r7.dptr must be configured properly as a pointer into the pram. this points to the 64-word segment that may be addressed by the xx.p instructions and the xx.pi instructions. it is not recommended to set r7.dtpr to point into the csa. special care must be taken that the context pram is not overwritten. ? the programmer must be careful not to inadvertently clear r7.cen when updating r7.dtpr (or any other field in r7). this would cause the channel program to generate a disabled channel interrupt to th e cpu when the next interrupt request to the channel occurs. ? any update to the flags that is caused by an instruction (e.g. mov r7, r0 which updates z and n) takes precedence over any explicit bits that are moved to r7. see page 11-11 . ? the interrupt system assumes srpn 0 is not a request. full context packing leaves the least significant 8 32-bit entries where channel 0 would normally be unused. that is, pram base -> pram base + 1 channel. in addition, for small context, the least significant 4 32-bit entries are unused, and for minimum context the least significant 2 32-bit entries are un-used. these ?unused? entries should not be used by channel programs. ? if ep = 0 is used, or if pcp_cs.rcb = 1, a channel entry table must be provided at the base of cmem. ? if there is a plan to use the small or minimum context model, and the lower registers are to hold global values, then there needs to be an initial channel program that sets these values at or near boot time. there are at least two choices for implementing this. for instance, a boot interrupt channel program can be invoked once to perform initialization, or there can be a program that routinely loads these values as a matter of course, and it is invoked at boot time, or at the very first interrupt. see page 11-147 . ? when using small or minimum context models and allowing a channel to be interrupted, care must be taken to ensure that the value of any registers that are not included in the context but are being used by a channel are not corrupted by interruption of the channel and subsequent operation of a higher-priority channel. particular care must be taken when using instructions that use r0 implicitly. if necessary, critical instruction sequences should be protected by use of the r7.ien bit (see page 11-153 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-153 v1.1, 2011-03 pcp, v2.08 11.21.3 use of channel interruption for channel interruption, the following note should be regarded. ? when a channel program consists of only a few instructions, it is best to configure the channel to be non-interruptible. this in creases overall efficiency by removing the context save/restore overhead that would be incurred if the channel were to be interruptible. 11.21.3.1 dynamic interrupt masking a channel program can dynamically control w hether it can be interrupted by use of the r7.ien bit. when masking interrupts (by clearing r7.ien), it must be noted that there is a delay of one instruction before the mask becomes effective. as a result the instruction that clears r7.ien must be placed at least one instruction before the instruction sequence that is to be un-interruptible. as an example, consider the following sequence: clr r7,ien ;clear the r7.ien bit ;<< interrupt can occur here nop ;<< interrupt can occur here ;first instruction of non-interruptible ;code sequence 11.21.3.2 control of channel priority (cppn) the pcp has three extended service request nodes (pcp_src9, pcp_src10 and pcp_scr11) that allow storage of suspended channel interrupt requests. this allows interrupt nesting to a depth of four. this limit on the nesting depth carries the danger that a high-priority service request will not be serviced because the pcp?s interrupt nesting depth has been exceeded. it is recommended that a four-level ?grouping? scheme should be adopted to avoid this problem. all pcp interrupt sources should be listed in order of their srpns.this list should then be subdivided into four contiguous groups, group 0 being the lowest priority and group 3 the highest. the csa for each channel program should be configured such that cr6.cppn contains the srpn value of the highest channel program within the group to which the channel belongs. as each channel starts, the operating priority (cppn) of the channel is loaded from the context. using the scheme recommended above, any channel program will run with the priority of the highest srpn within the group. as a result, the channel can only be interrupted by a service request from a higher-priority group (e.g. a group 0 channel program can be interrupted by a new service request for a channel in any group fr om 1 to 3, a group 2 channel program can only be interrupted by a new service request for a channel in group 3). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-154 v1.1, 2011-03 pcp, v2.08 note: when using this scheme, each channel program must ensure prior to channel exit that the r6.cppn field contains the appr opriate value, so that when the channel is next invoked, it will run at the correct priority. 11.21.4 implementing divide algorithms as discussed in section 11.18.4 , a divide algorithm must always start with a dinit instruction followed by a number of dstep instructions (up to four depending on the data width that is required). prior to execution of any dstep instruction, r0 always contains either 0 (if this is the first dstep instruction in a divide sequence r0 contains 0 due to the preceding dinit instruction, or the remainder from the previous dstep instruction). the dividend to be used in this step is generated in r0 by taking 256 the remainder of the last dstep instruction (r0 << 8) and adding the most significant byte of rb (rb >> 24) as the lsb of the new dividend. since the remainder of the last dstep instruction is by definition always less than the divisor (ra), it can be guaranteed that the result of the division of the dividend (calculated as above) by the divisor (ra) can always be contained within an 8-bit result. the description given on page 11-114 only holds true under this condition. if the restrictions on the use of the dstep instruction (specified on page 11-105 ) are adhered to, the above condition will always be met and this description of the instruction is correct. failure to adhere to these conditions will lead to invalid results, which are outside the scope of this document. during execution of a divide sequence, rb is used both to compile the final divide result and to hold the remnants of the original dividend. for example, in a 32-/32-bit divide sequence (which consists of 4 dstep instructions - see below), rb will have the following content: ? after the 1 st dstep instruction: the least significant 3 bytes (24 bits) of the original 32-bit dividend (held in the most significant 3 bytes of rb) and the most significant byte of the final result (held in the least significant byte of rb). ? after the 2 nd dstep instruction: the least significant 2 bytes (16 bits) of the original 32-bit dividend (held in the most significant 2 bytes of rb) and the most significant 2 bytes of the final result (held in the least significant 2 bytes of rb). ? after the 3 rd dstep instruction: the least significant byte of the original 32-bit dividend (held in the most significant byte of rb) and the most significant 3 bytes of the final result (held in the least significant 3 bytes of rb). ? after the final dstep instruction: the 32 bit final result. note that the dstep instruction always uses the divisor as a 32 bit value. in any divide sequence, the dividend can be 8, 16, 24 or 32 bits (according to the number of dstep www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-155 v1.1, 2011-03 pcp, v2.08 instructions in the sequence) but the divisor is always 32 bits. prior to the dinit instruction, the dividend must always occupy the appropriate most significant bits within the 32-bit dividend register (rb). divide examples example of a 32/32 bit divide (r5 / r3): dinit r5, r3 ;initialize ready for the divide jc handle_divide_by_zero, cc_v ;v flag was set ;so jump to divide ;by zero error handler dstep r5, r3 ;4 dstep instructions ;(4 * 8 = 32 bit dstep r5, r3 ;divide) dstep r5, r3 dstep r5, r3 after this sequence, r5 holds the result, r0 the remainder and r3 is unchanged. example of a 8/32 bit divide (r4 / r2): rr r4, 8 ;rotate r4 right by 8 to move ;least significant byte into ;most significant byte dinit r4, r2 ;initialize ready for the divide jc handle_divide_by_zero, cc_v ;v flag was set ;so jump to divide ;by zero error handler dstep r4, r2 ;dstep instruction ;(1 * 8 = 8 bit divide) after this sequence, r4 holds the result, r0 the remainder and r2 is unchanged. note that the above example is specified as bei ng a 8/32 bit divide rather than an 8/8 bit divide (see comments above). 11.21.5 implementing multiply algorithms as discussed in section 11.18.4 , a multiply algorithm must always start with a minit instruction, followed by a number of mstep32 or mstep64 instructions. the mstep32 instruction is used to compile a multiplication result contained in 32 bits, discarding any overflows. the mstep64 instruction is used to compile a 64-bit multiplication result with the least significant 32 bits of the result contained in rb and the most significant 32 bits of the result contained in r0. multiply examples example of a 32 8 bit multiply (r4 r1) yielding a 32 bit result (r4 = 32 bit, r1 = 8 bit): www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-156 v1.1, 2011-03 pcp, v2.08 rr r1, 8 ;rotate least significant byte of r1 ;to most significant byte minit r1, r4 ;initialize ready for multiply mstep32 r1, r4 ;perform one mstep32 instruction ;(8 bit multiply) after this sequence, r0 holds the result, r1 is left unchanged (right rotated by rr instruction then left rotated by mstep32 instruction), and r4 is unchanged. the result is only valid if there is no overflow (i.e. the product of the 8-bit number in r1 multiplied by the 32-bit number in r4 can be contained within 32 bits). it is the user?s responsibility to ensure that this is the case. the overflow condition cannot be detected after execution of the multiply sequence. example of a 32 16 bit multiply (r3 r2) yielding a 32 bit result (r3 = 32 bit, r2 = 16 bit): rr r2, 8 ;perform two 8 bit rotations ;(rr instructions) to get original ;least significant 16 bits into ;most significant 16 bits rr r2, 8 minit r2, r3 ;initialize ready for multiply mstep32 r2, r3 ;perform two mstep32 instructions ;(16 bit multiply) mstep32 r2, r3 after this sequence, r0 holds the result, r2 is left unchanged (right rotated by two rr instructions, then left rotated by two mstep32 instructions), r3 is unchanged. the comment above regarding overflow also applies to this sequence. example of a 32 32 bit multiply (r5 r2) yielding a 64 bit result (r5 = 32 bit, r2 = 32 bit): minit r2, r5 ;initialize ready for multiply mstep64 r2, r5 ;perform 4 mstep64 instructions ;(64-bit multiply) mstep64 r2, r5 mstep64 r2, r5 mstep64 r2, r5 after this sequence r0 and r2 hold the result (most significant word in r0, least significant word in r2), r5 is unchanged. there is no possibility of overflow as the result of 32 32 bits can always be contained in 64 bits. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-157 v1.1, 2011-03 pcp, v2.08 11.22 implementation of the pcp in the TC1798 the addresses of the pcp registers and memories in the TC1798 are given in the following subsections: 11.22.1 pcp memories in the TC1798, the location of the registers and the memories sizes of the pram and the cmem are given in table 11-19 . note: ?be? means that in case of an a ccess to this address region a bus error is generated. 11.22.2 bcopy instruction in the TC1798, the bcopy instruction can be used to perform burst transfers (2, 4, or 8 words) with dmi memories (local data ram) and the pcp memories. other internal and external memories can be accessed using a burst size of 2 words only (cnt0 = 10 b ). 11.22.3 pcp reset operation the pcp module can be reset by a system hardware signal (hard reset). pcp hard reset a pcp hard reset is always triggered if at least one of these TC1798 reset sources becomes active: ? watchdog timer reset ? hardware reset ? power-on reset table 11-19 general block address map unit address range access mode size read write pcp reserved f004 0000 h - f004 3eff h be be ? pcp registers f004 3f00 h - f004 3fff h see page 11-67 256 byte reserved f004 4000 h - f004 ffff h be be ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 peripheral control processor (pcp) users manual 11-158 v1.1, 2011-03 pcp, v2.08 each of these reset sources forces a hardware reset of the function al blocks within the pcp module. the effect of hard reset within the pcp is to: ? halt any operating channel ? reset all control registers to their reset values ? reset the pcp processor core to its default state ? reset the fpi bus interface www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-1 v1.1, 2011-03 dma, v1.6 12 direct memory acc ess controller (dma) this chapter describes the direct memory access (dma) controller and the memory checker module (mchk) of the TC1798. it contains the following sections: ? functional description of the dma controller kernel (see section 12.2 ) ? dma controller module register description (see section 12.3 ) ? TC1798 implementation-specific details of the dma controller (interrupt control, address decoding, clock control, see section 12.4 ) ? functional description of the memory checker (mchk) module (see section 12.5 ) ? memory checker module register description (see section 12.5.2 ) note: the dma kernel register names described in section 12.3 are referenced in the TC1798 users manual by the module name prefix ?dma_?. 12.1 what is new major differences of the audomax dma compared to audofuture: ? the audomax system architecture uses an sri-xbar in place of an lmb-bus. the dma lmb-master is replaced by an sri-master. ? the lmb-master 64-bit buffer to support read accesses to cached addresses (segment 8) is replaced by an sri-mast er 256-bit buffer. in audofuture a segment 8 read access was translated to a single data transfer double-word (sdtd) access; in audomax it is translated to a 4-transfer block transfer request (btr4) access. ? the access protection is extended from 32 to 64 fixed address ranges by the addition of a second move engine access enable register. the number of programmable address range extensions is increased from 4 to 8 by the addition of a second move engine access range register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-2 v1.1, 2011-03 dma, v1.6 12.2 dma controller kernel description the dma controller of the TC1798 transfers data from data source locations to data destination locations without intervention of the cpu or other on-chip devices. one data move operation is controlled by one dma channel. eight dma channels are provided in one dma sub-block. the bus switch provi des the connection of the dma sub-blocks to the two on chip bus interfaces and a dma peripheral interface. in the TC1798, the two on chip bus interfaces are connected to the system peripheral bus and the sri bus. the dma peripheral interface provid es a connection to the cerberus module, micro link interface modules and other dm a-related devices (memory checker module in the TC1798). clock control, address decoding, dma request wiring, and dma interrupt service request control are implem entation-specific and are managed outside the dma controller kernel. the index ?m? in the following block diagram refers to the dma sub-block number (m = 0-1). figure 12-1 dma block diagram interrupt request nodes mcb06149 clock control f dma sr[15:0] dma controller arbiter/ switch control bus switch fpi bus in terf a ce sri bus interface dma peripheral interface memory checker mli0 system peripheral bus sri bus dma requests of on-chip periph . units address decoder dma interrupt control ch0n_out dma channels 00-07 dma sub-block m request selection/ arbitration transaction control unit mli1 cerberus www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-3 v1.1, 2011-03 dma, v1.6 12.2.1 features the dma controller is a fast and flexible dma controller that has the following features: ? 16 independent dma channels ? 2 dma sub-blocks with (8 dma channels per dma sub-block) ? dma sub-blocks with support of paralle l channel execution (1 channel per sub- block, both sub-blocks in parallel) ? up to 16 selectable request inputs per dma channel ? 2-level programmable priority of dma channels within the dma sub-block ? software and hardware dma request ? hardware requests by selected on-chip peripherals and external inputs ? 3-level programmable priority of the dma sub-blocks on the chip bus interfaces ? buffer capability for move acti ons on the buses (at least 1 move per bus is buffered) ? sri master interface with 256-bit read buffer for read accesses to cached areas (segment 8). ? individually programmable operation modes for each dma channel ? single mode: stops and disables dma channel after a predefined number of dma transfers ? continuous mode: dma channel remains enabled after a predefined number of dma transfers; dma transaction can be repeated ? programmable address modification ? two shadow register modes (with / w/o automatic reset and direct write access). ? full 32-bit addressing capability of each dma channel ? 4 gbyte address range ? data block move > 32 kbyte per dma transaction ? circular buffer addressing mode with flexible circular buffer sizes ? programmable data width of dma transfer/ transaction: 8-bit, 16-bit, or 32-bit ? register set for each dma channel ? source and destination address register ? channel control and status register ? transfer count register ? flexible interrupt generation (the servic e request node logic for the mli channels is also implemented in the dma modules) ? dma module is working on fpi frequency, sri interface on sri frequency. dependant on the target/destination address, read/write requests from the move engines are directed to the fpi bus, sr i bus, mlis or to the cerberus module. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-4 v1.1, 2011-03 dma, v1.6 12.2.2 definition of terms some basic terms must be defined for the functional description of the dma controller. dma move a dma move is an operation that always consists of two parts: 1. a read move that loads data from a data source into the dma controller 2. a write move that puts data from the dma controller to a data destination within a dma move, data is always moved from the data source via the dma controller to the data destination. data is temporarily stored in the dma controller. the data widths of read move and write move are always identical (8-bit, 16-bit or 32-bit). data assembly or disassembly is not supported. figure 12-2 dma definition of terms dma transfer a dma transfer can be composed of 1, 2, 4, 8 or 16 dma moves. dma transaction a dma transaction is composed of several (at least one) dma transfers. the transfer count determines the number of dma transfers within one dma transaction. example: 1024 word (32-bit wide) transactions can be composed of 256 transfers of four dma word moves, or 128 transfer s of eight dma word moves. mca06150 data destination dma controller read move write move dma move dma channel data source www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-5 v1.1, 2011-03 dma, v1.6 12.2.3 dma principles the dma controller supports dma moves from one address location to another one. dma moves can be requested either by hardware or by software. dma hardware requests are triggered by specific request lines from the peripheral modules or from other dma channels (see figure 12-3 ). the number of available dma request lines from a peripheral module varies depending on the module functionality. typically, the parallel occurrence of dma requests and interrupts requests for dma channels is possible. therefore, the interrupt control unit and t he dma controller can react independently to interrupt and dma requests that have been generated by one source. figure 12-3 dma principle the dma controller mainly consists of two dma sub-blocks and a bus switch. once configured, the dma su b-blocks are able to act as a ma ster on the fpi bus and on the sri bus. mca06151 request dma controller dma sub- block 0 on - chip peripheral unit 1 request request bus switch on - chip peripheral unit 2 on - chip peripheral unit 3 fpi bus lmb bus dma peripheral interface dma sub- block 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-6 v1.1, 2011-03 dma, v1.6 12.2.4 dma channel functionality each of the 16 dma channels has one associated register set containing seven 32-bit registers. these registers ar e numbered by one index to indicate the related dma sub- block and one index to indicate the related dma channel: index ?m? refers to the dma sub-block number (m = 0-1) and index ?n? refers to the channel number (n = 0-7) within the dma sub-block. example: chcr04 is the control register of dma channel 4 in sub-block 0. the register set of a dma channel register contains the following registers: ? channel mn control register chcr0n (for details, see page 12-85 ) ? channel mn status register chsr0n (for details, see page 12-89 ) ? channel mn interrupt control register chicr0n (for details, see page 12-90 ) ? channel mn address control register adrcr0n (for details, see page 12-92 ) ? channel mn source address register sadr0n (for details, see page 12-97 ) ? channel mn destination address register dadr0n (for details, see page 12-98 ) ? channel mn shadow address register shadr0n (for details, see page 12-99 ) 12.2.4.1 shadowed source or destination address as a typical application, an asc module that receives data (fixed source address) has to deliver it to a memory buffer using a dma transaction (variable destination address). after a certain amount of data has been transferred, a new dma transaction should be initiated to deliver further asc data into another memory buffer. while the destination address register is updated during a running dma transaction with the actual destination address, a shadow mechanism allows pr ogramming of a new destination address without disturbing the content of the destination address register. in this case, the new destination address is written into a buffer r egister, i.e. the shadow address register. at the start of the next dma transaction, the new address is transferred from this shadow address register to the destination address register without cpu intervention. this shadow mechanism avoids the cpu having to check for the end of a dma transaction before reprogramming address registers. the shadow address register can be used also to store a source address. however, it cannot store source and destination address at the same time. this means that the shadow mechanism makes it possible to automatically update either a new source address, or a new destination address at the st art of a dma transaction. if both address registers (for source and destination address) have to be updated for the next dma transaction, a running dma transaction for this channel must be finished. after that, source and destination address registers ca n be written before the next dma transaction is started. figure 12-4 shows the actions that take place when a source address register is updated. the update of a destination register happens in an equivalent manner. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-7 v1.1, 2011-03 dma, v1.6 when writing a new address to the (address of) the source or destination address register and no dma transaction is running, the new address value is directly written into the source or destination address register. in this case, no buffering of the address is required. when writing a new address to th e (address of) the source or destination address register and a dma transaction is running, no transfer to an address register can take place and shadrmn holds the new address value that was written. for this operation, bit field adrcrmn.shct must be set either to 01 b (address is a source address) or 10 b (new address is a destination addr ess). at the start of the next dma transaction, the shadow transfer takes place and the content of shadrmn is written either into sadrmn or dadrmn (adrcrmn.shct must be set accordingly). after the shadow transfer, shadrmn is set to 0000 0000 h if the shadow register write enable bit is set to 0 (adrcrmn.shwen = 0). in this case (adrcrmn.shwen = 0), the software can check by reading the shadow address regist er whether or not the shadow transfer has already taken place. only one address register can be shadowed wh ile a transaction is running, because the shadow register can only be assigned either to the source or to the destination address register. note that the shadow address regist er transfer has the same behavior in single and continuous mode. when the shadow mechanism is disabled (adrcrmn.shct = 00 b ), shadrmn is always read as 0000 0000 h . if the shadow address register write enable bit is set to 1 (adrcrmn.shwen = 1), the shadow register shadrmn can be di rectly written. in this case (adrcrmn.shwen = 1) the value stored in the shadrmn is not modified when the shadow transfer takes place, and the shadow mechanism remains active and the shadow transfer will be repeated until channel mn is reset or until the value in shadr is 0000 0000 h , is written into the shadow register (direct or indirect by writing to the source or destination address register according to the shadow control register adrcrmn.shct). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-8 v1.1, 2011-03 dma, v1.6 figure 12-4 source address update (m = 0-1) the transfer count of a dma transaction, stored in bit field chcrmn.trel, can also be programmed if the dma transaction is running. at the start of a dma transaction, trel is transferred to bit field chsrmn.tco unt, which is then updated during the dma transaction. no reload of address or counter will be done if tcount is not equal to 0. the reprogramming of channel specific valu es (except for the selected address shadow register) should be avoided while a dma channel is active. mca06152 write new source address to ( address of ) sadrmn no new transaction started ? & (adrcrmn.shct = 01 b ) yes no content of shadr0n is transferred into sadrmn . if adrcrmn.shwen = 0 then shadrmn := 00000000 h yes transaction running ? (chsrmn.tcount != 0 or trsr.chmn = 1) new source address is directly transferred into sadrmn store new source address intermediately in shadrmn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-9 v1.1, 2011-03 dma, v1.6 figure 12-5 shadow source address and transfer count update with adrcrmn.shwen = 0 (m = 0-1) figure 12-5 shows how the contents of the source address register sadrmn and the transfer count chsrmn.tcount are updated during two dma transactions with a shadowed source address and transfer count update. at reference point 2) the dma transaction 1 is finished and dma transaction 2 is started. at 1) the dma channel is reprogrammed with two new parameters for the next dma transaction: transfer count tc2 and source address sa2. source address sa2 is buffered in sadrmn and transferred to sadrmn when the new dma transaction is started at 2). at this time, transfer count tc2 is also transferred to chsrmn.tcount. note that the shadow address register is only reset by hardware to 0000 0000 h as shown in this example, if the write enable bit is set to 0 (adrcrmn.shwen = 0). mct06153 tc1 = transfer count 1 tc2 = transfer count 2 sa1 = source address 1 sa2 = source address 2 tc1 1 tc1-1 tc2 tc2-1 tc2-2 tc1 tc2 tc3 sa1 sa1+1 sa2+1 sa2+2 sa2 tc1-1 sa1+ tc1 sa1+ sa2 sa3 1) 3) = writing to chcrmn and sadrmn 2) = start of new dma transaction with shadow transfer of source address 0000 0000 h 0 chsrmn.tcount shadrmn with adrcrmn.shct= 01 b sadrmn chcrmn.trel 1) 3) 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-10 v1.1, 2011-03 dma, v1.6 12.2.4.2 dma channe l request control figure 12-6 shows the control logic for dma requests that is implemented for each dma channel. figure 12-6 channel request control (m = 0-1) two different types of dma requests are possible: ? hardware dma requests ? software dma requests the hardware request chmn_req can be connected to one of sixteen possible hardware request input lines as selected by bit field chcrmn.prsel. the hardware request input structure for chcrmn.prsel includes a positive edge detector as the dma channels requires single pulse requests. hardware requests are enabled/disabled by status bit trsr.htremn. htremn can be set/reset by software or by hardware in single mode at the end of a dma transaction. a software request can be generated by setting bit streq.schmn. mca06154c trsr transfer request to channel arbiter htremn streq schmn & trsr chmn set reset chcrmn rroat end of transfer reset set reset m u x chcrmn chmode suspend control & susenmn suspmr trsr 0 1 end of transaction dchmn echmn htreq suspend request & transfer request lost interrupt errsr trlmn & set chrstr chmn end of transaction 1 1 pattern match reset reset m u x 4 chcrmn prsel chmn_req chmn_reqi00 chmn_reqi01 chmn_reqi02 chmn_reqi13 chmn_reqi14 chmn_reqi15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-11 v1.1, 2011-03 dma, v1.6 status flag trsr.chmn indicates whether or not a software or hardware generated dma request for dma channel mn is pending. trsr.chmn can be reset by software or by hardware at the end of a dma transfer (rroat = 0) or at the end of a dma transaction (rroat = 1). if a software or a hardware dma request is detected for channel mn while trsr.chmn is set, a request lost event occurs. this error event indicates that the dma is already processing a transfer and that another trans fer has been requested before the end of the previous one. in this case, bit errsr.trlmn will be set and a transfer lost interrupt can be generated. 12.2.4.3 dma channel operation modes the operation mode of a dma channel is individually programmable for each dma channel mn. basically, a dma channel can operate in the following modes: ? software controlled mode ? hardware controlled mode, in single or continuous mode in software-controlled mode, a dma channel re quest is generated by setting a control bit. in hardware-controlled mode, a dma channel request is generated by request signals typically generated by on-chip peripheral units. in hardware-controlled single mode, a dma channel mn becomes disabled by hardware after the last dma transfer of its dma transaction. in hardware-controlled continuous mode, a dma channel mn remains enabled after the last dma transfer of its dma transaction. in hardware- and software-controlled mode, a dma request signal can be configured to trigger a complete dma transaction or one single transfer. software-controlled modes in software-controlled mode, one software request starts one complete dma transaction or one single dma transfer. software-controlled modes are selected by writing htreq.dchmn = 1. this forces status fl ag trsr.htremn = 0 (hardware request of dma channel mn is disabled). the software-controlled mode that initiates one complete dma transaction to be executed is selected for dma channel mn by the following write operations: ? chcrmn.rroat = 1 ?streq.schmn=1 setting streq.schmn to 1 (this is the software request) causes the dma transaction of dma channel mn to be started and trsr.chmn to be set. at the start of the dma transaction, the value of chcrmn.trel is loaded into chsrmn.tcount (transfer count or tc) and the dma transfers are executed. after each dma transfer, tcount becomes decremented and next source and destination addresses are calculated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-12 v1.1, 2011-03 dma, v1.6 when tcount reaches the 0, dma channel mn becomes disabled and status flag trsr.chmn is reset. setting streq.schmn again starts a new dma transaction of dma channel mn with the parameters as actually defined in the channel register set. the software-controlled mode that initiates a single dma transfer to be executed is selected for dma channel mn by the following write operations: ? chcrmn.rroat = 0 ? streq.schmn = 1, repeated for each dma transfer when chcrmn.rroat = 0, trsr.chmn becomes reset after each dma transfer of the dma transaction and a new software request (writing streq.schmn = 1) must be generated for starting the next dma transfer. figure 12-7 software controlled mode operation (m = 0-1) tr0 tr1 trn tc-1 tc = initial transfer count tr0 tr1 0tc 1 0 tc tc-1 mct06155 tr0 tr1 trn tc = initial transfer count 0 tc 0 chcrmn .rroat = 1 chcrmn.rroat = 0 1 tc-1 chsrmn.tcount dma transfer mn trsr.chmn intmn (triggered by tcount = 0) writing streq.schmn = 1 chsrmn.tcount dma transfer mn trsr.chmn intmn (triggered by tcount = 0) writing streq.schmn = 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-13 v1.1, 2011-03 dma, v1.6 hardware-controlled modes in hardware-controlled modes, a hardware req uest signal starts a dma transaction or a single dma transfer. there are two hardware-controlled modes available: ? single mode: hardware requests are disabled by hardware after a dma transaction ? continuous mode: hardware requests are not disabled by hardware after a dma transaction hardware-controlled single mode in hardware-controlled single modes, one hardware request starts one complete dma transaction or one single dma transfer. the hardware-controlled single mode that initiates one complete dma transaction to be executed for dma channel mn is selected by the following operations: ? chcrmn.chmode = 0 ? chcrmn.rroat = 1 ? selecting one of the sixteen hardware request inputs via chcrmn.prsel ? htreq.echmn = 1 setting htreq.echmn to 1 causes the hardware request chmn_req of channel mn to be enabled (trsr.htremn = 1). wh enever the hardware request chmn_req becomes active, the value of chcrmn.trel is loaded into chsrmn.tcount and the dma transaction is started by executing its first dma transfer. after each dma transfer, tcount becomes decremented and next source and destination addresses are calculated. when tcount reaches the 0, dma channel 0n becomes disabled and status flags trsr.chmn and trsr.htremn are reset. in order to start a new hardware-controlled dma transaction, hardware requests must be enabled again by setting trsr.htremn through htreq.echmn = 1. the hardware request disable function in single mode is typically needed when a reprogramming of the dma channel register set (addresses, transfer count) is required before the next hardware triggered dma transaction is started. the hardware-controlled single mode in which each single dma transfer has to be requested by a hardware request signal is selected as described above, with one difference: ? chcrmn.rroat = 0 in this operation mode, trsr.chmn becomes reset after each dma transfer of the dma transaction, and a new hardware request at chmn_req must be generated for starting the next dma transfer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-14 v1.1, 2011-03 dma, v1.6 figure 12-8 hardware-controlled single mode operation (m = 0-1) hardware-controlled continuous mode in hardware-controlled continuous mode (chcrmn.chmode = 1), the hardware transaction request enable bit htremn is not reset at the end of a dma transaction. a new transaction of dma channel mn with the parameters actually stored in the channel register set of dma channel mn is starte d each time when chsrmn.tcount = 0 at the end of the dma transaction. no software re-enable for a hardware request at chmn_req is required. mct06156 tc = initial transfer count tc = initial transfer count chcrmn.rroat = 1 chcrmn.rroat = 0 tr0 tr1 trn tc-1 tr0 tr1 0 tc tc-1 0 1 tc tr0 tc-1 tc tr1 trn-1 trn 0 0 21 tc tr0 trsr.htremn chmn_req int (triggered at the end of a transaction with irdv=0) chsrmn.tcount dma transfer mn trsr.chmn trsr.htremn chmn_req trsr.chmn dma transfer mn chsrmn.tcount int (triggered at the end of a transaction with irdv=0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-15 v1.1, 2011-03 dma, v1.6 combined software/hard ware-controlled mode figure 12-9 shows how software- and hardware-controlled modes can be combined. in the example, the first dma transfer is triggered by software when setting streq.schmn. hardware requests are still disabled. after hardware requests have been enabled by setting htreq.echmn, subs equent dma transfers are triggered now by hardware request coming from the chmn_req line. in the example, dma channel mn operates in single mode (chcrmn.chmode = 0). in this mode, trsr.htremn becomes reset by hardware when chsrmn.tcount = 0 at the end of the dma transaction. figure 12-9 transaction start by software, continuation by hardware (m = 0-1) if a dma channel is configured to be triggered by parallel hardware and software requests then if the requests collide in the same clock cycle then a transaction/transfer request lost event will be flagged in the dma error status register. 12.2.4.4 error conditions the bus error flag errsr.fpier indicates an fpi bus error (spb) that occurred during a source move (read or write) of a dma module transaction. the bus error flag errsr.srier indicates an sri bus error that occurred during a source move (read or write) of a dma module transaction. mct06157 tc = initial transfer count tr0 trn-1 trn tr1 tc-1 tc 0 0 2 1 trsr.chmn writing streq.schmn=1 writing htreq.echmn=1 trsr.htremn chmn_req dma transfer mn chsrmn.tcount int (triggered at the end of a transaction with irdv =0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-16 v1.1, 2011-03 dma, v1.6 the source error flags errsr.memser indicates than an error occurred during source move (read) of a dma transaction of dma sub-block m. the destination error flags errsr.memder indicates than an error occurred during destination move (write) of a dma transaction of dma sub-block m the transaction lost error flag errsr.trlmn indicates if a dma request for a dma channel mn has been lost. in the case of a read error, the write action is not executed, but the destination address is updated. in the case of multiple errors, the error bits are set according to the error situations. this means that more than bus error flag can be set and that source/destination flags can be set. 12.2.4.5 channel reset operation a dma transaction of dma channel mn can be stopped (channel is reset) by setting bit chrstr.chmn. when a read or write on chip bus transaction of dma channel mn is executed at the time when chrstr.ch0n is set, this on chip bus transaction is finished normally. this behavior guarantees data consistency. when chrstr.chmn is set to 1: ? bits trsr.htremn, trsr.chmn, errsr.trlmn, intsr.ichmn, intsr.ipmmn, wrpsr.wrpdmn, wrpsr.wrpsmn, chsrmn.lxo, and bit field chsrmn.tcount are reset. ? source and destination address register will be set to the wrap boundary. shadrmn will be cleared. ? all automatic functions are stopped for channel mn. a user program must execute the following steps for resetting a dma channel: 1. if hardware requests are enabled for the dma channel mn, disable the dma channel mn hardware requests by setting htreq.dchmn = 1. 2. writing a 1 to chrstr.chmn. 3. waiting (polling) until chrstr.chmn = 0. a user program should execute the following steps for restarting a dma channel after it was reset: 1. optionally (re-)configuring the address and other channel registers. 2. restarting the dma channel mn by setting htreq.echmn = 1 for hardware requests or streq.schmn = 1 for software requests. the value of chcrmn.trel is copied to chsrmn.tcount when a new dma transaction is requested and shadow address register contents is not equal 0000 0000 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-17 v1.1, 2011-03 dma, v1.6 12.2.4.6 transfer count and move count the move count determines the number of moves (consisting of one read and one write each) to be done in each transfer. it allows the user to indicate to the dma the number of moves to be done after one request. the number of moves per transfer is selected by the block mode settings (chcrmn.blkm). figure 12-10 transfer and move count (m = 0-1) after a dma move, the next source and dest ination addresses are calculated. source and destination addresses are calculated independently of each other. the following address calculation parameters can be selected: ? the address offset, which is a multiple of the selected data width ? the offset direction: addition, subtraction, or none (unchanged address) control bits in address control register adrcrmn determine how the addresses are incremented/decremented. further, the data width as defined in chcrmn.chdw is taken into account for the address calculation. figure 12-11 and figure 12-12 show two examples of address calculation. in both examples, a data width of 16-bit (chcrmn.chdw = 01b) is assumed. tc-1 1 tc mct06158 chsrmn. tcount dma moves chmn_req 0 0 tc = initial transfer count transfer 0 transaction m1 m2 mx transfer 1 m1 m2 mx transfer n m1 m2 mx www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-18 v1.1, 2011-03 dma, v1.6 figure 12-11 programmable address modification - example 1 (m = 0-1) in figure 12-11 , 16-bit half-words are transferred from a source memory with an incrementing source address offset of 10 h to a destination memory with decrementing destination addresses offset of 08 h . in figure 12-12 , 16-bit half-words are transferred from a source memory with an incrementing source address offset of 02 h to a destination memory with incrementing destination addresses offset of 04 h . mca06159 adrcrmn parameters : smf = 011 b incs = 1 source memory destination memory d1 d0 31 0 15 16 dma moves 00 h d1 .... 31 0 15 16 04 h 08 h 0c h 10 h 14 h 18 h 1c h adrcrmn parameters : dmf = 010 b incd = 0 d0 .... 00 h 04 h 08 h 0c h 10 h 14 h 18 h 1c h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-19 v1.1, 2011-03 dma, v1.6 figure 12-12 programmable address modification - example 2 (m = 0-1) 12.2.4.7 circular buffer destination and source address can be configured to build a circular buffer separately for source and destination data. within this circular buffer, addresses are updated as defined in figure 12-11 and figure 12-12 with a wrap-around at the buffer limits. the circular buffer length is determined by bit fields adrcrmn.cbls (for the source buffer) and adrcrmn.cbld (for the destination buffer). these 4-bit wide bit fields determine which bits of the 32-bit address remain unchanged at an address update. possible buffer sizes of the circular buffers can be 2 cbls or 2 cbld bytes (= 1, 2, 4, 8, 16, ? up to 32k bytes). when source or destination addresses are u pdated (incremented or decremented) after a dma move, all upper bits [31:cbls] of source address and [31:cbld] of destination address are frozen and remain unchanged, even if a wrap-around from the lower address bits [cbls:0] or [cbld:0] occurr ed. this address-freezing mechanism always causes the circular buffers to be aligned to a multiple integer value of its size. if the circular buffer size is less or equal than the selected address offset (see figure 12-9 ), the same circular buffer address will always be accessed. mca06160 adrcrmn parameters : smf = 000 b incs = 1 source memory destination memory 00 h d0 31 0 15 16 dma moves 04 h 08 h 0c h 10 h 14 h 18 h 1c h 00 h d4 31 0 15 16 04 h 08 h 0c h 10 h 14 h 18 h 1c h adrcrmn parameters : dmf = 001 b incd = 1 d6 d1 d2 d3 d4 d5 d6 d7 d7 d5 d3 d1 d2 d0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-20 v1.1, 2011-03 dma, v1.6 12.2.5 transaction control engine each dma sub-block has a transaction cont rol unit. the transact ion control unit in the dma sub-block, as shown in the dma controller block diagram in figure 12-1 , contains a channel arbiter and a move engine. the channel arbiter arbitrates the transfer requests of the dma channels, and submits the transfers parameters of the dma channel with the highest channel priority that are needed for a dma transfer to the move engine. dma channels within a dma sub-block have a two-level programmable channel priority as defined by bit chcrmn.chprio. when two transfer requests of two different dma channels with identical channel priority become active at the same time, the dma channel with the lowest channel number (n) is serviced first. the move engine handles the execution of a dma transfer that has been detected by the channel arbiter to be the next one. the move engine requests the required buses and loads or stores data according to the parameters of a dma transfer. it is able to wait if a targeted bus is not available. in the move engine, a dma transfer of a dma transaction cannot be interrupted and always get finished. this means that a dma transfer, which can also be composed of several data moves (read move and write move), cannot be interrupted by a transfer of another dma channel. after a dma transfer is finished, the move engine will send back the actualized address register information to the related dma channel. possible error conditions are also reported. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-21 v1.1, 2011-03 dma, v1.6 figure 12-13 transaction control engine (m = 0-1) 12.2.6 bus switch, bus switch priorities the bus switch of the dma controller provides the connection from the dma sub-blocks to the two on chip bus master interfaces (connected to system peripheral bus and sri bus) and to the dma peripheral interface (see figure 12-14 ). the fpi bus interface of the dma includes a slave interface which provides the access to the dma and the peripherals connected to the dma peripheral interface (mli, cerberus and memory checker modules). the sri bus interface of the dma is a master interface. the dma module, the dma sub-blocks as well as the mli, the memory checker and the cerberus module working frequencies are identical to the fpi bus frequency. the working frequency of the sri master interface is identical to the sri/cpu working frequency. mca06161 dma ch 00 dma ch 01 dma ch 02 dma ch 03 dma ch 04 dma ch 05 dma ch 06 dma ch 07 dma channel arbiter dma channels 0n of sub-block m move engine m transaction control unit m bus switch www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-22 v1.1, 2011-03 dma, v1.6 figure 12-14 bus switch one access can be buffered in the bus interfaces. note: the accesses of the dm a move engine?s bus interfaces to the on chip bus interfaces are always done in supervisor mode. the arbiter/switch control unit arbitrates the requests from the connected active interfaces (fpi bus interface, dma move engines, mlis, cerberus,...) and grants the buses connected to the switch for data transfers. table 12-1 and table 12-2 define the bus switch priorities for requests to the same on chip bus interface. the arbitration scheme is valid in case of a collision of requests from active peripherals connected to the dma bus switch (move engine, mlis, cerberus) for the same resource (fpi bus interface, sri bus interface, dma peripheral interface, move engine). the arbitration is done for each bus switch request. the general overview of the bus switch priorities is given in table 12-1 . additional detailed information about the move engine priorities for concurrent accesses on the bus switch is described in table 12-2 . in case of a collision of the dma move engi ne requests on the dm a bus switch for the the same resource, a move engine write has priority over a move engine read. in case of a collision of both move engines with concurrent read requests or concurrent write requests for the same resource, the mo ve engine number together with the dma per ipher al inter face mca06162 m sri bus interface buffer m/s fpi bus interface fpi sri arbiter/ switch control move engine m dma sub-block m memory checker mli1 bus switch buffer cerberus mli0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-23 v1.1, 2011-03 dma, v1.6 chcrmn.dmaprio value determines the priority on the dma bus switch (see table 12-2 ). 12.2.7 dma module priorities on on chip busses ( fpi bus, sri bus) every active peripheral connected to the dma bus switch that requests for access to fpi bus or sri bus has to go through two arbitration stages before accessing the on chip table 12-1 dma bus switch priorities priority agent requests comment highest cerberus to on chip bus high priori ty selection by software in cerberus. fpi bus to dma peripheral interface accesses reason: minimizing wait states on the fpi bus. dma move engine write the detailed bus switch priorities for the two engines with concurrent reads or concurrent writes are listed in table 12-2 . dma move engine read the detailed bus switch priorities for the two engines with concurrent reads or concurrent writes are listed in table 12-2 . mli0 access ? mli1 access ? lowest cerberus to on chip bus low priority selection by software in cerberus. table 12-2 dma bus switch priorities of dma move engines priority dma move engine request comment highest lowest move engine 0 chcr0x.dmaprio = ?11? or chcr0x.dmaprio = ?01? (x=7-0). x reflects the channel of move 0 that won the move engine internal arbitration. move engine 1 chcr1y.dmaprio = ?11? or chcr1y.dmaprio = ?01? (y=7-0). y reflects the channel of move 1 that won the move engine internal arbitration. move engine 0 chcr0x.dmaprio = ?00? (x=7-0). x reflects the channel of move 0 that won the move engine internal arbitration. move engine 1 chcr1x.dmaprio = ?00? (y=7-0). y reflects the channel of move 1 that won the move engine internal arbitration. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-24 v1.1, 2011-03 dma, v1.6 bus: dma module internal arbitration at the dma bus switch and dma module external arbitration at the on chip bus. the dma module is connected to the fpi bus and to the sri bus with master interfaces. the dma sri master and the dma fpi master is each connected with three priorities to its on chip bus (low, medium and high priority), where it competes against the other bus masters connected to the on chip bus for bus access. the mapping of the move engines and the peripherals connected to the dma peripheral interface to the dma module priorities on the fpi bus and on the sri bus is described in table 12-3 . the mli modules are mapped to the low priority on chip bus requests of the dma module, while the mapping of the cerberus and the move engines to the on chip bus requests is selected by software (control register bits). the complete list of fpi master priorities can be found in the fpi bus control unit chapter. the complete list of sri master priorities can be found in the shared resource interconnect chapter. 12.2.8 dma module: on chip bus access rights, rmw support all accesses triggered by the dma move engines, the mli modules or the cerberus module are always done in sv mode. the dma module does not support read/modify write instructions to the peripherals connected to the dma peripheral interface (the mli, memory checker and cerberus modules). table 12-3 dma module priorities on on chip busses on chip bus priority dma on chip bu s request comment high cerberus high priority se lection by sw in cerberus. move engine m: chcrmx.dmaprio = ?11? priority selection by sw in move engine. (x=7-0) (m=1-0) medium move engine m: chcrmx.dmaprio = ?01? priority selection by sw in move engine. (x=7-0) (m=1-0) low move engine m: chcrmx.dmaprio = ?00? priority selection by sw in move engine. (x=7-0) (m=1-0) mli0 - mli1 - cerberus low priority select ion by sw in cerberus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-25 v1.1, 2011-03 dma, v1.6 12.2.9 dma module on chip bus master interfaces this chapter describes the features of the dma on chip bus master interfaces to the fpi bus and to the sri bus. the dma fpi master interface supports: ? single data read and write tr ansactions (8bit, 16bit, 32bit) ? generation of pipe lined fpi transaction s from different sources (move engines, cerberus, mlis) ? de-assertion of request after retry in order to prevent bus blocking. ? out of order transactions from different sources in order to avoid side effects (blocking) between the different sources (move engines, cerberus, mlis) ? three dedicated fpi requests (medium, low, high priority. see table 12-3 ) 1) . a single move engine supports only one transaction at a time. due to the fact that the move engines do generate read - write sequ ences, it is unlikely that the dma module generates permanent, pipeline, high priority requests. the dma sri master interface supports: ? single data read and write tr ansactions (8bit, 16bit, 32bit) ? 4-transfer burst transfer (btr4) for read accesses to segment 8 (cached area) ? pipeline transactions from different sources (move engines, cerberus, mlis) ? de-assertion of request after retry in order to prevent bus blocking. ? out of order transactions from different sources in order to avoid side effects (blocking) between the different sources (move engines, cerberus, mlis) ? three dedicated sri requests (medium, low, high priority. see table 12-3 ) 2) . a single move engine supports only one transaction at a time. due to the fact that the move engines do generate read - write sequ ences, it is unlikely that the dma module generates permanent, pipeline, high priority requests. dma sri master read buffer: the dma sri master interface includes a 256bit buffer for read accesses to cached addresses (segment 8). the dma sri master interface contains a data read buffer for read accesses to cached addresses. the read buffer allows to read four double words (=256 bit) of data read from specific memory areas on sri side (segment 8: 8000 0000 h - 8fff ffff h ) a read request to an segment 8 address (8bit, 16bit or 32bit) will be translated by the dma sri master interface into an sri 4-tr ansfer block transfer request. the dma sri master will forward th e requested 8bit, 16bit or 32bit data to the dma bus switch and 1) the complete list of fpi master priorities can be found in the fpi bus control unit chapter. 2) the complete list of sri master priorities can be found in the shared resource interconnect chapter. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-26 v1.1, 2011-03 dma, v1.6 save the 256bit read data together with the related 64bit aligned address in the dma sri master read buffer. if the next and subsequent read access to a segment 8 address is identical (64bit aligned) to the actual read buffer contents, the requested read data will be read from the read buffer by the dma sri master instead of reading it from the sri bus. if the next read to a read from a segment 8 address is not identical (64bit aligned) to the actual read buffer contents, the contents of the read buffer is invalidated. a 4-transfer block transfer request sri read is generated by the dma sri master interface, the requested 8bit, 16bit or 32 bit data is forwarded to the dma bus switch and the read buffer is updated with the new 256bit data and its related address. a dma write to a segment 8 address (8bit, 16bit, 32bit write, 64bit write is not supported) invalidates the read buffer. 12.2.10 dma module bridge functionality the dma module includes bridge functionality: ? from the fpi bus to the dma peripheral interface ? from the dma peripheral interface to the fpi bus and sri bus. fpi bus -> sri bus the dma module does not forward transacti on from the fpi bus to the sri bus. the dma module does not support / include bridge functionality between fpi bus and sri bus. fpi bus -> dma peripheral interface (mli, memory check, cerberus,...) the dma module forwards transactions fr om the fpi bus to the dma peripheral interface (fpi -> mli, memory check, cerberus,...). the identification of the target module on the dma peripheral interface is done by address decoding. dma peripheral interface -> on chip bus (fpi bus, sri bus) the dma module forwards transactions from the active modules that are connected to the dma peripheral interface (cerberus, mli,...) to the fpi bus and sri bus. the identification of the target on chip bus is done by address decoding. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-27 v1.1, 2011-03 dma, v1.6 12.2.11 on-chip de bug capabilities the dma controller in the TC1798 provides some debugging capabilities. these debug features support: ? soft-suspend mode of dma channels ? break signal generation ? trace signal generation in soft-suspend mode, the operations of dma channels are stopped. pending read or write transfers in the dma module on chip bus master interfaces (sri master interface, fpi master interface) are finished. under certain conditions also a break signal is generated for the on-chip debug support logic. further, dma trace information can be output. in soft-suspend mode, the dma module provides access to all control registers of the dma module (inc. move engines and memory checker module) and to the peripherals connected to the dma peripheral interface. 12.2.11.1 hard-suspend mode the hard-suspend mode is controlled in the TC1798 dma module clc register but should not be used in order to guarantee access to the device via jtag (cerberus). possible support of the hard-suspend mode by the peripherals connected to the dma peripheral interface is described in the related module chapters. 12.2.11.2 soft-suspend mode the TC1798 on-chip debug control unit is able to generate a soft-suspend mode request (susreq) for the dma controller. when this soft-suspend request becomes active, the state of a dma channel becomes frozen regarding hardware changes to ensure that the state of the dma channels can be analyzed by reading the register contents. pending read or write transfers in the dma module on chip bus master in terfaces (sri master interface, fpi master interface) are finished. the dma controller signals its soft suspend mode back to the on-chip debug control via an soft-suspend acknowledge. the soft- suspend acknowledge becomes active when all dma channels mn that are enabled for the soft-suspend mode have set its suspend active status flag suspmr.susacmn. soft-suspend mode of dma channel mn is entered if its suspend enable bit susenmn in the suspend mode register suspmr is set. when susreq becomes active, the operation of all dma channels mn that are enabled for soft-suspend mode is stopped automatically after its current dma transfers have been finished in the transaction control unit. afterwards, the suspend active status flag suspmr.susacmn is set, indicating that dma channel mn is in soft-suspend mode. dma channels that are disabled for suspend mode (susenmn = 0) continue with its normal operation. in soft-suspend mode, register contents can be modified. these modifications are taken into account for further dma transactions or dma transfers of the related dma channel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-28 v1.1, 2011-03 dma, v1.6 after suspend mode has been left again. suspend mode of dma channel mn is left and its normal operation continues if either the susreq signal becomes inactive, or if the enable bit susenmn is reset by software. figure 12-15 soft-suspe nd mode control (m = 0-1) 12.2.11.3 break signal generation the dma controller provides one break output signal that is generated for the on-chip debug support logic (see figure 12-16 ). the dma sub-block is able to detect two break conditions: ? transaction lost interrupt has occurred ? dma request transitions, indicated by bits trsr.chmn the output lines of the two break conditions in the dma sub-block are or-ed together to the break output signal. a transaction lost break condition occurs in dma sub-block m whenever at least one of its eight transaction lost interrupts becomes active, and when enable bit ocdsr.brl0 is set. the transaction lost interrupts do not generate a break condition if ocdsr.brl0 = 0. transaction interrupt control is described in section 12.2.12.2 . the second break condition of dma sub-block m becomes active when the transaction request bit trsr.chmn of one of its eight dma channels n (as selected by ocdsr.bchsn) indicates a transition of its state. the chmn transition type (change from no request is pending to request is pending, change from request is pending to no request is pending, changes in both directions) is selected by bit field ocdsr.btcrn. mca06163 soft suspend control transfer request to channel arbiter trsr chmn & susreq susacmn suspmr set susenmn suspmr transaction control unit m (move engine m ) & susack www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-29 v1.1, 2011-03 dma, v1.6 figure 12-16 dma break ev ent generation (m = 0-1) trsr ch01 brea k bchs0 ocdsr trsr ch07 edge detection btcr0 ocdsr & brl0 ocdsr enabled transaction lost interrupts 00- 07 dma sub-block m mca06164 3 2 1 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-30 v1.1, 2011-03 dma, v1.6 12.2.12 interrupts the interrupt structure of the dma controller is a very flexible control logic that allows an interrupt coming from an interrupt source within four interrupt source types to be connected to each of the sixteen interrupt outputs. this permits, for example, dma channels that very rarely generate interrupts to share one interrupt node. the remaining interrupt nodes can be assigned to dedicated dma channels to reduce the interrupt overhead for these channels. the f our interrupt source types are: ? channel interrupts ? transaction lost interrupt ? move engine interrupts ? wrap buffer interrupts some of the interrupt functions are common to all of the four interrupt source types. an interrupt event, internally generated as a request pulse, is always stored in an interrupt status flag. this interrupt status flag can be reset by software. further, the interrupt event can be enabled or disabled. when an interr upt event is enabled, a 4-bit interrupt node pointer determines which of the sixteen interrupt outputs will be activated. the following sections describe each of the four interrupt source types in more detail. 12.2.12.1 channel interrupts each dma channel mn has one associated channel interrupt. it can always be activated after a dma transfer, or when chsrmn.tcount matches with the value of bit field chicrmn.irdv after it has been decremented after a dma transfer. the pattern detection interrupts that are combined with the channel interrupts (one common interrupt node pointer chicrmn.intp) are activated when the pattern detection interrupt of dma channel mn becomes active (when enabled by chcrmn.patsel not equal 00 b ). a channel interrupt of dma channel mn is indicated when status flag intsr.ichmn is set. the status flags ichmn and ipmmn can be reset together by software when setting bit intcr.cichmn (or chrstr.chmn). the channel interrupt of dma channel mn is enabled when bit chicrmn.intct[1] is set. the channel interrupt pointer chicrmn.intp determines which of the interrupt outputs sr[15:0] 1) will be activated on an active channel interrupt or pattern detection interrupt. note that the signal that is set signal for the ichmn flag is availabl e as chmn_out signal at the dma module boundary. bit chicrmn.intct[0] selects these two types of interrupt sources. for the compare operation, bit field irdv (4-bit) is zero-extended to 10-bit and then compared with the 10-bit tcount value. this means that a tcount match interrupt can be generated after one of the last 16 dma transfers of a dma transaction. note that with 1) in the TC1798, only sr[7:0] are connected to in terrupt nodes. sr[8:15] are used for dma channel triggering/connections. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-31 v1.1, 2011-03 dma, v1.6 irdv = 0000 b , the match interrupt is generated at the end of a dma transaction (after the last dma transfer). the pattern detection interrupt is indicated when status flag intsr.ipmmn is set. the status flags ipmmn and ichmn can be reset together by software when setting bit intcr.cichmn (or chrstr.chmn). the pattern detection interrupt of dma channel mn is enabled when bit chcrmn.patsel is set to a value not equal to 00 b . the channel interrupt pointer chic rmn.intp defines which of the in terrupt outputs sr[15:0] will be activated on a pattern detection interrupt or the channel interrupt pointer chicrmn.intp determines which of the interrupt outputs sr[15:0] 1) will be activated on a pattern detection or channel interrupt. figure 12-17 channel interrupts (m = 0-1) 1) in the TC1798, sr[7:0] are connected to in terrupt nodes. sr[8:15] are used for dma channel triggering/connections. 1 mca06165 intp chicrmn intcr ichmn intsr intct[0] m u x 0 1 chicrmn intct[1] chicrmn cichmn set chmn_out patsel chcrmn ipmmn intsr set reset reset chrstr chmn enabled if patsel 00 b 4 n = 0 -7 chsrmn.tcount decremented chsrmn.tcount matches with chicrmn.irdv pattern detection interrupt mn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-32 v1.1, 2011-03 dma, v1.6 12.2.12.2 transaction lost interrupt each dma channel mn is able to detect a transaction request lost condition. this condition becomes true when a new hardware or software dma request occurs while the previous transaction or transfer on dma channel mn is not finished, indicated by trsr.chmn still set. if such a transaction request lost condition occurs, bit errsr.trlmn is set. the transaction lost interrupts of all dma channels are or-ed together to one common transaction lost interrupt that can be directed to one of the interrupt outputs sr[15:0] 1) by setting the transaction lost interrupt pointer eer.trlinp with a corresponding value. a transaction request lost condition of dma channel mn is indicated by status flag errsr.trlmn, which can be reset by setting bit clre.ctlmn or chrstr.chmn. the transaction lost interrupt for dma channel mn is enabled when bit eer.etrlmn is set. figure 12-18 transaction lost interrupt 1) in the TC1798 sr[7:0] are connected to interrupt no des. sr[15:8] are used as dm a channel trigger signals. 1 mca06166 trl00 transaction lost interrupt 00 etrl00 trlinp eer eer clre reset ctl00 eersr trl07 transaction lost interrupt 07 etrl07 eer clre ctl07 eersr n = 0 -7 set chrstr ch00 reset chrstr ch07 set reset 4 reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-33 v1.1, 2011-03 dma, v1.6 12.2.12.3 move engine interrupts the move engine is able to detect error conditions that occur during accesses to the fpi bus and sri bus interfaces of the bus switch (see figure 12-14 ). two error conditions can be detected: ? source error ? destination error a source error indicates an fpi bus or sri bus error that occurred during a read move from the data source. a destination error indicates an fpi bus or sri bus error that occurred during a write move to the data destination. a source error of move engine 0 is indicated by the status flag errsr.me0ser. status flag me0ser can be reset by software when setting bit clre.cme0ser. the source error interrupt of move engine 0 is enabled when bit eer.eme0ser is set. separate reset, status, and enable bits are available in the move engines for source error condition, as well as for destination error condition. the move engine?s interrupts can be directed to one of the interrupt outputs sr[15:0] 1) by setting the move engine interrupt pointer eer.me0inp with a corresponding value. note that in case of a read move error, the write move is not executed but the destination address is updated. figure 12-19 move engine interrupts 1) in the TC1798 sr[7:0] are connected to interrupt no des. sr[15:8] are used as dm a channel trigger signals. mca06167 me0ser move engine 0 source error interrupt eme0ser 1 me0inp eer eer clre reset cme0ser errsr me0der eme0der eer clre reset cme0der errsr move engine 0 destination error interrupt set set 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-34 v1.1, 2011-03 dma, v1.6 when a move engine 0 source or destination error occurs, additional status bits and bit fields are provided in the error status register errsr to indicate the following two status conditions: ? at which on chip bus interface a move engine 0 error occu rred (fpi or sri) ? for which dma channel a move engine 0 read or write move error was reported (lecme0) these error status bits and bit fields are required by error handler software to detect in detail at which on chip bus interface and dma channel the move engine error has been generated. errsr.fpier or errsr.srier is reset when bits clre.cfpi0er or clre.cfpi1er is respectively set. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-35 v1.1, 2011-03 dma, v1.6 12.2.12.4 wrap buffer interrupts each dma channel mn is able to generate a wrap buffer interrupt for source buffer or destination buffer overflow. further details on the pattern detection are described in section 12.2.13 . a wrap source buffer interrupt of dma channel mn is indicated by status flag wrpsr.wrpsmn. a wrap destination buffer interrupt of dma channel mn is indicated by the status flag wrpsr.wrpdmn. both interrupt status flags can be reset by software when bit intcr.cwrpmn (or chrstr.chm n becomes set). the wrap source buffer interrupt is enabled when bit chicrmn.wrpse is set. the wrap destination buffer interrupt is enabled when bit chicrmn.wrpde is set. the two interrupts for wrap source buffer and wrap destination buffer are or-ed together to one common wrap buffer interrupt of dma channel mn that can be directed to one of the interrupt outputs sr[15:0] 1) by setting the wrap buffer interrupt pointer chicrmn.wrpp with a corresponding value. note that the pattern match should not be enabled while a wrap interrupt is enabled for the same channel. figure 12-20 dma wrap buffer interrupts (m = 0-1) 1) in the TC1798 sr[7:0] are connected to interrupt no des. sr[15:8] are used as dm a channel trigger signals. 1 mca06168 wrps0n wrap source buffer interrupt 0n wrpse wrpp chicr0n chicr0n intcr reset cwrp0n wrpsr wrpd0n wrpde chicr0n reset wrpsr wrap destination buffer interrupt 0n n = 0-7 set set chrstr ch0n 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-36 v1.1, 2011-03 dma, v1.6 12.2.12.5 interrupt request compressor the interrupt control logic of the dma controller uses an interrupt compressing scheme that allows high flexibility in interrupt processing. the request compressor logic as shown in figure 12-21 condenses the 8 + 1 + 1 + 8 = 18 interrupt sources to the sixteen interrupt outputs. each internal interrupt source can be directed to one of the sixteen interrupt outputs sr[15:0] 1) by using a 4-bit interrupt node pointer. this also allows the connection of more than one interrupt source to one interrupt output srx. each interrupt output sr[15:0] 1) can also be activated by writing a 1 to the corresponding bit gintr.sidmax. 1) in the TC1798 sr[7:0] are connected to interrupt nodes. sr[15:8] are used as dma channel trigger signals. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-37 v1.1, 2011-03 dma, v1.6 figure 12-21 dma interrupt request compressor (m = 0-1) 12.2.13 pattern detection the move engine in the dma sub-block provides a register me0r that contains the data that was read during the last read move. parts of this read move data can be compared after the read move to data that is stored in the move engine pattern register me0pr of dma sub-block 0. the result of this pattern compare match is always stored in a bit (lxo) of the channel status register of the dma channel mn that is currently executing the dma move. therefore, the pattern match result lxo of the previous read move can also be combined together with the pattern match result of the actual read move. me0r is overwritten with each read move. mca06169 intp chicrmn mem dma channel interrupts (8) & pattern det. interrupts (8) trlinp eer meminp eer move engine m interrupts (1) wrpp chicrmn mem dma channel wrap buffer interrupts (8) interrupt output sr0 to sr1 interrupt output sr15 sidma0 chicrmn sidma15 chicrmn to sr14 mem transaction lost interrupts (1 ) to sr1 to sr14 to sr1 to sr14 to sr1 to sr14 1 1 4 4 4 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-38 v1.1, 2011-03 dma, v1.6 as the compare match patterns are stored in the move engine 0 (register me0pr), its compare patterns are used for all dma channels that are assigned to move engine 0 (all dma channels of the dma sub-block 0. the configuration and capabilities of the pattern detection logic further depends on the settings of chcrmn.chdw. chdw determines the data width for the read and write moves individually for each dma channel mn. another control bit, chcrmn.patsel, selects among the different operating modes for a specific value of chdw. depending on chcrmn.patsel and on the positive result of the comparison, two actions follow (if chcrmn.patsel=00, no action will be taken when a pattern match is detected, so the wrap interrupt can be used): ? the activation of the interrupt corresponding to the current active channel mn using the interrupt pointer defined in chicrmn.intp. ? reset trsr.htremn and trsr.chmn in order to stop the current transaction (hardware and software request enable). the value of chsrmn.tcount can be read out by the interrupt software. the software will have to service the interrupt an d to activate again the channel. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-39 v1.1, 2011-03 dma, v1.6 12.2.13.1 pattern compare logic read move data and compare match patterns are compared on a bit-wise level. the logic as shown in figure 12-22 is implemented in each comp block of figure 12-23 , figure 12-24 , and figure 12-25 . one comp block controls either 8 bits or 16 bits of data and makes it possible to mask each data bit for the compare operation. in the compare logic for one bit of the comp block, a data bit from register me0r is compared to the corresponding pattern bit stor ed in register me0pr. if both bits are equal and a pattern mask bit stored in another part of register me0pr is 0, the compare matched condition becomes active. when the pattern mask bit is set to 1, the compare matched condition is always active (set) for the related bit. when the compare matched conditions for each bit within a comp block are true, the compare match output line of the comp block becomes active. figure 12-22 pattern compare logic (comp block) mca06170 & data from me0pr register mask from me0pr register compare logic for 1 bit compare logics of other bits data from me0r register =1 mask compare match output 1 n n n 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-40 v1.1, 2011-03 dma, v1.6 12.2.13.2 pattern detection for 8-bit data width when 8-bit channel data width is selected (chcrmn.chdw = 00 b ), the pattern detection logic is configured as shown in figure 12-23 . three compare match configurations are possible. when 8-bit channel data width is selected, the pattern detection logic allows the byte of one read move to be compared with two different patterns. further, after each read move the pattern match result ?rd00 with pat01, masked by pat03? is stored in bit chcrmn.lxo. this operating mode allows, fo r example, two-byte sequences to be detected in an 8-bit data stream coming from a serial peripheral unit with 8-bit data width (e.g.: recognition of carriage-return, line-feed characters). a mask operation of each compared bit is possible. figure 12-23 pattern detection for 8-bit data width (chcr mn .chdw = 00 b ) (m = 0- table 12-4 pattern detectio n for 8-bit data width chcr mn . patsel pattern detection operating modes 00 b pattern detection disabled 01 b pattern compare of rd00 to pat00, masked by pat02 10 b pattern compare of rd00 to pat01, masked by pat03 11 b pattern compare of rd00 to pat00, masked by pat02 of the actual read move and pattern compare of rd00 to pat01, masked by pat03 of the previous read move of dma channel mn mca06171 rd0[3] rd0[2] rd0[1] rd0[0] comp 10 2 & patsel chcrxz pattern detected 11 lxo chsrxz mexr mexpr 1) 1) compare result is clocked into lxo after each read move mask mask pat 0[3] pat0 [2] pat 0[0 ] pat0[1] comp 01 00 0 31 7 0 8 0 31 15 16 7 8 23 24 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-41 v1.1, 2011-03 dma, v1.6 1) 12.2.13.3 pattern detection for 16-bit data width when 16-bit channel data width is selected (chcrmn.chdw = 01 b ) the pattern detection logic can be configured as shown in figure 12-24 . three compare match configurations are possible. when 16-bit channel data width is selected, the pattern detection logic makes it possible to compare the complete half-word of one read move only (aligned mode) or to compare upper and lower byte of two consecutive read moves (unaligned modes). both modes can be combined (combined mode) too. a mask operation of each compared bit is possible. in unaligned mode 1 (source address decremented), the high byte (rd01) of the current and the low byte (rd00) of the prev ious 16-bit read move are compared. in unaligned mode 2 (source address incremen ted), the low byte (rd00) of the current and the high byte (rd01) of the previous 16-bit read move are compared. if it is not known on which byte boundary (e ven or odd address) the 16-bit pattern to be detected is located, the combined mode should be used. this mode is the most flexible table 12-5 pattern detection for 16-bit data width chcr mn . patsel adrcr mn . incs pattern detection operating modes 00 b ? pattern detection disabled 01 b ? aligned mode: pattern compare of rd0[1:0] to pat0[1:0], masked by pat0[3:2] 10 b 0 unaligned mode 1 (source address decrement): pattern compare of rd01 to pat00, masked by pat02 of the actual read move and pattern compare of rd00 to pat01, masked by pat03 (lxo) of the previous read move of dma channel mn 1 unaligned mode 2 (source address increment): pattern compare of rd00 to pat01, masked by pat03 of the actual read move and pattern compare of rd01 to pat00, masked by pat02 (lxo) of the previous read move of dma channel mn 11 b 0 or 1 combined mode: pattern compare for aligned mode (patsel = 01 b ) or unaligned modes (patsel = 10 b ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-42 v1.1, 2011-03 dma, v1.6 mode that combines the pattern search capability for aligned and unaligned 16-bit data searches. figure 12-24 pattern detection for 16-bit data width (chcr mn .chdw = 01 b ) (m = 0-1) 2 mca06172 0 pat0[3] pat0[2] pat0[1] pat0[0] 31 & patsel chcrxz pattern detected lxo chsrxz mexpr comp rd 0[3] rd0 [2 ] rd0[1] rd0[0] 31 15 0 16 mexr comp comp 1) this signal is clocked into lxo after each read move 1) incs adrcrxz 1 15 16 23 7 8 24 7 8 23 24 1 mask mask mask 10 11 01 00 0 0 1 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-43 v1.1, 2011-03 dma, v1.6 12.2.13.4 pattern detection for 32-bit data width when 32-bit channel data width is selected (chcrmn.chdw = 10 b ) the pattern detection logic is configured as shown in figure 12-25 . three compare match configurations are possible. in 32-bit channel data width mode, the pattern detection logic makes it possible to compare the lower half-word only, the upper half-word only, or the complete 32-bit word with a pattern stored in the me0pr register. a mask operation is not possible. figure 12-25 pattern detection for 32-bit data width (chcr mn .chdw = 10 b ) (m = 0-1) table 12-6 pattern detection for 32-bit data width chcr mn . patsel pattern detection operating modes 00 b pattern detection disabled 01 b unmasked pattern compare of rd0[1:0] to pat0[1:0] 10 b unmasked pattern compare of rd0[3:2] to pat0[3:2] 11 b unmasked pattern compare of rd0[3:0] to pat0[3:0] mca06173 pat 0[3] pat0 [2] pat0[1] pat 0[0 ] rd0[3] rd0[2] rd0[1] rd0[0] comp comp 2 & patsel chcrxz pattern detected mexr mexpr 0 mask 10 11 01 00 0 0 31 15 16 0 mask 31 0 15 16 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-44 v1.1, 2011-03 dma, v1.6 12.2.14 access protection the dma controller provides an access protection logic that makes it possible to disable read and write accesses of the move engines to specific parts of the memory map. each address of a read move and a write move is always checked to determine if it is within an address range that is enabled for read/write access. if no address range is valid for an actual move address, a move engine interrupt can be generated. accesses outside of specific locations of t he memory map (aen address ra nges) are inva lid and will not be executed by the move engines or mlis and will result in an access protection violation. the access protection logic handles two levels of address range definitions: ? fixed address range ? programmable address range extension there are 32 fixed address ranges available that can be individually enabled/disabled in the move engine by the address range enable bits aenx (x = 0-31): these bits are located in the move engine m access enable registers memaenr0 and memaenr1. if bit aenx is set, read/write accesses to the associated address range x are allowed. if bit aenx is cleared (default after reset), read/write accesses to the associated address range x are not executed and a move engine interrupt for source or destination move is generated (see also section 12.2.12.3 ). additionally eight programmable address range extensions are available for each of the two move engines that are fixed assigned to the program scratch sram, the data scratch sram, the lmu sram and pcp data sram (see also section 12.4.2 ). each programmable address range extension makes it possible to define a sub-range within the corresponding address range where an access will be executed by the corresponding move engine if the address range is not disabled by the corresponding aenx bit. an access to the address range outside the defined sub-range will not be executed by the corresponding move engine. the parameters for the sub-ranges are stored in the move engine m access range registers memarr0 and memarr1. the programmable address range extension is a feature that is applicable for memory access protection of memory blocks. in such an application, several memory sections are defined as sub-ranges of a complete memory block. figure 12-26 shows the two levels of address range definitions with the resulting address sub-ranges of the programmable a ddress range extension. in a fixed address range, the width of fixed and variable address bits is constant. number ?a? determines the lowest bit position of the fixed address, and is fixed individually and product-specific for each of the 32 fixed address ranges. with the programmable address range extension, the variable address part of the fixed address range definition (as defined by aenx) is reduced by the definition of a pr ogrammable number (up to 32) of sub-ranges. bit field memarr0.size/memarr1.size determines the sub-range size and bit field memarr0.slice/memarr1.slice determines which of the sub-ranges is currently www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-45 v1.1, 2011-03 dma, v1.6 selected for access protection control. the two parameters (size, slice) of the eight address range extensions of a move engine are numbered by index ?n? (n = 0-3). in the TC1798 the number ?a? is defined in the following way: ? arr0.size0/arr0.slice0 covering th e program scratch sram, ?a? = 16 ? arr0.size1/arr0.slice1 covering the lmu sram, ?a? = 17 ? arr0.size2/arr0.slice2 covering the data scratch sram, ?a? = 17 ? arr0.size3/arr0.slice3 covering the pcp data sram, ?a? = 16 two sub-range examples (see figure 12-26 ): ?2 3 = 8 sub-ranges are available with size = 100 b . slice[2:0] selects one out of the eight sub-ranges. slice[4:3] is ?don?t care?. ?2 7 = 128 sub-ranges are basically available with sizen = 000 b . slicen[4:0] selects one out of the lowest 32 sub-ranges. the upper 3 x 32 = 96 sub-ranges are not selectable (fixed address bits a-1 and a-2). note: the definition of the fixed address rang es x and the assignment of each sub-range to one of the fixed address ranges is product-specific. the definitions of the address ranges for the dma controller as implemented in the TC1798 are defined on page 12-111 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-46 v1.1, 2011-03 dma, v1.6 figure 12-26 access protection address range definitions 0 0 fixed address 3) 1) 2) fixed address mca06174 31 0 assigned for aenx variable address aa-1 0 variable address a-1 size = 111 b variable address a-2 variable address a-3 0 variable address a-4 0 4) variable address a- 5 0 5) variable address a-6 0 31 a 5) a- 7 0 0 5) variable address a-8 0 fixed address fixed address 31 fixed address 31 fixed address 31 fixed address 31 fixed address 31 fixed address 31 variable address 1) this bit is defined by slice[0] 2) these 2 bits are defined by slice[1:0] 3) these 3 bits are defined by slice[2:0] 4) these 4 bits are defined by slice[3:0] 5) these 5 bits are defined by slice[4:0] fixed address range programmable address range extension size = 110 b size = 101 b size = 100 b size = 011 b size = 010 b size = 001 b size = 000 b 31 0 programmable by slice fixed address bits assigned for aenx x = 0-31 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-47 v1.1, 2011-03 dma, v1.6 12.3 dma module registers figure 12-27 and table 12-8 show all registers associated with the dma controller kernel. additionally, table 12-8 includes the dma module specific registers. all dma kernel register names described in this secti on are also referenced in other parts of the TC1798 users manual by the module name prefix ?dma_?. the registers are numbered by one index to indicate the related dma sub-block and one index to indicate the related dma channel: index ?m? refers to the dma sub-block number (m = 0-1) and index ?n? or ?x? refers to the channel number (n = 0-7 or x = 0-7) within the dma sub-block. dma registers overview figure 12-27 dma kernel registers table 12-7 registers address space - dma module module base address end address note dma f000 3c00 h f000 3eff h mca06175 sadrmn channel control/status registers general control/status registers channel address registers dadrmn chsrmn shadrmn system registers chcrmn chicrmn chrstr trsr streq htreq eer errsr clre mesr adrcrmn memr intsr intcr wrpsr move engine registers mempr ocdsr suspmr memaenr1 gintr memarr1 m = 0-1 memaenr0 memarr0 n = 0-7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-48 v1.1, 2011-03 dma, v1.6 table 12-8 registers overview - dma control registers short name description offset addr. 1) access mode reset class description see read write dma_clc dma clock control register 000 h u, sv sv, e 3 page 12-125 - reserved 004 h nbe sv - - dma_id dma module identification register reserved 008 h u, sv be - page 12-53 - reserved 00c h be be - - dma_chr str dma channel reset request register 010 h u, sv sv 3 page 12-59 dma_trs r dma transaction request state register 014 h u, sv be 3 page 12-60 dma_str eq dma software transaction request register 018 h u, sv sv 3 page 12-62 dma_htr eq dma hardware transaction request register 01c h u, sv sv 3 page 12-63 dma_eer dma enable error register 020 h u, sv sv 3 page 12-65 dma_err sr dma error status register 024 h u, sv be 3 page 12-68 dma_clr e dma clear error register 028 h u, sv sv 3 page 12-71 dma_gin tr dma global interrupt set register 02c h u, sv sv 3 page 12-58 dma_mes r dma move engine status register 030 h u, sv be 3 page 12-78 dma_me0 r dma move engine 0 read register 034 h u, sv be 3 page 12-80 dma_me1 r dma move engine 1 read register 038 h u, sv be 3 page 12-80 dma_me0 pr dma move engine 0 pattern register 03c h u, sv sv 3 page 12-80 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-49 v1.1, 2011-03 dma, v1.6 dma_me1 pr dma move engine 1 pattern register 040 h u, sv sv 3 page 12-80 dma_ me0aenr 0 dma move engine 0 access enable register0 044 h u, sv sv, e 3 page 12-81 dma_me0 arr0 dma move engine 0 access range register0 048 h u, sv sv, e 3 page 12-83 dma_ me1aenr 0 dma move engine 1 access enable register0 04c h u, sv sv, e 3 page 12-81 dma_me1 arr0 dma move engine 1 access range register0 050 h u, sv sv, e 3 page 12-83 dma_ints r dma interrupt status register 054 h u, sv be 3 page 12-73 dma_intc r dma interrupt clear register 058 h u, sv sv 3 page 12-77 dma_wrp sr dma wrap status register 05c h u, sv be 3 page 12-75 - reserved 060 h be be - - dma_ocd sr dma ocds register 064 h u, sv sv, e 1 page 12-54 dma_sus pmr dma suspend mode register 068 h u, sv sv, e 1 page 12-56 dma_me0 aenr1 dma move engine 0 access enable register 1 06c h u, sv sv, e 3 page 12-81 dma_me0 arr1 dma move engine 0 access range register 1 070 h u, sv sv, e 3 page 12-83 dma_me1 aenr1 dma move engine 1 access enable register 1 074 h u, sv sv, e 3 page 12-81 table 12-8 registers overview - dma control registers short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-50 v1.1, 2011-03 dma, v1.6 dma_me1 _arr1 dma move engine 1 access range register 1 078 h u, sv sv, e 3 page 12-83 - reserved 07c h be be dma_chs rmn dma channel mn status register (n = 0-7, m = 0-1) (n x 20 h ) + (m x 10 0 h ) + 080 h u, sv be 3 page 12-89 dma_chc rmn dma channel mn control register (n = 0-7, m = 0-1) (n x 20 h ) + (m x 10 0 h ) + 084 h u, sv sv 3 page 12-85 dma_chi crmn dma channel mn interrupt control register (n = 0-7, m = 0-1) (n x 20 h ) + (m x 10 0 h ) + 088 h u, sv sv 3 page 12-90 dma_ adrcrmn dma channel mn address control register (n = 0-7, m = 0-1) (n x 20 h ) + (m x 10 0 h ) + 08c h u, sv sv 3 page 12-92 dma_sad rmn dma channel mn source address register (n = 0-7, m = 0-1) (n x 20 h ) + (m x 10 0 h ) + 090 h u, sv sv 3 page 12-97 dma_dad rmn dma channel mn destination address register (n = 0-7, m = 0-1) (n x 20 h ) + (m x 10 0 h ) + 094 h u, sv sv 3 page 12-98 table 12-8 registers overview - dma control registers short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-51 v1.1, 2011-03 dma, v1.6 dma_sha drmn dma channel mn shadow address register (n = 0-7, m = 0-1) (n x 20 h ) + (m x 10 0 h ) + 098 h u, sv be / sv 2) 3 page 12-99 - reserved (n = 0-7, m = 0-1) (n x 20 h ) + (m x 10 0 h ) + 09c h be be - - - reserved 280 h - 29c h be be - - dma_ mli0src3 dma mli0 service request control reg. 3 2a0 h u, sv sv 3 page 12-127 dma_ mli0src2 dma mli0 service request control reg. 2 2a4 h u, sv sv 3 page 12-127 dma_ mli0src1 dma mli0 service request control reg. 1 2a8 h u, sv sv 3 page 12-127 dma_ mli0src0 dma mli0 service request control reg. 0 2ac h u, sv sv 3 page 12-127 ? reserved 2b0 h - 2b4 h be be - - dma_ mli1src1 dma mli1 service request control reg. 1 2b8 h u, sv sv 3 page 12-127 dma_ mli1src0 dma mli1 service request control reg. 0 2bc h u, sv sv 3 page 12-127 ? reserved 2c0 h - 2dc h be be 3 page 12-127 table 12-8 registers overview - dma control registers short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-52 v1.1, 2011-03 dma, v1.6 note: register bits marked ?w? in the following register description are virtual registers and do not contain flip-flops. they are always read as 0. dma_ src7 dma service request control register 7 2e0 h u, sv sv 3 page 12-126 dma_ src6 dma service request control register 6 2e4 h u, sv sv 3 page 12-126 dma_ src5 dma service request control register 5 2e8 h u, sv sv 3 page 12-126 dma_ src4 dma service request control register 4 2ec h u, sv sv 3 page 12-126 dma_ src3 dma service request control register 3 2f0 h u, sv sv 3 page 12-126 dma_ src2 dma service request control register 2 2f4 h u, sv sv 3 page 12-126 dma_ src1 dma service request control register 1 2f8 h u, sv sv 3 page 12-126 dma_ src0 dma service request control register 0 2fc h u, sv sv 3 page 12-126 1) the absolute register address is calculated as follows: module base address ( table 12-7 ) + offset address (shown in this column) further, the following ranges for parameters i, k, x, and n are valid: i = 0-7, k = 0-7, x = 0-1, n = 0-63. 2) write access mode to dma_shadrmn is cont rolled by the register bit dma_adrcrmn.shwen. dma_adrcrmn.shwen=0 -> access mode write for dma_shadrmn is be. dma_adrcrmn.shwen=1 -> access mode write for dma_shadrmn is sv. table 12-8 registers overview - dma control registers short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-53 v1.1, 2011-03 dma, v1.6 12.3.1 system registers dma module identification register. the ocds register describes the break c apability of the dma module. ocdsr is only reset with the ocds reset. dma_id module identificat ion register (008 h ) reset value: 001a c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). mod_type [15:8] r module type the bit field is set to c0 h which defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines a module identification number. the value for the dma module is 001a h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-54 v1.1, 2011-03 dma, v1.6 dma_ocdsr dma ocds register (064 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 brl 1 bchs1 btrc1 0 brl 0 bchs0 btrc0 r rw rw rw r rw rw rw field bits type description btrc0 [1:0] rw break trigger condition in sub-block 0 this bit field determines the transition type for the transaction request bit trsr.ch0n that leads to a break condition in dma sub-block 0. 00 b no break condition is generated 01 b a break condition is generated when trsr.ch0n changes from 0 to 1 10 b a break condition is generated when trsr.ch0n changes from 1 to 0 11 b a break condition is generated when trsr.ch0n changes its state bchs0 [4:2] rw break channel select in sub-block 0 this bit field determines the dma channel n of dma sub-block 0 whose transaction request bit trsr.ch0n is observed for signal transitions as defined by btrc0. 000 b dma channel 00 selected 001 b dma channel 01 selected ... b ... 110 b dma channel 06 selected 111 b dma channel 07 selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-55 v1.1, 2011-03 dma, v1.6 brl0 5rw break on request lost in sub-block 0 this bit field determines whether a break signal is generated for dma sub-block 0 when at least one of its eight transaction lost interrupts becomes active. 0 b no break condition is generated 1 b a break condition is generated for dma sub- block 0 when at least one of its eight transaction lost inte rrupts becomes active btrc1 [9:8] rw break trigger condition in sub-block 1 this bit field determines the transition type for the transaction request bit trsr.ch1n that leads to a break condition in dma sub-block 1. 00 b no break condition is generated 01 b a break condition is generated when trsr.ch1n changes from 0 to 1 10 b a break condition is generated when trsr.ch1n changes from 1 to 0 11 b a break condition is generated when trsr.ch1n changes its state bchs1 [12:10] rw break channel select in sub-block 1 this bit field determines the dma channel n of dma sub-block 1 whose transaction request bit trsr.ch1n is observed for signal transitions as defined by btrc1. 000 b dma channel 10 selected 001 b dma channel 11 selected ... b ... 110 b dma channel 16 selected 111 b dma channel 17 selected brl1 13 rw break on request lost in sub-block 1 this bit field determines whether a break signal is generated for dma sub-block 1 when at least one of its eight transaction lost interrupts becomes active. 0 b no break condition is generated 1 b a break condition is generated for dma sub- block 1when at least one of its eight transaction lost inte rrupts becomes active 0 [7:6], [31:14] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-56 v1.1, 2011-03 dma, v1.6 the suspend mode register contains bits for each dma channel that make it possible to enable/disable its soft-suspend mode capability and that indicate its suspend status. dma_suspmr dma suspend mode register (068 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sus ac 17 sus ac 16 sus ac 15 sus ac 14 sus ac 13 sus ac 12 sus ac 11 sus ac 10 sus ac 07 sus ac 06 sus ac 05 sus ac 04 sus ac 03 sus ac 02 sus ac 01 sus ac 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 sus en 17 sus en 16 sus en 15 sus en 14 sus en 13 sus en 12 sus en 11 sus en 10 sus en 07 sus en 06 sus en 05 sus en 04 sus en 03 sus en 02 sus en 01 sus en 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description susen0n (n = 0-7) nrw suspend enable for dma channel 1n this bit enables the soft suspend capability individually for each dma channel 0n. 0 b dma channel 0n is disabled for soft-suspend mode. the dma channel 0n does not react on an active suspend request signal susreq. 1 b dma channel 0n is enabled for soft-suspend mode. if the suspend request signal susreq becomes active, a dma transaction of dma channel 0n is stopped after the current dma transfer has been finished soft-suspend mode can be terminated when susen0n is written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-57 v1.1, 2011-03 dma, v1.6 note: this register is only reset by the debug reset. the global interrupt set register allows the interrupt output lines of the dma to be activated by software. susen1n (n = 0-7) 8+n rw suspend enable for dma channel 1n this bit enables the soft suspend capability individually for each dma channel 1n. 0 b dma channel 1n is disabled for soft-suspend mode. the dma channel 1n does not react on an active suspend request signal susreq 1 b dma channel 1n is enabled for soft-suspend mode. if the suspend request signal susreq becomes active, a dma transaction of dma channel 1n is stopped after the current dma transfer has been finished soft-suspend mode can be terminated when susenmn is written with 0. susac0n (n = 0-7) 16+n rh suspend active for dma channel 0n this status bit indicates whether dma channel 0n is in soft-suspend mode or not. 0 b dma channel 0n is not in soft-suspend mode or internal actions are not yet finished after the soft-suspend mode was requested 1 b dma channel 0n is in soft-suspend mode susac1n (n = 0-7) 24+n rh suspend active for dma channel 1n this status bit indicates whether dma channel 1n is in soft-suspend mode or not. 0 b dma channel 1n is not in soft-suspend mode or internal actions are not yet finished after the soft-suspend mode was requested 1 b dma channel 1n is in soft-suspend mode field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-58 v1.1, 2011-03 dma, v1.6 note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as dma channel request inputs ( page 12-101 ). dma_gintr dma global interrupt set register (02c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 si dma 15 si dma 14 si dma 13 si dma 12 si dma 11 si dma 10 si dma 9 si dma 8 si dma 7 si dma 6 si dma 5 si dma 4 si dma 3 si dma 2 si dma 1 si dma 0 wwwwwwwwwwwwwwww field bits type description sidmax (x = 0-15) xw set dma interrupt output line x 0 b no action 1 b dma interrupt output line srx will be activated. reading this bit returns a 0 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-59 v1.1, 2011-03 dma, v1.6 12.3.2 general contro l/status registers the bits in the channel reset request register are used to reset dma channel mn. dma_chrstr dma channel reset request register (010 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 14131211109876543210 ch 17 ch 16 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 07 ch 06 ch 05 ch 04 ch 03 ch 02 ch 01 ch 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description ch0n (n = 0-7) nrwh channel 0n reset these bits force the dma channel 0n to stop its current dma transaction. once set by software, this bit will be automatically cleared when the channel has been reset. writing a 0 to ch0n has no effect. 0 b no action (write) or the requested channel reset has been reset (read). 1 b dma channel 0n is stopped. more details see page 12-16 . ch1n (n = 0-7) 8+n rwh channel 1n reset these bits force the dma channel 1n to stop its current dma transaction. once set by software, this bit will be automatically cleared when the channel has been reset. writing a 0 to ch1n has no effect. 0 b no action (write) or the requested channel reset has been reset (read). 1 b dma channel 1n is stopped. more details see page 12-16 . 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-60 v1.1, 2011-03 dma, v1.6 the bits in the transaction request state register indicates which dma channel is processing a request, and which dma channel has hardware transaction requests enabled. dma_trsr dma transaction request state register (014 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ht re 17 ht re 16 ht re 15 ht re 14 ht re 13 ht re 12 ht re 11 ht re 10 ht re 07 ht re 06 ht re 05 ht re 04 ht re 03 ht re 02 ht re 01 ht re 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 ch 17 ch 16 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 07 ch 06 ch 05 ch 04 ch 03 ch 02 ch 01 ch 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description ch0n (n = 0-7) nrh transaction request state of dma channel 0n 0 b no dma request is pending for channel 0n. 1 b a dma request is pending for channel 0n. ch1n (n = 0-7) 8+n rh transaction request state of dma channel 1n 0 b no dma request is pending for channel 1n. 1 b a dma request is pending for channel 1n. htre0n (n = 0-7) 16+n rh hardware transaction request enable state of dma channel 0n 0 b hardware transaction request for dma channel 0n is disabled. an input dma request will not trigger the channel 0n. 1 b hardware transaction request for dma channel 0n is enabled. the transfers of a dma transaction are controlled by the corresponding channel request line of the dma requesting source. htre0n is set to 0 when chsr0n.tcount is decremented and chsr0n.tcount = 0. htre0n can be enabled and disabled with htreq.ech0n or htreq.dch0n. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-61 v1.1, 2011-03 dma, v1.6 htre1n (n = 0-7) 24+n rh hardware transaction request enable state of dma channel 1n 0 b hardware transaction request for dma channel 1n is disabled. an input dma request will not trigger the channel 1n. 1 b hardware transaction request for dma channel 1n is enabled. the transfers of a dma transaction are controlled by the corresponding channel request line of the dma requesting source. htre1n is set to 0 when chsr1n.tcount is decremented and chsr1n.tcount = 0. htre1n can be enabled and disabled with htreq.ech1n or htreq.dch1n. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-62 v1.1, 2011-03 dma, v1.6 the bits in the software transaction request register are used to generate a dma transaction request by software. note: register bits marked with ?w? are virtual and are not stored in flip-flops. reading streq returns 0 when read. dma_streq dma software transaction request register (018 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 sch 17 sch 16 sch 15 sch 14 sch 13 sch 12 sch 11 sch 10 sch 07 sch 06 sch 05 sch 04 sch 03 sch 02 sch 01 sch 00 wwwwwwwwwwwwwwww field bits type description sch0n (n = 0-7) nw set transaction request for dma channel 0n 0 b no action. 1 b a transaction for dma channel 0n is requested. when setting sch0n, trsr.ch0n becomes set to indicate that a dma request is pending for dma channel 0n. sch1n (n = 0-7) 8+n w set transaction request for dma channel 1n 0 b no action. 1 b a transaction for dma channel 1n is requested. when setting sch1n, trsr.ch1n becomes set to indicate that a dma request is pending for dma channel 1n. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-63 v1.1, 2011-03 dma, v1.6 the bits in the hardware transaction request register enable or disable dma hardware requests. dma_htreq dma hardware transaction request register (01c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dch 17 dch 16 dch 15 dch 14 dch 13 dch 12 dch 11 dch 10 dch 07 dch 06 dch 05 dch 04 dch 03 dch 02 dch 01 dch 00 wwwwwwwwwwwwwwww 1514131211109876543210 ech 17 ech 16 ech 15 ech 14 ech 13 ech 12 ech 11 ech 10 ech 07 ech 06 ech 05 ech 04 ech 03 ech 02 ech 01 ech 00 wwwwwwwwwwwwwwww field bits type description ech0n (n = 0-7) nw enable hardware transfer request for dma channel 0n see table below ech1n (n = 0-7) 8+n w enable hardware transfer request for dma channel 1n see table below dch0n (n = 0-7) 16+n w disable hardware transfer request for dma channel 0n see table below dch1n (n = 0-7) 24+n w disable hardware transfer request for dma channel 1n see table below table 12-9 conditions to set/ reset the bits trsr.htremn htreq.echmn htreq.dchm n transaction finishes 1) for channel mn modification of trsr.htremn 0 0 0 unchanged 100 set www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-64 v1.1, 2011-03 dma, v1.6 x1x reset xx1 reset 1) in single mode only. in continuous mode, the end of a transaction has no impact. table 12-9 conditions to set/ reset the bits trsr.htremn (cont?d) htreq.echmn htreq.dchm n transaction finishes 1) for channel mn modification of trsr.htremn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-65 v1.1, 2011-03 dma, v1.6 the enable error register describes how the dma controller reacts to errors. it enables the interrupts for the loss of a transaction request or move engine errors. dma_eer dma enable error register (020 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 trlinp me1inp me0inp e me1 der e me1 ser e me0 der e me0 ser rw rw rw rw rw rw rw 1514131211109876543210 e trl 17 e trl 16 e trl 15 e trl 14 e trl 13 e trl 12 e trl 11 e trl 10 e trl 07 e trl 06 e trl 05 e trl 04 e trl 03 e trl 02 e trl 01 e trl 00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description etrl0n (n = 0-7) nrw enable transaction request lost for dma channel 0n this bit enables the generation of an interrupt when the set condition for errsr.trl0n is detected. 0 b the interrupt generation for a request lost event for channel 0n is disabled. 1 b the interrupt generation for a request lost event for channel 0n is enabled. etrl1n (n = 0-7) 8+n rw enable transaction request lost for dma channel 1n this bit enables the generation of an interrupt when the set condition for errsr.trl1n is detected. 0 b the interrupt generation for a request lost event for channel 1n is disabled. 1 b the interrupt generation for a request lost event for channel 1n is enabled. eme0ser 16 rw enable move engi ne 0 source error this bit enables the generation of a move engine 0 source error interrupt. 0 b move engine 0 source error interrupt is disabled. 1 b move engine 0 source error interrupt is enabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-66 v1.1, 2011-03 dma, v1.6 eme0der 17 rw enable move engine 0 destination error this bit enables the generation of a move engine 0 destination error interrupt. 0 b move engine 0 destination error interrupt is disabled. 1 b move engine 0 destination error interrupt is enabled. eme1ser 18 rw enable move engi ne 1 source error this bit enables the generation of a move engine 1 source error interrupt. 0 b move engine 1 source error interrupt is disabled. 1 b move engine 1 source error interrupt is enabled. eme1der 19 rw enable move engine 1 destination error this bit enables the generation of a move engine 0 destination error interrupt. 0 b move engine 1 destination error interrupt is disabled. 1 b move engine 1 destination error interrupt is enabled. me0inp [23:20] rw move engine 0 error in terrupt node pointer me0inp determines the number n (n = 0-15) of the service request output srn that becomes active on a move engine 0 source or destination interrupt. 0000 b sr0 selected for move engine 0 interrupt 0001 b sr1 selected for move engine 0 interrupt ? b ? 1111 b sr15 selected for move engine 0 interrupt note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as dma channel request inputs ( page 12-101 ). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-67 v1.1, 2011-03 dma, v1.6 me1inp [27:24] rw move engine 1 error in terrupt node pointer me1inp determines the number n (n = 0-15) of the service request output srn that becomes active on a move engine 1 source or destination interrupt. 0000 b sr0 selected for move engine 1 interrupt 0001 b sr1 selected for move engine 1 interrupt ? b ? 1111 b sr15 selected for move engine 1 interrupt note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as dma channel request inputs ( page 12-101 ). trlinp [31:28] rw transaction lost inte rrupt node pointer trlinp determines the number n (n = 0-15) of the service request output srn that becomes active on a transaction lost interrupt. 0000 b sr0 selected for transaction lost interrupt 0001 b sr1 selected for transaction lost interrupt ? b ? 1111 b sr15 selected for tran saction lost interrupt note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as dma channel request inputs ( page 12-101 ). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-68 v1.1, 2011-03 dma, v1.6 the error status register indicates if the dma controller could not answer to a request because the previous request was not terminated (see section 12.2.4.4 ). it indicates also the fpi bus accesses that have been terminated with errors. dma_errsr dma error status register (024 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mli 1 lec me1 mli 0 lec me0 0 cer ber use r sri er fpie r me1 der me1 ser me0 der me0 ser rh rh rh rh r rhrhrhrhrhrhrh 1514131211109876543210 trl 17 trl 16 trl 15 trl 14 trl 13 trl 12 trl 11 trl 10 trl 07 trl 06 trl 05 trl 04 trl 03 trl 02 trl 01 trl 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description trl0n (n = 0-7) nrh transaction/transfer request lost of dma channel 0n 0 b 0 no request lost event has been detected for channel 0n. 1 b 1 a new dma request was detected while trsr.ch0n=1 (request lost event). this bit is reset by software when writing a 1 to clre.ctl0n, or by a channel reset (writing chrstr.ch0n = 1). trl1n (n = 0-7) 8+n rh transaction/transfer request lost of dma channel 1n 0 b no request lost event has been detected for channel 1n. 1 b a new dma request was detected while trsr.ch1n=1 (request lost event). this bit is reset by software when writing a 1 to clre.ctl1n, or by a channel reset (writing chrstr.ch1n = 1). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-69 v1.1, 2011-03 dma, v1.6 me0ser 16 rh move engine 0 source error this bit is set whenever a move engine 0 error occurred during a source (read) move of a dma transfer, or a request could not been serviced due to the access protection. 0 b no move engine 0 source error has occurred. 1 b a move engine 0 source error has occurred. me0der 17 rh move engine 0 destination error this bit is set whenever a move engine 0 error occurred during a destination (write) move of a dma transfer, or a request could not been serviced due to the access protection. 0 b no move engine 0 destination error has occurred. 1 b a move engine 0 destination error has occurred. me1ser 18 rh move engine 1 source error this bit is set whenever a move engine 1 error occurred during a source (read) move of a dma transfer, or a request could not been serviced due to the access protection. 0 b no move engine 1 source error has occurred. 1 b a move engine 1 source error has occurred. me1der 19 rh move engine 1 destination error this bit is set whenever a move engine 1 error occurred during a destination (write) move of a dma transfer, or a request could not been serviced due to the access protection. 0 b no move engine 1 destination error has occurred. 1 b a move engine 1 destination error has occurred. fpier 20 rh spb error this bit is set whenever a move that has been started by the dma/mli fpi master interface leads to an error on the fpi bus. 0 b no error occurred. 1 b an error occurred on fpi bus interface. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-70 v1.1, 2011-03 dma, v1.6 srier 21 rh sri error this bit is set whenever a move that has been started by the dma/mli sri master interface leads to an error on the sri bus. 0 b no error occurred. 1 b an error occurred on sri bus interface. cerberu ser 22 rh cerberus error source this bit is set whenever an on chip bus error occurred due to an action of cerberus. 0 b no on chip bus error occurred due to cerberus. 1 b an on chip bus error occurred due to cerberus. lecme0 [26:24] rh last error channel move engine 0 this bit field indicates the channel number of the last channel of move engine 0 leading to an on chip bus error that has occurred. mli0 27 rh mli0 error source this bit is set whenever an on chip bus error occurred due to an action of mli0. 0 b no on chip bus error occurred due to mli0. 1 b an on chip bus error occurred due to mli0. lecme1 [30:28] rh last error channel move engine 1 this bit field indicates the channel number of the last channel of move engine 1 leading to an on chip bus error that has occurred. mli1 31 rh mli1 error source this bit is set whenever an on chip bus error occurred due to an action of mli1. 0 b no on chip bus error occurred due to mli1. 1 b an on chip bus error occurred due to mli1. 0 23 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-71 v1.1, 2011-03 dma, v1.6 the clear error contains bits that make it possible to clear the transaction request lost flags or the move engine error flags. dma_clre dma clear error register (028 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 clr mli 1 0 clr mli 0 0 clc erb eru s c sri er c fpie r c me1 der c me1 ser c me0 der c me0 ser w w w w wwwwwww 1514131211109876543210 ctl 17 ctl 16 ctl 15 ctl 14 ctl 13 ctl 12 ctl 11 ctl 10 ctl 07 ctl 06 ctl 05 ctl 04 ctl 03 ctl 02 ctl 01 ctl 00 wwwwwwwwwwwwwwww field bits type description ctl0n (n = 0-7) nw clear transaction request lost for dma channel 0n 0 b no action 1 b clear dma channel 0n transaction request lost flag errsr.trl0n ctl1n (n = 0-7) n+8 w clear transaction request lost for dma channel 1n 0 b no action 1 b clear dma channel 1n transaction request lost flag errsr.trl1n cme0ser 16 w clear move engine 0 source error 0 b no action 1 b clear source error flag errsr.me0ser. cme0der 17 w clear move engine 0 destination error 0 b no action 1 b clear destination error flag errsr.me0der. cme1ser 18 w clear move engine 1 source error 0 b no action 1 b clear source error flag errsr.me1ser. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-72 v1.1, 2011-03 dma, v1.6 cme1der 19 w clear move engine 1 destination error 0 b no action 1 b clear destination error flag errsr.me1der. cfpier 20 w clear fpi error 0 b no action 1 b clear error flag errsr.fpier. csrier 21 w clear sri error 0 b no action 1 b clear error flag errsr.srier. clcerber us 22 w clear cerberus error 0 b no action 1 b clear error flag errsr.cerberus. clrmli0 27 w clear mli0 error 0 b no action 1 b clear error flag errsr.mli0. clrmli1 31 w clear mli1 error 0 b no action 1 b clear error flag errsr.mli1. 0 [26:23], [30:28] r reserved should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-73 v1.1, 2011-03 dma, v1.6 the interrupt status register indicates if chsrmn.tcount matches with chicrmn.irdv, or if chsrmn.tcount has been decremented (depending on chicrmn.intct[0]),or if a pattern has been detected. these conditions can also generate an interrupt if enabled (see figure 12-17 on page 12-31 ). dma_intsr dma interrupt status register (054 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ipm 17 ipm 16 ipm 15 ipm 14 ipm 13 ipm 12 ipm 11 ipm 10 ipm 07 ipm 06 ipm 05 ipm 04 ipm 03 ipm 02 ipm 01 ipm 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 ich 17 ich 16 ich 15 ich 14 ich 13 ich 12 ich 11 ich 10 ich 07 ich 06 ich 05 ich 04 ich 03 ich 02 ich 01 ich 00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description ich0n (n = 0-7) nrh interrupt from channel 0n this bit indicates that channel 0n has raised an interrupt for tcount = irdv or if tcount has been decremented (depending on chicr.intct[0]. this bit (and ip0n) is reset by software when writing a 1 to intcr.cich0n or by a channel reset (writing chrstr.ch0n = 1). 0 b a channel interrupt has not been detected. 1 b a channel interrupt has been detected. ich1n (n = 0-7) 8+n rh interrupt from channel 1n this bit indicates that channel 1n has raised an interrupt for tcount = irdv or if tcount has been decremented (depending on chicr.intct[0]. this bit (and ip1n) is reset by software when writing a 1 to intcr.cich1n or by a channel reset (writing chrstr.ch1n = 1). 0 b a channel interrupt has not been detected. 1 b a channel interrupt has been detected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-74 v1.1, 2011-03 dma, v1.6 ipm0n (n = 0-7) 16+n rh pattern detection from channel 0n this bit indicates that a pattern has been detected for channel 0n while the pattern detection has been enabled. this bit (and ich0n) is reset by software when writing a 1 to intcr.cich0n or by a channel reset (writing chrstr.ch0n = 1). 0 b a pattern has not been detected. 1 b a pattern has been detected. ipm1n (n = 0-7) 24+n rh pattern detection from channel 1n this bit indicates that a pattern has been detected for channel 1n while the pattern detection has been enabled. this bit (and ich1n) is reset by software when writing a 1 to intcr.cich1n or by a channel reset (writing chrstr.ch1n = 1). 0 b a pattern has not been detected. 1 b a pattern has been detected. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-75 v1.1, 2011-03 dma, v1.6 the wrap status register gives information about the channels that did a wrap-around on their source or destination buffer(s). this condition can also lead to an interrupt if it is enabled. dma_wrpsr dma wrap status register (05c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wrp d17 wrp d16 wrp d15 wrp d14 wrp d13 wrp d12 wrp d11 wrp d10 wrp d07 wrp d06 wrp d05 wrp d04 wrp d03 wrp d02 wrp d01 wrp d00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 wrp s17 wrp s16 wrp s15 wrp s14 wrp s13 wrp s12 wrp s11 wrp s10 wrp s07 wrp s06 wrp s05 wrp s04 wrp s03 wrp s02 wrp s01 wrp s00 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description wrps0n (n = 0-7) nrh wrap source buffer for channel 0n these bits indicate which channels have done a wrap-around of their source buffer(s). 0 b no wrap-around occurred for channel 0n. 1 b a wrap-around occurred for channel 0n. this bit is reset by software by writing a 1 to intcr.cwrp0n or chrstr.ch0n. wrps1n (n = 0-7) 8+n rh wrap source buffer for channel 1n these bits indicate which channels have done a wrap-around of their source buffer(s). 0 b no wrap-around occurred for channel 1n. 1 b a wrap-around occurred for channel 1n. this bit is reset by software by writing a 1 to intcr.cwrp1n or chrstr.ch1n. wrpd0n (n = 0-7) 16+n rh wrap destination buffer for channel 0n these bits indicate which channels have done a wrap-around of their destination buffer(s). 0 b no wrap-around occurred for channel 0n. 1 b a wrap-around occurred for channel 0n. this bit is reset by software by writing a 1 to intcr.cwrp0n or chrstr.ch0n. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-76 v1.1, 2011-03 dma, v1.6 wrpd1n (n = 0-7) 24+n rh wrap destination buffer for channel 1n these bits indicate which channels have done a wrap-around of their destination buffer(s). 0 b no wrap-around occurred for channel 1n. 1 b a wrap-around occurred for channel 1n. this bit is reset by software by writing a 1 to intcr.cwrp1n or chrstr.ch1n. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-77 v1.1, 2011-03 dma, v1.6 the bits in the interrupt clear register make it possible to reset the channel interrupt flags and the wrap buffer interrupt flags for dma channels mn. dma_intcr dma interrupt cl ear register (058 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 c wrp 17 c wrp 16 c wrp 15 c wrp 14 c wrp 13 c wrp 12 c wrp 11 c wrp 10 c wrp 07 c wrp 06 c wrp 05 c wrp 04 c wrp 03 c wrp 02 c wrp 01 c wrp 00 wwwwwwwwwwwwwwww 1514131211109876543210 c ich 17 c ich 16 c ich 15 c ich 14 c ich 13 c ich 12 c ich 11 c ich 10 c ich 07 c ich 06 c ich 05 c ich 04 c ich 03 c ich 02 c ich 01 c ich 00 wwwwwwwwwwwwwwww field bits type description cich0n (n = 0-7) nw clear interrupt fo r dma channel 0n these bits make it possible to reset the channel interrupt flags intsr.ich0n and intsr.ipm0n of dma channel 0n by software. 0 b no action. 1 b bits intsr.ich0n and intsr.ipm0n are reset. cich1n (n = 0-7) 8+n w clear interrupt fo r dma channel 1n these bits make it possible to reset the channel interrupt flags intsr.ich1n and intsr.ipm1n of dma channel 1n by software. 0 b no action. 1 b bits intsr.ich1n and intsr.ipm1n are reset. cwrp0n (n = 0-7) 16+n w clear wrap buffer interrupt for dma channel 0n these bits make it possible to reset the wrap source buffer interrupt flag wrpsr.wrps0n and the wrap destination buffer interrupt flag wrpsr.wrpd0n (both together) of dma channel 0n by software. 0 b no action. 1 b bits wrpsr.wrps0n and wrpsr.wrpd0n are reset. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-78 v1.1, 2011-03 dma, v1.6 12.3.3 move engine registers the move engine status register is a read-on ly register that holds status information about the transaction handled by the move engines. cwrp1n (n = 0-7) 24+n w clear wrap buffer interrupt for dma channel 1n these bits make it possible to reset the wrap source buffer interrupt flag wrpsr.wrps1n and the wrap destination buffer interrupt flag wrpsr.wrpd1n (both together) of dma channel 1n by software. 0 b no action. 1 b bits wrpsr.wrps1n and wrpsr.wrpd1n are reset. dma_mesr dma move engine status register (030 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 rbtsri me1 ws ch1 me1 rs rbtfpi me0 ws ch0 me0 rs rh rh rh rh rh rh rh rh field bits type description me0rs 0rh move engine 0 read status 0 b move engine 0 is not performing a read. 1 b move engine 0 is performing a read. ch0 [3:1] rh reading channel in move engine 0 this bit field indicates which channel number is currently being processed by the move engine 0. me0ws 4rh move engine 0 write status 0 b move engine 0 is not performing a write. 1 b move engine 0 is performing a write. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-79 v1.1, 2011-03 dma, v1.6 rbtfpi [7:5] rh read buffer trace for fpi bus interface this bit field contains trace information from the buffer in the fpi bus interface. in the TC1798 it indicates the source of a bus access to the fpi bus. 000 b default value. 001 b dma move engine 0 010 b dma move engine 1 011 b mli0 100 b mli1 101 b cerberus other bit combinations are reserved. rbtfpi is useful for emulation purposes. it is not recommended to evaluate this bit field during normal operation of the TC1798. me1rs 8rh move engine 1 read status 0 b move engine 1 is not performing a read. 1 b move engine 1 is performing a read. ch1 [11:9] rh reading channel in move engine 1 these bit field indicates which channel number is currently being processed by the move engine 1. me1ws 12 rh move engine 1 write status 0 b move engine 1 is not performing a write. 1 b move engine 1 is performing a write. rbtsri [15:13] rh read buffer trace for sri bus interface this bit field contains trace information from the buffer in the sri bus interface. in the TC1798, it indicates the source of a bu s access to the sri bus. 000 b default value 001 b dma move engine 0 010 b dma move engine 1 011 b mli0 100 b mli1 101 b cerberus other bit combinations are reserved. rbtsri is useful for emulation purposes. it is not recommended to evaluate this bit field during normal operation of the TC1798. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-80 v1.1, 2011-03 dma, v1.6 the move engine 0 read register indicates the value that has just been read by move engine 0. the value in this register is compared to the bits in register me0pr according to the bit fields chcrmn.patsel. the move engine 0 pattern register contains the patterns (mask and/or compare bits) to be processed by the pattern detection logic in move engine 0. dma_me0r dma move engine 0 read register (034 h ) reset value: 0000 0000 h dma_me1r dma move engine 1 read register (038 h ) reset value: 0000 0000 h 31 24 23 16 15 8 7 0 rd03 rd02 rd01 rd00 rh rh rh rh field bits type description rd00, rd01, rd02, rd03 [7:0], [15:8], [23:16], [31:24] rh read value for move engine 0 contains the 32-bit read data (four bytes rd0[3:0]) that is stored in the move engine 0 after each read move. the content of me0r is overwritten after each read move of a dma channel belonging to dma sub- block 0. dma_me0pr dma move engine 0 pattern register (03c h ) reset value: 0000 0000 h dma_me1pr dma move engine 1p attern register (040 h ) reset value: 0000 0000 h 31 24 23 16 15 8 7 0 pat03 pat02 pat01 pat00 rw rw rw rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-81 v1.1, 2011-03 dma, v1.6 the dma move engine 0 access enable register controls the access protection. it enables/disables the address protection r anges x (x = 0-31) for move engine 0. field bits type description pat00, pat01, pat02, pat03 [7:0], [15:8], [23:16], [31:24] rw pattern for move engine 0 determines up to four 8-bit compare patterns/mask patterns to be processed by the pattern detection logic in move engine 0. depending on the pattern detection configuration (chcr0n.patsel) and channel data width (chcr0n.chdw), the patterns are processed as bytes or half-words. dma_me0aenr0 dma move engine 0 access enable register 0 (044 h ) reset value: 0000 0000 h dma_me1aenr0 dma move engine 1 access enable register 0 (04c h ) reset value: 0000 0000 h dma_me0aenr1 dma move engine 0 access enable register 1 (06c h ) reset value: 0000 0000 h dma_me1aenr1 dma move engine 1 access enable register 1 (074 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 aen 31 aen 30 aen 29 aen 28 aen 27 aen 26 aen 25 aen 24 aen 23 aen 22 aen 21 aen 20 aen 19 aen 18 aen 17 aen 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 aen 15 aen 14 aen 13 aen 12 aen 11 aen 10 aen 9 aen 8 aen 7 aen 6 aen 5 aen 4 aen 3 aen 2 aen 1 aen 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-82 v1.1, 2011-03 dma, v1.6 note: see table 12-13 on page 12-111 for the TC1798-specific address range definition. field bits type description aenx (x = 0-31) xrw address range x enable this bit enables the read and write capability of the dma move engines for address range x (x = 0-31). 0 b dma read and write moves to address range x are disabled 1 b dma read and write moves to address range x are enabled if aenx = 0 for a read/write move to address range x, the read/write move is not executed and a source/destination move engine interrupt is generated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-83 v1.1, 2011-03 dma, v1.6 the dma move engine 0 access range register determines number and size of the sub-ranges for address range extension n (n = 0-3). see also figure 12-26 for bit field definitions. dma_me0arr0 dma move engine 0 access range register 0 (048 h ) reset value: 0000 0000 h dma_me1arr0 dma move engine 1 access range register 0 (050 h ) reset value: 0000 0000 h dma_me0arr1 dma move engine 0 access range register 1 (070 h ) reset value: 0000 0000 h dma_me1arr1 dma move engine 1 access range register 1 (078 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 size3 slice3 size2 slice2 rw rw rw rw 1514131211109876543210 size1 slice1 size0 slice0 rw rw rw rw field bits type description slice0 [4:0] rw address slice 0 slice0 selects a specific sub-range within address range extension 0. size0 [7:5] rw address size 0 size0 determines the sub-range size within address range extension 0. slice1 [12:8] rw address slice 1 slice1 selects a specific sub-range within address range extension 1. size1 [15:13] rw address size 1 size1 determines the sub-range size within address range extension 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-84 v1.1, 2011-03 dma, v1.6 note: see section 12.4.2 on page 12-111 for the TC1798-specific address range and address range extension definitions. slice2 [20:16] rw address slice 2 slice2 selects a specific sub-range within address range extension 2. size2 [23:21] rw address size 2 size2 determines the sub-range size within address range extension 2. slice3 [28:24] rw address slice 3 slice3 selects a specific sub-range within address range extension 3. size3 [31:29] rw address size 3 size3 determines the sub-range size within address range extension 3. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-85 v1.1, 2011-03 dma, v1.6 12.3.4 channel control/status registers the channel control register for dma channel mn contains its configuration and its control bits and bit fields. dma_chcr0x (x = 0-7) dma channel 0x control register (084 h +x*20 h ) reset value: 0000 0000 h dma_chcr1x (x = 0-7) dma channel 1x control register (184 h +x*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dma prio 0 ch prio 0 patsel 0 chdw ch mo de rro at blkm rw r rw r rw r rw rw rw rw 1514131211109876543210 prsel 0 trel rw r rw field bits type description trel [9:0] rw transfer reload value this bit field contains the number of dma transfers for a dma transaction of dma channel mn. this10-bit transfer count value is loaded into chsrmn.tcount at the start of a dma transaction (when trsr.chmn becomes set and chsrmn.tcount = 0). a write to chsrmn.trel during a running dma transaction has no influence to the running dma transaction. if chsrmn.trel = 0 or if chsrmn.trel = 1, chsrmn.tcount will be loaded with 1 when a new transaction is started (at least one dma transfer must be executed per dma transaction). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-86 v1.1, 2011-03 dma, v1.6 prsel [15:12] rw peripheral request select this bit field controls the hardware request input multiplexer of dma channel mn (see figure 12-6 on page 12-10 ). 0000 b input chmn_reqi0 selected 0001 b input chmn_reqi1 selected 0010 b input chmn_reqi2 selected 0011 b input chmn_reqi3 selected 0100 b input chmn_reqi4 selected 0101 b input chmn_reqi5 selected 0110 b input chmn_reqi6 selected 0111 b input chmn_reqi7 selected 1000 b input chmn_reqi8 selected 1001 b input chmn_reqi9 selected 1010 b input chmn_reqi10 selected 1011 b input chmn_reqi11 selected 1100 b input chmn_reqi12 selected 1101 b input chmn_reqi13 selected 1110 b input chmn_reqi14 selected 1111 b input chmn_reqi15 selected blkm [18:16] rw block mode blkm determines the number of dma moves executed during one dma transfer. 000 b one dma transfer has 1 dma move 001 b one dma transfer has 2 dma move 010 b one dma transfer has 4 dma move 011 b one dma transfer has 8 dma move 100 b one dma transfer has 16 dma move other bit combinations are reserved and must not be used. see also figure 12-10 on page 12-17 . rroat 19 rw reset request only after transaction rroat determines whether or not the trsr.chmn transfer request state flag is reset after each transfer. 0 b trsr.chmn is reset after each transfer. a transfer request is required for each transfer. 1 b trsr.chmn is reset when chsrmn.tcount = 0 after a transfer. one transfer request starts a complete dma transaction field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-87 v1.1, 2011-03 dma, v1.6 chmode 20 rw channel operation mode chmode determines the reset condition for control bit trsr.htremn of dma channel mn. 0 b single mode operation is selected for dma channel mn. after a transaction, dma channel mn is disabled for further hardware requests (trsr.htremn is reset by hardware) trsr.htremn must be set again by software for starting a new transaction. 1 b continuous mode operation is selected for dma channel mn. after a transaction, bit trsr.htremn remains set chdw [22:21] rw channel data width chdw determines the data width for the read and write moves of dma channel mn. 00 b 8-bit (byte) data width for moves selected 01 b 16-bit (half-word) data width for moves selected 10 b 32-bit (word) data width for moves selected 11 b reserved patsel [25:24] rw pattern select this bit field selects the mode of the pattern detection logic. depending on the channel data width, patsel selects different pattern detection configurations. if pattern detection is enabled (patsel not equal 00 b ), the pattern detection interrupt line will be activated on the selected pattern match. 8-bit channel data width (chdw = 00 b ): selected pattern detection configuration see table 12-4 on page 12-40 . 16-bit channel data width (chdw = 01 b ): selected pattern detection configuration see table 12-5 on page 12-41 . 32-bit channel data width (chdw = 10 b ): selected pattern detection configuration see table 12-6 on page 12-43 . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-88 v1.1, 2011-03 dma, v1.6 chprio 28 rw channel priority chprio determines the priority of dma channel n for the move engine m internal channel arbitration. this priority is used for the case when multiple channels of move engine m are triggered in parallel. 0 b dma channel mn has a low channel priority 1 b dma channel mn has a high channel priority dmaprio [31:30] rw dma priority this bit determines the dma the request priority that is used when a move operation related to channel mn is requesting an on chip bus. this bit has no effect in channel prioritization inside the move engine m in. 00 b low priority selected 01 b medium priority selected 10 b reserved 11 b high priority selected 0 [11:10], 23, [27:26], 29 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-89 v1.1, 2011-03 dma, v1.6 the channel status register contains the current transfer count and a pattern detection compare result. dma_chsr0x (x = 0-7) dma channel 0x status register (080 h +x*20 h ) reset value: 0000 0000 h dma_chsr1x (x = 0-7) dma channel 1x status register (180 h +x*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 lxo 0 tcount rh r rh field bits type description tcount [9:0] rh transfer count status tcount holds the actual value of the dma transfer count for dma channel mx. tcount is loaded with the value of chcrmx.trel when trsr.chmx becomes set (and tcount = 0). after each dma transfer, tcount is decremented by 1. lxo 15 rh old value of pattern detection this bit contains the compare result of a pattern compare operation when 8-bit or 16-bit data width is selected. 8-bit data width: see table 12-4 and figure 12-23 16-bit data width: see table 12-5 and figure 12-24 0 b the corresponding pattern compare operation did not find a pattern match on the last move 1 b the corresponding pattern compare operation found a pattern match at the last move 0 [14:10], [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-90 v1.1, 2011-03 dma, v1.6 the channel interrupt control register controls the interrupts generation. dma_chicr0x (x = 0-7) dma channel 0x interru pt control register (088 h +x*20 h ) reset value: 0000 0000 h dma_chicr1x (x = 0-7) dma channel 1x interru pt control register (188 h +x*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 irdv intp wrpp intct wrp de wrp se rw rw rw rw rw rw field bits type description wrpse 0rw wrap source enable 0 b wrap source buffer interrupt disabled 1 b wrap source buffer interrupt enabled wrpde 1rw wrap destination enable 0 b wrap destination buffer interrupt disabled 1 b wrap destination buffer interrupt enabled intct [3:2] rw interrupt control 00 b no interrupt w ill be generated on changing the tcount value. the bit intsr.ichmx is set when tcount equals irdv. 01 b no interrupt w ill be generated on changing the tcount value. the bit intsr.ichmx is set when tcount is decremented 10 b an interrupt is generated and bit intsr.ichmx is set each time tcount equals irdv 11 b interrupt is generated and bit intsr.ichmx is set each time tcount is decremented note: see figure 12-17 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-91 v1.1, 2011-03 dma, v1.6 note: the interrupt node of the wrap-around in terrupts is shared with the pattern match interrupt. in order to support interrupt generation in case of a pattern match, the wrap-around interrupt should be disabled. if the wrap-around interrupts are used, the pattern match interrupt should not be used. the settings are independent for each dma channel. wrpp [7:4] rw wrap pointer wrpp determines the number n (n = 0-15) of the service request output srn that becomes active on a wrap buffer interrupt. 0000 b sr0 selected for channel mx wrap buffer interrupt 0001 b sr1 selected for channel mx wrap buffer interrupt ? b ? 1111 b sr15 selected for channel mx wrap buffer interrupt note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as dma channel request inputs ( page 12-101 ). intp [11:8] rw interrupt pointer intp determines the number n (n = 0-15) of the service request output srn that becomes active on a channel interrupt. 0000 b sr0 selected for channel mx interrupt 0001 b sr1 selected for channel mx interrupt ? b ? 1111 b sr15 selected for channel mx interrupt note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as dma channel request inputs ( page 12-101 ). irdv [15:12] rw interrupt raise detect value these bits specify the value of chsrmx.tcount for which the interrupt threshold limit should be raised. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-92 v1.1, 2011-03 dma, v1.6 the address control register controls how source and destination addresses are updated after a dma move. furthermore, it determines whether or not a source or destination address register update is shadowed. dma_adrcr0x (x = 0-7) dma channel 0x address control register (08c h +x*20 h ) reset value: 0000 0000 h dma_adrcr1x (x = 0-7) dma channel 1x address control register (18c h +x*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 shw en shct rrwrw 1514131211109876543210 cbld cbls incd dmf incs smf rw rw rw rw rw rw field bits type description smf [2:0] rw source address modification factor this bit field and the data width as defined in chcrmx.chdw determine an address offset value by which the source address is modified after each dma move. see also table 12-10 . 000 b address offset is 1 x chcrmx.chdw 001 b address offset is 2 x chcrmx.chdw 010 b address offset is 4 x chcrmx.chdw 011 b address offset is 8 x chcrmx.chdw 100 b address offset is 16 x chcrmx.chdw 101 b address offset is 32 x chcrmx.chdw 110 b address offset is 64 x chcrmx.chdw 111 b address offset is 128 x chcrmx.chdw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-93 v1.1, 2011-03 dma, v1.6 incs 3rw increment of source address this bit determines whether the address offset as selected by smf will be added to or subtracted from the source address after each dma move. the source address is not modified if cbls = 0000 b . 0 b address offset will be subtracted 1 b address offset will be added. dmf [6:4] rw destination address modification factor this bit field and the data width as defined in chcrmx.chdw determines an address offset value by which the destination address is modified after each dma move. the destination address is not modified if cbld = 0000 b . see also table 12-10 . 000 b address offset is 1 x chdw 001 b address offset is 2 x chdw 010 b address offset is 4 x chdw 011 b address offset is 8 x chdw 100 b address offset is 16 x chdw 101 b address offset is 32 x chdw 110 b address offset is 64 x chdw 111 b address offset is 128 x chdw incd 7rw increment of destination address this bit determines whether the address offset as selected by dmf will be added to or subtracted from the destination address after each dma move. the destination address is not modified if cbld = 0000 b . 0 b address offset will be subtracted 1 b address offset will be added field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-94 v1.1, 2011-03 dma, v1.6 cbls [11:8] rw circular buffer length source this bit field determines which part of the 32-bit source address register remains unchanged and is not updated after a dma move operation (see also section 12.2.4.7 ). therefore, cbls also determines the size of the circular source buffer. 0000 b source address sadr[31:0] is not updated 0001 b source address sadr[31:1] is not updated 0010 b source address sadr[31:2] is not updated 0011 b source address sadr[31:3] is not updated ... b ... 1110 b source address sadr[31:14] is not updated 1111 b source address sadr[31:15] is not updated cbld [15:12] rw circular buffer length destination this bit field determines which part of the 32-bit destination address register remains unchanged and is not updated after a dma move operation (see also page 12-19 ). therefore, cbld also determines the size of the circular destination buffer. 0000 b destination address dadr[31:0] is not updated 0001 b destination address dadr[31:1] is not updated 0010 b destination address dadr[31:2] is not updated 0011 b destination address dadr[31:3] is not updated ... b ... 1110 b destination address dadr[31:14] is not updated 1111 b destination address dadr[31:15] is not updated field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-95 v1.1, 2011-03 dma, v1.6 shct [17:16] rw shadow control this bit field determines whether an address is transferred into the shadow address register when writing to source or destination address register. 00 b shadow address register not used. source and destination address register are written directly 01 b shadow address register used for source address buffering. when writing to sadrmx, the address is buffered in shadrmx and transferred to sadrmx with the start of the next dma transaction 10 b shadow address register used for destination address buffering. when writing to dadrmx, the address is buffered in shadrmx and transferred to dadrmx with the start of the next dma transaction 11 b reserved in case of shct = 01 b or 10 b , shct must not be changed until the next dma transaction has been started. shwen 18 rw shadow address register write enable this bit determines whether the shadow address register shadrmx is read only and automatically set to 0000 0000 h or if the shadow register can also be directly written and not modified when and shadow transfer takes place. 0 b shadow address register is read only and the value stored in the shadrmx is automatically set to 0000 0000 h when the shadow transfer takes place 1 b shadow address register shadrmx can be read and can be directly written. the value stored in the shadrmx is not automatically modified when the shadow transfer takes place 0 [31:19] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-96 v1.1, 2011-03 dma, v1.6 table 12-10 shows the offset values that are added or subtracted to/from a source or destination address register after a dma move. bit field smf and bit incs determine the offset value for the source address. bit field dmf and bit incd determine the offset value for the destination address. note: chcr mn .chdw = 11 b is reserved and should not be used. table 12-10 address offset calculation table chcr mn .chdw = 00 b (8-bit data width) chcr mn .chdw = 01 b (16-bit data width) chcr mn .chdw = 10 b (32-bit data width) smf dmf incs incd address offset smf dmf incs incd address offset smf dmf incs incd address offset 000 b 0-1 000 b 0-2 000 b 0-4 1+1 1+2 1+4 001 b 0-2 001 b 0-4 001 b 0-8 1+2 1+4 1+8 010 b 0-4 010 b 0-8 010 b 0-16 1+4 1+8 1+16 011 b 0-8 011 b 0-16 011 b 0-32 1 +8 1 +16 1 +32 100 b 0 -16 100 b 0-32 100 b 0-64 1 +16 1 +32 1 +64 101 b 0 -32 101 b 0-64 101 b 0-128 1 +32 1 +64 1 +128 110 b 0 -64 110 b 0 -128 110 b 0-256 1 +64 1 +128 1 +256 111 b 0-128111 b 0 -256 111 b 0-512 1 +128 1 +256 1 +512 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-97 v1.1, 2011-03 dma, v1.6 12.3.5 channel address registers the source address register contains the 32-bit source address. if a dma channel mn is active, sadrmn is updated continuously (if programmed) and shows the actual source address that is used for read moves within dma transfers. a write to sadrmn is executed directly only when the dma channel mn is inactive (chsrmn.tcount = 0 and trsr.chmn = 0). if dma channel mn is active when writing to sadrmn, the source address will not be written into sadrmn directly but will be buffered in the shadow register shadrmn until the start of the next dma transaction. during this shadowed address register operation, bit field adrcrmn.shct must be set to 01 b . dma_sadr0x (x = 0-7) dma channel 0x source address register (090 h +x*20 h ) reset value: 0000 0000 h dma_sadr1x (x = 0-7) dma channel 1x source address register (190 h +x*20 h ) reset value: 0000 0000 h 31 0 sadr rwh field bits type description sadr [31:0] rwh source start address this bit field holds the actual 32-bit source address of dma channel mx that is used for read moves. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-98 v1.1, 2011-03 dma, v1.6 the destination address register contains the 32-bit destination address. if a dma channel is active, dadrmn is updated continuously (if programmed) and shows the actual destination address that is used for write moves within dma transfers. a write to dadrmn is executed directly only when the dma channel mn is inactive (chsrmn.tcount = 0 and trsr.chmn = 0). if dma channel mn is active when writing to dadrmn, the source address will not be written into dadrmn directly but will be buffered in the shadow register shadrmn until the start of the next dma transaction. during this shadowed address register operation, bit field adrcrmn.shct must be set to 10 b . dma_dadr0x (x = 0-7) dma channel 0x destination address register (094 h +x*20 h ) reset value: 0000 0000 h dma_dadr1x (x = 0-7) dma channel 1x destination address register (194 h +x*20 h ) reset value: 0000 0000 h 31 0 dadr rwh field bits type description dadr [31:0] rwh destination address this bit field holds the actual 32-bit destination address of dma channel mx that is used for write moves. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-99 v1.1, 2011-03 dma, v1.6 the shadow address register holds the shadowed source or destination address before it is written into the source or destination address register. shadrmn can be read only. shadrmn is written when source or des tination address buffering is selected (adrcrmn.shct = 01 b or adrcrmn.shct = 10 b ) and a transaction is running. while the shadow mechanism is disabled, shadr is set to 0000 0000 h . if adrcrmn.shwen = 0 the value stored in the shadr is automatically set to 0000 0000 h when the shadow transfer takes place. the user can read the shadow register in order to detect if the shadow tran sfer has already taken place. if the value in shadr is 0000 0000 h , no shadow transfer can take place and the corresponding address register is modified according to the circular buffer rules. if adrcrmn.shwen = 1 shadow register shadrm n can be directly written. the value stored in the shadrmn is not modified when the shadow transfer takes place, the shadow mechanism remains active and the shadow transfer will be repeated until channel mn is reset or until the value in shadr is 0000 0000 h , is written into the shadow register. dma_shadr0x (x = 0-7) dma channel 0x shadow address register (098 h +x*20 h ) reset value: 0000 0000 h dma_shadr1x (x = 0-7) dma channel 1x shadow address register (198 h +x*20 h ) reset value: 0000 0000 h 31 0 shadr rwh field bits type description shadr [31:0] rwh shadowed address this bit field holds the shadowed 32-bit source or destination address of dma channel mx. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-100 v1.1, 2011-03 dma, v1.6 12.4 dma module implementation this section describes the TC1798 dma module interfaces with the clock control, interrupt control, and address decoding. chapter 12-28 shows the TC1798-specific implementation details and interconnections of the dma module. the dma module is supp lied with a separate clock control, address decoding, interrupt control, and the request input wiring matrix. figure 12-28 dma module implementation and interconnections the request sources of the peripheral modules (adc0, msc0, mli0/1, fadc, multican, and scu) are associated with interrupt node pointers and individual interrupt enable bits. as a result, each of the internal requests of a module can be routed independently to any of the interrupt output lines (int_ox) of the module. dma interrupt nodes mca06176 clock control f dma sr[7:0] dma controller arbiter/ switch control bus switch fpi bus in terfa ce sri bus interface dma peripher al interface memory checker mli 0 mli 1 system peripheral bus sri bus address decoder dma interrupt control ch0n_out mli interrupt nodes dma channels 00-07 dma sub-block m request selection / arbitration transaction control unitl 4 2 dma requests of on-chip periph . units cerberus www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-101 v1.1, 2011-03 dma, v1.6 12.4.1 dma request wiring matrix the dma request input lines of each dma channel within dma sub-block 0 and dma sub-block 1 are connected to request ou tput lines from the peripheral modules according to table 12-11 . table 12-11 dma request assign ment for dma sub-block 0 dma channel dma request line dma requesting unit selected by 00 dma_sr08 dma(int_o08) chcr00.prsel = 0000 b iout0 scu (eru) chcr00.prsel = 0001 b fadc_sr00 fadc chcr00.prsel = 0010 b adc_sr00 adc chcr00.prsel = 0011 b ssc0_rdr ssc0 chcr 00.prsel = 0100 b asc0_rdr asc0 chcr 00.prsel = 0101 b can_int_o0 multican chcr00.prsel = 0110 b mli0_sr4 mli0 chcr00.prsel = 0111 b stmirq0 stm chcr 00.prsel = 1000 b gpta_trig00 gpta 1) chcr00.prsel = 1001 b gpta_trig10 gpta 1) chcr00.prsel = 1010 b int1src eray chcr00.prsel = 1011 b ibusy eray chcr00.prsel = 1100 b ssc2_rdr ssc2 chcr 00.prsel = 1101 b reserved 2) - chcr00.prsel = 1110 b mli1_sr4 mli1 chcr00.prsel = 1111 b 01 dma_sr09 dma(int_o09) chcr01.prsel = 0000 b iout1 scu (eru) chcr01.prsel = 0001 b fadc_sr01 fadc chcr01.prsel = 0010 b adc_sr01 adc chcr01.prsel = 0011 b ssc1_rdr ssc1 chcr 01.prsel = 0100 b asc1_rdr asc1 chcr 01.prsel = 0101 b can_int_o1 multican chcr01.prsel = 0110 b mli0_sr5 mli0 chcr01.prsel = 0111 b stmirq0 stm chcr 01.prsel = 1000 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-102 v1.1, 2011-03 dma, v1.6 gpta_trig01 gpta 1) chcr01.prsel = 1001 b gpta_trig11 gpta 1) chcr01.prsel = 1010 b tint0src eray chcr01.prsel = 1011 b reserved 2) - chcr01.prsel = 1100 b ccu60_sr0 ccu60_sr0 chcr01.prsel = 1101 b reserved 2) - chcr01.prsel = 1110 b mli1_sr5 mli1 chcr01.prsel = 1111 b 02 dma_sr10 dma(int_o10) chcr02.prsel = 0000 b iout2 scu (eru) chcr02.prsel = 0001 b fadc_sr02 fadc chcr02.prsel = 0010 b adc_sr02 adc chcr02.prsel = 0011 b ssc0_tdr ssc0 chcr 02.prsel = 0100 b asc0_tdr asc0 chcr 02.prsel = 0101 b msc0_sr2 msc0 chcr02.prsel = 0110 b mli0_sr6 mli0 chcr02.prsel = 0111 b stmirq0 stm chcr 02.prsel = 1000 b gpta_trig02 gpta 1) chcr02.prsel = 1001 b gpta_trig12 gpta 1) chcr02.prsel = 1010 b ndat1src eray chcr02.prsel = 1011 b asc0_tbdr asc0 chcr 02.prsel = 1100 b ssc2_tdr ssc2 chcr 02.prsel = 1101 b msc1_sr2 msc1 chcr02.prsel = 1110 b mli1_sr6 mli1 chcr02.prsel = 1111 b 03 dma_sr11 dma(int_o11) chcr03.prsel = 0000 b iout3 scu (eru) chcr03.prsel = 0001 b fadc_sr03 fadc chcr03.prsel = 0010 b adc_sr03 adc chcr03.prsel = 0011 b ssc1_tdr ssc1 chcr 03.prsel = 0100 b asc1_tdr asc1 chcr 03.prsel = 0101 b msc0_sr3 msc0 chcr03.prsel = 0110 b table 12-11 dma request assign ment for dma sub-block 0 (cont?d) dma channel dma request line dma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-103 v1.1, 2011-03 dma, v1.6 mli0_sr7 mli0 chcr03.prsel = 0111 b stmirq0 stm chcr 03.prsel = 1000 b gpta_trig03 gpta 1) chcr03.prsel = 1001 b gpta_trig13 gpta 1) chcr03.prsel = 1010 b mbsc1src eray chcr03.prsel = 1011 b asc1_tbdr asc1 chcr 03.prsel = 1100 b reserved 2) - chcr03.prsel = 1101 b msc1_sr3 msc1 chcr03.prsel = 1110 b mli1_sr7 mli1 chcr03.prsel = 1111 b 04 dma_sr12 dma(int_o12) chcr04.prsel = 0000 b iout0 scu (eru) chcr04.prsel = 0001 b fadc_sr00 fadc chcr04.prsel = 0010 b adc_sr04 adc chcr04.prsel = 0011 b ssc0_tdr ssc0 chcr 04.prsel = 0100 b asc0_tdr asc0 chcr 04.prsel = 0101 b msc0_sr2 msc0 chcr04.prsel = 0110 b mli0_sr4 mli0 chcr04.prsel = 0111 b stmirq0 stm chcr 04.prsel = 1000 b gpta_trig04 gpta 1) chcr04.prsel = 1001 b gpta_trig14 gpta 1) chcr04.prsel = 1010 b int1src eray chcr04.prsel = 1011 b asc0_tbdr asc0 chcr 04.prsel = 1100 b obusy eray chcr04.prsel = 1101 b msc1_sr2 msc1 chcr04.prsel = 1110 b mli1_sr4 mli1 chcr04.prsel = 1111 b 05 dma_sr13 dma(int_o13) chcr05.prsel = 0000 b iout1 scu (eru) chcr05.prsel = 0001 b fadc_sr01 fadc chcr05.prsel = 0010 b adc_sr05 adc chcr05.prsel = 0011 b ssc1_tdr ssc1 chcr 05.prsel = 0100 b table 12-11 dma request assign ment for dma sub-block 0 (cont?d) dma channel dma request line dma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-104 v1.1, 2011-03 dma, v1.6 asc1_tdr asc1 chcr 05.prsel = 0101 b msc0_sr3 msc0 chcr05.prsel = 0110 b mli0_sr5 mli0 chcr05.prsel = 0111 b stmirq0 stm chcr 05.prsel = 1000 b gpta_trig05 gpta 1) chcr05.prsel = 1001 b gpta_trig15 gpta 1) chcr05.prsel = 1010 b tint1src eray chcr05.prsel = 1011 b asc1_tbdr asc1 chcr 05.prsel = 1100 b ccu61_sr0 ccu61 chcr05.prsel = 1101 b msc1_sr3 msc1 chcr05.prsel = 1110 b mli1_sr5 mli1 chcr05.prsel = 1111 b 06 dma_sr14 dma(int_o14) chcr06.prsel = 0000 b iout2 scu (eru) chcr06.prsel = 0001 b fadc_sr02 fadc chcr06.prsel = 0010 b adc_sr06 adc chcr06.prsel = 0011 b ssc0_rdr ssc0 chcr 06.prsel = 0100 b asc0_rdr asc0 chcr 06.prsel = 0101 b can_int_o0 multican chcr06.prsel = 0110 b mli0_sr6 mli0 chcr06.prsel = 0111 b stmirq0 stm chcr 06.prsel = 1000 b gpta_trig06 gpta 1) chcr06.prsel = 1001 b gpta_trig16 gpta 1) chcr06.prsel = 1010 b ndat1src eray chcr06.prsel = 1011 b ssc3_tdr ssc3 chcr 06.prsel = 1100 b ccu62_sr0 ccu62 chcr06.prsel = 1101 b adc_sr08 adc chcr06.prsel = 1110 b mli1_sr6 mli1 chcr06.prsel = 1111 b 07 dma_sr15 dma(int_o15) chcr07.prsel = 0000 b iout3 scu (eru) chcr07.prsel = 0001 b fadc_sr03 fadc chcr07.prsel = 0010 b table 12-11 dma request assign ment for dma sub-block 0 (cont?d) dma channel dma request line dma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-105 v1.1, 2011-03 dma, v1.6 adc_sr07 adc chcr07.prsel = 0011 b ssc1_rdr ssc1 chcr 07.prsel = 0100 b asc1_rdr asc1 chcr 07.prsel = 0101 b can_int_o1 multican chcr07.prsel = 0110 b mli0_sr7 mli0 chcr07.prsel = 0111 b stmirq0 stm chcr 07.prsel = 1000 b gpta_trig07 gpta 1) chcr07.prsel = 1001 b gpta_trig17 gpta 1) chcr07.prsel = 1010 b mbsc1src eray chcr07.prsel = 1011 b ssc3_rdr ssc3 chcr 07.prsel = 1100 b ccu63_sr0 ccu63 chcr07.prsel = 1101 b adc_sr09 adc chcr07.prsel = 1110 b mli1_sr7 mli1 chcr07.prsel = 1111 b 1) gpta_trig signals are per default level sensitive signal s while a dma channel is activated with every active request signal cycle. the dma internal positive edge detection will generate the channel request with the rising edge of the gpta_trig signal, if selected. if channel requests for the positive and/or negative gpta_trig signal is required, this can be realized either via the eru (some gpta_trig signals are mapped to it) or via gpta programming by using additional gpta cells. 2) reserved prsel combinations do not result to dma channel requests. table 12-12 dma request assign ment for dma sub-block 1 dma channel dma request line dma requesting unit selected by 10 dma_sr08 dma(int_o08) chcr10.prsel = 0000 b iout0 scu (eru) chcr10.prsel = 0001 b fadc_sr00 fadc chcr10.prsel = 0010 b adc_sr00 adc chcr10.prsel = 0011 b ssc0_rdr ssc0 chcr 10.prsel = 0100 b asc0_rdr asc0 chcr 10.prsel = 0101 b can_int_o0 multican chcr10.prsel = 0110 b mli0_sr4 mli0 chcr10.prsel = 0111 b stmirq0 stm chcr 10.prsel = 1000 b table 12-11 dma request assign ment for dma sub-block 0 (cont?d) dma channel dma request line dma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-106 v1.1, 2011-03 dma, v1.6 gpta_trig00 gpta 1) chcr10.prsel = 1001 b gpta_trig10 gpta 1) chcr10.prsel = 1010 b int1src eray chcr10.prsel = 1011 b ibusy eray chcr10.prsel = 1100 b ssc2_rdr ssc2 chcr 10.prsel = 1101 b reserved 2) - chcr10.prsel = 1110 b mli1_sr4 mli1 chcr10.prsel = 1111 b 11 dma_sr09 dma(int_o09) chcr11.prsel = 0000 b iout1 scu (eru) chcr11.prsel = 0001 b fadc_sr01 fadc chcr11.prsel = 0010 b adc_sr01 adc chcr11.prsel = 0011 b ssc1_rdr ssc1 chcr 11.prsel = 0100 b asc1_rdr asc1 chcr 11.prsel = 0101 b can_int_o1 multican chcr11.prsel = 0110 b mli0_sr5 mli0 chcr11.prsel = 0111 b stmirq0 stm chcr 11.prsel = 1000 b gpta_trig01 gpta 1) chcr11.prsel = 1001 b gpta_trig11 gpta 1) chcr11.prsel = 1010 b tint0src eray chcr11.prsel = 1011 b reserved 2) - chcr11.prsel = 1100 b ccu60_sr0 ccu60 chcr11.prsel = 1101 b reserved 2) - chcr11.prsel = 1110 b mli1_sr5 mli1 chcr11.prsel = 1111 b 12 dma_sr10 dma(int_o10) chcr12.prsel = 0000 b iout2 scu (eru) chcr12.prsel = 0001 b fadc_sr02 fadc chcr12.prsel = 0010 b adc_sr02 adc chcr12.prsel = 0011 b ssc0_tdr ssc0 chcr 12.prsel = 0100 b asc0_tdr asc0 chcr 12.prsel = 0101 b msc0_sr2 msc0 chcr12.prsel = 0110 b table 12-12 dma request assign ment for dma sub-block 1 (cont?d) dma channel dma request line dma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-107 v1.1, 2011-03 dma, v1.6 mli0_sr6 mli0 chcr12.prsel = 0111 b stmirq0 stm chcr 12.prsel = 1000 b gpta_trig02 gpta 1) chcr12.prsel = 1001 b gpta_trig12 gpta 1) chcr12.prsel = 1010 b ndat1src eray chcr12.prsel = 1011 b asc0_tbdr asc0 chcr 12.prsel = 1100 b ssc2_tdr ssc2 chcr 12.prsel = 1101 b msc1_sr2 msc1 chcr12.prsel = 1110 b mli1_sr6 mli1 chcr12.prsel = 1111 b 13 dma_sr11 dma(int_o11) chcr13.prsel = 0000 b iout3 scu (eru) chcr13.prsel = 0001 b fadc_sr03 fadc chcr13.prsel = 0010 b adc_sr03 adc chcr13.prsel = 0011 b ssc1_tdr ssc1 chcr 13.prsel = 0100 b asc1_tdr asc1 chcr 13.prsel = 0101 b msc0_sr3 msc0 chcr13.prsel = 0110 b mli0_sr7 mli0 chcr13.prsel = 0111 b stmirq0 stm chcr 13.prsel = 1000 b gpta_trig03 gpta 1) chcr13.prsel = 1001 b gpta_trig13 gpta 1) chcr13.prsel = 1010 b mbsc1src eray chcr13.prsel = 1011 b asc1_tbdr asc1 chcr 13.prsel = 1100 b reserved 2) - chcr13.prsel = 1101 b msc1_sr3 msc1 chcr13.prsel = 1110 b mli1_sr7 mli1 chcr13.prsel = 1111 b 14 dma_sr12 dma(int_o12) chcr14.prsel = 0000 b iout0 scu (eru) chcr14.prsel = 0001 b fadc_sr00 fadc chcr14.prsel = 0010 b adc_sr04 adc chcr14.prsel = 0011 b ssc0_tdr ssc0 chcr 14.prsel = 0100 b table 12-12 dma request assign ment for dma sub-block 1 (cont?d) dma channel dma request line dma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-108 v1.1, 2011-03 dma, v1.6 asc0_tdr asc0 chcr 14.prsel = 0101 b msc0_sr2 msc0 chcr14.prsel = 0110 b mli0_sr4 mli0 chcr14.prsel = 0111 b stmirq0 stm chcr 14.prsel = 1000 b gpta_trig04 gpta 1) chcr14.prsel = 1001 b gpta_trig14 gpta 1) chcr14.prsel = 1010 b int1src eray chcr14.prsel = 1011 b asc0_tbdr asc0 chcr 14.prsel = 1100 b obusy eray chcr14.prsel = 1101 b msc1_sr2 msc1 chcr14.prsel = 1110 b mli1_sr4 mli1 chcr14.prsel = 1111 b 15 dma_sr13 dma(int_o13) chcr15.prsel = 0000 b iout1 scu (eru) chcr15.prsel = 0001 b fadc_sr01 fadc chcr15.prsel = 0010 b adc_sr05 adc chcr15.prsel = 0011 b ssc1_tdr ssc1 chcr 15.prsel = 0100 b asc1_tdr asc1 chcr 15.prsel = 0101 b msc0_sr3 msc0 chcr15.prsel = 0110 b mli0_sr5 mli0 chcr15.prsel = 0111 b stmirq0 stm chcr 15.prsel = 1000 b gpta_trig05 gpta 1) chcr15.prsel = 1001 b gpta_trig15 gpta 1) chcr15.prsel = 1010 b tint1src eray chcr15.prsel = 1011 b asc1_tbdr asc1 chcr 15.prsel = 1100 b ccu61_sr0 ccu61 chcr15.prsel = 1101 b msc1_sr3 msc1 chcr15.prsel = 1110 b mli1_sr5 mli1 chcr15.prsel = 1111 b 16 dma_sr14 dma(int_o14) chcr16.prsel = 0000 b iout2 scu (eru) chcr16.prsel = 0001 b fadc_sr02 fadc chcr16.prsel = 0010 b table 12-12 dma request assign ment for dma sub-block 1 (cont?d) dma channel dma request line dma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-109 v1.1, 2011-03 dma, v1.6 adc_sr06 adc chcr16.prsel = 0011 b ssc0_rdr ssc0 chcr 16.prsel = 0100 b asc0_rdr asc0 chcr 16.prsel = 0101 b can_int_o0 multican chcr16.prsel = 0110 b mli0_sr6 mli0 chcr16.prsel = 0111 b stmirq0 stm chcr 16.prsel = 1000 b gpta_trig06 gpta 1) chcr16.prsel = 1001 b gpta_trig16 gpta 1) chcr16.prsel = 1010 b ndat1src eray chcr16.prsel = 1011 b ssc3_tdr ssc3 chcr 16.prsel = 1100 b ccu62_sr0 ccu62 chcr16.prsel = 1101 b adc_sr08 adc chcr16.prsel = 1110 b mli1_sr6 mli1 chcr16.prsel = 1111 b 17 dma_sr15 dma(int_o15) chcr17.prsel = 0000 b iout3 scu (eru) chcr17.prsel = 0001 b fadc_sr03 fadc chcr17.prsel = 0010 b adc_sr07 adc chcr17.prsel = 0011 b ssc1_rdr ssc1 chcr 17.prsel = 0100 b asc1_rdr asc1 chcr 17.prsel = 0101 b can_int_o1 multican chcr17.prsel = 0110 b mli0_sr7 mli0 chcr17.prsel = 0111 b stmirq0 stm chcr 17.prsel = 1000 b gpta_trig07 gpta 1) chcr17.prsel = 1001 b gpta_trig17 gpta 1) chcr17.prsel = 1010 b mbsc1src eray chcr17.prsel = 1011 b ssc3_rdr ssc3 chcr 17.prsel = 1100 b ccu63_sr0 ccu63 chcr17.prsel = 1101 b adc_sr09 adc chcr17.prsel = 1110 b mli1_sr7 mli1 chcr17.prsel = 1111 b table 12-12 dma request assign ment for dma sub-block 1 (cont?d) dma channel dma request line dma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-110 v1.1, 2011-03 dma, v1.6 1) gpta_trig signals are per default level sensitive signal s while a dma channel is activated with every active request signal cycle. the dma internal positive edge detection will generate the channel request with the rising edge of the gpta_trig signal, if selected. if channel requests for the positive and/or negative gpta_trig signal is required, this can be realized either via the eru (some gpta_trig signals are mapped to it) or via gpta programming by using additional gpta cells. 2) reserved prsel combinations do not result to dma channel requests. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-111 v1.1, 2011-03 dma, v1.6 12.4.2 access protection assignment dma access protection as described on page 12-44 requires the assignment of 32 fixed address range. table 12-13 shows this address range assignment as implemented in the TC1798 (see also: page 12-81 , page 12-81 ). table 12-13 dma access protection address ranges for dma_memaenr0 access protection range related module(s) no. n enable bit in memaenr selected address range 0 aen0 f000 0500 h - f000 06ff h scu, wdt 1 aen1 f000 0100 h - f000 01ff h sbcu 2 aen2 f000 0200 h - f000 02ff h stm 3 aen3 f000 0400 h - f000 04ff h ocds 4 aen4 f000 0800 h to f000 08ff h msc0 5 aen5 f000 0a00 h to f000 0aff h asc0 6 aen6 f000 0b00 h to f000 0bff h asc1 7 aen7 f000 0c00 h - f000 17ff h port 0 - port 11 8 aen8 f030 0000 h - f030 06ff h port 12 - port 18 9 aen9 f000 1800 h - f000 2fff h gpta0, gpta1, ltca2 10 aen10 f000 3c00 h - f000 3eff h dma 11 aen11 f000 4000 h - f000 7fff h multican 12 aen12 f004 0000 h - f004 ffff h pcp registers 13 aen13 f005 0000 h - f005 ffff h pcp data sram (pram) 14 aen14 f006 0000 h - f007 ffff h pcp code sram (cmem) 15 aen15 f031 0000 h - f031 01ff h f031 0800 h - f031 09ff h f031 0a00 h - f031 0bff h ssc0, ssc1 sscg0 sscg1 16 aen16 f031 0200 h - f031 03ff h f031 0c00 h - f031 0dff h f031 0e00 h - f010 0fff h ssc2, ssc3 sscg2 sscg3 17 aen17 f010 0400 h - f010 05ff h fadc 18 aen18 f010 1000 h - f010 1fff h adc0, adc1, adc2, adc3 19 aen19 f010 c000 h - f010 c0ff h f01e 0000 h - f01e 7fff h f020 0000 h - f023 ffff h mli0 module, mli0 small tws, mli0 large tws www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-112 v1.1, 2011-03 dma, v1.6 20 aen20 f010 c100 h - f010 c1ff h f01e 8000 h - f01e ffff h f024 0000 h - f027 ffff h mli1, mli1 small tws, mli1 large tws 21 aen21 f7e0 ff00 h - f7e0 ffff h f7e1 0000 h - f7e1 ffff h cps cpu core sfrs & gprs 22 aen22 f800 0000 h - f800 03ff h ebu 23 aen23 8000 0000 h - 82ff ffff h a000 0000 h - a2ff ffff h pflash0, pflash1 24 aen24 8300 0000 h - 8eff ffff h a300 0000 h - aeff ffff h external ebu space 25 aen25 8f00 0000 h - 8f0f ffff h af00 0000 h - af0f ffff h dflash0, dflash1 26 aen26 9f00 0000 h - 9f1f ffff h bf00 0000 h - bf1f ffff h emulation device memory space 27 aen27 8fff c000 h - 8fff ffff h afff c000 h - afff ffff h boot rom 28 aen28 f001 0000 h - f001 7fff h eray 29 aen29 9000 0000 h - 9001 ffff h b000 0000 h - b001 ffff h lmu sram 30 aen30 d000 0000 h - d001 ffff h d800 0000 h - d801 ffff h dmi (data scratch sram) 31 aen31 c000 0000 h - c000 7fff h c800 0000 h - c800 7fff h pmi (program scratch sram) table 12-14 dma access protection address ranges for dma_memaenr1 access protection range related module(s) no. n enable bit in memaenr selected address range 0 aen0 f010 c200 h - f010 c2ff h memchk 1 aen1 2 aen2 table 12-13 dma access protection address ranges for dma_memaenr0 access protection range related module(s) no. n enable bit in memaenr selected address range www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-113 v1.1, 2011-03 dma, v1.6 3 aen3 4 aen4 f000 0900 h to f000 09ff h msc1 5 aen5 6 aen6 7 aen7 8 aen8 9 aen9 10 aen10 f000 3000 h - f000 31ff h f000 3400 h - f000 34ff h ccu60, ccu61 gpt120 11 aen11 f000 3200 h - f000 33ff h f000 3500 h - f000 35ff h ccu62, ccu63 gpt121 12 aen12 f000 3800 h - f000 3aff h sdma 13 aen13 f032 0000 h - f032 00ff h fce 14 aen14 f032 0200 h - f032 02ff h she 15 aen15 f032 1000 h - f032 19ff h sent 16 aen16 f032 3000 h - f032 31ff h bmu registers 17 aen17 f870 0800 h - f870 08ff h lmu 18 aen18 f800 0500 h - f86f ffff h pmu, flash registers 19 aen19 f870 0000 h - f870 04ff h xbar 20 aen20 21 aen21 22 aen22 23 aen23 24 aen24 25 aen25 26 aen26 f032 4000 h - f032 7fff h bmuram 27 aen27 28 aen28 29 aen29 table 12-14 dma access protection address ranges for dma_memaenr1 access protection range related module(s) no. n enable bit in memaenr selected address range www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-114 v1.1, 2011-03 dma, v1.6 30 aen30 d820 0000 h - d820 3fff h dcache 31 aen31 c820 0000 h - c820 3fff h pcache table 12-14 dma access protection address ranges for dma_memaenr1 access protection range related module(s) no. n enable bit in memaenr selected address range www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-115 v1.1, 2011-03 dma, v1.6 in the TC1798, four internal memory areas (program scratch sram, data scratch sram, lmu sram and pcp data sram) are protected by an address range verification in addition to the access enable bits. the address range verification is based on the bit fields sizex and slicex (x = 3-0), which are located in the registers memarr0 and memarr1 (m = 1-0). an access to one of these four memory areas is only processed if it is enabled by the corresponding aenx bit and if the address is inside the sub-range defined by the corresponding sizex and slicex. if the address is outside of the defined sub-range, the transfer will not be processed and an error interrupt is generated (indicated by the corresponding mexder, mexser bit). if a protected memory is available from dma under multiple address ranges (sri, fpi, cached and or un-cached segments), the access protection is valid for all memory views in parallel, starting always with the base address of the memory views, ending always with the end address of the address range. the address ranges described by slicex and sizex are defined as follows: ? memarr0.slice0, memarr0.size0: 32-kb program scratch sram, assigned to address range 31 (aen31). the sub- ranges are controlled by bit fields memarr0.size0 and me0arr0.slice0 with a minimum granularity of 0,5 kb (see table 12-15 ). ? memarr0.size1 and memarr0.slice1: 128-kb lmu sram, assigned to address range 29 (aen29). the sub-ranges are controlled by bit fields memarr0.size1 and memarr0.slice1 with a minimum granularity of 1 kb (see table 12-16 ). ? memarr0.size2 and memarr0.slice2: 128-kb data scratch sram, assigned to address range 30 (aen30). the sub- ranges are controlled by bit fields me marr0.size2 and memarr0.slice2 with a minimum granularity of 1 kb (see table 12-17 ). ? memarr0.size3 and memarr0.slice3: 16-kbyte pcp data sram, assigned to address range 13 (aen13). the sub-range is controlled by bit fields memarr0.size3 and memarr0.slice3 with a minimum granularity of 0,5 kb (see table 12-18 ). ? memarr1.size0 and memarr1.slice0: reserved. ? memarr1.size1 and memarr1.slice1: reserved. ? memarr1.size2 and memarr1.slice2: reserved. ? memarr1.size3 and memarr1.slice3: reserved. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-116 v1.1, 2011-03 dma, v1.6 dma_memarr0.size0 and dma_memarr0.s lice0 bit fields: program scratch sram sub-range access protection bit fields size0 and slice0 for the pmi memory sub-range access protection (32 kb pspr) as shown in table 12-15 . the pmi memory is protected with a min. granularity of 0,5 kb up to the end address cx00 ffff h . pmi address ranges that are protected by the bit fields size0 and slice0: ? c000 0000 h - c000 7fff h (program scratch ram) ? c800 0000 h - c800 7fff h (program scratch ram) table 12-15 program scratch sram address protection sub-range definition size0 sub-ranges slice0 selected address range 000 b 32 sub-ranges of 512 bytes 00000 b 00001 b ? 11111 b xxx0 0000 h - xxx0 01ff h xxx0 0200 h - xxx0 03ff h ? xxx0 3e00 h - xxx0 3fff h 001 b 32 sub-ranges of 1 kbyte 00000 b 00001 b ? 11111 b xxx0 0000 h - xxx0 03ff h xxx0 0400 h - xxx0 07ff h ? xxx0 7c00 h - xxx0 7fff h 010 b 32 sub-ranges of 2 kbytes 00000 b 00001 b ? 11111 b xxx0 0000 h - xxx0 07ff h xxx0 0800 h - xxx0 0fff h ? xxx0 f800 h - xxx0 ffff h 011 b 16 sub-ranges of 4 kbytes x0000 b x0001 b ? x1111 b xxx0 0000 h - xxx0 0fff h xxx0 1000 h - xxx0 1fff h ? xxx0 f000 h - xxx0 ffff h 100 b 8 sub-ranges of 8 kbytes xx000 b xx001 b ? xx111 b xxx0 0000 h - xxx0 1fff h xxx0 2000 h - xxx0 3fff h ? xxx0 e000 h - xxx0 ffff h 101 b 4 sub-ranges of 16 kbytes xxx00 b xxx01 b xxx10 b xxx11 b xxx0 0000 h - xxx0 3fff h xxx0 4000 h - xxx0 7fff h xxx0 8000 h - xxx0 bfff h xxx0 c000 h - xxx0 ffff h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-117 v1.1, 2011-03 dma, v1.6 dma_memarr0.size1 and dma_memarr0.s lice1 bit fields: lmu sram sub- range access protection bit fields size1 and slice1 for the lmu sram sub-range access protection (128 kb) are coded as shown in table 12-16 . the 128 kb lmu sram memory is protected with a minimum granularity of 1 kb up to the end address x001 ffff h . ovram address ranges that are protected by the bit fields size1 and slice1: ? 9000 0000 h - 9001 ffff h (lmu sram) ? b000 0000 h - b001 ffff h (lmu sram) 110 b 2 sub-ranges of 32 kbytes xxxx0 b xxxx1 b xxxx 0000 h - xxxx 7fff h xxxx 8000 h - xxxx ffff h 111 b 64 kbytes xxxxx b xxxx 0000 h - xxxx ffff h table 12-16 lmu sram address pr otection sub-range definition size1 sub-ranges slice1 selected address range 000 b 32 sub-ranges of 1 kbytes 00000 b 00001 b ? 11111 b xxx0 0000 h - xxx0 03ff h xxx0 0400 h - xxx0 07ff h ? xxx0 7c00 h - xxx0 7fff h 001 b 32 sub-ranges of 2 kbyte 00000 b 00001 b ? 11111 b xxx0 0000 h - xxx0 07ff h xxx0 0800 h - xxx0 0fff h ? xxx0 f800 h - xxx0 ffff h 010 b 32 sub-ranges of 4kbytes 00000 b 00001 b ? 11111 b xxx0 0000 h - xxx0 0fff h xxx0 1000 h - xxx0 1fff h ? xxx1 f000 h - xxx1 ffff h 011 b 16 sub-ranges of 8 kbytes x0000 b x0001 b ? x1111 b xxx0 0000 h - xxx0 1fff h xxx0 2000 h - xxx0 3fff h ? xxx1 e000 h - xxx1 ffff h 100 b 8 sub-ranges of 16 kbytes xx000 b xx001 b ? xx111 b xxx0 0000 h - xxx0 3fff h xxx0 4000 h - xxx0 7fff h .... xxx1 c000 h - xxx1 ffff h table 12-15 program scratch sram address protection sub-range definition size0 sub-ranges slice0 selected address range www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-118 v1.1, 2011-03 dma, v1.6 dma_memarr0.size2 and dma_memarr0.s lice2 bit fields: data scratch sram sub-range access protection bit fields size2 and slice2 for the data scratch sram sub-range access protection. these bit fields are covering the 128 kb data scratch sram. the data scratch sram is protected with a min. granularity of 1 kb ( table 12-17 ) up to the end address dx01 ffff h . data scratch sram address ranges that ar e protected by the bit fields size2 and slice2: ? d000 0000 h - d001 ffff h (data scratch sram) ? d800 0000 h - d801 ffff h (data scratch sram) 101 b 4 sub-ranges of 32 kbytes xxx00 b xxx01 b xxx10 b xxx11 b xxx0 0000 h - xxx0 7fff h xxx0 8000 h - xxx0 ffff h xxx1 0000 h - xxx1 7fff h xxx1 8000 h - xxx1 ffff h 110 b 2 sub-ranges of 64 kbytes xxxx0 b xxxx1 b xxx0 0000 h - xxx0 ffff h xxx1 0000 h - xxx1 ffff h 111 b 128 kbytes xxxxx b xxx0 0000 h - xxx1 ffff h table 12-17 data scratch sram address protection sub-range definitions size2 sub-ranges slice2 selected address range 000 b 32 sub-ranges of 1 kbytes 00000 b 00001 b ? 11111 b xxx0 0000 h - xxx0 03ff h xxx0 0400 h - xxx0 07ff h ? xxx0 7c00 h - xxx0 7fff h 001 b 32 sub-ranges of 2 kbyte 00000 b 00001 b ? 11111 b xxx0 0000 h - xxx0 07ff h xxx0 0800 h - xxx0 0fff h ? xxx0 f800 h - xxx0 ffff h 010 b 32 sub-ranges of 4kbytes 00000 b 00001 b ? 11111 b xxx0 0000 h - xxx0 0fff h xxx0 1000 h - xxx0 1fff h ? xxx1 f000 h - xxx1 ffff h table 12-16 lmu sram address pr otection sub-range definition (cont?d) size1 sub-ranges slice1 selected address range www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-119 v1.1, 2011-03 dma, v1.6 dma_memarr0.size3 and dma_memarr0.s lice3 bit fields: pcp data sram sub-range access protection bit fields size3 and slice3 for the pcp data sram sub-range access protection. these bit fields are covering pcp data sram memory. the pcp data sram memory is protected with a min. granularity of 0,5 kb ( table 12-18 ) up to the end address f005 ffff h (16kb pram and 48kb reserved address space). pcp data sram address range that is protected by the bit fields size3 and slice3: ? f005 0000 h - f005 3fff h (pcp data sram on fpi bus, 16 kb) 011 b 16 sub-ranges of 8 kbytes x0000 b x0001 b ? x1111 b xxx0 0000 h - xxx0 1fff h xxx0 2000 h - xxx0 3fff h ? xxx1 e000 h - xxx1 ffff h 100 b 8 sub-ranges of 16 kbytes xx000 b xx001 b ? xx111 b xxx0 0000 h - xxx0 3fff h xxx0 4000 h - xxx0 7fff h .... xxx1 c000 h - xxx1 ffff h 101 b 4 sub-ranges of 32 kbytes xxx00 b xxx01 b xxx10 b xxx11 b xxx0 0000 h - xxx0 7fff h xxx0 8000 h - xxx0 ffff h xxx1 0000 h - xxx1 7fff h xxx1 8000 h - xxx1 ffff h 110 b 2 sub-ranges of 64 kbytes xxxx0 b xxxx1 b xxx0 0000 h - xxx0 ffff h xxx1 0000 h - xxx1 ffff h 111 b 128 kbytes xxxxx b xxx0 0000 h - xxx1 ffff h table 12-17 data scratch sram address protection sub-range definitions size2 sub-ranges slice2 selected address range www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-120 v1.1, 2011-03 dma, v1.6 table 12-18 pcp data sram size3 and sl ice3 address protection sub-range definition scheme size3 sub-ranges slice3 selected address range 000 b 32 sub-ranges of 512 bytes 00000 b 00001 b ? 11111 b f005 0000 h - f005 01ff h f005 0200 h - f005 03ff h ? f005 3e00 h - f005 3fff h 001 b 32 sub-ranges of 1 kbyte 00000 b 00001 b ? 11111 b f005 0000 h - f005 03ff h f005 0400 h - f005 07ff h ? f005 7c00 h - f005 7fff h 010 b 32 sub-ranges of 2 kbytes 00000 b 00001 b ? 11111 b f005 0000 h - f005 07ff h f005 0800 h - f005 0fff h ? f005 f800 h - f005 ffff h 011 b 16 sub-ranges of 4 kbytes x0000 b x0001 b ? x1111 b f005 0000 h - f005 0fff h f005 1000 h - f005 1fff h ? f005 f000 h - f005 ffff h 100 b 8 sub-ranges of 8 kbytes xx000 b xx001 b ? xx111 b f005 0000 h - f005 1fff h f005 2000 h - f005 3fff h ? f005 e000 h - f005 ffff h 101 b 4 sub-ranges of 16 kbytes xxx00 b xxx01 b xxx10 b xxx11 b f005 0000 h - f005 3fff h f005 4000 h - f005 7fff h f005 8000 h - f005 bfff h f005 c000 h - f005 ffff h 110 b 2 sub-ranges of 32 kbytes xxxx0 b xxxx1 b f005 0000 h - f005 7fff h f005 8000 h - f005 ffff h 111 b 64 kbytes xxxxx b f005 0000 h - f005 ffff h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-121 v1.1, 2011-03 dma, v1.6 dma_memarr1.size0 and dma_ memarr1.slice0 bit fields dma_memarr1.size1 and dma_ memarr1.slice1 bit fields dma_memarr1.size2 and dma_ memarr1.slice2 bit fields table 12-19 address protection sub-range definition size0 sub-ranges slice0 selected address range 000 b 001 b 010 b 011 b 100 b 101 b 110 b 111 b table 12-20 address protection sub-range definition size1 sub-ranges slice1 selected address range 000 b 001 b 010 b 011 b 100 b 101 b 110 b 111 b table 12-21 address protection sub-range definition size2 sub-ranges slice2 selected address range 000 b 001 b 010 b 011 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-122 v1.1, 2011-03 dma, v1.6 dma_memarr1.size3 and dma_ memarr1.slice3 bit fields 100 b 101 b 110 b 111 b table 12-22 address protection sub-range definition size3 sub-ranges slice3 selected address range 000 b 001 b 010 b 011 b 100 b 101 b 110 b 111 b table 12-21 address protection sub-range definition (cont?d) size2 sub-ranges slice2 selected address range www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-123 v1.1, 2011-03 dma, v1.6 12.4.3 implementation-sp ecific dma registers the dma controller as implemented in the TC1798 contains the following additional registers: ? dma clock control register ? service request control registers fo r dma controller in terrupts (dma_srcx) ? service request control registers for mli module interrupts (dma_mli0ysrc.x) figure 12-29 provides an overview of these registers. figure 12-29 dma implementa tion-specific registers note: further details on interrupt handling and processing are described in the ?interrupt system? chapter of the TC1798 system units users manual. the clock generation and interrupt control configuration as implemented in the dma controller module is shown in figure 12-29 . the dma controller, the cerberus and the two mli modules (mli0 and mli1) are supplied from a common module clock f dma that has the frequency of the system clock f fpi and is controlled via the dma_clc clock control register. the mli modules nor the cerberus module do not have their own clock control registers. their input clock is derived from the dma clock divided by separate fractional divider registers. the control of the suspend and break features is done independently inside each module. dma interrupt registers control register dma_clc dma_src0 dma_src1 dma_src2 dma_src3 mca06177a mli interrupt registers dma_mli 0src0 dma_mli 0src1 dma_mli 0src2 dma_mli 0src3 dma_mli 1src0 dma_mli 1src1 dma_src4 dma_src5 dma_src6 dma_src7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-124 v1.1, 2011-03 dma, v1.6 the dma controller module contains in total 14 interrupt request nodes with its interrupt service request control registers: ? eight interrupt requests sr[7:0] = int_o[7:0] from the dma controller; upper eight interrupt requests of the dma controller int_o[15:8] are used ad dma channel trigger inputs . ? four interrupt requests sr[3:0] = int_o[3:0] from the mli0 module; upper four interrupt requests of the mli0 module int_o[7:4] are not connected. ? two interrupt requests sr[1:0] = int_o[1:0] from the mli1 module; upper six interrupt requests of the mli1 module int_o[7:2] are not connected. figure 12-30 implementation of the dma module and the mli modules dma module kernel interrupt control in dma module clock control address decoder mca06178 int_o[15:0] f ml i0 f dma mli0 module kernel mli1 module kernel int_o[7:0] int_o[7:0] mli0_fdr mli 1_fdr f ml i1 f fpi sr[7:0] sr[3:0] sr[1:0] 16 8 1 cerberus cbs_src www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-125 v1.1, 2011-03 dma, v1.6 12.4.3.1 clock control register the clock control register controls the dma module internal f dma clock signal. this clock is also used for the mli modules as a common clock that can be individually divided for the mli modules. note: after a hardware reset oper ation, the dma module is enabled. note: the suspend mode does not modify any of the registers. dma_clc dma clock control register (000 h ) reset value: 0000 0008 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we one sp en diss disr r rwwrwrw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the module diss 1r module disable status bit bit indicates the current status of the module spen 2rw module suspend enable for ocds used to enable the suspend mode one 3rw reserved; returns 1 if read; must be written with 1. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. 0 5rw reserved; returns 0 if read; must be written with 0. 0 [31:6] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-126 v1.1, 2011-03 dma, v1.6 12.4.3.2 dma inte rrupt registers in the TC1798, the lower eight dma controller interrupts sr[7:0] are connected to service request control registers. the up per eight dma controller interrupt outputs sr[15:8] are used as dma channel request inputs ( page 12-101 ). dma_srcx (x = 0-7) dma service request control register x (2fc h - x*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp request is initiated sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-127 v1.1, 2011-03 dma, v1.6 12.4.3.3 mli interrupt registers the service request control registers of the mli module are located inside the dma address area, because the mli module does not have its own fpi bus interfaces. the mli modules shares one fpi bus slave interface with the dma controller. the mli0 module has eight interrupt output lines. only four of them [3:0] are controlled by the mli0 service request registers. the mli1 module has also eight interrupt output lines, but only two of them [1:0] are controlled by the mli1 service request registers. dma_mli0srcx (x = 0-3) dma mli0 service request control register x (2ac h - x*4 h ) reset value: 0000 0000 h dma_mli1srcy (y = 0-1) dma mli1 service request control register y (2bc h - y*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp request is initiated sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-128 v1.1, 2011-03 dma, v1.6 note: the bit coding of the mli0 /mli1 service request registers is identical to that of the dma service request control registers shown on the previous page. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-129 v1.1, 2011-03 dma, v1.6 12.4.4 address map the dma controller register block address map is shown in figure 12-31 . it shows how the different register blocks are arranged and adds the absolute address information. figure 12-31 dma controller register block address map mca06179 general module control dma control /status registers f000 3 c00 h f000 3 c10 h f000 3 c80 h f000 3c30 h dma channel 00 - 07 registers move engine registers dma control /status registers f000 3 c54 h mli service request control registers system service request control registers dma service request control registers f000 3 e8c h f000 3 ea0 h f000 3 ef0 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-130 v1.1, 2011-03 dma, v1.6 12.5 memory checker module the memory checker module (mchk) supports the checking of data consistency in memories. it includes two parallel cyclic redundancy checkers (crcs) that can be used to check the data consistency of two memories in parallel. each crc block contains two algorithm engines: 1. a legacy data compaction algorithm based on a multiple input shift register (misr) implementation. 2. a crc-32 ethernet polynomial implementation. both algorithm engines use a common input register and simultaneously compute a checksum. 12.5.1 functional description the memory checker module is connected to the dma peripheral interface and can be accessed via the spb. preferable the module is used in combination with the dma as it as described hereafter: a dma channel can be us ed to read 8-bit, 16-bit, or 32-bit data from an address area and to write the data in one of the two memory checker input register. with each write operation to th e chosen memory checker input register a polynomial checksum calculation is triggered and the result of the calculation is stored in the corresponding memory checker result register. the misr algorithm engine supports 8-bit, 16-bit and 32-bit read data accesses. the crc-32 ethernet polynomial is limited to 32-b it accesses. in order to start a memory check sequence, the memory checker misr and crc-32 ethernet polynomial result registers must be initialized (e.g. written with ffffffff h or with a desired start value) and a dma transaction must be set up (start address, length, etc.). when programming the dma channel for the memory checker with chcrmn.rroat = 1, one dma transfer request (software or hardware triggered) starts the dma transaction. during the read move operations of the dma transaction, data is always read from the memory and then written into the memory checker input register for the polynomial checksum calculation. at the end of the tr ansaction (chsrmn.tcount = 0), an interrupt can be generated by the dma channel (if chcrmn.rroat = 1), and the memory checker result register can be read out by software. both the misr and crc-32 memory checkers use the ieee 802.3 standard polynomial, which is given by: g 32 = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 (12.1) note: although the polynomial above is used for generation, the generation algorithm differs from the one that is used by the ethernet protocol. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-131 v1.1, 2011-03 dma, v1.6 figure 12-32 implementation of the multiple input shift register 12.5.1.1 ethernet crc-32 endianness in order to comply with the ethernet crc-32 standard the endianness of the input word needs to be big endian. this is important only when the input stream is made up of bytes, because each cpu architecture may have a different endianness. tricore is little endian, and when a byte pointer (to a byte array) is cast into a 32-bit word pointer, the compiler packs the bytes in little endian format and therefore the crc-32 checksum result provided by the mchk et hernet crc-32 hardware differs from that generated by an ethernet crc-32 software model using a byte stream. in order to generate a checksum compliant with the ethernet crc-32 checksum then the software must swap the order of the bytes. ... 0 f f f f f f f f 1 30 31 0 1 30 31 g32 mchkir: memory checker input data bits mchkrr: memory checker result data bits ... x o r x o r x o r x o r f f 2 x o r 2 m chk_structur e g32 & and result bits with polynomial bits x o r x o r x o r x o r x o r 31 5 8 23 24 29 g26 g10 g7 g2 g0 xor all bit s x o r x o r 26 27 g4 x o r x o r 20 21 x o r 9 x o r x o r 19 15 g23 g22 g16 g12 g11 g8 g5 x o r g1 30 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-132 v1.1, 2011-03 dma, v1.6 12.5.2 memory checker module registers this section describes the kernel registers of the memory checker module. mchk register overview figure 12-33 memory checker registers table 12-23 registers address space - memory checker module address space module base address end address note mchk f010 c200 h f010 c2ff h table 12-24 registers overview - memory checker module control registers short name description offset addr. 1) access mode reset class description see read write - reserved 000 h - 004 h be be - - mchk_id module identification register 008 h us, v be - page 12-133 - reserved 00c h be be - - mchk_ir0 memory checker input register 010 h u, sv u, sv 3 page 12-135 mchk_rr0 memory checker result register 014 h u, sv u, sv 3 page 12-135 mchk_ir1 memory checker input register 018 h u, sv u, sv 3 page 12-135 mchk_rr1 memory checker result register 01c h u, sv u, sv 3 page 12-135 mchk_reg _its memory checker registers mchk_ir0 mchk_rr0 mchk_wr other registers module register mchk_id mchk_crcr0 mchk_ir1 mchk_rr1 mchk_crcr1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-133 v1.1, 2011-03 dma, v1.6 12.5.2.1 memory checker module control registers the identification register allows the progra mmer version-tracking of the module. the table below shows the identification register which is implemented in the mchk module. mchk_wr memory checker write register 020 h u, sv u, sv 3 page 12-136 mchk_crc r0 memory checker result register 024 h u, sv u, sv, 32 3 page 12-136 mchk_crc r1 memory checker result register 028 h u, sv u, sv, 32 3 page 12-136 - reserved 02c h - 2ff h be be - - 1) the absolute register address is calculated as follows: module base address ( table 12-23 ) + offset address (shown in this column) mchk_id module identificat ion register (008 h ) reset value: 001b c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). table 12-24 registers overview - memory checker module control registers short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-134 v1.1, 2011-03 dma, v1.6 mod_type [15:8] r module type the bit field is set to c0 h which defines the module as a 32-bit module. mod_numbe r [31:16] r module number value this bit field defines a module identification number. the value for the memory checker module is 001b h . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-135 v1.1, 2011-03 dma, v1.6 a memory checker input register is used during write moves of a memory checker related dma transaction as data destination with its fixed register address. if the dma moves to register, for example mchk_ir0 ar e 8-bit or 16-bit wide, the unused register bits of the 32-bit mchkin0 value are taken as 0s for the current result calculation. note: mchk_ir is a write-only register . any read action will deliver 0000 0000 h . a memory checker result register contains the result of the memory check operation. before starting a checksum calculation operation, it should be written with an initial checksum calculation value. mchk_irx (x = 0-1) memory checker input register (010 h +x*08 h ) reset value: 0000 0000 h 31 0 mchkin w field bits type description mchkin [31:0] w memory checker input the value written to mchkin is used for the next checksum calculation. any r ead action will deliver 0. mchk_rrx (x = 0-1) memory checker result register (014 h +x*08 h ) reset value: 0000 0000 h 31 0 mchkr rwh field bits type description mchkr [31:0] rwh memory checker result this bit field contains the current result of the memory checksum calculat ion operation. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-136 v1.1, 2011-03 dma, v1.6 the memory checker write register is a dummy write-only register that is located within the memory checker address range. the memory checker write register can be used as dummy write register at the write back action of the dma or mli controller move engine when the pattern detection feature of the dma controller is used. accessing mchk_wr with the move engine of the mli or dma controller via the bus switch of the dma controller (see) does not request the two fpi buses of the TC1798, spb and dma, because it is near the mli modules address ranges. the crc registers stor e the working crc32 ethernet polynomial checksum. only 32- bit word accesses are permitted to the crc registers. in order to start a crc32 sequence the crc register must be initialised (e.g. written with 00000000 h or with a desired start value) and a dma transaction set up (start address, length, etc.). when data is written to mchk_irx then a polynomial checksum calculation is performed and mchk_crcx is updated. mchk_wr memory checker write register (020 h ) reset value: 0000 0000 h 31 0 wo w field bits type description wo [31:0] w write-only this write-only bit field is used to write dummy data during dma pattern detection. the data written to wo is not taken into account for any action. any read action of wo will deliver 0000 0000 h . mchk_crcx (x = 0-1) memory checker crc register (024 h +x*04 h ) reset value: 0000 0000 h 31 0 mchkcrc rwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-137 v1.1, 2011-03 dma, v1.6 field bits type description mchkcrc [31:0] rwh memory checker crc this bit field contains the working crc32 ethernet polynomial checksum. the stored value is inverted and reflected prior to a read. therefore if the register is written with all 1?s then the output will be all 0?s. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 direct memory access controller (dma) users manual 12-138 v1.1, 2011-03 dma, v1.6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-1 v1.1, 2011-03 sdma, v1.0 13 safe direct memory access controller (sdma) this chapter describes the safe direct memory access (sdma) controller of the TC1798. it contains the following sections: ? functional description of the sdma controller kernel (see section 13.2 ) ? sdma controller module register description (see section 13.3 ) ? TC1798 implementation-specific details of the sdma controller (interrupt control, address decoding, clock control, see section 13.4 ) note: the sdma kernel register names described in section 13.3 are referenced in the TC1798 users manual by the module name prefix ?sdma_?. 13.1 what is new sdma is based on the dma peripheral. sdma has additional features to support safety critical applications. the principal differences are: ? upper and lower address boundary checking of the source and destination address. ? generation of unique cr c checksums for source and destination addresses. ? generation of in-line crc checksum for read data. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-2 v1.1, 2011-03 sdma, v1.0 13.2 sdma controller kernel description the sdma controller of the TC1798 transfers data from data source locations to data destination locations without intervention of the cpu or other on-chip devices. one data move operation is controlled by one sdma channel. eight sdma channels are provided in one sdma sub-block. the bus switch provides the connection of the sdma sub- block to the on chip bus interfaces and a sdma peripheral interface. in the TC1798, the two on chip bus interfaces are connected to the system peripheral bus. clock control, address decoding, sdma request wiring, and sdma interrupt service request control are implementation-specific and are managed outside the sdma controller kernel. figure 13-1 sdma block diagram interrupt request nodes smcb06149 clock control f dma sr[15:0] safe dma controller arbiter/ switch control bus switch fpi bus interface system peripheral bus dma requests of on-chip periph . units address decoder dma interrupt control ch0n_out dma channels 00-07 safe dma sub-block m request selection/ arbitration transaction control unit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-3 v1.1, 2011-03 sdma, v1.0 13.2.1 features the sdma controller has the following features: ? 8 independent sdma channels ? 1 sdma sub-block with 8 sdma channels ? parallel channel execution ? up to 16 selectable request inputs per sdma channel ? 2-level programmable priority of sdma channels within the sdma sub-block ? software and hardware sdma request ? hardware requests by selected on-chip peripherals and external inputs ? individually programmable operation modes for each sdma channel ? single mode: stops and disables sdma channel after a predefined number of sdma transfers ? continuous mode: sdma channel remains enabled after a predefined number of sdma transfers; sdma transaction can be repeated ? programmable address modification ? two shadow register modes (with / w/o automatic reset and direct write access). ? full 32-bit addressing capability of each sdma channel ? 4 gbyte address range ? data block move > 32 kbyte per sdma transaction ? circular buffer addressing mode with flexible circular buffer sizes ? programmable data width of sdma transfer/ transaction: 8-bit, 16-bit, or 32-bit ? register set for each sdma channel ? source and destination address register ? channel control and status register ? transfer count register ? sdma module is working on fpi frequency. ? read/write requests from the move engine are directed to the fpi bus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-4 v1.1, 2011-03 sdma, v1.0 13.2.2 definition of terms some basic terms must be defined for the functional description of the sdma controller. sdma move a sdma move is an operation that always consists of two parts: 1. a read move that loads data from a data source into the sdma controller 2. a write move that puts data from the sdma controller to a data destination within a sdma move, data is always moved from the data source via the sdma controller to the data destination. data is temporarily stored in the sdma controller. the data widths of read move and write move are always identical (8-bit, 16-bit or 32-bit). data assembly or disassembly is not supported. figure 13-2 sdma de finition of terms sdma transfer a sdma transfer can be composed of 1, 2, 4, 8 or 16 sdma moves. sdma transaction a sdma transaction is composed of several (at least one) sdma transfers. the transfer count determines the number of sdma transfers within one sdma transaction. example: 1024 word (32-bit wide) transactions can be composed of 256 transfers of four sdma word moves, or 128 transfer s of eight sdma word moves. smca06150 data destination sdma controller read move write move safe dma move sdma channel data source www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-5 v1.1, 2011-03 sdma, v1.0 13.2.3 sdma principles the sdma controller supports sdma moves from one address location to another one. sdma moves can be requested either by hardware or by software. sdma hardware requests are triggered by specific request lines from the peripheral modules or from other sdma channels (see figure 13-3 ). the number of available sdma request lines from a peripheral module varies depending on the module functionality. typically, the parallel occurrence of sdma requests and interrupts requests for sdma channels is possible. therefore, the interrupt control unit and the sdma controller can react independently to interrupt and sdma requests that have been generated by one source. figure 13-3 sdma principle the sdma controller mainly consists of a sdma sub-block and a bus switch. once configured, the sdma sub-block is able to act as a master on the fpi bus. smca06151 request dma controller dma sub- block 0 on - chip peripheral unit 1 request request bus switch on - chip peripheral unit 2 on - chip peripheral unit 3 fpi bus lmb bus dma peripheral interface www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-6 v1.1, 2011-03 sdma, v1.0 13.2.4 sdma channel functionality each of the 8 sdma channels has one associated register set containing ten 32-bit registers. these registers are numbered by one index to indicate the related sdma channel: index ?n? refers to the channel number (n = 0-7) within the sdma sub-block. example: chcr04 is the control register of sdma channel 4 in sub-block 0. the register set of a sdma channel register contains the following registers: ? channel 0n control register chcr0n (for details, see page 13-65 ) ? channel 0n status register chsr0n (for details, see page 13-69 ) ? channel 0n interrupt control register chicr0n (for details, see page 13-70 ) ? channel 0n address control register adrcr0n (for details, see page 13-72 ) ? channel 0n source address register sadr0n (for details, see page 13-77 ) ? channel 0n destination address register dadr0n (for details, see page 13-78 ) ? channel 0n shadow address register shadr0n (for details, see page 13-79 ) 13.2.4.1 shadowed source or destination address as a typical application, an asc module that receives data (fixed source address) has to deliver it to a memory buffer using a sd ma transaction (variable destination address). after a certain amount of data has been transferred, a new sdma transaction should be initiated to deliver further asc data into another memory buffer. while the destination address register is updated during a running sdma transaction with the actual destination address, a shadow mechanism allows programming of a new destination address without disturbing the content of the destination address register. in this case, the new destination address is written into a buffer register, i.e. the shadow address register. at the start of the next sdma tr ansaction, the new address is transferred from this shadow address register to the des tination address register without cpu intervention. this shadow mechanism avoids the cpu having to check for the end of a sdma transaction before reprogramming address registers. the shadow address register can be used also to store a source address. however, it cannot store source and destination address at the same time. this means that the shadow mechanism makes it possible to automatically update either a new source address, or a new destination address at the start of a sdma transaction. if both address registers (for source and destination address) have to be updated for the next sdma transaction, a running sdma transaction for this channel must be finished. after that, source and destination address registers can be written before the next sdma transaction is started. figure 13-4 shows the actions that take place when a source address register is updated. the update of a destination register happens in an equivalent manner. when writing a new address to the (address of) the source or destination address register and no sdma transaction is runni ng, the new address value is directly written into the source or destination address register . in this case, no buffering of the address www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-7 v1.1, 2011-03 sdma, v1.0 is required. when writing a new address to the (address of) the source or destination address register and a sdma transaction is running, no transfer to an address register can take place and shadr0n holds the new address value that was written. for this operation, bit field adrcr0n.s hct must be set either to 01 b (address is a source address) or 10 b (new address is a destination address). at the start of the next sdma transaction, the shadow transfer takes place and the content of shadr0n is written either into sadr0n or dadr0n (adrcr0n.shct must be set accordingly). after the shadow transfer, shadr0n is set to 0000 0000 h if the shadow register write enable bit is set to 0 (adrcr0n.shwen = 0). in this case (adrcr0n.shwen = 0), the software can check by reading the shadow address regist er whether or not the shadow transfer has already taken place. only one address register can be shadowed wh ile a transaction is running, because the shadow register can only be assigned either to the source or to the destination address register. note that the shadow address regist er transfer has the same behavior in single and continuous mode. when the shadow mechanism is disabled (adrcr0n.shct = 00 b ), shadr0n is always read as 0000 0000 h . if the shadow address register write enable bit is set to 1 (adrcr0n.shwen = 1), the shadow register shadr0n can be directly written. in this case (adrcr0n.shwen = 1) the value stored in the shadr0n is not modified when the shadow transfer takes place, and the shadow mechanism remains active and the shadow transfer will be repeated until channel 0n is reset or until the value in shadr is 0000 0000 h , is written into the shadow register (direct or indirect by writin g to the source or destination address register according to the shadow control register adrcr0n.shct). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-8 v1.1, 2011-03 sdma, v1.0 figure 13-4 source address update (m=0) the transfer count of a sdma transaction, stored in bit field chcr0n.trel, can also be programmed if the sdma transaction is running. at the start of a sdma transaction, trel is transferred to bit field chsr0n.tc ount, which is then updated during the sdma transaction. no reload of address or counter will be done if tcount is not equal to 0. the reprogramming of channel specific valu es (except for the selected address shadow register) should be avoided while a sdma channel is active. mca06152 write new source address to ( address of ) sadrmn no new transaction started ? & (adrcrmn.shct = 01 b ) yes no content of shadr0n is transferred into sadrmn . if adrcrmn.shwen = 0 then shadrmn := 00000000 h yes transaction running ? (chsrmn.tcount != 0 or trsr.chmn = 1) new source address is directly transferred into sadrmn store new source address intermediately in shadrmn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-9 v1.1, 2011-03 sdma, v1.0 figure 13-5 shadow source address and transfer count update with adrcr0n.shwen = 0 (m = 0) figure 13-5 shows how the contents of the source address register sadr0n and the transfer count chsr0n.tcount are updated during two sdma transactions with a shadowed source address and transfer count update. at reference point 2) the sdma transaction 1 is finished and sdma transaction 2 is started. at 1) the sdma channel is reprog rammed with two new parameters for the next sdma transaction: transfer count tc2 and so urce address sa2. source address sa2 is buffered in sadr0n and transferred to sadr0n when the new sdma transaction is started at 2). at this time, transfer count tc2 is also transferred to chsr0n.tcount. note that the shadow address register is only reset by hardware to 0000 0000 h as shown in this example, if the write enable bit is set to 0 (adrcr0n.shwen = 0). mct06153 tc1 = transfer count 1 tc2 = transfer count 2 sa1 = source address 1 sa2 = source address 2 tc1 1 tc1-1 tc2 tc2-1 tc2-2 tc1 tc2 tc3 sa1 sa1+1 sa2+1 sa2+2 sa2 tc1-1 sa1+ tc1 sa1+ sa2 sa3 1) 3) = writing to chcrmn and sadrmn 2) = start of new dma transaction with shadow transfer of source address 0000 0000 h 0 chsrmn.tcount shadrmn with adrcrmn.shct= 01 b sadrmn chcrmn.trel 1) 3) 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-10 v1.1, 2011-03 sdma, v1.0 13.2.4.2 sdma channe l request control figure 13-6 shows the control logic for sdma requests that is implemented for each sdma channel. figure 13-6 channel request control(m = 0) two different types of sdma requests are possible: ? hardware sdma requests ? software sdma requests the hardware request ch0n_req can be connected to one of sixteen possible hardware request input lines as select ed by bit field chcr0n.prsel. the hardware request input structure for chcr0n.prsel incl udes a positive edge detector as the sdma channels requires single pulse requests. hardware requests are enabled/disabled by status bit trsr.htre0n. htre0n can be set/reset by software or by hardware in single mode at the end of a sdma transaction. a software request can be generated by setting bit streq.sch0n. mca06154c trsr transfer request to channel arbiter htremn streq schmn & trsr chmn set reset chcrmn rroat end of transfer reset set reset m u x chcrmn chmode suspend control & susenmn suspmr trsr 0 1 end of transaction dchmn echmn htreq suspend request & transfer request lost interrupt errsr trlmn & set chrstr chmn end of transaction 1 1 pattern match reset reset m u x 4 chcrmn prsel chmn_req chmn_reqi00 chmn_reqi01 chmn_reqi02 chmn_reqi13 chmn_reqi14 chmn_reqi15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-11 v1.1, 2011-03 sdma, v1.0 status flag trsr.ch0n indicates whether or not a software or hardware generated sdma request for sdma channel 0n is pending. trsr.ch0n can be reset by software or by hardware at the end of a sdma transfer (rroat = 0) or at the end of a sdma transaction (rroat = 1). if a software or a hardware sdma request is detected for channel 0n while trsr.ch0n is set, a request lost event occurs. this error event indicates that the sdma is already processing a transfer and that another trans fer has been requested before the end of the previous one. in this case, bit errsr.trl0n will be set and a transfer lost interrupt can be generated. 13.2.4.3 sdma channel operation modes the operation mode of a sdma channel is individually programmable for each sdma channel n. basically, a sdma channel can operate in the following modes: ? software controlled mode ? hardware controlled mode, in single or continuous mode in software-controlled mode, a sdma channel request is generated by setting a control bit. in hardware-controlled mode, a sdma channel request is generated by request signals typically generated by on-chip peripheral units. in hardware-controlled single mode, a sdma channel n becomes disabled by hardware after the last sdma transfer of its sdma transaction. in hardware-controlled continuous mode, a sdma channel n remains enabled after the last sdma transfer of its sdma transaction. in hardware- and software-controlled mode, a sdma request signal can be configured to trigger a complete sdma transaction or one single transfer. software-controlled modes in software-controlled mode, one software request starts one complete sdma transaction or one single sdma transfer. software-controlled modes are selected by writing htreq.dch0n = 1. this forces status flag trsr.htre0n = 0 (hardware request of sdma channel 0n is disabled). the software-controlled mode that initiates one complete sdma transaction to be executed is selected for sdma channel 0n by the following write operations: ? chcr0n.rroat = 1 ?streq.sch0n=1 setting streq.sch0n to 1 (this is the software request) causes the sdma transaction of sdma channel 0n to be started and trsr.ch0n to be set. at the start of the sdma transaction, the value of chcr0n.trel is loaded into chsr0n.tcount (transfer count or tc) and the sdma transfers are executed. after each sdma transfer, tcount becomes decremented and next source and destination addresses are calculated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-12 v1.1, 2011-03 sdma, v1.0 when tcount reaches the 0, sdma channel 0n becomes disabled and status flag trsr.ch0n is reset. setting streq.sch0n again starts a new sdma transaction of sdma channel 0n with the parameters as actually defined in the channel register set. the software-controlled mode that initiates a single sdma transfer to be executed is selected for sdma channel 0n by the following write operations: ? chcr0n.rroat = 0 ? streq.sch0n = 1, repeated for each sdma transfer when chcr0n.rroat = 0, trsr.ch0n becomes reset after each sdma transfer of the sdma transaction and a new software request (writing streq.sch0n = 1) must be generated for starting the next sdma transfer. figure 13-7 software controll ed mode operation (m = 0) tr0 tr1 trn tc-1 tc = initial transfer count tr0 tr1 0tc 1 0 tc tc-1 mct06155 tr0 tr1 trn tc = initial transfer count 0 tc 0 chcrmn .rroat = 1 chcrmn.rroat = 0 1 tc-1 chsrmn.tcount dma transfer mn trsr.chmn intmn (triggered by tcount = 0) writing streq.schmn = 1 chsrmn.tcount dma transfer mn trsr.chmn intmn (triggered by tcount = 0) writing streq.schmn = 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-13 v1.1, 2011-03 sdma, v1.0 hardware-controlled modes in hardware-controlled modes, a hardware request signal starts a sdma transaction or a single sdma transfer. there are two hardware-controlled modes available: ? single mode: hardware requests are disabled by hardware after a sdma transaction ? continuous mode: hardware requests are not disabled by hardware after a sdma transaction hardware-controlled single mode in hardware-controlled single modes, one hardware request starts one complete sdma transaction or one single sdma transfer. the hardware-controlled single mode that initiates one complete sdma transaction to be executed for sdma channel 0n is selected by the following operations: ? chcr0n.chmode = 0 ? chcr0n.rroat = 1 ? selecting one of the sixteen hardware request inputs via chcr0n.prsel ? htreq.ech0n = 1 setting htreq.ech0n to 1 causes the hardware request ch0n_req of channel 0n to be enabled (trsr.htre0n = 1). whenever the hardware request ch0n_req becomes active, the value of chcr0n.trel is loaded into chsr0n.tcount and the sdma transaction is started by executing its first sdma transfer. after each sdma transfer, tcount becomes decremented and next source and destination addresses are calculated. when tcount reaches the 0, sdma channel 0n becomes disabled and status flags trsr.ch0n and trsr.htre0n are reset. in order to start a new hardware- controlled sdma transaction, hardware requests must be enabled again by setting trsr.htre0n through htreq.ech0n = 1. the hardware request disable function in single mode is typically needed when a reprogramming of the sdma channel register set (addresses, transfer count) is required before the next hardware triggered sdma transaction is started. the hardware-controlled single mode in which each single sdma transfer has to be requested by a hardware request signal is selected as described above, with one difference: ? chcr0n.rroat = 0 in this operation mode, trsr.ch0n becomes reset after each sdma transfer of the sdma transaction, and a new hardware request at ch0n_req must be generated for starting the next sdma transfer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-14 v1.1, 2011-03 sdma, v1.0 figure 13-8 hardware-controlled single mode operation (m = 0) hardware-controlled continuous mode in hardware-controlled continuous mode (chcr0n.chmode = 1), the hardware transaction request enable bit htre0n is not reset at the end of a sdma transaction. a new transaction of sdma channel 0n with the parameters actually stored in the channel register set of sdma channel 0n is started each time when chsr0n.tcount = 0 at the end of the sdma transaction. no software re-enable for a hardware request at ch0n_req is required. mct06156 tc = initial transfer count tc = initial transfer count chcrmn.rroat = 1 chcrmn.rroat = 0 tr0 tr1 trn tc-1 tr0 tr1 0 tc tc-1 0 1 tc tr0 tc-1 tc tr1 trn-1 trn 0 0 21 tc tr0 trsr.htremn chmn_req int (triggered at the end of a transaction with irdv=0) chsrmn.tcount dma transfer mn trsr.chmn trsr.htremn chmn_req trsr.chmn dma transfer mn chsrmn.tcount int (triggered at the end of a transaction with irdv=0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-15 v1.1, 2011-03 sdma, v1.0 combined software/hard ware-controlled mode figure 13-9 shows how software- and hardware-controlled modes can be combined. in the example, the first sdma transfer is triggered by software when setting streq.sch0n. hardware requests are still disabled. after hardware requests have been enabled by setting htreq.ech0n, subs equent sdma transfers are triggered now by hardware request coming from the ch0n_req line. in the example, sdma channel 0n operates in single mode (chcr0n.chmode = 0). in this mode, trsr.htre0n becomes reset by hardware when chsr0n.tcount = 0 at the end of the sdma transaction. figure 13-9 transaction start by software, continuation by hardware (m = 0) if an sdma channel is configured to be triggered by parallel hardware and software requests then if the requests collide in the same clock cycle then a transaction/transfer request lost event will be flagged in the sdma error status register. 13.2.4.4 error conditions the bus error flag errsr.fpier indicates an fpi bus error (spb) that occurred during a source move (read or write) of a sdma module transaction. the source error flag errsr.me0ser indicates than an error occurred during source move (read) of a sdma transaction of sdma sub-block 0. mct06157 tc = initial transfer count tr0 trn-1 trn tr1 tc-1 tc 0 0 2 1 trsr.chmn writing streq.schmn=1 writing htreq.echmn=1 trsr.htremn chmn_req dma transfer mn chsrmn.tcount int (triggered at the end of a transaction with irdv =0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-16 v1.1, 2011-03 sdma, v1.0 the destination error flag errsr.me0der indicates than an error occurred during destination move (write) of a sdma transaction of sdma sub-block 0 the transaction lost error flag errsr.trl0n indicates if a sdma request for a sdma channel 0n has been lost. in the case of a read error, the write action is not executed, but the destination address is updated. in the case of multiple errors, the error bits are set according to the error situations. this means that more than bus error flag can be set and that source/destination flags can be set. 13.2.4.5 channel reset operation a sdma transaction of sdma channel 0n can be stopped (channel is reset) by setting bit chrstr.ch0n. when a read or write on chip bus transaction of sdma channel 0n is executed at the time when chrstr.ch0n is set, this on chip bus transaction is finished normally. this behavior guarantees data consistency. when chrstr.ch0n is set to 1: ? bits trsr.htre0n, trsr.ch0n, errsr.trl0n, intsr.ich0n, intsr.ipm0n, wrpsr.wrpd0n, wrpsr.wrps0n, chsr0n.lxo, and bit field chsr0n.tcount are reset. ? source and destination address register will be set to the wrap boundary. shadr0n will be cleared. ? all automatic functions are stopped for channel 0n. a user program must execute the following steps for resetting a sdma channel: 1. if hardware requests are enabled for the sdma channel 0n, disable the sdma channel 0n hardware requests by setting htreq.ech0n = 0. 2. writing a 1 to chrstr.ch0n. 3. waiting (polling) until chrstr.ch0n = 0. a user program should execute the following steps for restarting a sdma channel after it was reset: 1. optionally (re-)configuring the address and other channel registers. 2. restarting the sdma channel 0n by setting htreq.ech0n = 1 for hardware requests or streq.sch0n = 1 for software requests. the value of chcr0n.trel is copied to chsr0n.tcount when a new sdma transaction is requested and shadow address register contents is not equal 0000 0000 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-17 v1.1, 2011-03 sdma, v1.0 13.2.4.6 transfer count and move count the move count determines the number of moves (consisting of one read and one write each) to be done in each transfer. it allows the user to indicate to the sdma the number of moves to be done after one request. the number of moves per transfer is selected by the block mode settings (chcr0n.blkm). figure 13-10 transfer and move count (m = 0) after a sdma move, the next source and destination addresses are calculated. source and destination addresses are calculated independently of each other. the following address calculation parameters can be selected: ? the address offset, which is a multiple of the selected data width ? the offset direction: addition, subtraction, or none (unchanged address) control bits in address control register adrcr0n determine how the addresses are incremented/decremented. further, the data width as defined in chcr0n.chdw is taken into account for the address calculation. figure 13-11 and figure 13-12 show two examples of address calculation. in both examples, a data width of 16-bit (chcr0n.chdw = 01 b ) is assumed. tc-1 1 tc mct06158 chsrmn. tcount dma moves chmn_req 0 0 tc = initial transfer count transfer 0 transaction m1 m2 mx transfer 1 m1 m2 mx transfer n m1 m2 mx www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-18 v1.1, 2011-03 sdma, v1.0 figure 13-11 programmable address modification - example 1 (m = 0) in figure 13-11 , 16-bit half-words are transferred from a source memory with an incrementing source address offset of 10 h to a destination memory with decrementing destination addresses offset of 08 h . in figure 13-12 , 16-bit half-words are transferred from a source memory with an incrementing source address offset of 02 h to a destination memory with incrementing destination addresses offset of 04 h . mca06159 adrcrmn parameters : smf = 011 b incs = 1 source memory destination memory d1 d0 31 0 15 16 dma moves 00 h d1 .... 31 0 15 16 04 h 08 h 0c h 10 h 14 h 18 h 1c h adrcrmn parameters : dmf = 010 b incd = 0 d0 .... 00 h 04 h 08 h 0c h 10 h 14 h 18 h 1c h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-19 v1.1, 2011-03 sdma, v1.0 figure 13-12 programmable address modification - example 2 (m = 0) 13.2.4.7 circular buffer destination and source address can be configured to build a circular buffer separately for source and destination data. within this circular buffer, addresses are updated as defined in figure 13-11 and figure 13-12 with a wrap-around at the buffer limits. the circular buffer length is determined by bit fields adrcr0n.cbls (for the source buffer) and adrcr0n.cbld (for the destination buffer) . these 4-bit wide bit fields determine which bits of the 32-bit address remain unchanged at an address update. possible buffer sizes of the circular buffers can be 2 cbls or 2 cbld bytes (= 1, 2, 4, 8, 16, ? up to 32k bytes). when source or destination addresses are u pdated (incremented or decremented) after a sdma move, all upper bits [31:cbls] of source address and [31:cbld] of destination address are frozen and remain unchanged, even if a wrap-around from the lower address bits [cbls:0] or [cbld:0] occurr ed. this address-freezing mechanism always causes the circular buffers to be aligned to a multiple integer value of its size. if the circular buffer size is less or equal than the selected address offset (see table 13-7 ), the same circular buffer address will always be accessed. mca06160 adrcrmn parameters : smf = 000 b incs = 1 source memory destination memory 00 h d0 31 0 15 16 dma moves 04 h 08 h 0c h 10 h 14 h 18 h 1c h 00 h d4 31 0 15 16 04 h 08 h 0c h 10 h 14 h 18 h 1c h adrcrmn parameters : dmf = 001 b incd = 1 d6 d1 d2 d3 d4 d5 d6 d7 d7 d5 d3 d1 d2 d0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-20 v1.1, 2011-03 sdma, v1.0 13.2.5 transaction control engine the transaction control unit in the sdma sub-block, as shown in the sdma controller block diagram in figure 13-1 , contains a channel arbiter and a move engine. the channel arbiter arbitrates the transfer r equests of the sdma channels, and submits the transfers parameters of the sdma channel with the highest channel priority that are needed for a sdma transfer to the move engine. sdma channels within a sdma sub- block have a two-level programmable channel priority as defined by bit chcr0n.chprio. when two transfer requests of two different sdma channels with identical channel priority become active at the same time, the sdma channel with the lowest channel number (n) is serviced first. the move engine handles the execution of a sdma transfer that has been detected by the channel arbiter to be the next one. the move engine requests the required buses and loads or stores data according to the par ameters of a sdma transfer. it is able to wait if a targeted bus is not available. in the move engine, a sdma transfer of a sdma transaction cannot be interrupted and always get finished. this means that a sdma transfer, which can also be composed of several data moves (read move and write move), cannot be interrupted by a transfer of another sdma channel. after a sdma transfer is finished, the move engine will send back the actualized address register information to the related sdma channel. possible error conditions are also reported. figure 13-13 transaction control engine (m = 0) smca06161 safe dma ch 00 safe dma ch 01 safe dma ch 02 safe dma ch 03 safe dma ch 04 safe dma ch 05 safe dma ch 06 safe dma ch 07 sdma channel arbiter sdma channels 0n of sub-block m safe move engine m transaction control unit m bus switch www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-21 v1.1, 2011-03 sdma, v1.0 13.2.6 bus switch, bus switch priorities the bus switch of the sdma controller provides the connection from the sdma sub- block to the on chip bus system peripheral bus master interface and to the sdma peripheral interface (see figure 13-14 ). the sdma module working frequency is identical to the fpi bus frequency. figure 13-14 bus switch one access can be buffered in the bus interface. note: the accesses of the sdma move engine?s bus interfaces to the on chip bus interfaces are always done in supervisor mode. a move engine write has priority over a move engine read. 13.2.7 sdma module: on chip bus access rights, rmw support all accesses triggered by the sdma move engine are always done in sv mode. the sdma module does not support read/modify write instructions. 13.2.8 sdma on chip bus fpi master interface the sdma on chip bus fpi master interfaces supports: smca06162 buffer m/s fpi bus interface fpi arbiter/ switch control safe move engine m dma sub-block m bus switch www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-22 v1.1, 2011-03 sdma, v1.0 ? single data read and write tr ansactions (8bit, 16bit, 32bit) ? de-assertion of request after retry in order to prevent bus blocking. the move engine generates read - write sequences and supports only one transaction at a time. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-23 v1.1, 2011-03 sdma, v1.0 13.2.9 on-chip debug capabilities the sdma controller in the TC1798 prov ides some debugging capabilities. these debug features support: ? soft-suspend mode of sdma channels ? break signal generation ? trace signal generation in soft-suspend mode, the operations of sdma channels are stopped. pending read or write transfers in the sdma module on chip bus master interface are finished. under certain conditions also a break signal is generated for the on-chip debug support logic. further, sdma trace information can be output. in soft-suspend mode, the sdma module provi des access to all control registers of the sdma module. 13.2.9.1 hard-suspend mode the hard-suspend mode is controlled in the TC1798 sdma module clc register. 13.2.9.2 soft-suspend mode the TC1798 on-chip debug control unit is able to generate a soft-suspend mode request (susreq) for the sdma controller. when this soft-suspend request becomes active, the state of a sdma channel becomes fr ozen regarding hardware changes to ensure that the state of the sdma channels can be analyzed by reading the register contents. pending read or write transfers in the sdma module on chip bus fpi master interface are finished. the sdma controller signals its soft suspend mode back to the on-chip debug control via an soft-suspend acknowledge. the soft-suspend acknowledge becomes active when all sdma channels 0n that are enabled for the soft-suspend mode have set its suspend active status flag suspmr.susac0n. soft-suspend mode of sdma channel 0n is entered if its suspend enable bit susen0n in the suspend mode register suspmr is set. when susreq becomes active, the operation of all sdma channels 0n that are enabled for soft-suspend mode is stopped automatically after its current sdma transfers have been finished in the transaction control unit. afterwards, the suspend active status flag suspmr.susac0n is set, indicating that sdma channel 0n is in soft-suspend mode. sdma channels that are disabled for suspend mode (susen0n = 0) continue with its normal operation. in soft-suspend mode, register contents can be modified. these modifications are taken into account for further sdma transactions or sdma transfers of the related sdma channel after suspend mode has been left again. suspend mode of sdma channel 0n is left and its normal operation continues if either the susreq signal becomes inactive, or if the enable bit susen0n is reset by software. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-24 v1.1, 2011-03 sdma, v1.0 figure 13-15 soft-suspend mode control (m = 0) 13.2.9.3 break signal generation the sdma controller provides one break output signal that is generated for the on-chip debug support logic (see figure 13-16 ). the sdma sub-block is able to detect two break conditions: ? transaction lost interrupt has occurred ? sdma request transitions, indicated by bits trsr.ch0n the output lines of the two break conditions in the sdma sub-block are or-ed together to the break output signal. a transaction lost break condition occurs in sdma sub-block whenever at least one of its eight transaction lost interrupts becomes active, and when enable bit ocdsr.brl0 is set. the transaction lost interrupts do not generate a break condition if ocdsr.brl0 = 0. transaction interrupt control is described in section 13.2.10.2 . the second break condition of sdma sub-block becomes active when the transaction request bit trsr.ch0n of one of its eight sdma channels n (as selected by ocdsr.bchsn) indicates a transition of its state. the ch0n transition type (change from no request is pending to request is pending, change from request is pending to no request is pending, changes in both directions) is selected by bit field ocdsr.btcrn. mca06163 soft suspend control transfer request to channel arbiter trsr chmn & susreq susacmn suspmr set susenmn suspmr transaction control unit m (move engine m ) & susack www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-25 v1.1, 2011-03 sdma, v1.0 figure 13-16 sdma break ev ent generation (m = 0) trsr ch01 brea k bchs0 ocdsr trsr ch07 edge detection btcr0 ocdsr & brl0 ocdsr enabled transaction lost interrupts 00- 07 dma sub-block m mca06164 3 2 1 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-26 v1.1, 2011-03 sdma, v1.0 13.2.10 interrupts the interrupt structure of the sdma controller is a very flexible control logic that allows an interrupt coming from an interrupt source within four interrupt source types to be connected to each of the sixteen interrupt outputs. this permits, for example, sdma channels that very rarely generate interrupts to share one interrupt node. the remaining interrupt nodes can be assigned to dedicated sdma channels to reduce the interrupt overhead for these channels. the f our interrupt source types are: ? channel interrupts ? transaction lost interrupt ? move engine interrupts ? wrap buffer interrupts some of the interrupt functions are common to all of the four interrupt source types. an interrupt event, internally generated as a request pulse, is always stored in an interrupt status flag. this interrupt status flag can be reset by software. further, the interrupt event can be enabled or disabled. when an interr upt event is enabled, a 4-bit interrupt node pointer determines which of the sixteen interrupt outputs will be activated. the following sections describe each of the four interrupt source types in more detail. 13.2.10.1 channel interrupts each sdma channel 0n has one associated channel interrupt. it can always be activated after a sdma transfer, or when chsr0n.tcount matches with the value of bit field chicr0n.irdv after it has been decremented after a sdma transfer. the pattern detection interrupts that are combined with the channel interrupts (one common interrupt node pointer chicr0n.intp) are activated when the pattern detection interrupt of sdma channel 0n becomes active (when enabled by chcr0n.patsel not equal 00 b ). a channel interrupt of sdma channel 0n is indicated when status flag intsr.ich0n is set. the status flags ich0n and ipm0n can be reset together by software when setting bit intcr.cich0n (or chrstr.ch0n). the channel interrupt of sdma channel 0n is enabled when bit chicr0n.intct[1] is set. the channel interrupt pointer chicr0n.intp determines which of the interrupt outputs sr[15:0] 1) will be activated on an active channel interrupt or pattern detection interrupt. note that the signal that is set signal for the ich0n flag is available as ch0n_out signal at the sdma module boundary. bit chicr0n.intct[0] selects these two types of interrupt sources. for the compare operation, bit field irdv (4-bit) is zero-extended to 10-bit and then compared with the 10-bit tcount value. this means that a tcount match interrupt can be generated after one of the last 16 sdma transfers of a sdma transaction. note that with 1) in the TC1798, only sr[7:0] are connected to in terrupt nodes. sr[8:15] are used for sdma channel triggering/connections. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-27 v1.1, 2011-03 sdma, v1.0 irdv = 0000 b , the match interrupt is generated at the end of a sdma transaction (after the last sdma transfer). the pattern detection interrupt is indicated when status flag intsr.ipm0n is set. the status flags ipm0n and ich0n can be reset together by software when setting bit intcr.cich0n (or chrstr.ch0n). the pattern detection interrupt of sdma channel 0n is enabled when bit chcr0n.patsel is set to a value not equal to 00 b . the channel interrupt pointer chicr0n.intp defines which of the interrupt outputs sr[15:0] will be activated on a pattern detection interrupt or the channel interrupt pointer chicr0n.intp determines which of the interrupt outputs sr[15:0] 1) will be activated on a pattern detection or channel interrupt. figure 13-17 channel interrupts (m = 0) 1) in the TC1798, sr[7:0] are connected to in terrupt nodes. sr[8:15] are used for sdma channel triggering/connections. 1 mca06165 intp chicrmn intcr ichmn intsr intct[0] m u x 0 1 chicrmn intct[1] chicrmn cichmn set chmn_out patsel chcrmn ipmmn intsr set reset reset chrstr chmn enabled if patsel 00 b 4 n = 0 -7 chsrmn.tcount decremented chsrmn.tcount matches with chicrmn.irdv pattern detection interrupt mn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-28 v1.1, 2011-03 sdma, v1.0 13.2.10.2 transaction lost interrupt each sdma channel 0n is able to detect a transaction request lost condition. this condition becomes true when a new hardware or software sdma request occurs while the previous transaction or transfer on sd ma channel 0n is not finished, indicated by trsr.ch0n still set. if such a transaction request lo st condition occurs, bit errsr.trl0n is set. the transaction lost interrupts of all sdma channels are or-ed together to one common transaction lost interrupt that can be directed to one of the interrupt outputs sr[15:0] 1) by setting the transaction lost interrupt pointer eer.trlinp with a corresponding value. a transaction request lost condition of sdma channel 0n is indicated by status flag errsr.trl0n, which can be reset by setting bit clre.ctl0n or chrstr.ch0n. the transaction lost interrupt for sdma channel 0n is enabled when bit eer.etrl0n is set. figure 13-18 transaction lost interrupt 1) in the TC1798 sr[7:0] are connected to interrupt nodes. sr[15:8] are used as sdma channel trigger signals. 1 mca06166 trl00 transaction lost interrupt 00 etrl00 trlinp eer eer clre reset ctl00 eersr trl07 transaction lost interrupt 07 etrl07 eer clre ctl07 eersr n = 0 -7 set chrstr ch00 reset chrstr ch07 set reset 4 reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-29 v1.1, 2011-03 sdma, v1.0 13.2.10.3 move engine interrupt the move engine is able to detect error conditions that occur during accesses to the fpi bus interfaces of the bus switch (see figure 13-14 ). two error conditions can be detected: ? source error ? destination error a source error indicates an fpi bus error that occurred during a read move from the data source. a destination error indicates an fpi bus error that occurred during a write move to the data destination. a source error of move engine 0 is indicated by the status flag errsr.me0ser. status flag me0ser can be reset by software when setting bit clre.cme0ser. the source error interrupt of the move engine 0 is enabled when bit eer.eme0ser is set. separate reset, status, and enable bits are available in the move engine for source error condition, as well as for destination error condition. the move engine?s interrupts can be directed to one of the interrupt outputs sr[15:0] 1) by setting the move engine interrupt pointer eer.me0inp with a co rresponding value. note that in case of a read move error, the write move is not executed but the destination address is updated. figure 13-19 move engine interrupts 1) in the TC1798 sr[7:0] are connected to interrupt nodes. sr[15:8] are used as sdma channel trigger signals. mca06167 me0ser move engine 0 source error interrupt eme0ser 1 me0inp eer eer clre reset cme0ser errsr me0der eme0der eer clre reset cme0der errsr move engine 0 destination error interrupt set set 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-30 v1.1, 2011-03 sdma, v1.0 13.2.10.4 wrap buffer interrupts each sdma channel 0n is able to generate a wrap buffer interrupt for source buffer or destination buffer overflow. further details on the pattern detection are described in section 13.2.11 . a wrap source buffer interrupt of sdma channel 0n is indicated by status flag wrpsr.wrps0n. a wrap destination buffer interrupt of sdma channel 0n is indicated by the status flag wrpsr.wrpd0n. both interrupt status flags can be reset by software when bit intcr.cwrp0n (or chrstr.ch0n becomes set). the wrap source buffer interrupt is enabled when bit chicr0n.wr pse is set. the wrap destination buffer interrupt is enabled when bit chicr0n.wrpde is set. the two interrupts for wrap source buffer and wrap destination buffer are or-ed together to one common wrap buffer interrupt of sdma channel 0n that can be directed to one of the interrupt outputs sr[15:0] 1) by setting the wrap buffer interrupt pointer chicr0n.wrpp with a corresponding value. note that the pattern match should not be enabled while a wrap interrupt is enabled for the same channel. figure 13-20 sdma wrap buffer interrupts (m = 0) 1) in the TC1798 sr[7:0] are connected to interrupt nodes. sr[15:8] are used as sdma channel trigger signals. 1 mca06168 wrps0n wrap source buffer interrupt 0n wrpse wrpp chicr0n chicr0n intcr reset cwrp0n wrpsr wrpd0n wrpde chicr0n reset wrpsr wrap destination buffer interrupt 0n n = 0-7 set set chrstr ch0n 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-31 v1.1, 2011-03 sdma, v1.0 13.2.10.5 interrupt request compressor the interrupt control logic of the sdma controller uses an interrupt compressing scheme that allows high flexibility in interrupt processing. the request compressor logic as shown in figure 13-21 condenses the 8 + 1 + 1 + 8 = 18 interrupt sources to the sixteen interrupt outputs. each internal interrupt source can be directed to one of the sixteen interrupt outputs sr[15:0] 1) by using a 4-bit interrupt node pointer. this also allows the connection of more than one interrupt source to one interrupt output srx. each interrupt output sr[15:0] 1) can also be activated by writing a 1 to the corresponding bit gintr.sidmax. 1) in the TC1798 sr[7:0] are connected to interrupt nodes . sr[15:8] are used as sdma channel trigger signals. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-32 v1.1, 2011-03 sdma, v1.0 figure 13-21 sdma interrupt request compressor (m = 0) 13.2.11 pattern detection the move engine in the sdma sub-block prov ides a register me0r that contains the data that was read during the last read move. parts of this read move data can be compared after the read move to data that is stored in the move engine pattern register me0pr of sdma sub-block 0. the result of this pattern compare match is always stored in a bit (lxo) of the channel status register of the sdma channel 0n that is currently executing the sdma move. therefore, the patt ern match result lxo of the previous read mca06169 intp chicrmn mem sdma channel interrupts (8) & pattern det. interrupts (8) trlinp eer meminp eer move engine m interrupts ( 1) wrpp chicrmn mem sdma channel wrap buffer interrupts (8) interrupt output sr0 to sr1 interrupt output sr15 sidma0 chicrmn sidma15 chicrmn to sr14 mem transaction lost interrupts (1) to sr1 to sr14 to sr1 to sr14 to sr1 to sr14 1 1 4 4 4 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-33 v1.1, 2011-03 sdma, v1.0 move can also be combined together with the pattern match result of the actual read move. me0r is overwritten with each read move. as the compare match patterns are stored in the move engine 0 (register me0pr), its compare patterns are used for all sdma cha nnels that are assigned to move engine 0 (all sdma channels of the sdma sub-block 0). the configuration and capabilities of the pattern detection logic further depends on the settings of chcr0n.chdw. chdw determines the data width for the read and write moves individually for each sdma channel 0n. another control bit, chcr0n.patsel, selects among the different operating modes for a specific value of chdw. depending on chcr0n.patsel and on the positive result of the comparison, two actions follow (if chcr0n.patsel=00, no action will be taken when a pattern match is detected, so the wrap interrupt can be used): ? the activation of the interrupt corresponding to the current active channel 0n using the interrupt pointer defined in chicr0n.intp. ? reset trsr.htre0n and trsr.ch0n in order to stop the current transaction (hardware and software request enable). the value of chsr0n.tcount can be read out by the interrupt software. the software will have to service the interrupt an d to activate again the channel. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-34 v1.1, 2011-03 sdma, v1.0 13.2.11.1 pattern compare logic read move data and compare match patterns are compared on a bit-wise level. the logic as shown in figure 13-22 is implemented in each comp block of figure 13-23 , figure 13-24 , and figure 13-25 . one comp block controls either 8 bits or 16 bits of data and makes it possible to mask each data bit for the compare operation. in the compare logic for one bit of the comp block, a data bit from register me0r is compared to the corresponding pattern bit stor ed in register me0pr. if both bits are equal and a pattern mask bit stored in another part of register me0pr is 0, the compare matched condition becomes active. when the pattern mask bit is set to 1, the compare matched condition is always active (set) for the related bit. when the compare matched conditions for each bit within a comp block are true, the compare match output line of the comp block becomes active. figure 13-22 pattern compare logic (comp block) mca06170 & data from me0pr register mask from me0pr register compare logic for 1 bit compare logics of other bits data from me0r register =1 mask compare match output 1 n n n 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-35 v1.1, 2011-03 sdma, v1.0 13.2.11.2 pattern detection for 8-bit data width when 8-bit channel data width is selected (chcr0n.chdw = 00 b ), the pattern detection logic is configured as shown in figure 13-23 . three compare match configurations are possible. when 8-bit channel data width is selected, the pattern detection logic allows the byte of one read move to be compared with two different patterns. further, after each read move the pattern match result ?rd00 with pat01, masked by pat03? is stored in bit chcr0n.lxo. this operating mode allows, fo r example, two-byte sequences to be detected in an 8-bit data stream coming from a serial peripheral unit with 8-bit data width (e.g.: recognition of carriage-return, line-feed characters). a mask operation of each compared bit is possible. figure 13-23 pattern detection fo r 8-bit data width (chcrmn.chdw = 00 b ) table 13-1 pattern detectio n for 8-bit data width chcr0n. patsel pattern detection operating modes 00 b pattern detection disabled 01 b pattern compare of rd00 to pat00, masked by pat02 10 b pattern compare of rd00 to pat01, masked by pat03 11 b pattern compare of rd00 to pat00, masked by pat02 of the actual read move and pattern compare of rd00 to pat01, masked by pat03 of the previous read move of sdma channel 0n mca06171 rd0[3] rd0[2] rd0[1] rd0[0] comp 10 2 & patsel chcrxz pattern detected 11 lxo chsrxz mexr mexpr 1) 1) compare result is clocked into lxo after each read move mask mask pat 0[3] pat0 [2] pat 0[0 ] pat0[1] comp 01 00 0 31 7 0 8 0 31 15 16 7 8 23 24 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-36 v1.1, 2011-03 sdma, v1.0 (m = 0) 13.2.11.3 pattern detection for 16-bit data width when 16-bit channel data width is selected (chcr0n.chdw = 01b) the pattern detection logic can be configured as shown in figure 13-24 . three compare match configurations are possible. when 16-bit channel data width is selected, the pattern detection logic makes it possible to compare the complete half-word of one read move only (aligned mode) or to compare upper and lower byte of two consecutive read moves (unaligned modes). both modes can be combined (combined mode) too. a mask operation of each compared bit is possible. in unaligned mode 1 (source address decremented), the high byte (rd01) of the current and the low byte (rd00) of the prev ious 16-bit read move are compared. in unaligned mode 2 (source address incremen ted), the low byte (rd00) of the current and the high byte (rd01) of the previous 16-bit read move are compared. if it is not known on which byte boundary (e ven or odd address) the 16-bit pattern to be detected is located, the combined mode should be used. this mode is the most flexible table 13-2 pattern detection for 16-bit data width chcr0n. patsel adrcr0n. incs pattern detection operating modes 00 b ? pattern detection disabled 01 b ? aligned mode: pattern compare of rd0[1:0] to pat0[1:0], masked by pat0[3:2] 10 b 0 unaligned mode 1 (source address decrement): pattern compare of rd01 to pat00, masked by pat02 of the actual read move and pattern compare of rd00 to pat01, masked by pat03 (lxo) of the previous read move of sdma channel 0n 1 unaligned mode 2 (source address increment): pattern compare of rd00 to pat01, masked by pat03 of the actual read move and pattern compare of rd01 to pat00, masked by pat02 (lxo) of the previous read move of sdma channel 0n 11 b 0 or 1 combined mode: pattern compare for aligned mode (patsel = 01 b ) or unaligned modes (patsel = 10 b ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-37 v1.1, 2011-03 sdma, v1.0 mode that combines the pattern search capability for aligned and unaligned 16-bit data searches. figure 13-24 pattern detection for 16-bit data width (chcrmn.chdw = 01 b ) (m = 0) 2 mca06172 0 pat0[3] pat0[2] pat0[1] pat0[0] 31 & patsel chcrxz pattern detected lxo chsrxz mexpr comp rd 0[3] rd0 [2 ] rd0[1] rd0[0] 31 15 0 16 mexr comp comp 1) this signal is clocked into lxo after each read move 1) incs adrcrxz 1 15 16 23 7 8 24 7 8 23 24 1 mask mask mask 10 11 01 00 0 0 1 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-38 v1.1, 2011-03 sdma, v1.0 13.2.11.4 pattern detection for 32-bit data width when 32-bit channel data width is selected (chcr0n.chdw = 10 b ) the pattern detection logic is configured as shown in figure 13-25 . three compare match configurations are possible. in 32-bit channel data width mode, the pattern detection logic makes it possible to compare the lower half-word only, the upper half-word only, or the complete 32-bit word with a pattern stored in the me0pr register. a mask operation is not possible. figure 13-25 pattern detection for 32-bit data width (chcrmn.chdw = 10 b ) (m = 0) 13.2.12 memory protection the sdma controller provides a memory pr otection system that makes it possible to disable read and write accesses of the move engine to specific parts of the memory map. each address of a read move and write move is checked to determine if it is within the table 13-3 pattern detection for 32-bit data width chcr 0n . patsel pattern detection operating modes 00 b pattern detection disabled 01 b unmasked pattern compare of rd0[1:0] to pat0[1:0] 10 b unmasked pattern compare of rd0[3:2] to pat0[3:2] 11 b unmasked pattern compare of rd0[3:0] to pat0[3:0] mca06173 pat 0[3] pat0 [2] pat0[1] pat 0[0 ] rd0[3] rd0[2] rd0[1] rd0[0] comp comp 2 & patsel chcrxz pattern detected mexr mexpr 0 mask 10 11 01 00 0 0 31 15 16 0 mask 31 0 15 16 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-39 v1.1, 2011-03 sdma, v1.0 lower and upper range limits that are enabl ed for the read/write access. if no address range is valid for an actual move address, a move engine interrupt can be generated. each channel has lower and upper source and destination address boundary registers. memory protection within a channel is permanently enabled. the lower boundary register is reset to 00000000 h and the upper boundary is reset to ffffffff h . 13.2.13 sdma checksums the sdma controller uses the crc-32 ieee 802.3 standard polynomial to generate unique checksum calculations for the sour ce address, destin ation address and read data. the source and destination address checksums are used to verify that the correct address sequence was followed. the read data checksum is calculated as a read move loads data from a data source into the sdma controller. t he checksum is used to verify the integrity of data transfers. in order to start the generation of a ch ecksum sequence the crc register(s) must be initialized (e.g. written with 00000000 h or with a desired start value) and a sdma transaction must be set up (start address, length, etc.). the address checkums are calculated as the source or destination address changes. the read data checksum is calc ulated as the value in the read value in the move engine read register is refreshed. the checksum ca lculation is limited to 32-bit accesses. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-40 v1.1, 2011-03 sdma, v1.0 13.3 sdma module registers figure 13-26 and table 13-5 show all registers associated with the sdma controller kernel. additionally, table 13-5 includes the sdma module specific registers that are shown in figure 13-26 . all sdma kernel register names described in this section are also referenced in other parts of the tc1 798 users manual by the module name prefix ?sdma_?. the registers are numbered by one index to indicate the related sdma sub-block and one index to indicate the related sdma channel: index ?m? refers to the sdma sub- block number (m = 0) and index ?n? or ?x? refers to the channel number (n = 0-7 or x = 0- 7) within the sdma sub-block. sdma registers overview figure 13-26 sdma kernel registers smca06175 sadr0n channel control/status registers general control/status registers channel address registers samin0n chcr0n samax0n system registers chcs0n chicr0n chrstr trsr streq htreq eer errsr clre mesr me0r intsr intcr wrpsr move engine registers me0pr ocdsr suspmr gintr n = 0-7 dadr0n damin0n scrc0n channel crc registers dcrc0n rdcrc0n damax0n shadr0n memory protection registers id www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-41 v1.1, 2011-03 sdma, v1.0 table 13-4 registers address space - sdma module module base address end address note sdma f000 3800 h f000 3aff h table 13-5 registers overview - sdma control registers short name description offset addr. 1) access mode reset class description see read write sdma_clc sdma clock control register 000 h u, sv sv, e 3 page 13-92 - reserved 004 h nbe sv - - sdma_id sdma module identification register 008 h u, sv be - page 13-46 - reserved 00c h be be - - sdma_chr str sdma channel reset request register 010 h u, sv sv 3 page 13-51 sdma_trs r sdma transaction request state register 014 h u, sv be 3 page 13-52 sdma_str eq sdma software transaction request register 018 h u, sv sv 3 page 13-53 sdma_htr eq sdma hardware transaction request register 01c h u, sv sv 3 page 13-54 sdma_eer sdma enable error register 020 h u, sv sv 3 page 13-55 sdma_err sr sdma error status register 024 h u, sv be 3 page 13-57 sdma_clr e sdma clear error register 028 h u, sv sv 3 page 13-59 sdma_gint r sdma global interrupt set register 02c h u, sv sv 3 page 13-50 sdma_mes r sdma move engine status register 030 h u, sv be 3 page 13-63 sdma_me0 r sdma move engine 0 read register 034 h u, sv be 3 page 13-64 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-42 v1.1, 2011-03 sdma, v1.0 - reserved 038 h be be - - sdma_me0 pr sdma move engine 0 pattern register 03c h u, sv sv 3 page 13-64 - reserved 040 h - 050 h be be - - sdma_ints r sdma interrupt status register 054 h u, sv be 3 page 13-60 sdma_intc r sdma interrupt clear register 058 h u, sv sv 3 page 13-62 sdma_wrp sr sdma wrap status register 05c h u, sv be 3 page 13-61 - reserved 060 h be be - - sdma_ocd sr sdma ocds register 064 h u, sv sv, e 1 page 13-47 sdma_sus pmr sdma suspend mode register 068 h u, sv sv, e 1 page 13-49 - reserved 06c h - 07c h be be - - sdma_chs r0n sdma channel 0n status register (n = 0-7) (n x 20 h ) + 080 h u, sv be 3 page 13-69 sdma_chc r0n sdma channel 0n control register (n = 0-7) (n x 20 h ) + 084 h u, sv sv 3 page 13-65 sdma_chic r0n sdma channel 0n interrupt control register (n = 0-7) (n x 20 h ) + 088 h u, sv sv 3 page 13-70 sdma_ adrcr0n sdma channel 0n address control register (n = 0-7) (n x 20 h ) + 08c h u, sv sv 3 page 13-72 table 13-5 registers overview - sdma control registers (cont?d) short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-43 v1.1, 2011-03 sdma, v1.0 sdma_sad r0n sdma channel 0n source address register (n = 0-7) (n x 20 h ) + 090 h u, sv sv 3 page 13-77 sdma_dad r0n sdma channel 0n destination address register (n = 0-7) (n x 20 h ) + 094 h u, sv sv 3 page 13-78 sdma_sha dr0n sdma channel 0n shadow address register (n = 0-7) (n x 20 h ) + 098 h u, sv be / sv 2) 3 page 13-79 - reserved (n = 0-7) (n x 20 h ) + 09c h be be - - sdma_sami n0n sdma channel 0n source address lower boundary register (n = 0-7) (n x 20 h ) + 180 h u, sv, 32 sv, 32 3 page 13-80 sdma_sam ax0n sdma channel 0n source address upper boundary register (n = 0-7) (n x 20 h ) + 184 h u, sv, 32 sv, 32 3 page 13-80 sdma_dami n0n sdma channel 0n destination address lower boundary register (n = 0-7) (n x 20 h ) + 188 h u, sv, 32 sv, 32 3 page 13-81 sdma_dam ax0n sdma channel 0n destination address upper boundary register (n = 0-7) (n x 20 h ) + 18c h u, sv, 32 sv, 32 3 page 13-81 sdma_scr c0n sdma channel 0n source address crc checksum register (n x 20 h ) + 190 h u, sv, 32 sv, 32 3 page 13-82 table 13-5 registers overview - sdma control registers (cont?d) short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-44 v1.1, 2011-03 sdma, v1.0 sdma_dcr c0n sdma channel 0n destination address crc checksum register (n x 20 h ) + 194 h u, sv, 32 sv, 32 3 page 13-82 sdma_rdc rc0n sdma channel 0n read data crc checksum register (n x 20 h ) + 198 h u, sv, 32 sv, 32 3 page 13-83 - reserved (n = 0-7) (n x 20 h ) + 19c h be be - - reserved 280 h - 2dc h be be - - sdma_ src7 sdma service request control register 7 2e0 h u, sv sv 3 page 13-94 sdma_ src6 sdma service request control register 6 2e4 h u, sv sv 3 page 13-94 sdma_ src5 sdma service request control register 5 2e8 h u, sv sv 3 page 13-94 sdma_ src4 sdma service request control register 4 2ec h u, sv sv 3 page 13-94 sdma_ src3 sdma service request control register 3 2f0 h u, sv sv 3 page 13-94 sdma_ src2 sdma service request control register 2 2f4 h u, sv sv 3 page 13-94 table 13-5 registers overview - sdma control registers (cont?d) short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-45 v1.1, 2011-03 sdma, v1.0 note: register bits marked ?w? in the following register description are virtual registers and do not contain flip-flops. they are always read as 0. sdma_ src1 sdma service request control register 1 2f8 h u, sv sv 3 page 13-94 sdma_ src0 sdma service request control register 0 2fc h u, sv sv 3 page 13-94 1) the absolute register address is calculated as follows: module base address ( table 13-4 ) + offset address (shown in this column) further, the following ranges for parameters i, k, x, and n are valid: i = 0-7, k = 0-7, x = 0-1, n = 0-63. 2) write access mode to sdma_shadr0n is cont rolled by the register bit sdma_adrcr0n.shwen. sdma_adrcr0n.shwen=0 -> access mode write for sdma_shadr0n is be. sdma_adrcr0n.shwen=1 -> access mode write for sdma_shadr0n is sv. table 13-5 registers overview - sdma control registers (cont?d) short name description offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-46 v1.1, 2011-03 sdma, v1.0 13.3.1 system registers sdma module identification register. the ocds register de scribes the break capability of the sdma module. ocdsr is only reset with the ocds reset. sdma_id module identificat ion register (008 h ) reset value: 0087 c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). mod_type [15:8] r module type the bit field is set to c0 h which defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines a module identification number. the value for the sdma module is 0087 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-47 v1.1, 2011-03 sdma, v1.0 sdma_ocdsr sdma ocds register (064 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 brl 1 bchs1 btrc1 0 brl 0 bchs0 btrc0 r rw rw rw r rw rw rw field bits type description btrc0 [1:0] rw break trigger condition in sub-block 0 this bit field determines the transition type for the transaction request bit trsr.ch0n that leads to a break condition in sdma sub-block 0. 00 b no break condition is generated 01 b a break condition is generated when trsr.ch0n changes from 0 to 1 10 b a break condition is generated when trsr.ch0n changes from 1 to 0 11 b a break condition is generated when trsr.ch0n changes its state bchs0 [4:2] rw break channel select in sub-block 0 this bit field determines the sdma channel n of sdma sub-block 0 whose transaction request bit trsr.ch0n is observed for signal transitions as defined by btrc0. 000 b sdma channel 00 selected 001 b sdma channel 01 selected ... b ... 110 b sdma channel 06 selected 111 b sdma channel 07 selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-48 v1.1, 2011-03 sdma, v1.0 brl0 5rw break on request lost in sub-block 0 this bit field determines whether a break signal is generated for sdma sub-block 0 when at least one of its eight transaction lost interrupts becomes active. 0 b no break condition is generated 1 b a break condition is generated for sdma sub- block 0 when at least one of its eight transaction lost inte rrupts becomes active btrc1 [9:8] rw break trigger condition in sub-block 1 this bit field determines the transition type for the transaction request bit trsr.ch1n that leads to a break condition in sdma sub-block 1. 00 b no break condition is generated 01 b a break condition is generated when trsr.ch1n changes from 0 to 1 10 b a break condition is generated when trsr.ch1n changes from 1 to 0 11 b a break condition is generated when trsr.ch1n changes its state bchs1 [12:10] rw break channel select in sub-block 1 this bit field determines the sdma channel n of sdma sub-block 1 whose transaction request bit trsr.ch1n is observed for signal transitions as defined by btrc1. 000 b sdma channel 10 selected 001 b sdma channel 11 selected ... b ... 110 b sdma channel 16 selected 111 b sdma channel 17 selected brl1 13 rw break on request lost in sub-block 1 this bit field determines whether a break signal is generated for sdma sub-block 1 when at least one of its eight transaction lost interrupts becomes active. 0 b no break condition is generated 1 b a break condition is generated for sdma sub- block 1when at least one of its eight transaction lost inte rrupts becomes active 0 [7:6], [31:14] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-49 v1.1, 2011-03 sdma, v1.0 the suspend mode register contains bits for each sdma channel that allow the enabling/disabling of its soft suspend mode capability and to indicate its suspend status. sdma_suspmr sdma suspend mode register (068 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 sus ac 07 sus ac 06 sus ac 05 sus ac 04 sus ac 03 sus ac 02 sus ac 01 sus ac 00 r rhrhrhrhrhrhrhrh 1514131211109876543210 0 sus en 07 sus en 06 sus en 05 sus en 04 sus en 03 sus en 02 sus en 01 sus en 00 rw rw rw rw rw rw rw rw rw field bits type description susen0n (n = 0-7) nrw suspend enable for sdma channel 0n this bit enables the soft suspend capability individually for each sdma channel 0n. 0 b sdma channel 0n is disabled for soft-suspend mode. the sdma channel 0n does not react on an active suspend request signal susreq 1 b sdma channel 0n is enabled for soft-suspend mode. if the suspend request signal susreq becomes active, a sdma transaction of sdma channel 0n is stopped after the current sdma transfer has been finished soft-suspend mode can be terminated when susen0n is written with 0. susac0n (n = 0-7) n + 16 rh suspend active for sdma channel 0n this status bit indicates whether or not sdma channel 0n is in soft-suspend mode. 0 b sdma channel 0n is not in soft-suspend mode or internal actions are not yet finished after the soft-suspend mode was requested 1 b sdma channel 0n is in soft-suspend mode 0 [15:8] rw reserved read as 0; must be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-50 v1.1, 2011-03 sdma, v1.0 note: register suspmr is only reset by the ocds reset. the global interrupt set register allows the interrupt output lines of the sdma to be activated by software. note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as sdma channel request inputs. 0 [31:24] r reserved read as 0; should be written with 0. sdma_gintr sdma global interrupt set register (02c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 si dma 15 si dma 14 si dma 13 si dma 12 si dma 11 si dma 10 si dma 9 si dma 8 si dma 7 si dma 6 si dma 5 si dma 4 si dma 3 si dma 2 si dma 1 si dma 0 wwwwwwwwwwwwwwww field bits type description sidmax (x = 0-15) xw set sdma interrup t output line x 0 b no action 1 b dma interrupt output line srx will be activated. reading this bit returns a 0 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-51 v1.1, 2011-03 sdma, v1.0 13.3.2 general contro l/status registers the bits in the channel reset request register are used to reset sdma channel mn. sdma_chrstr sdma channel reset request register (010 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 14131211109876543210 0 ch 07 ch 06 ch 05 ch 04 ch 03 ch 02 ch 01 ch 00 r rwh rwh rwh rwh rwh rwh rwh rwh field bits type description ch0n (n = 0-7) nrwh channel 0n reset these bits force the sdma channel 0n to stop its current sdma transaction. once set by software, this bit will be automatically cleared when the channel has been reset. writing a 0 to ch0n has no effect. 0 b no action (write) or the requested channel reset has been reset (read). 1 b sdma channel 0n is stopped. more details see page 13-16 . 0 [31:8] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-52 v1.1, 2011-03 sdma, v1.0 the bits in the transaction request state register indicates which sdma channel is processing a request, and which sdma ch annel has hardware transaction requests enabled. sdma_trsr sdma transaction request state register (014 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 ht re 07 ht re 06 ht re 05 ht re 04 ht re 03 ht re 02 ht re 01 ht re 00 r rhrhrhrhrhrhrhrh 1514131211109876543210 0 ch 07 ch 06 ch 05 ch 04 ch 03 ch 02 ch 01 ch 00 r rhrhrhrhrhrhrhrh field bits type description ch0n (n = 0-7) nrh transaction request state of sdma channel 0n 0 b no sdma request is pending for channel 0n. 1 b a sdma request is pending for channel 0n. ch0n is reset when a pattern match is detected. htre0n (n = 0-7) n+16 rh hardware transaction request enable state of sdma channel 0n 0 b hardware transaction request for sdma channel 0n is disabled. an input sdma request will not trigger the channel 0n. 1 b hardware transaction request for sdma channel 0n is enabled. the transfers of a sdma transaction are controlled by the corresponding channel request line of the sdma requesting source. htre0n is set to 0 when chsr0n.tcount is decremented and chsr0n.tcount = 0. htre0n can be enabled and disabled with htreq.ech0n or htreq.dch0n. htre0n is reset when a pattern match is detected. 0 [31:24], [15:8] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-53 v1.1, 2011-03 sdma, v1.0 the bits in the software transaction req uest register are used to generate a sdma transaction request by software. note: register bits marked with ?w? are virtual and are not stored in flip-flops. reading streq returns 0 when read. sdma_streq sdma software transaction request register (018 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 sch 07 sch 06 sch 05 sch 04 sch 03 sch 02 sch 01 sch 00 r wwwwwwww field bits type description sch0n (n = 0-7) nw set transaction request for sdma channel 0n 0 b no action. 1 b a transaction for sdma channel 0n is requested. when setting sch0n, trsr.ch0n becomes set to indicate that a sdma request is pending for sdma channel 0n. 0 [31:8] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-54 v1.1, 2011-03 sdma, v1.0 the bits in the hardware transaction request register enable or disable sdma hardware requests. sdma_htreq sdma hardware transaction request register (01c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 dch 07 dch 06 dch 05 dch 04 dch 03 dch 02 dch 01 dch 00 r wwwwwwww 1514131211109876543210 0 ech 07 ech 06 ech 05 ech 04 ech 03 ech 02 ech 01 ech 00 r wwwwwwww field bits type description ech0n (n = 0-7) nw enable hardware transfer request for sdma channel 0n see table below dch0n (n = 0-7) 16+n w disable hardware transfer request for sdma channel 0n see table below 0 [31:24] , [15:8] r reserved read as 0; should be written with 0. table 13-6 conditions to set/ reset the bits trsr.htremn htreq.echmn htreq.dchm n transaction finishes 1) for channel mn 1) in single mode only. in continuous mode, the end of a transaction has no impact. modification of trsr.htremn 0 0 0 unchanged 100 set x1x reset xx1 reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-55 v1.1, 2011-03 sdma, v1.0 the enable error register describes how the sdma controller reacts to errors. it enables the interrupts for the loss of a transaction request or move engine errors. sdma_eer sdma enable error register (020 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 trlinp 0 me0inp 0 e me0 der e me0 ser rw r rw r rw rw 1514131211109876543210 0 e trl 07 e trl 06 e trl 05 e trl 04 e trl 03 e trl 02 e trl 01 e trl 00 r rwrwrwrwrwrwrwrw field bits type description etrl0n (n = 0-7) nrw enable transaction request lost for sdma channel 0n this bit enables the generation of an interrupt when the set condition for errsr.trl0n is detected. 0 b the interrupt generation for a request lost event for channel 0n is disabled. 1 b the interrupt generation for a request lost event for channel 0n is enabled. eme0ser 16 rw enable move engi ne 0 source error this bit enables the generation of a move engine 0 source error interrupt. 0 b move engine 0 source error interrupt is disabled. 1 b move engine 0 source error interrupt is enabled. eme0der 17 rw enable move engine 0 destination error this bit enables the generation of a move engine 0 destination error interrupt. 0 b move engine 0 destination error interrupt is disabled. 1 b move engine 0 destination error interrupt is enabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-56 v1.1, 2011-03 sdma, v1.0 me0inp [23:20] rw move engine 0 error in terrupt node pointer me0inp determines the number n (n = 0-15) of the service request output srn that becomes active on a move engine 0 source or destination interrupt. 0000 b sr0 selected for move engine 0 interrupt 0001 b sr1 selected for move engine 0 interrupt ? b ? 1111 b sr15 selected for move engine 0 interrupt note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as sdma channel request inputs. trlinp [31:28] rw transaction lost inte rrupt node pointer trlinp determines the number n (n = 0-15) of the service request output srn that becomes active on a transaction lost interrupt. 0000 b sr0 selected for transaction lost interrupt 0001 b sr1 selected for transaction lost interrupt ? b ? 1111 b sr15 selected for tran saction lost interrupt note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as sdma channel request inputs. 0 [15:8], [19:18] , [27:24] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-57 v1.1, 2011-03 sdma, v1.0 the error status register indicates if the sdma controller could not answer to a request because the previous request was not terminated (see section 13.2.4.4 ). it indicates also the fpi bus accesses that have been terminated with errors. sdma_errsr sdma error status register (024 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 lec me0 0 fpie r 00 me0 der me0 ser r rh r rh r r rh rh 1514131211109876543210 0 trl 07 trl 06 trl 05 trl 04 trl 03 trl 02 trl 01 trl 00 r rhrhrhrhrhrhrhrh field bits type description trl0n (n = 0-7) nrh transaction/transfer request lost of sdma channel 0n 0 b 0 no request lost event has been detected for channel 0n. 1 b 1 a new sdma request was detected while trsr.ch0n=1 (request lost event). this bit is reset by software when writing a 1 to clre.ctl0n, or by a channel reset (writing chrstr.ch0n = 1). me0ser 16 rh move engine 0 source error this bit is set whenever a move engine 0 error occurred during a source (read) move of a sdma transfer, or a request could not been serviced due to the access protection. 0 b no move engine 0 source error has occurred. 1 b a move engine 0 source error has occurred. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-58 v1.1, 2011-03 sdma, v1.0 me0der 17 rh move engine 0 destination error this bit is set whenever a move engine 0 error occurred during a destination (write) move of a sdma transfer, or a request could not been serviced due to the access protection. 0 b no move engine 0 destination error has occurred. 1 b a move engine 0 destination error has occurred. fpier 20 rh spb error this bit is set whenever a move that has been started by the sdma fpi master interface leads to an error on the fpi bus. 0 b no error occurred. 1 b an error occurred on fpi bus interface. lecme0 [26:24] rh last error channel move engine 0 this bit field indicates the channel number of the last channel of move engine 0 leading to an on chip bus error that has occurred. 0 [15:8], [19:18], [23:21], [31:27] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-59 v1.1, 2011-03 sdma, v1.0 the clear error contains bits that make it possible to clear the transaction request lost flags or the move engine error flags. sdma_clre sdma clear error register (028 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 c fpie r 0 c me0 der c me0 ser r w wwww 1514131211109876543210 0 ctl 07 ctl 06 ctl 05 ctl 04 ctl 03 ctl 02 ctl 01 ctl 00 w wwwwwwww field bits type description ctl0n (n = 0-7) nw clear transaction request lost for sdma channel 0n 0 b no action 1 b clear sdma channel 0n transaction request lost flag errsr.trl0n cme0ser 16 w clear move engine 0 source error 0 b no action 1 b clear source error flag errsr.me0ser. cme0der 17 w clear move engine 0 destination error 0 b no action 1 b clear destination error flag errsr.me0der. cfpier 20 w clear fpi error 0 b no action 1 b clear error flag errsr.fpier. 0 [15:8], [19:18], [31:21] r reserved should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-60 v1.1, 2011-03 sdma, v1.0 the interrupt status register indicates if chsr0n.tcount matches with chcr0n.irdv, or if chsr0n.tcount has been decremented (depending on chicr0n.intct[0]), or if a pattern has been detected. these conditions can also generate an interrupt if enabled (see figure 13-17 on page 13-27 ). sdma_intsr sdma interrupt status register (054 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 ipm 07 ipm 06 ipm 05 ipm 04 ipm 03 ipm 02 ipm 01 ipm 00 r rhrhrhrhrhrhrhrh 1514131211109876543210 0 ich 07 ich 06 ich 05 ich 04 ich 03 ich 02 ich 01 ich 00 r rhrhrhrhrhrhrhrh field bits type description ich0n (n = 0-7) nrh interrupt from channel 0n this bit indicates that channel 0n has raised an interrupt for tcount = irdv or if tcount has been decremented (depending on chicr.intct[0]. this bit (and ip0n) is reset by software when writing a 1 to intcr.cich0n or by a channel reset (writing chrstr.ch0n = 1). 0 b a channel interrupt has not been detected. 1 b a channel interrupt has been detected. ipm0n (n = 0-7) n + 16 rh pattern detection from channel 0n this bit indicates that a pattern has been detected for channel 0n while the pattern detection has been enabled. this bit (and ich0n) is reset by software when writing a 1 to intcr.cich0n or by a channel reset (writing chrstr.ch0n = 1). 0 b a pattern has not been detected. 1 b a pattern has been detected. 0 [15:8], [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-61 v1.1, 2011-03 sdma, v1.0 the wrap status register provides information on the channels that perform a wraparound on their source or destination buffe r(s). this condition can also lead to an interrupt if it is enabled. sdma_wrpsr sdma wrap status register (05c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 wrp d07 wrp d06 wrp d05 wrp d04 wrp d03 wrp d02 wrp d01 wrp d00 r rhrhrhrhrhrhrhrh 1514131211109876543210 0 wrp s07 wrp s06 wrp s05 wrp s04 wrp s03 wrp s02 wrp s01 wrp s00 r rhrhrhrhrhrhrhrh field bits type description wrps0n (n = 0-7) n rh wrap source buffer for channel 0n these bits indicate which channels have done a wrap-around of their source buffer(s). 0 b no wrap-around occurred for channel 0n. 1 b a wrap-around occurred for channel 0n. note: this bit is reset by software by writing a 1 to intcr.cwrp0n or chrstr.ch0n. wrpd0n (n = 0-7) n+16 rh wrap destination buffer for channel 0n these bits indicate which channels have done a wrap-around of their destination buffer(s). 0 b no wrap-around occurred for channel 0n. 1 b a wrap-around occurred for channel 0n. note: this bit is reset by software by writing a 1 to intcr.cwrp0n or chrstr.ch0n. 0 [15:8], [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-62 v1.1, 2011-03 sdma, v1.0 the bits in the interrupt clear register allow the channel interrupt flags and the wrap buffer interrupt flags for sdma channels 0n to be reset. 13.3.3 move engine registers the move engine status register is a read-on ly register that holds status information about the transaction handled by the move engines. sdma_intcr sdma interrupt clear register (058 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 c wrp 07 c wrp 06 c wrp 05 c wrp 04 c wrp 03 c wrp 02 c wrp 01 c wrp 00 r wwwwwwww 1514131211109876543210 0 c ich 07 c ich 06 c ich 05 c ich 04 c ich 03 c ich 02 c ich 01 c ich 00 r wwwwwwww field bits type description cich0n (n = 0-7) nw clear interrupt fo r sdma channel 0n these bits allow the channel interrupt flags intsr.ich0n and intsr.ipm0n of sdma channel 0n to be reset by software. 0 b no action. 1 b bits intsr.ich0n and intsr.ipm0n are reset. cwrp0n (n = 0-7) n + 16 w clear wrap buffer interru pt for sdma channel 0n these bits allow the wrap source buffer interrupt flag wrpsr.wrps0n and the wrap destination buffer interrupt flag wrpsr.wrpd0n (both together) of sdma channel 0n to be reset by software. 0 b no action. 1 b bits wrpsr.wrps0n and wrpsr.wrpd0n are reset. 0 [15:8], [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-63 v1.1, 2011-03 sdma, v1.0 sdma_mesr sdma move engine status register (030 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0rbtfpi me0 ws ch0 me0 rs r rhrhrhrh field bits type description me0rs 0rh move engine 0 read status 0 b move engine 0 is not performing a read. 1 b move engine 0 is performing a read. ch0 [3:1] rh reading channel in move engine 0 this bit field indicates which channel number is currently being processed by the move engine 0. me0ws 4rh move engine 0 write status 0 b move engine 0 is not performing a write. 1 b move engine 0 is performing a write. rbtfpi [7:5] rh read buffer trace for fpi bus interface this bit field contains trace information from the buffer in the fpi bus interface. in the TC1798 it indicates the source of a bus access to the fpi bus. 000 b sdma move engine 0 other bit combinations are reserved. rbtfpi is useful for emulation purposes. it is not recommended to evaluate this bit field during normal operation of the TC1798. 0 [31:8] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-64 v1.1, 2011-03 sdma, v1.0 the move engine 0 read register indicates the value that has just been read by move engine 0. the value in this register is compared to the bits in register me0pr according to the bit fields chcr0n.patsel. the move engine 0 pattern register contains the patterns (mask and/or compare bits) to be processed by the pattern detection logic in move engine 0. sdma_me0r sdma move engine 0 read register (034 h ) reset value: 0000 0000 h 31 24 23 16 15 8 7 0 rd03 rd02 rd01 rd00 rh rh rh rh field bits type description rd00, rd01, rd02, rd03 [7:0], [15:8], [23:16], [31:24] rh read value for move engine 0 contains the 32-bit read data (four bytes rd0[3:0]) that is stored in the move engine after each read move. the content of me0r is overwritten after each read move of a sdma channel belonging to sdma sub-block. sdma_me0pr sdma move engine 0 pattern register(03c h ) reset value: 0000 0000 h 31 24 23 16 15 8 7 0 pat03 pat02 pat01 pat00 rw rw rw rw field bits type description pat00, pat01, pat02, pat03 [7:0], [15:8], [23:16], [31:24] rw pattern for move engine 0 determines up to four 8-bit compare patterns/mask patterns to be processed by the pattern detection logic in move engine 0. depending on the pattern detection configuration (chcr0n.patsel) and channel data width (chcr0n.chdw), the patterns are processed as bytes or half-words. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-65 v1.1, 2011-03 sdma, v1.0 13.3.4 channel control/status registers the channel control register for sdma channel 0n contains its configuration and its control bits and bit fields. sdma_chcr0x (x = 0-7) sdma channel 0x control register(084 h +x*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 ch prio 0 patsel 0 chdw ch mo de rro at blkm rrwrrwrrwrwrwrw 1514131211109876543210 prsel 0 trel rw r rw field bits type description trel [9:0] rw transfer reload value this bit field contains the number of sdma transfers for a sdma transaction of sdma channel 0n. this10-bit transfer count value is loaded into chsr0n.tcount at the start of a sdma transaction (when trsr.ch0n becomes set and chsr0n.tcount = 0). a write to chsr0n.trel during a running sdma transaction has no influence to the running sdma transaction. if chsr0n.trel = 0 or if chsr0n.trel = 1, chsr0n.tcount will be loaded with 1 when a new transaction is started (at least one sdma transfer must be executed per sdma transaction). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-66 v1.1, 2011-03 sdma, v1.0 prsel [15:12] rw peripheral request select this bit field controls the hardware request input multiplexer of sdma channel 0n (see figure 13-6 on page 13-10 ). 0000 b input ch0n_reqi0 selected 0001 b input ch0n_reqi1 selected 0010 b input ch0n_reqi2 selected 0011 b input ch0n_reqi3 selected 0100 b input ch0n_reqi4 selected 0101 b input ch0n_reqi5 selected 0110 b input ch0n_reqi6 selected 0111 b input ch0n_reqi7 selected 1000 b input ch0n_reqi8 selected 1001 b input ch0n_reqi9 selected 1010 b input ch0n_reqi10 selected 1011 b input ch0n_reqi11 selected 1100 b input ch0n_reqi12 selected 1101 b input ch0n_reqi13 selected 1110 b input ch0n_reqi14 selected 1111 b input ch0n_reqi15 selected blkm [18:16] rw block mode blkm determines the number of sdma moves executed during one sdma transfer. 000 b one sdma transfer has 1 sdma move 001 b one sdma transfer has 2 sdma move 010 b one sdma transfer has 4 sdma move 011 b one sdma transfer has 8 sdma move 100 b one sdma transfer has 16 sdma move other bit combinations are reserved and must not be used. see also figure 13-10 on page 13-17 . rroat 19 rw reset request only after transaction rroat determines whether or not the trsr.ch0n transfer request state flag is reset after each transfer. 0 b trsr.ch0n is reset after each transfer. a transfer request is required for each transfer. 1 b trsr.ch0n is reset when chsr0n.tcount = 0 after a transfer. one transfer request starts a complete sdma transaction field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-67 v1.1, 2011-03 sdma, v1.0 chmode 20 rw channel operation mode chmode determines the reset condition for control bit trsr.htre0n of sdma channel 0n. 0 b single mode operation is selected for sdma channel 0n. after a transaction, sdma channel 0n is disabled for further hardware requests (trsr.htre0n is reset by hardware) trsr.htre0n must be set again by software for starting a new transaction. 1 b continuous mode operation is selected for sdma channel 0n. after a transaction, bit trsr.htre0n remains set chdw [22:21] rw channel data width chdw determines the data width for the read and write moves of sdma channel 0n. 00 b 8-bit (byte) data width for moves selected 01 b 16-bit (half-word) data width for moves selected 10 b 32-bit (word) data width for moves selected 11 b reserved patsel [25:24] rw pattern select this bit field selects the mode of the pattern detection logic. depending on the channel data width, patsel selects different pattern detection configurations. if pattern detection is enabled (patsel not equal 00 b ), the pattern detection interrupt line will be activated on the selected pattern match. 8-bit channel data width (chdw = 00 b ): selected pattern detection configuration see table 13-1 on page 13-35 . 16-bit channel data width (chdw = 01 b ): selected pattern detection configuration see table 13-2 on page 13-36 . 32-bit channel data width (chdw = 10 b ): selected pattern detection configuration see table 13-3 on page 13-38 . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-68 v1.1, 2011-03 sdma, v1.0 chprio 28 rw channel priority chprio determines the priority of sdma channel n for the move engine 0 internal channel arbitration. this priority is used for the case when multiple channels of move engine 0 are triggered in parallel. 0 b sdma channel 0n has a low channel priority 1 b sdma channel 0n has a high channel priority 0 [11:10], 23, [27:26], [31:29] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-69 v1.1, 2011-03 sdma, v1.0 the channel status register contains the current transfer count and a pattern detection compare result. sdma_chsr0x (x = 0-7) sdma channel 0x status register(080 h +x*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 lxo 0 tcount rh r rh field bits type description tcount [9:0] rh transfer count status tcount holds the actual value of the sdma transfer count for sdma channel 0x. tcount is loaded with the value of chcr0x.trel when trsr.ch0x becomes set (and tcount = 0). after each sdma transfer, tcount is decremented by 1. lxo 15 rh old value of pattern detection this bit contains the compare result of a pattern compare operation when 8-bit or 16-bit data width is selected. 8-bit data width: see table 13-1 and figure 13-23 16-bit data width: see table 13-2 and figure 13-24 0 b the corresponding pattern compare operation did not find a pattern match on the last move 1 b the corresponding pattern compare operation found a pattern match at the last move 0 [14:10], [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-70 v1.1, 2011-03 sdma, v1.0 the channel interrupt control register controls the interrupts generation. sdma_chicr0x (x = 0-7) sdma channel 0x interrupt control register (088 h +x*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 irdv intp wrpp intct wrp de wrp se rw rw rw rw rw rw field bits type description wrpse 0rw wrap source enable 0 b wrap source buffer interrupt disabled 1 b wrap source buffer interrupt enabled wrpde 1rw wrap destination enable 0 b wrap destination buffer interrupt disabled 1 b wrap destination buffer interrupt enabled intct [3:2] rw interrupt control 00 b no interrupt w ill be generated on changing the tcount value. the bit intsr.ich0x is set when tcount equals irdv. 01 b no interrupt w ill be generated on changing the tcount value. the bit intsr.ich0x is set when tcount is decremented 10 b an interrupt is generated and bit intsr.ich0x is set each time tcount equals irdv 11 b interrupt is generated and bit intsr.ich0x is set each time tcount is decremented note: see figure 13-17 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-71 v1.1, 2011-03 sdma, v1.0 note: the interrupt node of the wrap-around in terrupts is shared with the pattern match interrupt. in order to support interrupt generation in case of a pattern match, the wrap-around interrupt should be disabled. if the wrap-around interrupts are used, the pattern match interrupt should not be used. the settings are independent for each sdma channel. wrpp [7:4] rw wrap pointer wrpp determines the number n (n = 0-15) of the service request output srn that becomes active on a wrap buffer interrupt. 0000 b sr0 selected for channel 0x wrap buffer interrupt 0001 b sr1 selected for channel 0x wrap buffer interrupt ? b ? 1111 b sr15 selected for channel 0x wrap buffer interrupt note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as sdma channel request inputs. intp [11:8] rw interrupt pointer intp determines the number n (n = 0-15) of the service request output srn that becomes active on a channel interrupt. 0000 b sr0 selected for channel 0x interrupt 0001 b sr1 selected for channel 0x interrupt ? b ? 1111 b sr15 selected for channel 0x interrupt note: in the TC1798, sr[7:0] are connected to interrupt nodes. sr[15:8] are used as sdma channel request inputs. irdv [15:12] rw interrupt raise detect value these bits specify the value of chsr0x.tcount for which the interrupt threshold limit should be raised. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-72 v1.1, 2011-03 sdma, v1.0 the address control register controls how source and destination addresses are updated after a sdma move. furthermore, it determines whether or not a source or destination address register update is shadowed. sdma_adrcr0x (x = 0-7) sdma channel 0x address control register (08c h +x*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 shw en shct rrwrw 1514131211109876543210 cbld cbls incd dmf incs smf rw rw rw rw rw rw field bits type description smf [2:0] rw source address modification factor this bit field and the data width as defined in chcrx.chdw determine an address offset value by which the source address is modified after each sdma move. see also table 13-7 . 000 b address offset is 1 x chcr0x.chdw 001 b address offset is 2 x chcr0x.chdw 010 b address offset is 4 x chcr0x.chdw 011 b address offset is 8 x chcr0x.chdw 100 b address offset is 16 x chcr0x.chdw 101 b address offset is 32 x chcr0x.chdw 110 b address offset is 64 x chcr0x.chdw 111 b address offset is 128 x chcr0x.chdw incs 3rw increment of source address this bit determines whether the address offset as selected by smf will be added to or subtracted from the source address after each sdma move. the source address is not modified if cbls = 0000 b . 0 b address offset will be subtracted 1 b address offset will be added. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-73 v1.1, 2011-03 sdma, v1.0 dmf [6:4] rw destination address modification factor this bit field and the data width as defined in chcr0x.chdw determines an address offset value by which the destination address is modified after each sdma move. the destination address is not modified if cbld = 0000 b . see also table 13-7 . 000 b address offset is 1 x chdw 001 b address offset is 2 x chdw 010 b address offset is 4 x chdw 011 b address offset is 8 x chdw 100 b address offset is 16 x chdw 101 b address offset is 32 x chdw 110 b address offset is 64 x chdw 111 b address offset is 128 x chdw incd 7rw increment of destination address this bit determines whether the address offset as selected by dmf will be added to or subtracted from the destination address after each sdma move. the destination address is not modified if cbld = 0000 b . 0 b address offset will be subtracted 1 b address offset will be added cbls [11:8] rw circular buffer length source this bit field determines which part of the 32-bit source address register remains unchanged and is not updated after a sdma move operation (see also section 13.2.4.7 ). therefore, cbls also determines the size of the circular source buffer. 0000 b source address sadr[31:0] is not updated 0001 b source address sadr[31:1] is not updated 0010 b source address sadr[31:2] is not updated 0011 b source address sadr[31:3] is not updated ... b ... 1110 b source address sadr[31:14] is not updated 1111 b source address sadr[31:15] is not updated field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-74 v1.1, 2011-03 sdma, v1.0 cbld [15:12] rw circular buffer length destination this bit field determines which part of the 32-bit destination address register remains unchanged and is not updated after a sdma move operation (see also page 13-19 ). therefore, cbld also determines the size of the circular destination buffer. 0000 b destination address dadr[31:0] is not updated 0001 b destination address dadr[31:1] is not updated 0010 b destination address dadr[31:2] is not updated 0011 b destination address dadr[31:3] is not updated ... b ... 1110 b destination address dadr[31:14] is not updated 1111 b destination address dadr[31:15] is not updated shct [17:16] rw shadow control this bit field determines whether an address is transferred into the shadow address register when writing to source or destination address register. 00 b shadow address register not used. source and destination address register are written directly 01 b shadow address register used for source address buffering. when writing to sadr0x, the address is buffered in shadr0x and transferred to sadr0x with the start of the next sdma transaction 10 b shadow address register used for destination address buffering. when writing to dadr0x, the address is buffered in shadr0x and transferred to dadr0x with the start of the next sdma transaction 11 b reserved in case of shct = 01 b or 10 b , shct must not be changed until the next sdma transaction has been started. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-75 v1.1, 2011-03 sdma, v1.0 shwen 18 rw shadow address register write enable this bit determines whether the shadow address register shadr0x is read only and automatically set to 0000 0000 h or if the shadow register can also be directly written and not modified when and shadow transfer takes place. 0 b shadow address register is read only and the value stored in the shadr0x is automatically set to 0000 0000 h when the shadow transfer takes place 1 b shadow address register shadr0x can be read and can be directly written. the value stored in the shadr0x is not automatically modified when the shadow transfer takes place 0 [31:19] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-76 v1.1, 2011-03 sdma, v1.0 table 13-7 shows the offset values that are added or subtracted to/from a source or destination address register after a sdma move. bit field smf and bit incs determine the offset value for the source address. bit field dmf and bit incd determine the offset value for the destination address. note: chcr 0n .chdw = 11 b is reserved and should not be used. table 13-7 address offset calculation table chcr 0n .chdw = 00 b (8-bit data width) chcr 0n .chdw = 01 b (16-bit data width) chcr 0n .chdw = 10 b (32-bit data width) smf dmf incs incd address offset smf dmf incs incd address offset smf dmf incs incd address offset 000 b 0-1 000 b 0-2 000 b 0-4 1+1 1+2 1+4 001 b 0-2 001 b 0-4 001 b 0-8 1+2 1+4 1+8 010 b 0-4 010 b 0-8 010 b 0-16 1+4 1+8 1+16 011 b 0-8 011 b 0-16 011 b 0-32 1 +8 1 +16 1 +32 100 b 0 -16 100 b 0-32 100 b 0-64 1 +16 1 +32 1 +64 101 b 0 -32 101 b 0-64 101 b 0-128 1 +32 1 +64 1 +128 110 b 0 -64 110 b 0 -128 110 b 0-256 1 +64 1 +128 1 +256 111 b 0-128111 b 0 -256 111 b 0-512 1 +128 1 +256 1 +512 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-77 v1.1, 2011-03 sdma, v1.0 13.3.5 channel address registers the source address register contains the 32 -bit source address. if a sdma channel 0n is active, sadr0n is updated continuously (if programmed) and shows the actual source address that is used for read moves within sdma transfers. a write to sadr0n is executed directly only when the sdma channel 0n is inactive (chsr0n.tcount = 0 and trsr.ch0n = 0). if sdma channel 0n is active when writing to sadr0n, the source address will not be written into sadr0n directly but will be buffered in the shadow register shadr0n until the start of the next sdma transaction. during this shadowed address register operation, bit field adrcr0n.shct must be set to 01 b . sdma_sadr0x (x = 0-7) sdma channel 0x source address register (090 h +x*20 h ) reset value: 0000 0000 h 31 0 sadr rwh field bits type description sadr [31:0] rwh source start address this bit field holds the actual 32-bit source address of sdma channel 0x that is used for read moves. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-78 v1.1, 2011-03 sdma, v1.0 the destination address register contains the 32-bit destination address. if a sdma channel is active, dadr0n is updated co ntinuously (if programmed) and shows the actual destination address that is used for write moves within sdma transfers. a write to dadr0n is executed directly only when the sdma channel 0n is inactive (chsr0n.tcount = 0 and trsr.ch0n = 0). if sdma channel 0n is active when writing to dadr0n, the source address will not be written in to dadr0n directly but will be buffered in the shadow register shadr0n until the start of the next sdma transaction. during this shadowed address register operation, bit field adrcr0n.shct must be set to 10 b . sdma_dadr0x (x = 0-7) sdma channel 0x destination address register (094 h +x*20 h ) reset value: 0000 0000 h 31 0 dadr rwh field bits type description dadr [31:0] rwh destination address this bit field holds the actual 32-bit destination address of sdma channel 0x that is used for write moves. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-79 v1.1, 2011-03 sdma, v1.0 the shadow address register holds the shadowed source or destination address before it is written into the source or destination address register. shadr0n can be read only. shadr0n is written when source or destination address buffering is selected (adrcr0n.shct = 01 b or adrcr0n.shct = 10 b ) and a transaction is running. while the shadow mechanism is disabled, shadr is set to 0000 0000 h . if adrcr0n.shwen = 0 the value stored in the shadr is automatically set to 0000 0000 h when the shadow transfer takes place. the user can read the shadow register in order to detect if the shadow tran sfer has already taken place. if the value in shadr is 0000 0000 h , no shadow transfer can take place and the corresponding address register is modified according to the circular buffer rules. if adrcr0n.shwen = 1 shadow register shadr0n can be directly written. the value stored in the shadr0n is not modified when the shadow transfer takes place, the shadow mechanism remains active and the shadow transfer will be repeated until channel 0n is reset or until the value in shadr is 0000 0000 h , is written into the shadow register. sdma_shadr0x (x = 0-7) sdma channel 0x shadow address register (098 h +x*20 h ) reset value: 0000 0000 h 31 0 shadr rwh field bits type description shadr [31:0] rwh shadowed address this bit field holds the shadowed 32-bit source or destination address of sdma channel x. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-80 v1.1, 2011-03 sdma, v1.0 13.3.6 memory protection registers the memory protection registers control the lower and upper source and destination address boundaries. only 32-bit word accesses are permitted to the memory protection registers. byte and half word accesses will return a bus error. sdma_samin0x (x = 0-7) sdma channel 0x source address lower boundary register (180 h +x*20 h ) reset value: 0000 0000 h 31 0 samin rw field bits type description samin [31:0] rw source address lower boundary this bit field holds the 32-bit source address lower boundary value of sdma channel 0x that is used for read moves. sdma_samax0x (x = 0-7) sdma channel 0x source address lower boundary register (184 h +x*20 h ) reset value: ffff ffff h 31 0 samax rw field bits type description samax [31:0] rw source address upper boundary this bit field holds the 32-bit source address upper boundary value of sdma channel 0x that is used for read moves. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-81 v1.1, 2011-03 sdma, v1.0 sdma_damin0x (x = 0-7) sdma channel 0x destination address lower boundary register (188 h +x*20 h ) reset value: 0000 0000 h 31 0 damin rw field bits type description damin [31:0] rw destination address lower boundary this bit field holds the 32-bit destination address lower boundary value of sdma channel 0x that is used for write moves. sdma_damax0x (x = 0-7) sdma channel 0x destination address upper boundary register (18c h +x*20 h ) reset value: ffff ffff h 31 0 damax rw field bits type description damax [31:0] rw destination address upper boundary this bit field holds the 32-bit destination address upper boundary value of sdma channel 0x that is used for write moves. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-82 v1.1, 2011-03 sdma, v1.0 13.3.7 channel crc registers the channel crc registers store the working crc32 ethernet polynomial checksum. only 32-bit word accesses are permitted to the crc registers. byte and half word accesses will return a bus error. in order to start a crc32 sequence the crc r egisters must be initialized (e.g. written with 00000000 h or with a desired start value) and an sdma transaction must be set up (start address, length, etc.). during each sdma move a read move loads data from a data source to the sdma controller and a write move puts data from the sdma controller to a dma destination. during an sdma move each crc register will perform one polynomial checksum calculation. sdma_scrc0x (x = 0-7) sdma channel 0x source address crc register (190 h +x*20 h ) reset value: 0000 0000 h 31 0 scrc rwh field bits type description scrc [31:0] rwh source address crc this bit field contains the working crc32 ethernet polynomial checksum for the source address. sdma_dcrc0x (x = 0-7) sdma channel 0x destination address crc register (194 h +x*20 h ) reset value: 0000 0000 h 31 0 dcrc rwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-83 v1.1, 2011-03 sdma, v1.0 field bits type description dcrc [31:0] rwh destination address crc this bit field contains the working crc32 ethernet polynomial checksum for the destination address. sdma_rdcrc0x (x = 0-7) sdma channel 0x read data crc register (198 h +x*20 h ) reset value: 0000 0000 h 31 0 rdcrc rwh field bits type description rdcrc [31:0] rwh read data crc this bit field contains the working crc32 ethernet polynomial checksum for read data. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-84 v1.1, 2011-03 sdma, v1.0 13.4 sdma module implementation this section describes the TC1798 sdma module interfaces with the clock control, interrupt control, and address decoding. figure 13-27 shows the TC1798-specific implementation details and interconnections of the sdma module. the sdma module is supplied with a separate clock control, address decoding, interrupt control, and the request input wiring matrix. figure 13-27 sdma module implementation and interconnections the request sources of the peripheral modules (adc0, multican, and scu) are associated with interrupt node pointers and individual interrupt enable bits. as a result, each of the internal requests of a module can be routed independently to any of the interrupt output lines (int_ox) of the module. 13.4.1 sdma request wiring matrix the sdma request input lines of each sdma channel within the sdma sub-block are connected to request output lines from the peripheral modules according to table 13-8 . interrupt request nodes smcb06149 clock control f dma sr[15:0] safe dma controller arbiter/ switch control bus switch fpi bus interface system peripheral bus dma requests of on-chip periph . units address decoder dma interrupt control ch0n_out dma channels 00-07 safe dma sub-block m request selection/ arbitration transaction control unit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-85 v1.1, 2011-03 sdma, v1.0 table 13-8 sdma request assi gnment for sdma sub-block sdma channel sdma request line sdma requesting unit selected by 00 sdma_sr08 sdma(int_o08) chcr00.prsel = 0000 b iout0 scu (eru) chcr00.prsel = 0001 b sent_trig0 sent chcr00.prsel = 0010 b adc_sr02 adc chcr00.prsel = 0011 b ssc0_rdr ssc0 chcr 00.prsel = 0100 b asc0_rdr asc0 chcr 00.prsel = 0101 b fadc_sr00 fadc chcr00.prsel = 0110 b mil0_sr4 mil0 chcr00.prsel = 0111 b misc0_sr2 msc0 chcr00.prsel = 1000 b gpta_trig00 gpta chcr00.prsel = 1001 b - - chcr00.prsel = 1010 b int1src eray chcr00.prsel = 1011 b ibusy eray chcr00.prsel = 1100 b - - chcr00.prsel = 1101 b - - chcr00.prsel = 1110 b - - chcr00.prsel = 1111 b 01 sdma_sr09 sdma(int_o09) chcr01.prsel = 0000 b iout1 scu (eru) chcr01.prsel = 0001 b sent_trig1 sent chcr01.prsel = 0010 b adc_sr03 adc chcr01.prsel = 0011 b ssc0_tdr ssc0 chcr 01.prsel = 0100 b asc1_rdr asc1 chcr 01.prsel = 0101 b fadc_sr01 fadc chcr01.prsel = 0110 b mil0_sr5 mil0 chcr01.prsel = 0111 b msc0_sr3 msc0 chcr01.prsel = 1000 b gpta_trig01 gpta chcr01.prsel = 1001 b - - chcr01.prsel = 1010 b tint0src eray chcr01.prsel = 1011 b - - chcr01.prsel = 1100 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-86 v1.1, 2011-03 sdma, v1.0 - - chcr01.prsel = 1101 b - - chcr01.prsel = 1110 b - - chcr01.prsel = 1111 b 02 sdma_sr10 sdma(int_o10) chcr02.prsel = 0000 b iout2 scu (eru) chcr02.prsel = 0001 b sent_trig2 sent chcr02.prsel = 0010 b adc_sr04 adc chcr02.prsel = 0011 b ssc1_rdr ssc1 chcr 02.prsel = 0100 b asc0_tdr asc0 chcr 02.prsel = 0101 b asc0_tbdr asc0 chcr 02.prsel = 0110 b mil0_sr6 mil0 chcr02.prsel = 0111 b msc0_sr2 msc0 chcr02.prsel = 1000 b gpta_trig02 gpta chcr02.prsel = 1001 b ccu60_sr0 ccu60 chcr02.prsel = 1010 b ndat1src eray chcr02.prsel = 1011 b - - chcr02.prsel = 1100 b - - chcr02.prsel = 1101 b - - chcr02.prsel = 1110 b - - chcr02.prsel = 1111 b 03 sdma_sr11 sdma(int_o11) chcr03.prsel = 0000 b iout3 scu (eru) chcr03.prsel = 0001 b sent_trig3 sent chcr03.prsel = 0010 b adc_sr05 adc chcr03.prsel = 0011 b ssc1_tdr ssc1 chcr 03.prsel = 0100 b asc1_tdr asc1 chcr 03.prsel = 0101 b asc1_tbdr asc1 chcr 03.prsel = 0110 b mil0_sr7 mil0 chcr03.prsel = 0111 b msc0_sr3 msc0 chcr03.prsel = 1000 b gpta_trig03 gpta chcr03.prsel = 1001 b ccu61_sr0 ccu61 chcr03.prsel = 1010 b table 13-8 sdma request assi gnment for sdma sub-block (cont?d) sdma channel sdma request line sdma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-87 v1.1, 2011-03 sdma, v1.0 mbsc1src eray chcr03.prsel = 1011 b - - chcr03.prsel = 1100 b - - chcr03.prsel = 1101 b - - chcr03.prsel = 1110 b - - chcr03.prsel = 1111 b 04 sdma_sr12 sdma(int_o12) chcr04.prsel = 0000 b stmirq0 stm chcr 04.prsel = 0001 b sent_trig4 sent chcr04.prsel = 0010 b adc_sr06 adc chcr04.prsel = 0011 b ssc2_rdr ssc2 chcr 04.prsel = 0100 b asc0_tdr asc0 chcr 04.prsel = 0101 b asc0_tbdr asc0 chcr 04.prsel = 0110 b mil0_sr4 mil0 chcr04.prsel = 0111 b msc1_sr2 msc1 chcr04.prsel = 1000 b gpta_trig10 gpta chcr04.prsel = 1001 b - - chcr04.prsel = 1010 b int1src eray chcr04.prsel = 1011 b obusy eray chcr04.prsel = 1100 b - - chcr04.prsel = 1101 b - - chcr04.prsel = 1110 b - - chcr04.prsel = 1111 b 05 sdma_sr13 sdma(int_o13) chcr05.prsel = 0000 b stmirq0 stm chcr 05.prsel = 0001 b sent_trig5 sent chcr05.prsel = 0010 b adc_sr07 adc chcr05.prsel = 0011 b ssc2_tdr ssc2 chcr 05.prsel = 0100 b asc1_tdr asc1 chcr 05.prsel = 0101 b asc1_tbdr asc1 chcr 05.prsel = 0110 b mil0_sr5 mil0 chcr05.prsel = 0111 b msc1_sr3 msc1 chcr05.prsel = 1000 b table 13-8 sdma request assi gnment for sdma sub-block (cont?d) sdma channel sdma request line sdma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-88 v1.1, 2011-03 sdma, v1.0 gpta_trig11 gpta chcr05.prsel = 1001 b - - chcr05.prsel = 1010 b tint1src eray chcr05.prsel = 1011 b - - chcr05.prsel = 1100 b - - chcr05.prsel = 1101 b - - chcr05.prsel = 1110 b - - chcr05.prsel = 1111 b 06 sdma_sr14 sdma(int_o14) chcr06.prsel = 0000 b cam_int_o0 multican chcr06.prsel = 0001 b sent_trig6 sent chcr06.prsel = 0010 b adc_sr08 adc chcr06.prsel = 0011 b ssc2_rdr ssc2 chcr 06.prsel = 0100 b asc0_rdr asc0 chcr 06.prsel = 0101 b fadc_sr00 fadc chcr06.prsel = 0110 b mil0_sr6 mil0 chcr06.prsel = 0111 b msc1_sr2 msc1 chcr06.prsel = 1000 b gpta_trig12 gpta chcr06.prsel = 1001 b ccu62_sr0 ccu62 chcr06.prsel = 1010 b ndat1src eray chcr06.prsel = 1011 b - - chcr06.prsel = 1100 b - - chcr06.prsel = 1101 b - - chcr06.prsel = 1110 b - - chcr06.prsel = 1111 b 07 sdma_sr15 sdma(int_o15) chcr07.prsel = 0000 b cam_int_o1 multican chcr07.prsel = 0001 b sent_trig7 sent chcr07.prsel = 0010 b adc_sr09 adc chcr07.prsel = 0011 b ssc2_tdr ssc2 chcr 07.prsel = 0100 b asc1_rdr asc1 chcr 07.prsel = 0101 b fadc_sr01 fadc chcr07.prsel = 0110 b table 13-8 sdma request assi gnment for sdma sub-block (cont?d) sdma channel sdma request line sdma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-89 v1.1, 2011-03 sdma, v1.0 mil0_sr7 mil0 chcr07.prsel = 0111 b msc1_sr3 msc1 chcr07.prsel = 1000 b gpta_trig13 gpta chcr07.prsel = 1001 b ccu63_sr0 ccu63 chcr07.prsel = 1010 b mbsc1src eray chcr07.prsel = 1011 b - - chcr07.prsel = 1100 b - - chcr07.prsel = 1101 b - - chcr07.prsel = 1110 b - - chcr07.prsel = 1111 b table 13-8 sdma request assi gnment for sdma sub-block (cont?d) sdma channel sdma request line sdma requesting unit selected by www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-90 v1.1, 2011-03 sdma, v1.0 13.4.2 implementation-spec ific sdma registers the sdma controller as implemented in the TC1798 contains the following additional registers: ? sdma clock control register ? service request control registers for sdma controller interrupts (sdma_srcx) figure 13-28 provides an overview of these registers. figure 13-28 sdma implementation-specific registers note: further details on interrupt handling and processing are described in the ?interrupt system? chapter of the TC1798 system units users manual. the clock generation and interrupt control configuration as implemented in the sdma controller module is shown in figure 13-29 . the sdma controller is supplied from a common module clock f sdma that has the frequency of the fpi-bus clock f fpi and is controlled via the sdma_clc clock control register. sdma interrupt registers control register sdma_ clc sdma_src0 sdma_src1 sdma_src2 sdma_src3 smca06177a sdma_src4 sdma_src5 sdma_src6 sdma_src7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-91 v1.1, 2011-03 sdma, v1.0 the sdma controller module contains in total 8 interrupt request nodes with its interrupt service request control registers: ? eight interrupt requests sr[7:0] = int_o[7:0] from the sdma controller; upper eight interrupt requests of the sdma controller int_o[15:8] are used as sdma channel trigger inputs . figure 13-29 implementation of the sdma module dma module kernel interrupt control in dma module clock control address decoder smca06178 int_o[15:0] f sd ma sr[3:0] scu f fpi sr[3:0] 16 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-92 v1.1, 2011-03 sdma, v1.0 13.4.2.1 clock control register the clock control register controls the sdma module internal f sdma clock signal. sdma_clc sdma clock control register (000 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we edis sp en diss disr r rwwrwrw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the module diss 1r module disable status bit bit indicates the current status of the module spen 2rw module suspend enable for ocds used to enable the suspend mode edis 3rw sleep mode enable control used for module sleep mode control. 0 b sleep mode request is regarded. module is enabled to go into sleep mode. 1 b sleep mode request is disregarded. sleep mode cannot be entered on a request. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-93 v1.1, 2011-03 sdma, v1.0 note: after a hardware reset operat ion, the sdma module is enabled. note: the suspend mode does not modify any of the registers. fsoe 5rw fast switch off enable used for fast clock switch-off in suspend mode. 0 b clock switch-off in suspend mode via disable control feature (secure clock switch off) selected 1 b fast clock switch off in suspend mode selected this bit can be written only if sbwe is set during the same write operation. 0 [31:6] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-94 v1.1, 2011-03 sdma, v1.0 13.4.2.2 sdma inte rrupt registers in the TC1798, the lower eight sdma controller interrupts sr[7:0] are connected to service request control registers. the up per eight sdma controller interrupt outputs sr[15:8] are used as sdma channel request inputs. sdma_srcx (x = 0-7) sdma service request control register x (2fc h - x*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp request is initiated sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-95 v1.1, 2011-03 sdma, v1.0 13.4.3 address map the sdma controller register block address map is shown in figure 13-30 . it shows how the different register blocks are arranged and adds the absolute address information. figure 13-30 sdma controller register block address map mca06179 general module control sdma control /status registers f000 3800 h f000 3810 h f000 3880 h f000 3830 h sdma channel 00 - 07 registers move engine registers sdma control /status registers f000 3854 h system service request control registers sdma service request control registers f000 3a8c h f000 3 af0 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 safe direct memory access controller (sdma) users manual 13-96 v1.1, 2011-03 sdma, v1.0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-1 v1.1, 2011-03 fce, v1.7 14 flexible crc engine (fce) this document describes the flexible crc engine (fce) module. the fce provides a parallel implementation of one or more c yclic r edundancy c ode (crc) algorithms. the current fce version for the TC1798 microcontroller implem ents the ieee 802.3 ethernet crc32 and the castagnoli crc32c polynomials. fce?s generic structure enables it to be extended with multiple crc polynomials. the primary target of fce is to be used as an hardware acceleration engine for software applications or operating systems services (compatible with autosar crc ?specification of crc routines?) using crc signatures. crc algorithms are commonly used to calculate unique message signatures that can be used to check message integrity during transport over communication channels like internal busses or interfaces between mi cro-controllers. crc signatures are also suitable to sign blocks of data residing in variable or invariable stor age elements. signatures computed based on polynomial divisi on provide a very high bit error detection capability. the fce operates as a standard fpi bus slave peripheral and is fully controlled through a set of configuration and control registers. this chapter is structured as follows: ? ?fce features? on page 14-3 ? ?operational overview? on page 14-4 ? ?fce functional description? on page 14-6 ? ?fce module registers? on page 14-14 ? ?interfaces of the fce module? on page 14-13 ? ?programming guide? on page 14-28 ? ?properties of crc code? on page 14-31 note: the fce kernel register names described in ?fce module registers? on page 14-14 are referenced in a product users manual by the module name prefix ?fce_?. note: the fce may in the future be used as well in a 16-bit microcontroller. there is no such requirement currently, but this poss ible extension can already be considered during the development phase. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-2 v1.1, 2011-03 fce, v1.7 14.1 related documentation input documents ? [d1] a painless guide to crc error detection algorithms, ross n. williams ? [d2] autosar r3.1 rev 0001, specification of crc routines v3.0.2 ? [d3] 32-bit cyclic redunda ncy codes for internet a pplications, philip koopman, international conference on dependable systems and networks (dsn), 2002 related standards and norms ? [s1] ieee 802.3 ethernet 32-bits crc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-3 v1.1, 2011-03 fce, v1.7 14.2 fce features the fce provides the following features: ? architecture supports up to 4 different crc polynomials. current fce version implements: ? ieee 802.3 crc32 ethernet polynomial: 0x82608edb 1) (crc kernel 0) ? crc32c castagnoli polynomial: 0x8f6e37a0 (crc kernel 1) ? parallel crc implementation (32-bits wide) ? data blocks to be computed by fc e shall be a multiple of 32-bits ? start address of data blocks to be comp uted by fce shall be at least 32-bits aligned ? only 32-bit write accesses are allowed to the kernel input register. ? 8 or 16-bit write accesses to the configuration registers are supported. ? register interface compliant with autosar specification for crc routines. enables to support reentrant software routines via a software-based save/restore mechanism. ? extended register interface to control reliability of fce execution. ? critical registers controlling the fce operation are implemented redundant to capture transient errors ? error notification scheme via dedicated interrupt node for: ? transient error detection: error interrupt generation (maskable) with local status register (cleared by software) ? checksum failure: error inte rrupt generation (maskable) with local status register (cleared by software) ? fce implements its own interrupt service node 1) the polynomial hexadecimal representation covers the coefficients 32 down to 1 (x 0 is implicit) enabling to use 32-bits to characterize the polynomial. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-4 v1.1, 2011-03 fce, v1.7 14.3 operational overview the fce is a standard fpi slave module. the fce is fully synchronous with the fpi bus and runs with a 1:1 clock ratio. it connects to the fpi peripheral bus of a micro-controller. figure 14-1 fce system integration: single crc kernel the fce operation is controlled over a set of memory mapped registers. the main purpose is to serve as hardware accelera tion for software applications requiring crc checksum computation. the register set has been designed to enable the fce. depending on the hardware configuration the fce may implement more crc kernels with different crc polynomials. the specific configuration for a product will be described into the product customizing chapter. every crc kernel will present the same hardware and software architecture. the rest of this document will fo cus only on the desc ription of the generic crc kernel architecture. the figure 14-2 shows a multi kernel configuration. fce fpi bus peripheral interface crc32 ieee 802.3 ethernet smif fpi slave only interface interrupt control se rvice re qu est no de smif fpi bus interface f clk einit system control unit (scu) interrupt bus (pcp or tricore) fpi bus bus control unit crc kernel 0 address decoder chip select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-5 v1.1, 2011-03 fce, v1.7 figure 14-2 fce system integration: multi-crc kernels in a multi-kernel implementation the interrupt lines are ored together, the fce only present a single interrupt node to the syst em. each crc kernel implements a status register that enables the software to identify which interrupt source is active. please refer to the sts register description for a detailed description of the status and interrupt handling. fce fpi bus peripheral interface alternate crc polynomial 3 alternate crc polynomial 2 crc32 ieee 802.3 ethernet 0x82608edb smif smif smif crc kernel 0 crc kernel 2 crc kernel 3 fpi slave only interface interrupt control se rvice requ est no de smif signal groups crc32c castagnoli 0x8f6e37a0 smif crc kernel 1 fpi bus or interrupt bus (pcp or tricore) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-6 v1.1, 2011-03 fce, v1.7 14.4 fce functional description . figure 14-3 crc kernel architecture a checksum algorithm based on crc polynomial division is characterized by the following properties: ? [1] polynomial degree (e.g. 32, that represents the highest power of two of the polynomial) ? [2] polynomial (e.g. 0x04c11db7: the 33rd bit is omitted because always equal to 1) ? [3] init value: the initia l value of the crc register generic crc kernel architecture next_crc=f(ir,crc) xor (bitwise) crc w r access decode byte reflect mux2->1 input register (ir) mux2->1 crc register (crc) mux2->1 result register (res) config register (cfg) length register (length) crc check (check) cfg.refin cfg.refout crc reflect crc register 0xffffffff 31 30 1 0 16 15 mux2->1 0x 00000000 cfg.xsel r egister with redundancy post _ crc1 post_crc2 ir_step 1 next_crc compare crc status (sts) other status signals dr awing conventions register with access protection einit ctr.fcm crc test register (ctr) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-7 v1.1, 2011-03 fce, v1.7 ? [4] input data reflected: indicates if each byte of the input parallel data is reflected before being used to compute the crc ? [4] result data reflected: indicates if the final crc value is reflected or not ? [5] xor value: indicates if a final xor operation is done before returning the crc result all the properties are static once a pol ynomial has been chosen. however the fce provides the capability to contro l the two reflection steps a nd the final xor as depicted in figure 14-3 through the cfg register. the rese t values are compatible with the implemented algorithm. the final xor control enables to select either 0xffffffff or 0x00000000 to be xored with the post_crc1 (see figure 14-3 ) value. these two values are those used by the most common crc polynomials. note: the reflection steps and final xor do not modify the properties of the crc algorithm in terms of error detection, only the crc final signature is affected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-8 v1.1, 2011-03 fce, v1.7 crc operation software must first ensure that the crc ke rnel is properly configured, especially the initial crc register value written via the crc register. if the software whishes to use the automatic signature check at the end of a message, the length register and check registers must be configured with respective ly the length (as number of 32-bit words) of the message and the expected signature ( check ). the check value takes into account the final crc reflection and xor operation. the self check is enable by the cfg.cce bit field. property: if the input message m1 consists of a message m0 appended with the crc signature of m0, then the crc signature of m1 shall be 0. the software writes as many times as necessary into the ir register according to the length of the message. if cfg.cce bit field is set, every time the ir register is written, the lengh register is decremented by one. if length is already at zero but software still writes to ir (by mistake) every bit of the length should be set to 1 and hold this value until software initializes it again for the processing of a new message. in such case the sts.mlf (message length flag) should be set and an interrupt generated if the cfg.mle (message length error) is set. the hardware monitors the transition of the length register from 1 to 0 to detect the e nd of the message and proceed with the comparison of the post_crc2 (see figure 14-3 ) value with the check register value. the next two figures provides an overview of the control and status features of a crc kernel. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-9 v1.1, 2011-03 fce, v1.7 figure 14-4 crc kernel configuration register figure 14-5 crc kernel status register crc configuration register [8] refin: input byte reflection enable [9] refout: final crc reflexion enable [10] xorout: selects value for final xor [0] interrupt control cmi: enables c rc m ismatch i nterrupt [1] interrupt control cei: enables c onfiguration e rror i nterrupt interrupt generation control crc operation control [4] cce: crc check enable [2] interrupt control lei: e nables l ength e rrori nterrupt crc algorithm control [2] interrupt control bei: e nables b us e rror i nterrupt [5] alr: automatic length reload crc status register [0] interrupt status cmf: c rc m ismatch f lag [1] interrupt status cef: c onfiguration e rror f lag [2] interrupt status lef: l ength e rror f lag [3] interrupt status bef: b us e rror f lag www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-10 v1.1, 2011-03 fce, v1.7 register protection and monitoring methods register monitoring: applied to cfg and check registers because cfg and check registers are critical to the crc operation, some mechanisms to detect and log transient errors are provided. early detection of transient failures enables to improve the failure detection time and asses the severity of the failure. the monitoring mechanisms are implemented using two redundant instances as presented in figure 14-6 . figure 14-6 register monitoring scheme let TC1798 flexible crc engine (fce) users manual 14-11 v1.1, 2011-03 fce, v1.7 register access protection: applies to length and check registers in order to reduce the probability of a mis-configuration of the check and length registers (in the case the automatic check is used), the write access to the check and length registers must follow the procedure depicted in figure 14-7 : figure 14-7 access control to check register let TC1798 flexible crc engine (fce) users manual 14-12 v1.1, 2011-03 fce, v1.7 fce interrupts each fce crc kernel provides one internal interrupt source. the interrupt lines from each crc kernel are ored together to be sent to the fce interrupt control block that implements the standard interrupt node logic and register. when multiple crc kernels are present within a fce, the interrupt lines from each crc kernel are ored together to provide a single interrupt source to the interrupt control block. if the interrupt from the fce is arbitrated, the fce interrupt handler must use the status information located within the sts status register of each crc kernel. each crc kernel provides the following interrupt sources: ?c rc m ismatch i nterrupt controlled by cfg.cmi bit field and observable via the status bit field sts.cmf (crc mismatch flag). ?c onfiguration e rror i nterrupt controlled by cfg.cei bit field and observable via the status bit field sts.cef (configuration error flag). ?l ength e rror i nterrupt controlled by cfg.lei bit field and observable via the status bit field sts.lef (length error flag). ? fpi error interrupt controlled by cfg.fei bit field and observable via the status bit field sts.fef (fpi error flag). interrupt generation rules ? a status flag shall be cleared by software by writing a 1 to the corresponding bit position. ? if an status flag is set and a new hardware condition occurs, no new interrupt is generated by the kernel: th e sts. TC1798 flexible crc engine (fce) users manual 14-13 v1.1, 2011-03 fce, v1.7 14.5 interfaces of the fce module the fce module implements its own interrupt node, therefore implements an interface to the tricore and pcp interrupt controllers. for protection purposes it uses the einit information to control the configuration of critical resources. the einit protection is described in the register chapter. table 14-1 generic fce digital connections signal from/to module i/o to fce einit scu i www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-14 v1.1, 2011-03 fce, v1.7 14.6 fce module registers figure 14-8 and table 14-3 show all registers associated with a fce crc-kernel. all fce kernel register names are described in this section. they should get the prefix ?fce_? when used in the context of a product specification. the registers are numbered by one index to indicate the related fce crc kernel (m = 0-1). fce registers overview figure 14-8 fce kernel registers figure 14-9 shows the fce module register map. the system registers region comprises the interrupt service request node and module identifier registers. crc kernel register map input register crc configuration register crc result 0x00 0x04 0x14 0x0c length register 0x08 irm len g cfg m res m crc kernel status sts m crc check 0x10 che c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-15 v1.1, 2011-03 fce, v1.7 figure 14-9 fce register map table 14-2 registers address space - fce module module base address end address note fce f032 0000 h f032 00ff h table 14-3 registers overview - crc kernel registers short name description offset addr. 1) access mode reset class descriptio n see read write fce_clc clock control register 00 h u, sv e, sv 3 page 14-17 fce_id module identification register 08 h u, sv be 3 page 14-20 irm input register m 20 h + m*20 h u, sv u, sv 3 page 14-21 resm crc result register m 24 h + m*20 h u, sv be 3 page 14-21 cfgm crc configuration register m 28 h + m*20 h u, sv e, sv 3 page 14-22 fce address map crc kernel 0 address space (m = 0 ) fpi base address for fce crc kernel 1 address space (m = 1 ) crc kernel 2 address space (m = 2 ) crc kernel 3 address system registers address space a ddress range = 256 bytes 32 byt es 32 byte s 32 b ytes 32 byte s e s @fce_fpi @ fce_fpi + 32+ 3 @ fce_fpi + 32+ 3 @ fce_fpi + 32+ 3 @ fce_fpi + 32+ 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-16 v1.1, 2011-03 fce, v1.7 access mode rules the table 14-3 ?registers overview - crc kernel registers? on page 14-15 uses the standard access mode conventions. ? e indicates that an access is only possible if the end of initialization signal from the system control unit is active. in this case supervisor mode (sv) is also mandatory. ? when u, sv are both listed it means that a read or write access can be done either in user mode (u) or supervisor mode (v). ? be stands for bus error, nsc stands for no special condition. stsm crc status register m 2c h + m*20 h u, sv u, sv 3 page 14-24 lengthm crc length register m 30 h + m*20 h u, sv u, sv 3 page 14-25 checkm crc check register m 34 h + m*20 h u, sv u, sv 3 page 14-25 crcm crc register m 38 h + m*20 h u, sv u, sv 3 page 14-26 ctrm crc test register m 3c h + m*20 h u, sv u, sv 3 page 14-27 fce_src service request control register fc h u, sv sv 3 page 14-18 1) the absolute register byte address for each crc kernel m is calculated as follows: crc kernel register base address ( table 14-2 ) + m*20h, m = 0-1 table 14-3 registers overview - crc kernel registers short name description offset addr. 1) access mode reset class descriptio n see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-17 v1.1, 2011-03 fce, v1.7 14.6.1 system registers fce module clock control register. this register is global to fce and not part of a crc kernel. fce does not implement a fractional divider, the fce kernel (when enabled) always runs with the peripheral bus clock. fce_clc control clock register (00 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fso e sbw e edis spe n diss disr r rwwrwrwrhrw field bits type description disr 0rw module disable bit request used for enable/disable control of the module 0 b module disable is not requested 1 b module disable is requested diss 1rh module disable bit status bit indicates the current status of the module 0 b module is enabled 1 b module is disabled spen 2rw module suspend enable used for enabling the suspend mode. 0 b module cannot be suspended (suspend is disabled) 1 b module can be suspended (suspend is enabled) this bit can be written only if sbwe is set during the same write operation. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-18 v1.1, 2011-03 fce, v1.7 edis 3rw sleep mode enable control used for module sleep mode control. 0 b sleep mode request is regarded. module is enabled to go into sleep mode. 1 b sleep mode request is disregarded: sleep mode cannot be entered on a request. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. 0 b bits spen and fsoe are write-protected 1 b bits spen and fsoe are overwritten by respective value of spen or fsoe reading this bit returns always 0. fsoe 5rw fast switch off enable used for fast clock switch-off in suspend mode. 0 b clock switch-off in suspend mode via disable control feature (secure clock switch off) selected 1 b fast clock switch off in suspend mode selected this bit can be written only if sbwe is set during the same write operation. 0 [31:6] r reserved read as 0; should be written with 0. fce_src service request control register (fc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn wwrwhrwrrw r rw field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-19 v1.1, 2011-03 fce, v1.7 fce module identification register. this register is global to fce and not part of a crc kernel. field bits type description srpn [7:0] rw service request priority number 00 h service request is never serviced 01 h service request is on lowest priority ... ff h service request is on highest priority tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp service is initiated sre 12 rw service request enable 0 b service request is disabled 1 b service request is enabled srr 13 rwh service request flag 0 b no service request is pending 1 b a service request is pending 1) 1) the bit field srr is automatically cleared by hardware at the end of an interrupt arbitration round if the node was the winner, therefore this information is not suitable for interrupt plausibility checks. clrr 14 w request clear bit clrr is required to clear srr. 0 b no action 1 b clear srr; bit value is not stored; read always returns 0; no action if setr is set also. setr 15 w request set bit setr is required to set srr. 0 b no action 1 b set srr; bit value is not stored; read always returns 0; no action if clrr is set also. 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-20 v1.1, 2011-03 fce, v1.7 fce_id module identificat ion register (08 h ) reset value: 008a c001 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). mod_type [15:8] r module type the bit field is set to c0 h which defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines a module identification number. the value for the fce module is 008a h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-21 v1.1, 2011-03 fce, v1.7 14.6.2 crc kernel cont rol/status registers a write to irm triggers the crc kernel to update the message checksum according to the ir contents and to the current crc regist er contents. only 32-bit write transactions are allowed to irm registers, any other fpi write transaction will lead to a bus error. irm (m = 0-1) input register m (20 h + m*20 h ) reset value: 0000 0000 h 31 0 ir rw field bits type description ir [31:0] rw input register this bit field holds the 32-bit data to be computed resm (m = 0-1) crc result register m (24 h + m*20 h ) reset value: ffff ffff h 31 0 res r field bits type description res [31:0] r result register returns the final crc value including crc reflection and final xor according to the cfg register configuration. writing to this register has no effect. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-22 v1.1, 2011-03 fce, v1.7 cfgm (m = 0-1) crc configuration register m (28 h + m*20 h ) reset value: 0000 0700 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 x sel ref out ref in 0 cce fei lei cei cmi r rw rw rw r rw rw rw rw rw field bits type description cmi 0rw crc mismatch interrupt 0 b crc mismatch interrupt is disabled 1 b crc mismatch interrupt is enabled cei 1rw configuration error interrupt when enabled, an configuration error interrupt is generated whenever a mismatch is detected in the cfg and check redundant registers. 0 b configuration error interrupt is disabled 1 b configuration error interrupt is enabled lei 2rw length error interrupt when enabled, an length error interrupt is generated if software writes to ir register with length equal to 0 and cfg.cce is set to 1. 0 b length error interrupt is disabled 1 b length error interrupt is enabled fei 3rw fpi error interrupt when enabled, an interrupt is generated if a fpi write transaction other than 32-bits is issued to the input register. 0 b fpi error interrupt is disabled 1 b fpi error interrupt is enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-23 v1.1, 2011-03 fce, v1.7 cce 4rw crc check comparison 0 b crc check comparison at the end of a message is disabled 1 b crc check comparison at the end of a message is enabled refin 8rw ir byte wise reflection 0 b ir byte wise reflection is disabled 1 b ir byte wise reflection is enabled refout 9rw crc 32-bit wise reflection 0 b crc 32-bit wise is disabled 1 b crc 32-bit wise is enabled xsel 10 rw selects the value to be xored with the final crc 0 b 0x00000000 1 b 0xffffffff 0 [7:5], [31:11] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-24 v1.1, 2011-03 fce, v1.7 stsm (m = 0-1) crc status register m (2c h + m*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fef lef cef cmf r rwh rwh rwh rwh field bits type description cmf 0rwh crc mismatch flag this bit is set per hardware only. to clear this bit, software must write a 1 to this bit field location. writing 0 per software has no effect. if this bit is equal to 1 and a new interrupt is raised by hardware, it will not be propagated to the fce interrupt service node. cef 1rwh configuration error flag this bit is set per hardware only. to clear this bit, software must write a 1 to this bit field location. writing 0 per software has no effect. if this bit is equal to 1 and a new interrupt is raised by hardware, it will not be propagated to the fce interrupt service node. lef 2rwh length error flag this bit is set per hardware only. to clear this bit, software must write a 1 to this bit field location. writing 0 per software has no effect. if this bit is equal to 1 and a new interrupt is raised by hardware, it will not be propagated to the fce interrupt service node. fef 3rwh fpi error flag this bit is set per hardware only. to clear this bit, software must write a 1 to this bit field location. writing 0 per software has no effect. if this bit is equal to 1 and a new interrupt is raised by hardware, it will not be propagated to the fce interrupt service node. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-25 v1.1, 2011-03 fce, v1.7 0 [31:4] r reserved read as 0; should be written with 0. lengthm (m = 0-1) crc length register m (30 h + m*20 h ) reset value: 0000 0000 h 31 0 reserved length rrwh field bits type description length [15:0] rwh message length register number of 32-bits words building the message over which the crc checksum is calculated. this bit field is modified by the hardware: every write to the ir register decrements the value of the length bit field. 0 [31:16] r reserved read as 0; should be written with 0. checkm (m = 0-1) crc check register m (34 h + m*20 h ) reset value: 0000 0000 h 31 0 check rw field bits type description check [31:0] rw check register expected crc value to be checked by the hardware upon detection of a 1 to 0 transition of the length register. the comparison is enabled by the cfg.cce bit field field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-26 v1.1, 2011-03 fce, v1.7 crcm (m = 0-1) crc register m (38 h + m*20 h ) reset value: 0000 0000 h 31 0 crc rwh field bits type description crc [31:0] rwh crc register this register enables to directly access the internal crc register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-27 v1.1, 2011-03 fce, v1.7 ctrm (m = 0-1) crc test register m (3c h + m*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 frm _ch eck frm _ cfg fcm r rwrwrw field bits type description fcm 0rw force crc mismatch forces the crc compare logic to issue an error regardless of the check and crc values. the hardware detects a 0 to 1 transition of this bit field and triggers a crc mismatch interrupt frm_cfg 1rw force cfg register mismatch this field is used to control the error injection mechanism used to check the compare logic of the redundant cfg registers. this is a one shot operation. when the hardware detects a 0 to 1 transition of this bit field it triggers a configuration mismatch interrupt (if enabled by the corresponding cfgm register). frm_check 2rw force check register mismatch this field is used to control the error injection mechanism used to check the compare logic of the redundant check registers. this is a one shot operation. the hardware detects a 0 to 1 transition of this bit field and triggers a check register mismatch interrupt (if enabled by the corresponding cfgm register). 0 [31:3] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-28 v1.1, 2011-03 fce, v1.7 14.7 programming guide this section provides some guidelines showing how the fce configuration features can be mapped to the autosar api for crc32 routines. figure 14-10 autosar initialization api uint32 crc_initializecrc 32 ( bool crc_refin, bool crc_refout, uint32 crc_xorout ) uint32 crc_calculatecrc32 ( const uint8 * crc_dataptr, uint32 crc_length, uint32 crc_startvalue32 ) sw fce einit crc_initializecrc32 (true, true, 0xffffffff ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-29 v1.1, 2011-03 fce, v1.7 figure 14-11 autosar crc_calculate api sw fce execution thread crc_calculatecrc32 (crc_dataptr, crc_lenght, crc_startvalue32) note: crc_calculatecrc TC1798 flexible crc engine (fce) users manual 14-30 v1.1, 2011-03 fce, v1.7 figure 14-12 autosar crc_calculate api with save/restore sw fce execution thread crc_calculatecrc32 (crc_dataptr, crc_lenght, crc_startvalue32) crc_calculatecrc TC1798 flexible crc engine (fce) users manual 14-31 v1.1, 2011-03 fce, v1.7 14.8 properties of crc code hamming distance the hamming distance defines the error detection capability of a crc polynomial. a cyclic code with a hamming distance of d can detect all d-1 bit errors. table 14-4 ?hamming distance as a function of message length (bits)? on page 14-31 shows the dependency of the hamming distance with the length of the message. table 14-4 hamming distance as a function of message length (bits) 1) 1) data from technical paper ?32-bit cyclic redundancy codes for internet applications? by philip koopman, carnegie mellon university, 2002 hamming distance ieee crc32 castagnoli 15 8 - 10 14 8 - 10 13 8 - 10 12 11 - 12 8 - 17 11 13 - 21 18 - 21 10 22 - 34 22 - 27 9 35 - 57 22 - 27 8 58 - 91 28 - 58 7 92 - 171 59 - 81 6 172 - 268 82 - 1060 5 269 - 2974 1061 - 65504 4 2973 - 91607 1061 - 65504 3 91607 - 131072 65506 - 131072 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexible crc engine (fce) users manual 14-32 v1.1, 2011-03 fce, v1.7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-1 v1.1, 2011-03 ebu, v1.9 15 sri external bus unit (ebu) the external bus unit (ebu), TC1798 controls the transactions between external memories or peripheral units, and the inter nal memories and peripheral units. the basic interfaces of the ebu are shown in figure 15-1 . figure 15-1 ebu interface diagram the ebu is internally connected to the sri bus matrix by a single slave interface. 15.1 overview the memory controller module for sri-based systems connects on-chip controller cores (e.g. tricore cpu, dma controller) to external resources such as memories and peripherals. figure 15-2 shows memory controller within a typical system. any sri master can (in conjunction with an sri matrix) access external memories through the memory controller. 15.2 references the ebu complies with the requirements of the following specifications when generating accesses to external memories: ? jesd21-c revision 18a, sections relating to sdram & lpsdram (3.11.5.1) ? jesd21-c revision 18a, section relating to lpddr nvm (3.6.3). ? jesd209, low power double data rate (lpddr) sdram standard ? open nand flash interface specificati on. revision 2.0, 27-february-2008 ? intel?, pc sdram specification, revision 1.7, november 1999. external bus unit ebu mca05712 32 to/from sri bus matrix address/ data bus address bus sram control chip select lines 24 9 4 64 sdram control 7 burst flash control 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-2 v1.1, 2011-03 ebu, v1.9 15.3 feature list features supported in the memory controller:- ? highly programmable access parameters. ? intel-style peripheral/device support. ? burst flash support (see section 15.17 for specific device types). ? cellular ram support (see section 15.17 for specific device types). ? nand flash ? multiplexed access (address & data on the same bus) ? data buffering: two read buffers. single write buffer in the sri interface. ? four programmable address regions. ? external bus frequency: module frequency:flash clock = 1:1, 1:2, 1:3 or 1:4. ? jedec 42.4 lpddr nvm support ? ddr burst flash support. ? sdram support (see section 15.18 for specific device types). ? ddram support (see section 15.18 for specific device types). ? onfi 2.0 nand flash support ? configurable clock generation and edge recovery logic using a programmable dll (delay locked loop) to control clock phase and edge positioning ? external bus frequency: module frequency:ddr device clock = 1:1, 1:2, or 1:4. figure 15-2 typical external memory system ebua0001 ebua0001 - typical external memory system memory interface 32 bit sdram 32 bit xip burst flash 32 bit data flash 32 bit 32 bit peripheral data www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-3 v1.1, 2011-03 ebu, v1.9 15.4 differences between audo-future and audo-max ebus the clocking scheme of the ebu has been upgraded. a dll has been added to allow reconstruction of a 50% duty cycle clock and the generation of phase shifted clocks for ddr device support. this has added a new register, ebu_dllcon , to the ebu register space. the ebu can now also be configured to run at half the cpu frequency or asynchronously to the cpu using the flexray pll as its clock source. the features are programmed using the sync and div2 fields in ebu_clc . new features have been added to the ebu_modcon register: ? busstate , a monitor bit which is set to 1 b when the ebu owns the external bus ? fast_sri , the normal address process decode takes 2 clock cycles. if the sri clock frequency is 180 mhz or lower, then this bit can be set to reduce the decode time to 1 clock cycle. ? fifo_bypass , a control bit for the data read mode for devices using an sdram protocol or ddr data transfer protocol. under normal circumstances the read data from these devices is considered to be asynchronous and is resynchronised to the ebu clock using a data fifo. if the external bus frequency is low enough, this bit can be set to load the data directly into the internal read buffers. this will remove one external bus clock from the access latency. to make space for these, the four bit gl obalcs field previously in modcon has been made region specific and moved to individual globalcs fields for each cs in ebu_addrselx (x = 0-3). support for three new memory protocols has been added. all of these can be grouped under the heading ddr flash: ? lpddr-nvm (jedec 42.4). this is a ddr memory protocol based on the pc100 sdram standard. adding this protocol also allows the ebu to support ddram and sdram (where environmental conditions allow). ? the following registers have been added to the ebu to allow configuration of the new protocol: ebu_sdrmcon ; ebu_sdrmod ; ebu_sdrmref ; ebu_sdrstat ; ebu_ddrncon ; ebu_ddrnmod ; ebu_ddrnmod2 ; ebu_ddrnsrr ; ebu_ddrnprld and ebu_ddrntagx (x=0-3) ? the ebu will now also recognise values of 8 d (sdram), 10 d (lpddr-nvm) and 12 d (ddram) as being valid for the agen fields in ebu_busrconx (x = 0-3) and ebu_buswconx (x = 0-3) ? a new differential clock output (ddrclko & ddrclko ), new control signals (ras , cas , cke), and data strobes (dqs[3:0]) have been added to the ebu pinout. the byte control signals (bc[3:0]) now have an alternate function as data modifiers (dqm[3:0]). ? spansion 29ds032j. (1.8v i/o mode only) this is a hybrid device using a standard flash command protocol and ddr transfer of read data. support for this device is configured using an agen value of 9 d . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-4 v1.1, 2011-03 ebu, v1.9 ? onfi 2.0. ddr interface protocol for nand flash memories. support for this device type is configured using an agen value of 13 d . adding this device has required the following changes to the ebu: ?the portw field in ebu_busrconx (x = 0-3) now takes 00 b as a valid value configuring an 8 bit device. this is valid for all values of agen except 8 d , 9 d , 10 d and 12 d . ? nand flash control signals ale and cre are now output on adv and baa respectively. this applies to agen value 2 d as well as 13 d . ? the timing of the mr/w signal has been changed for accesses to memories configured using agen values 2 d and 13 d . for these accesses the timing of mr/w will follow the standard rd/wr signal. additional fields have also been added to the ebu_usercon register to provide finer control of switching pins between ebu and gpio functions. this will now allow individual high order address bits to be reallocated for gpio if not required by attached memory devices and also address bits 15 down to 0 to be allocated for gpio if all attached memories have multiplexed address and data connections. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-5 v1.1, 2011-03 ebu, v1.9 15.5 ebu interface signals the external ebu interface signals are listed in table 15-1 below. in many case, the ebu pins have multiple functions depending on the memory devices configured and being accessed. in these cases, the primary designation of the pin is emphasised. table 15-1 ebu interface signals signal/pin type function ad[31:0] o multiplexed address/data bus lines 0-31 a[27:0] o address bus lines 0-27. dqs[3:0] i/o data strobe lines for ddr devices. can also be used as a[27:24] if ddr devices are not attached to the ebu. dqs[3]->a[24], dqs[2]-> a[25], dqs[1]->a[26], dqs[0]->a[27] a[27:24] o cs[3:0] o chip select 0-3 cscomb o combined chip select for global select rd o read control line rd/wr o write control line adv o address valid output. can be inverted for use as address latch enable. also used as ale for nand flash. ale o bc[3:0] o byte control lines 3 to 0 alternatively, these pins are used as data mask outputs when accessing jedec 42.4 lpddr-nvm memory, ddram orsdram dqm[3:0] o bfclko o clock output for synchronous accesses bfclki i feedback clock input for synchronous accesses ddrclko o clock output for jedec 42.4 lpddr-nvm memory accesses & ddram memory accesses. alternately, sdram clock output. sdclko o ddrclko o negative phase of balanced ddrclko signal alternatively, can also be used as the negative phase of bfclko if a ddr nor flash memory is attached or the feedback clock for sdclko. sdclki i bfclko o cke o clock enable output for jedec 42.4 lpddr-nvm memory, ddram and sdram ras o row address strobe for jedec 42.4 lpddr-nvm memory, ddram and sdram www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-6 v1.1, 2011-03 ebu, v1.9 15.5.1 address/data bus, ad[31:0] this bus transfers address and data information. the width of this bus is 32 bits. external devices with 8, 16 or 32 bits of data width can be connected to the data bus. the ebu adjusts the data on the data bus to the width of the external device, according to the programmed parameters in its control registers. the byte control signals bc[3:0] specify which parts of the data bus carry valid data. 15.5.2 address bus, a[27:0] the total address bus of the ebu consists of 24 address output lines, giving a directly addressable range of 64 mbytes (2 24 , 32 bit words). an external device can be selected via one of the chip select lines. since there are four chip select lines, four such devices with up to 256 mbytes of address range can be used in the external system. 15.5.3 global chip select, cscomb the ebu provides a combined or global chip select line. this can be programmed to be asserted with any combination of the normal chip selects cs[3:0] . see chapter 15.13.7 for more details. 15.5.4 chip selects, cs[3:0] the ebu provides four chip select outputs, cs0 , cs1 , cs2 and cs3 . the address ranges for which these chip selects are generated are programmed separately for each chip select line in a very flexible way via the address select registers ebu_addrselx. more details are described on page 15-53 . cas o column address strobe for jedec 42.4 lpddr-nvm memory, ddram and sdram wait i wait input mr/w o write control line with timing suitable for motorola peripherals. onfi 2.0 flash clock output oclko o baa o burst address advance output. also control register enable (cre) for nand flash accesses cre o hold i hold request input hlda o hold acknowledge output breq o bus request output table 15-1 ebu interface signals (cont?d) signal/pin type function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-7 v1.1, 2011-03 ebu, v1.9 15.5.5 read/write control lines, rd , rd/wr two lines are provided to trigger the read (rd ) and write (rd/wr ) operations of external devices. while some read/write devices require both signals, there are devices with only one control input. the rd/wr line is then used for these devices. this line will go to an active-low level on a write, and will stay inactive high on a read. the external device should only evaluate this signal in conjunction with an active chip select. thus, an active chip select in combination wi th a high level on the rd/wr line indicates a read access to this device. 15.5.6 address valid, adv the address valid signal, adv , validates the address lines a[23:0] (and also the address placed on the data bus ad[31:0] when attaching multiplexed address/data devices). it can be used to latch these addresses externally. the polarity can be inverted to allow use as a positive logic address latch enable signal (ale). it is also used as ale when accessing nand flash. in this case, the timing will be adjusted so that it is stable for the entire access. 15.5.7 byte c ontrols, bc[3:0] the byte control signals bc[3:0] select the appropriate byte lanes of the data bus for both read and write accesses. table 15-2 shows the activation on access to a 16-bit or 8-bit external device. please note that this scheme supports little-endian devices. signals bcx can be programmed for different timing. the available modes cover a wide range of external devices, such as ram with separate byte write-enable signals, and ram with separate byte chip select signals. this allows external devices to connect without any external ?glue? logic. table 15-2 byte control pin usage width of external device bc3 bc2 bc1 bc0 32-bit device with byte write capability d[31:24] d[23:16] d[15:8] d[7:0] 16-bit device with byte write capability inactive (high) inactive (high) d[15:8] d[7:0] 8-bit device inactive (high) inactive (high) inactive (high) d[7:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-8 v1.1, 2011-03 ebu, v1.9 15.5.8 burst flash clock ou tput/input, bfclko/bfclko /bfclki the flash clock output signal of the ebu is pr ovided at pin bfclko. it is used for timing purposes (timing reference) during burst mode accesses. bfclko is, by default, only generated during synchronous accesses. the clock input bfclki of the ebu is used to latch read data into the ebu. normally bfclki is directly fedback and connected to bfclko. this feedback path can be configured externally to maximize the operat ing fiuency for a given flash device or to compensate the bfclko clock pad delay. more details are given on page 15-91 . ddr flash devices require a differential clock. if a ddr flash device is configured, then bfclko will be generated on the ddrclko pin. 15.5.9 wait input, wait this is an input signal to the ebu that is used to dynamically insert wait states into read or write data cycles controlled by the device on the external bus. 15.5.10 burst address advance, baa the burst address advance output, baa , is provided for advancing the addresses during a burst flash read cycle. this signal is not assert ed for burst flash writes. this pin also functions as the control register enable (cre) for accesses to nand flash. 15.5.11 motorola periphe ral write signal, mr/w a write control signal held valid for the duration of an access (from chip select asserted to chip select negated). table 15-3 byte control signal timing options mode ebu_busconx. bcgen description chip select mode 00 b bcx signals have the same timing as the generated chip select cs . control mode 01 b bcx signals have the same timing as the generated control signals rd or rd/wr . write enable mode 10 b bcx signals have the same timing as the generated control signal rd/wr . dqm mode 11 b bcx signals are used as dqm for sdram/ddram. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-9 v1.1, 2011-03 ebu, v1.9 15.5.12 onfi 2.0 clock output, oclko the onfi 2.0 devices require a clock i nput when working as a synchronous, ddr memory. the input pin on the device is also used as the write input, wr , when the device is operating in asynchronous mode. to enable the device to be successfully connected, a copy of the bfclko signal will be generated on the mr/w pin as oclcko when a region is configured for onfi 2.0 memory. 15.5.13 ddr clock outp ut/input ddrc lko/ddrclko /sdclki the ebu provides a clock output for sdram devices on the sdclko pin. sdclko is, by default, a continuously running signal but can also be configured to switch off between accesses to conserve power. the feedback clock input, sdclki, is used as a timing reference for the capture of read data on sdram accesses. it should be connected via a pcb trace to the clock pin of the sdram device. for ddr devices a differential clock is required but the use of dqs lines to clock read data means that sdclki is not necessary. in this case, the negative phase clock, sdclko , is output on the sdclki pin. if the combined clock mode is selected, s dclko will be output on the bfclko pin. 15.5.14 lpddr-nvm, ddram, sdram control signals, cke, cas and ras these signals implement, along with the rd/wr signal, the command interface for an attached memory device using an pc100 sdram type control protocol. 15.5.15 ddr data strobes, dqs[3:0] the dqs signals are used as clocks for data being transferred using ddr protocols. they are driven by the ebu on write accesses and by the attached memory device on read accesses. 15.5.16 bus arbitration signals, hold , hlda , and breq the hold input signal is the external bus arbitration signal that indicates to the ebu when an external bus master requests to obtain ownership of the external bus. the hlda output signal is the external bus arbitration signal that indicates to a external bus master that it has obtained ownership of the external bus from the ebu. the breq output signal is the external bus arbitration signal that is asserted by the ebu when it requests to obtain back the ownership of the external bus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-10 v1.1, 2011-03 ebu, v1.9 15.5.17 ebu reset the ebu is asynchronously initialised by the application reset. 15.5.17.1 allocation of unused signals as gpio the ebu will allow pins not required for its programmed configuration to be allocated for use as gpio. the signals required are as defined below: table 15-4 ebu interface signals required by operating mode signal/pin when needed by ebu ad[15:0] always needed when the ebu is enabled. ebu_modcon.arbmode != 00 b 1) rd rd/wr mr/w bc[1:0] a[18:16] wait this signal is required by the ebu when any enable region is configured to use wait by setting the busconx.wait field to a value other than 00 b (ebu_modcon.arbmode != 00 b ) and (ebu_addrselx.regenab=1 b or ebu_addrselx.altenab=1 b ) and (busrconx.wait != 00 b ) a[27:19] these address bits can be indvidually enabled for use as gpio by setting the relevant enable bit in the usercon register. setting ebu_modcon.arbmode = 00 b will also enable for gpio. if ddr devices are connected, then the 4 msbs of the address are used for dqs and will be enabled regardless of the state of the usercon bits. a[15:0] these address bits are not required if the only devices connected have a multiplexed address/data bus. in this case they will be made available for gpio if usercon.addrlsw=1 b . setting ebu_modcon.arbmode = 00 b will also enable for gpio. adv the adv output can be made available for gpio by setting the advio bit in the usercon register to 1 b . setting ebu_modcon.arbmode = 00 b will also enable for gpio. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-11 v1.1, 2011-03 ebu, v1.9 bfclko these signals are required by the ebu when the ebu is enabled and an enabled region is configured for burst device support (ebu_modcon.arbmode != 00 b ) and (((ebu_addrselx.regenab=1 b ) or (ebu_addrselx.altenab=1 b ) or (busrconx.bfcmsel=0 b )) and (busconx.agen = 1 h or 3 h or 6 h or 5 h or 7 h or 9 h or b h )) or (modcon.clkcomb = 1 b ) ) bfclki baa ras these signals are required by the ebu when the ebu is enabled and an enabled region is configured for sdram, ddram or lpddr- nvm support. (ddrclko is also required if ddr burst flash is connected and will additionally be enabled in this case) (ebu_modcon.arbmode != 00 b ) and ((ebu_addrselx.regenab=1 b or ebu_addrselx.altenab=1 b ) and (busrconx.agen = 8 d or 10 d or 12 d ) cas cke ddrclko ddrclko hold these signals are required by the ebu when the ebu is configured to arbitrate for the external bus. e.g. ebu_modcon.arbmode = 01 b or 10 b breq hlda ad[31:16] these signals are required by the ebu when the ebu is enabled and an enabled region is configured for accessing 32 bit memory (ebu_modcon.arbmode != 00 b ) and ((ebu_addrselx.regenab=1 b or ebu_addrselx.altenab=1 b ) and (busrconx.portw = 10 b or 11 b ) dqs[3:2] bc[3:2] cs[3:0] the chip select lines are individually controlled and will be required for ebu operation when the associated memory region is enabled. (ebu_modcon.arbmode != 00 b ) and (ebu_addrselx.regenab=1 b or ebu_addrselx.altenab=1 b ) cscomb the global chip select line is required by the ebu when any ebu_addrsel. globalcs != 0 b and the ebu is enabled (ebu_modcon.arbmode != 00 b ) 1) if the ebu is disabled by writing 00 to the ebuco n.arbmode field, there will be a delay before the signals become available for gpio usage as the ebu will wait for all pending external memory accesses to be completed and the arbitration logic to return to the ?nobus? state before releasing the signals. table 15-4 ebu interface signals required by operating mode (cont?d) signal/pin when needed by ebu www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-12 v1.1, 2011-03 ebu, v1.9 15.6 bus state during reset the state of the various bus signals is controlled by memory controller during reset as follows:- table 15-5 memory controller extern al bus pin states during reset pin name state during reset 1) state during idle 2) state during ?no bus? mode ad(31:16) gpio high impedance - pull ups enabled to pull to ?1?. gpio ad(15:0) high impedance pull to ?1? (high). high impedance - pull ups enabled to pull to ?1?. high impedance - pull ups enabled to pull to ?1? (high). a(27:19) gpio driven to ?0? after reset, otherwise last used address gpio a(19:0) high impedance pull to ?1? (high). driven to ?1? (high) at reset, last used address when idle high impedance pull to ?1? (high). cs (0) high impedance pull to ?1? (high). driven to ?1? (high). h igh impedance pull to ?1? (high). cs (3:1) gpio driven to ?1? (high). gpio rd high impedance pull to ?1? (high). driven to ?1? (high). h igh impedance pull to ?1? (high). wr high impedance pull to ?1? (high). driven to ?1? (high). h igh impedance pull to ?1? (high). cas gpio driven to ?1? (high). gpio ras gpio driven to ?1? (high). gpio cke gpio dependant on sdram clocking/power save mode gpio adv gpio driven to ?1? (high). gpio ddrclko gpio driven to ?0? (low). gpio www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-13 v1.1, 2011-03 ebu, v1.9 applicable reset is cgu_con_clk_rst_n_i. 15.7 memory controller structure ddrclko gpio high impedance gpio bfclki gpio high impedance gpio bfclko gpio driven to ?0? (low). gpio bc (3:2) gpio driven to ?1? (high). gpio bc (1:0) high impedance pull to ?1? (high). driven to ?1? (high). h igh impedance pull to ?1? (high). wait gpio always an input ( must have a pull-resistor to inactive state ). gpio cscomb gpio driven to ?1? (high). gpio hold gpio depends on state of bus arbitration logic gpio hlda gpio gpio breq gpio gpio mr/w gpio driven to ?1? (high). gpio baa gpio driven to ?1? (high). gpio 1) gpio controlled pins should be high impedance with pull up during reset. 2) assuming that the pins have not been made available as gpio. table 15-5 memory controller extern al bus pin states during reset (cont?d) pin name state during reset 1) state during idle 2) state during ?no bus? mode www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-14 v1.1, 2011-03 ebu, v1.9 figure 15-3 memory cont roller block diagram the sri interface translates sri transactions from the ports into appropriate transaction requests which can be transferred to the arbiter. the interface can handle two transactions simultaneously as required by the sri protocol which has a two deep, command pipeline. the interface will also generate an ecc code for all read data returned and will check ecc codes received along with each sri transaction. in the event of a transaction failing the ecc che ck, an error will be flagged to the system for further processing and the transaction will be terminated with an sri error. the arbiter looks at the transaction requests and schedules corresponding requests to the relevant state machine. only one state machine can be active at any time and the arbiter is designed to preven t out-of-order execution. the dedicated state machines are used to sequence control signals and to co-ordinate accesses to each of the different external memory/device types and also the internal registers. if two consecutive accesses are to the same state machine, the second access will be queued before the first has completed. this allows accesses to run ?back-to-back? on the external bus and maximises bandwidth utilisation. control lines ebua0004 - block diagram region selector asynchronous (& nand flash) state machine data & address path address & data transaction address (28-bit) write data (64-bit) read data buffer (4x64-bit) 8-word read data buffer 8-word read data buffer transaction handler transaction handler sri data (64-bit) sri address (32-bit) sri command sri bus transaction & select transaction request arbiter burst-flash state machine control registers sdram/ddram state machine 8 word write buffer sri interface registers www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-15 v1.1, 2011-03 ebu, v1.9 15.8 memory controlle r read architecture the memory controller contains two, identical read buffers each with a capacity of 4, 64 bit words. a read access will be allowed to proceed if one of the buffers is flagged as available. the data read from the external memory will be stored in the read buffer and the outputs from the read buffer will be mult iplexed to the sri por t. once the sri port signals that all data has been returned to the requesting sri master, the read buffer will again be flagged as available. this architecture allows reads to be in progress simultaneously, as a second read can be running while the first read is still waiting for data to be returned to the sri master. 15.9 access arbitration arbitration of sri accesses is handled by the sri matrix. the ebu will only ensure that accesses are processed in the order that they arrive at the sri port 15.9.1 programming sequence locking programming sequences for some burst flash devices require that the source of the programming transactions has exclusive access to the external memory device for the duration of the write sequence. if such devices are used and can be accessed by multiple transaction sources then the ?locked programming sequence? feature can be enabled via register bit ebu_buswconx.lockcs. a programming sequence is considered to start when the processor data port carries out an initial write transaction. note: it has been assumed that the processor data port is the only port that will ever attempt programming operations to a nor flash. a programming sequence is considered to have ended when the processor data port carries out a subsequent read transaction to a cs which it has locked, or when the processor data port, which has locked csx, carries out a write to csy resulting in the locking of csy, or when an internal fail-safe timeout expires. a programming sequence lock is aborted if an access is attempted from the processor instruction port to the locked device. an aborted sequence will be flagged by the status bit. lckabrt, in the ebu_modcon register. this flag will be cleared by writing 1 b to the lckabrt field. note: this is to prevent a system livelock in the event that the code running the programming sequence is interrupted. if programming sequence locking is enabled for csx , then once a write transaction to cs x is accepted from the proc essor data port, the sri inte rface automatically ?locks? ownership of the device on cs x to that port. any transaction requests (read or write) to the same cs x from other transaction sources wil be errored until the end of the www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-16 v1.1, 2011-03 ebu, v1.9 programming sequence. accesses to other cs y or cs z devices from the other initiators will be permitted. sequence ?locking? takes place in the sri interface block. the fail-safe timeout timer defaults to a count of 255 and is decremented at a frequency of ebu_clk/16. it commences counting from the preload value every time a write completes. the default value can be changed by writing to the ebu_buscon.locktimeout register field. 15.9.2 source access inhibit transactions not initiated by the processor can be temporarily denied access to external memory by setting the ebu_modcon.access_inh bit. this is to allow reprogramming of access parameters for external memory by the processor while preventing the other potential masters from attempting to access with invalid settings. while this bit is set accesses which do not originate from one of the processor ports will be errored. port access inhibit will be enabled after reset. note: if a dll relock is trigged while access inhibit is active, then access inhibit should not be removed until a dll relock has completed. 15.10 clocking strategy and local clock generation the memory controller can be configured to operate from several possible clock sources. the clock generation logic is used to select between these clock sources and generate the internal clock used for the memory controller, ebu_clk. 15.10.1 clocking modes the bridges can be operated in one of two modes using one of two clocks:- ? asynchronous mode: the sri clock a nd memory controller internal clock (ebu_clk) are assumed to be asynchronous . ebu_clk is derived from the flexray pll output. ? synchronous mode: the ebu_clk is derived from the controller (sri) clock. the ebu_clk and sri interface clocks have aligned edges (although pulse swallowing can be used on the ebu_clk clock, so that the ebu core can run at a lower frequency than the sri bus matrix). ? synchronous or asynchronous mode at half of sri clock: the ebu clock is running at half the frequency of the processor clock. the ebu clock is edge aligned with the processor and sri interface clocks. the clock for the sri interface of the memory controller, is always be derived from the same synchronous source (the processor clock, . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-17 v1.1, 2011-03 ebu, v1.9 operation of the bridge in asynchronous mode provides maximum flexibility in clocking different domains at different frequencies. this is, however, at the cost of additional latency (for signal resynchronisation) through the bridge. operation of the bridge in synchronous mode minimises the latency through the bridge at the cost of forcing the sri and ebu_clk domains to run from the same source clock (the processor clock). the mode of operation of the bridge is controlled by the ebu_clc .sync register field. the ebu_clc .syncack field will be updated to report the current operating mode. the ebu_clc .sync register field can be used (dynamically) to switch between these two modes. the memory controller contains internal control logic to sequence the switching between modes to ensure that external bus accesses are not corrupted as a result of switching clocking modes. the memory controller updates the ebu_clc .syncack to signal the status of the bridge (?1? = operating in synchronous mode, ?0? = operating in asynchronous mode). if ebu_clc .div2 is set to 0 b , then ebu_clc .sync also controls the clock input and switches it between the processor clock and the flexray pll output. however, if ebu_clc .div2 is set to 1 b , then ebu clock source is forced to be half the frequency of the processor clock and ebu_clc .sync only enables and disables the resynchronisation stages necessary for asynchronous operation. setting ebu_clc .sync to 0 b will only activate the resynchronisation stages, the ebu clock will remain fixed at half the processor clock frequency . the value of div2 in use by the memory controller is stored in the ebu_clc .div2ack field. 15.10.2 local clock divider a local divider can be used to reduce the frequency of ebu_clk. the divider can be programmed to for divide ratios of 1:1, 2:1, 3:1 or 4:1 using the ebu_clc . ebudiv register field. the ratio currently in use is provided in the ebu_clc . ebudivack register field. the purposes of the divider is to allow the memory controller core to operate synchronously at an integer divide ratio of the sri clock. by also setting the ebu_clc . div2 bitfield, the available divide ratios between the sri clock and the ebu_clk become 1:2, 1:4, 1:6 and 1:8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-18 v1.1, 2011-03 ebu, v1.9 figure 15-4 sri/memory co ntroller clock domains if a divide ratio of 1:3 is selected using the local clock divider and a memory device is being used at a 1:1 or 1:3 external clock ratio, then the device clock outputs, bfclko and sdclko, will not have a 50% duty cycle unl ess the dll is used to correct the duty cycle. this is because the local divider ope rates by pulse swallowing the module input clock to generate ebu_clk. for all clock ratios other than 1:3 the negative phase clock can be generated using a shifted pulse swallowing control signal but accurate positioning of the negative edge of a 1:3 clock is not possible. 1) 1) all clock duty cycle ratios are nominal and will be affected by pll jitter and pad rise/fall asymmetry ebua0015 - clocking block diagram memory interface core ebu_clk domain ebua 0015 flexray clock clock control ebu_clk data transaction sri data (64-bit) sri address (32-bit) sri bridge hclk domain sri clock clock divide www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-19 v1.1, 2011-03 ebu, v1.9 figure 15-5 example of bfclko generation using 1:3 case the figure above shows an example of external bus clock generation. ? firstly, the system clock is di vided to generat e the sri clock ? then the ebu local clock divider divides the sri clock to generate the ebu internal clock ? an ebu_clk signal is also generated from the sri clock by shifting the pulse swallowing control signal and inverting the signal if required ? for 1:1 division, there is no phase shift and the clock is inverted only ? for 1:2 division, the phase shift is one period of the sri clock and there is no inversion ? for 1:3 division, the phase shift is one period of the sri clock and the signal is inverted ? for 1:4 division, the phase shift is two periods of the sri clock and there is no inversion. ? for 1:6 division, the phase shift is three periods of the sri clock and there is no inversion. ? for 1:8 division, the phase shift is four periods of the sri clock and there is no inversion. ? the inverted clock signal is used to position the negative edge of the external bus clock in 1:1 ebu_clk:bfclko mode (busconx. extclock =00 b ) and also the edges of control signals shifted by one half of an ebu_clk period (see chapter 15.16.4 and chapter 15.17.8 ). 15.10.3 standby mode the memory controller can be configured to disable its internal clock and enter standby mode by writing a logic ?1? to the ebu_clc.disr register field. system_clk sri_clk ebu_clk ebu_clk bfclko www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-20 v1.1, 2011-03 ebu, v1.9 once the register field is written, the memory contro ller will wait for any running accesses to finish and will then disable t he clock to the core logic of the memory controller (ebu_clk). as this will also dis able the refresh counters, it is necessary to set the ebu_sdrmref.autoselfr register field if this mode is to be used with sdram. this will instruct the memctrl to place any attached sdram into self refresh mode before allowing clock mode switching or standby. exit from standby mode is triggered by writing 0 b to the ebu_clc.disr field an access arriving on any of the memory controller, sr i interfaces will trigger an automatic exit from standby mode to service the access request. this condition may also prevent standby mode being entered at all depending upon when the new access arrives at the sri interface note: once a pending sri access has triggered an exit from stand by mode, if all pending sri accesses have been serviced and the standby request is still active, the memory controller will not return to standby mode. an automatic exit from standby mode will not clear the ebu_clc.disr field. if automatic exit is used, then the ebu_clc.disr field will have to be cleared by an explicit write of 0 b before standby mode can be used again. 15.10.4 dll operation the dll is required for the following reasons: ? it is used to delay the dqs signals from the external ddr memory and enable read data to be successfully transferred between the ddr sdram and the memory controller. this is enabled by setting ebu_dllcon . rd_en to 1 b . ? it is used to delay the write data output from the memory controller to the ddr memory device and enable the correct relationship between the dq, dqm and dqs lines to be establised when the external bus clock is running at the same frequency as ebu_clk. (for signal timing with other clock ratios see ?generation of ddr control signals without using the dll? on page 15-24 ). this is enabled by setting ebu_dllcon . wr_en to 1 b . ? it is used to adjust the duty cycle of th e clocks to external memory to the optimum 50% when the ratio between internal and external clock is 1:1. this is enabled by setting ebu_dllcon . dcc_en to 1 b the calibrated delay value used by the slave delay lines will only be updated when it is safe to do so. ? the delays affecting write data (dq and dqm) will only be updated when a ddr write is not taking place ? the delays affecting the dqs inputs will only be updated when a ddr read is not taking place ? the delays used to compensa te the duty cycle will be cont inuously updated but using a clocking signal that is phase shifted so that glitches cannot occur on the output. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-21 v1.1, 2011-03 ebu, v1.9 15.10.4.1 locking the dll once enabled by setting ebu_dllcon . dll_dis to 0 b , the dll can be initialised by writing 1 b to ebu_dllcon . dll_rst . this will trigger the dl l to lock to the current ddr clock frequency. if the ebu_clk frequency is modified, then this field should be rewritten to lock the dll to the new frequency. a status bit is provided, ebu_dllcon . dll_lck . this will be set when the dll successfully locks to the current ebu_clk frequency. it will be cleared after reset and when either ?1 b is written to ebu_dllcon . dll_rst ? the dll loses lock with ebu_clk. once initial lock has been achieved, the dll will continually update its lock point. this behaviour will be inhibited when ebu_dllcon . dll_dis is set to logic one. the dll will only flag "loss of lock" by setting ebu_dllcon . dll_lck to 0 b if the input frequency is sufficiently low that the master delay line has too few delay line elements to enable a lock point to be achieved. in all other cases, the delay line will attempt to track the input frequency. if the input frequency is changed using the cgu control logic, signal positioning will be incorrect while the dela y line tries to relock. however the lock signal will remain set unless the new frequency is out of range. for this reason, it is recommended that frequency changes are always performed using the clock source control logic. see ?clocking modes? on page 15-16 . after reset, the dll w ill be disabled with ebu_dllcon . dll_dis set to logic ?1?. the dll has two possible locking algorithms selected by the ebu_dllcon . algo bit. when set to 0 b , the dll will use a fast locking algorithm to rapidly scan the delay setting using intervals of four delay cells from zero to just past the lock point. it will then adjust the delay back down incrementally until the lock point is reached. if ebu_dllcon . algo is set to 1, the dll will use a slow locking algorithm where the delay is scanned using increments of one delay cell until the lock point is passed. this mode has a lesser risk of spurious errors if the clock period is sufficiently small that the four delay cell increments of the fast locking mode are a significant proportion of the clock period. 15.10.4.2 dll operating modes the dll is only designed to lock at frequencies between 80 mhz and 180 mhz. at lower frequencies, the dll can be operated unlocked with a a static delay programmed by the ebu_dllcon . dll_value register field. in this mode, ?1? should be written to ebu_dllcon . dll_dis . this will prevent the dll from trying to lock. the dll value will th en remain at the value written to the ebu_dllcon . dll_value register field (permitted values 0 to 425). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-22 v1.1, 2011-03 ebu, v1.9 this preprogrammed value should therefore pr ovide sufficient margin between clock and delayed dqs edges for the interface to operate. note: each delay element should have a delay of between 35ps and 120ps depending on the operating conditions of the device. note: the master delay line can add 425 delay elements to the input clock and the logic is therefore designed to cope with a master delay line output of 0 to 425. writing a larger value than 425 d to ebu_dllcon . dll_value when ebu_dllcon . dll_dis is set will cause arithmetic overflows in the slave delay elements and cause the delayed signals to be disabled 15.10.4.3 dll related a ccess error conditions accesses to ddr memory will return an sri error if: ? ebu_dllcon . dll_lck is 0 b and ? ebu_dllcon . dll_dis is 0 b and ? ebu_dllcon . wr_en is 1 b or ebu_dllcon . rd_en is 1 b accesses to any external memo ry will return an error if: ? ebu_dllcon . dll_lck is 0 b and ? ebu_dllcon . dll_dis is 0 b and ? ebu_dllcon . dcc_en is 1 b 15.10.4.4 dq and dqm outputs ( ebu_dllcon . wr_en =1 b ) the dq and dqm output s will be delayed by 25% of a clock cycle. there will be two delay elements adjusting the clocks of the f lipflops driving the dq and dqm outputs (one for positive edge and one for negative edge). the optimum value can be adjusted manually by up to +3/64 and -4/64 of a cl ock cycle by writing th e appropria te signed value to the ebu_dllcon . wr_d_adj register field 1) . the delay lines will only be allowed to update when a write is not in progress. 15.10.4.5 dqs inputs ( ebu_dllcon . rd_en =1 b ) the dqs inputs will be individually delayed by 25% of a clock period (ebu_clk) before being used as the capture clock for the read data (one delay per byte lane). the optimum value can be adjusted manually by up to +3/ 64 and -4/64 of a clock cycle by writing the appropriate signed value to the ebu_dllcon . rd_dqs_adj register field1). the setpoint of the delay lines can only be updated when a read is not in progress. this is not a problem for ddr devices using the synchronous state machine where the device protocols enforce a gap on the databus bet ween ?back-to-back? reads but can be an 1) the field allows for a signed number with a value between -4 and +3.. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-23 v1.1, 2011-03 ebu, v1.9 issue for devices using the sdram state machine where reads can be aggressively pipelined. see chapter 15.19 and chapter 15.20 for more information on managing updates of the slave delay lines. 15.10.4.6 duty cycle correction the negative clock edge is used to clock the flipflops used to generate the negative edge of the external memory clocks w hen 1:1 clock ratio is selected. it also clocks the flipflops generating those control signals generated on the negative edge of the internal clock. if ebu_clk does not have a 50% duty cycle then the edges will deviate for the nominal position. the duty cycle correction delay is used to compensate for the duty cycle distortion caused by the pulse swallowing circuit used to locally divide the input clock to generate ebu_clk. a delay line with a nominal value of 50% of clock period is used to generate a clock edge at the same position in the cl ock cycle as the negative edge of a 50% duty cycle clock of the same period. if duty cycle correction is disabled by setting the ebu_dllcon . dcc_en register bit to 0 b , the negative edge flipflops are connected directly to an anti-phase version of the ebu_clk clock signal. see ?local clock divider? on page 15-17 for information on how this anti-phase clock is generated. note: this is intended to allow the correct gen eration of the external interface signals at lower frequencies of the memory contro ller input clock (outside the dll lock range) when the duty cycle is 50% and the lo cal clock division circuit is set to 1:1. 15.10.5 dll drift detector the dll contains a modified phase detector with an expanded detection window intended to detect when the drift rate of the locking point has exceeded the tracking limit of the dll. this circuit is enabled when the following conditions are true: ? the dll has achieved lock. ?1 b is written to the ebu_dllcon . win_en bitfield. once enabled the drift detector will monitor the phase of the dll input and output clocks. if the phase variation of the input and outpu t clocks exceeds the window of the detector, all accesses to ddr memory will be stalled by the ebu and the ebu_sdrstat . drift_warn bitfield will be set to 1 b . once the drift detector registers that the phase variation has decreased to within the window, the stalled accesses will be allowed to proceed. ebu_sdrstat . drift_warn will not clear until written with 0 b . the size of the window is set to be 6 delay elements. the principle of operation is that the error on the lockpoint should never exceed one delay element if the dll control logic can keep up with the current rate of drift. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-24 v1.1, 2011-03 ebu, v1.9 if this feature is to be relied on to prevent data corruption, it must be ensured that the operating frequency of the ddr interface is limited so that the worst case signal positioning error does not cause a timing violation. 15.10.6 generation of ddr control signals without using the dll the previous section covered the principles of using the dll to generate the correct signal timing for ddr signals when the internal to external clock ratio is 1:1. if the ratio of the internal to external clocks is not 1:1, then the internal clock is used to generate the necessary signal timing for outputs without the use of the dll. for this to work correctly, the shifting of write dq and dqm by the dll must be disabled ( ebu_dllcon . wr_en must be 0 b ) figure 15-6 write da ta update points 15.10.7 read data capture for ddr devices the ebu has two possible methods of capturing the data read from ddr devices: ebu_clk 1:2 1:4 external bus clock = lsw data update (captured on positive edge of external clock) = msw data update (captured on negative edge of external clock) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-25 v1.1, 2011-03 ebu, v1.9 15.10.7.1 read data fifo the read data fifo is clocked by the dqs signals generated by the ddr memory device. as the memory device will generate dqs edges aligned with data changes, the dqs signals have to be phase shifted using the delay lines to guarantee safe capture of the data. see ?dqs inputs (ebu_dllcon.rd_en=1b)? on page 15-22 for the method used to generate a fixed delay of 25% of an ebu_clk period (nominal). this method can be used at any setting of the ebu_clk to external clock ratio provided that 25% of an ebu_clk period provides sufficient setup time to successfully capture the data. if the dll is not locked, then a fixed delay value can be written into ebu_dllcon . dll_value . this will insert a fixed number of delay cells into the dqs input path ( dll_value /4). as there is no feedback mechanism in this mode to compensate for changes in operating conditions, the value of the delay inserted will vary as voltage and temperature of the device changes. this method treats the dqs inputs as asynchronous clocks and the data is resynchronised to ebu_clk. 15.10.7.2 fifo bypass mode at lower frequencies it is possible to capture the read data from ddr memories without using the data fifo to resynchronise it to the internal clock domain. this allows ddr memories to be accessed without requiring the dll. for this mode to work correctly, the following constraints must be met: ? the rising edge of the feedback clock must be guaranteed not to coincide with the rising edge of the internal clock. for the TC1798, this is possible up to a maximum external bus frequency frequency of 45 mhz. ? the external bus frequency must be sufficiently low to allow the dqs & dq to be generated from one clock edge and reach a stable state before the next clock edge. ? the first dqs/dq transition must be triggered by a rising clock edge ? once the first dqs/dq transition has occurred all clock edges must trigger a dqs/dq transition until the access completes. in this mode ddrclko will be used as the feedback clock and both edges of the feedback clock will be used to register dq (data) and dqs lines from the memory. a change in state of the dqs will cause the sampled data to be transferred into the read fifo. fifo bypass mode is enabled by writing 1 b to the ebu_modcon . fifo_bypass bitfield. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-26 v1.1, 2011-03 ebu, v1.9 figure 15-7 data read timing for accesses bypassing the fifo 15.10.8 external bus clock generation the memory controller can generate two external bus clocks. one of these is intended for use with sdram/ddram type devices controlled by the sdram state machine 1) and is output on ddrclko (and ddrclko if a differential clock is required). see ?sdram external bus clock generation? on page 15-117 1) see ?programmable device types? on page 15-54 for the device types supported by the ebu and the state machines used to control them feedback clock data dqs dqs (latched using +ve clock edge) dqs (latched using -ve clock edge) ls data (latched using -ve clock edge) ms data (latched using +ve clock edge) d0 d1 d0 d1 xx h xx h xx h xx h data to read buffer sdclko (before output pad) pending edge of sdclk ls data (resynched using +ve clock edge) d0 xx h xx h d1 & d0 xx h xx h data synched to internal clock gated with pending edge internal ebu clock www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-27 v1.1, 2011-03 ebu, v1.9 the other is intended for use with other synchronous memories such as burst flash and is output on bfclko (and ddrclko if a differential clock is required). see ?burst flash clock? on page 15-91 for devices without dqs outputs, clock feedback is used to correct for pad output and pcb track delays and each clock output therefore has an equivalent clock input. these are sdclki (ddrclko alternate function) and bfclki respectively. if a device does have dqs outputs, these are used to time read data capture (for the only exception see ?fifo bypass mode? on page 15-25 ). if a ddr memory is attached to the ebu, it will normally require a differential clock. for devices using the sdram control state machine this is ddrclk & ddrclk . for devices using the burst flash control state machine, the differential clock will be bfclko and ddrclk . the clocking mode will be determined by the agen fields of the configured memory regions. ? if any region is configured for lpddr nvm ( agen = 10 d ) or ddram ( agen = 12 d ), then the differential ddrclk will be output on ddrclk and ddrclk . ? if any region is configured for ddr burst flash ( agen = 9 d ) or onfi 2 ddr flash ( agen = 13 d ), the differential ddrclk will be output on bfclko and ddrclk . ? configuring both of the above conditions will force the ddrclk and bfclko outputs to use identical settings, in this case both regions must be configured with identical extclock and sdcmsel / bfcmsel settings. if this is not done, the the ebu contains logic which will try and configure sensible clock settings as follows: ? the frequency of the output clock will be set by the extclock setting of the highest priority region configured for ddr memory 1) . ? bfclko and sdclko will both output the positive phase of ddrclk ? if an enabled region configured as ddr burst flash has bfcmsel set to 0 b or an enabled region is configured for ddram or lpddr nvm with sdcmsel set to 0 b then the clock will run continuously at the frequency specified by the extclock setting of that region. ? clock feedback for both memory types (i f required) will be taken from the sdclki pin. ? setting the clk_comb bit in the ebu_modcon register will have an identical effect to configuring both types of ddr memory. this is not dependent on having any ddr memory configured. (e.g. this could be used to run sdram off the bfclko clock output.) note: all attached ddr memories use the same dqs signals and read/write datapaths. due to the practical difficulties of dyna mically switching the clock frequency of a ddr interface, this effectively forces all ddr devices attached to the ebu to be run at the same clock frequency. 1) region 0 has the highest priority and region 3 the lowest www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-28 v1.1, 2011-03 ebu, v1.9 15.11 external bus arbitration external bus arbitration is provided to allow the ebu to share its external bus with other master devices. this capability allows other external master devices to obtain ownership of the external bus, and to use the bus to a ccess external devices connected to this bus. the scheme provided by the ebu is compatible with other tricore and xc2xxx devices and therefore allows the use of such devices as (external bus) masters together with the TC1798. note: in this section, the term ?external ma ster? is used to denote a device which is located on the external bus and is capable of generating accesses across the external bus (i.e. is capable of driving t he external bus). an external master is not able to access units that are located inside the TC1798. 15.11.1 external bus modes the ebu can be in one of two bus states on the external bus: ? owner state ? hold state when in owner state, the ebu operates as the master of the external bus. in other words, the ebu drives the external bus as required in order to access devices located on the external bus. while the ebu is in owner state it is not possible for any other master to perform any accesses on the external bus. when the ebu is in owner state, ebu_modcon . busstate is set to 1 b . in hold state, the ebu tri-states the appropriate signal on the external bus in order to allow another external bus master to perform accesses on the external bus (i.e. to allow another master to drive the various external bus signals without contention with ebu). when the ebu is in hold state, ebu_modcon . busstate is set to 0 b . 15.11.2 arbitration signals and parameters the arbitration scheme consists of an external bus master that is responsible for controlling the allocation of the external bus. this master is referred to as the ?arbiter? within this document. the other external bus master (termed participant within this document) requests ownership of the bus, and when necessary, from the arbiter. the ebu can be programmed to operate either as an arbiter or as a participant (see page 15-30 ). the following three lines are used by the ebu to arbitrate the external bus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-29 v1.1, 2011-03 ebu, v1.9 two components that are equipped with the ebu arbitration protocol can be directly connected together (without additional external logic) as shown below: figure 15-8 connection of bus arbitration signals note: in the example of figure 15-8 , it is possible for the ebu to perform the function or either arbiter or participant (or indeed bo th the arbiter and participant may be the ebu). table 15-7 lists the programmable parameters for the external bus arbitration. table 15-6 ebu external bu s arbitration signals signal direction function hold in hold is asserted (low) by an external bus master when the external bus master requests to obtain ownership of the external bus from the ebu. hlda in/out 1) 1) the direction of this signal depends upon t he mode in which the ebu is operating (see page 15-30 ). hlda is asserted (low) by the arbiter to signal that the external bus is available for use by the participant (i.e. the bus is not being used by the arbiter). hlda is sampled by the participant to detect when it may use the external bus. breq out breq is asserted (low) by the ebu when the ebu requests to obtain ownership of the external bus. hold hlda breq arbiter user breq hlda hold mca05714 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-30 v1.1, 2011-03 ebu, v1.9 15.11.3 arbitration modes the arbitration mode of the ebu can be selected through configuration pins during reset or by programming the ebu_modcon.arbmode bit field (see page 15-30 ) after reset. four different modes are available: ? no bus mode ? sole master mode ? arbiter mode ? participant mode 15.11.3.1 no bus arbitration mode all accesses of the ebu to devices on the ex ternal bus are prohibited and will generate an sri bus error. the ebu is in hold state all the time. the hold and hlda arbitration inputs are ignored and breq arbitration output remains at high (inactive) level. no bus mode is selected by ebu_modcon.arbmode = 00 b . 15.11.3.2 sole master arbitration mode the ebu is the only master on the external bus; therefore no arbitration is necessary and the ebu has access to the external bus at any time. the ebu is in owner state all the time. the hold arbitration input is ignored, and the hlda and breq arbitration outputs remain at high (inactive) level. sole master mode is selected by ebu_modcon.arbmode = 11 b . 15.11.3.3 arbiter mode arbitration mode the ebu is the default owner of the external bus (e.g. applicable when operating from external memory). arbitration is performed if an external master (e.g. second tricore) needs to access the external bus. the ebu is cooperative in relinquishing ownership of the external bus while operating in arbiter mode. when the hold input is active, the ebu will generate delay any attempt to access the external bus from the internal sri. however, the ebu is aggressive in table 15-7 external bus arbitration programmable parameters parameter function description see ebu_modcon.arbmode arbit ration mode selection page 15-30 ebu_modcon.arbsync arbitration i nput signal sampling control ebu_modcon.extlock external bus ownership locking control ebu_modcon.timeoutc external bus time-out control www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-31 v1.1, 2011-03 ebu, v1.9 regaining ownership of the external bus while operating in arbiter mode. the ebu, having yielded ownership of the bus, will always request return of ownership even if there is no ebu external bus access pending. arbiter mode is selected by ebu_modcon.arbmode = 01 b . table 15-8 and figure 15-9 show the functionality of the arbitration signals in arbiter mode. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-32 v1.1, 2011-03 ebu, v1.9 figure 15-9 arbitration sequence with the ebu in arbiter mode in arbiter mode, the arbitration sequence starts with the ebu as owner of the external bus. table 15-8 function of arbitration pins in arbiter mode pin type pin function in arbiter mode hold in in owner state (ebu is the owner of the external bus), a low level at hold indicates a request for bus ownership from the external master. in hold state (ebu is not the owner of the external bus), a high level at hold indicates that the external master has relinquished bus ownership, which causes the ebu to exit hold state. hlda out while hlda is high, the ebu is operating in owner state. a high-to- low transition indicates that the ebu has entered hold state and that the external bus is available to the external master. while hlda is low, the ebu is operating in hold state. a low-to-high transition indicates that the ebu has exited hold state, and has retaken ownership of the external bus. breq out breq is high during normal operation. the ebu drives breq low two ebu clock cycles after entering hold state (after asserting hlda low). breq returns high one clock cycle a fter the ebu has exited hold state (after driving hlda high). hlda (ebu output) ebu on bus mct05715 hold (ebu input) 1) 4) 2) 5) 3) 6) 2 cycles min. breq (ebu output) external bus external master on bus ebu on bus 1 cycle min 1 cycle www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-33 v1.1, 2011-03 ebu, v1.9 1. the external master wants to perform an external bus access by asserting a low signal on the hold input. 2. when the ebu is able to release bus ownership, it enters hold state by tri-stating its bus interface lines and drives hlda = 0 to indicate that it has released the bus. at this point, the external master ia allowed to drive the bus. 3. two clock (ebu_clk) cycles minimum after issuing hlda low, the ebu drives breq low in order to regain bus ownership. this bus request is issued whether or not the ebu has a pending external bus access. however, the external master will ignore this signal until it has finished its bus access. this scheme assures that the external master can perform at leas t one complete external bus access. 4. when the external master has completed its access, it tri-states its bus interface and sets hold to inactive (high) level to signal that it has released the bus back to the ebu. 5. when the ebu detects that the bus has been released, it returns hlda to high level and returns to owner state by actively driving the bus interface lines. there is always at least one clock (ebu_clk) cycle del ay from the release of the hold input to the ebu driving the bus. 6. finally, the ebu deactivates the breq signal a minimum of one clock (ebu_clk) cycle after deactivation of hlda . now (and not earlier) the external master can generate a new hold request to the ebu. this sequence assures that the ebu can pe rform at least one complete bus cycle before it re-enters hold state as a result of a request from the external master. the conditions that cause change of bus ownership when the ebu is operating in arbiter mode are shown in figure 15-10 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-34 v1.1, 2011-03 ebu, v1.9 figure 15-10 bus ownership control in arbiter mode mca05716 ebu in owner state (i.e. owner of the external bus) the ebu holds ownership of the external bus: while extlock = 1 or until all current/queued external accesses are completed. when the external master requests the external bus (hold = 0) and conditions are appropriate the ebu releases ownership of the bus by hlda = 0. start access to external bus is starting? ebu_con. extlock = 1? hold = 0? ebu in hold state (i.e. not owner of the external bus) perform appropriate external bus access (for read access return result to lmb) yes no yes no no yes hold = 0? yes no the ebu remains in hold state until the bus is released by the external master (signalled by the external master setting hold = 1). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-35 v1.1, 2011-03 ebu, v1.9 15.11.3.4 ?participant mode? arbitration mode the ebu tries to gain bus ownership only in case of pending transfers (e.g. when operating from internal memory and performing stores to external memory). while the ebu is not the owner of the external bus (default state), any sri access to the external bus will be delayed by the ebu. any such access will cause the ebu to arbitrate for ownership of the external bus. once the access has been completed, the ebu will continue to accept requests from the sri bus until the external master asserts hold = 0. after the external master has asserted hold = 0, the ebu will respond by delaying subsequent sri accesses to external memory and will return ownership of the bus to the external master once any ongoing transaction is complete. the use of the arbitration signals in participant mode is: participant mode arbitration mode is selected by ebu_con.arbmode = 10 b . table 15-9 function of arbitration pins in participant mode pin type pin function in participant mode hold in when the ebu is not in hold state (hlda = 0) and has completely taken over control of the external bus, a low level at hold requests the ebu to return to hold state. hlda in when the hlda signal is high, the ebu is in hold state. when the ebu has requested ownership of the bus, the ebu is released from hold state by a high-to-low transition at hlda . breq out breq remains high as long as the ebu does not need to access the external bus. when the ebu detects that an external access is required, it sets breq = 0 and waits for signal hlda to become low. when the ebu has completed the external bus access (and has re- entered hold state), it will set breq = 1 to signal that it has relinquished ownership of the external bus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-36 v1.1, 2011-03 ebu, v1.9 figure 15-11 arbitration sequence with the ebu in participant mode in participant mode, the arbitration sequence starts with the ebu in hold state. 1. the ebu detects that it has to perform an external bus access by asserting a low signal on the breq output. 2. when the external master is able to release bus ownership, the external master releases the external bus by tri-stating its bus interface lines and drives the hlda =0. 3. at least one clock (ebu_c lk) cycle after detecting hlda = 0, the ebu will start to drive the external bus. 4. when the ebu is in owner state, the external master may optionally drive hold =0 to signal that it wants to regain ownership of the external bus. 5. when the criterias are met for the ebu to release the bus ownership, the ebu enters hold state and drives breq = 1 output high to signal that it has released the bus. 6. when the external master detects that the ebu has released the bus (breq =1), it returns hlda to high level and takes ownership of the external bus. 7. the ebu will not request ownership of the external bus again (breq = 0) at least one clock (ebu_clk) cycle after hlda has been driven high). 8. in owner state, the ebu will not request ownership of the external bus breq =0) for at least one clock (ebu_clk) cycle after its hold input has been driven high. the conditions that cause change of bus ownership when the ebu is operating in participant mode is shown in figure 15-10 . hlda (ebu input) ext. master on bus mct05717 breq (ebu output) 1) 5) 2) 6) 4) hold (ebu input) external bus ebu on bus ext. master on bus 1 cycle min 1 cycle min 7) 1 cycle min 8) 3) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-37 v1.1, 2011-03 ebu, v1.9 figure 15-12 bus ownership control with the ebu in participant mode ebu is in hold state the ebu remains in hold state until an access to the external bus is received. this access is stalled with wait states and the ebu starts an arbitration cycle to gain ownership of the bus. start ebu access to ext. bus is pending? hlda = 0? yes no ebu is in hold state yes no ebu is in owner state ebu access to ext. bus is underway? new ebu access to ext. bus is waiting? ebu_con. extlock = 1? ebu access to ext. bus is pending? yes no yes no yes no yes no the ebu remains in hold state until the bus is released by the arbiter (signalled by the hlda = 0). once the ebu has gained the external bus ownership it holds ownership: while extlock = 1 or until all queued external accesses are completed. or while an external bus access is pending (only until a time-out occurs). when the conditions are appropriate the ebu voluntarily surrenders external bus ownership to the arbiter (regardless of the state of the hold input). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-38 v1.1, 2011-03 ebu, v1.9 15.11.4 switching arbitration modes the arbitration logic will allow arbitrati on modes to be switch ed ?on-the-fly? and will switch between modes as described in the following sections. however it is recommended that the arbitration mode is set as soon as possible after power on and that it is then not modified. if this is not possible, then changes in arbi tration mode should use ?no bus? mode as an intermediate state with the arbiter in participant mode being placed in no bus mode first. once both arbiters are in no bus mode, then the new modes can be set. note: it should be remembered that the arbitration logic drives the hlda pin in arbiter or sole master modes and that having both se ts of logic in one of these modes should be avoided to prevent contention on the signal. 15.11.4.1 exiting no bus mode as arbitration is disabled in this mode, there will be no attempt to gain or release the bus when exiting the mode. a transfer to participant mode will occur immediately and the arbitration logic will directly enter the hold state. transfers to sole master or arbiter mode will occur immediately an d will result in the arbitration logic entering the owner state directly. if an attached sdram is conf igured for automat ic self refresh, th e sdram will be taken out of self refresh as part of the transition to owner state. 15.11.4.2 exiting sole master mode the arbitration logic will switch directly from sole master to arbiter mode remaining in the owner state. the arbitration logic will exit sole master mode and transfer to no bus or participant modes only when in the hold state. if the arbitration logic is in owner state when the request to change mode is made, then the arbitration logic will release the bus before entering the new mode. 15.11.4.3 exiting arbiter mode the arbitration logic will exit arbiter mode and transfer to so le master mode only when in the owner state. if the arbitration logic is in hold state when the request to change mode is made, then the arbitration logic will request the bus and wait until ownership is granted before switching mode. the arbitration logic will exit arbiter mode and transfer to no bus or participant modes only when in the hold state. if the arbitration logic is in owner state when the request to change mode is made, then the arbitration logic will release the bus before entering the new mode. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-39 v1.1, 2011-03 ebu, v1.9 note: if a transfer to participant mode result s in both arbiters being in participant mode then there is a high possibility of a system deadlock. any attempt to access external memory will result in the bus being requested. however, neither arbiter can drive hlda so the bus cannot be granted. the external memory access will therefore stall indefinitely, blocking any further attempt to write to the ebu_modcon register to change arbitration mode. 15.11.4.4 exiting participant mode the arbitration logic will exit participant mode and transfer to no bus mode only when in the hold state. if the arbitration logic is in owner state when the request to change mode is made, then the arbitration logic will release the bus before switching mode. the arbitration logic will exit participant mode and transfer to sole master or arbiter modes only when in the owner state. if the arbitration logic is in hold state when the request to change mode is made, then the ar bitration logic will request the bus and wait until ownership is granted before entering the new mode. note: as switching to sole master or arbiter mode requires ownership of the bus, it follows that the other arbite r in the system must be in arbiter mode to grant the bus. this will result in contention on the hlda signal when the mode change completes. 15.11.5 arbitration input signal sampling the sampling of the arbitration inputs can be programmed for two modes: ? synchronous arbitration ? asynchronous arbitration when synchronous arbitration signal sampling is selected (arbsync = 0), the arbitration input signals are sampled and evaluated in the same clock cycle. this mode provides the least overhead during arbitrati on (i.e. when changing bus ownership). the disadvantage is that the input signals must adhere to setup and hold times with respect to ebu_clk to prevent the propagation of meta-stable signals in the ebu. when asynchronous arbitrati on signal sampling is se lected (arbsync = 1), the arbitration signals are sampled and then fed to an additional register to be evaluated in the cycle following that in which they were sampled. this provid es the ebu with good immunity to signals changing state at or aroun d the time at which they are sampled. the disadvantage is the introduction of additional latency during arbitration (i.e. when changing bus ownership). 15.11.6 locking the external bus the external bus can be locked to allow the ebu to perform uninterrupted sequences of external bus accesses. the ebu allows two methods of locking the external bus: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-40 v1.1, 2011-03 ebu, v1.9 ? locked sri accesses (i.e read-modify-write) ? lock bit extlock when the ebu has ownership of the exter nal bus and is performing external bus accesses in response to a locked sri access sequence, the ownership of the external bus will not be relinquished until the locked sri access sequence has been completed. when lock bit extlock = 1, the ebu will hold the ownership of the external bus until extlock is subsequently cleared. if extlock is written to 1 while the ebu is the owner of the external bus, the ebu is immediately prevented from responding to requests for the external bus until extlock is cleared 1) . if extlock is written to 1 while the ebu is not the owne r of the external bus, the ebu will immediately attempt to gain ownership. when the ebu gains the ownership of the external bus the next time, the external master is prevented from rega ining ownership of the external bus until extlock is again cleared. note: there is no time-out mechanism available for the extlock bit. when the ebu is owner of the external bus with extlock bit set, the external master will remain locked off the bus until the extlock bit is cleared by software. 15.11.7 interaction with debug system the ebu monitors the ocds suspend signal used to freeze peripheral state when the system receives a break command. if the ebu detects a break it will request the external bus (if it is not the current owner). once th e ebu owns the bus, it will refuse any further arbitration requests until the suspend is rele ased. this allows the external memories to be read by the attached debugger. if this behaviour is not required, setting the ebu_modcon . ocds_susp_dis bitfield will cause ecternal bus arbitration to c ontinue to operate normally during a break. 15.11.8 arbitrating sdram control signals normally, the memory controller will not surrender control of a connected sdram type device 2) when arbitrating the external bus. this is because the memory controller needs to keep track of which pages are open in the sdram and also because of restrictions on the sdram clock. however, the memory controller can be programmed to tri-state the sdram control signals sdclko, cke, ras and cas by setting the ebu_modcon.sdtri bit to 1 b . when this bit is set, sdram can be shared with another controller provided certain conditions are met by both memory controllers. 1) requests for the external bus already pending when extlock is set will not be cancelled so the ebu can give up control of the external bus after extlock is set provided that the request occurs before the extlock bit is set. 2) sdram, ddram & lpddr-nvm devices www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-41 v1.1, 2011-03 ebu, v1.9 ? the sdram must be in self refresh mode with the clock safely stopped before ownership of the external bus is transfer red. this ensures that all pages in the sdram are closed and that the cke signal is at logic zero. this can be achieved for the memory controller by setting the sdrmref.autoselfr to 1 b . ? the sdram cke input must have a pull down sufficient to ensure that there is a guaranteed logic zero on the input while bus ownership is being transferred. 15.12 start-up/boot process during reset, the ebu will be in ?nobus? mode and all pins will be controlled by the port i/o logic. after reset is removed, the ebu will check to see if external boot has been requested. if external boot is required, then the ebu will set the busconx.portw and busrconx.agen fields to the appropriate values and enable the necessary pins for use by the ebu. if external boot is not requested then the ebu will remain in ?nobus? mode until configured by software. 15.12.1 disabled (arbitration mode is ?nobus?) the ebu will come up with access to the external bus disabled after reset (i.e. no access from sri to external memory is possible without ebu re-configuration). 15.12.2 external boot mode the external boot mode of the ebu allows the ebu to boot (i.e. run all start-up code) from external memory. imme diately after reset a system may have no knowledge as to the type of memory connected to the exter nal bus. when external boot mode is selected, the ebu will exit reset with the registers configures to allow slow (safe) accesses to both mexed and non-muxed asynchronous memories. when external boot mode is selected, the ebu will be configured to automatically read a 32-bit boot configuration value from an external memory (connected to cs0 , chip select region 0). the boot configuration value in the external boot memory makes it possible to initialize the ebu with more appropriate configuration values for the external boot memory. these configuration values will, in turn, be used for the subsequent read accesses from the external boot memory (i.e. instruction fetches). the boot configuration fetch can be triggered using two methods: ? setting the syscon.setextben bit and then resetting the ebu. in this case all accesses to the ebu will be held while the configuration fetch is in progress ?writing 1 b to the ebu_extboot.ebucfg bit before the end of system boot 1) . in this case the ebu_extboot.cfgend bit should be polled to determine when the fetch has ended and the registers updated. 1) this is determined by the state of the boot_active flag generated by the scu. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-42 v1.1, 2011-03 ebu, v1.9 in both cases the ebu_extboot.cfgerr bit will be set if the configuration word fetch fails to retrieve valid data. see ?configuration word fetch process? on page 15-42 for a full description of the configuration process. note: external boot cannot be used if an sdram/ddram or lpddr_nvm is connected. this is because these devices do not have an external reset input and will therefore be in an indeterminate state after a reset of the ebu. this state could cause the memory device to drive the databus and, as th e ddrclko output is disabled after reset, the memory device will remain in this state during the external boot process and interfere with th e reads from the boot memory. 15.12.2.1 configuration word fetch process if an external boot configuration fetch is e nabled, the ebu will perform one external bus read access to external bus address 000004 h of the memory device attached to chip select line cs0 . as it is assumed by the that the attached memory device has a 32 bit data bus, this is equivalent to a sri or byte address of 000010 h because of the address translation implemented in the ebu (see chapter 15.13.4 on page 15-52 ). the data read by this read access is used to configure the ebu with parameters (see page 15-44 ). the boot read access itself is perf ormed as an asynchronous access cycle with all timing parameters set to their maximum values. this access scheme supports roms, eproms or flash memories with bot h separate address and data connections and also multiplexed address and data connections. figure 15-13 shows a timing example of booting from a standard demultiplexed asynchronous memory device. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-43 v1.1, 2011-03 ebu, v1.9 figure 15-13 boot read access cycle when a configuration fetch is triggered, the ebu waits 256 ebu_clk clock cycles until the access is initiated, as shown in figure 15-13 . this gap is inserted to fulfill the recovery times needed by external synchronous devices such as flash roms. during the read access, the maximum number of programmable ebu_clk cycles is inserted (waitrdc = 31), and the evaluation of the wait signal is inhibited. note: the boot memory must be connected to chip select line cs0 . the ebu assumes that the boot memory is 32-bits wide and, therefore, always reads a 32-bit configuration word at the ?data in? point shown above. note: if ffff h is returned as on bits 15 downto 0 of the configuration word during the boot read cycle (e.g. by readi ng the configuration word from an erased external boot memory device), the arbitration mode is set to no bus mode (arbmode = 00 b , see ?no bus arbitration mode? on page 15-30 ). however since a value for the bcgen field of 11 b is not legal for boot, at least one bit of the fetched word will be 0 b for valid data data in ebu_clk a[23:0] 000004 h mct05720 ap0-14 ah0-14 cd0 cd14 cp0 cs0 rd d[31:0] cp30 address phase (15 ebu_clk cycles) command delay phase (15 ebu_clk cycles) bc[3:0] command phase (31 ebu_clk cycles ) write data to buscon register x sample 0004 h address hold phase (15 ebu_clk cycles) adv www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-44 v1.1, 2011-03 ebu, v1.9 15.12.2.2 boot configuration value the ebu supports boot operation from 32-bit wide memories. the format of the boot configuration value is as follows (bits 31 to 16 are reserved for future expansion): boot configuration value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res 1514131211109876543210 bcgen wait wai tinv addrc waitrdc portw field bits description portw 1:0 port width 00 b external memory is 8 bit 01 b external memory is 16 bit 10 b external memory is two 16 bit memories in parallel to make a 32 bit memory 11 b external memory is 32 bit waitrdc [6:2] number of wait states for read accesses loaded into ebu_busrap0.waitrdc. addrc [10:7] number of cycles in the address phase loaded into ebu_busrap0.addrc. waitinv 11 wait input polarity control loaded into ebu_busrcon0.waitinv. wait [13:12] external wait state control loaded into ebu_busrcon0.wait. bcgen [15:14] byte control signal control loaded into ebu_busrcon0.bcgen. res [31:16] reserved this bit field is reserved for future use. in the TC1798, res should always be set to 0 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-45 v1.1, 2011-03 ebu, v1.9 15.13 accessing the external bus each internal sri master can access external devices via the ebu. the ebu provides four user-programmable external memory r egions. each of these regions is provided with a set of registers that determine the pa rameters of the external bus transaction and one chip select signal. an sri transaction that matches one of these user-programmable external memory regions is translated by the ebu to the appropriate external access(es). in the TC1798, the ebu responds to the address ranges as defined in table 15-10 . the ?compare? action means that the ebu compares the supplied sri address to all its external regions. if a match is found, the ebu performs the appropriate external bus access. otherwise, the ebu generates an sri error acknowledge. the ?access registers? action means that the ebu is selected for a control/status register access. the ebu performs the requested register access (or generates an sri error acknowledge if there is no regi ster at the supplied address). for all address ranges that not listed in table 15-10 the ebu is not selected and sri requests are ignored. 15.13.1 external memory regions each of the external memory regions has its own associated chip select output cs[3:0] and a set of control registers to specify the type of memory/peripheral device and the access parameters. the access parameters for each of the regi ons can be programmed individually to accommodate different types of external devices. separate control registers are available to control read and write accesses. this allows optimal access types, speeds and parameters to be chosen. access type is configured via busrconx and buswconx. access parameters are co nfigured via busrapx and buwapx. throughout this document the generic term ebu_busconx is used when either of busrconx or buswconx is applicable and ebu_busapx is used when either of busrapx or buswapx is applicable. table 15-10 ebu external address ranges address range description action 8300 0000 h - 8eff ffff h external memory space (cached area) compare a300 0000 h - aeff ffff h external memory space (non-cached area) f800 0000 h - f800 03ff h ebu registers access registers www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-46 v1.1, 2011-03 ebu, v1.9 table 15-12 lists the programmable parameters that are available for the four external regions (regions 0 to 3) independent of the attached memory device. table 15-11 ebu address regions, registers and chip selects region associated chip select address select registers bus configuration registers bus access parameters registers region 0 cs0 ebu_addrsel0 ebu_busrcon0 ebu_buswcon0 ebu_busrap0 ebu_buswap0 region 1 cs1 ebu_addrsel1 ebu_busrcon1 ebu_buswcon1 ebu_busrap1 ebu_buswap1 region 2 cs2 ebu_addrsel2 ebu_busrcon2 ebu_buswcon2 ebu_busrap2 ebu_buswap2 region 3 cs3 ebu_addrsel3 ebu_busrcon3 eub_buswcon3 ebu_busrap3 ebu_buswap3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-47 v1.1, 2011-03 ebu, v1.9 table 15-12 programmable parameters of regions register parameter (bit/bit field) function ebu_addrselx altseg alternate segment of region to be compared to sri address bits [31:28]. base region base address to be compared with sri address in conjunction with the mask parameter. mask address mask for each external region. specifies the number of right-most bits in the base address starting from bit 26. wprot write protect bit for each region. altenab alternate segment enable of a region. determines whether or not parameter altseg is always compared to sri address. regenab enable bit for each region. a disabled region will always generate a miss during address comparison. ebu_busconx agen region access type: see section 15.14.1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-48 v1.1, 2011-03 ebu, v1.9 15.13.2 address comparison address comparison is implemented in addition to the address decoding in the sri bus matrix and is used to map sri addresses to the ebu regions. the address comparison operation will, by default, take two clock cycl es. if the frequency of the sri bus is set to be less than or equal to 180 mhz, then the sri interface of the ebu can be set to use single cycle decode. this is controlled by the ebu_modcon . fast_sri bitfield. when set to 1 b , the sri interface will use a single cycle for address decode. note: as the fast_sri bit modifies the sri interface behaviour dynamically, some care is needed when changing the mode of opera tion. when setting or clearing the bit, time should be allowed after writing the register for the setting to take effect before attempting a read from the ebu. to ensure the new setting has taken effect, it is suggested that the ebu_mod con register is written twice with the new setting. this is because internal architecture cons traints mean that the data from the first write must have been transferred to t he register before the second write can proceed. 15.13.2.1 operation address comparison each of the four ebu regions can be programmed for independent base addresses and lengths by bits and bit fields in registers ebu_addrselx. ? bit regen is the enable control of a region. if the region is disabled (regen = 0), no address comparison will take place for the region. ? bit field base specifies addre ss bits a[31:12] of region x, where a[31:28] must only point to segments 8, 10, 13, and 14 (see table 15-13 on page 15-50 ). 1) ? bit field mask determines the length of a region. it specifies how many bits of ansri sri address must match the co ntents of the base(x) bit field (to a maximum of 15, starting with a[26]). note that address bits a[31:27] must always match. ? bit wprot write protects a region. if the region is protected (wprot = 1), no address comparison will take place for that region on a write access 2) ? bit field altseg determines the number of an alternate segment that can be used for address comparison with a[31:28] (if enabled by altenab = 1). ? bit altenab determines whether an additional alternate segment number as defined by altseg is used for address comparison. 1) there is no hardware lockout preven ting other values being written to a[ 31:28], but in most cases this will result in an inaccessible memory. enabling a memory region at segment f8 h will result in the memory region conflicting with the registers. the ebu will not work correctly if this is done. 2) the wprot bit also appiles to the read phase of a read modify write, sri transaction. this is to prevent two possible error conditions. the first would be wher e the read phase was accepted and the write phase errored. this is an sri protocol violation. the second would be where the read and write accesses occurred to different memory addresses (if the read took place to a write protected region and there was an unprotected, lower priority, region mapped to the same address space). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-49 v1.1, 2011-03 ebu, v1.9 the address comparison scheme is shown in figure 15-14 . figure 15-14 address comparison to detect access to external region when the ebu is processing an sri access, the address is compared in parallel to the parameters of all four regions. the address comparison process for one region is shown in figure 15-14 . this process is as follows: 1. the most significant four bits of the sr i address are compared with the altseg bit field (?alternate? segment address). the re sult of the comparison (1 if equal, otherwise 0) is fed to an and gate. 2. if altenab = 0, the alternate segment function is disabled and the output of the and gate is 0. with altenab = 1, the al ternate segment function is enabled, and the result of the comparison between altseg and the segment part of the sri address is fed to an or gate. mca05722 31 sri address 28 27 26 12 11 0 equal ? & 15 15 expansion & & equal ? 4 31 ebu_addrselx register 28 27 26 12 10 4 7 base mask region selected altseg 8 11 equal ? altenab & equal ? 1 2 3 4 regenab 5 17 16 15 14 0 6 sri write ? & 7 10 1 wrprot 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-50 v1.1, 2011-03 ebu, v1.9 3. the most significant four bits of the sri address (?main? segment address) are compared to the most significant four bits of the base bit field. the result of the comparison (1 if equal, otherwise 0) is fed to the or gate. 4. the or gate combines the result of the ?main? and ?alternate? segment comparisons generates a 1 if the sri address is in the selected segment(s) for the region, otherwise it generates 0. the output of the or gate is fed to the final and gate. 5. bit 27 of the sri address is (unconditionally) compared with bit 15 of the base bit field. the result of the comparison (1 if equal, otherwise 0) is fed to the final and gate. 6. the appropriate number of sri address bits from bit 26 downwards is compared with the corresponding bits from bit field base bi t 14 downwards. the number of bits used for the comparison is controll ed by the mask bit field. th e result of the comparison (1 if the appropriate bits are equal, ot herwise 0) is fed to the final and gate. 7. the nand gate delivers a 0 if a writ e is performed to a read-only region (wrprot=1), and prevents the region from being selected. the output of the nand gate is fed to the final and gate. 8. the final and gate delivers a 1 if a match occurs at the address comparison, and the region x is enabled by regenab = 1, and the access is not a write access when the region is defined as read-only access. this address decoding scheme has the following effects: ? the smallest possible address region is 2 12 bytes (4 kbyte) ? the largest possible address region is 2 27 bytes (128 mbyte) ? the start address of a region depends on the size of the region. it must be at an address that is a multiple of the size of a region; for example, the smallest region can be placed on any 4-kbyte boundary, while the largest region can be placed on 8-mbyte boundaries only. table 15-13 shows the possible region sizes and st art granularity, as determined by the programming of the mask bit field. the range of the offset address within such a region is also given. table 15-13 ebu address regions size and start address relations mask no. of address bits compared to base[26:12] range of address bits compared to base[26:12] region size and start address granularity range of offset address bits within region 1111 b 15 a[26:12] 4 kbyte a[11:0] 1110 b 14 a[26:13] 8 kbyte a[12:0] 1101 b 13 a[26:14] 16 kbyte a[13:0] 1100 b 12 a[26:15] 32 kbyte a[14:0] 1011 b 11 a[26:16] 64 kbyte a[15:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-51 v1.1, 2011-03 ebu, v1.9 the ebu uses the four region select outputs from the above scheme, in conjunction with its own address decode logic, to react to sri accesses as follows: 1. address is in the ebu register space: an ebu register access is executed, and in case of a illegal register address, sri error acknowledge is returned. 2. address matches exactly one enabled external region: the requested access is performed to external memory. 3. address matches more than one enabled region (overlapping regions): the requested access is performed using the parameters from the region with highest priority. region 0 has the highest priority and region 3 the lowest priority. 4. address matches disabled region(s) or no address match: the ebu returns an sri error acknowledge. when defining mirrored segments, the user is responsible for ensuring that there is no collision. there is no checking mechanism in hardware that ensures that each segment defined (either in base[31:28] or altseg[11:8] or both) is exclusive. therefore, the user must ensure that each mapping from regi on 0 to 3 does not interfere with any other; otherwise, only the mapping with the highest priority will take effect. 15.13.3 sri bus width translation if the sri access size is wider than the external bus width specified for the selected external region, the internal a ccess is split in the ebu into several external accesses. for example, if the sri requests to read a 64-bit word and the external device is only 16-bit 1010 b 10 a[26:17] 128 kbyte a[16:0] 1001 b 9 a[26:18] 256 kbyte a[17:0] 1000 b 8 a[26:19] 512 kbyte a[18:0] 0111 b 7 a[26:20] 1 mbyte a[19:0] 0110 b 6 a[26:21] 2 mbyte a[20:0] 0101 b 5 a[26:22] 4 mbyte a[21:0] 0100 b 4 a[26:23] 8 mbyte a[22:0] 0011 b 3 a[26:24] 16 mbyte a[23:0] 0010 b 2 a[26:25] 32 mbyte a[24:0] 0001 b 1 a[26] 64 mbyte a[25:0] 0000 b 0 ? 128 mbyte a[26:0] table 15-13 ebu address regions size and start address relations (cont?d) mask no. of address bits compared to base[26:12] range of address bits compared to base[26:12] region size and start address granularity range of offset address bits within region www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-52 v1.1, 2011-03 ebu, v1.9 wide, the ebu will automatically perform four external 16-bit accesses. when multiple accesses are generated in this way, external bus arbitration is blocked until the multiple access is complete. this means that the ebu remains the owner of the external bus for the duration of the access sequence. the external accesses are performed in ascending sri address order. 15.13.4 address alignment during bus accesses during an external bus access, the ebu will align the internal byte address to generate the appropriate external word or half-word add ress aligned to the external address pins. the address alignment will be done as follows: ? for 8 bit memory accesses ? ad[15:0] will be driven with the value from a sri [15:0] (mutiplexed accesses only) ? a[27:0] will be driven with the value from a sri [27:0] ? for 16 bit memory accesses ? ad[15:0] will be driven with the value from a sri [16:1] (mutiplexed accesses only) ? a[27:0] will be driven with the value from a sri [28:1] ? for 32 bit memory accesses ? ad[15:0] and ad[31:16] will both be driven with the value from a sri [17:2] (accesses to paired 16-bit multiplexed devices only) ? ad[31:0] will be driven with the right-justified and zero-padded value from a sri [31:2] (accesses to pa ired 32-bit multiplexed devices only) ? a[27:0] will be driven with the value from a sri [28:2] 15.13.5 sri data buffering the data for all sri writes are ?posted? into a buffer in the sri interface before the access is passed to the state ma chine blocks for execution. th is means that all the write data is available to the state machine before the access starts independent of the relative clock frequencies of the internal and external buses and that the write completes at the initiating master before the data is written to the external memory. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-53 v1.1, 2011-03 ebu, v1.9 15.13.6 chip select control the ebu generates four chip select signals, csx , which are all available at dedicated chip select outputs. ea ch chip select is associated exclusively with an ebu region. see ?external memory regions? on page 15-45 for a complete description.... 15.13.7 combined chip select (cscomb ) the ebu can also generate a combined, global chip select. this is controlled using the ebu_addrselx.globalcs register fields. if this is set to 1 b in a register, then the cscomb chip select is asserted whenever t he associated normal chip select is asserted. multiple globalcs fields can be set simultaneously. 15.14 connecting external memories the ebu supports interconnection to a wide variety of memory/peripheral devices with flexible programming of the access parameters. in the following sections, the basic features for these access mo des are described. the types of external access cycles provided by the ebu are: ? asynchronous accesses with multiplexed or demultiplexed address and data bus ? roms, eproms ? nor flash devices ? nand flash devices ? static rams and psrams ? synchronous accesses with multiplexed or demultiplexed address and data bus ? nor flash devices (operating in burst mode) ? ddr flash devices ? psrams ? page mode flash 1) ? accesses using sdram type command protocol ? mobile sdram ? mobile ddram ? lpddr-nvm note: not all memory types supported by the memory controller are known to be available in all quality grades and temperature ranges. each type of access is controlled by a state machine in the ebu kernel. see table 15-14 for a list of the access types supported and the controlling state machine. sdram type accesses comply with the relevant protocol and have limited programmability. asynchronous and synchro nous accesses use the concept of access 1) page mode flash devices are not synchronous but have in common with synchronous devices the ability to return multiple data words for each supplied address. they are therefore handled by the synchronous state machine of the ebu www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-54 v1.1, 2011-03 ebu, v1.9 phases of programmable duration an d are more fully described in ?phases for asynchronous and synchronous accesses? on page 15-62 15.14.1 programmable device types each cs region (0 to 3) can be individually configured using the busconx.agen register field, to be connected to one of the following external memory/device types: the agen fields for the busrconx and buswconx can, in most cases, be set independently. this allows devices such as burst flash, which require synchronous reads and asynchronous writes to be supported efficiently. there are device types where this capability does not confer any advantage. in these cases, writing to the busrconx.agen fi eld will also update the buswconx.agen field. the agen values which trigger the automatic buswconx.agen update are: ? sdram: 8 d ? lpddr nvm: 10 d table 15-14 agen description agen value device type state machine 0 muxed asynchronous type (default after reset) asynchronous 1 muxed burst type synchronous 2 nand flash (page optimised) asynchronous 3 muxed cellular ram synchronous 4 demuxed asynchronous type asynchronous 5 demuxed burst type synchronous 6 demuxed page mode synchronous 7 demuxed cellular ram synchronous 8 sdram sdram 9 ddr burst flash (spansion protocol) synchronous 10 lpddr nvm (jedec 42.4 ddr non-volatile memory) sdram 11 reserved - 12 ddram sdram 13 onfi 2.0 nand flash synchronous 14 reserved - 15 reserved - www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-55 v1.1, 2011-03 ebu, v1.9 ? ddram: 12 d while the busrconx.agen field is set to one of these values, any attempt to set the value of the related buswconx.agen field will be ignored. 15.14.2 support for multiplexed device configurations memory controller supports a number of configurations of multiplexed memory/peripheral devices using different values of the ebu_busrconx.portw bit- field. the ebu_buswconx registers also contain the portw field but in this case the field is read only and reflects the val ue set in the related one of the ebu_busrconx registers. the values set in the ebu_busrco nx registers are used for both read and write accesses. note: when using multiplexed devices a non-zero recovery phase is mandatory for all devices to prevent read data from one access conflicting with the address for the next access to the multiplexed memory. table 15-15 pins used to connect multiplexed devices to memory controller memory device configuration memory controller pins section a(27:0) 1) 1) these pins are always outputs which are connect ed to address pins on the multiplexed device(s) ad(31:16) ad(15:0) 8-bit mux a(27:0) - a(7:0)/ d(7:0) 8-bit multiplexed memory/peripheral configuration 16-bit mux a(27:0) - a(15:0)/ d(15:0) 16-bit multiplexed memory/peripheral configuration twin 16-bit mux a(27:0) a(15:0)/ d(31:16) a(15:0)/ d(15:0) twin 16-bit multiplexed device configuration 32-bit mux - a(31:16)/ d(31:16) a(15:0)/ d(15:0) 32-bit multiplexed memory/peripheral configuration table 15-16 selection of multiplexed device configuration portw value 00 b 8-bit multiplexed (deprecated) 1) 01 b 16-bit multiplexed 2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-56 v1.1, 2011-03 ebu, v1.9 15.14.2.1 twin 16-bit multip lexed device configuration this mode allows the use of two 16-bit multiplexed devices to create a 32-bit wide bus. throughout the complete ex ternal bus cycle the address 1) is driven onto memory controller pins a(27:0). during the addres s phase the low 16 bits of the address are driven (in parallel) to memory controller pins ad(15:0) and ad(31:16). this ensures that both multiplexed devices are issued with the same address during the address phase. data (32-bit) is written to/read from the ad(31:16) pins for msw and the ad(15:0) pins for lsw during the data phase. the interconnect between memory controller and two 16-bit multiplexed devices in this mode is shown below (note: for clarity only the address/data signals are shown):- 10 b twin, 16-bit multiplexed 3) 11 b 32 bit multiplexed 4) 1) 8-bit port width is only intended for nand flash and on fi devices which do not require particular values on the address bus. correct operation of multiplexed addressing is not verified or guaranteed. 2) address will only be driven onto ad(15:0) during the add ress and address hold phases. a(15:0) will be driven with address for duration of access 3) lower 16 bits of address will be driven onto both a(15:0) and ad(15:0) during the address and address hold phases 4) full address will be driven onto a(15:0) and ad(15:0) during the address and address hold phases 1) this address is pre-aligned according to the bus width as detailed in section 15.13.4 . table 15-16 selection of multiplexed device configuration (cont?d) portw value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-57 v1.1, 2011-03 ebu, v1.9 figure 15-15 connection of twin 16-bit mu ltiplexed device?s to memory controller 15.14.2.2 16-bit multiplexed me mory/peripheral configuration throughout the complete ex ternal bus cycle the address 1) is driven onto memory controller pins a(27:0). during the addres s phase the low 16 bits of the address are driven to memory controller pins ad(15:0). da ta (16-bit) is driven to/read back from the ad(15:0) pins during the data phase. the in terconnect between memory controller and a 16-bit multiplexed device in this mode is shown below (note: for clarity only the address/data signals are shown):- 1) this address is pre-aligned according to the bus width as detailed in section 15.13.4 . memory controller a(max:16) ad(31:16) ad(15:0) memory/peripheral a(max:16) ad(15:0) memory/peripheral a(max:16) ad(15:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-58 v1.1, 2011-03 ebu, v1.9 figure 15-16 connection of a 16-bit multiplexed device to memory controller 15.14.2.3 8-bit multiplexed me mory/peripheral configuration the ebu drives signals for 8 bit devices in an identical manner to 16 bit devices. ad(15:0) are driven for address and write data and bc(1:0) are enabled. however valid write data only appears on ad(7:0) and bc(1) is always inactive. read data is only sampled from ad(7:0). 15.14.2.4 32-bit multiplexed me mory/peripheral configuration during the address phase the lower 16 bits of the 25 bit address are driven to memory controller pins ad(15:0), the most significant 9 bits of the address are driven to pins ad(24:16) and pins ad(31:17) are driven with 0 (zero). data (32-bi t) is driven to/read from the ad(31:0) pins during the dat a phase. the interconnect between memory controller and a 32-bit multiplexed device in this mode is shown below (note: for clarity only the address/data signals are shown):- memory/peripheral a(max:16) ad(15:0) memory controller a(max:16) ad(15:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-59 v1.1, 2011-03 ebu, v1.9 figure 15-17 connection of a 32-bit multiplexed device to memory controller 15.14.3 support for non-multiplexed device configurations the memory controller supports 16-bit and 32-bit non-multiplexed memory devices. table 15-17 pins used to connect non-multiplexed devices to memory controller memory device configuration memory controller pins section a(27:0) ad(31:16) ad(15:0) 8-bit non-mux a(27:0) - d(7:0) 8-bit non-multiplexed memory/peripheral configuration 16-bit non-mux a(27:0) - d(15:0) 16-bit non-multiplexed memory/peripheral configuration twin, 16-bit non- mux a(27:0) d(31:16) d(15:0) 32-bit non-multiplexed memory/peripheral configuration 32-bit non-mux a(27:0) d(31:16) d(15:0) 32-bit non-multiplexed memory/peripheral configuration memory/peripheral ad(31:0) memory controller a(max:16) ad(31:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-60 v1.1, 2011-03 ebu, v1.9 15.14.3.1 16-bit non-multiplexed memory/peripheral configuration throughout the complete ex ternal bus cycle the address 1) is driven onto memory controller pins a(27:0). data (16-bit) is driven to/read back from the ad(15:0) pins during the data phase. the interconnect between memory controller and a 16-bit non- multiplexed device in this mode is shown below (note: for clarity only the address/data signals are shown):- figure 15-18 connection of a 16-bit non-multiplexed device to memory controller 15.14.3.2 8-bit non-multiplexed memory/peripheral configuration the ebu drives signals for 8 bit devices in an identical manner to 16 bit devices. ad(15:0) are driven for address and write data and bc(1:0) are enabled. however valid table 15-18 selection of non-multiplexed device configuration portw value 00 b 8-bit 1) 1) 8-bit port width is only intended for nand flash and onfi devices which do not require particular values on the address bus. correct operation of addressing for other device types is not verified or guaranteed 01 b 16-bit 10 b twin 16-bit 11 b 32-bit 1) this address is pre-aligned according to the bus width as detailed in section 15.13.4 . memory/peripheral a(max:0) d(15:0) memory controller a(max:0) ad(15:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-61 v1.1, 2011-03 ebu, v1.9 write data only appears on ad(7:0) and bc(1) is always inactive. read data is only sampled from ad(7:0). 15.14.3.3 32-bit non-multiplexed memory/peripheral configuration throughout the complete ex ternal bus cycle the address 1) is driven onto memory controller pins a(27:0). data (32-bit) is driven to/read back from the ad(31:0) pins during the data phase. the interconnect between memory controller and a 16-bit non- multiplexed device in this mode is shown below (note: for clarity only the address/data signals are shown):- figure 15-19 connection of a 32-bit non-multiplexed device to memory controller 15.14.3.4 twin, 16-bit non-multiple xed memory/peripheral configuration throughout the complete ex ternal bus cycle the address 2) is driven onto memory controller pins a(27:0). data (32-bit) is driven to/read back from the ad(31:0) pins during the data phase. the interconnect between memory controller and two, 16-bit non- multiplexed devices in this mode is shown below (note: for clarity only the address/data signals are shown):- 1) this address is pre-aligned according to the bus width as detailed in section 15.13.4 . 2) this address is pre-aligned according to the bus width as detailed in section 15.13.4 . memory/peripheral a(max:0) d(31:0) memory controller a(max:0) ad(31:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-62 v1.1, 2011-03 ebu, v1.9 figure 15-20 connection of two 16-bit non-multiplexed devices to the memory controller this mode primarily affects the mode register and status register operations for sdram, ddram and lpddr-nvm devices. if the region is configured as twin, 16-bit, then the mode register data will be replicated on both halves of the 32 bit data bus to ensure that both the connected devices are written with an identical configuration. 15.15 phases for asynchronous and synchronous accesses accesses to asynchronous and synchronous devices are composed of a number of standard access phases (according to the type of device and the type of access). each output signal for the ebu is active in defi ned phases. the length of the phases can be programmed to adjust the pulse width and timing relationships of the output signals there are six access phases defined: memory/peripheral a(max:0) d(15:0) memory controller a(max:0) ad(15:0) ad(31:16) memory/peripheral a(max:0) d(15:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-63 v1.1, 2011-03 ebu, v1.9 ? address phase ap (mandatory for read and write cycles of both device types) ? command delay phase cd (optional) ? command phase cp (mandatory) ? burst phase bp (synchronous accesses only) ? control hold ch (optional, synchronous accesses to ddr nor flash only) ? data hold phase dh (optional, only applies to write cycles) ? recovery phase rp (optional) throughout the remainder of this document, a short-hand notation is adopted to represent any clock cycle in any phase. this notation consists of two or three letters followed by a number. the letters identify the access phase within which the clock cycle is located (e.g. ap for address phase). the number denotes the number of ebu_clk clock cycles within the phase (i.e. 1 = first, etc.). in the case of delays that can be extended by external control inputs the lower case letters ?e? and ?i? are inserted following the two letter phase identifier to differentiate between internally (?i?) and externally (?e?) generated delays. for example, ap2 identifies the second clock in the address phase. cpe3 identifies the third clock in the command phase which is being extended by external wait-states. 15.15.1 address phase (ap) the address phase is mandatory. it always consists of at least one or more ebu_clk cycles. the phase can be optionally extended to accommodate slower devices. at the start of the address phase, the ebu: ? selects the device to be accessed by asserting the appropriate csx signal, ? issues the address which is to be accessed on the address bus, ? for multiplexed devices, drives the address onto the muliplexed address/data bus, ? asserts the adv signal low, 1) ? asserts the appropriate bcx signals if these are programmed to be asserted with the csx signal, ? asserts the mr/w signal according to the type of access to be performed (low in the case of a write access, not used in burst read cycles). this level is retained until the start of the next address phase. ? at the end of the address phase the ebu returns the adv signal to high. the length (number of ebu_clk cycles) of the addre ss phase is programmed via the ebu_busapx.addrc bit field parameter. 1) if an active high, ale, signal is required, the polarity of the adv output can be inverted by setting the ale field of the ebu_modcon register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-64 v1.1, 2011-03 ebu, v1.9 15.15.2 address hold phase (ah) the address hold phase is optional. it cons ists of zero or more ebu_clk cycles. it is intended to provide hold time for the multiplexed address bits after the adv signal has returned to the inactive state. at the end of the address hold phase, the multiplexed address can be removed from the bus: ? during a read access, the multiplexed address/data bus can return to the high impedance condition to allow the read data to be driven by the external memory ? during a write access, the write data can be driven onto the multiplexed address/data bus 15.15.3 command delay phase (cd) the command delay phase is optional. this means that it can also be programmed for a length of zero ebu_clk clock cycles. the cd phase allows for the insertion of a delay between address phase (or optional address hold phase) and command phase(s). this phase accommodates devices that are not fast enough to receive commands immediately after getting the address or multiplexed devices which require a bus turnaround delay on reads. the length (number of ebu_clk cycles) of the command delay phase is programmed via the ebu_busapx.cmddelay bit field. this parameter makes it possible to select between zero to seven command delay phases. 15.15.4 command phase (cp) the command phase is mandatory for asynchronous devices. it always consists of at least one or more ebu_clk cycles. the phase can optionally be extended to accommodate slower devices. the length (number of ebu _clk cycles) of the comm and phase is separately programmable for read and write a ccesses. bit field ebu_busapx.waitrdc determines the basic length of command phases dur ing read cycles and bit field ebu_busapx.waitwrc determin es the basic length of command phases during write cycles. additionally, when accessing asynchronous devices, a command phase can also be extended externally using the wait signal when the region being accessed is programmed for external command delay control via bit ebu_busconx.wait or ebu_emubc.wait. the command phase is further subdivided into: ? cpi (= internally-programmed command phase) ? cpe (= externally-prolonged command phase, i.e. prolonged by the assertion of the wait signal). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-65 v1.1, 2011-03 ebu, v1.9 at the start of the command phase, the ebu: ? asserts the appropriate control signal rd or rd/wr low according to the access type (read or write), ? issues the data to be writt en on the data bus ad[15:0] (i n the case of a write cycle), ? asserts the appropriate bcx low (in the case where bcx is programmed to be asserted with the rd or rd/wr signals). at the end of the command phase during an asynchronous access, the ebu: ? returns the appropriate control signal rd or rd/wr high according to the type of access type (read or write), ? latches the data from the data bus ad[15:0] (in the case of a read cycle), ? returns the appropriate bcx high (in the case where bcx is programmed to be asserted with the rd or rd/wr signals). at the end of the command phase during a synchronous access, the rd or rd/wr signals hold their state and the state machine transfers to the burst phase. transition to burst phase will always occur synchrnously wi th a rising edge of bfclko. if necessary, the command phase will be extended to ensure that this happens. 15.15.5 data hold phase (dh) the data hold phase is optional. this means that it can also be programmed for a length of zero ebu_clk clock cycles. furthermore, it is only ava ilable for asynchronous write accesses (with two exceptions, see below). the data hold phase extends the amount of time for which data is still held on the bus after the rising edge of the rd/wr signal occurred. the data hold phase is used to accommodate external devices that require a data hold time after the rising edge of the rd/wr signal. the length (number of ebu_clk cycles) of the data hold phase is programmed via the ebu_busapx.datac bit field. 15.15.5.1 exceptional use of data hold in two cases, signals other than the data bus may need to have a hold time maintained relative to rd/wr or rd . these cases occur when adv and baa are being used as nand flash control signals which happens for agen settings of 2 d or 13 d . for these two settings, the data hold phase will apply to both reads and writes. 15.15.6 burst phase (bp) the burst phase is mandatory during burst accesses. at the end of the burst phase the ebu reads data from the data bus or updates the write data. during a burst access, burst phases are repeated as many times as require d in order to read or write the required amount of data from or to the external memory device. at the start of the first burst phase during a burst read access, the ebu: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-66 v1.1, 2011-03 ebu, v1.9 ? drives the baa signal low to cause the burst flash device to advance the address with each subsequent bfclko positive edge. the first burst phase of an access will always start on arising edge of bfclko. if necessary, the length of the previous phase will be extended to ensure that this happens. at the end of the last burst phase during a burst access, the ebu: ? returns the baa signal high, ? returns the csx signal high, ? returns the rd signal high. ? returns the rd/wr signal high provided that a control hold phase has not been programmed. during accesses to burst flash devices the length of the burst phase will be programmed such that the end of the burst phase always coincides with a positive edge of the appropriate bfclko (burst flash clock) signal. a burst phase is always at least one clock cycle in length. the length of each burst phase (i.e. the number of ebu_clk cycles) is derived from the value of the extclock and extdata fields in the ebu_busapx regist er. the length of t he burst phase will be either be: ? one period of bfclko if extdata is 00 b , ? two periods of bfclko if extdata is 01 b . ? four periods of bfcl ko if extdata is 10 b . ? eight periods of bfclko if extdata is 11 b . 15.15.7 control hold (ch) the control hold phase applies to synchronous reads to ddr burst flash (busrconx.agen = 9 d and busrconx.agen = 13 d ). the length of this phase will be forced to zero cl ocks for write accesses. it is an optional phase designed to allow for a variable delay between the memory device clock input and the device outputs. for ddr memories, this can potentially be more than a device clock cycle. programming a control hold phase allows the active state of the rd, baa and csx signals to maintained while the device completes the read access. the length of the control hold phase is controlled using the ebu_busrapx.datac bitfield. if an control hold phase is programmed for an onfi 2.0 device (busrconx.agen = 13 d ), then an additional cycle of bfclko will be added at the end of the programmed length with cs active and all other control signals inactive. this is needed to ensure that the memory device registers an idle command at the end of the access and returns the dqs and ad lines to a high impedance state. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-67 v1.1, 2011-03 ebu, v1.9 15.15.8 recovery phase (rp) the recovery phase is optional (although for access types which would cause a bus contention a single cycle of recovery is norma lly forced by the memory controller logic). this means that it can also be programmed for a length of zero ebu_clk clock cycles. this phase allows the insertion of a delay following an external bus access that delays the start of the address phase for the next external bus access. this permits flexible adjustment of the delay between accesses to the various external devices. the following individually programmable delays are prov ided on a region by region basis for the following conditions: ? bit fields ebu_busapx.rdrecovc determine the basic length of the recovery phase after a read access. ? bit fields ebu_busapx.wrrecovc determine the basic length of the recovery phase after a write access. ? bit fields ebu_busapx.dtacs determine the length (basic number of ebu_clk clock cycles) of the recovery phase after a read/write access of one region that is followed by a read/write access of another region or a read to one region is followed by a write to the same region (busrapx.dta cs) or a write to one region is followed by a read to the same region (buswapx.dtacs). the ebu implements a ?highest wins? algorithm to ensure that the longest applicable recovery delay is always used between consecutive accesses to the external bus. table 15-19 shows the scheme for determining this delay for all possible circumstances. for example, if a read access to a region associated with cs1 is followed by a write to a region associated with cs2 , the delay will be the highest of busrap1.dtacs and busrap1.rdrecovc. in this case, if busrap1.dtacs is greater than busrap1.rdrecovc, then the number of re covery cycles between the two accesses is busrap1.dtacs clock cycles (minimum). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-68 v1.1, 2011-03 ebu, v1.9 table 15-19 parameters for recovery phase case parameter(s) used to calculate ?highest wins? recovery phase region current access next access same csn read read rdrecovc write write wrrecovc read write busrapx.dtacs write read buswapx.dtacs different csn read read busrapx.dtacs, rdrecovc write write buswapx.dtacs, wrrecovc read write busrapx.dtacs, rdrecovc write read buswapx.dtacs, wrrecovc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-69 v1.1, 2011-03 ebu, v1.9 15.16 asynchronous read/write accesses asynchronous read/write access of the ebu support the following features: ? ebu_clk clock-synchronous signal generation ? support for 8-bit, 16-bit and 32-bit bus width performing an sri access with a data size greater than that of the external device automatically triggers a sequence of the ap propriate number of external accesses to match the sri access width. ? demultiplexed address/data lines ? programmable access parameters ? internal control of command delay cycles ? external and/or internal control of wait states ? variable data hold cycles for write operation (to allow flexible hold time adjustment) ? variable inactive/recovery cycles when: switching between different memory regions (cs), switching between read and write operations, after each read cycle, after each write cycle. software driver routines are required in order to support nand flash devices using asynchronous device accesses. a single nand flash access sequence is performed by generating the appropriate sequence of discrete asynchronous device accesses in software. 15.16.1 signal list the following signals of the ebu are used for asynchronous accesses: table 15-20 asynchronous mode signal list signal/pin type function ad[31:0] o address/data bus lines 0-31 a[27:0] o address bus lines 0-27 cs[3:0] o chip select 0-3 rd o read control line rd/wr o write control line bc[3:0] o byte control lines 0-3 wait i wait input mr/w o read/write signal with timimg for motorola peripherals www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-70 v1.1, 2011-03 ebu, v1.9 15.16.2 standard asynchronous access phases accesses to asynchronous devices are composed of a subset of the standard access phases which are detailed in section 15.15 . the standard access phases for asynchronous devices are: ? ap: address phase (compulsory - see page 15-63 ) ? ah: address hold phase (optional - see page 15-64 ) ? cd: command delay phase (optional - see page 15-64 ) ? cp: command phase (compulsory - see page 15-64 ) ? dh: data hold phase (optional - see page 15-65 ) ? rp: recovery phase (optional - see page 15-67 ) figure 15-21 above shows an example of an access to a non-multiplexed device and figure 15-22 an example of an access to a multiplexed device. 15.16.3 example waveforms the following figures show example wa veforms for asynchronous accesses www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-71 v1.1, 2011-03 ebu, v1.9 figure 15-21 asynchronous non-muxed access data in ebu_clk a[23:0] address ap0-14 ah0-14 cd0 cd14 cp0 cs0 rd d[31:0] cp30 address phase (1->15 ebu_clk cycles) command delay phase (0->15 ebu_clk cycles) bc[3:0] command phase (1->31 ebu_clk cycles) sample address hold phase (0->15 ebu_clk cycles) adv rp0 read cycle ebu_clk a[23:0] address ap0-14 ah0-14 cd0 cd14 cp0 cs0 wr d[31:0] cp30 address phase (1->15 ebu_clk cycles) command delay phase (0->15 ebu_clk cycles) bc[3:0] command phase (1->31 ebu_clk cycles) address hold phase (0->15 ebu_clk cycles) adv dh0 write cycle write data rp0 data hold phase (0->15 ebu_clk cycles) recovery phase (0->15 ebu_clk cycles) recovery phase (0->15 ebu_clk cycles) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-72 v1.1, 2011-03 ebu, v1.9 figure 15-22 asynchronous muxed access data in ebu_clk a[23:0] address ap0-14 ah0-14 cd0 cd14 cp0 cs0 rd d[31:0] cp30 address phase (1->15 ebu_clk cycles) command delay phase (0->15 ebu_clk cycles) bc[3:0] command phase (1->31 ebu_clk cycles) sample address address hold phase (0->15 ebu_clk cycles) adv rp0 read cycle ebu_clk a[23:0] address ap0-14 ah0-14 cd0 cd14 cp0 cs0 wr d[31:0] cp30 address phase (1->15 ebu_clk cycles) command delay phase (0->15 ebu_clk cycles) bc[3:0] command phase (1->31 ebu_clk cycles) address address hold phase (0->15 ebu_clk cycles) adv dh0 write cycle write data rp0 data hold phase (0->15 ebu_clk cycles) recovery phase (0->15 ebu_clk cycles) recovery phase (0->15 ebu_clk cycles) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-73 v1.1, 2011-03 ebu, v1.9 15.16.4 control of adv & other signal delays during asynchronous accesses for asynchronous accesses, the memory controller output signals: adv , cs , rd , rd/wr , and bc signals can be delayed with respect to the start of the access phases they are asserted in. the amount by which the signal is delayed depends on the setting of the ebu_busrapx.extclock field of the region being addressed for read accesses and the ebu_buswapx.extclock field of the region being addressed for writes:- ? when extclock is set to 00 b , control signals are asserted on the negative edge of ebu_clk. i.e. they are in effect delayed by an ebu_clk high pulse width (t ph )with respect to the other signals. ? when extclock is not set to 00 b , control signals are asserted on the next positive edge of ebu_clk. i.e. th ey are in effect dela yed by an ebu_clk cycle (t clk ) with respect to the other signals. the memory controller allows these delays to be enabled and disabled independently via the register bits ebu_busconx.ebse for adv and ebu_busconcx.ecse for the other control signals. the default setting after reset has the delay disabled. table 15-21 adv signal timing extclock is set to adv falling edge position adv rising edge position delay disabled 1) 1) see figure 15-21 for details of this signal positioning. delay enabled delay disabled 1) delay enabled 00 b start of ap1 start of ap1 + t ph start of ap1 start of ap1 + t ph 01 b , 10 b , 11 b start of ap1 end of ap1 start of ap1 end of ap1 table 15-22 rd and rd/wr signal timing extclock is set to set at: cleared at: delay disabled 1) 1) see figure 15-21 for details of this signal positioning. delay enabled delay disabled 1) delay enabled 00 b start of cp1 start of cp1 + t ph end of cpn 2) 2) cpn indicates the final command phase. end of cpn + t ph 01 b , 10 b , 11 b start of cp1 end of cp1 end of cpn end of cpn + t clk www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-74 v1.1, 2011-03 ebu, v1.9 the byte control signals, bc x, can either use the timing in table 15-22 if ebu_busconx.bcgen is set to 01 b or 10 b or the timing in table 15-23 if ebu_busconx.bcgen is set to 00 b . a ebu_busconx.bcgen value of 11 b is not valid for asynchronous accesses. write data is handled differently to the other signals. delays are never applied to the write data. note: if the control signals are delayed a recovery phase must be used to prevent conflicts between accesses as the rising edge of the control signals will be delayed past the end of the command phase. if a multiplexed access is used without a recovery phase, the address for the ne xt access will be delayed by one clock cycle to enforce a bus turnaround time on the da ta bus, resulting in the valid address being driven one clock after adv is asserted. 15.16.5 programmable parameters table 15-24 lists the programmable parame ters for asynchronous accesses. table 15-23 cs signal timing extclock is set to set at: cleared at: delay disabled 1) 1) see figure 15-21 for details of this signal positioning. delay enabled delay disabled 1) delay enabled 00 b start of ap1 start of ap1 + t ph end of dhn 2) 2) dhn indicates the final data hold phase. this is replaced by cpn, the final command phase, if the programmed data hold phase length is zero clocks. end of dhn + t ph 01 b , 10 b , 11 b start of ap1 end of ap1 end of dhn end of dhn + t clk www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-75 v1.1, 2011-03 ebu, v1.9 15.16.6 asynchronous access control in general, there are only two critical phase during accesses to asynchronous devices with separate address and data buses. these phases are: ? command phase (see page 15-64 ) which is used to control the widths of the output enable and write enable pulses. the length of the command phase is set by the bit fields ebu_busrapx.waitrdc and ebu_buswapx.waitwrc. ? data hold phase (see page 15-65 ) which is used to ensure that the write data is stable long enough to allow it to be successfully latched into the device. the length of the command phase is set by the bit field ebu_buswapx.datac as the ?address to data valid? and the ?chip select to data? valid parameters of asynchronous devices are usually greater than ?output enable to data valid? parameter, table 15-24 asynchronous access programmable parameters register parameter (bit/bit field) function ebu_busapx addrc number of cycles in address phase cmddelay number of programmed command delay cycles 1) . 1) this phase can be programmed for devices withou t multiplexed address and data busses but serves no purpose other than extending the access ahold number of cycles in address hold phase 1) waitrdc number of programmed wait states for read accesses. waitwrc number of programmed wait states for write accesses. datac number of data hold cycles. ebu_busapx rdrecovc number of minimum recovery cycles after a read access. wrrecovc number of minimum re covery cycles after a write access. dtardwr number of minimum recovery cycles between a read access and a write access. dtacs number of minimum recovery cycles when the next access going to a different memory region. ebu_busconx wait external wait state control (off, asynchronous, synchronous) waitinv reversed polarity at wait : active low or active high www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-76 v1.1, 2011-03 ebu, v1.9 the lengths of the ?address?, ?address hold? and ?command delay? phases can be used to extend the time between the start of the access when the address and chip select are driven and the end of the command phase when the read or write event occurs. for devices with a multiplexed address and data buses two additional phases control the latching of the address into the device and also critical: ? address phase (see page 15-63 ) which is used to control the width of the adv pulse. the length of the address phase is available via bit fields ebu_busapx. addrc ? address hold phase (see page 15-64 ) which is used to ensure that the address is stable long enough to allow it to be successfully latched into the device. the length of the address phase is available via bit fields ebu_busapx. aholdc 15.16.6.1 external extension of the command phase by wait the wait input can be used to cause the ebu to extend the command phase by inserting additional cycles prio r to deactivation of the rd and rd/wr lines. this signal can be programmed separately for each region to be ignored or sampled either synchronously or asynchronously (selecte d via the ebu_busconx.wait bit field). additionally, the polarity of wait can be programmed for active low (default after reset) or active high function via bit ebu_busconx.waitinv. the signal will only take effect after the programmed number of command p hase cycles has passed. this means that the signal can only be used to extend the phase, not to shorten it. when programmed for synchronous operation, wait is sampled on every rising edge of ebu_clk during the command phase. the sampled value is then used on the next rising edge of ebu_clk to decide whether to prolong the command phase or to start the next phase. figure 15-23 shows an example of wait used in synchronous mode. note: due to the one-cycle delay in synchronous mode between the sampling of the wait input and its evaluation by the ebu , the command phase must always be programmed to be at least one ebu _clk cycle (via ebu_busapx.waitrdc or ebu_busapx.waitwrc) in this mode. table 15-25 operation of wait input value of busconx.wait mode of the wait input 0 d off (default after reset). 1 d asynchronous input at wait. 2 d synchronous input at wait. 3 d reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-77 v1.1, 2011-03 ebu, v1.9 when programmed for asynchronous operation, wait is also sampled at each rising edge of ebu_clk during the command phase. however, an extra synchronization cycle is inserted prior to the use of the sa mpled value. this means that the sampled value is not used until the second following rising edge of ebu_clk. figure 15-24 shows an example of wait used in asynchronous mode. note: due to the two-cycle delay in asynch ronous mode between the sampling of the wait input and its evaluation by the ebu , the command phase must always be programmed to be at least two ebu_clk cycles (via ebu_busapx.waitrdc or ebu_busap.waitwrc) in this mode. figure 15-23 shows an example of the extension of the command phase through the wait input in synchronous mode: ? at ebu_clk edge 1 (at the end of the address phase), the ebu samples the wait input as low and starts the first cycle of the command phas e (cpi1 - internally programmed). ? at ebu_clk edge 2, the ebu samples the wait input as low and starts an additional command phase cycle (cpe2 - externally generated) as a result of the wait input sampled as low at ebu_clk edge 1. ? at ebu_clk edge 3, the ebu samples the wait input as high and starts an additional command phase cycle (cpe3 - externally generated) as a result of the wait input sampled as low at ebu_clk edge 2. ? finally at ebu_clk edge 4, as a result of the wait input sampled as high at point 3, the ebu terminates the command phase, reads the input data from d[31:0] and starts the recovery phase. note: synchronous operation means that even though access to the device may be asynchronous, the control logic generating the control signals must meet setup and hold time requirements with respect to ebu_clk. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-78 v1.1, 2011-03 ebu, v1.9 figure 15-23 external wait insertion (synchronous mode) figure 15-24 shows an example of the extension of the command phase through the wait input in asynchronous mode: ? at ebu_clk edge 1 (at the end of the address phase), the ebu samples the wait input as low and starts the first cycle of the command phas e (cpi1 - internally programmed). ebu_clk a[23:0] address ap cpi1 cpi2 cpe3 rp1 csx rd data in ad[15:0] wait read access with synchronous wait 1 2 3 4 (active low) in the example above, the command delay phase is internally programmed to zero ebu_clk cycles (no command delay phase). the command phase is internally programmed to one ebu_clk cycle. all other phases are programmed for one ebu_clk cycle. note: address adv www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-79 v1.1, 2011-03 ebu, v1.9 ? at ebu_clk edge 2, the ebu samples the wait input as low and starts the second cycle of the command phase (cpi2 - internally programmed). ? at ebu_clk edge 3, the ebu samples the wait input as high and starts an additional command phase cycle (cpe3 - externally generated) as a result of the wait input sampled as low at ebu_clk edge 1. ? at ebu_clk edge 4, the ebu starts an additional command phase cycle (cpe4 - externally generated) as a result of the wait input sampled as low at ebu_clk edge 2. ? finally at ebu_clk edge 5, as a result of the wait input sampled as high at ebu_clk edge 3, the ebu terminates the command phase, reads the input data from ad[15:0],and starts the recovery phase. figure 15-24 external wait insertion (asynchronous mode) ebu_clk a[20:16] address mct05732 ap cpi1 cpi2 cpe3 cpe4 csx rd ad[15:0] rp1 read access with asynchronous wait 1 2 3 4 5 data in in the example above, the command delay phase is internally programmed to zero ebu_clk cycles (no command delay phase). the command phase is internally programmed to two ebu_clk cycles. all other phases are programmed for one ebu_clk cycle. note: wait (active low) address adv www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-80 v1.1, 2011-03 ebu, v1.9 15.16.7 interaction with ddr signal timing if a ddr device is attached and ebu_dllcon . wr_en is enabled, then the write data and byte control signal timing will be affect ed. the storage elements used to drive the signal outputs will be operating off a shifted clock controlled by the dll. this will shift the outputs relative to the expected timing. for these reasons, asynchronous writes to single data rate devices when ebu_dllcon . wr_en is enabled will require additional data hold time. the recommendation is to allow an extra two clock cycles of data hold phase. 15.16.8 interfacing to asynchronous nand flash devices the memory controller provides support for specific nand flash devices. the required access sequences (read or write) are gen erated by connecting the nand flash device as an asynchronous device and using appropriate processor generated access sequences to emulate the nand flash commands. figure 15-25 shows an example of memory controller connected to a nand flash device:- figure 15-25 example of interfacing a nand flash device to the memory controller the r/b input from the nand flash is connected to the memory controller wait input and is available as the ebu_modcon.sts. this enables a nand flash to be driven by software from the processor. in the instance shown above two address lines are connected to the nand flash, and rather than being connected to address inputs, they are connected to control inputs. this allows access to three ?registers? in the nand flash as follows:- memory interface ebua 0002 memory interface ad(7:0) a(17) cs rd wr a(16) nand flash ce ale cle i/o(1:8) re we r/b wait www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-81 v1.1, 2011-03 ebu, v1.9 note: sri addresses are byte addresses and addresses on the external bus are word addresses. the sri address of the virtual register will depend on the port width. of the addressed memory region. see ?sri bus width translation? on page 15-51 15.16.8.1 nand flash page mode nand flash memories are page oriented devices capable of extended read operations with a single setup phase for command signals at the beginning of the access. the asynchronous controller of the memory controller will split a large transfer into multiple accesses to external memory but each of these accesses will have the ov erhead of the initial setup phase. enabling page mode, by setting the agen field in ebu_busconx to 2 d , will cause the standard flow of the controller to be modified as follows: ? for a read, if data remains to be fetched at the end of a command phase, the controller will start a new command delay phase, instead of a new address phase or recovery phase and the address will not be incremented. if ebu_busrapx.cmddelay is set to zero, the command delay phase will have a duration of one clock cycle but in this case the comma nd delay phase is mandatory to ensure that the rd and rd/wr signals return to the high state. ? for a write, if data remains to be written at the end of a data hold phase (or command phase if the length of data hold is zero), the controller will start a new command phase, instead of a new address phase or recovery phase and the address will not be incremented. if ebu_buswapx.datac is set to zero, the data hold phase will have a duration of one clock cycle as in this ca se the data hold phase is mandatory to ensure that the rd and rd/wr signals return to the high state. the command phase will be forced to have a minimum length of two clocks. enabling nand flash page mode will also reconfigure the ebu signals used for ale and cle. while a(17:16) can still be used directly, the same va lues will also be output on adv and baa . ?adv will be used as ale and will output the va lue of a(16). ? baa will be used as cre and will output the va lue of a(17). table 15-26 nand flash ?registers? (8 bit device) sri address ?register? comment base + 00000 h data register read/write: used to read data from and write data to the device. base + 10000 h address register write only: used to write the required access address to the device. base + 20000 h command register write only: used to write the required command to the device. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-82 v1.1, 2011-03 ebu, v1.9 figure 15-26 nand flash connection for agen=3 d to allow accesses to run consecutively without violating adv and baa timing restrictions, both signals will be set inactive (1 b ) at the beginning of the recovery phase of the access. see figure 15-27 for example waveforms. memory interface ebua 0053 memory interface ad(7:0) baa cs rd wr adv nand flash ce ale cle i/o(1:8) re we r/b wait www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-83 v1.1, 2011-03 ebu, v1.9 figure 15-27 nand flash page mode accesses example nand flash read sequence figure 15-28 shows an example of how the processor can generate a nand flash read access sequence given this configuration:- ebu_clk ap1 ah1 cpi1 cpi2 ad(7:0) adv csx ale/cle data in rd ap2 cdi1 cpi2 cdi1 cpi1 (a) read access ebu_clk ap1 ah1 cpi1 ad(7:0) ale csx ale/cle data out rd/wr ap2 cdi1 cpi2 dh1 (b) write access a(17:16) a(17:16) dh1 data in cpi1 cpi2 data out dh2 baa dh2 rp1 ale cre dh1 dh2 cre adv baa www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-84 v1.1, 2011-03 ebu, v1.9 figure 15-28 example of an memory controller nand flash access sequence (read) nand flash pins cle (a(17) or baa) ale (a(16 or adv) ce (cs2) we (wr) i/o(8:1) re (rd) ebul 4038 r/b (wait) read command 1 address (high byte) 2 address (middle byte) 3 address (low byte) 4 1st data 5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-85 v1.1, 2011-03 ebu, v1.9 1. in the cycle marked ?1? in figure 15-28 the processor initiates a read sequence by writing the ?read command? value to address ?nand_flash_base + 0x20000?. this generates a write sequence with cle (a(17)) driven high and ale (a(16)) driven low. 2. in the cycle marked ?2? the processor load s the most significant byte of the read address by writing to ad dress ?nand_flash_base + 0x 10000?. this generates a write sequence with cle (a(17)) driven low and ale (a(16)) driven high. 3. in the cycle marked ?3? the processor loads the middle significant byte of the read address by repeating the access specified in ?2? above. 4. in the cycle marked ?4? the processor load s the least significant byte of the read address by repeating the access specified in ?2? above. the nand flash responds to this final address byte by driving it?s r/b output low. the processor monitors this pin (using the ebu_modcon.sts bit) until the nand flash has completed it?s internal data fetch. 5. in the cycle marked ?5? the processor reads th e first byte of data by reading address ?nand_flash_base + 0x00000?. the processor can subsequently read any additionally required (sequential) data bytes by repeating cycle ?5?. note: a similar scheme can be used to generate write access sequences. 15.17 synchronous read/write accesses the memory controller is designed to generate waveforms compatible with the burst modes of: 1. intel and compatible burst flash devices 2. spansion and compatible burst flash devices 3. infineon and micron cellular ram 4. fujitsu and compatible fcram/utram/cosmoram 5. samsung onenand burst capable nand flash and compatible devices 6. m-systems diskonchipg3 and compatible devices 7. gsi ssram 8. ddr burst flash (xip) 9. onfi 2.0 nand flash note: not all of the supported synchronous memory types are known to be available in automotive grade features the synchronous access controller is primarily designed to perform burst mode read and write cycles for an external instruct ion memories, external cellular ram and fcram data memories. in general, the features are:- ? fully synchronous timing with flexible programmable timing parameters (address cycles, read wait cycles, data cycles). ? programmable wait function. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-86 v1.1, 2011-03 ebu, v1.9 ? programmable burst (mode and length) ? 8-bit device width. ? 16-bit device width. ? 32-bit device width ? page mode read accesses. ? resynchronisation of read data to a feedback clock to maximise the frequency of operation (optional). ? ddr device support 15.17.1 signals the following signals are used for the burst flash interface:- 15.17.2 support for four burst flash device types support is provided for a maximum of four di fferent burst flash configurations on the external bus - i.e. one on each external chip select. bit-fields ebu_busconx.ebse, ebu_ busconx.ecse, ebu_busconx.wait, ebu_busconx.fbbmsel, ebu_busconx.bfcmsel and table 15-27 burst fl ash signal list signal type function ad(31:0) i/o multiplexed address/data bus rd o read control wr o write control a(27:0) o address bus adv o address valid strobe wait i wait/terminate burst control cs (3:0) o chip select bfclko o burst flash clock, running equal to, 1/2, 1/3 or 1/4 of the frequency of ebu_clk. bfclki i burst flash clock feedback. ddrclko o negative phase of differential ddr clock baa o advance burst address sts i burst flash status input (optional, value of wait pin available through status register) mr/w o read/write signal for motorola type peripherals oclko o clock signal for onfi2 memory devices. output on the wr pin www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-87 v1.1, 2011-03 ebu, v1.9 ebu_busconx.fetblen are used to confi gure specific characteristics for burst access cycles. 15.17.3 typical burst flash connection the figure below shows a typical burst flash connection. figure 15-29 typical burst flash connection memory interface ad(15:0) csx rd rd/wr wait bfclko a(n:0) adv bfclki burst flash mem. dq(15:0) ce oe we adv wait clk a(n:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-88 v1.1, 2011-03 ebu, v1.9 15.17.4 standard access phases accesses to burst flash devices are composed of a number of ?standard access phases? (which are detailed in section 15.15 ). the standard access phases for burst flash devices are:- ? ap: address phase (compulsory - see ?address phase (ap)? on page 15-63 ). ? ah: address hold phase (optional see ?address hold phase (ah)? on page 15-64 ). ? cd: command delay phase (optional - see ?command delay phase (cd)? on page 15-64 ). ? cp: command phase (optional - see ?command phase (cp)? on page 15-64 ). ? bp: burst phase (compulsory - see ?burst phase (bp)? on page 15-65 ). ? ch: command hold phase (optional - see ?control hold (ch)? on page 15-66 ) ? rp: recovery phase (optional - see ?recovery phase (rp)? on page 15-67 ). note: during a burst access the burst phas e (bp) is repeated the required number of times to complete the burst length. see figure 15-30 for an example synchronous access to a non-multiplexed device and figure 15-31 for an example synchronous access to a multiplexed device. 15.17.5 example waveforms the following figures show example waveforms for synchronous accesses www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-89 v1.1, 2011-03 ebu, v1.9 figure 15-30 synchronous non-muxed access data in ebu_clk a[23:0] address ap0-14 ah0-14 cd0 cp0 cs0 rd d[31:0] address phase (1->15 ebu_clk cycles) command delay phase (0->15 ebu_clk cycles) bc[3:0] sample address hold phase (0->15 ebu_clk cycles) adv rp0 read cycle ebu_clk a[23:0] address ap0-14 ah0-14 cd0 cp0 cs0 wr d[31:0] address phase (1->15 ebu_clk cycles) command delay phase (0->15 ebu_clk cycles) bc[3:0] command phase (1->31 ebu_clk cycles) address hold phase (0->15 ebu_clk cycles) adv write cycle rp0 recovery phase (0->15 ebu_clk cycles) recovery phase (0->15 ebu_clk cycles) burst phase (0->15 ebu_clk cycles) bp0 bp14 burst phase (0->15 ebu_clk cycles) bp0 bp14 command phase (1->31 ebu_clk cycles) data in sample burst phase (0->15 ebu_clk cycles) bp0 bp14 write data 0 write data 1 burst flash write pulse cellular ram write pulse write pulse positioning selected by agen value bp0 bp14 burst phase (0->15 ebu_clk cycles) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-90 v1.1, 2011-03 ebu, v1.9 figure 15-31 synchronous muxed access data in ebu_clk a[23:0] address ap0-14 ah0-14 cd0 cp0 cs0 rd d[31:0] address phase (1->15 ebu_clk cycles) command delay phase (0->15 ebu_clk cycles) bc[3:0] sample address address hold phase (0->15 ebu_clk cycles) adv rp0 read cycle ebu_clk a[23:0] address ap0-14 ah0-14 cd0 cp0 cs0 wr d[31:0] address phase (1->15 ebu_clk cycles) command delay phase (0->15 ebu_clk cycles) bc[3:0] command phase (1->31 ebu_clk cycles) address address hold phase (0->15 ebu_clk cycles) adv write cycle rp0 recovery phase (0->15 ebu_clk cycles) recovery phase (0->15 ebu_clk cycles) burst phase (0->15 ebu_clk cycles) bp0 bp14 burst phase (0->15 ebu_clk cycles) bp0 bp14 command phase (1->31 ebu_clk cycles) data in sample burst phase (0->15 ebu_clk cycles) bp0 bp14 write data 0 write data 1 burst flash write pulse cellular ram write pulse write pulse positioning selected by agen value bp0 bp14 burst phase (0->15 ebu_clk cycles) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-91 v1.1, 2011-03 ebu, v1.9 15.17.6 burst length control the maximum number of valid data samples that can be generated by a flash device in a single read access is set by the ebu_busconx.fbbmsel bit and the ebu_busconx.fetblen bit field. the ebu_busconx.fbbmsel bit is used to select continuous burst mode where there is no limit to the number of data samples in a burst read access. the ebu_busconx.fbbmsel an d ebu_busconx.fetblen bit-fields are used to select the maximum number of data samples in a single access. where an sri request exceeds the amount of data that can be fetched or stored by the programmed number of data samples, the ebu will automatically generate the appropriate number of burst accesses to transfer the required amount of data. note: selection of continuous burst mode (by use of the ?fbbmsel? bit) overrides the maximum burst setting (specified by the fetblen bit-field). 15.17.7 burst flash clock since the ebu_clk can run too fast for clocking burst flash devices, the memory controller provides an additional clock source (bfclko). this signal is generated by a programmable clock divider driven by ebu_clk and allows ebu_clk to bfclko ratios of 1:1, 2:1, 3:1 and 4:1 to be selected. the frequency of the signal is determined by bit-field ebu_busrp.extclock. note that it is possible to set a different clock rate for synchronous writes to the same de vice by programming ebu_buswp.extclock to a different value. if a continuously running bfclko is required, then the busrconx.bfcmsel field can be used to enable an ungated flash clock. this bit is normally set to 1 b in all the busrconx registers after reset. if cleared, the related busrapx.extclock field will be used to generate a stable bfclko. if mu ltiple busrconx.bfcmsel fields are set to 0 b , then the highest priority (lowest index) busrapx.extclock field will be used. during a burst access to a synchronous device, bfclko will generate correctly aligned clock edges as shown in figure 15-32 . the bfclko signal is gated to ensure that it is low (zero) at all other times (including asynchronous read/writes of/to synchronous devices). this provides power savings and ensures correct asynchronous accesses to burst flash device(s). the start of the address and burst phases are synchronised, by hardware, to the rising edge of bfclko. exiting from a phase extended by the wait input will also be synchronised to the rising edge of bfclko. attaching ddr memory devices to the memory controller will impose additional restrictions on external bus clock generation. see ?external bus clock generation? on page 15-26 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-92 v1.1, 2011-03 ebu, v1.9 note: the length of the standard accesses phases during burst flash accesses are programmed as a multiple of ebu_clk independent of the bfclko frequency. it is the users responsibility to program the access phases to ensure that the sampling of data by memory controller g uarantees valid sampling of the data from the burst flash device. the ebu uses the ebu_clk clock to generate all external bus access sequences. unless documented elsewhere, all outputs to th e external bus are generated of the rising edge of ebu_clk. the bfclko phase is controlled so that control signal changes will normally occur at the rising edge of bfclko unless confi gured otherwise by register settings. 15.17.8 control of adv & control signal delays during synchronous accesses the memory controller output signals: adv , cs , rd , rd/wr , bc and ad signals can be delayed with respect to the bfclko clock signal. the delays can be enabled and disabled by the register bits ebu_busconx.ebse for the adv signal and by ebu_buscon.ecse for the cs , rd , rd/wr , baa and write data signals the amount by which the signal is delayed depends on the ratio of ebu_clk to the burst flash clock as follows:- ? when the ratio of ebu_clk to bfclko is 1:1, signals are asserted on the negative edge of ebu_clk. i.e. it is in effect delayed by an ebu_clk high pulse width (t ph ) with respect to bfclko. ? when the ratio of ebu_clk to bfclko is 1:2 or 1:3, control signals are asserted on the next positive edge of ebu_clk. i.e. it is in effect delayed by an ebu_clk cycle (t clk ) with respect to bfclko. ? when the ratio of ebu_clk to bfclko is 1:4, control signals are asserted on the negative edge of bfclko. i.e. it is in effect delayed by two ebu_clk cycles (2*t clk ) with respect to bfclko. table 15-28 extclock to clock ratio mapping extclock value bfclko divide ratio 00 1:1 01 1:2 10 1:3 11 1:4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-93 v1.1, 2011-03 ebu, v1.9 ? if the access is to a ce llular ram (buswconx.agen=3 d or 7 d ), then the rd/wr signal is treated as a qualifier to the address and its timing will therefore not be affected by the setting of ebu.buswcon.ecse. for read accesses the extclock field used will be from the busrapx register of the region being accessed. for write accesses th e extclock field used will be from the buswapx register of the region being a ccessed. however if a continuous bfclko is being generated (busrconx.bfcmsel=0 b ), for all accesses, the extclock value from the register with bfcmsel set to 0 b will be used when calculating delays. this ensures that the signals are always delayed correclty relative to the clock on the bflcko output. the default setting after reset has the delays disabled. if the delay is disabled, then the signals will not be delayed in 1:1 mode (except for adv which will be guaranteed to be after the edge of bfclko). in 2:1, 3:1 and 4:1 mode, the signals will be delayed by an ebu_clk high pulse width (t ph ) from the start of the cycle in which they are asserted. table 15-29 adv signal timing extclock is set to adv falling edge position adv rising edge position delay disabled 1) 1) see figure 15-30 for details of this signal positioning. delay enabled delay disabled 1) delay enabled 00 b start of ap1 start of ap1+t ph end of apn end of apn+t ph 01 b , 10 b start of ap1+t ph end of ap1 end of apn+t ph end of apn+ t clk 11 b start of ap1+t ph end of ap1 + t clk end of apn+t ph end of apn + 2*t clk table 15-30 rd and rd/wr signal timing extclock is set to set at: cleared at: delay disabled 1) delay enabled delay disabled delay enabled 00 b start of cp1 start of cp1 + t ph end of cpn 2) end of cpn + t ph www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-94 v1.1, 2011-03 ebu, v1.9 the byte control signals, bc x, can either use the timing in table 15-30 if ebu_busconx.bcgen is set to 01 b or 10 b or the timing in table 15-31 if ebu_busconx.bcgen is set to 00 b . a ebu_busconx.bcgen value of 11 b is not valid for synchronous accesses. 01 b , 10 b start of cp1 + t ph end of cp1 end of cpn + t ph end of cpn + t clk 11 b start of cp1 + t ph end of cp1 + t clk end of cpn + t ph end of cpn + 2*t clk 1) see figure 15-30 for details of this signal positioning. 2) cpn indicates the final command phase. table 15-31 cs data signal timing extclock is set to set at: cleared at: delay disabled 1) 1) see figure 15-30 for details of this signal positioning. delay enabled delay disabled delay enabled 00 b start of ap1 start of ap1 + t ph end of dhn 2) 2) dhn indicates the final data hold phase. this is r eplaced by cpn if the programmed data hold phase length is zero clocks. end of dhn + t ph 01 b , 10 b start of ap1 + t ph end of ap1 end of dhn + t ph end of dhn + t clk 11 b start of ap1 + t ph end of ap1 + t clk end of dhn + t ph end of dhn + 2*t clk table 15-30 rd and rd/wr signal timing (cont?d) extclock is set to set at: cleared at: delay disabled 1) delay enabled delay disabled delay enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-95 v1.1, 2011-03 ebu, v1.9 these delay options apply to write data only. addresses which are output on the data bus to support devices with multiplexed address and data connections are not delayed. note: if the control signals are delayed a recovery phase must be used to prevent conflicts between accesses as the rising edge of the control signals will be delayed past the end of the command phase. if a multiplexed access is used without a recovery phase, the address for the ne xt access will be delayed by one clock cycle to enforce a bus turnaround time on the da ta bus, resulting in the valid address being driven one clock after adv is asserted. 15.17.9 interaction with ddr signal timing if a ddr device is attached and ebu_dllcon . wr_en is enabled, then the write data and byte control signal timing will be affect ed. the storage elements used to drive the signal outputs will be operating off a shifted clock controlled by the dll. this will degrade the timing margins relative to the bfclko output and may shift the outputs by a complete clock cycle due to the differen t resynchronisation stages used. for these reasons, correct operation of synchronous writes to single data rate devices when ebu_dllcon . wr_en is enabled cannot be guaranteed and this combination of settings should be avoided. table 15-32 write data signal timing extclo ck is set to data driven at: data cleared at: data changes at: delay disabled 1) 1) see figure 15-30 for details of this signal positioning. delay enabled delay disabled delay enabled delay disabled delay enabled 00 b start of cp1 start of cp1 + t ph end of dhn 2) 2) dhn indicates the final data hold phase. this is r eplaced by cpn if the programmed data hold phase length is zero clocks. end of dhn + t ph start of bp1 start of bp1 + t ph 01 b , 10 b start of cp1 + t ph 3) 3) data bus will be enabled at the start of cp1 end of cp1 3) end of dhn + t ph end of dhn + t clk start of bp1 + t ph end of bp1 11 b start of cp1 + t ph 3) end of cp1 + t clk 3) end of dhn + t ph end of dhn + 2*t clk start of bp1 + t ph end of bp1 + t clk www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-96 v1.1, 2011-03 ebu, v1.9 15.17.10 burst flash clock feedback the memory controller can be configured to use clock feedback to optimise the operating frequency for a given flash device. this is enabled by setting the ebu_busconx.fdbken bit to one. with this bit enabled the first sampling stage for read data has its own clock (pd_bfclkfee dbk_i). this will be derived from the bfclko output by using a second pad (bfclki) to monitor the bfclko signal after the output pad delay. clock feedback should be used whenever possible as it allows the best possible performance a side effect of using this mode is an increase in data latency by one bfclko cycle compared with not using clock feedback. note: clock feedback will be automatically di sabled for burst writes as the additional latency on the wait input would prevent correct operation of the memory controller. 15.17.11 asynchronous address phase as operating frequency increases, it becomes increasingly hard to avoid violating some timing parameters. the asynchronous address phase allows the address to be latched into the flash memory using the adv signal before the clock is enabled. this is only possible if explicitly allowed by the flash data sheet. if the ebu_busconx.aap is set, then the clock will not start until the end of t he address hold phase of the access. the rising edge of the clock will always be co-incident with the transition from the address hold phase. if the address hold phase has zero length then the first rising edge of the clock will coinci de with the tranistion from the address phase. if this mode is enabled a recovery phase of one bfclk period will be enforced at the end of the previous transaction to ensure that the clock has time to turn off before the start of the next access. setting this mode for any region will force the clocks on all synchronous accesses to be disabled in the recovery p hase. only one clock pulse will occur during the recovery phase. aap mode is incompatible with the contin uous clock mode and will be disabled automatically if continuous clocking is enabled by setting any busrconx.bfcmsel bit to 0 b . 15.17.12 critical word first read accesses in the default case, the memory controller will always start a burst at the lowest address possible and wrapping of the burst data is handled internally to the memory controller. however, some burst devices implement a wrapping feature which is compatible with the wrapped bursts used by the processor cache fill requests. if this is the case, there is an www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-97 v1.1, 2011-03 ebu, v1.9 advantage to using the wrapping mode in the device as the instruction required by the processor (the critical word) can be fetched first from the external memory. the mode is enabled by setting the ebu_bus conx.dba bit for the appropriate region. once enabled, the memory controller will not align the star t address for t he burst and the device will be relied on to return data in the correct order. the memory controller must fetch all the data in a single burst. if the transaction is split into multiple accesses on the external bus by use of the fetblen field, the issued addresses will be incorrect. note: the cache line fill will use an sri, btr4 transfer. this translates to a 16 word burst for a 16 bit device. the device must ther efore support a 16 word wrap setting. a 32 bit memory must support a 8 word wrap setting. the memory controller supports a 16 word burst using the continuous burst setting for fbbmsel. other burst opcodes must not be generated for accesses to the external memory by the system if this mode is enabled, otherwise data corruption will occur. 15.17.13 example burst flash access cycle the figure below shows an example burst flash access without clock feedback configured. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-98 v1.1, 2011-03 ebu, v1.9 figure 15-32 burst flash read without clock feedback (burst length of 4) ebu_clk ap1 ap3 cdi1 cpi2 bp2 a(max:0) x address csx rd ap2 ah1 cdi2 cpi1 bp1 bp1 bp1 bp1 rp2 bp2 bp2 bp2 rp1 new ap1 bfclko adv ad(15:0) (16 bit wide data) data in (address 0) data in (address 2) data in (address 4) data in (address 6) data latched by ebu on +ve edge of int_clk next data value issued by flash in response to +ve edge of bfclko notes: 1. 2. 3. the start of the cycle is synchronised to a +ve edge of the bfclko signal. the bfclko signal is used to clock the burst flash devices. bfclko to int_clk frequency ratio can be programmed to be 1:1, 1:2, 1:3 or 1:4 (1:2 operation is shown). each bfclko +ve edge is generated from a +ve edge of int_clk. 4. addresses shown are "byte addresses" (e.g. for 32-bit operation each value read by the ebu represents a 4 byte address increment). 5. adv signal positioning is programmable via the ebse bit in the buscon registers. ebua 0034 address www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-99 v1.1, 2011-03 ebu, v1.9 figure 15-32 shows an example of a burst read access (burst length of four) to a burst flash device with wait and clock feedback functions disabled. programmability of t he length of the ad dress, command dela y and command phases allows flexible configuration to meet the initial read access time of a burst flash device. data is sampled at the end of each burst phase cycle. the burst phase is repeated the appropriate number of times for the program med burst length (programmable for lengths of 1, 2, 4 or 8 via the ebu_busconx.fetblen bit-field). figure 15-32 shows an access cycle with the following settings:- ? clock feedback disabled. ? address phase length = 3 ebu _clk cycles (see addrc and ?address phase (ap)? on page 15-63 ). ? command delay phase length = 3 ebu_clk cycles (see cmddelay and ?command delay phase (cd)? on page 15-64 ). ? command phase length = 2 ebu_clk cycles (see waitrdc and ?command phase (cp)? on page 15-64 ). ? burst phase length = 2 ebu_clk cycles (see extclock, extdata and ?burst phase (bp)? on page 15-65 ). ? recovery phase length = 2 ebu_clk cycles (see ?recovery phase (rp)? on page 15-67 ). ? burst length = 4 (see fetblen). ? bfclko frequency = 1/2 of ebu_clk frequency (see extclock). 15.17.14 external cycle control via the wait input memory controller provides control of the burst flash device via the wait input. this allows memory controller to support oper ation of burst flash while crossing burst flash page boundaries. during a burst flash access the wait input operates in one of four modes:- ? disabled ? early wait for page load. ? wait for page load. ? abort and retry access. selection of the mode in which the wait input operates during burst flash reads is selected via the ebu_busconx.wait bits. table 15-33 operation of wait input value of busconx.wait mode of the wait input 0 d off (default after reset). 1 d wait for page load (early wait). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-100 v1.1, 2011-03 ebu, v1.9 note: selection of ?disabled? via the wait bit-field prevents the wait input having any effect on a burst flash access cycle wait for page load mode this mode supports devi ces which assert a wait output for the duration of clock cycles in which the data output by the device is invalid or, alternatively, one clock cycle earlier than the data output is invalid. this includes intel and amd burst flash devices (and compatibles) configured for early wait generation mode (ebu_busconx.wait=01 b ) and standard wait generation (ebu_busconx.wait=10 b ). in operation, the burst flash controller loads a counter with the required number of samples at the start of each burst. at the end of each burst phase, the burst flash controller samples the wait input and the data bus at the end of each burst phase. if wait is inactive, the sample is valid, the sample counter is decremented and the sampled data is passed to the datapath of the memory controller. this synchronous sampling means that the validity of the sample can not be determined until the clock cycle after the end of the burst phase. the burst flash contro ller will therefore overrun and generate extra burst phases until the sample counter is decremented to zero. extra data samples returned after the sample counter is zero will be discarded. the only difference if early wait is used is that the validity of data in burst phase "n" is determined by the value of wait in burst phase "n-1". this mode of operation is compatible with the use of clock feedback as, with feedback enabled, wait is fed through the same resynchronisation signals as the data bus. the only effect on operation is t hat the number of overrun cycl es will increase as the decrementing of the sample counter will be lagged by the resynchronisation stages. during the initial phases of an access, wait is sampled on every edge of ebu_clk. this is so the first burst phase is working with an accurate value for the wait signal. to ensure this is the case, the command phase should be of sufficient length to allow the device to drive wait and for the signal to propagate to the controller. abort and retry access in this mode, the wait input is polled during the address and address hold phases only. if an active state on wait is detected, the address phase of the access will be restarted after the end of the address hold phase. 2 d wait for page load (wait with data). 3 d reserved table 15-33 operation of wait input (cont?d) value of busconx.wait mode of the wait input www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-101 v1.1, 2011-03 ebu, v1.9 in this mode wait cannot be used to extend the command phase of an access. 15.17.15 flash non-array access support several types of flash memories will assert wait permanently during an access which is not directed to the memory array. an example of this would be polling the status register to check if a programming operation has completed. if the busrcon[3:0].naa field is set, then an access to the region with sri a(26) set will proceed as if the appropriate wait field in busrcon[3:0] or buswcon[3:0] was set to 00 b and wait was disabled. when set, this field affects both read and write accesses. 15.17.16 termination of a burst access a burst read operation is terminated by de-asserting csx signal followed by the appropriate length recovery phase. figure 15-33 shows an example of termination of a burst access following the read of two locations (i.e. two burst phases) from a 16-bit non-multiplexed burst flash device. figure 15-33 terminating a burst by de-asserting cs 15.17.17 burst flash device programming sequences programming sequences for some burst flash devices must not be interrupted by other read/write operations to the same device. there is an optional hardware lock feature to ebu_clk ap2 cpi2 bp1 bp2 bp1 bp2 a(max:0) address adv csx rd data 1 cpi1 ad(15:0) rp1 rp2 bfclko data 2 ebua 0040 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-102 v1.1, 2011-03 ebu, v1.9 guarantee that programming sequences are not interrupted. see section 15.9.1 for details. 15.17.18 cellular ram cellular ram devices have been designed to meet the growing memory and bandwidth demands of modern cellular phone designs. the devices have been designed with a ?multi-protocol? interface to allow use of the devices with existing memory interfaces (i.e. by re-use of existing memory protocols). th e supported interface protocols supported by cellular ram devices are:- 1. sram (asynchronous read and write). 2. nor flash (synchronous burst read, asynchronous write). 3. synchronous (synchronous burst read and write). in principle, when using previous versions of memory controller, the first two of the above modes (1 and 2 above) provided cellular ram support. for maximum performance, the memory controller now su pports synchronous mode (3 above) for cellular ram (synchronous burst read and write). as cellular ram synchronous mode consists of a burst flash compatible burst read access, cellular ram support has been provided by enhancing the burst flash interface by the inclusion of a burst writ e capability. for this reason cellular ram is treated as a special type of burst flash device. cellular ram support is selected by progra mming the desired region as cellular ram via the ebu_busconx.agen bit-field. synchronous read access a synchronous cellular ram burst read access is compatible with a burst flash burst read access. as a result preceding sections applying to burst flash devices apply and should be consulted for details of cellular ram burst read accesses. 15.17.18.1synchronous write access www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-103 v1.1, 2011-03 ebu, v1.9 figure 15-34 burst cellular ram burst write access (burst length of 4) figure 15-34 shows an example of a cellular ram burst write access. ebu_clk ap1 ah1 cp1 bpi2 a (max:16) -muxed a(max:0) - non- muxed x address csx wr ap2 ah2 cp2 bpi1 bp1 bp1 bp1 rp2 bp2 bp2 bp2 rp1 new ap1 bfclko adv ad(15:0) (16 bit wide data) data out (addr 0) data out (addr 2) data out (addr 4) data out (addr 6) data latched by cram in response to +ve edge of bfclko next data value issued on +ve edge of int_clk ebua 0041 notes: 1. 2. 3. the start of the cycle is synchronised to a +ve edge of the bfclko signal. the bfclko signal is used to clock the cellular ram devices. bfclko to int_clk frequency ratio can be programmed to be 1:1, 1:2, 1:3 or 1:4 (1:2 operation is shown). each bfclko +ve edge is generated from a +ve edge of int_clk. 4. addresses shown are "byte addresses" (e.g. for 16-bit operation each value written by the ebu represents a 2 byte address increment). 5. adv signal positioning is programmable via the ebse bit in the buscon registers. wait 1 2 4 3 5 address bp1 bp2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-104 v1.1, 2011-03 ebu, v1.9 note: figure 15-34 shows operation with a bfclko to ebu_clk ratio of 1:2. the start of the access cycle is the same as for a synchronous read access (see figure 15-32 ) except that the wr signal is treated as an address phase signal (i.e. it is asserted active during the address phase and address hold phase and is then deasserted). see ?fujitsu fcram support (burst wr ite with wr active during data phase)? on page 15-104 for alternative wr timing during burst write. the remaining sequence is as follows (with reference to the figure above):- 1. at the positive edge of ebu_clk labelled as ?1? above the first burst phase starts. as the state machine is currently in the command phase, the interface samples the wait input. this is sampled as ?active?. by coincidence, in this example, the cellular ram also deasserts it?s wait output as a response to this clock edge to signal that it will start to take the data from the data bus on the bfclko rising clock edge after the next (i.e. the rising edge of bfclko labelled as ?5? above) - this need not be the case. 2. at the positive edge of ebu_clk labelled as ?2? above the second programmed ebu_clk period of the burst phase begins. 3. at the positive edge of ebu_clk labelled as ?3? above the burst flash evaluates the wait sample from ?1? above. as this samp le was ?active? the write data is not updated. as this clock edge is coincident with the end of a burst phase the wait input is resampled. the value of this new wait sample is ?inactive?. 4. at the positive edge of ebu_clk labelled as ?5? above the burst flash again evaluates the wait sample from ?3? above. as this sample was ?in-active?, and the edge is coincident with the end of a burst phase, the next data value is issued to the ad(15:0) pins and the next burst phase is started. this process continues until all the data is written. 15.17.18.2fujitsu fcram support (burst write with wr active during data phase) the fcram device type can be supported in two ways. later fcrams have a compatibility bit in the device configurat ion register which programmes the device to expect the wr signal to be active with the address and to be latched with the adv signal. in this mode, fcram can be treated as an infineon/micron cellular ram. alternatively, if a write is attempted to a region configured as a burst flash, the memory controller will generate a burst write with the wr signal asserted with the write data. this should be directly compatible with an fcram operating in its native mode. 15.17.19 ddr burst flash support the memory controller includes features which allow the support of flash memories using a ddr data bus protocol. t he memory types supported are: ? ddr nor flash memory, supporting ddr read and write accesses www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-105 v1.1, 2011-03 ebu, v1.9 ? onfi 2.0 nand flash configuring a region to support either of the memory types will enable the requisite number of dqs lines to support the attached memory. the dqs lines will be multiplexed onto the most significant address lines as these will not be required for the supported ddr memo ries. once enabled as dqs, the address lines will not be availabl e as addresses for any devi ces attached to the ebu. it is recommended that ddr flash is only used with other ddr memories due to the critical load matching requirements on the dq/dqs/dqm lines. mixing memory types may limit the supportable operating frequency. ddr flash support using an busconx.extclock setting of 00 b (1:1 internal to external clock ratio) requires the use of the memory controller dll. other clock ratios are supported using edges of the internal cl ock signal to generate the signal waveforms (see ?generation of ddr control signals without using the dll? on page 15-24 ). 15.17.19.1 ddr nor burst flash ddr nor burst flash support is configured by setting the agen fields of the busconx register to 9 d . however, at present there are no dev ices that are known to support writes using this protocol so it is expected that the device will be configured for ddr reads and asynchrnonous writes. configuring support for this type of device will enable the differential bfclk clock (see ?external bus clock generation? on page 15-26 ). it will also enable the generation of addresses on the ad bus to allow support multiplexed address/data memories. ddr nor burst flash can have an internal pll. if this is the case, the clock must be set to continuous mode by setting the bfcmsel field of the busrcon register to 0 b . note: once the differential clock has been enabled, there will be a delay while the pll locks. during this delay, the device cannot be a ccessed synchronously. for accesses to ddr nor flash, the reading of data will be handled in the same way as for ddram. see chapter 15.10.4 and chapter 15.10.6 for a full description of the methods available. due to uncertainty in the read signal output timing of the attached device, read accesses will always use the full burst length programmed in the fetblen bitfield. continuous burst mode is not available. setting continuous burst mode using the fbbmsel bitfield will result in a burst length of sixteen being programmed. for read accesses, any unused data words will be discarded. as the burst length of the ebu is defined in cycles of bfclko and the burst length of the flash may be defined in data words, there may be a mismatch for ddr devices. if the device burst length is defined in data words per read then the programmed ebu burst length must be half the burst length prog rammed into the device configuration register. the ebu will expect two data words per burst phase when accessing ddr devices. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-106 v1.1, 2011-03 ebu, v1.9 ddr nor flash read accesses should be extended using a control hold phase ( ?control hold (ch)? on page 15-66 ). this is used to prevent the device outputs being disabled before the last data word can be output by the device. this is necessary as the worst case timing delay between the clock input to the device and the output of the dqs and data word may be great enough to move the output signals into the next clock period. cancellin g the control signals at the end of the burst p hase may therefore diable the device outputs before the last data can be latched into the ebu. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-107 v1.1, 2011-03 ebu, v1.9 figure 15-35 ddr nor burst flash read cycle ebu_clk ap1 ap3 cdi1 cpi2 a(max:0) x address csx rd ap2 ah1 cdi2 cpi1 bp1 bp1 bp1 ch2 ch1 new ap1 bfclko adv ad(31:0) (32 bit wide data) d0 data latched by ebu on edge of dqs shifted internally by the dll next data value issued by flash in response to edge of bfclko notes: 1. 2. 3. the start of the cycle is synchronised to a +ve edge of the bfclko signal. the bfclko signal is used to clock the burst flash devices. bfclko to int_clk frequency ratio can be programmed to be 1:1, 1:2, 1:3 or 1:4 (1:2 operation is shown). each bfclko +ve edge is generated from a +ve edge of int_clk. 4. adv signal positioning is programmable via the ebse bit in the buscon registers. ebua 0052 address bp1 bp1 bp1 bp1 bp1 d1 d2 d3 d4 d5 d6 d7 xx h dqs rp2 rp1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-108 v1.1, 2011-03 ebu, v1.9 15.17.19.2 onfi 2.0 nand flash the ebu can interface to nand flash memories complying with the onfi 2.0 specification. initial, asynchronous, oper ation is handled using the agen value 2 d (nand flash page mode). once configured for synchronous operation, the agen field should be set to 13 d . connection of an eight bit device is as in below. connection of 16 and 32 bit devices is the same with the additional ad and dqs connections. a 16 bit device will need ad(15:8) and dqs(1). a 32 bit device will also need ad(31:16) and dqs(3:2). multiple devices can also be connected in parallel to make up a large word width. figure 15-36 connection of 8 bit onfi 2.0 nand flash while agen is set to 2 d , the state of the dqs signal(s) on a write access will be determined by a(18) of the access. this is equivalent to a sri (18) for 8 bit devices. when agen is set to 13 d , the state of the dqs signal(s) during a write access will be determined by a(18) unless both a(17) ands a(16) are set to 1 b . if a ebu (17:16) is set to 11 b , a data transfer (as defined in the onfi specification) is in progress and the dqs lines will be used to clock the data. if agen is 13 d and a data transfer is not in progress then the burst length of all transfers to the device should be restricted by software to a single data phase. this is to enable the successful writes of command and address data. write data will be transferred at single data rate if a data transfer is not in progress as the attached device will use the clock to latch the write data and will not expect dqs. memory interface ebua 0054 ad(7:0) baa cs rd mr/w adv onfi 2.0 nand flash ce ale cle i/o(1:8) re we or clk r/b wait dqs(0) dqs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-109 v1.1, 2011-03 ebu, v1.9 example waveforms for the onfi 2.0 interface protocol are shown below. table 15-34 onfi 2.0 nand flash comma nd signal control (8 bit device) sri address signal(s) set asynchronous mode usage synchronous mode usage base + 00000 h no command signals set read/write: used to read data from and write data to the device. bus idle. 1) 1) if used on a read access, the ebu will stall indefinitely waiting for read data. base + 10000 h ale write only: used to write the required access address to the device. base + 20000 h cre write only: used to write the required command to the device. base + 30000 h ale+cre invalid data transfer base + 40000 h dqs read/write: use base + 0000 h instead bus idle base + 50000 h ale+dqs write only: used to write the required access address to the device. use base + 10000 h instead. base + 60000 h cre+dqs write only: used to write the ?set features? command to the device. base + 70000 h ale+cre invalid data transfer www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-110 v1.1, 2011-03 ebu, v1.9 figure 15-37 onfi 2.0 nand flash: data transfer cycles oclko ap1 ah1 cpi1 bp4 ad(7:0) adv csx data w/r ap2 cpi bp1 bp2 bp3 (a) read access oclko ap1 ah1 cpi1 ap2 cdi1 bp1 dh2 (b) write access b ua0055 ? onfi 2.0 nand flash dh1 bp4 dh1 rp1 baa dh2 ale cre bp2 bp3 dqs data data data data data data data ad(7:0) adv csx data w/r baa ale cre data data data data data data data dqs rp1 control hold 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-111 v1.1, 2011-03 ebu, v1.9 figure 15-38 onfi 2.0 command cycles note: the onfi 2.0 specification does not su pport byte transfers to/from 16 or 32 bit devices in source synchronous mode. th e ebu will translate requests for byte reads into a word read and discard the extra data. writes, however, will always transfer 16 bits of data to the device (the superfluous data will not be masked). 15.17.20 programma ble parameters the following table lists the programmable parameters for burst flash accesses. these parameters only apply when the ebu_busconx.agen parameter for a particular memory region is set for access to synchronous burst devices (page mode or otherwise). oclko ap1 bp1 dh2 bp1 ad(7:0) adv csx w/r cpi1 dh1 ap1 ap2 cpi1 (a) status read access oclko ap1 bp1 dh2 cpi1 dh1 ap1 rp1 (b) write access dh1 dh1 dh2 rp2 baa dh2 rp1 ale cre cpi1 bp1 dqs ad(7:0) adv csx w/r baa ale cre dqs data data write data write data write data www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-112 v1.1, 2011-03 ebu, v1.9 table 15-35 burst flash access programmable parameters parameter function register addrc number of cycles in address phase. ebu_busapx aholdc number of cycles in address hold. ebu_busapx cmddelay number of programmed command delay cycles. ebu_busapx waitrdc number of programmed wait states for read accesses. ebu_busapx waitwrc number of programmed wait states for write accesses. ebu_buswapx extdata extended data ebu_busapx rdrecovc number of minimum recovery cycles after a read access when the next access is to the same region. ebu_busrapx wrrecovc number of minimum recovery cycles after a write access when the next access is to the same region. ebu_buswapx rddtacs number of minimum recovery cycles after a read access when the next access is to a different region. ebu_busrapx wrdtacs number of minimum recovery cycles after a write access when the next access is to a different region. ebu_buswapx wait sampling of wait input: off, synchronous, asynchronous or wait_cellular_ram ebu_busconx fbbmsel flash synchronous burst mode: continuous or defined (as in fetblen) ebu_busconx fetblen synchronous burst length: single, burst2, burst4 or burst8 ebu_busconx bfcmsel flash clock mode, continuous or gated ebu_busrconx www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-113 v1.1, 2011-03 ebu, v1.9 note: datac is not used for burst write accesses 15.18 sdram interface the sdram interface supports 16 and 32 bit bit sdram configurations with four banks at densities up to 1 gbit. please see the intel? pc100 specification for signalling waveforms for this interface. the memory controller can support a single sdram region. to enable sdram support the agen fields of a single register pai r of ebu_busrcon and ebu_buswcon must be set to "8 d ". note: programming the agen fields of multiple regions for sdram and connecting multiple sdrams will result in data co rruption as the "page open" tags in the sdram controller will be applied indiscriminately to all connected devices. 15.18.1 features ? compatible with mobile pc133 memories at 125 mhz (if maximum bus load is not exceeded) when used with optimised pads. ? mobile sdram support. extclock frequency of external clock at pin oclko: equal, 1/2 or 1/4 of ebu_clk ebu_busapx ebse delay adv output to improve hold margin ebu_busconx ecse delay cs , wr and write data outputs to improve hold margin ebu_busconx lockcs enable locked write sequences for this region ebu_buswconx fdbken enable clock feedback to improve read data margins ebu_busrconx dba disable alignment of read bursts on external bus ebu_busrconx aap enable the "asynchronous address phase" mode. ebu_busconx portw memory port width ebu_busrconx table 15-35 burst flash access programmable parameters (cont?d) parameter function register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-114 v1.1, 2011-03 ebu, v1.9 ? support for 64, 128, 256, 512 mbit and 1 gbit sdram devices. ? auto-refresh mode support. ? support for 16 and 32 bit bus widths. ? power-on/mode-set sequence triggered by sri write to ebu_sdrmod configuration register. ? programmable refresh rate. ? programmable timing parameters (row-to-c olumn delay, row-precharge time, mode- register setup time, initialization refresh cycles, refresh periods). ? multiple power save modes supported ? clock stop ? power down without precharge ? power down with auto-precharge ? power down with precharge ? self refresh 15.18.2 signal list the following signals are used for the sdram interface:- table 15-36 sdram signal list (16 bit support) signal type function ad(15:0) i/o data bus a(27:0) o address bus rd/wr o read and write control cke o clock enable cs(3:0) o chip select sdclk0 o/i external sdram clock. sdclki i external sdram clock feedback ras o row address strobe for sdram accesses. cas o column address str obe for sdram accesses. dqm(3:0) o data qualifiers (output on bc (3:0)) table 15-37 sdram signal list (32 bit support) signal type function ad(31:16) i/o data bus msw ad(15:0) i/o data bus lsw a(15:0) o address bus (a(27:16) not needed for sdram) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-115 v1.1, 2011-03 ebu, v1.9 15.18.3 external interface the external interface can be directly connected to dram chips without any glue-logic. special board layout and timing constraints may apply when additional memory/peripherals (in addition to sdram devi ces) are directly connected to the bus. 16 and 32 bit devices are supported. additionally, two 16 bit devices connected in parallel to make a 32 bit device are also supported. in this case, the memory controller region should be configured to support a 32 bit device but with the buscon portw fields set to 10 b to indicate a twin, 16 bit configuration. note: the memory controller always resets to ?no bus? arbitration mode and will then synchronously transition to the appr opriate mode and enable the required pins based on the register settings. this me ans that the sdram specific pins will be under the control of the ports i/o logic af ter reset. cke must either be driven to an appropriate value for the application by the reset value of the ports logic or held to a valid state by a pull resistor on the pcb. rd/wr o read and write control cke 1) o clock enable cs(3:0) o chip select sdclk0 o/i external sdram clock sdclki i external sdram clock feedback ras o row address strobe for sdram accesses. cas o column address strobe for sdram accesses. dqm(3:0) o data qualifiers (output on bc (3:0)) 1) pull down resistor required to maintain a valid logic level when the ebu is not driving the bus. see chapter 15.18.3 table 15-37 sdram signal list (32 bit support) (cont?d) signal type function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-116 v1.1, 2011-03 ebu, v1.9 figure 15-39 connectivity for 16 bit sdram ebua0046 flash d(15:0) a(15:0) memctrl cs sram cs cs rom cs sdram #1 ad(15:0) a(24:0) cs[m] other lines cs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-117 v1.1, 2011-03 ebu, v1.9 figure 15-40 connectivity for 32 bit sdram 15.18.4 sdram external bus clock generation the memory controller uses the ebu_clk clock as a reference to generate all external bus access sequences. sdclko is required by sdram memories and the frequency of this output is controlled by the ebu_busrap.extclock field of the highest priority (lowest region number) region which has ebu_busrcon.agen set to 8 d , 10 d or 12 d which are the values used to select the sdram state machine. ebu_buswap.extclock has no effect for sdram. unless documented elsewhere, all outputs to the external bus are generated synchronously to the falling edge of sdclko. this means that the sdram memory device sees control signal changes occur on the negative clock edge. connecting ddr memories to the ebu will impose additional constaints on the external bus clocks. see ?external bus clock generation? on page 15-26 . ebua0047 flash d(15:0) d(31:16) a(14:0) memctrl cs sram cs cs rom cs sdram #1 ad(15:0) ad(31:16)/ a(15:0) cs[m] other lines cs sda(14:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-118 v1.1, 2011-03 ebu, v1.9 15.18.5 sdram characteristics sdrams are synchronous drams with burst read/write capability which are controlled by a set of commands at the pins cs , ras , cas , we , dqm and a10. as for standard drams, a periodic refresh must be performed. sdram devices are subdivided into ?banks?. each bank is subdivided into a number of ?rows 1) ?. each row is, in turn, subdivided into a number of ?columns?. the number of banks and the size of a row varies from one sdram device to another. a specific location (half-word) within a device is specified by supplying a bank, row and column address. devices supported by memory controller must conform to the following criteria:- ? number of banks: 2 or 4 only. ? row size: 256, 512 or 1024 only. sdram devices produce high speed data transfer rates by use of the bank and row architecture. when an initial access is made to a specific row within a specific bank then memory controller must issue a ?row? address to specifiy which row in which bank is to accessed. in response to th is the sdram device loads the entire row to a local (high speed) buffer area. at this point (i.e. when the local buffer associated with a bank contains data from the main sdram array) the bank is said to be ?open?. memory controller then issues a ?column? address to specifiy which location(s) within the row are to be accessed. subsequent accesses to locations within the same row can then be performed at high speed (with memory controller supplying only a column address) since the appropriate data is already contained within the local buffer and there is no requirement for the sdram to fetch data from the main sdram array. prior to accessing a location in a different row me mory controller must issue a ?precharge? command so that the local buffer is written back to the main sdram array. an sdram device provides a local buffer for each bank within the device, thus it is simultaneously possible for each of the banks to be ?open?, this is termed ?multibanking?. multibanking is supported in order to allow interleaved bank accesses. comparison of table 15-38 extclock to clock ratio mapping extclock value sdclko divide ratio 00 1:1 01 1:2 10 1:4 11 1:4 1) previous memory controller document ation uses the term ?page? to refer to a ?row?. where possible this has been changed to reflect the more commonly used term ?row?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-119 v1.1, 2011-03 ebu, v1.9 banks is done prior to initiating external memory accesses (see ?sdram bank management? on page 15-131 ). 15.18.6 supported sdram commands table 15-39 lists the supported sdram commands , how they are triggered and which signals are activated:- table 15-39 supported sdram commands command event cke (n-1) cke (n) cs ras cas rd/ wr see section 15.18.17 for memory controller pins a12 1) a11 a10 a (9:0) ba (1:0) device deselect region not sel?ted h-h------- nop idleh-lhhh---- bank activate open a closed bank h- l l hhvalid address read read access h- lhlhvalid addr lvalid address write write access h- lhllvalid addr lvalid address read with autoprecharge read access h- lhlhvalid addr hvalid address write with autoprecharge write access h- lhllvalid addr hvalid address precharge selective bank or row miss h - l l h l - l - bank precharge all refresh is due or going into power down h- llhl- h - - www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-120 v1.1, 2011-03 ebu, v1.9 15.18.7 sdram device size the memory controller supports sdram?s with the following sizes:- ? size 1) : 64mbit, 128mbit, 256mbit, 512mbit and 1gbit. autorefresh refresh is due, after precha rge all is done hhlllh ---- self refresh entry going into power down after precha rge all is done hllllh ---- self refresh exit coming out of power down lhh------- mode register set during initializ ation h- llllvalid mode (see register ebu_sdrmod) 00 b extended mode register set during initializ ation h- llllvalid mode (see register ebu_sdrmod) 10 b 2) 1) a12 is required by larger memories 2) 10 b is default value for sdram. this can be changed using the ebu_sdrmod . xba field 1) in addition verified support is limited to specific s dram device geometries (number of banks and row size). support for other sizes/geometries may be possible but this has not been verified. table 15-39 supported sdram commands (cont?d) command event cke (n-1) cke (n) cs ras cas rd/ wr see section 15.18.17 for memory controller pins a12 1) a11 a10 a (9:0) ba (1:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-121 v1.1, 2011-03 ebu, v1.9 15.18.8 power up sequence during power-up the sdram should be initialized with the proper sequence. this includes the requirement of bringing up the vdd, vddq and the stable clock (minimum 200 s before any accesses to sdram) and cs remains inactive. 15.18.9 initialization sequence sdrams must be initialised before being used. application of power must be followed by 200 s pause (timed by software) with a stable clock. then a precharge all banks command must be issued. following this, the device must go through auto refresh cycles (the number of refresh commands is programmable through crfsh in sdrmcon registers and the number of nop cycles in between is programmable through crc ). at the end of it, the mode register must be programmed through the address lines. following that some number of nop cycles programmable through crsc in ebu_sdrmcon. note: this sequence will be referred to as a "c old start",and is nec essary when both the memory and the memory cont roller have just had power applied. conversely a "warm start" will be required when the memory controller has just been powered up but data has been retained in the extern al memory by the use of self refresh mode. the sdram controller will power up with the sdram clock disabled and cke high. care must be taken during software configuration of memory controller to ensure the correct sdram initialisation sequence is generated for both cold start and warm start. 15.18.9.1 cold start initialisation the recomended sequence for memory controller register initialisation after a cold start when using sdram devices is as follows:- 1. if the ebu is in ?no bus? arbitration mode, write to ebu_modcon to switch to an arbitration mode which allows external bus accesses 2. write to buscon to define which region has sdram connected and the required divide ratio for the sdram clock. 3. write to ebu_sdrmcon to configure the controller for the attached sdram device(s) and to enable the sdram clock. ( sdcmsel = 0 b and clkdis =0 b .) 4. initialise all other memory controller registers except sdram specific registers (i.e. other than those listed below). 5. wait for 200 s (or the appropriate initialisation delay required by the attached device) 6. write to ebu_sdrmod with the " coldstart " bit set to precharge tall banks in he device, perform the required refresh commands and write the mode register values to the sdram mode register. 7. write to ebu_sdrmref to configure refresh rate. (see ?refresh cycles? on page 15-133 .) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-122 v1.1, 2011-03 ebu, v1.9 figure 15-41 sdram initialization the sequence is triggered by a write to the sdram mode register sdrmod. a device attached to a region having agen in busconx set to ?1000 b ? will be configured with the mode from sdrmod. while this sequence is being executed, sdrmbusy flag in the sdrmstat status register will be set accordingly. note: as no other accesses are permitted in the current implementation while the sdram initialisation sequence is running, it will not be possible to poll the sdrmbusy bit at ?1? unless there has been a failure in the controller logic. the user has to make sure that the sdram is programmed in the following way: csx rd (not connected to sdram) rd/wr ad bus initialization bc(3:0) ebu_clk a(10) ras cas a(15:11) precharge all banks nop (repeated crp times) refresh don?t care don?t care don?t care nop (repeated crc times) refresh nop (repeated crc times) a programmable number ( crfsh ) of re- fresh sequences will be performed mode register set nop (repeated crsc times) mode mode mode dont care dont care dont care a(9:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-123 v1.1, 2011-03 ebu, v1.9 the memory controller uses the cas latency value and burst length to adjust the burst read timing. all other fields have no influ ence on the memory controller, which means only a single value is accepted for those fields. the complete initialization sequence described will only be issued on the first write (since reset) to the ebu_sdrmod register with the coldstart field set to logic ?1?. on subsequent writes with the coldstart field set to logic ?1?, the sdram device does not need to be initialized, so a simple mode register set command can be issued to refresh the contents of the registers in the sdram. a precharge-all command needs to be issued to the sdram before this can happen. an initialisation sequence will write to both the mode register and the extended mode register (if the extended mode register has been enabled). a write to the ebu_sdrmod register with the coldstart cleared will update the ebu register and will also write to the config registers of the sdram but will not execute the refresh cycles which are part of the full initialisation required at cold start. 15.18.9.2 warm star t initialisation the recomended sequence for memory controller register initialisation after a warm start when using sdram devices requires a pull- down resistor on the cke pin and is as follows: 1. if the ebu is in ?no bus? arbitration mode, write to ebu_modcon to switch to an arbitration mode which allows external bus accesses table 15-40 sdram mode register setting field value meaning sdrmod position corresponding address pins burst length "100" ?011? ?010? ?001? "000" bursts of length 16 bursts of length 8 bursts of length 4 bursts of length 2 bursts of length 1 burstl [2:0] a[2:0] burst type ?0? sequential bursts btyp [3] a[3] cas latency ?001? ?010? ?011? ?1xx? reserved latency 2 latency 3 reserved caslat [6:4] a[6:4] operation mode all ?0? burst read and burst write opmode [13:7] a[12:7] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-124 v1.1, 2011-03 ebu, v1.9 2. write to ebu_busrcon to define which region has sdram connected and the required divide ratio for the sdram clock. 3. write to ebu_sdrmcon to configure the controller for the attached sdram device(s) and to enable the sdram clock. ( sdcmsel =0 b and clkdis =0 b .) 4. write to ebu_sdrmref to configure refresh rate. 5. all other memory controller registers e xcept sdram specific registers (i.e. other than those listed below). 6. write to ebu_sdrmod with the " coldstart " bit cleared to update the mode register values. the sdram will be taken out of self-refresh when step two is completed. auto-refresh by the ebu will start at the completion of step 4 when the refresh counters in the sdram controller expire. care should be taken when setting the registers to ensure that the maximum refresh period is not exceeded. 15.18.10 mobile sdram support mobile sdrams include an ?extended mode register?. this is accessed using a similar mechanism to the existing pc-133 mode register but with an additional select code on the sdram device ba pins. the ebu_sdrmod . xba bits are used to select ?mobile? sdram support for each of the sdram devices. if this field is non-zero, then the extended mode register will be automatically written during the initialization phase (immediately after the ?standard? mode register write). in addition writes to the extended mode register(s) will be triggered by writes to the ebu_sdrmod register (i.e. whenever the ?standard? mode register is written). the ebu_sdrmod . xopm bit-field is used to program the value that is to be written to the extended mode register. the ebu_sdrmod . xba bit-field is used to program the logic levels asserted on the device ba(1:0) pins (i.e. to program the specific command used to access the extended mode register). note: in order to cater for possible future device variations the memory controller allows the user to select the logic levels issu ed on the ba(1:0) pins during an extended mode register. care should be taken in programming this bit field since it is possible to generate an unwanted ?standard ? mode register write by use of this bit field. 15.18.11 burst accesses the memory controller supports sdram burst lengths of 1, 2, 4, 8 and 16. bursts of other lengths are supported but are implem ented using data-masking. burst length 16 is currently not supported by available sdr memories. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-125 v1.1, 2011-03 ebu, v1.9 15.18.12 short burst accesses and byte writes the memory controller can be configured to generate sdram bursts lengths of either one, two, four, eight or sixteen via the ebu_sdrmod. burstl bit fields. when configured for burst lengths of four or eight the interface will use data masking to support shorter write accesses. however, when configured for a burst length of one data masking is not used. figure 15-42 shows how short burst write accesses are handled. during the write access data masking is activated (with zero clock latency) to prevent unwanted write operation. data masking is activated through the bc x outputs (connected to dqm on the sdram device) during a write cycle. figure 15-42 short burst write access through data masking the figure shows how a two beat burst write is translated to an eight beat burst write with data masking. during the first two data cycles (c5 and c6) the bc0 and bc1 outputs are driven low to cause the sdram device to write the required data. in cycle c7 the bc0 and bc1 outputs are driven high to mask subsequent data writes. when performing byte writes, the dqm signals on bc[3:0] signals are used to mask the byte lines not required for the write in progress. 15.18.13 sdram addressing scheme sdram devices use a multiplexed address issued as ?bank?, ?row? and ?column? addresses. the bank address is used to qualify row and column addresses and is used to divide the addressed memory into physically indpendent regions. an sdram bank will have its own sense amplifiers and row buffer which operate independently of the sense amplifiers and row buffers of the other banks in the device. action sdram d dqm (bcx) sdram a ba nop write nop c1 c2 c3 c4 c5 c6 c7 c8 c9 @dr @dc d0 @dr nop c10 c11 c12 c13 c14 x nop nop nop nop nop d1 0 3 @dr x www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-126 v1.1, 2011-03 ebu, v1.9 the row address determines which row is bei ng accessed within a bank and is placed on the bus during a ?bank activate command?. the bank activate command loads to contents of the row into one of the row buffers of the sdram device. once in the row buffer it can be modified by write commands or transferred to the memory controller by read commands. the row buffer used is determined by the bank address bits. the column address determines which location is being accessed within a row. the column address is placed on the bus during read or write commands. since the number of rows per bank and the row sizes can differ from one sdram device to another it is necessary to provide a programmable address multiplexing scheme. selection of the multiplexing scheme is via the ebu_sdrmcon . awidth and ebu_sdrmcon . bankm bit-fields. the sri address (a sri ) is mapped to the sdram as follows: ?a sri (n:0) are used as the column address, where n is defined using the awidth field. see ?column address multiplexing? on page 15-127 ?a sri (m-1:n+1) are used as the row address, where m is defined using the bankm field. see ?row address multiplexing? on page 15-128 ?a sri (m+1:m) are used as the bank address. see ?bank address multiplexing? on page 15-126 15.18.14 bank address multiplexing a bank address is always issued whenever either a row or column address is issued. as a result the bank address multiplexing must be the same regardless of whether a row or column address is being issued. note: the memory controller uses it?s addr ess output pins to select the bank being accessed (rather than having dedicated bank select outputs). the sdram bank select pin(s) (ba[1:0]) must be connected to the memory controller a[15:14] address pins. the ebu_sdrmcon . bankm bit-field must be set correctly to ensure that they are driven by the appr opriate sri address (according to the sdram geometry). the "ebu_sdrmcon. bankm " (bank mask) bit-field must be set to the appropriate value to set the sri address bit range used to detect which bank is being accessed. the value to be written to this bit-field is de termined by the device size setting (see ?sdram device size? on page 15-120 ) and the number of banks in the device. ? when the device has 2 banks then the " bankm " value must be set to include the most significant address bit of the sri address range occupied by the sdram device (i.e. region) - see table 15-45 and table 15-46 . ? when the device has 4 banks then the "bankm" value must be set to include the most significant two address bits of the sri address range occupied by the sdram device (i.e. region) - see table 15-45 and table 15-46 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-127 v1.1, 2011-03 ebu, v1.9 the following settings must be used: 15.18.15 column address multiplexing when a column address is issued: ? the most significant memory controller address outputs (a[27:16]) are driven with '0' (zero). ? the least significant ten address outputs (a[9:0]) are driven with the (correctly aligned) column address. this address alignment is a one bit right shift of the sri address if the sdram is 16 bit or a two bit shift if the sdram is 32 bit. this address alignment is performed according to the device row size specified by the "awidth" bit-field and the ?portw? field (see table 15-42 ). note that all 10 possible column address lines are always driven regardless of the row size of the device. superfluous address bits will be ignored by the attached memory ? address output ten (a[10]) is driven with a ?command? value (used by the sdram in conjunction with the other control signals to determine which command is to be executed. ? the address outputs (a[15:14]) are driven with the bank address signals, ba[1:0] (see ?bank address multiplexing? on page 15-126 ). the "ebu_sdrmcom. awidth " bit-field sets row size of the attached memory and therefore the number of address bits the memory device require for the column address. the value to be written to this bit-field is as follows: table 15-41 ? bankm ? selection ? bankm ? setting sri address bits used for ba[1:0] comment 0 none reserved - do not use (default after reset). 1a sri [21 to 20] bank size = 8mbit 2a sri [22 to 21] bank size = 16mbit 3a sri [23 to 22] bank size = 32mbit 4a sri [24 to 23] bank size = 64mbit 5a sri [25 to 24] bank size = 128mbit 6a sri [26 to 25] bank size = 256mbit. 7a sri [27 to 26] not supported for sdram/ddram www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-128 v1.1, 2011-03 ebu, v1.9 15.18.16 row address multiplexing when a row address is issued as follows:- ? the most significant memory controller address outputs not required by the sdram (a[27:16]) are driven with '0' (zero). ? a[15:14] are driven with the bank address signals, ba[1:0] ? the least significant fourteen address outputs (a[13:0]) are driven with the correctly aligned row address. this address alignment is performed according to the device row size specified by the "awidth" bit-field and the ?portw? field (see table 15-44 ). note that all 14 possible row address lines are always driven regardless of the number of rows in the device. superfluous address bits will be ignored by the attached memory. during the issue of a row address the following address multiplexing is used:- table 15-42 selection of address multiplexing awidth row size 16 bit dram portw ="01" 32 bit dram portw ="11" 00 b reserved; do not use - - 01 b 256 words a sri (8:0) (512 bytes) a sri (9:0) (1024 bytes) 10 b 512 words a sri (9:0) (1024 bytes) a sri (10:0) (2048 bytes) 11 b 1024 words a sri (10:0) (2048 bytes) a sri (11:0) (4096 bytes) table 15-43 column address generation for sdram/ddram 16 bit, portw ="01" address generation (at memory controller pins) 32 bit, portw ="11" address generation (at memory controller pins) a[27:16] = ?0? a[15:14] = ba[1:0] a[10] = command a[9:0] = a sri [10:1] a[26:16] = ?0? a[15:14] = ba[1:0] a[10] = command a[9:0] = a sri [11:2] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-129 v1.1, 2011-03 ebu, v1.9 15.18.17 supported sd ram configurations the following sdram types can be connected to memory controller: table 15-44 row address generation for 16 bit sdram awidth 16 bit, portw ="01" address generation (at memory controller pins) 32 bit, portw ="11" address generation (at ebu pins) 01 b a[13:0] = a sri [22:9] a[13:0] = a sri [23:10] 10 b a[13:0] = a sri [23:10] a[13:0] = a sri [24:11] 11 b a[13:0] = a sri [24:11] a[13:0] = a sri [25:12] table 15-45 example supported configurations for 16-bit wide data bus sdram portw = 01 b (16-bit) signal mapping memory controller pins unused bits at msb(s) of fields awi dth size mbit add a(15:14) a(13:11) a(10) a(9:0) 1024 64mx 16 row sdram ba(1:0) ra(13:11) ra(10) ra(9:0) 11 a sri signals (26:25) (24:22) (21) (20:11) col sdram ba(1:0) cmd ca(9:0) a sri signals (26:25) cmd (10:1) 512 32mx 16 row sdram ba(1:0) ra(12:11) ra(10) ra(9:0) 11 a sri signals (25:24) (23:22) (21) (20:11) col sdram ba(1:0) cmd ca(9:0) a sri signals (25:24) cmd (10:1) 256 16mx 16 row sdram ba(1:0) ra(12:11) ra(10) ra(9:0) 10 a sri signals (24:23) (22:21) (20) (19:10) col sdram ba(1:0) cmd ca(8:0) a sri signals (24:23) cmd (9:1) 128 8mx 16 row sdram ba(1:0) ra(11) ra(10) ra(9:0) 10 a sri signals (23:22) (21) (20) (19:10) col sdram ba(1:0) cmd ca(8:0) a sri signals (23:22) cmd (9:1) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-130 v1.1, 2011-03 ebu, v1.9 64 16mx 4 1) row sdram ba(1:0) ra(11) ra(10) ra(9:0) 11 a sri signals (24:23) (22) (21) (20:11) col sdram ba(1:0) cmd ca(9:0) a sri signals (24:23) cmd (10:1) 8mx8 2) row sdram ba(1:0) ra(11) ra(10) ra(9:0) 10 a sri signals (23:22) (21) (20) (19:10) col sdram ba(1:0) cmd ca(8:0) a sri signals (23:22) cmd (9:1) 4mx 16 row sdram ba(1:0) ra(11) ra(10) ra(9:0) 01 a sri signals (22:21) (20) (19) (18:9) col sdram ba(1:0) cmd ca(7:0) a sri signals (22:21) cmd ca(8:1) 16 4mx4 3) row sdram ba(0) 4) ra(10) ra(9:0) 11 a sri signals (22) (21) (20:11) col sdram ba(0) cmd ca(9:0) a sri signals (22) cmd (10:1) 2mx8 5) row sdram ba(0) 6) ra(10) ra(9:0) 10 a sri signals (21) (20) (19:10) col sdram ba(0) cmd ca(8:0) a sri signals (21) cmd (9:1) 1mx 16 row sdram ba(0) 7) ra(10) ra(9:0) 01 a sri signals (20) (19) (18:9) col sdram ba(0) cmd (8:1) a sri signals (20) cmd (8:1) 1) deprecated, 4 devices in parallel needed to make a 16mx16 configuration 2) 2 devices in parallel needed to make an 8mx16 configuration 3) deprecated, 4 devices in parallel needed to make a 4mx16 configuration 4) 2 bank device. accessing device with a sri (23) set will cause page tag corruption and access errors 5) 2 devices in parallel needed to make an 2mx16 configuration 6) 2 bank device. accessing device with a sri (22) set will cause page tag corruption and access errors table 15-45 example supported configurations for 16-bit wide data bus (cont?d) sdram portw = 01 b (16-bit) signal mapping memory controller pins unused bits at msb(s) of fields awi dth size mbit add a(15:14) a(13:11) a(10) a(9:0) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-131 v1.1, 2011-03 ebu, v1.9 notes: ? ra: row address ? ba: bank select (msb of row address) ? ca: column address ? cmd: auto pre-charge command is currently not supported ? areas in shades are not recommended for sdram configurations, in order to minimize loads on the pads. 15.18.18 sdram bank management the ebu maintains a page tag register for each bank of the sdram device. this is updated with the row tag of the opened page when a ?bank activate? occurs. it is flagged as valid every time a row is opened in the bank and invalidated when the row is precharged (the bank is ?closed?). 7) 2 bank device. accessing device with a sri (21) set will cause page tag corruption and access errors table 15-46 example supported configurations for 32-bit wide data bus sdram portw = 11 b (32-bit) signal mapping memory controller pins unused bits at msb(s) of fields awi dth size mbit add a(15:14) a(13:11) a(10) a(9:0) 1024 32mx32 row sdram ba(1:0) ra(12:11) ra(10) ra(9:0) 11 a sri signals (26:25) (24:23) (23) (21:12) col sdram ba(1:0) cmd ca(9:0) a sri signals (26:25) cmd (11:2) 512 16mx32 row sdram ba(1:0) ra(12:11) ra(10) ra(9:0) 10 a sri signals (25:24) (23:22) (21) (20:11) col sdram ba(1:0) cmd ca(8:0) a sri signals (25:24) cmd (10:2) 256 8mx32 row sdram ba(1:0) ra(11) ra(10) ra(9:0) 10 a sri signals (24:23) (22) (21) (20:11) col sdram ba(1:0) cmd ca(8:0) a sri signals (24:23) cmd (10:2) 128 4mx 32 row sdram ba(1:0) ra(11) ra(10) ra(9:0) 01 a sri signals (23:22) (21) (20) (19:10) col sdram ba(1:0) cmd ca(8:0) a sri signals (23:22) cmd (9:2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-132 v1.1, 2011-03 ebu, v1.9 the ebu contains four page tag registers. this allows devices with up to four banks to be supported. the "ebu_sdrmcon. awidth " bit-field is used to set the lower bound of the sri address range of the page tag. the upper end of the address range is determined by the bankm setting. the row tag is the address range between the most-significant column address width as determined by awidth and the least significant bank address bit as determined by bankm . when a read or write transaction is address ed to the sdram, the bank address bits will decoded from the sri address. this will be used to select the appropriate page tag. if the page tag is valid (bank hit) and the row tag of the current access matches the row tag stored in the page tag register, then a ?row hit? will be flagged. the other options, invalidated page tag regi ster (bank miss) and unmatched page tag (row miss) are used to determine the necessary controller actions needed to complete the access. 15.18.18.1decisions over ?row hit? when a row hit occurs, the memory controller can continue the access operation using data already in the sdram row buffer and without updating the stored page tag. the absence of a ?row hit? can result in several other activities. ? if the absence of a ?row hit? is due to the bank being accessed not having an open row (?bank miss?), then the memory controller does not have to issue a precharge operation but can activate the bank, update the appropriate page tag to reflect the new bank status (i.e. to ?open? with the specified row address) and continue the access operation. ? if a ?row miss? occurs without a ?bank miss?, then the memory controller has to close the open row in the bank being accessed, (i.e. do a precharge). this is then followed by re-activating the bank, updating the appropriate page tag to reflect the new bank status (i.e. ?open? with the new page address) and continuing the access operation. 15.18.19 banks precharge the system is required to precharge a bank under one of the following conditions: 1. when the next access to a bank is to a different row to the previous access within the bank, the affected bank will be selectively precharged to enable the new row to be opened. this is triggered as detailed in ?bank address multiplexing? on page 15-126 . 2. when an sri request cannot be completed before the row active time t ras max is due, then the bank must explicitly be closed and opened again for the current request. since t ras max (of the order of 100 s) is usually much greater compared to the refresh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-133 v1.1, 2011-03 ebu, v1.9 period (distributed refresh is in order of 15 s for 4096 rows) this is generally fulfilled by systematically carrying out refresh to the sdrams (see ?3? below). 3. all banks must also be pre- charged, when a refresh cycle is due as explained next. see ?refresh cycles? on page 15-133 . 4. all banks must also be pre-charged, prior to issuing self refresh entry command. see ?self-refresh mode? on page 15-133 . 15.18.20 refresh cycles the refresh sequence is controlled by the ebu hardware and is periodically triggered by an internal refresh counter with programmable rate. the rate is set using the erfshc and refreshc fields in the ebu_sdrmref regist er. these fields are combined to create an eight bit value ( erfshc as msbs). this value is then multiplied by 64 and used as the number of ebu_clk cycles between refresh opera tions being requested. all sdram banks will be pre-charged using a single ?precharge all? command before any refresh commnads are issued. after the ?precharge all? command, the ebu will insert nop commands on the external bus to allow the precharge command to be completed by the memory device. the num ber of nops will be determined by the ebu_sdrmcon . crp bitfield. the specific refresh command issued is auto refresh (cbr) command, in which the device keeps track of the row addresses to be refreshed. the number of commands issued for each refresh sequence is programmable through refreshr in ebu_sdrmref . after each refresh command, the ebu will issue nop commands on the external bus to allow time for the device to complete the refresh operation before another command is issued. the number of nops will be determined by the ebu_sdrmcon . crc bitfield. a refresh request has precedence over an sri access to sdram, i.e. if both occur at the same time the refresh sequence is entered and the sri access is delayed. a refresh error occurs when a previous refresh request has not been satisfied and another refresh request occurs. an error flag ( referr ) in the ebu_sdrstat status register will be set accordingly. 15.18.21 self-refresh mode sdram devices provide a self-refresh mode. in this mode the sdram automatically performs internal refresh sequences in response to an on-chip timer. self refresh mode is entry command is asserted with ras, cas, and cke low and we high. in self- refresh mode all external control signals except cke (but including the clock) are disabled). returning cke to high enables the clock and initiates the self-refresh mode exit operation. after the exit command, at least one trc delay is required prior to any access command. this delay can be configured using the ebu_sdrmref . selfrex_dly bitfield. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-134 v1.1, 2011-03 ebu, v1.9 low power sdrams provide additional power saving features such as:- programmable refresh period of the on-chip timer such that the refresh period can be optimised (maximised) by taking the device operating temperature in to account. partial array self-refresh mode such that only selected banks will be refreshed. data written to the non-selected banks will be lost (due to lack of refresh to the bank) after a period defined by t ref . these additional features are programmed by issuing an extended mode register write (see ?mobile sdram support? on page 15-124 ). to activate self-refresh mode, software must write ?1? to bit selfren in ebu_sdrmref register. memory controller will then: 1. precharge all the banks, and 2. issue a self refresh command (see table 15-39 ) to the attached sdram device. in completion of this command all sdram devices will ignore all inputs but cke signal. the read-only bit selfrenst reflects the status of issuing this command. when the command is completed, power-down can be safely entered. the devices would perform low-current self refresh during the power down. when exiting from power-down and before doing any accesses to sdram, software must write ?1? to bit selfrex in ebu_sdrmref registers. memory controller will then assert the cke signal for all the sdram devices to get out of the se lf-refresh mode. the read-only bit selfrexst reflects the completion of this command, upon which an access to sdrams can be performed. two additional fields affect the method the memory controller uses to exit self refresh. 1. after cke is taken high (self refresh exit command), a single nop cycle is generated. the ebu_sdrmref . arfsh field is checked. if set to one a single auto refresh command is output to the memory. 2. after step 1, the ebu_sdrmref . selfrex_dly field is checked. if the field is non- zero, the value in the field is used to generate a sequence of nop instructions to the memory. this allows between 1 and 255 nops to be inserted before the device sees a non-null command. for predictable operation of the device during warm start, both the ebu_sdrmref . arfsh and ebu_sdrmref . selfrex_dly fields should be set to 0 before triggering the warm start. 15.18.22 power down mode in order to reduce standby power consum ption sdram devices provide a power down mode. all banks can optionally be precharged before the device enters power down mode. once power down mode is initiated by holding cke low, all receiver circuits except for clk and cke are gated off. power down mode does not perform any refresh operations in the way that self refresh mode does, therefore to prevent loss of data, the device must not remain in power down mode longer than the refresh period (tref) of www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-135 v1.1, 2011-03 ebu, v1.9 the device. taking the device out of power down to perform autoreresh is handled automatically by the sdram controller. exit from this mode is performed by taking cke ?high?. one clock cycle delay is required for power down mode entry and exit. the memory controller provides automatic support for power down mode via the ebu_sdrmcon.sdcmsel (sdram clock mode select) bit. when this bit is ?0? power down mode will not be used and the sdram clock will always be present at the sdclko pin. when the bit is ?1? the device will automatically be placed into power down mode when there are no sdram accesses pend ing. in this case the sdram clock will only be present during an memory controller-generated sdram access (data, refresh, bank/row open etc) and will be gated off at all other times. when a refresh is required (at the programmed rate) memory controller will automatically take the device out of power down mode, issue the required refresh and will then return the device to power down mode (providing no other sdram accesses are pending following the refresh). by default, the memory controller automatical ly issues the ?pre-charge all? command sequence and closes all pages prior to entry into power down mode (ebu_sdrmcon.pwr_mode set to 00 b ). the memory controller can also be configured to use the auto-precharge option when running a command (ebu_sdrmcon.pwr_mode set to 01 b ) or not to precharge banks at all (active power down mode) with ebu_sdrmcon.pwr_mode set to 10 b . as a final option, "clock stop" power down mode is also supported. in this case, the clock is disabled between accesses with no preparatory command cycles (ebu_sdrmcon.pwr_mode set to 11 b ). the default reset state of memory controller is power down mode disabled (ebu_sdrmcon.sdcmsel = ?0?). note: the programmer should be very careful about the use of this feature as some external devices may require this clock to be running in some modes. there are restrictions within the pc-133 specific ation about when the clock can be disabled, especially if the sdrams are operated in self-refresh mode. a separate field ebu_sdrmref . res_dly is provided to allow a delay to be programmed after exiting the power down mode. this field is the delay, in external clock cycles (nops), after cke is taken high on exiting power down mo de before another command is permitted. an additional bit ebu_sdrmcon.clkdis is provided to allow the clock output to be completely disabled. setting this bit will allow a self refresh exit to be performed to enable cke without starting the clock. 15.18.23 sdram recovery phases www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-136 v1.1, 2011-03 ebu, v1.9 15.18.23.1recovery after sdram command a recovery phase can be programmed to increase the minimum gap between an sdram access and an access to another connected memory. for write cycles, the minimum value for this gap is two periods of the internal clock between last command/data driven and the next access starting (for ddr the gap for data is one cycle). this can be increased by setting the buswap.wrdtacs field to the required number of internal clock cycles. for read accesses, the gap can also be increased using the busrap.rddtacs field in the same way. however, the counter is started when the last read command is issued by the controller and the controller does not permit another device to be accessed until two clock cycles after the last data has been re ad into the read buffers. as the read data is significantly delayed by the latency through the read synchronisation logic (minimum latency is 2 clock cycles cas latency plus 2 clo ck cycles internal latency), setting this for read accesses is unlikely to make a significa nt difference unless very large values are used. 15.18.23.2write recovery time (t wrc ) sdrams require a write recovery time after the last data is written before the next command can be processed. the usual valu e for this is one cycle of the sdram clock and this value is hard coded into the controlling state machine. some devices require more delay and this can be programmed using the wrrecovc field of the buswapx register. values of 0 h or 1 h (corresponding to zero or one cycle of recovery) have no effect because of the hard coded lower limit of one clock cycle of recovery but programming larger values w ill set the number of clock cycles of write recovery time to the number programmed into the field. the programmed value will se t the number of sdram clock (sdclko) cycles of write recovery used rather than the number of ebu_clk cycles. 15.18.24 status register definition the ebu_sdrstat register contains four bits which can be used to interrogate the status of ebu functions critical for sdram accesses. where these bits report an error condition, they will latch at 1 b until reset by writing 0 b to the register bit. 15.18.24.1refresh error ( referr ) the sdram controller will schedule a refresh operation to an attached sdram memory at an interval set by the ebu_sdrmref . refreshr bitfield. the referr bit is set if the scheduled refresh has not occurred by the time the next refresh becomes due. if this error condition occurs, then the refresh operations are not keeping up with the device reaquirements and data loss is likely. this bit latches and must be cleared by software. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-137 v1.1, 2011-03 ebu, v1.9 15.18.24.2sdram controller busy ( sdrmbusy ) this bit is set while the controller is performing the initialisation sequence of an attached memory. it will clear once the initialisation is complete. this bit can be polled to ensure that other ebu functions (such as clock switching) are not performed while an initialisation is in progress. 15.18.24.3sdram read error ( sderr ) the sderr bit is set when the control logic detects an error has occurred transferring data from an attached memory device using the sdram data path. this bit will latch. the bit will set under the following conditions: ? the addressed memory does not respond within sixteen clock cycles of the external bus clock ? the device returns more data than is expected by the controller. ? the device does not return enough data to complete the access. ? fifo bypass mode is enabled and the controller detects that a ddr device is not returning data within half a clock period 15.18.24.4dll drift detected ( drift_warn ) see ?dll drift detector? on page 15-23 . 15.18.25 programma ble parameters the following table lists programmable parameters for sdram accesses. these parameters are only effective when parameter agen (in busconx registers) for a particular memory region is set to "8 d ". table 15-47 sdram access programmable parameters parameter function register address mapping bankm map sri address bits to the bank address bits. ebu_sdrmcon awidth number of address bits to be used for column address ebu_sdrmcon refresh control parameters refreshr number of refresh commands issued during each refresh operation. ebu_sdrmref www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-138 v1.1, 2011-03 ebu, v1.9 erfshc & refreshc number of cycles (multiplied by 64) between refresh operations: 0 : no refresh needed 1 - 255 : refresh period defined ebu_sdrmref arfsh execute auto refresh on exit from self refresh when set to one ebu_sdrmref crfsh number of refresh commands during initialization ebu_sdrmcon sdram timing constraint compliance parameters crc number of nop cycles after a refresh comand before another command can be executed. (device t rfc ) ebu_sdrmcon crcd number of nop cycles between a row and column address (device t rcd ) ebu_sdrmcon crp number of nop cycles after a precharge command before another command can be executed. (device t rp ) ebu_sdrmcon crsc number of nop cycles after a mode register set command before another command can be executed. (device t mrd ) ebu_sdrmcon cras minimmum number of cycles between a row activate and a precharge command to the same row (device t ras minimum) ebu_sdrmcon res_dly delay after exiting power down before permitting any command other than nop (device t xp ) ebu_sdrmref selfrex_dly delay after exiting self refresh before permitting any command other than nop (device t xsr ) ebu_sdrmref wrrecovc recovery time after write command before starting another command, used to meet device t wr parameter ebu_buswap rddtacs recovery time after read command before accessing another region. ebu_busrap wrdtacs recovery time after write command before accessing another region. ebu_buswap table 15-47 sdram access programmable parameters (cont?d) parameter function register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-139 v1.1, 2011-03 ebu, v1.9 sdram device register contents opmode to specify write operation mode: only burst_write is recognized ebu_sdrmod caslat to specify cas latency : 2 or 3 clocks ebu_sdrmod btyp to specify burst operation mode: sequential only ebu_sdrmod burstl to specify burst length: 1,2,4, 8 or 16 ebu_sdrmod xopm value to be written to the extended mode register ebu_sdrmod xba bank address value to be used for extended mode register write ebu_sdrmod sdram status sdrmbusy indicate the busy status of sdram ebu_sdrstat referr indicate a refresh error ebu_sdrstat sderr indicates an error has occurred on an sdram read ebu_sdrstat drift_warn indicates an error has occurred on an sdram read ebu_sdrstat sdram controller mode control pwr_mode sdram controller power savemode ebu_sdrmcon selfren to kick-off a self refresh entry command ebu_sdrmref selfrenst status of self refresh entry command ebu_sdrmref selfrex to kick-off a self refresh exit command ebu_sdrmref selfrexst status of self refresh exit command ebu_sdrmref autoselfr to activate automatic self refresh entry/exit when arbitrating the external bus ebu_sdrmref clock control extclock ratio between internal clock and external memory clock for sdram accesses. ebu_busrap sdcmsel sdram clocking mode - continuous clock or power save enabled ebu_sdrmcon clkdis disable the sdram clock output ebu_sdrmcon table 15-47 sdram access programmable parameters (cont?d) parameter function register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-140 v1.1, 2011-03 ebu, v1.9 15.19 ddram/mobile ddram support support for ddram is in most ways simila r to support for sdram. device command definitions are the same. the major differenc es are necessary to support the generation and latching of data on both clock edges. this section should therefore be read as an extension of chapter 15.18 , sdram interface . additional waveform diagrams can be found in jesd209, low power double data rate (lpddr) sdram standard. the following functionality has been provided to support ddr memory: ? a dll is used to retime the dqs signals for read and write accesses to enable successful data capture. see ?dll operation? on page 15-20 for information on the dll. ? a read data fifo is used to enable data to be successfully transferred to the read buffers after being latched by the ddr generated dqs lines. these functions, and the necessary remapping of interface pins to support the load requirements of the ddr interface, are enabled by configuring the agen field of any ebu_busrcon register to specify a ddr device. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-141 v1.1, 2011-03 ebu, v1.9 figure 15-43 example ddr waveform ddr_clk_n cs[3:0] ddr_clk cas we dqs dq/dqm address amode=b10 address address address* dqs dq/dqm write read address amode=b00 ras c rcd cas2 t ck device ck->dq valid * second address not part of command,shown for timing purpses only www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-142 v1.1, 2011-03 ebu, v1.9 notes on figure 15-43 1. the ddr clock is a differential signal with the positive clock edge defined as the time when a rising edge of ddr_clk crosses a falling edge on ddr_clk_n 2. two different modes for address generation are available. see ?sdram addressing scheme? on page 15-125 for information. 3. cas is shown for a burst length of 4. address for amode=b00 and b01 is shown for burst length 2 to clarify differences in addressing modes. 4. the address will only change if necessary. the final address change shown on the waveforms will therefore only occur if a further access has been pipelined. if no access is pending, the last address will remain on the bus. 15.19.1 ddr mode address outputs there are two options for generating the address outputs to ddr memory. option one is for the address for a ddr memory access to be generated in phase with the rising edge of the ddr device clock. this allows a whole clock cycle of setup for the address but means that the address cannot be incremented every clock cycle without timing violations. this prevents burst lengths of two being used for ddram but is the simplest mode to configure. set ebu_dllcon . amode to 01 b for this mode. as a second option, the ddr addresses can be generated with the same timing as the ddr control signals. this will work if the address line loading is closely matched to the clock signal loading. the exact amount of mismatch that can be tolerated will depend on the implementation and required operating frequency. set ebu_dllcon . amode to 00 b for this mode. 15.19.2 ddram initialization sequence ddrams must be initialised in the same way as sdrams before being used. application of power must be followed by 200 s pause (timed by software) with a stable clock. then a precharge all banks command must be issued. following this, the device must go through auto refresh cycles (the number of refresh commands is programmable through crfsh in sdrmcon registers and the num ber of nop cycles in between is programmable through crc ). at the end of it, the mode register must be programmed through the address lines. following that some number of nop cycles programmable through crsc in ebu_sdrmcon. note: this sequence will be referred to as a "c old start",and is nec essary when both the memory and the memory cont roller have just had power applied. conversely a "warm start" will be required when the memory controller has just been powered up but data has been retained in the extern al memory by the use of self refresh mode. the sdram controller will, by default, power up with the ddram clock disabled and cke high in compliance with the jedec specification jesd209 for mobile ddram. this www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-143 v1.1, 2011-03 ebu, v1.9 is not compatible with jesd79e, the specif ication for standard ddram, which requires cke to be low. 15.19.2.1 cold start initialisation care must be taken during software configuration of memory controller to ensure the correct ddram initialisation sequence is generated for both cold start and warm start. the recomended sequence for memory controller register initialisation after a cold start when using mobile ddram devices requires a pull-up resistor to be attached to the cke pin 1) and is as follows:- 1. if the ebu is in ?nobus? arbitration mode, write to the modcon register to set a valid arbitration mode which allows accesses to external memory. 2. write to the appropriate busrconx to define which region has ddram connected and the required divide ratio for the ddram clock output. 2) 3. for ddr mode, initiali se the dll if required 3) . 4. write to ebu_sdrmcon to configure the controller for the attached ddram device(s) and to enable the ddram clock. ( sdcmsel =0 b and clkdis =0 b .) 5. all other memory controller registers e xcept sdram specific registers (i.e. other than those listed below). 6. wait for 200ms (or the appropriate initialisation delay required by the attached device) 7. write to ebu_sdrmod with the " coldstart " bit set to write the mode register values to the ddram mode register. 8. write to ebu_sdrmref to configure refresh rate. 15.19.2.2 warm star t initialisation the pull-up resistor needed on the cke pin for correct cold start initialisation means that mobile ddram cannot be used with warm start as cke will taken high by the pull up as soon as the ebu is disabled which will in turn take the attached device out of self-refresh mode. the recomended sequence for memory controller register initialisation after a warm start when using ddram devices is as follows:- 1. if the ebu is in ?nobus? arbitration mode, write to the modcon register to set a valid arbitration mode which allows accesses to external memory. 1) the initialisation sequence for standard ddram requires a pull-down resistor on the cke pin but is otherwise the same. 2) the agen field in the appropri ate buswconx register will be set automatically to the same value. 3) the dll is required for ddr if either the internal to external clock ratio is 1:1 or the ebu input clock has an asymmetric duty cycle and the internal to external clock ratio is 1:2 or 1:3. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-144 v1.1, 2011-03 ebu, v1.9 2. write to busrconx to define which re gion has ddram connected and the required divide ratio for the ddram clock. 3. for ddr mode, trigger a lock of the dll if required. 4. write to ebu_sdrmcon to configure the controller for the attached ddram device(s) and to enable the ddram clock. ( sdcmsel =0 and clkdis =0 b .) 5. initialise all other memory controller registers except sdram specific registers. 6. write to ebu_sdrmod with the " coldstart " bit cleared to update the mode register values. 15.19.3 ddr external bus clock generation the frequency of the ddr clock is controlled in the same way as sdram clock generation (see ?sdram external bus clock generation? on page 15-117 ) except that the ebu_busrconx. agen value of 12 d is used as well as 8 d when determining whether a region has a valid device attached. see ?external bus clock generation? on page 15-26 for more information on clocking ddr devices. 15.20 lpddr nvm flash support (jedec 42.4 lpddr-nvm protocol) this section should be read in conjucntion with chapter 15.19 , ?ddram/mobile ddram support? on page 15-140 15.20.1 overview the memory controller can be confgured to support nor flash devices utilising an extended version of the interface protocol used for ddr sdram memories. the variations on the protocol can be summarised as follows: ? no refresh required ? no precharge required ? no pipelining of "row activate" during a running access possible (only one set of sense amps) ? two clock cycles of ras during "row acti vate" due to the smaller row size creating the need to load more row address bits ? longer "row to column delay" requir ed because of longer flash read time ? extra mode register command needed during initialisation. this maps the command registers of the flash into the me mory space at an arbitrary address. ? support for ?status register reads? required. due to the complexity of the initialisation sequence, it is not be possible to boot directly from the lpddr-nvm device. the device initialisation must be handled by code running from the internal flash before accesses are attempted. support for the lpddr-nvm protocol is linked to the support for mobile ddram memory and will therefore enable the ddr mode of the sdram controller when any www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-145 v1.1, 2011-03 ebu, v1.9 agen field is set to 10 d . the memory controller can support one ddram memory and one lpddr- nvm memory simultaneously. a region is configured for accessing lpddr-nvm flash by setting the buscon.agen field to 10 d . pin restrictions on the device do not allow ddr and non-ddr memories to be mixed in the same application unless either extreme care is taken to match the dq/dqs/dqm loading or the maximum operating frequency is reduced to allow for the differential signal skew. 15.20.2 implementation requirements as this lpddr nvm flash protocol is bas ed on the ddram protocol, implementation will be described as deltas to the ddr implementation described in section 15.19 . for a description of options for address generation timing, see section 15.10.4 dll operation . 15.20.3 initialisation as the nor flash does not require prec harge or refresh, the mandatory device initialisation sequence consists of the following operations under the control of the boot rom firmware ? once power has stabilised, drive cke to l ogic ?1?. this will happen as soon as the ebu is enabled by setting ebu_modcon.arbmode to a value other than 00 b . ? configure the dll or set up the ebu_clk to ddr_clk ratio to allow ddr accesses without the dll. ? enable ddr clock. clock frequency on the external bus should be 50 mhz maximum. ? the external bus must then remain in either the deselect or idle command states for 200us. ? write to mode register 11 b to set the dai bit in the internal control register of the memory device. ?wait for t mrd . ? poll the dai bit (see ?status register reads? on page 15-148 ) ? write to mode register 01 b with address 12 h ? wait for tsrr ? issue read command to mode register 01 with address 12 ? check state of dai bit in returned data ? if the dai bit is not cleared, repeat the mode register read ? read the device characterist ics from status register 0 ? write to mode register 01 b with address 11 h ? wait for tsrr ? issue read command to mode register 01 with address 11 ? decode device boot characteristics from returned data www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-146 v1.1, 2011-03 ebu, v1.9 ? program initial values to to ddr flash configuration registers. ? program initial values to the ebu_ddrnmod register based on ?min cl? and ?max bl? values. control can now be code read from the external flash device. this code can optionally reconfigure the ebu parameters for optimally match the attached flash device if this has not been done as part of the initialisation. 15.20.4 additional supported commands the lpddr-nvm specification requires two new commands to be implemented. these commands are signalled to the device by reusing two of the commands from the sdram/ddram protocol. preactivate and acti vate are linked commands used to load an rab (row address buffer) in the memory device. the activate command will also load the memory page selected by the rab into one of the rdbs (row data buffers). the rab and rdb to be used are selected by the bank address used for the preactive and active commands. 15.20.5 normal operating mode normal operating mode is enabled when the ebu_ddrncon . mode field is set to 0 b . this defines the memory as being suitable for ?execute in place? (xip) operation. during normal operation, the memory controller will issue preactive and active commands to load a page of the attached memory into an internal buffer of the memory device from where it can be read. these commands are separated by sufficient clock cycles not to violate t rp for the memory device. th is delay is set by the ebu_ddrncon . crp field. there is then a row to column delay (set with ebu_ddrncon . crcd ) before the column address is issued. the number of addr ess bits required for the column address table 15-48 supported lpddr-nvm commands command event cke (n-1) cke (n) cs ras cas rd/ wr see section 15.20.5 for memory controller pins a(13:0) ba(1:0) preactivate load high address bits into rab h - l l h l address msbs 1) 1) see ?normal operating mode? on page 15-146 for details of address bit mapping. bank address activate load rdb h - l l h h address lsbs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-147 v1.1, 2011-03 ebu, v1.9 is set using the ebu_ddrncon . pagesize field. this is used to inform the memory controller of the page size of the attached memory device. as the lpddr nvm is only assumed to have one set of sense amplifiers a row activate cannot be queued before the row to column delay of a previous active command has expired. the ebu_ddrncon . maxadd field is used to set the size of the device. this performs a similar function to the ebu_sdrmcon . bankm when mapping access addresses to pages in the memroy device. the memory controller will maintain a set of ?page tag? registers. this will allow the memory controller to track the addresses of the four, row data buffers (rdb) in the flash memory. each page tag will be linked to a particular value of the bank address bits used when accessing the device and hence one particular rdb. the ebu_ddrncon . maxadd bitfield is used to determine the most significant address bit used for page comparisons and ebu_ddrncon . pagesize is used to determine the least significant address bit. the memory controller will reuse an rdb under the following condition: ? if an access is to the page that has already been loaded into an rdb, the page tag will be reused, the row activate cycles will be skipped and only the column address will be issued. if the reuse criterion above does not apply , the memory controller will apply a ?least active? algorithm to determine which rdb to use for an access. each page tag register in the memory controller has a counter and an ?active flag? 1) associated with it. this counter will be incremented when an access to the lpddr-nvm occurs unless the access uses the page tag, in which case the counter will be set to zero and the active flag set. in the event of an access not matching an active page tags full address then ? as a first case, a inactive page tag will be used an its associated rdb opened ? otherwise, the page tag with the highest count will be reused if, in either case, more than one page tag matches the condition, then the page tag with the lowest value for bank address will be used. if the page tag to be used already has the correct value for the preactive address bits then the preactive command will be skipped 1) the active flag will only be cleared when an rdb invalidation occurs. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-148 v1.1, 2011-03 ebu, v1.9 15.20.6 status register reads status register reads are a variation on the mode register write commands used for ddram. a mode register write is performed to the device and the next read is then performed on an internal status register of the memory device instead of the memory array. status register reads are controlled by accessing the ebu_ddrnmod2 register. writing to ebu_ddrnmod2 with a bank address value of 01 b (set by the ebu_ddrnmod2 . xba field) and the act bit set will trigger the expected mode register write. the address of the status r egister to be read will be obtained from the xopm field of the ebu_ddrnmod2 register. this defines a(11:0) of the external address bus. bits (13:12) are always set to 00 b . table 15-49 a sri and ca to sda bit mapping(16 bit port width) sda bit 1) 1) the jedec standard allows for memories of up to 16 gbytes. this implementation only supports memories up to 1 gbyte requiring a(28:0) of the internal address com- mand 1514131211109876543210 a sri pre- active ba (1:0) - - - 28 27 26 25 24 23 22 21 20 19 18 active - 171615141312111098765 ca(n) read/ write ba (1:0) - 13121110987654321 table 15-50 a sri and ca to sda bit mapping(32 bit port width) sda bit 1) 1) the jedec standard allows for memories of up to 16 gbytes. this implementation only supports memories up to 1 gbyte requiring a(28:0) of the internal address com- mand 1514131211109876543210 a sri pre- active ba (1:0) - - - - 28272625242322212019 active - 1817161514131211109876 ca(n) read/ write ba (1:0) - 141312111098765432 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-149 v1.1, 2011-03 ebu, v1.9 however as a write to mode register 01 is used as a command to prepare the device for a status register read, the write will be followed (after a delay set by the csrr field in the ebu_ddrncon register) by a read operation using the same value on the address bus as the write. the data returned by this read will be placed in the ebu_ddrnsrr . srrdata0 field if a single device is connected or both ebu_ddrnsrr . srrdata0 and ebu_ddrnsrr . srrdata1 if two 16 bit devices are connected in parallel in a 32 bit configuration. it is not normally permitted for other commands to be pipelined to the lpddr nvm before the status register read command has completed. this delay is set by the ebu_ddrncon . csrs field. while a status register operation is in progress, the act bit will remain set. once the operation has completed, the bit will be cleared by hardware. 15.20.7 discrete mode register writes when operating an lpddr_nvm memory it is necessary to perform writes to mode registers which are not connected to device initialisation. these discrete mode register writes are using to configure the device programming interface. mode register 11 b is available for these functions and is accessed by writing to the ebu_ddrnmod2 register with the act bit set and the xba field set to 11 b . the data to be written to the register is contained in the xopm field of the ebu_ddrnmod2 register. this field contains twelve bits of data and will be output on a[11:0] of the external address bus. the unused bits of the external address bus will be set to 0 b . 15.20.8 page preload this register has two uses. the first applies when ebu_ddrncon . mode is set to 1 b . in this case, the memory is defined as being unsuitable for ?execute in place? xip operation and therefore needs to be treated in the same way as a nand flash memory. if a value is written to the ebu_ddrnprld register, the contents will be treated as the memport address of a memory page to be preloaded into the device buffer. the memory controller will issue the preactive and active command sequence as detailed in ?normal operating mode? on page 15-146 , but will not expect any data to be returned and so will not issue the final read command. the page tags in the memory controller will be updated to show that the page is available. this is intended to enable support for a nand flash memory with the lpddr nvm type interface. the proposed method of access would be to issue the page load and then wait for the device t rcd to expire. accesses to the preloaded page could then be issued. it would be the responsib ility of software to ensure that a premature access to the page was not accidentally issued by either polling the device status register or using a dead reckoning timer to measure the page load time of the device. accesses to an unopened page will result in an error being returned on the internal bus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-150 v1.1, 2011-03 ebu, v1.9 if the csa function is enabled for the lpddr-nvm, then bit 28 of the register (corresponding to a memport (28) will be monitored and used to determine which of the two lpddr-nvm memories is affected by the preload operation. it is invalid for two rdbs to have overlapping addresses. the memory controller hardware will detect if the address to be preloaded overlaps another page tag other than that targetted by the page load operation and prevent the page load from taking place. this will not be flagged to the controlling software as the requested page is already available. for the second use, see ?overlay window control? on page 15-150 . 15.20.9 page tag control page tags are set active when first used. there are some circumstances in which the contents of the rdbs in the memory are no longer guaranteed to be an accurate copy of the device contents and in these cases the rdbs need to be invalidated. this is done by resetting the page tags to inactive. the next accesses to the memory will then force a reload of the rdbs from the memory contents. the following conditions will automatically invalidate the page tags: ? writing to any of mode registers 00 b , 01 b or 11 b either by triggering an initialisation sequence (write to ebu_ddrnmod ) or by a mode register write (write to ebu_ddrnmod2 ). the page tags can be invalidated under software control by writing 0 b to the ebu_ddrntagx (x=0-3) . active bitfield of the appropriate register. writing 1 b to this bit field has no effect and will not activate an inactive page tag. this operation does not invalidate the rdb in the memory device 15.20.10 overlay window control the overlay window is controlled using mode register 11 b in the memory device. mode register 11 b can be accessed using the ebu_ddrnmod2 register to trigger discrete mode register writes (see ?discrete mode register writes? on page 15-149 ). once enabled, the overlay window occupies part of the memory device address space and can be written to. note that writes to the overlay window are via the rdbs and that the rdb will therefore need to be flushed to transfer the data to the overlay window. if the memory device supports the optional flush bit in mode register 11, then the data can be flushed to the overlay window by using a discrete mode register write to write 1 to the flush bit. otherwise, the flush operation can be triggered by sending an active command to the appropriate rdb. to do this, use the ebu_ddrnprld register to trigger the command sequence using the ebu_ddrnprld . ba field to select the correct rdb. which rdb (or rdbs) is currently allocated to the overlay window address space can be determined by polling the ebu_ddrntagx (x=0-3) registers. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-151 v1.1, 2011-03 ebu, v1.9 15.20.11 clearing the read fifo error flag writing to the ebu_ddrncon will clear the read fifo error flag in the sdram status register. this is in addition to a write to the ebu_sdrmcon register clearing the flag. 15.20.12 lpddr-nvm access programmable parameters the following parameters can be used to configure accesses to lpddr-nvm memories. table 15-51 lpddr-nvm access programmable parameters parameter function register maxadd highest order address bit used by the nvm memory ebu_ddrncon pagesize size of a page in the nvm memory ebu_ddrncon crsc number of nop cycles after a mode register set command ebu_ddrncon crp number of nop cycles between a preactive and active command ebu_ddrncon csrs number of delay cycles between a status register read and the next command on the bus ebu_ddrncon csrr number of delay cycles between a mode register write to mr01 and the associated status register read ebu_ddrncon crcd number of nop cycles betw een a row activate and a column address ebu_ddrncon mode operating mode for attached memory. either xip (execute in place) or software controlled page load (nand mode) ebu_ddrncon xba bank address value to be used for an extended mode register access ebu_ddrnmod opmode to specify write operation mode: only burst_write is recognized ebu_ddrnmod xopm value to be written to the extended mode register ebu_ddrnmod caslat cas latency setting to be used for device accesses ebu_ddrnmod btyp to specify burst operation mode: sequential ebu_ddrnmod burstl to specify burst length: 4, 8 or 16 ebu_ddrnmod xba bank address value to be used for an extended mode register access to the second extended mode register. ebu_ddrnmod2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-152 v1.1, 2011-03 ebu, v1.9 xopm value to be written to the second extended mode register ebu_ddrnmod2 ba bank address to be used for page preloaded ebu_ddrnprld page internal, byte address of page to be preloaded ebu_ddrnprld table 15-51 lpddr-nvm access programmable parameters (cont?d) parameter function register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-153 v1.1, 2011-03 ebu, v1.9 15.21 ebu registers [cover refid=register_map_24] this sectio n describes the registers and programmable parameters of the ebu. all these registers can be read in user mode, but can only be written in supervisor mode. all registers are reset by the module reset. table 15-52 registers address space -flash registers module base address end address note ebu f800 0000 h f800 03ff h - table 15-53 registers overview ebu control registers register short name register long name offset address access mode description see read write ebu_clc ebu clock control register 0000 h u, sv, 32, 64 sv, 32, 64, be page 15-156 ebu_modcon ebu configuration register 0004 h u, sv, 32, 64 sv, 32, 64 page 15-158 ebu_modid ebu module id register 0008 h u, sv, 32, 64 sv, 32, 64 page 15-200 ebu_usercon ebu test/control configuration register 000c h u, sv, 32, 64 sv, 32, 64 page 15-199 ebu_extboot ebu external boot control register 0010 h u,sv, 32 sv, 32 1) page 15-161 reserved 0014 h be be ebu_addrsel0 ebu address select register 0 0018 h u, sv, 32, 64 sv, 32, 64 page 15-163 ebu_addrsel1 ebu address select register 1 001c h u, sv, 32, 64 sv, 32, 64 page 15-163 ebu_addrsel2 ebu address select register 2 0020 h u, sv, 32, 64 sv, 32, 64 page 15-163 ebu_addrsel3 ebu address select register 3 0024 h u, sv, 32, 64 sv, 32, 64 page 15-163 ebu_busrcon0 ebu bus configuration register 0 0028 h u, sv, 32, 64 sv, 32, 64 page 15-165 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-154 v1.1, 2011-03 ebu, v1.9 ebu_busrap0 ebu bus access parameter register 0 002c h u, sv, 32, 64 sv, 32, 64 page 15-172 ebu_buswcon0 ebu bus configuration register 0 0030 h u, sv, 32, 64 sv, 32, 64 page 15-169 ebu_buswap0 ebu bus access parameter register 0 0034 h u, sv, 32, 64 sv, 32, 64 page 15-175 ebu_busrcon1 ebu bus configuration register 1 0038 h u, sv, 32, 64 sv, 32, 64 page 15-165 ebu_busrap1 ebu bus access parameter register 1 003c h u, sv, 32, 64 sv, 32, 64 page 15-172 ebu_buswcon1 ebu bus configuration register 1 0040 h u, sv, 32, 64 sv, 32, 64 page 15-169 ebu_buswap1 ebu bus access parameter register 1 0044 h u, sv, 32, 64 sv, 32, 64 page 15-175 ebu_busrcon2 ebu bus configuration register 2 0048 h u, sv, 32, 64 sv, 32, 64 page 15-165 ebu_busrap2 ebu bus access parameter register 2 004c h u, sv, 32, 64 sv, 32, 64 page 15-172 ebu_buswcon2 ebu bus configuration register 2 0050 h u, sv, 32, 64 sv, 32, 64 page 15-169 ebu_buswap2 ebu bus access parameter register 2 0054 h u, sv, 32, 64 sv, 32, 64 page 15-175 ebu_busrcon3 ebu bus configuration register 3 0058 h u, sv, 32, 64 sv, 32, 64 page 15-165 ebu_busrap3 ebu bus access parameter register 3 005c h u, sv, 32, 64 sv, 32, 64 page 15-172 ebu_buswcon3 ebu bus configuration register 3 0060 h u, sv, 32, 64 sv, 32, 64 page 15-169 ebu_buswap3 ebu bus access parameter register 3 0064 h u, sv, 32, 64 sv, 32, 64 page 15-175 ebu_sdrmcon ebu, sdram control register 0068 h u, sv, 32, 64 sv, 32, 64 page 15-178 table 15-53 registers overview ebu control registers (cont?d) register short name register long name offset address access mode description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-155 v1.1, 2011-03 ebu, v1.9 access restrictions note: the ebu registers are accessible only through word or double-word accesses. half-word and byte accesses on ebu registers will generate a bus error. accesses ebu_sdrmod ebu, sdram mode register 006c h u, sv, 32, 64 sv, 32, 64 page 15-180 ebu_sdrmref ebu, sdram refresh control register 0070 h u, sv, 32, 64 sv, 32, 64 page 15-183 ebu_sdrstat ebu, sdram status register 0074 h u, sv, 32, 64 sv, 32, 64 page 15-185 ebu_dllcon ebu, dll control register 0078 h u, sv, 32, 64 sv, 32, 64 page 15-187 ebu_ddrncon ebu, lpddr nvm control register 007c h u, sv, 32, 64 sv, 32, 64 page 15-190 ebu_ddrnmod ebu, lpddr nvm mode register 0080 h u, sv, 32, 64 sv, 32, 64 page 15-192 ebu_ddrnmod2 ebu, lpddr nvm extended mode register 0084 h u, sv, 32, 64 sv, 32, 64 page 15-194 ebu_ddrnsrr ebu, lpddr nvm page preload register 0088 h u, sv, 32, 64 sv, 32, 64 page 15-196 ebu_ddrnprld ebu, lpddr nvm page preload register 008c h u, sv, 32 sv, 32 page 15-197 ebu_ddrntag0 ebu, lpddr nvm page tag register 0090 h u, sv, 32, 64 sv, 32, 64 page 15-198 ebu_ddrntag1 ebu, lpddr nvm page tag register 0094 h u, sv, 32, 64 sv, 32, 64 page 15-198 ebu_ddrntag2 ebu, lpddr nvm page tag register 0098 h u, sv, 32, 64 sv, 32, 64 page 15-198 ebu_ddrntag3 ebu, lpddr nvm page tag register 009c h u, sv, 32, 64 sv, 32, 64 page 15-198 - reserved 00a0 h - 03fc h be be 1) the extboot register is only writable when the boot_active flag from the scu is set. table 15-53 registers overview ebu control registers (cont?d) register short name register long name offset address access mode description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-156 v1.1, 2011-03 ebu, v1.9 to a 64bit word only partially populated with accessible registers will cause a bus error. writes to unused address space, or writes to the end init protected clc register will also cause an error . 15.21.1 clock control register, clc ebu_clc ebu clock control register (000 h ) reset value: 0055 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res ebudiva ck div2 ack sync ack ebudiv div2 sync r r r r rw rw rw 1514131211109876543210 res epe res diss disr rrwrrrw field bits type description disr 0rw ebu disable request bit 1) this bit is used for enable/disable control of the ebu. 0 b ebu disable is not requested 1 b ebu disable is requested diss 1r ebu disable status bit diss is always read as 0, as accessing the ebu will automatically enable it. 0 b ebu is enabled (default after reset) 1 b ebu is disabled res 7:2 r reserved read as 0; should be written with 0. epe 8rw endinit protection enable 2) 0 b disable endinit protection of the clc register (default after reset). 1 b enable endinit protection of the clc register. res 15:9 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-157 v1.1, 2011-03 ebu, v1.9 sync 16 rw ebu clocking mode 0 b request ebu to run asynchronously to processor clock and use separate clock source 1 b request ebu to run synchronously to processor (default after reset) div2 17 rw div2 clocking mode 0 b standard clocking mode. clock input selected by sync bitfield (default after reset). 1 b request ebu to run off processor clock divided by 2. ebudiv 19:18 rw ebu clock divide ratio 00 b request ebu to run off input clock 01 b request ebu to run off input clock divided by 2 (default after reset) 10 b request ebu to run off input clock divided by 3 11 b request ebu to run off input clock divided by 4 syncack 20 r ebu clocking mode status 0 b the ebu is asynchronous to the sri bus clock and is using a separate clock source 1 b ebu is synchronous to the sri bus clock (default after reset) div2ack 21 r div2 clocking mode status 0 b ebu is using standard clocking mode. clock input selected by sync bitfield (default after reset). 1 b ebu is running off processor clock divided by 2. ebudivack 23:22 r ebu clock divide ratio status 00 b ebu is running off input clock (default after reset) 01 b ebu is running off input clock divided by 2 10 b ebu is running off input clock divided by 3 11 b ebu is running off input clock divided by 4 res 31:24 r reserved read as 0; should be written with 0. 1) while the disr bit is implemented in the ebu, it connects to the standby logic which will disable the clock tree. standby mode w ill be exited automatically when an attempt is made to access the ebu. 2) this register can be endinit-prot ected after initialization. writ ing to this register in this state will cause the ebu to generate an sri error. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-158 v1.1, 2011-03 ebu, v1.9 15.21.2 configuration register, modcon ebu_modcon ebu configuration register (004 h ) internal boot reset value: 3000 0020 h ebu_modcon ebu configuration register (004 h ) external boot reset value: 3000 0060 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ale bus sta te acc sinh ack acc sinh res ocd s_s usp _dis fas t_s ri fifo _by pas s locktimeout rw rh r rw r rw rw rw rw 1514131211109876543210 timeoutc arb mode arb sync extl ock clk _co mb sdt ri lck abr t sts rw rw rw rw rw rwh rwh r field bits type description sts 0r memory status bit software access to the wait input pin to the ebu. lckabrt 1rwh lock abort this is a status bit which is set when a chip select lock has been cancelled by a pr ogram fetch. the flag is cleared by writing 1 b to the field. see section 15.9.1 0 b lock function is operating normally 1 b lock function has been aborted by processor instruction read from locked device sdtri 2rw sdram tristate 0 b sdram control signals are driven by the ebu when the ebu does not own the external bus. sdram cannot be shared. 1 b sdram control signals are tri-stated by the ebu when the ebu does not own the external bus. the sdram can be shared. note: the signals affected by this setting are cke, sdclko, cas and ras www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-159 v1.1, 2011-03 ebu, v1.9 clk_comb 3rw combined external bus clock burst flash protocol and sdram protocol devices use the same external clock when set. 0 b the sdram and synchronous state machines use clocks on separate pins 1 b both state machines use the clock on bfclko when accessing external memories extlock 4rw external bus lock control allows the external bus arbitration to be locked with the ebu owning the bus. 0 b external bus is not locked after the ebu gains ownership 1 b external bus is locked after the ebu gains ownership arbsync 5rw arbitration signal synchronization control assumed status of the arbitration control signals, breq and hlda 0 b arbitration inputs are synchronous 1 b arbitration inputs are asynchronous, use two resynchronisation flip-flops. arbmode 7:6 rw arbitration mode selection operating mode of the external bus arbitration 00 b no bus arbitration mode selected 01 b arbiter mode arbitration mode selected 10 b participant arbitration mode selected 11 b sole master arbitration mode selected timeoutc 15:8 rw bus time-out control this bit field determines th e number of inactive cycles after the ebu gains ownsership of the external bus before an arbitration time-out occurs and re- arbitration can occur. 00 h time-out is disabled. 01 h time-out is generated after 1 8 clock cycles. ? h ? ff h time-out is generated after 255 8 clock cycles. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-160 v1.1, 2011-03 ebu, v1.9 locktimeou t 23:16 rw lock timeout counter preload value to be preloaded into the timeout counter for the arbitration lock. note: (see section 15.9.1 ) fifo_bypas s 24 rw read mode for sdram/ddr memories 0 b use data fifo for read data (default) 1 b bypass the fifo. see ?fifo bypass mode? on page 15-25 for detailed description. fast_sri 25 rw clock cycles used for sri address decode 0 b use two clock cycles for address decode (default after reset) 1 b use one clock cycle for address decode. see ?address comparison? on page 15-48 for a detailed description. ocds_susp_ dis 26 rw ocds suspend disable the ebu external arbitration will normally be disabled with the ebu owning the external bus while ocds is active. setting this bit will allow external bus arbitration to continue operation. see section 15.11.7 res 27 r reserved write with 0 h accsinh 28 rw access inhibit request prevent any transactions except for processor initiated transfers from accessing the memory regions 0 b accesses enabled 1 b accesses inhibited note: (see section 15.9 ) accsinhack 29 r access inhibit acknowledge 0 b port normal operation possible 1 b port accesses have been inhibited (except processor) note: (see section 15.9 ) field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-161 v1.1, 2011-03 ebu, v1.9 15.21.3 external boot configuration control register, extboot busstate 30 rh external bus state status bit controlled by the arbitration logic (see ?external bus arbitration? on page 15-28 ) reflecting the ownership of the external memory bus. 0 b the ebu does not own the external bus and attached memories cannot be accessed. 1 b the ebu owns the external bus. ale 31 rw ale mode switch the adv output to be an active high ale signal instead of active low adv . 0 b output is adv 1 b output is ale ebu_extboot ebu external boot conf iguration register(00010 h ) reset value: 0000 0001 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ebu cfg res wr 1514131211109876543210 res cfg err cfg end rrhrh field bits type description cfgend 0rh configuration end 0 b configuration fetch is running 1 b configuration fetch has completed or not started cfgerr 1rh configuration fetch error 0 b no error 1 b the configuration fetch has returned a word with all bits set. this indicates an unprogrammed or missing flash field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-162 v1.1, 2011-03 ebu, v1.9 ebucfg 31 w configuration word fetch write 1 b to trigger automatically set the ebu to arbiter arbitration mode and fetch a configuration word from external memory. always reads 0 b res 30:2 r reserved read as 0; must be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-163 v1.1, 2011-03 ebu, v1.9 15.21.4 address select register, addrselx ebu_addrselx (x = 1-3) ebu address select register 1-3 (018 h +x*4 h ) addrsel[3:1] - reset value: 0000 0000 h ebu_addrsel0 ebu address select register 0 (018 h ) addrsel0 - reset value: a000 0001 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 base rw 1514131211109876543210 base altseg mask glo bal cs wpr ot alt en ab reg en ab rw rw rw rw rw rw rw field bits type description regenab 0rw memory region enable 0 b memory region is disabled (default after reset 1) ). 1 b memory region is enabled. altenab 1rw alternate segment comparison enable 0 b altseg is never compared to sri address (default after reset). 1 b altseg is always compared to sri address. wprot 2rw memory region write protect 0 b region is enabled for write accesses 1 b region is write protected. globalcs 3rw combined chip select control controls whether the cscomb output should be asserted for valid accesses to this region. 0 b cscomb not asserted 1 b cscomb asserted www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-164 v1.1, 2011-03 ebu, v1.9 mask 7:4 rw memory region address mask specifies the number of right-most bits in the base address starting at bit 26, which should be included in the address comparison. bi ts [31:27] will always be part of the comparison. altseg 11:8 rw memory region alternate segment alternate segment to be compared to sri address bit [31:28]. base 31:12 rw memory region base address base address to be compared to sri address in conjunction with the mask control. 1) except for addrsel0, regenab in register addrsel0 is 1 b after reset. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-165 v1.1, 2011-03 ebu, v1.9 15.21.5 bus configuration register, busrconx ebu_busrconx (x = 0-3) ebu bus configuration register (028 h +x*10 h ) reset value: 00d3 0040 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 agen res 0 aap wait portw bcgen wai tinv dba ebse ecse rw r rw rw rw rw rwrwrwrw 1514131211109876543210 res naa bfc msel fdb ken res 1 fbb msel fetblen r rwrwrw r rw rw field bits type description fetblen 2:0 rw burst length for synchronous burst defines maximum number of burst data cycles which are executed by memory controller during a burst access to a synchronous burst device. 000 b 1 data access (default after reset). 001 b 2 data accesses. 010 b 4 data accesses. 011 b 8 data accesses. 1xx b reserved. fbbmsel 3rw synchronous burst buffer mode select 0 b burst buffer length defined by value in fetblen (default after reset). 1 b continuous mode. all data required for transaction is transferred in a single burst. reserved 4r reserved 0 b reserved bit always reads ?0?. fdbken 5rw burst flash clock feedback enable 0 b bfclk feedback not used. 1 b incoming data and control signals (from the burst flash device) are re-synchronised to the bfclki input. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-166 v1.1, 2011-03 ebu, v1.9 bfcmsel 6rw burst flash clock mode select 0 b burst flash clock runs continously with values selected by this register 1 b burst flash clock is disabled between accesses naa 7rw enable flash non-array access workaround set to logic one to enable workaround when region is accessed with address bit 28 set. see ?flash non- array access support? on page 15-101 res1 15:8 r reserved 00 h reserved value ecse 16 rw early chip select fo r synchronous burst 0 b cs is delayed. 1 b cs is not delayed. note: (see control of adv & other signal delays during asynchronous accesses and control of adv & control signal delays during synchronous accesses ) ebse 17 rw early burst signal enable for synchronous burst 0 b adv is delayed. 1 b adv is not delayed. note: (see control of adv & other signal delays during asynchronous accesses and control of adv & control signal delays during synchronous accesses ) field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-167 v1.1, 2011-03 ebu, v1.9 dba 18 rw disable burst address wrapping 0 b memory controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. 1 b memory controller always starts any burst access to a synchronous burst device at the address specified by the sri request. any required address wrapping must be automatically provided by the burst flash device. note: care must be taken with the use of this feature. the burst capable device must be programmed to wrap at the appropriate address boundary prior to selection of this mode. ?critical word first read accesses? on page 15-96 waitinv 19 rw reversed polarity at wait 0 b off , input at wait pin is active low (default after reset). 1 b polarity reversed , input at wait pin is active high. bcgen 21:20 rw byte control signal control this bit field selects the timing mode of the byte control signals. 00 b byte control signals follow chip select timing. 01 b byte control signals fo llow control signal timing (rd , rd/wr ) (default af ter reset). 10 b byte control signals follow write enable signal timing (rd/wr only). 11 b sdram access type. signals used for dqm. portw 23:22 rw device addressing mode see table 15-16 and table 15-18 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-168 v1.1, 2011-03 ebu, v1.9 note: when in external boot mode (see page 15-41 ) the reset value of buscon0 is overwritten automatically (subs equent to the release of re set) as a result of the external boot configuration value fetch. wait 25:24 rw external wait control function of the wait input. this is specific to the device type (i.e. the agen field). for asynchronous devices, see ?external extension of the command phase by wait? on page 15-76 for synchronous burst devices, see ?external cycle control via the wait input? on page 15-99 aap 26 rw asynchronous address phase: enables an access mode fo r synchronous memories where the clock is not started until after the address hold phase. 0 b clock is enabled at beginning of access. 1 b clock is enabled at after address phase. res0 27 r reserved, always 0 agen 31:28 rw device type for region see section 15.14.1 programmable device types field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-169 v1.1, 2011-03 ebu, v1.9 15.21.6 bus write configuration register, buswconx ebu_buswconx (x = 0-3) ebu bus write configuration register(030 h +x*10 h ) reset value: 00d3 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 agen loc kcs aap wait portw bcgen wai tinv res ebse ecse rw rw rw rw r rw rw r rw rw 1514131211109876543210 res0 naa res1 fbb msel fetblen rrrrwrw field bits type description fetblen 2:0 rw burst length for synchronous burst defines maximum number of burst data cycles which are executed by memory controller during a burst access to a synchronous burst device. 000 b 1 data access (default after reset). 001 b 2 data accesses. 010 b 4 data accesses. 011 b 8 data accesses. 1xx b reserved. fbbmsel 3rw synchronous burst buffer mode select 0 b burst buffer length defined by value in fetblen (default after reset). 1 b continuous mode. all data required for transaction transferred in single burst res 6:4 r reserved, always reads 0 naa 7r enable flash non-array access workaround set to logic one to enable workaround when region is accessed with address bit 28 set. see ?flash non- array access support? on page 15-101 . mirror of equivalent field in busrcon register. res0 15:8 r reserved 00 h reserved value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-170 v1.1, 2011-03 ebu, v1.9 ecse 16 rw early chip select fo r synchronous burst 0 b cs is delayed. 1 b cs is not delayed. note: (see control of adv & other signal delays during asynchronous accesses and control of adv & control signal delays during synchronous accesses ) ebse 17 rw early burst signal enable for synchronous burst 0 b adv is delayed. 1 b adv is not delayed. note: (see control of adv & other signal delays during asynchronous accesses and control of adv & control signal delays during synchronous accesses ) res1 18 r reserved, always reads 0 waitinv 19 rw reversed polarity at wait 0 b off , input at wait pin is active low (default after reset). 1 b polarity reversed , input at wait pin is active high. bcgen 21:20 rw byte control signal control this bit field selects the timing mode of the byte control signals. 00 b byte control signals follow chip select timing. 01 b byte control signals fo llow control signal timing (rd , rd/wr ) (default af ter reset). 10 b byte control signals follow write enable signal timing (rd/wr only). 11 b reserved. portw 23:22 r device addressing mode see table 15-16 and table 15-17 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-171 v1.1, 2011-03 ebu, v1.9 note: when in external boot mode (see page 15-41 ) the reset value of buscon0 is overwritten automatically (subs equent to the release of re set) as a result of the external boot configuration value fetch. wait 25:24 rw external wait control function of the wait input. this is specific to the device type (i.e. the agen field). for asynchronous devices, see ?external extension of the command phase by wait? on page 15-76 for synchronous burst devices, see ?external cycle control via the wait input? on page 15-99 aap 26 rw asynchronous address phase: enables an access mode fo r synchronous memories where the clock is not started until after the address hold phase. 0 b clock is enabled at beginning of access. 1 b clock is enabled at after address phase. lockcs 27 rw lock chip select enable chip select for automatic locking in the event of a write access 0 b chip select cannot be locked (default after reset). 1 b chip select will be au tomatically locked when written to from the processor data port. agen 31:28 rw device type for region see section 15.14.1 programmable device types field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-172 v1.1, 2011-03 ebu, v1.9 15.21.7 bus read access parameter register, busrapx ebu_busrapx (x = 0-3) ebu bus read access parameter register (02c h +x*10 h ) reset value: ffff ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 addrc aholdc cmddelay extdata extclock rw rw rw rw rw 1514131211109876543210 datac waitrdc rdrecovc rddtacs rw rw rw rw field bits type description rddtacs 3:0 rw recovery cycles between different regions this bit field determines the number of clock cycles of the recovery phase between consecutive accesses directed to different regions or different types of access. see ?recovery phase (rp)? on page 15-67 and ?sdram recovery phases? on page 15-135 0000 b no recovery phase clock cycles available. 0001 b 1 clock cycle selected. ? b ? 1110 b 14 clock cycles selected. 1111 b 15 clock cycles selected. rdrecovc 6:4 rw recovery cycles after read accesses this bit field determines the basic number of clock cycles of the recovery p hase at the end of read accesses. 000 b no recovery phase cl ock cycles available. 001 b 1 clock cycle selected. ? b ? 110 b 6 clock cycles selected. 111 b 7 clock cycles selected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-173 v1.1, 2011-03 ebu, v1.9 waitrdc 11:7 rw programmed wait states for read accesses number of programmed wait states for read accesses. for synchronous a ccesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. 00000 b 1 wait state. 00001 b 1 wait states. 00010 b 2 wait state. ? b ? 11110 b 30 wait states. 11111 b 31 wait states. datac 15:12 rw data hold cycles for read accesses this bit field determines the basic number of data hold phase clock cycles during read accesses. this is used for a limited number of read cycle types. see ?data hold phase (dh)? on page 15-65 . also controls the length of the control hold phase. see ?control hold (ch)? on page 15-66 . 0000 b no recovery phase clock cycles available. 0001 b 1 clock cycle selected. ? b ? 1110 b 14 clock cycles selected. 1111 b 15 clock cycles selected. extclock 17:16 rw frequency of external clock at pin bfclko or sdclko see ?external bus clock generation? on page 15-26 extdata 19:18 rw extended data see burst phase (bp) 00 b external memory outputs data every bfclk cycle 01 b external memory outputs data every two bfclk cycles 10 b external memory outputs data every four bfclk cycles 11 b external memory outputs data every eight bfclk cycles field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-174 v1.1, 2011-03 ebu, v1.9 note: when in external boot mode (see page 15-41 ), the reset value of busap0 is overwritten automatically (subs equent to the release of re set) as a result of the external boot configuration value fetch. cmddelay 23:20 rw command delay cycles this bit field determines the basic number of command delay phase clock cycles. 000 b 0 clock cycle selected. 001 b 1 clock cycle selected. ? b ? 110 b 6 clock cycles selected. 111 b 7 clock cycles selected. aholdc 27:24 rw address hold cycles this bit field determines the number of clock cycles of the address hold phase.. 0000 b 1 clock cycle selected 0001 b 1 clock cycle selected ? b ? 1110 b 14 clock cycles selected 1111 b 15 clock cycles selected addrc 31:28 rw address cycles this bit field determines the number of clock cycles of the address phase. 000 b 1 clock cycle selected 001 b 1 clock cycle selected ? b ? 110 b 6 clock cycles selected 111 b 7 clock cycles selected field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-175 v1.1, 2011-03 ebu, v1.9 15.21.8 bus write access parameter register, buswapx ebu_buswapx (x = 0-3) ebu bus write access parameter register (034 h +x*10 h ) reset value: ffff ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 addrc aholdc cmddelay extdata extclock rw rw rw rw rw 1514131211109876543210 datac waitwrc wrrecovc wrdtacs rw rw rw rw field bits type description wrdtacs 3:0 rw recovery cycles between different regions this bit field determines the number of clock cycles of the recovery phase between consecutive accesses directed to different regions or different types of access. see ?recovery phase (rp)? on page 15-67 and ?sdram recovery phases? on page 15-135 0000 b no recovery phase clock cycles available. 0001 b 1 clock cycle selected. ? b ? 1110 b 14 clock cycles selected. 1111 b 15 clock cycles selected. wrrecovc 6:4 rw recovery cycles after write accesses this bit field determines the basic number of clock cycles of the recovery p hase at the end of write accesses. see ?recovery phase (rp)? on page 15-67 and ?sdram recovery phases? on page 15-135 000 b no recovery phase cl ock cycles available. 001 b 1 clock cycle selected. ? b ? 110 b 6 clock cycles selected. 111 b 7 clock cycles selected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-176 v1.1, 2011-03 ebu, v1.9 waitwrc 11:7 rw programmed wait states for write accesses number of programmed wait states for write accesses. for synchronous a ccesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. 00000 b 1 wait state. 00001 b 1 wait states. 00010 b 2 wait state. ? b ? 11110 b 30 wait states. 11111 b 31 wait states. datac 15:12 rw data hold cycles for write accesses this bit field determines the basic number of data hold phase clock cycles during write accesses. 0000 b no recovery phase clock cycles available. 0001 b 1 clock cycle selected. ? b ? 1110 b 14 clock cycles selected. 1111 b 15 clock cycles selected. extclock 17:16 rw frequency of external clock at pin bfclko or sdclko see ?external bus clock generation? on page 15-26 . extdata 19:18 rw extended data see burst phase (bp) 00 b external memory outputs data every bfclk cycle 01 b external memory outputs data every two bfclk cycles 10 b external memory outputs data every four bfclk cycles 11 b external memory outputs data every eight bfclk cycles field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-177 v1.1, 2011-03 ebu, v1.9 cmddelay 23:20 rw command delay cycles this bit field determines the basic number of command delay phase clock cycles. 000 b 0 clock cycles selected. 001 b 1 clock cycles selected. ? b ? 110 b 6 clock cycles selected. 111 b 7 clock cycles selected. aholdc 27:24 rw address hold cycles this bit field determines the number of clock cycles of the address hold phase.. 0000 b 1 clock cycle selected 0001 b 1 clock cycle selected ? b ? 1110 b 14 clock cycles selected 1111 b 15 clock cycles selected addrc 31:28 rw address cycles this bit field determines the number of clock cycles of the address phase. 0000 b 1 clock cycle selected 0001 b 1 clock cycle selected ? b ? 1110 b 14 clock cycles selected 1111 b 15 clock cycles selected field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-178 v1.1, 2011-03 ebu, v1.9 15.21.9 sdram control register, sdrmcon memctrl sdram control register ebu_sdrmcon ebu sdram control register (068 h ) reset value: 1000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sdc mse l pwr_mo de clk dis res bankm crc rw rw rw r rw rw 1514131211109876543210 crcd awidth crp crsc crfsh cras rw rw rw rw rw rw field bits type description sdcmsel 31 rw sdram clock mode select 1 b clock disabled between accesses 0 b clock continuously runs note: (see ?power down mode? on page 15-134 ) pwr_mode 30:29 rw power save mode used for gated clock mode 0 h precharge before clock stop (default after reset) 1 h auto-precharge before clock stop 2 h active power down (stop clock without precharge) 3 h clock stop power down note: (see ?power down mode? on page 15-134 ) clkdis 28 rw disable sdram clock output 0 b clock enabled 1 b clock disabled note: (see ?power down mode? on page 15-134 ) res 27:25 r reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-179 v1.1, 2011-03 ebu, v1.9 bankm 24:22 rw mask for bank tag sri address bits to be used for determining bank number. 0 h reserved; (defau lt after reset) 1 h address bit 21 to 20 2 h address bit 22 to 21 3 h address bit 23 to 22 4 h address bit 24 to 23 5 h address bit 25 to 24 6 h address bit 26 to 25 7 h address bit 26 note: see ?bank address multiplexing? on page 15-126 . crc 21:16 rw refresh cycle time counter number of nop cycles following a refresh command before another command (other than a nop) can be issued to the sdram. combined with the crce bit as follows:- 0-3f h : insert crc + 1 nop cycles. crcd 15:14 rw row to column delay counter number of nop cycles betw een a row address and a column address. 0-3 h : insert crcd + 1 nop cycl es (default after reset crcd is 0). awidth 13:12 rw width of column address number of address bits from bit 0 to be used for column address. see also ?sdram addressing scheme? on page 15-125 . e.g. for 16 bit drams 0 h reserved , do not use 1 h address(8:0) 2 h address(9:0) 3 h address(10:0) crp 11:10 rw row precharge time counter number of nop cycles in serted after a precharge command. the actual number performed can be greater due to cas latency and burst length. 0-3 h : insert crsc + 1 nop cycles (default after reset crp is 0) field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-180 v1.1, 2011-03 ebu, v1.9 15.21.10 sdram mode register, sdrmod sdram mode register crsc 9:8 rw mode register set-up time number of nop cycles after a mode register set command. 0-3 h : insert crsc + 1 nop cycles (default after reset crsc is 0) crfsh 7:4 rw initialization refresh commands counter number of refresh commands issued during power- up initialization sequence. 0-15 h : perform crfsh + 1 refresh cycles (default after reset crfsh is 0) cras 3:0 rw row to precharge delay counter number of clock cycles between row activate command and a precharge command. 0-15 h : minimum cras + 1 clock cycles (default after reset cras is 0) ebu_sdrmod ebu sdram mode register (6c h ) reset value: 0000 0020 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 xba xopm rw rw 1514131211109876543210 col dst art res opmode caslat bty p burstl w r rw rw rw rw field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-181 v1.1, 2011-03 ebu, v1.9 field bits type description xba 31:30 rw extended operation bank select value to be written to the bank select pins of a ?mobile? sdram device during an extended mode register write operation. control of these bits is provided to allow support of future enhanced ?mobile? sdram devices. see ?mobile sdram support? on page 15-124 note: care must be taken when programming these bits to ensure that a valid extended mode register access occurs (e.g. it is possible to generate an extra unwanted standard mode register write by incorrect programming of these bits). 3. consult the appropriate sdram documentation for the function of these bits. xopm 29:16 rw extended operation mode value to be written to the extended mode register of a ?mobile? sdram device. this value is issued to the sdram via it?s address inputs during an extended mode register write. this field is wider than current extended mode registers to allow support of future enhanced ?mobile? sdram devices. note: consult the appropriate sdram documentation for the func tion of these bits. coldstart 15 w sdram coldstart this bit will always read 0. if a write to the ebu_sdrmod register takes place with this bit set, the sdra m device mode register will be updated to match the data written to the register. see ?initialization sequence? on page 15-121 res 14 r reserved 0 h fixed value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-182 v1.1, 2011-03 ebu, v1.9 opmode 13:7 rw operation mode memory controller only supports burst write standard operation. 0 h only this value should be written (default after reset) note: other values reserved caslat 6:4 rw cas latency number of clocks between a read command and the availability of data. 2 h two clocks (default after reset) 3 h three clocks note: other values reserved btyp 3rw burst type memory controller only supports sequential burst. 0 b only this value should be written (default after reset) 1 b reserved burstl 2:0 rw burst length number of locations can be accessed with a single command. 0 h 1 (default after reset) 1 h 2 2 h 4 3 h 8 4 h 16 note: other values reserved field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-183 v1.1, 2011-03 ebu, v1.9 15.21.11 sdram refresh co ntrol register, sdrmref sdram refresh control register ebu_sdrmref ebu sdram refresh co ntrol register(070 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res_dly arf sh selfrex_dly rrwrw rw 1514131211109876543210 erfshc aut ose lfr sel fre n sel fre nst sel fre x sel fre xst refreshr refreshc rw rw rw rh rw rh rw rw field bits type description res 31:28 r reserved 0 h reserved value res_dly 27:25 rw delay on power down exit number of nops after the sdram controller exits power down before an active command is permitted. note: see ?power down mode? on page 15-134 arfsh 24 rw auto refresh on self refresh exit if set to one, an auto refr esh cycle will be performed on exiting self refresh before the self refresh exit delay. if set to zero, no refresh will be performed. note: see ?self-refresh mode? on page 15-133 selfrex_dl y 23:16 rw self refresh exit delay number of nop cycles inse rted after a self refresh exit before a command is permitted to the sdram/ddram. note: see ?self-refresh mode? on page 15-133 erfshc 15:14 rw extended refresh counter period this field is used to increase the range of the refreshc field from 6 bits to 8 bits with erfshc being used as bits 7 and 6 of the extended field and refreshc as bit 5 to 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-184 v1.1, 2011-03 ebu, v1.9 autoselfr 13 rw automatic self refresh when this bit is set to ?1 ?, memory controller will automatically issue the self refresh entry command to all sdram devices when it gives up control of the external bus, and will au tomatically issue self refresh exit when it regains control of the bus. selfren 12 rw self refresh entry when this bit is written with ?1? the self refresh entry command is issued to all sdram devices, regardless whether they are attached to type 0 or type 1. selfrenst 11 rh self refresh entry status. if this bit is set to ?1?, it means the self refresh entry command has been successfully issued. this bit is reset when bit selfrex is set to ?1? or a reset takes place. selfrex 10 rw self refresh exit (power up). when this bit is written with ?1? the self refresh exit command is issued to all sdram devices, regardless whether they are attached to type 0 or type 1. this is also used after power is applied to drive cke high selfrexst 9rh self refresh exit status. if this bit is set to ?1?, it means the self refresh exit command has been successfully issued. this bit is reset when bit selfren is set to ?1? or a reset takes place. refreshr 8:6 rw number of refresh commands the number of additional refresh commands issued to sdram each time a refresh is due. 00 h 1 refresh command is issued (default after reset). 01 h 1 additional refresh command is issued. ? h ? 06 h 6 additional refresh commands are issued. 07 h 7 additional refresh commands are issued. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-185 v1.1, 2011-03 ebu, v1.9 15.21.12 sdram status register, sdrstat sdram status register refreshc 5:0 rw refresh counter period number of clock cycles between refresh operations. uses ((erfshc x 64) +refreshc) as a single counter value where 0 d means that no refresh is needed an the refresh generator is disable. this is the default setting after reset. for all other vales, the refresh period is ((erfshc x 64) + refreshc) x 64 clock cycles ebu_sdrstat ebu sdram status register (074 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res r 1514131211109876543210 res drif t_w arn sde rr sdr mbu sy ref err r rwhrwhrhrwh field bits type description res 31:4 r reserved 0 h reserved value drift_warn 3rwh dll drift warning the drift detector has detected that the dll operating point drift has exceeded the tracking limit of the dll. this bit latches at 1 b until cleared by writing a 0 b . see ?dll drift detected (drift_warn)? on page 15-137 0 b dll tracking successfully 1 b dll tracking limit has been exceeded field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-186 v1.1, 2011-03 ebu, v1.9 sderr 2rwh sdram read error sdram controller has detected an error when returning read data. see ?sdram read error (sderr)? on page 15-137 0 b reads running successfully 1 b read error condition has been detected note: this bit latches at 1 b and is reset by writing 0 b . sdrmbusy 1rh sdram busy the status of power-up initialization sequence. see ?sdram controller busy (sdrmbusy)? on page 15-137 0 b power-up initialization sequence is not running 1 b power-up initialization sequence is running referr 0rwh sdram refresh error unsuccessful previous refresh request collides with a new request. see ?refresh error (referr)? on page 15-136 this bit latches at 1 b and is reset by writing 0 b . 0 b no refresh error. 1 b refresh error occurred. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-187 v1.1, 2011-03 ebu, v1.9 15.21.13 dll control register, ebu_dllcon dll control register ebu_dllcon ebu dll control register (078 h ) reset value: 0000 2000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 amode wr_ en rd_ en win _en res0 rd_dqs_adj res 1 wr_d_adj rw rw rw rw r rw r rw 1514131211109876543210 alg o dll _rs t dll _dis dll _lc k dcc _en res2 dll_value rwwrwrhrw r rwh field bits type description amode 31:30 rw mode for generating address bits on ddr accesses. 00 b ddr control timing 01 b early address generation) 10 b reserved 11 b reserved. note: see ?ddr mode address outputs? on page 15-142 wr_en 29 rw write delay enable 0 b the slave delay line used to phase shift the outgoing dqs signals is disabled. 1 b the slave delay line used to phase shift the outgoing dqs signals is enabled. rd_en 28 rw read delay enable 0 b the slave delay lines used to phase shift the incoming dqs signals are disabled. 1 b the slave delay lines used to phase shift the incoming dqs signals are enabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-188 v1.1, 2011-03 ebu, v1.9 win_en 27 rw drift window enable see ?dll drift detector? on page 15-23 for information on this field 0 b warning window is disabled 1 b warning window is enabled res0 26:23 r reserved rd_dqs_adj 22:20 rw read dqs adjust signed binary number (in 64ths of a clock cycle) added to the shift value for the dqs inputs. the value will be sign extended. see ?dll operation? on page 15-20 res1 19 r reserved 0 b reserved value wr_d_adj 18:16 rw write data adjust signed binary number (in 64ths of a clock cycle) added to the shift value for the write data outputs. the value will be sign extended. see ?dll operation? on page 15-20 algo 15 rw lock algorith m control 0 b fast locking algorithm 1 b slow locking algorithm dll_rst 14 w reset the dll write ?1? to reset the dll control logic. if the dll is enabled, this will trigger a full relock. always reads ?0? dll_dis 13 rw disable dll lock function 0 b dll normal operation 1 b lock dll to value in dll_value field note: this should be set to one when the ddr clock frequency is too low for the dll to lock. it will force the dll to use the preloaded value. dll_lck 12 rh dll lock status 0 b dll is not locked 1 b dll is locked dcc_en 11 r duty cycle correction enable 0 b disabled 1 b enabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-189 v1.1, 2011-03 ebu, v1.9 res2 10:9 r reserved 0 b reserved value dll_value 8:0 rwh dll lock value when read will return the current lock value of the dll register. (i.e. the number of delay elements required to delay the clock by one clock period) when written will preload the dll register if the dll is not enabled. see ?dll operation? on page 15-20 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-190 v1.1, 2011-03 ebu, v1.9 15.21.14 lpddr nvm configuration register, ddrncon ebu_ddrncon ebu lpddr nvm configuration register (07c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod e maxadd csrs csrr crp rw rw rw rw rw 1514131211109876543210 pagesize crsc crcd rw rw rw field bits type description mode 31 rw device operating mode 0 b xip , attached memory is execute in place technology. 1 b nand , attached memory is not capable of being used as xip maxadd 30:28 rw nvm device size sri address bits to be used for accessing the attached device. 0 h sri address bits 21 to 0 1 h sri address bits 22 to 0 2 h sri address bits 23 to 0 3 h sri address bits 24 to 0 4 h sri address bits 25 to 0 5 h sri address bits 26 to 0 6 h sri address bits 27 to 0 7 h sri address bits 28 to 0 note: see ?bank address multiplexing? on page 15-126 . csrs 27:24 rw srr to next command delay number of memory clock cycl es delay to insert after the srr command of a status register read to satisfy the memory device t srs parameter. delay inserted will be csrs+1 nop cycles. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-191 v1.1, 2011-03 ebu, v1.9 csrr 23:20 rw mrs to srr command delay number of memory clock cycles delay to insert between the mrs command and the srr command during a status register read to satisfy the memory device t srr parameter. crp 19:16 rw preactive to active command delay number of memory clock cycles delay to insert between preactive and active commands to satisfy the memory device t rp parameter. pagesize 15:12 rw device page size page size of the memory device. this defines the number of internal address bits from bit 1 to be used for column address. see also ?normal operating mode? on page 15-146 . 3 h 32 bytes , address(3:1) 4 h 64 byte , address(4:1) 5 h 128 byte , address(5:1) 6 h 256 bytes , address(6:1) 7 h 512 bytes , address(7:1) 8h 1024 bytes , address(8:1) 9 h 2048 bytes , address(9:1) a h 4096 bytes , address(10:1) b h 8192 bytes , address(11:1) c h 16384 bytes , address(12:1) note: all other values reserved and must not be used crsc 11:8 rw mode register set-up time number of nop cycles afte r a mode register set command. 0-3 h : insert crsc + 1 nop cycl es (default after reset crsc is 0) crcd 7:0 rw row to column delay counter number of nop cycles between a row address and a column address. 0-31 d : insert crcd + 1 nop cycles of the device clock (default after reset crcd is 0). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-192 v1.1, 2011-03 ebu, v1.9 15.21.15 lpddr nvm mode register, ddrnmod ebu_ddrnmod ebu ddr nvm mode register (080 h ) reset value: 0000 0024 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 xba xopm rw rw 1514131211109876543210 res opmode caslat bty p burstl r rw rwrwrw field bits type description xba 31:30 rw extended operation bank select value to be written to the bank select pins of a lpddr nvm device during an extended mode register write operation. control of these bits is provided to allow support of future devices. note: care must be taken when programming these bits to ensure that a valid extended mode register access occurs (e .g. it is possible to generate an extra unwanted standard mode register write by incorrect programming of these bits). xopm 29:16 rw extended operation mode value to be written to the extended mode register of a lpddr nvm device. this value is issued to the device via it?s address inputs during an extended mode register write. this field is wider than current extended mode registers to allow support of future devices. note: consult the appropriate device documentation for the function of these bits. res 15:14 r reserved reads 0 b . must be written with 0 b . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-193 v1.1, 2011-03 ebu, v1.9 opmode 13:7 rw operation mode memory controller only supports burst write standard operation. this field should always be programmed with 00 h . all other values are reserved for possible future device extensions. see the memory device data sheet for any further information. caslat 6:4 rw cas latency number of clocks between a read command and the availability of data. 010 b cas2 , two clocks (defau lt after reset) 011 b cas3 , three clocks note: all other values reserved for future expansion and are not supported by the memory controller btyp 3rw burst type memory controller only supports sequential burst. 0 b linear , only this value should be written (default after reset) 1 b interleave , reserved. this value is not supported by the memory controller and is reserved in the jedec specification burstl 2:0 rw burst length number of locations can be accessed with a single command. 010 b 4 , word burst 011 b 8 , word burst 100 b 16 , word burst note: all other values reserved and not supported by the memory controller. not all burst lengths are necessarily supported by all memory devices. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-194 v1.1, 2011-03 ebu, v1.9 15.21.16 lpddr nvm extended mode register, ddrnmod2 ebu_ddrnmod2 ebu ddr nvm extended mode register (084 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 act xba dev sel xopm rwh rw r rw 1514131211109876543210 res r field bits type description act 31 rwh status register operation active write 1 b to this bitfield to trigger a mode/status register operation. when the operation is completed, the bit will be reset to 0 b by hardware. writing 0 b will have no effect. writing 1 b while an operation is in progress will not trigger a second status register operation but may overwrite the data to be written by the first. xba 30:29 rw extended operation bank select value to be written to the bank select pins of an lpddr-nvm device during an mode register write operation. note: care must be taken when programming these bits to ensure that a valid extended mode register access occurs (e.g. it is possible to generate an extra unwanted standard mode register write by in correct programming of these bits). dev_sel 28 r device select must be written with 0 b . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-195 v1.1, 2011-03 ebu, v1.9 xopm 27:16 rw extended operation mode value to be written to the second extended mode register of a lpddr-nvm device. this value is issued to the nvm via it?s address inputs during an extended mode register write. this field is wider than current extended mode registers to allow support of future devices. note: consult the appropriate device documentation for the function of these bits. 4. memory controller provides a 12-bit wide bit-field for the extended mode register to cater for devices that could theoretically use additional control bits (in comparison to currently available devices). res 15:0 r reserved reads as all 0 b . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-196 v1.1, 2011-03 ebu, v1.9 15.21.17 lpddr nvm status register, ddrnsrr ebu_ddrnsrr ebu ddr nvm status register (088 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 srrdata1 rh 1514131211109876543210 srrdata0 rh field bits type description srrdata1 31:16 rh status register read data returns the value of the last status register read operation. this field is only used when the lpddr- nvm region is configured as twin 16 bit. ie. two 16 bit memories are connected. srrdata0 15:0 rh status register read data returns the value of the last status register read operation. this field is used when a single 16 bit or 32 bit device is connected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-197 v1.1, 2011-03 ebu, v1.9 15.21.18 ddr preload register, ddrnprld ebu_ddrnprld ebu ddr nvm page preload register (08c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 acti ve ba page rh rw rw 1514131211109876543210 page rw field bits type description page 28:0 rw preload page byte address of page to be preloaded. note: see ?page preload? on page 15-149 ba 30:29 rw bank address two bit field identifying the rdb to be used. this value will be used as the bank address bits for the access active 31 rh preload active this bit will be set to 1 b while the preload command is in progress www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-198 v1.1, 2011-03 ebu, v1.9 15.21.19 ddr tag register, ddrntagx ebu_ddrntagx (x=0-3) ebu ddr tag registers (090 h +x*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 acti ve tag rwh rh 1514131211109876543210 tag rh field bits type description tag 30:0 rh current value for page tag byte address (internal, processor address) of page tag. significant bits will depend on hardware settings active 31 rwh page tag active status 0 b inactive , tag status is idle. address is invalid 1 b active , tag status is idle. address is valid www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-199 v1.1, 2011-03 ebu, v1.9 15.21.20 test/control config uration register, usercon ebu_usercon ebu test/control configuration register (00c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 add lsw advi o res0 addio rw rw r rw 1514131211109876543210 res1 naf dip rrwrw field bits type description dip 0rw disable internal pipelining reserved, set to 0 b naf 7:1 rw no assigned function reserved for future requirements res1 15:8 r reserved read as 0; should be written with 0. addio 24:16 rw address pins to gpio mode individual control bits for address bus bits 27 downto 19 respectively. 0 b address bit is required for addressing memory 1 b address bit switched to gpio function res 29:25 r reserved advio 30 rw adv pin to gpio mode control bit for the adv /ale output 0 b adv pin is required for controlling memory 1 b adv pin is switched to gpio function addlsw 31 rw enable address lsw, a(15:0) for gpio switch the least significant 16 bits of the address bus to gpio mode. 0 b a(15:0) in use by ebu 1 b a(15:0) used as gpio. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 sri external bus unit (ebu) users manual 15-200 v1.1, 2011-03 ebu, v1.9 15.22 registers for sfr extraction ebu_id ebu module identifi cation register (08 h ) reset value: 0014 c00a h 31 0 id_value r field bits type description id_value [31:0] r module identification value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-1 v1.1, 2011-03 interrupt, v1.5 16 interrupt system the TC1798 interrupt system pr ovides a flexible and time-e fficient means of processing interrupts. this chapter describes the inte rrupt system for the TC1798. topics covered include the architecture of the interrupt system, interrupt system configurat ion, and the interrupt operations of the TC1798 peripherals and central processing unit (cpu). general information is also given about the peripheral control processor (pcp). 16.1 overview an interrupt request can be serviced either by the cpu or by the pcp. interrupt requests are called ?service requests? rather than ?i nterrupt requests? in this document because they can be serviced by either one of the service providers. each peripheral in the TC1798 can generate service requests. additionally, the bus control units, the debug unit, the pcp, and even the cpu itself can generate service requests to either of the two service providers. as shown in figure 16-1 , each TC1798 unit that can generate service requests is connected to one or more service request nodes (srns). each srn contains a service request control register mod_srcx, where ?mod? is the identifier of the service requesting unit and ?x? an optional index. two arbitration buses connect the srns with two interrupt control units (icus), which handle interrupt arbitration among competing interrupt service requests, as follows: ? the interrupt control unit (icu) arbitrates service requests for the cpu and administers the cpu interrupt arbitration bus. ? the peripheral interrupt control unit (picu) arbitrates service requests for the pcp and administers the pcp interrupt arbitration bus. the pcp can make service requests directly to itself (via the picu), or it can make service requests to the cpu. the debug unit can generate service requests to the pcp or the cpu. the cpu can make service requests di rectly to itself (via the icu), or it can make service requests to the pcp. the cpu service request nodes are activated through software. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-2 v1.1, 2011-03 interrupt, v1.5 figure 16-1 block diagram of the TC1798 interrupt system pcp interrupt control unit picu service req. nodes service req. nodes service requestors cpu interrupt control unit service req. nodes interrupt service providers tc 1798_int_system 38 srns 38 gpta1 3 srns 3 ssc0 3 srns ssc1 4 srns 4 asc0 4 srns asc1 16 srns multican 9 srns adc0 4 srns fadc 2 srns 2 stm pcp interrupt arbitration bus cpu interrupt arbitration bus 5 srns 2 srns pcp2 int. ack. ccpn 5 srns int. req. pipn cpu ccpn int. ack. software and breakpoint interrupts icu 5 srns 38 srns 38 gpta0 16 srns 16 ltca2 4 srn 1 srn 1 srn 2 srn 8 srns mli0 service requestors xbar sbcu cerberus dma 4 srns int. req. pipn scu 3 4 16 9 4 4 4 4 2 2 4 4 9 9 16 16 4 4 4 4 3 3 3 3 16 16 38 38 38 38 4 4 2 2 8 8 1 1 1 1 1 8 2 4 5 5 2 5 5 55 5 2 5 msc1 mli1 msc0 2 srn 2 srn 2 srns 2 2 2 2 2 2 2 2 2 8 srns sdma 8 8 8 1 srn 1 srn she fce 1 1 1 1 1 2 srns 2 sscg0 / sscg1 2 srns sscg2 / sscg3 2 2 2 2 2 3 srns 3 ssc2 3 srns ssc3 3 3 3 3 3 1 6 srns gpt120 6 srns gpt121 6 6 6 6 6 6 8 srns cc6061 8 srns cc6263 8 8 8 8 8 8 tc 1798_int_system 4 srn sent 4 4 4 1 srn bmu 1 1 1 10 srns e-ray 10 10 10 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-3 v1.1, 2011-03 interrupt, v1.5 16.2 service request nodes each srn contains a service request control register and interface logic that connects it to the triggering unit and to the two interrupt arbitration buses. some peripheral units of the TC1798 have multiple srns. 16.2.1 service request control registers all service request control registers in the TC1798 have the same format. in general, these registers contain: ? enable/disable information ? priority information ? service provider destination ? service request status bit ? software-initiated service request set and reset bits besides being activated by the associated triggering unit through hardware, each srn can also be set or reset by software via two software-initiated service request control bits. the description given in this chapter characte rizes all service request control registers of the TC1798. information on peripheral module interrupt functions such as enable or request flags is provided in the corresponding sections of the module chapters. 16.2.1.1 general serv ice request control register format the description given in this chapter characte rizes all service request control registers of the TC1798. information on peripheral module interrupt functions such as enable or request flags is provided in the corresponding sections of the module chapters. mod_src service request control register (00 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-4 v1.1, 2011-03 interrupt, v1.5 field bits type description srpn [7:0] rw service request priority number 00 h service request is never serviced 01 h service request is on lowest priority ?? ff h service request is on highest priority tos 10 rw type of service control 0 cpu service is initiated 1 pcp request is initiated sre 12 rw service request enable 0 service request is disabled 1 service request is enabled srr 13 rh service request flag 0 no service request is pending 1 a service request is pending clrr 14 w request clear bit clrr is required to reset srr. 0 no action 1 clear srr; bit value is not stored; read always returns 0; no action if setr is set also. setr 15 w request set bit setr is required to set srr. 0 no action 1 set srr; bit value is not stored; read always returns 0; no action if clrr is set also. 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-5 v1.1, 2011-03 interrupt, v1.5 16.2.1.2 request set and clear bits (setr, clrr) the setr and clrr bits allow software to set or clear the service request bit srr. writing a 1 to setr causes bit srr to be set to 1. writing a 1 to clrr causes bit srr to be cleared to 0. if hardware attempts to modify srr during a read-modify-write software operation (such as the bit-set or bi t-clear instructions), the software operation will succeed and the hardware operation will ha ve no effect. the value written to setr or clrr is not stor ed. writing a 0 to these bits has no effect. these bits always return 0 when read. if both, setr and clrr, are set to 1 at the same time, srr is not changed. 16.2.1.3 enable bit (sre) the sre bit enables an interrupt to take part in the arbitration for the selected service provider. it does not enable or disable the setting of the request flag srr; the request flag can be set by hardware or by software (via setr) independent of the state of the sre bit. this allows service requests to be handled automatically by hardware or through software polling. if sre = 1, pending service requests are pa ssed on to the designated service provider for interrupt arbitration. the srr bit is automatically set to 0 by hardware when the service request is acknowledged and serviced. it is recommended that in this case, software should not modify the srr bit to avoid unexpected behavior due to the hardware controlling this bit. if sre = 0, pending service requests are not passed on to service providers. software can poll the srr bit to check whether a service request is pending. to acknowledge the service request, the srr bit must then be reset by software by writing a 1 to clrr. note: in this document, ?active source? means an srn whose service request control register has its request enable bit sre se t to 1 to allow its service requests to participate in interrupt arbitration. 16.2.1.4 service request flag (srr) when set, the srr flag indicates that a service request is pending. it can be set or reset directly by hardware or indirectly throug h software using the setr and clrr bits. writing directly to this bit via software has no effect. the srr status bit can be directly set or re set by the associated hardware. for instance, in the general purpose array unit, an associated timer event can cause this bit to be set to 1. the details of how hardware events can cause the srr bit to be set are defined in the individual peripheral/module chapters. the acknowledgment of the service request by either the interrupt control unit (icu) or the pcp interrupt control unit (picu) causes the srr bit to be cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-6 v1.1, 2011-03 interrupt, v1.5 srr can be set or cleared either by hardwar e or by software regardless of the state of the enable bit sre. however, the request is only forwarded for service if the enable bit is set. if sre = 1, a pending service request takes part in the interrupt arbitration of the service provider selected by the device?s tos bit. if sre = 0, a pending service request is excluded from interrupt arbitrations. srr is automatically reset by hardware wh en the service request is acknowledged and serviced. software can poll srr to check for a pending service request. srr must be reset by software in this case by writing a 1 to clrr. it is not advisable to clear a pending service request flag srr (writing clrr = 1) and enable the corresponding service request node srn (writing sre = 1) simultaneously at the same write access to the service request control register. if this should happen, an unintended interrupt request may be generated. instead of executing one write access, it is recommended to split the two actions into two consecutive write accesses to the corresponding service request control register, starting with the clearing of the pending interrupt flag and followed by the enabling of the service request node. 16.2.1.5 type-of-serv ice control (tos) there are two service providers for service requests in the TC1798, the cpu and the pcp. the tos bit is used to select whether a service request generates an interrupt to the cpu (tos = 0) or to the pcp (tos = 1). bit 11 of the service request control register is read-only, returning 0 when read . writing to this bit position has no effect. however, to ensure compatibility with future extensions, bit 11 should always be written with a 0. note that several service request control registers (e.g. in the pcp) have a hardwired tos bit (0 or 1) that cannot be written. th ese registers can only generate an interrupt to one dedicated service provider (pcp or cpu). note: before modifying the content of a tos bit, the corresponding srn must be disabled (sre = 0). 16.2.1.6 service request priority number (srpn) the 8-bit service request priority number (s rpn) indicates the priority of a service request with respect to other sources requesti ng service from the same service provider, and with respect to the priority of the service provider itself. each active source selecting the same service provider must have a unique srpn value to differentiate its priority. the special srpn value of 00 h excludes an srn from taking part in arbitration, regardless of the state of its sre bit. the srpn values for active sources selecting different service providers (cpu vs. pcp) may overlap. if a source is not active ? meaning its sre bit is 0 ? no restrictions are applied to the service request priority number. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-7 v1.1, 2011-03 interrupt, v1.5 the srpn is used by service providers to select an interrupt service routine (isr)) or channel program (in case of the pcp) to service the request. isrs are associated with service request priority numbers by an interr upt vector table located in each service provider. this means that the TC1798 inte rrupt vector table is ordered by priority number. this is unlike traditional interrupt architectures in which their interrupt vector tables are ordered by the source of the interrupt. the TC1798 interrupt vector table allows a single peripheral to have multip le priorities for different purposes. the range of values for srpns used in a system depends on the number of possible active service requests and the user-definable organization of the interrupt vector table. the 8-bit srpns permit up to 255 sources to be active at one time (remembering that the special srpn value of 00 h excludes an srn from taking part in arbitration). note: before modifying the content of an sr pn bit field, the corresponding srn must be disabled (sre = 0). srpns in the TC1798 in the TC1798, interrupt sources selecting the same service provider are also allowed to have identical srpn values. in this case, the software (interrupt service routine) must check which of the interrupt sources with identical srpn has become active. note that module-specific interrupt reques t flags must be available because the srr flags cannot be used for this check. srr flags (meaning all srr flags of interrupts with identical srpn values) are in general automatically reset by hardware when a service request is acknowledged and serviced. note: this practice with identical srpn values is not recommended as it is not portable to other tricore devices. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-8 v1.1, 2011-03 interrupt, v1.5 16.3 interrupt control units the interrupt control units manage the inte rrupt system, arbitrate incoming service requests, and determine whether and when to interrupt the service provider. the TC1798 contains two interrupt control units, one for the cpu (called icu), and one for the pcp (called picu). each one controls its associated interrupt arbitration bus and manages the communication with its service provider (see ). 16.3.1 interrupt control unit (icu) this section describes the interrupt control unit (icu) for the cpu. 16.3.1.1 icu interrupt c ontrol register (icr) the icu interrupt control register icr hold s the current cpu priority number (ccpn), the global interrupt enable/disable bit (ie), th e pending interrupt priority number (pipn), and bit fields which control the interrupt arbitration process. icr icu interrupt contro l register (f7e1fe2c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 c one cyc carbcyc pipn rrwrw rh 1514131211109876543210 0ie ccpn rrwh rwh field bits type description ccpn [7:0] rwh current cpu priority number the current cpu priority number (ccpn) bit field indicates the current priority level of the cpu. it is automatically updated by hardware on entry and exit of interrupt service routines, and through the execution of a bisr instruction. ccpn can also be updated through an mtcr instruction. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-9 v1.1, 2011-03 interrupt, v1.5 ie 8rwh global interrupt enable bit the interrupt enable bit globally enables the cpu service request system. whether or not a service request is delivered to the cpu depends on the individual service request enable bits (sre) in the srns, and the current state of the cpu. ie is automatically updated by hardware on entry and exit of an interrupt service routine (isr). ie is cleared to 0 when an interrupt is taken, and is restored to the previous value when the isr executes an rfe instruction to terminate itself. ie can also be updated through the execution of the enable, disable, mtcr, an d bisr instructions. 0 interrupt system is globally disabled 1 interrupt system is globally enabled pipn [23:16] rh pending interrupt priority number pipn is a read-only bit field that is updated by the icu at the end of each interrupt arbitration process. it indicates the priority number of the pending service request. pipn is set to 0 when no request is pending, and at the beginning of each new arbitration process. 00 h no valid pending request yy h a request with priority yy h is pending carbcyc [25:24] rw number of arbitration cycles carbcyc controls the numbe r of arbitration cycles used to determine the request with the highest priority. 00 b 4 arbitration cycles (default) 01 b 3 arbitration cycles 10 b 2 arbitration cycles 11 b 1 arbitration cycle conecyc 26 rw number of clocks per arbitration cycle control the conecyc bit determines the number of system clocks per arbitration cycle. for the TC1798 this bit can be set to 1 (for spb fr equencies up to the max spb frequency as defined in the data sheet). 0 2 clocks per arbitration cycle (default) 1 1 clock per arbitration cycle 0 [15:9], [31:27] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-10 v1.1, 2011-03 interrupt, v1.5 16.3.1.2 operation of the in terrupt control unit (icu) service-request arbitration is performed in the icu in parallel with normal cpu operation. when a triggering event occurs in one or more interrupt sources, the associated srns, if enabled, send service requests to the cpu through the icu. the icu determines which service request has the highest priority. the icu will then forward the service request to the cpu. the service request will be acknowledged by the cpu and serviced, depending upon the state of the cpu. the icu arbitration process takes place in o ne or more arbitration cycles over the cpu interrupt arbitration bus. the icu begins a new arbitration process when a new service request is detected. at the end of the arbitration process, the icu will ha ve determined the service request with the highest priority number. this number is stored in the icr.pipn bit field and becomes the pending service request. after the arbitration process, the icu forwar ds the pending service request to the cpu by attempting to interrupt it. the cpu can be interrupted only if interrupts are enabled globally (that is, icr.ie = 1) and if the priority of the service request is higher than the current processor priority (icr.pipn > icr.ccpn). also, the cpu may be temporarily blocked from taking interrupts, for example, if it is executing a multi-cycle instruction such as an atomic read-modify-write operation. the full list of conditions which could block the cpu from immediately responding to an interrupt request generated by the icu is: ? current cpu priority, icr.ccpn, is equal to or higher than the pending interrupt priority, icr.pipn ? interrupt system is globally disabled (icr.ie = 0) ? cpu is in the process of entering an interrupt- or trap-service routine ? cpu is executing non-interruptible trap services ? cpu is executing a multi-cycle instruction ? cpu is executing an instruction which modifies the conditions of the global interrupt system, such as modifying the icr ? cpu detects a trap condition (such as context depletion) when trying to enter a service routine when the cpu is not otherwise prevented from taking an interrupt, the cpu?s program counter will be directed to the interrupt service routine entry point associated with the priority of the service request. next, the cpu saves the value of icr.pipn internally, and acknowledges the icu. the icu then forwards the acknowledge signal back to the srn that is requesting service in order to inform it that it will be serviced by the cpu. the srr bit in this srn is then reset to 0. after sending the acknowledgement, the icu resets icr.pipn to 0 and may start a new arbitration process if there is another pending interrupt request. if not, icr.pipn remains at 0 and the icu enters an idle state, waiting for the next interrupt request to awaken it. if there is a new service request waiting, th e priority number of the new request will be written to icr.pipn at the end of the new arbitration pr ocess and the icu will deliver the pending interrupt to the cpu according to the rules described in this section. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-11 v1.1, 2011-03 interrupt, v1.5 if a new service request is received by the icu before the cpu has acknowledged the pending interrupt request, the icu deactivates the pending request and starts a new arbitration process. this reduces the laten cy of service requests posted before the current request is acknowledged. the icu deactivates the current pending interrupt request by setting the icr.pipn bit field to 0, indicating that the icu has not yet found a new valid pending request. it then executes its arbitration process again. if the new service request has a higher priority than the previous one, its priority will be written to icr.pipn. if the new interrupt has a lower priority, the priority of the previous interrupt request will again be written to icr.pipn. in any case, the icu will deliver a new interrupt request to the cpu according to the rules described in this section. once the cpu has acknowledged the current pending interrupt request, any new service request generated by an srn must wait at least until the end of the next service request arbitration process to be serviced. essentially, arbitration in the icu is pe rformed whenever a new service request is detected, regardless of whether or not the cp u is servicing interrupts. because of this, the icr.pipn bit field always reflects t he pending service request with the highest priority. this can, for example, be used by software polling techniques to determine high- priority requests while leavin g the interrupt system disabled. 16.3.2 pcp interrupt control unit (picu) the pcp interrupt control unit (picu) is closely coupled with the pcp and its interrupt control register (pcp_picr). the operation of the picu is very similar to the icu of the cpu with respect to the overall scheme. note: details of the picu and the pcp_icr re gister are described in the chapter about the pcp. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-12 v1.1, 2011-03 interrupt, v1.5 16.4 arbitration process the arbitration process impl emented in the TC1798 uses a number of arbitration cycles to determine the pending interrupt request with the highest priority number, srpn. in each of these cycles, two bits of the srpns of all pending service requests are compared against each other. the sequence st arts with the high-order bits of the srpns and works downwards, such that in the last cycle, bits [1 :0] of the srpn s are compared. thus, to perform an arbitration through all 8 bi ts of an srpn, four arbitration cycles are required. there are two factors determining the duration of the arbitration process: ? number of arbitration cycles, and ? duration of arbitration cycles. both of these can be controlled by the user. 16.4.1 controlling the numb er of arbitration cycles in a real-time system where responsiveness is critical, arbitration must be as fast as possible. however, to maintain flexibility, the TC1798 system is de signed to have a large range of service priorities. if not all priori ties are needed in a system, arbitration can be accelerated by not examining all the bits used to identify all 255 unique priorities. for instance, if a 6-bit number is enough to i dentify all priority numbers used in a system (meaning that bits [7:6] of all srpns are always 0), it is not necessary to perform arbitration on these two bits. three arbitration cycles will be enough to find the highest number in bits [5:0] of the srpns of all pending requests. similarly, the number of arbitration cycles can be reduced to two if only bits [3:0] are used in all srpns, and the number of arbitration cycles can be reduced to one cycle if only bits [1:0] are used. the icr.carbcyc bit field cont rols the number of cycles in the arbitration process. its default value is 0, which selects four arbitration cycles. table 16-1 gives the options for arbitration cycle control. note: if less than four arbitration cycles are selected, the corresponding upper bits of the srpns are not examined, even if they do not contain zeros. table 16-1 arbitration cycle control number of arbitration cycles 4321 icr.carbcyc 00 b 01 b 10 b 11 b relevant bits of the srpns [7:0] [5:0] [3:0] [1:0] range of priority numbers covered 1..255 1..63 1..15 1..3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-13 v1.1, 2011-03 interrupt, v1.5 16.4.2 controlling the duration of arbitration cycles during each arbitration cycle, th e rate of information flow between the srns and the icu can become limited by propagation delays within the TC1798 when it is executing at high system clock frequencies. at high frequencies , arbitration cycles may require two system clocks to execute properly. in order to optimize the arbi tration scheme at lower system frequencies, an additional control bit, icr.conecyc, is implemented. the default value of 0 of this bit select s two clock cycles per arbitration cycl e. setting this bit to 1 selects one clock cycle per arbitration cycle. the maximum frequency for the icr.conecyc=1 setting is defined in the product data sheetsetting this bit for system frequencies above the specified limit leads to unpredictable behavior of the interrupt system. correct operation is then no t guaranteed. 16.5 entering an interrupt service routine when an interrupt request from the icu is pending and all conditions are met such that the cpu can now service the interrupt request, the cpu performs the following actions in preparation for entering the designated interrupt service routine (isr): 1. upper context of the current task is saved 1) . the current cpu priority number, icr.ccpn, and the state of the global interrupt enable bit, icr.ie, are automatically saved with the pcxi register (bit field pcpn and bit pie). 2. interrupt system is globally disabled (icr.ie is set to 0). 3. current cpu priority number (icr.ccpn) is set to the value of icr.pipn. 4. psw is set to a default value: a) all permissions are enabled, that is, psw.io = 10 b . b) memory protection is switched to prs0, that is, psw.prs = 0. c) the stack pointer bit is set to the interrupt stack, that is, psw.is = 1. d) the call depth counter is cleared, the call depth limit is set to 63, that is, psw.cdc = 0. 5. stack pointer, a10, is reloaded with the contents of the interrupt stack pointer, isp, if the psw.is bit of the interrupted routine was set to 0 (using the user stack); otherwise it is left unaltered. 6. cpu program counter is assigned with an effective address consisting of the contents of the biv register or-ed with the icr.pipn number left-shifted by 5. this indexes the interrupt vector table entry corresponding to the interrupt priority. 7. contents at the effective address of the pr ogram counter in the interrupt vector table are fetched as the first instruction of the interrupt service routine (isr). execution continues linearly from there until the isr branches or exits. 1) note that, if a context-switch trap occurs while the cpu is in the process of saving the upper context of the current task, the pending isr will not be entered, the interrupt request will be left pending, and the cpu will enter the appropriate trap handling routine instead. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-14 v1.1, 2011-03 interrupt, v1.5 as explained, receipt of further interrupts is disabled (icr.ie = 0) when an interrupt service routine is entered. at the same time , the current cpu priority icr.ccpn is set by hardware to the priority of th e interrupting source (icr.pipn). clearly, before the processor can receive any more interrupts, the isr must eventually re-enable the interrupt system again by setting icr.ie = 1. furthermore, the isr can also modify the priority number icr.ccpn to al low effective interrupt priority levels. it is up to the user to enable the interrupt system again and optionally modify the priority number ccpn to implement interrupt priority levels or handle special cases. to simply enable the interrupt system again, the enable instructio n can be used, which sets icr.ie bit to 1. the bisr instruction offers a convenient way to re-enable the interrupt system, to set icr.ccpn to a new value, and to save the lower context of the interrupted task. it is also possible to use an mtcr instruction to modify icr.ie and icr.ccpn. however, this should be performed together with an isync instruction (which synchronizes the instruction stream) to ensure completion of this operation before the execution of following instructions. note: the lower context can also be saved through execution of an svlcx (save lower context) instruction. 16.6 exiting an interrupt service routine when an isr exits with an rfe (return from exception) instruction, the hardware automatically restores the upper context. re gister pcxi, which holds the previous cpu priority number (pcpn) and the previous gl obal interrupt enable bit (pie), is a part of this upper context. the value saved in pc pn is written to icr.ccpn to set the cpu priority number to the value before the interruption, and bit pie is written to icr.ie to restore the state of this bit. the interrupted routine then continues. note: there is no automatic restoring of the lower context on an exit from an interrupt service routine. if the lower context wa s saved during the execution of the isr, either through execution of the bisr inst ruction or an svlcx instruction, the isr must restore the lower context again via the rslcx (restore lower context) instruction before it exits through rfi execution. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-15 v1.1, 2011-03 interrupt, v1.5 16.7 interrupt vector table interrupt service routines (isrs) are associated with interrupts at a particular priority by way of the interrupt vector table. the interrupt vector table is an array of isr entry points. when the cpu takes an interrupt, it calculates an address in the interrupt vector table that corresponds with the priority of the interrupt (the icr.pipn bit field). this address is loaded in the program counter. the cpu begins executing instructions at this address in the interrupt vector table. the code at this address is the start of the selected isr. depending on the code size of the isr, the interrupt vector table may only store the initial portion of the isr, such as a jump instruction that vectors the cpu to the rest of the isr elsewhere in memory. the interrupt vector table is stored in code memory. the biv register specifies the base address of the interrupt vector table. in terrupt vectors are ordered in the table by increasing priority. the base of interrupt vector table register (biv) stores the base address of the interrupt vector table. it can be assigned to any available code memory. its default on power-up is fixed at 0000 0000 h . however, the biv register can be modified using the mtcr instruction during the initialization phase of the system, before interrupts are enabled. with this arrangement, it is possible to have multiple interrupt vector tables and switch between them by changing the contents of the biv register. note: the biv register is protected by the e ndinit bit (see chapter describing the watchdog timer). modifications should only be done while the interrupt system is globally disabled (icr.ie = 0). also, an i sync instruction should be issued after modifying biv to ensure completion of this operation before execution of following instructions. when interrupted, the cpu calculates the entry point of the appropriate isr from the pipn and the contents of the biv register. the pipn is left-shifted by five bits and or-ed with the address in the biv register to generate a pointer into the interrupt vector table. execution of the isr begins at this address. due to this operation, it is recommended that bits [12:5] of register biv are set to 0 (see figure 16-2 ). note that bit 0 of the biv register is always 0 and cannot be written to (instructions have to be aligned on even byte boundaries). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-16 v1.1, 2011-03 interrupt, v1.5 figure 16-2 interrupt vector table entry address calculation left-shifting the pipn by 5 bits creates entries into the interrupt vector table which are evenly spaced 8 words apart. if an isr is very short, it may fit entirely within the eight words available in the vector table entry. otherwise, the code at the entry point must ultimately cause a jump to the rest of the isr residing elsewhere in memory. due to the way the vector table is organized according to the interrupt priorities, the TC1798 offers an additional option by allowing spanning several interrupt vector table entries as long as those entries are otherwise unused. figure 16-3 illustrates this. the required size of the interrupt vector table depends only on the range of priority numbers actually used in a system. of the 256 vector ent ries, 255 may be used. vector entry 0 is never used, because if icr.pipn is 0, the cpu is not interrupted. distinct interrupt handlers are supported, but systems requiring fewer entries need not dedicate the full memory area required by the largest configurations. mca06182 0 0 0 0 b iv pipn or resulting interrupt vector table entry address 0 0 000 0 5 31 12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-17 v1.1, 2011-03 interrupt, v1.5 figure 16-3 interrupt vector table 8 words 8 words mca06183 interrupt vector table 8 words 8 words biv pn = 0 (never used) pn = 1 pn = 2 pn = 3 pn = 4 pn = 5 pn = 255 priority number (may not be use d if spanned by is r with pn = 2) service routine may span several entries www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-18 v1.1, 2011-03 interrupt, v1.5 16.8 usage of the TC1798 interrupt system the following sections provide examples of using the TC1798 interrupt system to solve both typical and special application requirements. 16.8.1 spanning interrupt service ro utines across vector entries each interrupt vector table entry consists of eight words of memory. if an isr can be made to fit directly in the interrupt vector table there is no need for a jump instruction to vector to the rest of the interrupt handler elsewhere in memory. however, only the simplest isrs can fit in the eight words available to a single entry in the table. but it is easy to arrange for isrs to span across multiple entries, since the interrupt vector table is ordered not by the interrupt source but by interrupt priority. this technique is explained in this section. in the example of figure 16-3 , entry locations 3 and 4 are occupied by the isr for entry 2. in figure 16-3 , the next available entry after entry 2 is entry 5. of course, if this technique is used, it would be improper to allow any srn to request service at any of the spanned vector priorities. thus, priority levels 3 and 4 must not be assigned to srns requesting cpu service. they can, however, be used to request pcp service. there is a performance trade-off that may arise when using this technique because the range of priority numbers used increases. this may have an impact on the number of arbitration cycles required to perform arbitrat ion. consider the ca se in which a system uses only three active interrupt sources, that is, where there are only three srns enabled to request service. if these three ac tive sources are assigned to priority numbers 1, 2, and 3, it would be sufficient to perform the arbitrat ion in just one cycle. however, if the isr for interrupt priority 2 is spanned across three interrupt vector table entries as shown in figure 16-3 , the priority numbers 1, 2 and 5 would have to be assigned. thus, two arbitration cycles would have to be us ed to perform the fu ll arbitration process. the trade-off between the performance impact of the number of arbitration cycles and the performance gain through spanning service routines can be made by the system designer depending on system needs. reduci ng the number of arbitration cycles reduces the service request arbitration latency - spanning service routines reduces the run time of service routines (and therefore al so the latency for further interrupts at that priority level or below). for example, if th ere are multiple fleeting measurements to be made by a system, reducing arbitration latency may be most important. but if keeping total interrupt response time to a minimum is most urgent, spanning interrupt vector table entries may be a solution. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-19 v1.1, 2011-03 interrupt, v1.5 16.8.2 configuring ordinary interrupt service routines when the cpu starts to service an interrupt, the interrupt system is globally disabled and the cpu priority icr.ccpn is set to the priority of the interrupt now being serviced. this blocks all further interrupts from being serviced until the interrupt system is enabled again. after an ordinary isr begins execution, it is usually desirable for the isr to re-enable global interrupts so that higher-priority interrupts (that is, interrupts that are greater than the current value of icr.ccpn) can be serviced even during the current isr?s execution. thus, such an isr may set icr.ie = 1 again with, for instance, the enable instruction. if the isr enables the interrupt system again by setting icr.ie = 1 but does not change icr.ccpn, the effect is that from that point on the hardware can be interrupted by higher-priority interrupts but w ill be blocked from servicing interrupt requests with the same or lower priority than the current value of bit field isr.ccpn. since the current isr is clearly also at this priority level, the hardware is also blocked from delivering further interrupts to it as well. (this condition is clearly necessary so that the isr can service the interrupt request automatically.) when the isr is finished, it exits with an rfe instruction. hardware then restores the values of icr.ccpn and icr.ie to the values of the interrupted program. 16.8.3 interrupt priority groups it is sometimes useful to create groups of interrupts at the same or different interrupt priorities that cannot interrupt each other?s isrs. for instance, devices that can generate multiple interrupts may need to have interrupts at different priorities interlocked in this way. the TC1798 interrupt architecture can be used to create such interrupt priority groups. it is effected by managing the current cpu priority level icr.ccpn in a way described in this section. for example, in order to make an interrupt priority group out of priority numbers 11 and 12, one would not want an isr executing at priority 11 to be interrupted by a service request at priority 12, since this would be in the same priority group. only interrupts above 12 should be allowed to interrupt the isrs in this interrupt priority group. however, under ordinary isr usage, the isr at priori ty 11 would be interrupted by any request with a higher priority number, including priority 12. if, however, all isrs in the interrupt priority group set the value of icr.ccpn to the highest priority level within their group before they re-enable interrupts, then the desired interlocking will occur. figure 16-4 shows an example for interrupt priority grouping. the interrupt requests with the priority numbers 11 and 12 form one group , while the requests with priority numbers 14 through 17 form another group. each isr in group 1 sets the value of icr.ccpn to 12, the highest number in that group, before re-enabling the interrupt system. each isr in group 2 sets the value of icr.ccpn to 17 before re-ena bling the interrupt system. if, www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-20 v1.1, 2011-03 interrupt, v1.5 for example, interrupt 14 is serviced, it can only be interrupted by requests with a priority number higher than 17; therefore it will no t be interrupted by requests from its own priority group or requests with lower priority. in figure 16-4 , the interrupt request with priority number 13 can be said to form an interrupt priority group with just itself as a member. setting icr.ccpn to the maximum value 255 in each service routine has the same effect as not re-enabling the interrupt system; all interrupt requests can then be considered to be in the same group. interrupt priority groups demonstrate the pow er of the TC1798 priority-based interrupt- ordering system. thus the flexibilit y of interrupt priority levels ranges from all interrupts in one group to each interrupt request building its own group, and to all possible combinations in between. figure 16-4 interrupt priority groups 16.8.4 splitting interrupt service across diff erent priority levels interrupt service can be divided into multiple isrs that execute at different priority levels. for example, the beginning stage of interrupt service may be very time-critical, such as reading a data value within a limited time window after the interrupt request activation. however, once the time-critical phase is past, there may still be more to do ? for instance, mca06184 interrupt vector table pn = 25 5 pn = 18 pn = 17 pn = 16 pn = 15 pn = 14 pn = 13 pn = 12 pn = 11 pn = 10 priority group 2 priority group 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-21 v1.1, 2011-03 interrupt, v1.5 to process the observation. during this second phase, it may be acceptable for this isr to be interrupted by lower-level interrupts. this can be performed as follows. for example, the initial interrupt priority is fixed very high because response time is critical. the necessary actions are carried out i mmediately by the isr at that high-priority level. then the isr prepares to invoke another isr at a lower priority level through software to perform the lower-priority actions. to invoke an isr through software, the high-priority isr directly sets an interrupt request bit in an srn that will invoke the appropriate low-priority isr. then the high-priority isr exits. when the high-priority isr exits, the pending low-priority interrupt will eventually be serviced (depending on the priority of othe r pending interrupts). when the low-priority isr eventually executes, the low-priority actions of the interrupt will be performed. the inverse of this method can also be empl oyed, wherein a low-priority isr raises its own priority level, or leaves interrupts turned off while it executes. for instance, the priority of a service request might be low because the time to respond to the event is not critical, but once it has been granted servic e, this service should not be interrupted. in this case, the isr could raise the value of icr.ccpn to a priority that would exclude some or all other interrupts, or simply leave interrupts disabled. 16.8.5 using different priorities for the same interrupt source for some applications, the urgency of a service request may vary, depending on the current state of the system. to handle this, different priority numbers (srpns) can be assigned at different times to a service request depending on the application needs. of course, interrupt service routines must be placed in the interrupt vector table at all addresses corresponding to the range of priorities used. if service remains the same at different priorities, copies of the isr can be placed at the possible different entries, or the entries can all vector to a common isr. if the isr should execute different code depending on its priority, one need merely pu t the appropriate isr in the appropriate entry of the interrupt vector table. this flexibility is another advantage of the TC1798 interrupt architecture. in traditional interrupt systems where the interrupt vectors are ordered by interrupting source, the isr would have to check the current priority of the interrupt request and perform a branch to the appropriate code section, causing a delay in the response to the request. in the TC1798, however, the extra check and branch in the isr are not necessary, hence reduces the interrupt latency. because this approach may necessitate an increase in the range of interrupt priorities, the system designer must trade off this advantage against any possible increase in the number of arbitration cycles. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-22 v1.1, 2011-03 interrupt, v1.5 16.8.6 interrupt priority 1 interrupt priority 1 is the first and lowest-priority entry in the interrupt vector table. it is generally reserved for isrs which perform task management. isrs whose actions cause software-managed tasks to be created post a soft ware interrupt request at priority level 1 to signal the event. the isr that triggers this event can then exec ute a normal return from interrupt. there is no need for it to check whether the isr is returning to the background-task priority level (priority 0) or is returning to a lower-priority isr that it interrupted. when there is a pending interrupt at a priority higher than the return context for the current interrupt, this interrupt will then be serviced. when a return to the background-task priority level (level 0) is performed, the software-posted inte rrupt at priority level 1 will be serviced automatically. 16.8.7 software-ini tiated interrupts software can set the service request bit (srr) in a srn by writing to its service request control register. thus, software can initiate interrupts that are handled by the same mechanism as hardware interrupts. after the srr bit is set in an active srn, there is no way to distinguish between a software-initiated interrupt request and a hardware interrupt request. for this reason, software should only use srns and interrupt priority numbers that are not being used for hardware interrupts. the TC1798 contains four srns that suppor t software-initiated interrupts. these srns are not connected to peripheral modules and can only cause interrupts when software sets its srr bit. these srns are called the cpu service request nodes (cpu_src[3:0]). the pcp can also cause these four srns to generate service requests. see also the tricore chapter for TC1798-specific implementation details of the four cpu service request control registers. additionally, any otherwise unused srn can be employed to generate software interrupts. 16.8.8 external interrupts four srns (scu_src[3:0]) are reserved to handle external interrupts. the setup for external gpio port input signals (edge/level triggering, gating etc.) that are able to generate an interrupt request is controlled in the external request unit (eru). the eru functionality is described in detail in the scu chapter. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-23 v1.1, 2011-03 interrupt, v1.5 16.9 service request node table table 16-2 shows all TC1798 service request nodes. table 16-2 service request nodes in the TC1798 module no. of nodes description src register cpu 4 cpu service request nodes [3:0] cpu_src[3:0] 1) 1 software breakpoint request node cpu_sbsrc 1) cerberus 2 cerberus/ocds request node[1:0] cbs_src[1:0] lbcu 1 lbcu request node lbcu_src 1) sbcu 1 sbcu request node sbcu_src dma 8 dma service request nodes [7:0] dma_src[7:0] 4 mli0 service request nodes [3:0] dma_mli0src [3:0] 2 mli1 service request nodes [1:0] dma_mli1src [1:0] sdma 8 safety dma service request nodes [7:0] sdma_src[7:0] pcp 12 pcp service request nodes [11:0] pcp_src[11:0] 1) stm 2 stm service request nodes [1:0] stm_src[1:0] scu 4 scu service request nodes [3:0] scu_src[3:0] asc0 4 asc0 transmit interrupt service request node asc0_tsrc asc0 receive interrupt service request node asc0_rsrc asc0 error interrupt service request node asc0_esrc asc0 transmit buffer interrupt service request node asc0_tbsrc asc1 4 asc1 transmit interrupt service request node asc1_tsrc asc1 receive interrupt service request node asc1_rsrc asc1 error interrupt service request node asc1_esrc asc1 transmit buffer interrupt service request node asc1_tbsrc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-24 v1.1, 2011-03 interrupt, v1.5 ssc0 3 ssc0 transmit interrupt service request node ssc0_tsrc 1) ssc0 receive interrupt service request node ssc0_rsrc 1) ssc0 error interrupt service request node ssc0_esrc 1) ssc1 3 ssc1 transmit interrupt service request node ssc1_tsrc 1) ssc1 receive interrupt service request node ssc1_rsrc 1) ssc1 error interrupt service request node ssc1_esrc 1) ssc2 3 ssc2 transmit interrupt service request node ssc2_tsrc 1) ssc2 receive interrupt service request node ssc2_rsrc 1) ssc2 error interrupt service request node ssc2_esrc 1) ssc3 3 ssc3 transmit interrupt service request node ssc3_tsrc 1) ssc3 receive interrupt service request node ssc3_rsrc 1) ssc3 error interrupt service request node ssc3_esrc 1) sscg0 1 ssc0 guardian sscg0_gsrc sscg1 1 ssc1 guardian sscg1_gsrc sscg2 1 ssc2 guardian sscg2_gsrc sscg3 1 ssc3 guardian sscg3_gsrc sent 4 sent [3:0] sent_src[3:0] she 1 secure hardware extension] she_src fce 1 flexible crc engine fce_src bmu 1 bus monitor unit bmu_src msc0 2 msc0 service request nodes [1:0] msc0_src[1:0] msc1 2 msc1 service request nodes [1:0] msc1_src[1:0] can 16 can service request nodes [15:0] can_src[15:0] 1) table 16-2 service request nodes in the TC1798 (cont?d) module no. of nodes description src register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-25 v1.1, 2011-03 interrupt, v1.5 gpta0 38 gpta0 service request nodes [37:00] gpta0_src [37:0] gpta1 38 gpta1 service request nodes [37:00] gpta1_src [37:0] ltca2 8 ltca service request nodes [07:00] ltca2_src[07:00] cc6061 4 cc60 service request nodes [3:0] ccu60_src[3:0] cc6061 4 cc61 service request nodes [3:0] ccu61_src[3:0] cc6263 4 cc62 service request nodes [3:0] ccu62_src[3:0] cc6263 4 cc63 service request nodes [3:0] ccu63_src[3:0] gpt120 6 gpt12_0 service request nodes [05:00] gpt120_src[05:00] gpt121 6 gpt12_1 service request nodes [05:00] gpt121_src[05:00] adc0 9 adc0 service request nodes [8:0] adc0_src[8:0] 1) fadc 4 fadc service request nodes [3:0] fadc_src[3:0] 1) e-ray 8 interrupt 0 service request control register eray_int0src 1) interrupt 1 service request control register eray_int1src 1) timer interrupt 0 service request control register eray_tint0src 1) timer interrupt 1 service request control register eray_tint1src 1) new data 0 service request control register eray_ndat0src 1) new data 1 service request control register eray_ndat1src 1) message buffer status changed 0 service request control register eray_mbsc0src 1) message buffer status changed 1 service request control register eray_mbsc1src 1) 1) these service request registers are not bit-addressabl e because its register address is outside the first 16 kbyte of a segment. table 16-2 service request nodes in the TC1798 (cont?d) module no. of nodes description src register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 interrupt system users manual 16-26 v1.1, 2011-03 interrupt, v1.5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-1 v1.1, 2011-03 stm, v1.6 17 system timer (stm) this chapter describes the system timer (stm). the TC1798?s stm is designed for global system timing applic ations requiring both high precision and long period. 17.1 overview the stm has the following features: ? free-running 56-bit counter ? all 56 bits can be read synchronously ? different 32-bit portions of the 56-bit counter can be read synchronously ? flexible service request generation bas ed on compare match with partial stm content ? counting starts automatically after a reset operation ? stm registers are reset by an application re set if bit arstdis.stmdis is cleared. if bit arstdis.stmdis is set, t he stm registers are not reset. 1) ? stm can be halted in debug/suspend mode (via stm_clc register) special stm register semantics provide syn chronous views of the entire 56-bit counter, or 32-bit subsets at different levels of resolution. the maximum timer period is 2 56 f stm . at f stm = 50 mhz, for example, the stm counts 46.85 years before overflowing. thus, it is capable of continuously timing the entire expected product life time of a system without overflowing. 17.2 operation the stm is an upward counter, running either at the fpi-bus frequency f fpi or at a fraction of it. the stm clock frequency is f stm = f fpi /rmc with rmc = 0-7 (default after reset is f stm = f fpi /2, selected by rmc = 010 b ). rmc is a bit field in register stm_clc. in case of an application reset, the stm is re set if bit scu_arstdis. dis0 is set. after reset, the stm is enabled and immediately starts counting up. it is not possible to affect the content of the timer during normal operation of the TC1798. the timer registers can only be read but not written to. the stm can be optionally disabled for power-saving purposes, or suspended for debugging purposes via its clock control register. in suspend mode of the TC1798 (initiated by writing an appropriate value to stm_clc register), the stm clock is stopped but all registers are still readable. due to the 56-bit width of the stm, it is not possible to read its entire content with one instruction. it needs to be read with two load instructions. since the timer would continue to count between the two load operations, there is a chance that the two values read are not consistent (due to possible overflow from the low part of the timer to the high part 1) ?stm registers? means all registers except stm_clc, stm_src0, and stm_src1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-2 v1.1, 2011-03 stm, v1.6 between the two read operations). to enable a synchronous and consistent reading of the stm content, a capture register (stm_c ap) is implemented. it latches the content of the high part of the stm each time when one of the registers stm_tim0 to stm_tim5 is read. thus, stm_cap holds the upper value of the timer at exactly the same time when the lower part is read. the second read operation would then read the content of the stm_cap to get the complete timer value. the stm can also be read in sections from seven registers, stm_tim0 through stm_tim6, that select increasingly higher-order 32-bit ranges of the stm. these can be viewed as individual 32-bit timers, each with a different resolution and timing range. the content of the 56-bit system timer can be compared against the content of two compare values stored in the stm_cmp0 an d stm_cmp1 registers. service requests can be generated on a compare match of th e stm with the stm_cmp0 or stm_cmp1 registers. figure 17-1 provides an overview on the stm module. it shows the options for reading parts of the stm content. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-3 v1.1, 2011-03 stm, v1.6 figure 17-1 general block diagram of the stm module registers stm module 00 h stm_cap stm_tim6 stm_tim5 00 h 56-bit system timer address decoder clock control mcb06185_mod compare register 0 interrupt control compare register1 application reset stm_tim4 stm_tim3 stm_tim2 stm_tim1 stm_tim0 stm_cmp1 stm_cmp0 enable / disable f stm stm ir0 31 23 15 7 0 31 23 15 7 0 55 47 39 31 23 15 7 0 stm ir1 to dma etc. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-4 v1.1, 2011-03 stm, v1.6 17.2.1 resolution and ranges table 17-1 is an overview on the individual timer registers with their resolutions and timing ranges. as an example, the values for 75 mhz stm input clock frequency f stm are given. table 17-1 system timer resolutions and ranges register stm bits resolution [s] range [s] resolution range f stm [mhz] stm_tim0 [31:0] 1 / f stm 2 32 / f stm 13.3 ns 57.3 s 75 stm_tim1 [35:4] 16 / f stm 2 36 / f stm 213 ns 916.2 s stm_tim2 [39:8] 256 / f stm 2 40 / f stm 3.41 s 244.3 min stm_tim3 [43:12] 4096 / f stm 2 44 / f stm 54.6 s 65.1 h stm_tim4 [47:16] 65536 / f stm 2 48 / f stm 0.874 ms 43.44 days stm_tim5 [51:20] 2 20 / f stm 2 52 / f stm 13.98 ms 1.90 yr stm_tim6 [55:32] 2 32 / f stm 2 56 / f stm 57.3 s 30.47 yr stm_cap [55:32] 2 32 / f stm 2 56 / f stm 57.3 s 30.47 yr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-5 v1.1, 2011-03 stm, v1.6 17.2.2 compare register operation the content of the 56-bit stm can be compared against the content of two compare values stored in the stm_cmp0 and stm_ cmp1 registers. service requests can be generated on a compare match of the st m with the stm_cmp0 or stm_cmp1 registers. two parameters are programmab le for the compare operation: 1. the width of the relevant bits in registers stm_cmp0/stm_cmp1 (compare width msizex) that is taken for the compare operation can be programmed from 1 to 32. 2. the first bit location in the 56-bit stm th at is taken for the compare operation can be programmed from 0 to 24. these programming capabilities make compare functionality ve ry flexible. it even makes it possible to detect bit transitions of a single bit n (n = 0 to 24) within the 56-bit stm by setting msize = 0 and mstart = n. figure 17-2 compare mode operation figure 17-2 shows an example of the compare operation. in this example the following parameters are programmed: ? msize0 = 10001 b = 17 d ; mstart0 = 01010 b = 9 d ? msize1 = 00111 b = 7 d ; mstart1 = 00111 b = 6 d 56-bit system timer compare register 0 equal ? compare match event with stm_cmp0 register mca06186_mod msize0 mstart0 msizex mstartx = 0-31 = 0-24 msize1 equal ? compare match event with stm_cmp1 register mstart1 compare register 1 stm_cmp1 stm_cmp0 31 23 15 7 55 47 39 31 23 15 7 31 23 15 7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-6 v1.1, 2011-03 stm, v1.6 a compare operation with msize not equal 0 always implies that the compared value as stored in the cmp register is right-extended wi th zeros. this means that in the example of figure 17-2 , the compare register content stm_cmp0[17:0] plus nine zero bits right- extended is compared with stm[27:0] with stm[8:0] = 000 h . in case of register stm_cmp1, stm[14:0] with stm[5:0] = 00 h are compared with stm_cmp1[8:0] plus six zero bits right-extended. 17.2.3 compare match interrupt control the compare match interrupt control logic is shown in figure 17-3 . each stm_cmpx register has its compare match interrupt reque st flag (stm_icr.cmpxir) that is set by hardware on a compare match event. the interrupt request flags can be set (stm_issr.cmpxirs) or cleared (stm_issr.cmpxirr) by software. note that setting stm_icr.cmpxir by writing a 1 into stm_issr.cmpxirs does not generate an interrupt at stmirx. the compare match interrupts from cmp0 and cmp1 can be further directed by stm_icr.cmpxos to either output signal stmir0 or stmir1. the stmir0 and stmir1 outputs are each connected to interrupt service request control registers, stm_src0 and stm_scr1, respectively. figure 17-3 stm interrupt control the compare match interrupt flags stm_icr. cmpxir are immediately set after an stm reset operation, caused by a compare match event with the reset values of the stm and the compare registers stm_cmpx. this setting of the cmpxir flags does not directly mca06187_mod compare match event from cmp 0 register set cmp0 ir cmp0 os cmp0 en cmp1 ir cmp1 os cmp1 en compare match event from cmp 1 register set 31 31 0 1 stmir0 stmir1 stm_icr register cmp0 irr cmp1 irr cmp1 irs cmp0 irs stm_isrr reg. set clear set clear 0 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-7 v1.1, 2011-03 stm, v1.6 generate compare match interrupts because the compare match interrupts are automatically disabled after a stm reset operation (cmpxen = 0). therefore, before enabling a compare match interrupt after a stm reset operation, the cmpxir flags should be cleared by software (writing register stm_issr with cmpxirr set). otherwise, undesired compare match interrupt events are triggered. details about dma connections of stmir0 and stmir1 are given in table 17-4 on page 17-21 . 17.3 stm registers this section describes the stm registers of the stm. the stm registers can be divided into four types, as shown in figure 17-4 . stm registers overview figure 17-4 stm registers in TC1798 all registers are readable is suspend mode. the complete and detailed address map of the stm module with its registers is shown in table 17-5 on page 17-22 . table 17-2 registers address space module base address end address note stm f000 0200 h f000 02ff h - mca06188_mod stm_tim0 timer/capture registers stm_tim1 stm_tim2 stm_tim3 stm_tim4 stm_tim5 stm_tim6 stm_cap compare registers stm_cmp0 stm_cmp1 interrupt registers stm_icr stm_isrr stm_cmcon module control register stm_clc stm_src0 stm_src1 stm_id www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-8 v1.1, 2011-03 stm, v1.6 table 17-3 registers overview - stm registers register short name register long name offset address description see stm_clc 1) 1) these registers are reset by an application reset if bit arstdis.stmdis is set. stm clock control register 00 h page 17-9 stm_id stm module identification register 08 h page 17-10 stm_tim0 stm timer register 0 10 h page 17-11 stm_tim1 stm timer register 1 14 h page 17-11 stm_tim2 stm timer register 2 18 h page 17-12 stm_tim3 stm timer register 3 1c h page 17-12 stm_tim4 stm timer register 4 20 h page 17-12 stm_tim5 stm timer register 5 24 h page 17-13 stm_tim6 stm timer register 6 28 h page 17-13 stm_cap stm timer capture register 2c h page 17-14 stm_cmp0 stm compare register 0 30 h page 17-14 stm_cmp1 stm compare register 1 34 h page 17-14 stm_cmcon stm compare match control register 38 h page 17-15 stm_icr stm interrupt control register 3c h page 17-17 stm_isrr stm interrupt set/reset register 40 h page 17-19 stm_src1 1) stm service request control register 1 f8 h page 17-20 stm_src0 1) stm service request control register 0 fc h page 17-20 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-9 v1.1, 2011-03 stm, v1.6 17.3.1 clock control register the stm clock control register is used to switch the stm on or off and to control its input clock rate. after a power-on reset, the stm is always enabled and starts counting. the stm can be disabled by setting bit disr to 1. stm_clc stm clock control register (00 h ) reset value: 0000 0200 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0rmc0 fs oe sb we e dis sp en dis s dis r r rw r rwwrwrw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the stm module. 0 b no disable requested 1 b disable requested diss 1r module disable status bit bit indicates the current status of the stm module. 0 b stm module is enabled 1 b stm module is disabled spen 2rw module suspend enable for ocds used for enabling the suspend mode. edis 3rw sleep mode enable control used for module sleep mode control. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. fsoe 5rw fast switch off enable used for fast clock switch off in ocds suspend mode. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-10 v1.1, 2011-03 stm, v1.6 the stm module identification register id contains read-only information about the module version. rmc [10:8] rw clock divider in run mode 000 b no clock signal f stm generated 001 b clock signal f stm = f fpi selected 010 b clock signal f stm / 2 selected (default after reset) 011 b clock signal f stm / 3 selected ... 111 b clock signal f stm / 7 selected 0 [7:6], [31:11] r reserved read as 0; should be written with 0. stm_id stm module identifi cation register (08 h ) reset value: 0000 c0xx h 31 0 modnum modtype modrev rrr field bits type description modrev [7:0] r module revision number modrev defines the module revision number. the value of a module revision starts with 01 h (first revision). modtype [15:8] r module type this bit field defines the module as a 32-bit module: c0 h modnum [31:16] r module number value this bit field defines the module identification number for the stm: 0000 h field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-11 v1.1, 2011-03 stm, v1.6 17.3.2 timer/capture registers registers stm_tim1 to stm_tim6 provide 32-bit views at varying resolutions of the underlying stm counter. stm_tim0 stm timer register 0 (10 h ) reset value: 0000 0000 h 31 0 stm[31:0] r field bits type description stm[31:0] [31:0] r system timer bits [31:0] this bit field contains bits [31:0] of the 56-bit stm. stm_tim1 stm timer register 1 (14 h ) reset value: 0000 0000 h 31 0 stm[35:4] r field bits type description stm[35:4] [31:0] r system timer bits [35:4] this bit field contains bits [35:4] of the 56-bit stm. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-12 v1.1, 2011-03 stm, v1.6 stm_tim2 stm timer register 2 (18 h ) reset value: 0000 0000 h 31 0 stm[39:8] r field bits type description stm[39:8] [31:0] r system timer bits [39:8] this bit field contains bits [39:8] of the 56-bit stm. stm_tim3 stm timer register 3 (1c h ) reset value: 0000 0000 h 31 0 stm[43:12] r field bits type description stm[43:12] [31:0] r system timer bits [43:12] this bit field contains bits [43:12] of the 56-bit stm. stm_tim4 stm timer register 4 (20 h ) reset value: 0000 0000 h 31 0 stm[47:16] r field bits type description stm[47:16] [31:0] r system timer bits [47:16] this bit field contains bits [47:16] of the 56-bit stm. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-13 v1.1, 2011-03 stm, v1.6 stm_tim5 stm timer register 5 (24 h ) reset value: 0000 0000 h 31 0 stm[51:20] r field bits type description stm[51:20] [31:0] r system timer bits [51:20] this bit field contains bits [51:20] of the 56-bit stm. stm_tim6 stm timer register 6 (28 h ) reset value: 0000 0000 h 31 24 23 0 0 stm[55:32] rr field bits type description stm[55:32] [23:0] r system timer bits [55:32] this bit field contains bits [55:32] of the 56-bit stm. 0 [31:24] r reserved read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-14 v1.1, 2011-03 stm, v1.6 note: the bits in registers stm_cap to stm_tim0 are all read-only bits. 17.3.3 compare registers the compare register cmpx holds up to 32-bits; its value is compared to the value of the stm. stm_cap stm timer capture register (2c h ) reset value: 0000 0000 h 31 24 23 0 0 stm_cap[55:32] rr field bits type description stm[55:32] [23:0] r captured system timer bits [55:32] the capture register stm_ cap always captures the stm bits [55:32] when one of the registers stm_tim0 to stm_tim5 is read. this capture operation is performed in order to enable software to operate with a coherent value of all the 56 stm bits at one time stamp.this bit field contains bits [55:32] of the 56-bit stm. 0 [31:24] r reserved read as 0. stm_cmpx (x = 0-1) stm compare register x (30 h +x*4 h ) reset value: 0000 0000 h 31 0 cmpval rw field bits type description cmpval [31:0] rw compare value of compare register x this bit field holds up to 32 bits of the compare value (right-adjusted). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-15 v1.1, 2011-03 stm, v1.6 the stm compare match control register controls the parameters of the compare logic. stm_cmcon stm compare match control register (38 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0mstart10 msize1 rrwrrw 1514131211109876543210 0mstart00 msize0 rrwrrw field bits type description msize0 [4:0] rw compare register size for cmp0 this bit field determines the number of bits in register cmp0 (starting from bit 0) that are used for the compare operation with the system timer. 00000 b cmp0[0] used for compare operation 00001 b cmp0[1:0] used for compare operation ... 11110 b cmp0[30:0] used for compare operation 11111 b cmp0[31:0] used for compare operation mstart0 [12:8] rw start bit location for cmp0 this bit field determines the lowest bit number of the 56-bit stm that is compared with the content of register cmp0 bit 0. the number of bits to be compared is defined by bit field msize0. 00000 b stm[0] is the lowest bit number 00001 b stm[1] is the lowest bit number ... 10111 b stm[23] is the lowest bit number 11000 b stm[24] is the lowest bit number bit combinations 11001 b to 11111 b are reserved and must not be used. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-16 v1.1, 2011-03 stm, v1.6 msize1 [20:16] rw compare register size for cmp1 this bit field determines the number of bits in register cmp1 (starting from bit 0) that are used for the compare operation with the system timer. 00000 b cmp1[0] used for compare operation 00001 b cmp1[1:0] used for compare operation ... 11110 b cmp1[30:0] used for compare operation 11111 b cmp1[31:0] used for compare operation mstart1 [28:24] rw start bit location for cmp1 this bit field determines the lowest bit number of the 56-bit stm that is compared with the content of register cmp1 bit 0. the number of bits to be compared is defined by bit field msize1. 00000 b stm[0] is the lowest bit number 00001 b stm[1] is the lowest bit number ... 10111 b stm[23] is the lowest bit number 11000 b stm[24] is the lowest bit number bit combinations 11001 b to 11111 b are reserved and must not be used. 0 [7:5], [15:13], [23:21], [31:29] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-17 v1.1, 2011-03 stm, v1.6 17.3.4 interrupt registers the two compare match interrupts of the stm are controlled by the stm interrupt control register. stm_icr stm interrupt control register (3c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 cmp 1 os cmp 1 ir cmp 1 en 0 cmp 0 os cmp 0 ir cmp 0 en r rw rh rw r rw rh rw field bits type description cmp0en 0rw compare register cmp0 interrupt enable control this bit enables the compare match interrupt with compare register cmp0. 0 b interrupt on compare match with cmp0 disabled 1 b interrupt on compare match with cmp0 enabled cmp0ir 1rh compare register cmp0 interrupt request flag this bit indicates whether or not a compare match interrupt request of compare register cmp0 is pending. cmp0ir must be cleared by software. 0 b a compare match interrupt has not been detected since the bit has been cleared for the last time. 1 b a compare match interrupt has been detected. cmpir0 must be cleared by software and can be set by software, too (see cmpisrr register). after a stm reset operation, cmp0ir is immediately set as a result of a compare match event with the reset values of the stm and the compare registers cmp0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-18 v1.1, 2011-03 stm, v1.6 cmp0os 2rw compare register cmp0 interrupt output selection this bit determines the interrupt output that is activated on a compare match event of compare register cmp0. 0 b interrupt output stmir0 selected 1 b interrupt output stmir1 selected cmp1en 4rw compare register cmp1 interrupt enable control this bit enables the compare match interrupt with compare register cmp1. 0 b interrupt on compare match with cmp1 disabled 1 b interrupt on compare match with cmp1 enabled cmp1ir 5rh compare register cmp1 interrupt request flag this bit indicates whether or not a compare match interrupt request of compare register cmp1 is pending. cmp1ir must be cleared by software. 0 b a compare match interrupt has not been detected since the bit has been cleared for the last time. 1 b a compare match interrupt has been detected. cmpir1 must be cleared by software and can be set by software, too (see cmpisrr register). after a stm reset, cmp1ir is immediately set as a result of a compare match event with the reset values of the stm and the compare register cmp1. cmp1os 6rw compare register cmp1 interrupt output selection this bit determines the interrupt output that is activated on a compare match event of compare register cmp1. 0 b interrupt output stmir0 selected 1 b interrupt output stmir1 selected 0 3, [31:7] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-19 v1.1, 2011-03 stm, v1.6 the bits in the stm interrupt set/reset regist er make it possible to set or cleared the compare match interrupt request status flags of register icr. note: reading register cmisrr always returns 0000 0000 h . stm_isrr stm interrupt set/ reset register (40 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 cmp 1 irs cmp 1 irr cmp 0 irs cmp 0 irr r wwww field bits type description cmp0irr 0w reset compare register cmp0 interrupt flag 0 b bit icr.cmp0ir is not changed. 1 b bit icr.cmp0ir is cleared. cmp0irs 1w set compare register cmp0 interrupt flag 0 b bit icr.cmp0ir is not changed. 1 b bit icr.cmp0ir is set. the state of bit cmp0irr is ?don?t care? in this case. cmp1irr 2w reset compare register cmp1 interrupt flag 0 b bit icr.cmp1ir is not changed. 1 b bit icr.cmp1ir is cleared. cmp1irs 3w set compare register cmp1 interrupt flag 0 b bit icr.cmp1ir is not changed. 1 b bit icr.cmp1ir is set. the state of bit cmp1irr is ?don?t care? in this case. 0 [31:4] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-20 v1.1, 2011-03 stm, v1.6 in the TC1798, the compare match interrupt output signals of the stm, stmir0 and stmir1 are controlled by the stm service request control registers stm_src0 and stm_src1. stm_src0 stm service request control register 0 (fc h ) reset value: 0000 0000 h stm_src1 stm service request control register 1 (f8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-21 v1.1, 2011-03 stm, v1.6 17.4 stm module implementation this section defines implementation specific details of the stm in the TC1798. 17.4.1 on-chip service request connections the two compare match service request out puts stmir0 and stmir1 are connected in the TC1798 to on-chip devices as described in table 17-4 . 17.4.2 stm address map table 17-5 defines the complete address range of the stm with absolute addresses and the read/write access rights. table 17-4 system timer on-chip interconnections service request signal connected to stmir0 dma channel 00 request input 8 dma channel 01 request input 8 dma channel 02 request input 8 dma channel 03 request input 8 dma channel 04 request input 8 dma channel 05 request input 8 dma channel 06 request input 8 dma channel 07 request input 8 dma channel 10 request input 8 dma channel 11 request input 8 dma channel 12 request input 8 dma channel 13 request input 8 dma channel 14 request input 8 dma channel 15 request input 8 dma channel 16 request input 8 dma channel 17 request input 8 stmir1 adc0_reqgt[4:0]_5 adc1_reqgt[4:0]_5 adc2_reqgt[4:0]_5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 system timer (stm) users manual 17-22 v1.1, 2011-03 stm, v1.6 table 17-5 address map of stm short name description address access mode reset value read write system timer (stm) stm_clc stm clock control register f000 0200 h u, sv sv, e 0000 0200 h ? reserved f000 0204 h be be ? stm_id stm module identification register f000 0208 h u, sv be 0000 c0xx h ? reserved f000 020c h be be ? stm_tim0 stm timer register 0 f000 0210 h u, sv u, sv 0000 0000 h stm_tim1 stm timer register 1 f000 0214 h u, sv u, sv 0000 0000 h stm_tim2 stm timer register 2 f000 0218 h u, sv u, sv 0000 0000 h stm_tim3 stm timer register 3 f000 021c h u, sv u, sv 0000 0000 h stm_tim4 stm timer register 4 f000 0220 h u, sv u, sv 0000 0000 h stm_tim5 stm timer register 5 f000 0224 h u, sv u, sv 0000 0000 h stm_tim6 stm timer register 6 f000 0228 h u, sv u, sv 0000 0000 h stm_cap stm timer capture reg. f000 022c h u, sv u, sv 0000 0000 h stm_cmp0 stm compare register 0 f000 0230 h u, sv u, sv 0000 0000 h stm_cmp1 stm compare register 1 f000 0234 h u, sv u, sv 0000 0000 h stm_ cmcon stm compare match control register f000 0238 h u, sv u, sv 0000 0000 h stm_icr stm interrupt control register f000 023c h u, sv u, sv 0000 0000 h stm_isrr stm interrupt set/reset register f000 0240 h u, sv u, sv 0000 0000 h ? reserved f000 0244 h - f000 02f4 h be be ? stm_ src1 stm service request control register 1 f000 02f8 h u, sv u, sv 0000 0000 h stm_ src0 stm service request control register 0 f000 02fc h u, sv u, sv 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-1 v1.1, 2011-03 bmu, v2.6 18 bus monitor unit (bmu) this document describes the functionality of the bus monitor unit (bmu). the bmu is primarily intended to be used in high integrit y safety applications. it provides the base hardware mechanisms to simplify the monitori ng functions that safety applications need to implement. the core functionality of the bmu consists of logging the peripheral bus write activity. the logged information is st ored in a local buffer managed as a cyclic buffer. in non-safety applications the bmu can be used as a pcp data memory extension. the bmu operates as a standa rd fpi bus slave peripheral and is fully controlled through a set of configuration and control registers. additionally a dedicated slave interface enables burst accesses to the logged information. this chapter is structured as follows: ? bmu features (see section 18.2 ) ? an operational overview of the bmu module (see section 18.3 ) ? functional description of the bmu module (see section 18.4 ) ? interfaces of the bmu module (see section 18.5 ) ? description of the bmu module registers (see section 18.6 ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-2 v1.1, 2011-03 bmu, v2.6 18.1 related documentation input documents ? [d1] pro-sil safety concept for microcontrollers related standards and norms ? [s1] iec61508 standard. functional safety of electrical/electronic/programmable electronic safety-rela ted systems parts 2,7. ? [s2] iso26262 standard. road vehicles - functional safety - part 5: product development: hardware level www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-3 v1.1, 2011-03 bmu, v2.6 18.2 bmu features the bmu implements the following features: ? fully synchronous module running at the peripheral bus clock frequency ? implements a standard interrupt service node connecting to the tricore and pcp interrupt busses. ? every internal interrupt source can be identified by a dedicated status flag, cleared by software only. new interrupt events with an active status flag do not lead to a new interrupt. ? logs write transactions to software selectable peripheral address space ? uses the system-on-chip address decoders select lines to qualify target peripherals (no internal address space decoding) ? the address phase from master accesses initiated by the secure hardware extension module can optionally be logged. data phase information is excluded because of secure keys exchange (the address map of the she is not visible to the bmu). ? implements a bus transaction fifo (btf) that can be accessed via the fpi slave interface using btr2, btr4 or btr8 fpi read bursts. the size of the btf can be configured on a product basis. it must be a power of two in size. ? the btf entries are protected by error correction codes (ecc) with single-bit error correction and double-bit error detection capability (secded) covering the data field. ? the btf is accessed as a cyclic buffer wi th automatic wrap around support. the btf write and read pointers are controlled by hardware. ? the btf entries are made of the following fpi information: ? fpi_a[27:2] address bits of the fpi transaction. ? fpi_svm fpi supervisor mode indication ? fpi_tag[3:0] fpi tag, identifies the fpi bus master ? fpi_status transaction completion status. this is not an fpi signal ? fpi_d[31:0] fpi write data ? fifo handler that monitors the fullness of the btf: ? implements a configurable threshold register to early detect fullness threshold. ? detects and prevents overruns and underruns (configurable). ? the btf can be used as a standard memory mapped sram in non-safety applications. the sram can only be accessed using btr2, btr4 or btr8 fpi bursts. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-4 v1.1, 2011-03 bmu, v2.6 18.3 operational overview 18.3.1 microcontroller monitoring framework the bmu is a component of the pro-sil tm monitoring framework that enables to simplify the overall software monitoring requirements a safety application must fulfil. two practical use cases are presented that directly take benefit of the bmu: ? break-after-make flow ? detection of illegal access to safety-related configuration and status registers (csfr) break-after-make use case in a single processing channel (a microcontr oller without hardware redundancy at the application level) there are two common architectures dealing with the detection of failures at the execution level: ? two processors running in static lockstep or loosely coupled lockstep mode, executing the same safety code and comparing the resu lts in a near cycle accurate fashion. any discrepancy between the master cpu and the checker cpu caused by any soft or hardware fault is captured by an independent compare unit. the checker cpu does not produce any data to the peripherals nor to the storage elements (srams). the lockstep flow is presented in figure 18-1 ?break-after-make concept? on page 18-5 (left side). ? a single processor runs sequentially two redundant tasks. the redundant tasks can be implemented with diversity. there is a control task (or control execution thread) that executes and commits its results to the peripherals. the results from the control task need to be saved in order to be checked at a later time. the monitor task (or monitor execution thread) is then scheduled and produces an alternate set of data. the results of both tasks/threads are gathered and compared by an hardware unit independent to the processor. the control flow is presented in figure 18-1 ?break- after-make concept? on page 18-5 (right side). this is the basic scheme used in the pro-sil tm safety concept. the combination of the bmu hardware and the bmu driver running on the pcp provide a generic mechanism that can be used by safety applications to monitor specific data flows to safety-relevant peripherals. the bmu software driver specification is not in the scope of this document. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-5 v1.1, 2011-03 bmu, v2.6 figure 18-1 break-a fter-make concept cpu0 control cpu1 monitor instruction cache shared bus compare (hw) data srams cpu0 log control thread monitor thread control thread logger (bmu) shared bus monitor thread logger (pcp) compare (pcp) log instruction cache data srams time sam e code executes concur rently lockstep architecture break-before-make lockstep emulation ? break-after-make peripheral peripheral redundant code executes sequentially www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-6 v1.1, 2011-03 bmu, v2.6 18.3.2 bus monitor unit overview the bmu is a standard fpi slave module that implements a fpi slave interface and a bus peripheral interface (bpi) compliant with the fpi bus architecture. the bmu is not fpi master capable. the bmu is fully synchronous with the fpi bus clock and runs with a 1:1 clock ratio. it does not implement a fractional divider figure 18-2 bmu overview in addition to the standard fpi connectivity, the bmu also receives the individual peripheral select signals decoded by the address decoders. the granularity of each select line is not a peripheral but a fpi region that may include several peripherals . each decoded region provides a fpi_ack[1:0] signal that indicates the completion status of each individual data phase. the fpi_ack[1:0] of the fpi regions listed in table 18-4 ?identification of fpi regions? on page 18-22 are required by the bmu to determine if write transactions have been normally terminated or not. peripherals (fpi slaves ) peripherals (fpi slaves ) bus monitor unit (bmu) peripherals (spb slaves) slave interface m onitor ing port transact ion fifo entry = {addr, data, master id } addr ess decoder bmu _cs system control unit (sc u ) f spb application reset system peripheral bus (spb) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-7 v1.1, 2011-03 bmu, v2.6 figure 18-3 bmu operation in TC1798 in a typical microcontroller architecture, t he write accesses to the peripherals can be directly controlled by the tricore cpu or via dma engines and possibly by the peripheral control processor (pcp). in the TC1798 microcontroller four possible masters (see figure 18-3 ?bmu operation in TC1798? on page 18-7 ) can control the write data accesses to the peripherals. logging she write transaction in the TC1798 microcontroller the secure hardware extension (she) module also implements a dma capability but is not supposed to perform write accesses to per ipherals in a safety application. because the she module is used in security applications, logging of data written into the she is forbidden. for debug purposes it is possible to log the address of write accesses performed by the she module, the write data from the fpi bus is ignored and replaced by all zeros. the four upper bits of the address and the two lower bits of the address generated by the she module are not logged. the only way to identify that the logging information is related to a she write transaction is by using the master identifier information that is logged into the bmu (see figure 18-5 ?bus transaction information? on page 18-12 ). peripherals (fpi slaves) peripherals (fpi slaves) TC1798 system peripheral bus (fpi protocol) bus monitor unit (bmu) peripherals (fpi slaves) fpi master (bridge) fpi master (pcp2) fpi master (dma) m s m s m s bpi fpi master (safedma) m s select signal from address map decoders fpi master (she) m s slave interface bpi select port www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-8 v1.1, 2011-03 bmu, v2.6 18.4 bmu functional description 18.4.1 bmu microarchitecture figure 18-4 bmu microarchitecture the bmu is made of the following functions as represented in figure 18-4 ?bmu microarchitecture? on page 18-8 : interrupt generation bus peripheral interface control registers btf bus transaction fifo (cyclic buffer ) (ecc) fifo monitor overflow underflow threshold fifo monitor registers write pointer monitoring registers bmu bpi address decoder w rite interface (ecc encode) slave interface system peripheral bus data response read interface (ecc decode) writ e enable bpi select port peripheral pn address decoder transaction filter select signals read pointer fpi _ack[ 1:0 ] peri pheral fpi ack port a, d, ctrl bmu_sel bmuram address decoder bcu bmuram_sel bmu interrupt www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-9 v1.1, 2011-03 bmu, v2.6 ? a fpi bus peripheral interface (bpi) that allows software to control the features of the bmu and read status information. ? a cyclic buffer called the bus transaction fifo (btf) where the selected write transaction are stored. ? a fifo monitor that monitors the distance between the btf write and read pointers. the fifo monitor is configured with a threshold register fmth that enables the bmu to raise an interrupt if the threshold is reached. ? a fpi slave interface that provides the following functions: ? filter write transactions taking place in the bus, and if all conditions are fulfilled write the information inside the btf. the hardware is responsible for the write pointer wrap around conditions. ? perform memory mapped read and write accesses to the bmu ram. this mode is the default one a fter power-on reset. refer to section ?usage in non safety applications? on page 18-20 for a description of this mode. the bmu ram is intended to be use by the pcp processor. ? perform fifo-based accesses to the btf to read the logged information. this mode should be enabled in the ctl register. in fifo mode, the fpi_a[31:0] address information is not used to directly access an entry in the btf. the internal read and write pointers are updated according to the size of the fpi bus burst transaction. ? table 18-1 ?fpi access modes to bmu fpi slave interface? on page 18-10 provides the list of fpi transactions supported by the slave interface in the different modes. ? a service request node that centralizes all internal interrupt sources and enables the bmu to directly send interrupt requests to the pcp or the tricore cpus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-10 v1.1, 2011-03 bmu, v2.6 note: single transfer transactions (sdtb, sdth,sdtw) part of a read-modify-write are logged as well. note: during any sdtb, sdth single transfer transactions the whole 32-bit data bus is written. as the fpi opcode and the lowe r two bits of the fpi address are not logged, it is not possible to know which by tes were valid during the write. this is a limitation that should be c onsidered by the data monitoring applications using the bmu. table 18-1 fpi access modes to bmu fpi slave interface fpi transaction fpi_opc[3:0] transaction logging in fifo mode transaction support in fifo mode transaction support in sram mode sdtb (8-bit single transfer) read not applicable no (bus error) no (bus error) write yes no (bus error) no (bus error) sdth (16-bit single transfer) read not applicable no (bus error) no (bus error) write yes no (bus error) no (bus error) sdtw (32-bit single transfer) read not applicable no (bus error) no (bus error) write yes no (bus error) no (bus error) btr2 (2 transfers of 32-bit) read not applicable yes yes write yes no (bus error) yes btr4 (4 transfers of 32-bit) read not applicable yes yes write yes no (bus error) yes btr8 (8 transfers of 32-bit) read not applicable yes yes write yes no (bus error) yes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-11 v1.1, 2011-03 bmu, v2.6 18.4.2 handling of fpi corner cases there are specific situations that lead to exceptions with respect to the correct termination of a fpi write transaction, like: master aborts, slave retries, time-out,... the flag fpi_status indicates if the write data phase has been normally completed (fpi_status = 1) or not (fpi_status = 0) . in the case of an error there is no additional information that defines the nature of the error. a data phase is completed when the target bpi interface issues a fpi_rdy=1; the signal fpi_ack[1:0] provides additional information about the status of the completion. the bpi can insert wait states in the fpi bus by delaying the assertion of fpi_rdy. the following situations lead to the detection of an error condition indicating that a write data phase has been either aborted by the master or not accepted by the slave: ? the fpi master fpi_abort_n is asserted during the data phase wait states or coincides with the fpi_rdy assertion by the bpi. if this happens during a burst all subsequent data phases are aborted. ? the bpi issues fpi_rdy=1 together with fpi_ack=2?b11 (err). ? the bpi issues fpi_rdy=1 together with fpi_ack=2?b10 (rty). ? in the occurrence of a timeout, fpi_tout is issued by the bus control unit during one clock cycle and the selected slave must te rminate the data tran sfer with an error condition (fpi_rdy=1 with fpi_ack=2?b11) in the following cycle. therefore the fpi_tout does not need to be handled by bmu. please refer to the fpi specification version v4.2, 2003-11 chapter 6: fpi bus termination conditions for a detailed overview. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-12 v1.1, 2011-03 bmu, v2.6 18.4.3 bus transaction table the figure 18-5 ?bus transaction information? on page 18-12 defines how each phase of a fpi transaction is written into the btf. the set of information bits related to a write data is written as a 64-bit value into the btf. a btf word or entry is made of: ? the write data itself, referred as the btf[dataphase] field and ? the btf[control] field figure 18-5 bus transaction information the logging of burst transactions follows the sa me rules as for single write transactions: the fpi master provides for each data phase the corresponding address information. examples with single write and burst are given in figure 18-6 ?logging information for fpi burst transactions? on page 18-13 . the address information shown is directly the information present in the fpi bus. fpi_d[31:0] fpi_a[27:2] fpi_tag[3:0] btf[dataphase ] btt[control] 0 0 31 spb protocol (fpi) information mapping to btf 30 information available during fpi address phase fpi_ status is not a standar d fpi signal , it encodes information available during fpi data phase and defining the com pletion status of a tr ansaction fpi_status 31 0 btf[control] btf[dataphase ] 31 32 63 25 26 29 fpi_ svm www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-13 v1.1, 2011-03 bmu, v2.6 figure 18-6 logging information for fpi burst transactions ecc[7:0] 0 btf[0][control] {fpi_a[27:2]} btf[0 ] [dat aphase ] ... ... ... ... btf[9][control] {fpi_a[27:2]} btf[9 ] [dat aphase ] transaction 0 : sdtw transaction 2: sdtw 31 32 63 64 71 btf[10][control] {fpi_a[27:2]} btf[10 ] [dat aphase 1 ] transaction 3: btr2 btf[11 ][control] { fpi_a[27 :2 ] + 0x 1} btf[11 ] [dat aphase 2 ] btf[12][control] {fpi_a[27:2]} btf[12 ] [dat aphase 1 ] btf[13 ][control] { fpi_a[27 :2 ] + 0x 1} btf[13 ] [dat aphase 2 ] btf[14 ] [dat aphase 3 ] btf[15 ] [dat aphase 4 ] btf[14 ][control] { fpi_a[27 :2 ] + 0x 2} btf[15 ][control] { fpi_a[27 :2 ] + 0x 3} transaction 4: btr4 note : fpi pr otocol pr ovides addr ess for each data phase btf[1][control] {fpi_a[27:2]} btf[1 ] [dat aphase 1] btf[2][control] {fpi_a[27:2] + 0x1} btf[2 ] [dat aphase 2] btf[3][control] {fpi_a[27:2] + 0x2} btf[3 ] [dat aphase 3] btf[4][control] {fpi_a[27:2] + 0x3} btf[4 ] [dat aphase 4] btf[5][control] {fpi_a[27:2] + 0x4} btf[5 ] [dat aphase 5] btf[6][control] {fpi_a[27:2] + 0x5} btf[6 ] [dat aphase 6] btf[7][control] {fpi_a[27:2] + 0x6} btf[7 ] [dat aphase 7] btf[8][control] {fpi_a[27:2] + 0x7} btf[8 ] [dat aphase 8] transaction 1: btr8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-14 v1.1, 2011-03 bmu, v2.6 18.4.4 write operation and fifo structure figure 18-7 btf cyclic buffe r write pointer management the write pointer is controlled by the bmu internal logic. if n is the number of words in the btf (corresponding a maximum of n single write fpi transactions), when the write pointer reaches the word at position n-1 and a new single write fpi transaction is logged, the new position of the write pointer is 0. if in the meantime no read pointer update took place, the btf is declared full. 0 1 n-2 n-1 wptr rptr y wptr wptr write pointer after one transaction recording write pointer after y transaction recording wptr write pointer after n-2 transaction recording 0 1 n-2 n-1 2 2xr rptr wptr used entries free entries btf st at us after n+2 single writes and 2xr single reads wptr w r ap ar ound after a btr4 write burst www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-15 v1.1, 2011-03 bmu, v2.6 18.4.5 read operation and fifo structure figure 18-8 btf cyclic buffe r read pointe r management the read pointer ( rptr in figure 18-7 ) is also only controlled by hardware. depending on the fpi transaction size given by the fpi_opc[3:0] opcode the read pointer is incremented accordingly . a btr2 read burst will increment the read pointer by 2 and so on. the fpi_a[31:0] address information is not used to directly access an entry in the btf. the fpi_a[31:0] shall point to the base address of the btf sram, otherwise a bus error will be returned with the firs t read data terminatin g the fpi burst. having the read pointer controlled by hardware ena bles to free the fifo space in a faster way, increasing the logging performance. 0 1 n-2 n-1 2 3 4 6 rptr wptr 5 rptr rptr readpointer after a btr2 read transaction to btf readpointer after a btr4 read transaction to btf 0 1 n-2 n-1 rptr wptr rptr readpointer after several read transaction to btf leading to an em pty s ta te write pointer wrap around at fifo boundary after a btr4 write burst read pointer wrap around at fifo boundary after a btr 2 read burst www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-16 v1.1, 2011-03 bmu, v2.6 18.4.6 fullness monitoring the figure 18-9 ?btf fullness monitoring? on page 18-16 shows how the fullness is calculated in order to check if the fullness threshold defined by the register fmth is reached or not. the buffersize is a constant value defining the number of 64-bit words of the internal sram building the bus transaction fifo. figure 18-9 btf fullness monitoring the fullness information is computed dynamically based on the contents of the read and write pointers and the corresponding events (write pulse/read pulse indicators). for convenience the fullness information (see figure 18-9 ?btf fullness monitoring? on page 18-16 ) is made visible to software via the fullness registers. if a write event takes place and the next position of the write pointer is identical to the read pointer and if no read event takes place the btf is declared full . if a read event only takes place and the value of the read pointer equals the value of the write pointer the btf is declared empty . hardware fifo handler ? fullness calculation rptr wptr if ( wptr >= rptr ) { usedcells = wptr - rptr; freecells = bsize - (wptr - rptr ) } buffersize emptycells rptr wptr if ( wptr < rptr ) { usedcells = bsize - (rptr - wptr ); freecells = (rptr - wptr ) } buffersize linear increasing address usedcells usedcells usedcells emptycells emptycells www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-17 v1.1, 2011-03 bmu, v2.6 figure 18-10 btf fullness monitoring - threshold interrupts figure 18-10 ?btf fullness monitoring - threshold interrupts? on page 18-17 shows the fullness conditions that can be reported by the fifo monitor: ? [1] the fullness reaches or crosses the high threshold level as configured in the register fmth . if the corresponding bit is set in the fmctl register an interrupt is triggered to the interrupt service request node and the corresponding flag is set in the fmsts register. the flag is set regardl ess of the interrupt generation mode. ? [2] the btf is full. a new write access is detected leading to an overrun condition. the interrupt reporting is similar to the one described for the case [1]. the write pointer is not incremented and the fpi transaction information is not logged. if the overrun situation occurs during a burst tran saction, only the data phases that can do not lead to the overrun condition are logged. ? [3] reaching again the high threshold value while the fullness is decreasing does not trigger an interrupt. ? [4] the fifo (btf) is empty, a read takes place leading to an underrun condition. the interrupt reporting is similar to the one described for the case [1]. the read pointer is not incremented. if the underrun condition occurs during a read burst, a data phase error acknowledge will be issued by the bmu. the software handling the bmu should take care to avoid such conditions. howe ver errors taking place in the system caused by soft errors (single event upsets for instance), may lead to such condition. full highthreshold empty fifo fullness state overrunint highthresholdint 1 2 3 4 time hardware fifo handler ? interrupt generation logged tr ansaction leads to full state new tr ansaction with fifo full leads to overrun read access to em pty fifo leads to underr un underrunint www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-18 v1.1, 2011-03 bmu, v2.6 18.4.7 error correction code (ecc) the bmu sram is protected by information redundancy based on error correction codes with a hamming distance of 4. the ecc information redundancy applies to the data bits of each bmu sram word. ctl limitations with ecc accesses when the ecc mapping is enabled the memory access limitations described in ?usage in non safety applications? on page 18-20 apply as well. therefore the ecc information can only be accessed using fpi btr2 bursts as described in figure 18-11 ?ecc information mapping into fpi btr2 transactions? on page 18-18 . the burst base address is 8-byte a ligned (fpi_a[2:0] = 3?b000). figure 18-11 ecc information mappin g into fpi btr2 transactions memory integrity error control a pair of architecturally visible registers (miecon, miecon2) are included to allow software to control the memory integrity e rror detection / correction mechanisms. the existence of the miecon and miecon2 registers is architecturally defined. however, the fields within these registers are implementation specific. the behavior of miecon2 ecc update using fpi btr 2 w r ite bur st ( when sm acom .bm uram = 2 ) don?t care don?t care 0 31 32 63 x[31:0] y[31 :0 ] ... ... ... ... ... ... offset @1 ecc access using fpi btr 2 read bur st ( when sm acom .bm uram = 2) fpi addr fpi rd data @1 @1 + 0x4 fpi addr fpi wr data 64 71 ... ecc1 ecc1 ... ... 0 7 8 31 0 31 @1 don?t care ecc1 0 7 8 @1+4 don?t care 0 31 31 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-19 v1.1, 2011-03 bmu, v2.6 is configured according to the ?secwen_i? in put to the bmu. ?secwen_i? is connected to a product configuration bit from the scu, and is locked after execution of startup software (ssw). with ?secwen_i? not assert ed, and the miecon2 bits previously set by ssw, single-bit correction of memory integrity errors is transparent to software and may not be disabled or detected. when ?secwen_i? is asserted, miecon2 may only be written in supervisor mode and is endinit protected. miecon2 reads return the register contents. when ?secwen_i? is not asserted accesses to miecon2 will generate an fpi error acknowledge. the ded_en and sec_en bits (located miecon and miecon2 respectively) and the appropriate smacon field settings interact to perform the following general function: table 18-2 memory integrity error modes sec_en ded_en smacon description xx 01 b or 10 b array mapping all single and double-bit memory integrity errors ignored. 00 00 b or 11 b no memory integrity handling all single and double-bit memory integrity errors ignored. 01 00 b or 11 b error detection mode single and double-bit errors treated as un- correctable errors. in this mode the bmu_ecc_error_o is asserted every time a single or double bit error is detected. 10 00 b or 11 b sec only mode single-bit errors corrected by ecc, double-bit errors ignored. bmu_ecc_error_o is never asserted in this mode 11 00 b or 11 b secded mode single-bit errors corrected by ecc, double-bit errors treated as un-correctable errors. bmu_ecc_error_o is asserted every time a double bit error is detected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-20 v1.1, 2011-03 bmu, v2.6 18.4.8 usage in non safety applications when the bmu is not used in a safety application the btf fifo can be accessed as a standard linear memory through the bmu sl ave interface using btr2, btr4 or btr8 fpi transactions. this mode of operation is controlled by the ctl .mode field. single word or sub word (8/16-bit) accesses are not allowed; such requests will result in a bus error. the start address of the fpi burst transact ions is aligned with the size of the burst. figure 18-12 ?mapping between fpi burs t transaction and sram contents? on page 18-20 shows how the fpi bus 32-bit data phases are mapped into the 64-bit word of the bmu sram. an example with read and write bursts is given. figure 18-12 mapping between fpi burst transaction and sram contents table 18-3 sram address map module base address end address note bus monitoring unit f032 4000 h f032 5fff h bmuram fpi write burst (e.g. btr2) x[31:0 ] y[ 31: 0] 0 c[31:0] d[31:0] a[31:0] b[31:0] 31 32 63 x[31 :0 ] y[31:0] ... ... ... ... ... ... offset @1 fpi read burst (e.g. btr4) @2 @2 + 0x4 offset @2 offset @2 + 8 @2 + 0x8 @2 + 0xc a[31:0] b[ 31 : 0] c[ 31 : 0] d[31:0] fpi addr fpi rd data @1 @1 + 0x4 fpi addr fpi wr data bmu sram ... ... www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-21 v1.1, 2011-03 bmu, v2.6 18.4.9 bmu interrupts interrupt generation rules ? each interrupt source has a dedicated status bit that indicates if an interrupt has been issued or not. ? a status flag shall be cleared by software by writing a 1 to the corresponding bit position. ? if a status flag is set and a new hardware condition leading to an interrupt occurs, no new interrupt is generated. if a software access to clear the interrupt status bit takes place and in the same cycle the hardware wants to set the bit, the hardware condition wins the arbitration . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-22 v1.1, 2011-03 bmu, v2.6 18.4.10 peripheral mo nitoring selection the table 18-4 shows the list of peripherals present in the TC1798 device together with an identifier. the fpi bus infrastructure pr ovides address decoders that are configured to generate chip select signals. the chip select signals are connected to the standard bpi modules or to the fpi slave interfaces or directly to custom fpi interfaces (some fpi peripherals have neither a bpi nor a fpi slave interface). each select line identifies a fpi region that corresponds to the fpi regions defined in the pset0 and pset1 registers. behind a decoded fpi region there ma y be multiple peripherals. this situation is reflected in table 18-4 . peripherals that belong to the dma subsystem (fpi extension) will all use the dma identifier. only the fpi write transactions enabled by pset0 and pset1 will be stored in the bmu. table 18-4 identification of fpi regions unit fpi region identifier system peripheral bus control unit (sbcu) 0 system timer (stm) 1 system control unit (scu) and watchdog timer (wdt) 2 microsecond bus controller 0 (msc0) 3 microsecond bus controller 1 (msc1) 4 async./sync. serial interface 0 (asc0) 5 async./sync. serial interface 1 (asc1) 5 port group 0 6 port group 1 7 port group 2 8 port group 3 9 general purpose timer array (gpta0) 10 general purpose timer array (gpta1) 10 local timer cell array (ltca2) 10 capture/compare unit 6 0 (ccu60) 11 capture/compare unit 6 1 (ccu61) 11 capture/compare unit 6 2 (ccu62) 12 capture/compare unit 6 3 (ccu63) 12 general purpose timer 12 0 (gpt120) 13 general purpose timer 12 1 (gpt121) 14 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-23 v1.1, 2011-03 bmu, v2.6 safety direct memory ac cess controller (sdma) 15 direct memory access controller (dma) 16 on-chip debug support (cerberus) 17 belongs to dma region 2 micro link interface 0 (mli0) 17 belongs to dma region 2 micro link interface 1 (mli1) 17 belongs to dma region 2 memory checker (mchk) 17 belongs to dma region 2 mli0 small transfer windows 17 belongs to dma region 2 mli1 small transfer windows 17 belongs to dma region 2 mli0 large transfer windows 17 belongs to dma region 2 mli1 large transfer windows 17 belongs to dma region 2 multican controller (can) 18 flexray tm protocol controller (e-ray) 19 pcp pcp registers 20 pcp data memory (pram) 20 pcp code memory (pcode) 20 fast analog-to-digital converter (fadc) 21 analog-to-digital converter 0 (adc0) 22 analog-to-digital converter 1 (adc1) 22 analog-to-digital converter 2 (adc2) 22 analog-to-digital converter 3 (adc3) 22 synchronous serial interface 0 (ssc0) 23 synchronous serial interface 1 (ssc1) 24 synchronous serial interface 2 (ssc2) 25 table 18-4 identification of fpi regions unit fpi region identifier www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-24 v1.1, 2011-03 bmu, v2.6 synchronous serial interface 3 (ssc3) 26 guardian for ssc0 (sscg0) 27 guardian for ssc1 (sscg1) 28 guardian for ssc2 (sscg2) 29 guardian for ssc3 (sscg3) 30 flexible crc engine (fce) 31 secure hardware extension (she) not logged sent module (sent) 32 peripheral bus monitor registers (bmu) 33 peripheral bus monitor memory (bmuram) not logged table 18-4 identification of fpi regions unit fpi region identifier www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-25 v1.1, 2011-03 bmu, v2.6 18.5 interfaces of the bmu module this section only describes th e signals that do not belong to the system -on-chip standard interfaces (interrupt bus, fpi bus). notes ? fpi_clk_en is the fpi clock signal. ? ocds_p_suspend: the suspend feature is not supported by bmu. the ocds_p_suspend signal is not used. ? sleep_n is used to contro l the sleep mode. the sl eep mode function is not supported by bmu, the sleep_n signal is not used. ? the fpi_ack[1:0] signals from the fpi bus are ored together and sent to all masters (only the granted master inte rprets the fpi_ack[1:0] c ontents). the bmu will see the global fpi_ack[1:0] signal and not directly the individual fpi_ack corresponding to a fpi region. ? the width of the bmu_spb_sel signal is set to 64 bits to make it independent from the peripheral configuration. the non-used upper bits of bmu_spb_sel must be set to the logic value low. the order of the select lines is given by table 18-4 ?identification of fpi regions? on page 18-22 . table 18-5 generic bmu digital connections 1) 1) the postfix indicating the direction of the signal is no t part of the signal name specification as it depends on the naming conventions used by the development flow. the i/o column indicated the direction of the signal. when the signal is specific to the bmu module it gets ?bmu_? as prefix. signal from/to module i/o to bmu reset value einit scu (system control unit) i fpi_clk_en scu (system control unit) i ocds_p_suspend on chip debug i sleep_n scu (system control unit) i secwen scu (system control unit) connects to scu prdcfg2.senav single error correction availability control i bmu_ecc_error scu (system control unit) un-correctable ecc error detected output o0 bmu_spb_sel[63:0] system peri pheral bus (spb) address decoders i bmu_spb_ack[1:0] global fpi_ack[1:0] generated by the fpi bus i www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-26 v1.1, 2011-03 bmu, v2.6 ? the bmu_ecc_error is an active high signal that delivers a pulse of one fpi clock cycle duration. see table 18-2 ?memory integrity error modes? on page 18-19 for the un-correctable modes. ? in TC1798 microcontroller there are 47 bmu_spb_sel signals connected to the bmu. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-27 v1.1, 2011-03 bmu, v2.6 18.6 bmu module registers figure 18-13 shows the bmu module register map. table 18-6 shows the bmu address space table 18-7 lists all registers implemented in the bmu. bmu address map overview figure 18-13 bmu register map in TC1798 device the bus transaction table is made of 1024 entries, where each entry is made of 64-bits. table 18-6 shows the base address of the addressable sram space when the access mode defined by the ctl .mode configuration register is set to 0. table 18-6 registers address space for TC1798 module base address end address note bmu f032 3000 h f032 31ff h registers configuration & status registers 512 bytes @bmu = fpi base address bus transaction table n entries cyclic buffer @bmu + 0x1000 reserved bmu area @bmu + 0x200 accessed via bpi a ccessed via fp i s lave inte rface www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-28 v1.1, 2011-03 bmu, v2.6 access mode rules the table 18-7 ?registers overview? on page 18-28 uses the standard access mode conventions. ? e indicates that an access is only possible if the end of initialization signal from the system control unit is active. in this case supervisor mode (sv) is also mandatory. ? when u, sv are both listed it means that a read or write access can be done either in user mode (u) or supervisor mode (v). table 18-7 registers overview short name description offset addr access mode reset class description see read write system registers clc clock control register 00 h u, sv sv, e 3 page 18-30 id module identifier 08 h u, sv be 3 page 18-32 global control over read access to bus transaction table ctl transaction filtering control register 20 h u, sv sv, e 3 page 18-33 ptr btf running pointers 24 h u, sv be 3 page 18-34 fullness fifo fullness 28 h u, sv be 3 page 18-35 bus logging configuration registers pset0 peripheral set 0 30 h u, sv sv, e 3 page 18-36 pset1 peripheral set 1 34 h u, sv sv, e 3 page 18-39 tid transaction id set 0 38 h u, sv sv, e 3 page 18-42 fifo monitoring configuration and status registers fmctl control register 40 h u, sv sv, e 3 page 18-43 fmsts status register 44 h u, sv u,sv 3 page 18-43 fmth high threshold value 48 h u, sv sv, e 3 page 18-44 control of ecc operation smacon control of sist mode 50 h u, sv sv, e 3 page 18-46 miecon ecc modes control 54 h u, sv sv, e 3 page 18-47 miecon2 ecc modes control 58 h u, sv sv, e 3 page 18-47 interrupt system registers src service request control fc h u, sv sv 3 page 18-49 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-29 v1.1, 2011-03 bmu, v2.6 ? be stands for bus error, nsc stands for no special condition note: configuration registers that determin e the behavior of the bmu are protected by the end of init protection mechanism. th ey are intended to be only configured once during the initial system startup phase. in safety-related applications the configuration is controlled by the safety driver. registers that need to be updated by the application (run-time interaction) are only protected by supervisor mode: applies to fmsts . register access constraints the registers that control the operation of the bmu are assumed to be static, they are configured by the safety driver according to the requirements of the safety application(s) during the initial microcontroller configuration. exceptions will be documented in each register sub-chapter. as indication the list of registers that are assumed to be static are: ? pset0 , pset1 , tid 1) , fmctl , fmth ? ctl is only allowed to be change if sist mode is used during run-time for ecc checks. the necessity to do ecc checks during run-time will depend on the safety monitoring concept. 1) currently tid is a read-only register, this may change in future enhancements of the bmu. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-30 v1.1, 2011-03 bmu, v2.6 18.6.1 system registers description bmu module clock control register. note: the bmu does not implement a fractional divider. note: sleep and suspend modes are not supp orted by bmu, therefore the bit fields controlling those feat ures are not present in the clc register. note: the bmu can be disabled. when th e disable state is requested all pending transactions running on the fpi slave interface must be completed before the disabled state is entered. the clc register module disable bit status bmu_clc.diss indicates whether the module is currently disabled (diss == 1). any attempt to write any of the bpi writab le registers with the exception of the clc register will generate a bus error. a read operation of bpi registers is allowed and does not generate a bus error. as long as the bmu is disabled no logging is possible (including the write access to the bmu_clc register to enable again the clc control clock register (00 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 1514131211109876543210 0 fsoe sbwe edis spen diss disr r rwwrwrwrhrw field bits type description disr 0rw module disable bit request used for enable/disable control of the module 0 b module disable is not requested 1 b module disable is requested diss 1rh module disable bit status bit indicates the current status of the module 0 b module is enabled 1 b module is disabled 0 [31:2] r reserved read as 0; write has no effect. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-31 v1.1, 2011-03 bmu, v2.6 bmu). logging is possible after software wr ites 0 to disr and the diss field value indicates the enabled state. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-32 v1.1, 2011-03 bmu, v2.6 bmu module identification register. id module identificat ion register (08 h ) reset value: 0089 c001 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). mod_type [15:8] r module type the bit field is set to c0 h which defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines a module identification number. the value for the bmu module is 0089 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-33 v1.1, 2011-03 bmu, v2.6 18.6.2 bmu control/ status registers ctl defines the access mode to the internal sram and enables to control additional logging mechanisms based on the initiator of the transaction. the operation mode is statically defined for the whole run-time, changes of operating mode are to be avoided. in the event the bmu is configured in fifo mode (ctl.mode = 1) then the ctl register should be polled to confirm the fifo mode is set before any write transaction on the fpi bus is logged. however when the bmu is configured in fifo mode, it may be necessary to switch to sram mode if run time diagnostics of the ecc logic is required. it must be ensured at system level that during the time the diagnostic s will be performed, the safety application ctl transaction filtering control (20 h ) reset value: 0000 0000 h 31 0 0 t m f m o d e rrwrw field bits type description mode 0rw access mode 0 b the btf is accessed in linear mode as a standard memory mapped sram 1 b the btf is used in fifo mode enabling to log the write transaction to the regions selected in pset0 and pset1 registers. tmf 1rw transaction master filtering in fifo mode, this field enables an additional logging mechanism controlled by the master identifier of a fpi write transaction. 0 b logging controlled by the transaction master identifier disabled. 1 b logging controlled by the transaction master identifier enabled. 0 [31:2] r reserved bit fields. a write has no effect. returns 0s on read. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-34 v1.1, 2011-03 bmu, v2.6 will not be able to use the logging capability of the bmu. if the bmu is intended to be used in sram mode only, it is not allowed to switch during run-time to fifo mode. in the fpi bus protocol the initiator (also called the master) is uniquely identified by the fpi transaction identifier made of 4-bits. when the mode field and tmf field are both set to 1, the bmu monitors the master identifier of every fpi write transaction. when the master identifier matches with the value(s) present in the tid register, the address information of every address phase of the transaction is logged into the bmu fifo. the logging based on the master identifier m onitoring has precedence over the logging based on the fpi region monitoring. ptr is to be used for debug or verification purposes. ptr pointer information for bus transaction fifo (24 h ) reset value: 0000 0000 h 31 0 0wptr0 rptr rrhrrh field bits type description rptr [9:0] rh read pointer for a 1024 entry sram indicates the current position of the read pointer. a write to this field has no hardware effect. for debug purposes only. wptr [25:16] rh write pointer for a 1024 entry sram indicates the current position of the write pointer. a write to this field has no hardware effect. for debug purposes only. 0 [15:10], [31:26] r reserved bit fields. a write has no effect. returns 0s on read. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-35 v1.1, 2011-03 bmu, v2.6 the ucells and fcells information can be used to schedule the number of consecutive burst reads that can be made to read the available information from the btf. fullness fullness information for bus transaction fifo (28 h ) reset value: 0400 0000 h 31 0 0 fcells 0 ucells rrhrrh field bits type description ucells [10:0] rh number of valid (used) entries in the btf fullness of the btf as a number of words. ucells value ranges from 0 to n, where n is the number of fifo entries. ucells = n represents a full fifo. for TC1798 microcontroller, n = 1024. writing to this field has no effect. fcells [26:16] rh number of free entries in the btf writing to this field has no effect. fcells value ranges from 0 to n, where n is the number of fifo entries. fcells = n represents an empty fifo. for TC1798 microcontroller, n = 1024. writing to this field has no effect. 0 [31:27], [15:11] r reserved bit fields. a write has no effect. returns 0s on read. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-36 v1.1, 2011-03 bmu, v2.6 18.6.3 bmu: bus logging configuration registers pset0 peripheral set 0 configuration (30 h ) reset value: 0000 0000 h 31 0 fpi_sel31 fpi_sel30 fpi_sel29 fpi_sel28 fpi_sel27 fpi_sel26 fpi_sel25 fpi_sel24 fpi_sel23 fpi_sel22 fpi_sel21 fpi_sel20 fpi_sel19 fpi_sel18 fpi_sel17 fpi_sel16 fpi_sel15 fpi_sel14 fpi_sel13 fpi_sel12 fpi_sel11 fpi_sel10 fpi_sel9 fpi_sel8 fpi_sel7 fpi_sel6 fpi_sel5 fpi_sel4 fpi_sel3 fpi_sel2 fpi_sel1 fpi_sel0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description fpi_sel0 0rw select bit for fpi region 0 0 b region disabled 1 b region enabled fpi_sel1 1rw select bit for fpi region 1 0 b region disabled 1 b region enabled fpi_sel2 2rw select bit for fpi region 2 0 b region disabled 1 b region enabled fpi_sel3 3rw select bit for fpi region 3 0 b region disabled 1 b region enabled fpi_sel4 4rw select bit for fpi region 4 0 b region disabled 1 b region enabled fpi_sel5 5rw select bit for fpi region 5 0 b region disabled 1 b region enabled fpi_sel6 6rw select bit for fpi region 6 0 b region disabled 1 b region enabled fpi_sel7 7rw select bit for fpi region 7 0 b region disabled 1 b region enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-37 v1.1, 2011-03 bmu, v2.6 fpi_sel8 8rw select bit for fpi region 8 0 b region disabled 1 b region enabled fpi_sel9 9rw select bit for fpi region 9 0 b region disabled 1 b region enabled fpi_sel10 10 rw select bit for fpi region 10 0 b region disabled 1 b region enabled fpi_sel11 11 rw select bit for fpi region 11 0 b region disabled 1 b region enabled fpi_sel12 12 rw select bit for fpi region 12 0 b region disabled 1 b region enabled fpi_sel13 13 rw select bit for fpi region 13 0 b region disabled 1 b region enabled fpi_sel14 14 rw select bit for fpi region 14 0 b region disabled 1 b region enabled fpi_sel15 15 rw select bit for fpi region 15 0 b region disabled 1 b region enabled fpi_sel16 16 rw select bit for fpi region 16 0 b region disabled 1 b region enabled fpi_sel17 17 rw select bit for fpi region 17 0 b region disabled 1 b region enabled fpi_sel18 18 rw select bit for fpi region 18 0 b region disabled 1 b region enabled fpi_sel19 19 rw select bit for fpi region 19 0 b region disabled 1 b region enabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-38 v1.1, 2011-03 bmu, v2.6 fpi_sel20 20 rw select bit for fpi region 20 0 b region disabled 1 b region enabled fpi_sel21 21 rw select bit for fpi region 21 0 b region disabled 1 b region enabled fpi_sel22 22 rw select bit for fpi region 22 0 b region disabled 1 b region enabled fpi_sel23 23 rw select bit for fpi region 23 0 b region disabled 1 b region enabled fpi_sel24 24 rw select bit for fpi region 24 0 b region disabled 1 b region enabled fpi_sel25 25 rw select bit for fpi region 25 0 b region disabled 1 b region enabled fpi_sel26 26 rw select bit for fpi region 26 0 b region disabled 1 b region enabled fpi_sel27 27 rw select bit for fpi region 27 0 b region disabled 1 b region enabled fpi_sel28 28 rw select bit for fpi region 28 0 b region disabled 1 b region enabled fpi_sel29 29 rw select bit for fpi region 29 0 b region disabled 1 b region enabled fpi_sel30 30 rw select bit for fpi region 30 0 b region disabled 1 b region enabled fpi_sel31 31 rw select bit for fpi region 31 0 b region disabled 1 b region enabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-39 v1.1, 2011-03 bmu, v2.6 pset1 peripheral set 1 configuration (34 h ) reset value: 0000 0000 h 31 0 fpi_sel63 fpi_sel62 fpi_sel61 fpi_sel60 fpi_sel59 fpi_sel58 fpi_sel57 fpi_sel56 fpi_sel55 fpi_sel54 fpi_sel53 fpi_sel52 fpi_sel51 fpi_sel50 fpi_sel49 fpi_sel48 fpi_sel47 fpi_sel46 fpi_sel45 fpi_sel44 fpi_sel43 fpi_sel42 fpi_sel41 fpi_sel40 fpi_sel39 fpi_sel38 fpi_sel37 fpi_sel36 fpi_sel35 fpi_sel34 fpi_sel33 fpi_sel32 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description fpi_sel32 0rw select bit for fpi region 32 0 b region disabled 1 b region enabled fpi_sel33 1rw select bit for fpi region 33 0 b region disabled 1 b region enabled fpi_sel34 2rw select bit for fpi region 34 0 b region disabled 1 b region enabled fpi_sel35 3rw select bit for fpi region 35 0 b region disabled 1 b region enabled fpi_sel36 4rw select bit for fpi region 36 0 b region disabled 1 b region enabled fpi_sel37 5rw select bit for fpi region 37 0 b region disabled 1 b region enabled fpi_sel38 6rw select bit for fpi region 38 0 b region disabled 1 b region enabled fpi_sel39 7rw select bit for fpi region 39 0 b region disabled 1 b region enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-40 v1.1, 2011-03 bmu, v2.6 fpi_sel40 8rw select bit for fpi region 40 0 b region disabled 1 b region enabled fpi_sel41 9rw select bit for fpi region 41 0 b region disabled 1 b region enabled fpi_sel42 10 rw select bit for fpi region 42 0 b region disabled 1 b region enabled fpi_sel43 11 rw select bit for fpi region 43 0 b region disabled 1 b region enabled fpi_sel44 12 rw select bit for fpi region 44 0 b region disabled 1 b region enabled fpi_sel45 13 rw select bit for fpi region 45 0 b region disabled 1 b region enabled fpi_sel46 14 rw select bit for fpi region 46 0 b region disabled 1 b region enabled fpi_sel47 15 rw select bit for fpi region 47 0 b region disabled 1 b region enabled fpi_sel48 16 rw select bit for fpi region 48 0 b region disabled 1 b region enabled fpi_sel49 17 rw select bit for fpi region 49 0 b region disabled 1 b region enabled fpi_sel50 18 rw select bit for fpi region 50 0 b region disabled 1 b region enabled fpi_sel51 19 rw select bit for fpi region 51 0 b region disabled 1 b region enabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-41 v1.1, 2011-03 bmu, v2.6 fpi_sel52 20 rw select bit for fpi region 52 0 b region disabled 1 b region enabled fpi_sel53 21 rw select bit for fpi region 53 0 b region disabled 1 b region enabled fpi_sel54 22 rw select bit for fpi region 54 0 b region disabled 1 b region enabled fpi_sel55 23 rw select bit for fpi region 55 0 b region disabled 1 b region enabled fpi_sel56 24 rw select bit for fpi region 56 0 b region disabled 1 b region enabled fpi_sel57 25 rw select bit for fpi region 57 0 b region disabled 1 b region enabled fpi_sel58 26 rw select bit for fpi region 58 0 b region disabled 1 b region enabled fpi_sel59 27 rw select bit for fpi region 59 0 b region disabled 1 b region enabled fpi_sel60 28 rw select bit for fpi region 60 0 b region disabled 1 b region enabled fpi_sel61 29 rw select bit for fpi region 61 0 b region disabled 1 b region enabled fpi_sel62 30 rw select bit for fpi region 62 0 b region disabled 1 b region enabled fpi_sel63 31 rw select bit for fpi region 63 0 b region disabled 1 b region enabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-42 v1.1, 2011-03 bmu, v2.6 pset0 and pset1 are used to control which fpi region is to be monitored by the bmu. the transaction identifier tid enables to perform monitoring actions based on the master identifier provided by the fpi mast er. this mode can be further extended (in future versions of the bmu) to do broader checks based on the tid: for instance in a multi-processor system, the tid can uniquely id entity the cpu core that initiated the transaction. the current implementation only allows to do a static detection of write accesses initiated by the she module when present in the product. tid fpi transaction id set 0 configuration (38 h ) reset value: 0000 000d h 31 0 0tid0 rr field bits type description tid0 [3:0] r transaction identifier 0 this field is statically encoded with the 4?b1101 value that corresponds to the she fpi master identifier in the TC1798 device. 0 [31:4] r reserved bit fields. a write has no effect. returns 0s on read. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-43 v1.1, 2011-03 bmu, v2.6 18.6.4 bmu: fifo monitoring registers fmctl controls the interrupt generation related to the fifo fullness monitoring. fmctl fifo monitor co ntrol register (40 h ) reset value: 0000 0000 h 31 0 0 udf_int ovf_int fht_int rrwrwrw field bits type description fht_int 0rw interrupt enable for fifo high threshold 0 b interrupt generation disabled 1 b interrupt generation enabled ovf_int 1rw interrupt enable for overflow detection 0 b interrupt generation disabled 1 b interrupt generation enabled udf_int 2rw interrupt enable for underflow detection 0 b interrupt generation disabled 1 b interrupt generation enabled 0 [31:3] r reserved bit fields. a write has no effect. returns 0s on read. fmsts fifo monitor st atus register (44 h ) reset value: 0000 0000 h 31 0 0 udf_sts ovf_sts fht_sts rrwhrwhrwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-44 v1.1, 2011-03 bmu, v2.6 fmsts is used to log the status of the interrupt source(s). the bits are set to 1 by hardware. to clear a status bit the software must write a 0 at the bit position corresponding to be bit to be cleared (writing a 1 per software has no effect on the status bits). if software writes a 0 to a status bit that is already cleared and in the same cycle the hardware wants to set the bit, the hardware has priority over the software. field bits type description fht_sts 0rwh status flag for fifo high threshold interrupt 0 b no interrupt pending 1 b event related to high threshold monitoring has been detected. the event leads to an interrupt if fmctl.fht_int = 1. ovf_sts 1rwh status flag for overrun interrupt 0 b no interrupt pending 1 b event related to overflow monitoring has been detected. the event leads to an interrupt if fmctl.ovf_int = 1. udf_sts 2rwh status flag for underflow interrupt 0 b no interrupt pending 1 b event related to underflow monitoring has been detected. the event leads to an interrupt if fmctl.udf_int = 1. 0 [31:3] r reserved bit fields. a write has no effect. returns 0s on read. fmth fifo monitor: fullness threshold register (48 h ) reset value: 0000 0000 h 31 0 0fht rrw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-45 v1.1, 2011-03 bmu, v2.6 fmth defines a boundary for the number of used words in the bus transaction fifo that will be monitored during run-time. when the number of words configured in the fht field is reached (or crossed) and if the fmctl . fht_int field is set, an interrupt is triggered. this fht field must be initialized by sw to the expected threshold before enabling the interrupt generation. field bits type description fht [9:0] rw fifo high threshold this field defines a number of used entries defining a threshold. when set to 0 the threshold monitoring is disabled. 0 [31:10] r reserved bit fields. a write has no effect. returns 0s on read. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-46 v1.1, 2011-03 bmu, v2.6 18.6.5 bmu: sist mode access control register note: please see ?error correction code (ecc)? on page 18-18 for more information regarding the use of this register. this register is endinit protected. smacon sist mode access control register (50 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 bmuram rrw field bits type description bmuram [1:0] rw sist mode access control 00 b normal operation, no mapping 01 b data array mapping, no error detection/correction 10 b check array mapping, no error detection/correction 11 b data array mapping, error detection/correction enabled 0 [31:2] r reserved returns ?0? if read; should be written with ?0?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-47 v1.1, 2011-03 bmu, v2.6 please see ?error correction code (ecc)? on page 18-18 for more information regarding the use of this register. miecon memory integrity erro r control register(54 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ded_en rrw field bits type description ded_en 0rw double error detection enable 0 b double bit error detection for bmuram disabled 1 b double bit error detection for bmuram enabled 0 [31:1] r reserved returns ?0? if read; should be written with ?0?. miecon2 memory integrity error control 2 register(58 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 sec_en rrw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-48 v1.1, 2011-03 bmu, v2.6 please see ?error correction code (ecc)? on page 18-18 for more information regarding the use of this register. note: this register is endini t protected, in addition the register cannot be accessed unless the ?secwen_i? input is asse rted. when ?secwen_i? is not asserted accesses to miecon2 will generate an fpi error acknowledge. field bits type description sec_en 0rw single error correction enable 0 b single bit error correction for bmuram disabled 1 b single bit error correction for bmuram enabled 0 [31:1] r reserved returns ?0? if read; should be written with ?0?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-49 v1.1, 2011-03 bmu, v2.6 18.6.6 interrupt sy stem registers src service request control register (fc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn wwrwhrwrrw r rw field bits type description srpn [7:0] rw service request priority number 00 h service request is never serviced 01 h service request is on lowest priority ... ff h service request is on highest priority tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp service is initiated sre 12 rw service request enable 0 b service request is disabled 1 b service request is enabled srr 13 rwh service request flag 0 b no service request is pending 1 b a service request is pending 1) clrr 14 w request clear bit clrr is required to clear srr. 0 b no action 1 b clear srr; bit value is not stored; read always returns 0; no action if setr is set also. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 bus monitor unit (bmu) users manual 18-50 v1.1, 2011-03 bmu, v2.6 setr 15 w request set bit setr is required to set srr. 0 b no action 1 b set srr; bit value is not stored; read always returns 0; no action if clrr is set also. 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. 1) the bit field srr is automatically cleared by hardware at the end of an interrupt arbitration round if the node was the winner, therefore this information is not suitable for interrupt plausibility checks. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-1 v1.1, 2011-03 ocds, v1.5 19 on-chip debug support (ocds) this chapter gives an overview about the debug features of the TC1798 device. this chapter does not describe the TC1798 debug functionality and capabilities in detail. for detailed information about the on-chip debug support (ocds) functionality as required by tool suppliers please contac t local infineon representatives. 19.1 overview TC1798 supports ocds level 1 and 3. ocds level 1 the ocds level 1 is mainly assigned for system software debug ging purposes which have a demand for low-cost standard debugger hardware. the ocds level 1 is based on a debug interface that is used by the external debug hardware to communicate with the system. the on-chip cerb erus module controls the interactions between the debug interface and the on-chip modules and allows in particular to access the whole address space of the device. the memory mapped on- chip debug resources make it possible to trigger on instruction and data addresses as well as to control user program execution (run/stop, breakpoint, single-step). ocds level 3 the ocds level 3 is based on a multi core debug solution (mcds) using an emulation device. this device has the following featur es required for high-end emulation purposes: ? emulation device is available in the same package variants as TC1798 ? higher current consumption due to trace and overlay ram is the only difference ? tricore program trace ? tricore data trace (no register file trace) ? pcp ownership trace ? pcp program trace ? pcp data write to pram trace (no register file trace) ? full visibility of internal peripheral bus (spb) ? full visibility of up to two arbitrary sri bus slaves ? time aligned parallel trace of all sources ? breakpoints and watchpoints based on common event generation logic ? magnitude comparators working on instruction pointers and memory addresses: a<=ip<=b ? masked magnitude comparators working on the data busses: data = ?xxxx55xx? ? sequential event logic: counters driven by events and equipped with limit comparators are used as event sources a gain for breakpoint or trace qualification ? optimized compression of buffered trace data ? code and data fetch from emulation memory www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-2 v1.1, 2011-03 ocds, v1.5 ? highly sophisticated complex qualification- and trigger mechanism ? pre- and post event trace buff ering (?digital oscilloscope?) ? performance counters ? continuous trace logging and trace data acquisition up to the bandwidth of the used host interface ? central time stamp unit to correlate traces from different cores or other sources ? central mechanism to start and stop all cores simultaneously or selectively ? halt the system when trace memory is full the emulation device includes the product chip part extended with additional emulation hardware. for detailed information about the emulation device functionality (e.g. as required by tool suppliers), please co ntact local infineon representatives. figure 19-1 shows a block diagram of the TC1798 ocds system. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-3 v1.1, 2011-03 ocds, v1.5 figure 19-1 ocds system block diagram emulation device only ocds_blockdiagram sri tricore ocds sdma ocds bus switch fabric ocds cerberus otgs scu oscu sbcu ocds she ocds ioclient #1 dap jtag pins mcds emem ioc32 ioclient #2 spb dma ocds trig www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-4 v1.1, 2011-03 ocds, v1.5 components the ocds of the TC1798 consists of the following building blocks: ? ocds system control unit (oscu) ? tricore ocds ? pcp ocds ? dma ocds ? sbcu ocds ? sri ocds ? multi core break switch (mcbs) ? break pin control ? ioclient ? device access port (dap) ? jtag interface ? overlay control summary of ocds features ? ocds system control unit (oscu) ? controls ocds enabling ? automatic power saving ? reset control of debug resources ? halt after reset ? hot attach of a debugger to a running system ? key mechanism allows control th e device access in a secure way. ? state-aware watchdog timer suspension during debugging ? control of soc specific ocds features ? interrupt service request node for debug purposes ? tricore ocds features ? hardware event generation ? break by debug instruction or break signal from break switch ? suspend by suspend bus or break signal from break switch ? full hardware supported single step ? concurrent access to memory and sfrs via cerberus ? pcp ocds features ? break by debug instruction or break signal from break switch ? concurrent access to memory and sfrs via cerberus ? dma/sdma ocds features ? soft-suspend mode of dma channels ? break signal generation ? trace signal generation ? sbcu ocds features ? event generation on specified transactions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-5 v1.1, 2011-03 ocds, v1.5 ? sri ocds features ? error recording and service request on bus error ? multi-core break switch (cerberus mcbs) ? tricore, pcp, dma/sdma, break pins and sbcu available as break sources ? tricore and pcp available as break targets; other parts can be suspended in addition ? synchronous stop and restart of the system ? break to suspend converter 19.2 ocds level 1 the basic principle of the tricore ocds lev el 1 is that all relevant user and debug resources are memory mapped. these resources include on-chip memories, cpu core registers and registers of the peripheral units. a typical ocds level 1 debugging configuration is shown in figure 19-2 . it comprises two parts: ? the tool software ? the tool access hardware interface adapter this configuration makes it possible to realize a cost effective debugging environment that permits comprehensive real-time debugging tasks to be performed. figure 19-2 typical ocds level 1 hardware connections debug_environment .vsd target hardware tool software on pc usb, ethernet , etc. interface tool access hardware dap/jtag product chip dap/jtag www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-6 v1.1, 2011-03 ocds, v1.5 19.2.1 tricore cpu ocds level 1 this section describes the basic features of the tricore ocds level 1 hardware. for more details please refer to the ?trico re core architecture v1.6? manual. features ? single-step support by hardware ? up to 8 programmable hardware breakpoints. each one can be defined as a combination of program counter and data address: ? breaks on program counter (pc) value two precise pc values or one pc range break before make (bbm) possible ? breaks on data address two precise data addresses or one data address range no break before make possible (due to pipelined architecture) ? combinations of the above break conditions ? suspend features ? core suspend-out to suspend bus ? configurable core suspend-in ? real-time features ? read and write of memory/registers independent of cpu, with minimum intrusion (stealing bus cycles by cerberus) ? high-priority requests can still be serviced when the core is in emulation mode - by interrupting the monitor program 19.2.1.1 basic concept the tricore cpu in the TC1798 provides ocds with the following two basic parts: ? debug event trigger generation ? debug event trigger processing the first part controls the generation of debug events and the second part controls what actions are taken when a debug event is generated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-7 v1.1, 2011-03 ocds, v1.5 figure 19-3 basic tricore debug concept 19.2.1.2 debug event generation if debug mode is enabled, debug events can be generated by: ? debug event generation from debug triggers ? activation of the external core break-in signal to the core ? execution of a debug instruction ? execution of an mtcr/mfcr instruction debug event generation from debug triggers the debug event generation unit is responsible for generating debug events when a programmable set of debug triggers is active . tc1.6 has 8 address comparator registers dedicated for debug. pairs can be used for range triggers. these debug triggers provide the inputs to a programmable block of combinational logic that outputs debug events. the aim is to be able to specify the breakpoints that use fairly simple criteria purely in the on-chip debug event generation unit, and to rely on help from the external debug system or debug monito r to implement more complex breakpoints. tricore_ocds.vsd debug event generation debug triggers debug event processing core break -in execution of the debug instruction execution of mtcr / mfcr instruction www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-8 v1.1, 2011-03 ocds, v1.5 activation of the external core break-in signal when activating the TC1798 device pin brkin = 0 and if mcbs and port control is configured to forward this event to the core break-in signal, a break event is induced as specified in an external break input event spec ifier register exevt ( figure 19-4 ). execution of a debug instruction the tricore architecture supports a mechan ism through which software can explicitly generate a debug event. this can be used, for instance, by a debugger to patch code held in ram in order to implement breakpoints. a special debug instruction is defined which is a user mode instruction, and its operation depends on whether the debug mode is enabled. 16-bit and 32-bit forms of the debug instruction are provided. if debug mode is enabled, the debug instruction causes a debug event to be raised and the action defined in the software break event specifier register swevt is taken. if the debug mode is not enabled, then the debug instruction is treated as a nop instruction. execution of an mtcr/mfcr instruction in order to protect the emulator resource , a debug event is raised whenever an mtcr or mfcr instruction is used to read or modify a user core sfr, but an event is not raised when the user reads or modifies one of the dedicated core debug registers: dbsr, crevt, swevt, exevt, tr0evt, tr1 evt, dms, dcx or dbgtcr. the action that is performed when an mtcr or mfcr instruction is executed on user core sfrs defined by the content of the emulator resource protection event specifier register crevt. 19.2.1.3 debug actions four types of debug actions are available: ? assert core break-out signal and brkout ( figure 19-4 ) via mcbs unit and port control ? halt the cpu core ? cause a breakpoint trap ? generate an interrupt request these debug actions are selected by prog ramming the corresponding event specifier registers. their contents determine which action shall be taken when the corresponding debug event occurs. in parallel the core suspend-out signal can be activated. 19.2.1.4 tricore ocds registers please refer to ?tricore core architecture v1.6? manual. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-9 v1.1, 2011-03 ocds, v1.5 19.2.2 pcp ocds level 1 pcp has no hardware means of generating trigger events. to set breakpoints, the debugger is expected to patch the code in the pcp code memory (cmem) with debug instructions. if a debug instruction is executed, the running channel program is terminated, either with debug exit or with error exit. the pcp has a suspend input, a break input and a break output. the break switch can send an external break request to the pcp, with the same consequence as above (debug exit or error exit). 19.2.3 sbcu ocds level 1 the bcu of the spb bus in the TC1798 offers very powerful means for trigger generation. the bcu contains comparators for ? the arbitration phase (look for specific bus master) ? the address phase (look for specific address or range) ? the data phase (look for read, write, supervisor mode, etc.) the results can be combined to generate a break request signal, which is sent to the break switch. the ocds registers of sbcu are described in chapter ?on-chip system buses and bus bridges? starting from section ?system bus control unit registers?. 19.2.4 dma/sdma ocds level 1 the dma/sdma controller in the TC1798 provides the following debugging capabilities: ? hard suspend mode of the dma/sdma controller (for test purposes only) ? soft suspend mode of dma/sdma channels ? break signal generation in suspend modes, the operations of dma/sdma channels or the complete module are stopped. under certain conditions, a break signal is also generated for the on-chip debug support logic. more details on the ocds level 1 debug capabilities of the dma/sdma controller are provided in section ?on-chip debug capabilities? of the dma/sdma chapter. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-10 v1.1, 2011-03 ocds, v1.5 19.3 debug interface (cerberus) the cerberus module is the on-chip unit that controls all ocds main debug functions. generally, the cerberus may not be used by any application software, since this could disturb the emulation tool behavior. the cerberus module is built up by three parts (see also figure 19-1 ): ? ocds system control unit - oscu ? ioclient ? multi core break switch - mcbs a tool can be connected to the device in two ways: ? a two line dap interface via the dap module receives the debugger commands, converts them and outputs them to the ioclient interface. ? standard jtag interface is connected vi a the jtag controller with the ioclient interface two additional pins are available to handl e an external break condition. the external debug hardware can access the cerberus registers and arbitrary memory locations across the system peripheral bus. features ? ocds level 1 control via ? 5-pin standard jtag interface ? 2-pin dap interface ? generation of external break condition via brkin /brkout pins possible ? full access to the complete spb bus address space via dap/jtag ? no user resources (hardware/software) are required ? no or minimum run-time impact (cerber us bus priority can be controlled) ? generic memory read/write functionality ? write word, half-word and byte ? block read and write ? full support for communication between an on-chip monitor program and the external debugger ? pending reads/writes can be optionally triggered by the ocds module (memory tracing) ? download of programs and data via dap/jtag ? control of the ocds blocks ? data acquisition 19.3.1 rw mode as the name implies, the rw mode is used by a dap/jtag host to r ead or write arbitrary memory locations via the dap/jtag interface. the rw mode needs the spb bus master interface of the cerberus to acti vely request data reads or data writes. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-11 v1.1, 2011-03 ocds, v1.5 data types supported ? word (32-bit): the default data type; us ed for single word transfers and block transfers. ? hword (16-bit): for reading 16-bit registers without getting a bus error, a dedicated ioclient instruction is provided. ? byte (8-bit): if the dap/jtag host wants to read a byte, it has to read the associated word or half-word. then the host has to extract the part needed itself. 19.3.2 communication mode in communication mode, the cerberus has no access to the internal buses and communication is established between the external dap/jtag host and a software monitor (embedded into the application pr ogram) via the cerberus registers. the communication mode is the default mode after reset. in communication mode, the external dap/jtag host is master of all transactions. the host requests the monitor to write or read a value to/from the cerberus register comdata. the difference to rw mode is that the read or write request is not actively executed by cerberus. the request just sets bits in the cpu accessible iosr register to signal the monitor that the debugger wants to send or receive a value. the software monitor has to poll the iosr register for that. 19.3.3 triggered transfers triggered transfers can be used to read from or write to a certain memory location when an ocds trigger becomes active. the main application for triggered transfers is to trace a certain memory location. this can be done, when the ocds of the cpu activates its break out signal, if this memory location is written by the user program. this event is used as a transfer trigger through the configuration of the mcbs. cerberus is co nfigured to read the location on this trigger. 19.3.4 multi core break switch in TC1798, there are several sources and targets for break signals. for instance the ocds run control of one processor can brea k the other processor unit. the multi core break switch (mcbs) is a part of the cer berus and allows to propagate break requests from sources to targets in a generic and flexible way. figure 19-4 shows the break signal interfaces of the mcbs. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-12 v1.1, 2011-03 ocds, v1.5 figure 19-4 break switch interfaces the mcbs unit supports the following features: ? break-in sources: tricore, pcp, dma, sbcu, mli0, mli1 ? up to two device pins configurable as brkin /brkout pins ? two independent break buses ? suspend generation supports delayed suspend ? break-to-suspend converter ocds_mcbs tricore pcp mcds (ed only) sbcu, sri, sdma dma, mli0/1 multi core break switch (mcbs) port control brkin halt brkin brkout brkout brkout brkout brkin brkin brkout mode error www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-13 v1.1, 2011-03 ocds, v1.5 ? create interrupt request with a break coming from a source ? synchronous restart of the system 19.4 jtag interface the jtag interface is a standardized unit that is typically used for boundary scan and internal device tests. because both of these applications are not active during normal device operation in a system, the jtag port can be used during normal device operation as an ideal interface for debugging tasks. 19.5 device access port (dap) the cost inferred by each non-functional pin is a strong argument to reduce the tool access port to as few pins as possible. the standardized device access port (dap) of infineon?s latest micro controllers offers a convenient method to get the required functionality at the least possible cost. with dap only two pins (dap0 for the clock, dap1 for the bidirectional data) are needed to communicate with the tool. dap uses a straightforward half-duplex protocol, i.e. the dap1 pin is used for data transfer from tool to device and from device to tool at different periods of time while the clock is provided by the tool to the dap0 input. 19.5.1 dap telegram format all information transport between tool and device is done in telegrams. mandatory 6 bit crc check sums assure secure transport even in noisy environments. splitting command and reply into separate units transported sequentially allows half-duplex transmission over a single bidirectional line. the physical interface medium can be chosen independently as long as the se rial bit stream can be transported. 19.5.2 dap telegram catalog this chapter lists the telegrams implemen ted by the TC1798. other telegrams are silently ignored, resulting in a time-out condition on the tool side. three groups of telegrams can be distinguished: control telegrams these four telegrams are needed to establish and maintain the connection from tool to device as such. no data is transported. ? sync - request synchronization pattern ? turn_off - shut down dap ? poll - get the current service request ? set_maxwait - adjust the parameter for time out www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-14 v1.1, 2011-03 ocds, v1.5 jtag telegrams the telegrams of this group are simple wrappers around the standard jtag commands, adding the relaxed timing and increased transmission speed and quality of dap. ? jtag_mode - switch dap to bypass mode ? jtag_reset - reset the tap controller ? jtag_setir - write the tap?s instruction register ? jtag_swapir - write and read the tap?s instruction register ? jtag_setdr - write the current jtag data register ? jtag_swapdr - write and read the current jtag data register ? jtag_moredr - write and read part of a long jtag data register client telegrams the last group allows direct access to ioclients like cerberus of the device, completely hiding the asynchronous timing between tool clock and system clock of the device. the following five telegrams belong to this group: ? client_set - define the current ioclient ? client_get - ask for the index of the current ioclient ? client_reset - reset the current ioclient ? client_write - write to the current ioclient ? client_read - read from the current ioclient 19.6 cerberus and jtag registers this section summarizes all cerberus an d jtag registers for reference purposes. details on these registers are contained in ocds documents that are available for tool suppliers on request (please contact local infineon representatives). all cerberus registers are prefixed ?cbs_? in the register map of a device. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-15 v1.1, 2011-03 ocds, v1.5 figure 19-5 jtag/cerberus register overview table 19-1 jtag/cerberus register overview register short name register long name address jtag controller registers bypass jtag bypass register (1-bit) 1) id jtag device identification register (32-bit) 1) instruction jtag instruction register (8-bit) 1) iopath io client selection register (2-bit) 1) cerberus registers ojconf oscu configuration by jtag register 1) register_file.vsd client_id 1) jdi registers ojconf 1) oscu registers mcdbbs mcbs registers oec ocntrl ostate 1) these registers are only accessible via the jtag interface bypass 1) jtag controller registers mcdbbss mcdssg mcdssgc src0 ioconf 1) ioinfo 1) ioaddr 1) iodata 1) id 1) instruction 1) iopath 1) jdpid comdata iosr intmod ictsa ictta cerberus registers src1 traddr 1) trig trigc trigs jtagid www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 on-chip debug support (ocds) users manual 19-16 v1.1, 2011-03 ocds, v1.5 oec ocds enable control register f000 0478 h ocntrl oscu configuration and control register f000 047c h ostate oscu status register f000 0480 h client_id jtag client identification register (32-bit) 1) ioconf configuration register (12-bit) 1) ioinfo state information for error analysis register (16-bit) 1) ioaddr address for data access register (32-bit) 1) iodata rw mode data register (32-bit) 1) jdpid cerberus module identification register f000 0408 h jtagid jtag device identification register f000 0464 h comdata communication mode data register f000 0468 h iosr status register f000 046c h intmod internal mode status and control register f000 0484 h ictsa internal controlled trace source address register f000 0488 h ictta internal controlled trace target address register f000 048c h mcdbbs break bus switch configuration register f000 0470 h mcdbbss break bus switch status register f000 0490 h mcdssg suspend signal generation status and control register f000 0474 h mcdssgc suspend signal generation configuration register f000 0494 h src0 service request control register 0 f000 04fc h src1 service request control register 1 f000 04f8 h traddr triggered transfer destination address 1) trig trigger to host f000 04a8 h trigc clear trigger to host f000 04a4 h trigs set trigger to host f000 04a0 h 1) these registers are only accessible via the jtag interface. table 19-1 jtag/cerberus register overview (cont?d) register short name register long name address www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-1 v1.1, 2011-03 asc, v1.5 20 asynchronous/synchronous serial interface (asc) this chapter describes the two asc asynch ronous/synchronous serial interfaces, asc0 and asc1, of the TC1798. it contains the following sections: ? functional description of the asc kernel, valid for asc0 and asc1 (see page 20-1 ) ? asc kernel register description, descr ibes all asc kernel specific registers (see page 20-19 ) ? TC1798 implementation-specific details and registers of the asc0/asc1 modules (see page 20-30 ). note: the asc kernel register names described in section 20.2 are referenced in the TC1798 users manual by the module name prefix ?asc0_? for the asc0 interface and by ?asc1_? for the asc1 interface. 20.1 asc kernel description figure 20-1 shows a global view of the asc interface. figure 20-1 general block diagram of the asc interface the asc module communicates with the external world via two i/o lines. the rxd line is the receive data input signal (and also output signal in synchronous mode), and txd is the transmit output signal. clock control, address decoding, and interrupt service request control are managed outside the asc module kernel. mcb05762_mod clock control address decoder interrupt control f asc asc module (kernel) port control rxd txd rxd txd to dma eir tbir tir rir www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-2 v1.1, 2011-03 asc, v1.5 20.1.1 overview the asc provides serial communication between the TC1798 and other microcontrollers, microprocesso rs, or external peripherals. the asc supports full-duplex asynchronous communication and half-duplex synchronous communication. in synchronous mode, data is transmitted or received synchronous to a shift clock that is generated by the asc internally. in asynchronous mode, 8-bit or 9-bit data transfer, parity g eneration, and the number of stop bits can be selected. parity, framing, and overrun error detection are provided to increase the reliability of data transfers. transmission and reception of data is double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back option. a 13-bit baud rate generator provides the asc with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider. features ? full-duplex asynchronous operating modes ? 8-bit or 9-bit data frames, lsb first ? parity-bit generation/checking ? one or two stop bits ? baud rate from 6.875 mbit/s to 1.64 bit/s (@ 110 mhz module clock) ? multiprocessor mode for automatic address/data byte detection ? loop-back capability ? half-duplex 8-bit synchronous operating mode ? baud rate from 13.75 mbit/s to 1119 bit/s (@ 110 mhz module clock) ? double-buffered transmitter/receiver ? interrupt generation ? on a transmit buffer empty condition ? on a transmit last bit of a frame condition ? on a receive buff er full condition ? on an error condition (fra me, parity, overrun error) ? implementation features ? connections to dma controller ? connections of receiver input to gpta (ltc) for baud rate detection and lin break signal measuring www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-3 v1.1, 2011-03 asc, v1.5 20.1.2 general operation the asc supports full-duplex asynchronous communication up to mbit/s and half-duplex synchronous communication up to mbit/s (@ mhz module clock). in synchronous mode, data is transmitted or received synchronous to a shift clock generated by the microcontroller. in asynchro nous mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. parity, framing, and overrun error detection are provided to in crease the reliability of data transfers. transmission and reception of data are double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back option. a 13-bit baud rate generator provides the asc with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider. a transmission is started by writing to the transmit buffer register, tbuf. only the number of data bits deter mined by the sele cted operating mode will actually be transmitted; that is, bits written to positi ons 9 through 15 of register tbuf are always insignificant. data transmission is double-buffered, so a new character may be written to tbuf before the transmission of the previous character is complete. this allows a back- to-back transmission of characters to take place without gaps. data reception is enabled by the receiver enable bit con.ren. after a reception has been completed, the received data and, if provided by the selected operating mode, the received parity bit can be read from the (read-only) receive buffer register rbuf. unused bits in the upper half of rbuf that are not required in the selected operating mode will be read as zeros. data reception is double-buffered, so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register. in all modes, receive buffer overrun error detection can be selected through bit con.oen. when enabled, the overrun error status flag con.oe and the error interrupt request line eir will be activated when the re ceive buffer register has not been read by the time reception of a second character is complete. in this case, the previously received character in the receive buffer is overwritten. the loop-back option (selected by bit co n.lb) allows the data currently being transmitted to be received simultaneously in the receive buffer. this may be used to test serial communication routines at an early stage without having to provide an external network. in loop-back mode, the alternate input/output function of port pins is not required. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-4 v1.1, 2011-03 asc, v1.5 20.1.3 asynchronous operation asynchronous mode supports full-duplex communication, in which both transmitter and receiver use the same data frame format and have the same baud rate. data is transmitted on pin txd and received on pin rxd. figure 20-2 shows the block diagram of the asc when operating in asynchronous mode. figure 20-2 asynchronous mode of the asc mca0620 1 13-bit baud rate timer 13-bit reload register f brt f div r f asc fractional divider fde f br brs serial port control ren fen pen oen lb receive int. req. transmit int. req. transmit buffer int. req. error int. req. eir tbi r tir rir m odd stp oe pe fe shift clock shift clock receive shift register transmit shift register txd receive buffer reg. rbuf samp- ling transmit buffer reg. tbuf rxd internal bus mux mux 2 3 16 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-5 v1.1, 2011-03 asc, v1.5 20.1.3.1 asynchronous data frames asynchronous data frames can consis t of 8-bit or 9-bit data frames. 8-bit data frames the 8-bit data frames consist of eith er eight data bits d7 ? d0 (con.m = 001 b ), or of seven data bits d6 ? d0 plus an automatically generated parity bit (con.m = 011 b ). parity may be odd or even, depending on bit con.odd. an even pari ty bit will be set if the modulo-2 sum of the seven data bits is 1. an odd parity bit will be cleared in this case. parity checking is enabled via bit con.pen (always off in 8-bit data mode). the parity error flag con.pe will be set, along with the er ror interrupt request fl ag, if a wrong parity bit is received. the received parity bi t itself will be stored in rbuf too. figure 20-3 asynchronous 8-bit frames mct06202 d5 d0 lsb d3 d1 d2 d4 d7 msb d6 start bit 0 (1st) stop bit (2nd) stop bit 8 data bits 11 c on.m = 001 b c on.m = 011 b d5 d0 lsb d3 d1 d2 d4 parity bit d6 msb start bit 0 (1st) stop bit (2nd) stop bit 7 data bits 11 10-/11-bit uart frame 10-/11-bit uart frame www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-6 v1.1, 2011-03 asc, v1.5 9-bit data frames the 9-bit data frames consist of nine data bits d8 ? d0 (con.m = 100 b ), or of eight data bits d7 ? d0 plus an automatically generated parity bit (con.m = 111 b ) or of eight data bits d7 ? d0 plus wake-up bit (con.m = 101 b ). parity may be odd or even, depending on bit con.odd. an even parity bit will be set if the modulo-2-sum of the eight data bits is 1. an odd parity bit will be cleared in this case. parity checking is enabled via bit con.pen (always off in 9-bit data and wake-up mode). the parity error flag con.pe will be set along with the error interrupt request flag if a wrong parity bit is received. the received parity bit itself will be stored in rbuf too. figure 20-4 asynchronous 9-bit frames in wake-up mode (con.m = 101 b ), received frames are transferred to the receive buffer register only if the 9 th bit (the wake-up bit) of the frame is 1. if this bit is 0, no receive interrupt request will be activated and no data will be transferred. this feature can be used to control co mmunication in multi-processor systems, for example: when the master processor aims to transmit a block of data to one of several slaves, it first sends out an address ?byte? (in this case, a ?byte? consists of nine bits) that identifies the target slave. an address ?byte? differs from a data ?byte? in that the additional 9 th bit is a 1 for an address ?byte? but is a 0 for a data ?byte?, so, no slave will be interrupted by a data ?byte?. an address ?byte? will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the eight lsbs of the received character (the address). the addr essed slave will switch to 9-bit dat a mode (for example, by clearing bit con.m[0]), which enables it to also receive the data bytes that will be coming (having the wake-up bit cleared). the slaves that we re not being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data ?bytes?. 11 mct06203 d5 d0 lsb d3 d1 d2 d4 d7 d6 start bit 0 (1st) stop bit (2nd) stop bit 9 data bits bit 9 con.m = 100 b : bit 9 = data bit d8 con.m = 101 b : bit 9 = wake-up bit con.m = 111 b : bit 9 = parity bit 11-/12-bit uart frame www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-7 v1.1, 2011-03 asc, v1.5 20.1.3.2 asynchronous transmission asynchronous transmission begins when the next overflow of the divide-by-16 baud rate timer (transition of the baud rate clock f br ) occurs, if bit con.r is set and data has been loaded into tbuf. the transmitted da ta frame consists of three elements: 1. the start bit 2. the data field (8 or 9 bits, lsb first, including a parity bit, if selected) 3. the delimiter (1 or 2 stop bits) data transmission is double-buffered. when the transmitter is idle, the transmit data loaded into tbuf is immediately moved to the transmit shift register; thus, freeing tbuf for the next transmit data to be loaded. this is indicated by the transmit buffer interrupt request line tbir being activated. tbuf ma y then be loaded with the next transmit data while transmission of the previous one continues. the transmit interrupt request line tir will be activated before the last bit of a frame is transmitted, that is, before the first or the second stop bit is shifted out of the transmit shift register. note: a dedicated gpio device pin which is connected to the m odule output pin txd must be configured by software as al ternate data output for asynchronous transmission. 20.1.3.3 asynchronous reception asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin rxd, on the condition that bits con.r and con.ren are set. the receive data input pin rxd is sampled at sixteen times the rate of the selected baud rate. a majority decision of the 7 th , 8 th and 9 th sample determines the effective sampled bit value. this avoids erroneous results that may be caused by noise. if the detected value is not a 0 when the start bit is sampled, the receive circuit is reset and waits for the next 1-to-0 transition at pin rxd. if the start bit proves valid, the receive circuit continues sampling and shifts the incoming data frame into the receive shift register. when the last stop bit has been received, the contents of the receive shift register are transferred to the receive data buffer register rbuf. simultaneously, the receive interrupt request line rir is activated after the 9 th sample in the last stop bit time-slot (as programmed), regardless whether valid stop bits have been received or not. the receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input line. note: a dedicated gpio pin that is conne cted to the module input pin rxd must be configured by software as input for asynchronous reception. asynchronous reception is stopped by clearing bit con.ren. a currently received frame is completed including generation of the receive interrupt request and an error interrupt request, if appropriate. start bits that follow this frame will not be recognized. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-8 v1.1, 2011-03 asc, v1.5 note: in wake-up mode, received frames are transferred to the receive buffer register only if the 9 th bit (the wake-up bit) is 1. if this bit is 0, no receive interrupt request will be activated and no data will be transferred. 20.1.3.4 rxd/txd data path sele ction in asynchronous modes the data paths for the serial input and output data in asynchronous modes are affected by control bit con.lb (loop-back) as shown in figure 20-5 . figure 20-5 rxd/txd data path selection in asynchronous modes mca0620 4 asc asynch. mode logic r xd con lb tx d 0 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-9 v1.1, 2011-03 asc, v1.5 20.1.4 synchronous operation synchronous mode supports half-duplex communication, usable for simple i/o expansion via shift registers. data is transmitted and received via pin rxd while pin txd outputs the shift clock. these signals are ty pically connected as alternate functions with gpio port pins. synchronous mode is selected with con.m = 000 b . eight data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator. the shift clock is active only as long as data bits are transmitted or received. figure 20-6 synchronous mode of serial channel asc mca0620 5 brs f brt f div r f asc f br serial port control ren oen lb receive int. req. transmit int. req. transmit buffer int. req. error int. req. eir tbi r tir rir m = 000 b oe shift clock shift clock receive shift register transmit shift register receive buffer reg. rbuf transmit buffer reg. tbuf r xd internal bus t xd mux 0 1 mux 4 2 3 13-bit baud rate timer 13-bit reload register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-10 v1.1, 2011-03 asc, v1.5 20.1.4.1 synchronous transmission synchronous transmission begins within four state times after data has been loaded into tbuf, provided that con.r is set and co n.ren = 0 (half-duplex, no reception), with one exception: in loop-back mode (bit con.lb set), con.ren must be set for reception of the transmitted byte. data transmission is double-buffered. when the transmitter is idle, the transmit data loaded into tbuf is immediately moved to the transmit shift register, thus freeing tbuf for the next data to be sent. this is indicated by the transmit buffer interrupt request line tbir being ac tivated. tbuf may now be loaded with the next data, while transmission of the prev ious one continues. the data bits are transmitted synchronously with the shift clock. after the bit time for the 8 th data bit, both txd and rxd will be set to high level, the transmit interrupt request line tir is activated, and serial data transmission stops. note: the dedicated gpio device pins t hat are connected to txd and rxd must be configured by software as alternate data ou tputs in order to provide the shift clock and the output data during synchronous transmission. 20.1.4.2 synchronous reception synchronous reception is initiated by settin g bit con.ren = 1. if bit con.r = 1, the data applied at rxd is clocked into the receive shift register synchronously to the clock which is output at txd. after the 8 th bit has been shifted in, the contents of the receive shift register are transferred to the receive data bu ffer rbuf, the receive interrupt request line rir is activated, the receiver enable bit co n.ren is reset, and serial data reception stops. synchronous reception is stopped by cleari ng bit con.ren. any byte that is currently being received is completed, including the generation of the receive interrupt request and an error interrupt request, if appropriate. writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission. if a previously received byte has not been read out of the receive buffer register by the time the reception of the next byte is complete, both the error interrupt request line eir and the overrun error status flag con.oe will be activated/set, provided that the overrun check has been enabled by bit con.oen. note: the dedicated gpio device pin that is connected to txd must be configured by software as alternate data output in order to provide the shift clock. the dedicated gpio device pin that is connected to rxd must be configured by software as input during synchronous reception. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-11 v1.1, 2011-03 asc, v1.5 20.1.4.3 synchronous timing figure 20-7 shows timing diagrams of the asc synchronous mode data reception and data transmission. in idle state, the shift clock is at high level. with the beginning of a synchronous transmission of a data byte, the da ta is shifted out at rxd with the falling edge of the shift clock. if a data byte is received through rxd, data is latched with the rising edge of the shift clock. one shift clock cycle ( f br ) delay is inserted between two consecutive receive or transmit data bytes. figure 20-7 asc synchronous mode waveforms d0 valid data n+2 valid data n valid data n+1 data bit n+2 data bit n data bit n+1 mct06206 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 r eceive data ( rxd) t ransmit data ( rxd) s hift clock ( txd) c ontinuous transmit timing receive/transmit timing s hift clock ( txd) r eceive data ( rxd) shift latch shift latch shift 1. byte 1. byte 2. byte 2. byte t ransmit data ( rxd) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-12 v1.1, 2011-03 asc, v1.5 20.1.5 baud rate generation the asc has its own dedicated 13-bit baud rate generator with 13-bit reload capability, allowing baud rate generation independent of other timers. the baud rate generator is clocked with a clock ( f div ) which is derived via a prescaler from the asc module clock f asc . the baud rate timer is counting downwards and can be started or stopped through the baud rate generator run bit con.r. each underflow of the timer generates one clock pulse to the serial channel. the timer is reloaded with the value stored in its 13-bit reload register at each underflow. the resulting clock f brt is again divided by a factor for the baud rate clock ( 16 in asynchronous operating modes and 4 in synchronous operating mode). the prescaler is selected by the bits con.brs and con.fde. in the asynchronous operating modes, a fractional divider prescaler unit is available (in addition to the two fixed dividers) that allows selection of prescaler divider ratios of n/512 with n = 0-511. therefore, the baud rate of asc is determined by the module clock, the content of register fdv, the reload value in register bg, and the operating mode (asynchronous or synchronous). register bg is the dual-function baud rate generator/reload register. reading bg returns the contents of the timer in bit field br_value (bits 31:13 return zero), while writing to bg always updates the reload register (bits 31:13 are insignificant). an auto-reload of the timer with the contents of the reload register is performed each time bg is written to. however, if con.r = 0 at the time the write operation to bg is performed, the timer will not be reloaded until the first instruction cycle after con.r = 1. for a clean baud rate initialization, bg should only be written if con.r = 0. if bg is written with con.r = 1, an unpredictable behavior of the asc may occur during running transmit or receive operations. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-13 v1.1, 2011-03 asc, v1.5 20.1.5.1 baud rates in asynchronous mode for asynchronous operation, the baud rate generator provides a clock f brt with sixteen times the rate of the established baud rate. every received bit is sampled on the 7 th , 8 th and 9 th cycle of this clock. the clock divider circuitry, which generates the input clock f div for the 13-bit baud rate timer, is extended by a fractional divider circuitry that allows the adjustment of more accurate baud rates and the extension of the baud rate range. the baud rate of the baud rate generator depends on the settings of the following bits and register values: ? input clock f asc ? selection of the baud rate timer input clock f div by bits con.fde and con.brs ? if bit con.fde = 1 (fractional divider): value of register fdv ? value of the 13-bit reload register bg the output clock of the baud rate timer with the reload register is the sample clock in the asynchronous operating modes of the asc. for baud rate calculations, this baud rate clock f br is derived from the sample clock f brt by a division of sixteen. figure 20-8 asc baud rate generator circuitry in asynchronous modes mca06207 13-bit baud rate timer sample clock 13-bit reload register brs f brt f div r f asc 2 brs 0 1 selected divide r 3 fractional divider fde baud rate clock f br fde 0 0 x 1 fractional divide r 2 3 16 mux www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-14 v1.1, 2011-03 asc, v1.5 using the fixed input clock divider the baud rate for asynchronous operation of the serial channel asc when using the fixed input clock divider ratios (con.fde = 0) and the required bg reload value for a given baud rate can be determined by the following formulas: bg represents the content of the reload register bit field bg.br_value, taken as an unsigned 13-bit integer. the maximum baud rate that can be achieved for the asynchronous operating modes when using the two fixed clock dividers and a module clock of 110 mhz is 3.4375 mbit/s. table 20-2 lists various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baud rate. note: con.fde must be 0 to achieve the b aud rates in the table above. the deviation errors given in the table are rounded. us ing a baud rate crystal will provide correct baud rates without deviation errors. table 20-1 asynchronous baud rate formulas using the fixed input clock dividers fde brs bg formula 0 0 0 ? 8191 1 table 20-2 typical asynchronous baud rates using fixed input clock dividers baud rate con.brs = 0, f asc = 110 mhz con.brs = 1, f asc = 110 mhz deviation error reload value deviation error reload value 3.4375 mbit/s ? 0000 h ?? 19.2 kbit/s +0.02% / -0.6% 00b2 h / 00b3 h +0.3% / -0.6% 0076 h / 0077 h 9600 bit/s +0.02% / -0.3% 0165 h / 0166 h +0.3% / -0.1% 00ed h / 00ee h 4800 bit/s +0.02% / -0.1% 02cb h / 02cc h +0.1% / -0.1% 01dc h / 01dd h baud rate f asc 32 bg 1 + () ------------------------------------ = bg f asc 32 baud rate -------------------------------------- - 1 ? = baud rate f asc 48 bg 1 + () ------------------------------------ - = bg f asc 48 baud rate --------------------------------------- 1 ? = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-15 v1.1, 2011-03 asc, v1.5 using the fractional divider when the fractional divider is selected, the input clock f div for the baud rate timer is derived from the module clock f asc by a programmable fractional divider. if con.fde = 1, the fractional divider is activated. it divides f asc by a fraction of n/512 for any value of n from 0 to 511. if n = 0, the divider ratio is 1, which means that f div = f asc . in general, the fractional divider allows the baud rate to be programmed with much better accuracy than with the two fixed prescaler divider stages. note: in fractional divider mode, the clock f div can have a maximum period jitter of one f asc clock period. bg represents the content of the reload register bit field bg.br_value, taken as an unsigned 13-bit integer. fdv represents the contents of the fractional divider register bit field fdv.fd_value, taken as an unsigned 9-bit integer. table 20-3 asynchronous baud rate formulas using the fractional input clock divider fde brs bg fdv formula 1 ? 0 ? 8191 1 ? 511 0 table 20-4 typical asynchronous baud rates using the fractional input clock divider f asc desired baud rate bg fdv resulting baud rate deviation 110 mhz 115.2 kbit/s 003a h 1fa h 115.160 kbit/s -0.04% 57.6 kbit/s 0075 h 1fa h 57.579 kbit/s -0.04% baud rate fdv 512 ------------ f asc 16 bg 1 + () ------------------------------------ = baud rate f asc 16 bg 1 + () ------------------------------------ = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-16 v1.1, 2011-03 asc, v1.5 20.1.5.2 baud rates in synchronous mode for synchronous operation, the baud rate generator provides a clock f brt that runs with four times the established baud rate (see figure 20-9 ). figure 20-9 asc baud rate generator circuitry in synchronous mode the baud rate for synchronous operation of the serial channel asc can be determined by the formulas as shown in table 20-5 . bg represents the content of the reload register bit field bg.br_value, taken as an unsigned 13-bit integer. the maximum baud rate that can be achieved in synchronous mode when using a module clock of mhz is mbit/s. table 20-5 synchronous baud rate formulas brs bg formula 0 0 ? 8191 1 mca06208 13-bit baud rate timer shift / samp le clock 13-bit reload register brs f brt f div r f asc 2 brs 0 1 selected divide r 3 2 3 4 mux baud rate f asc 8bg1 + () -------------------------------- - = bg f asc 8 baud rate ----------------------------------- 1 ? = baud rate f asc 12 bg 1 + () ------------------------------------ = bg f asc 12 baud rate -------------------------------------- - 1 ? = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-17 v1.1, 2011-03 asc, v1.5 20.1.6 hardware error detection capabilities to improve the reliability of serial data exchange, the serial channel asc provides an error interrupt request flag that indicates the presence of an error and three (selectable) error status flags in register con that indicate which error has been detected during reception. upon completion of a reception, the error in terrupt request line eir will be activated simultaneously with the receive interrupt request line rir, if one or more of the following conditions are met: ? if the framing error detection enable bit con.fen is set and any of the expected stop bits is not high, the framing error flag con.fe is set, indicating that the error interrupt request is due to a framing error (asynchronous operating modes only). ? if the parity error detection enable bit con.pen is set in the modes where a parity bit is received and the parity check on the received data bits proves false, the parity error flag con.pe is set, indicating that the error interrupt request is due to a parity error (asynchronous operating modes only). ? if the overrun error detection enable bit con.oen is set and the last character received was not read out of the receive buffer by software or dma transfer at the time the reception of a new frame is complete, the overrun error flag con.oe is set indicating that the error interrupt request is due to an overrun error (asynchronous and synchronous modes). 20.1.7 interrupts four interrupt sources are provided for serial channel asc. line tir indicates a transmit interrupt, tbir indicates a transmit buffer interrupt, rir indicates a receive interrupt, and eir indicates an error interrupt of the serial channel. the interrupt output lines tbir, tir, rir, and eir are activated (active state) for two periods of the module clock f asc . the cause of an error interrupt request eir (framing, parity, overrun error) can be identified by the error status flags con.fe, con.pe, and con.oe. note: by contrast to the error interrupt request line eir, the error status flags con.fe/con.pe/con.oe are not reset automatically but must be cleared by software. for normal operation (that is, other than error interrupt), the asc provides three interrupt requests to control data exchange via this serial channel: ? tbir is activated when data is moved from tbuf to the transmit shift register. ? tir is activated before the last bit of an asynchronous frame is transmitted, or after the last bit of a synchronous frame has been transmitted. ? rir is activated when the received frame is moved to rbuf. while the task of the receive interrupt handler is quite clear, the transmitter is serviced by two interrupt handlers. this provides advantages for the servicing software. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-18 v1.1, 2011-03 asc, v1.5 for single transfers, it is sufficient to use the transmitter interrupt (tir), which indicates that the previously loaded data has been transmitted, except for the last bit of an asynchronous frame. for multiple back-to-back transfers, it is necessary to load the following piece of data at least before the last bit of the previous frame has been transmitted. in asynchronous mode, this leaves just one bit-time for the handler to respond to the transmitter interrupt request; in synchronous mode, it is entirely impossible. using the transmit buffer interrupt (tbir) to reload transmit data provides the time necessary to transmit a complete frame for the service routine, as tbuf may be reloaded while the previous data is still being transmitted. figure 20-10 asc interrupt generation as shown in figure 20-10 , tbir is an early trigger for the reload routine, while tir indicates the completed transmission. software using handshake should, therefore, rely on tir at the end of a data block to ensure that all data has been transmitted. idle start stop start stop start stop idle mct06209 asynchronous mode tbir tbir tir rir tbir tir tir rir rir idle idle tbir tbir tir tbir tir tir rir rir rir s ynchronous mode www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-19 v1.1, 2011-03 asc, v1.5 20.2 asc kernel registers this section describes the kernel registers of the asc module. all asc kernel register names described in this section will be referenced in other parts of the TC1798 users manual by the module name prefix ?asc0_? for the asc0 interface and ?asc1_? for the asc1 interface. all registers in the asc address spaces are reset with the application reset. asc kernel register overview figure 20-11 asc kernel registers the complete and detailed address map of the of the asc module and its registers is described in table 20-10 on page 20-42 . table 20-6 registers address space module base address end address note asc0 f000 0a00 h f000 0aff h ? asc1 f000 0b00 h f000 0bff h ? table 20-7 registers overview - asc kernel registers register short name register long name offset address 1) description see pisel peripheral input select register 0004 h page 20-20 id module identification register 0008 h page 20-21 con control register 0010 h page 20-22 bg baud rate timer reload register 0014 h page 20-27 fdv fractional divider register 0018 h page 20-27 tbuf transmit buffer register 0020 h page 20-28 mca5772a_mod con bg tbuf control registers data registers fdv rbuf pisel whbcon identification register id www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-20 v1.1, 2011-03 asc, v1.5 20.2.1 control registers the asc module kernel provides two receiv e input lines, rxd_i0 and rxd_i1. bit ris in the peripheral input select register pi sel determines which of theses two input lines is taken for rxd receive input purposes. note: implementation specific de tails (ris functionality) see ?peripheral input select register? on page 20-35 . rbuf receive buffer register 0024 h page 20-29 whbcon write hardware bits control register 0050 h page 20-25 1) the absolute register address is calculated as follows: module base address (( table 20-6 on page 20-19 ) + offset address (shown in this column) pisel peripheral input select register (04 h ) reset value: 0000 0000 h 31 0 0 ri s rrw field bits type description ris 0rw receive input select 0 b asc receiver input rxd_i0 selected 1 b asc receiver input rxd_i1 selected 0 [31:1] r reserved read as 0; should be written with 0. table 20-7 registers overview - asc kernel registers (cont?d) register short name register long name offset address 1) description see www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-21 v1.1, 2011-03 asc, v1.5 the asc module identification register id contains read-only information about the module version. id module identificat ion register (08 h ) reset value: 0000 44xx h 31 16 15 8 7 0 0 modnum modrev rrr field bits type description modrev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). modnum [15:8] r module number value this bit field defines the module identification number for the asc: 44 h 0 [31:16] r reserved read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-22 v1.1, 2011-03 asc, v1.5 the serial operating modes of the asc module are controlled by its control register con. this register contains control bits for mode and error check selection, and status flags for error identification. con control register (10 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 r lb brs odd fde oe fe pe oen fen pen ren stp m rw rw rw rw rw rwh rwh rwh rw rw rw rwh rw rw field bits type description m [2:0] rw mode selection 000 b 8-bit data synchronous mode 001 b 8-bit data asynchronous mode 010 b reserved. do not use this combination. 011 b 7-bit data + parity asynchronous mode 100 b 9-bit data asynchronous mode 101 b 8-bit data + wake up bit asynchronous mode 110 b reserved. do not use this combination. 111 b 8-bit data + parity asynchronous mode stp 3rw number of stop bit selection 0 b one stop bit 1 b two stop bits ren 4rwh receiver enable control 0 b receiver disabled 1 b receiver enabled bit is reset by hardware after reception of a byte in synchronous mode. pen 5rw parity check enable (asynchronous mode only) 0 b ignore parity 1 b check parity www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-23 v1.1, 2011-03 asc, v1.5 fen 6rw framing check enable (asynchronous mode only) 0 b ignore framing errors 1 b check framing errors oen 7rw overrun check enable 0 b ignore overrun errors 1 b check overrun errors pe 8rwh parity error flag set by hardware on a parity error (pen = 1). must be reset by software. fe 9rwh framing error flag set by hardware on a framing error (fen = 1). must be reset by software. oe 10 rwh overrun error flag set by hardware on an overrun error (oen = 1). must be reset by software. fde 11 rw fractional divider enable 0 b fractional divider disabled 1 b fractional divider is enabled and used as prescaler for baud rate timer (bit brs is don?t care) odd 12 rw parity selection 0 b even parity selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data) 1 b odd parity selected (parity bit = 1 on even number of 1s in data, parity bit = 0 on odd number of 1s in data) brs 13 rw baud rate selection 0 b baud rate timer prescaler divide-by-2 selected 1 b baud rate timer prescaler divide-by-3 selected brs is don?t care if fde = 1 (fractional divider enabled) lb 14 rw loop-back mode enable 0 b loop-back mode disabled 1 b loop-back mode enabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-24 v1.1, 2011-03 asc, v1.5 serial data transmission or reception is possi ble only when the run bit con.r is set to 1. otherwise, the serial interface is idle. to avoid unpredictable behavior of the serial interface, do not program the mode control field con.m to one of the reserved combinations. critical ?rwh? bits register con contains three error flags: pe, fe, and oe. if the software modifies only one of these error flags, it uses typically a read-modify-write (rmw) instruction. when one of the other error flags that is not intended to be modified by the rmw instruction is changed by hardware after the read access but before the write back access of the rmw instruction, it is overwritten with the old bit value, and the hardware change of the bit gets lost. this problem does not affect the bits that are intended to be modified by the rmw instruction. it only affects bits that were not intended to be changed with the rmw instruction. the three error flags in register con and the ren bit can be additionally set or reset by software via register whbcon. this capabili ty avoids the problem with the con register rmw instruction access to the error flags. whbcon is a write-only register. reading whbcon always returns 0000 0000 h . r 15 rw baud rate generator run control 0 b baud rate generator disabled (asc inactive) 1 b baud rate generator enabled register bg should only be written if r = 0. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-25 v1.1, 2011-03 asc, v1.5 whbcon write hardware bits control register (50 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 set oe set fe set pe clr oe clr fe clr pe 0 set ren clr ren 0 r wwwwww r ww r field bits type description clrren 4w clear receiver enable bit 0 b no effect 1 b bit con.ren is cleared. bit is always read as 0. setren 5w set receiver enable bit 0 b no effect 1 b bit con.ren is set. bit is always read as 0. clrpe 8w clear parity error flag 0 b no effect 1 b bit con.pe is cleared. bit is always read as 0. clrfe 9w clear framing error flag 0 b no effect 1 b bit con.fe is cleared. bit is always read as 0. clroe 10 w clear overrun error flag 0 b no effect 1 b bit con.oe is cleared. bit is always read as 0. setpe 11 w set parity error flag 0 b no effect 1 b bit con.pe is set. bit is always read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-26 v1.1, 2011-03 asc, v1.5 note: when the set and clear bits for an error flag are set at the same time during a whbcon write operation (e.g setpe = clrpe = 1), the error flag in con is not affected. setfe 12 w set framing error flag 0 b no effect 1 b bit con.fe is set. bit is always read as 0. setoe 13 w set overrun error flag 0 b no effect 1 b bit con.oe is set. bit is always read as 0. 0 [3:0], [7:6], [31:14] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-27 v1.1, 2011-03 asc, v1.5 the baud rate timer reload register bg of the asc module contains the 13-bit reload value for the baud rate timer in asynchronous and synchronous modes. the fractional divider register fdv of the asc module contains the 9-bit divider value for the fractional divider (asynchronous mode only). bg baud rate timer/reload register (14 h ) reset value: 0000 0000 h 31 13 12 0 0 br_value rrwh field bits type description br_value [12:0] rwh baud rate timer/reload register value reading br_value returns the 13-bit content of the baud rate timer. writing br_value loads the baud rate timer reload register. bg should only be written if con.r = 0. 0 [31:13] r reserved read as 0; should be written with 0. fdv fractional divider register (18 h ) reset value: 0000 0000 h 31 9 8 0 0fd_value rrw field bits type description fd_value [8:0] rw fractional divider register value fd_value contains the 9-bit value n of the fractional divider which determines the fractional divider ratio n/512 (n = 0-511). with n = 0, the fractional divider is switched off (divider ratio = 1). 0 [31:9] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-28 v1.1, 2011-03 asc, v1.5 20.2.2 data registers the transmit buffer register tbuf of the asc module contains the transmit data value in asynchronous and synchronous modes. tbuf transmit buffer register (20 h ) reset value: 0000 0000 h 31 9 8 0 0td_value rrw field bits type description td_value [8:0] rw transmit data register value tbuf contains the data to be transmitted in the asynchronous and synchronous operating modes of the asc. data transmission is double-buffered; therefore, a new value can be written to tbuf before the transmission of the previous value is complete. 0 [31:9] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-29 v1.1, 2011-03 asc, v1.5 the receive buffer register rbuf of the asc module contains the receive data value in asynchronous and synchronous modes. rbuf receive buffer register (24 h ) reset value: 0000 0000 h 31 9 8 0 0rd_value rrh field bits type description rd_value [8:0] rh receive data register value rbuf contains the received data bits and, depending on the selected mode, the parity bit in the asynchronous and synchronous operating modes of the asc. in asynchronous mode, with con.m = 011 b (7-bit data + parity), the received parity bit is written into rbuf.7. in asynchronous mode, with con.m = 111 b (8-bit data + parity), the received parity bit is written into rbuf.8. 0 [31:9] r reserved read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-30 v1.1, 2011-03 asc, v1.5 20.3 asc0/asc1 module implementation this section describes asc0/asc1 module interfaces with the clock control, port connections, interrupt control, and address decoding. 20.3.1 interfaces of the asc modules the serial i/o lines of both modules are connected either to port 5 or port 6. each of the asc modules is further supplied with interrupt control, address decoding, and port control logic. two dma requests can be generated by each asc module. both asc modules are supplied by one common clock control unit. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-31 v1.1, 2011-03 asc, v1.5 figure 20-12 asc0/asc1 module implementation and interconnections some of the receive inputs of the asc0 and asc1 are connected via a multiplexer to an ltc input of the gpta module. details are described in the scu and the gpta chapters. mcb05773_mod asc0 module (kernel) port 5 & port 6 control asc1 module (kernel) p6.8 / rxd0b p6.9 / txd0 interrupt control eir tbir tir rir clock control address decoder interrupt control f asc eir tbir tir rir p5.0 / rxd0a p5.1 / txd0 p6.10 / rxd1b p6.11 / txd1 p5.2 / rxd1a p5.3 / txd1 rxd_i1 rxd_o rxd_i0 txd_o to dma asc0_rdr asc0_tdr to dma asc1_rdr asc1_tdr rxd_i1 rxd_o rxd_i0 txd_o to gpta asc1_tbdr asc0_tbdr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-32 v1.1, 2011-03 asc, v1.5 20.3.2 asc0/asc1 module related external registers figure 20-13 summarizes the module-related external registers which are required for asc0/asc1 programming (see also figure 20-11 for the module kernel-specific registers). figure 20-13 asc0/asc1 implementation-s pecific special function registers mca05774 asc0_clc asc0_tsrc p5_iocr0 asc0_rsrc asc0_esrc asc0_tbsrc asc1_tsrc asc1_rsrc asc1_esrc asc1_tbsrc control registers interrupt registers port registers asc0_pisel asc1_pisel p6_iocr8 p5_pdr p6_pdr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-33 v1.1, 2011-03 asc, v1.5 20.3.2.1 clock control register the clock control register asc0_clc allows the programmer to adapt the functionality and power consumption of the asc modules to the requirements of the application. the description below shows the clock control register functionality which is implemented for the asc modules. because asc0 and asc1 share one common clock control interface, asc0_clc controls the f asc module clock signal, sleep mode, suspend mode and fast shut-off mode for both modules. asc0_clc asc0 clock control register (00 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 rmc 0 fs oe sb we e dis sp en dis s dis r rw r rw w rw rw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the module. diss 1r module disable status bit bit indicates the current status of the module. spen 2rw module suspend enable for ocds used to enable the suspend mode. edis 3rw sleep mode en able control used to control module?s sleep mode. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. fsoe 5rw fast switch off enable used to switch off fast clock in suspend mode. rmc [15:8] rw 8-bit clock divider value in run mode 0 [7:6], [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-34 v1.1, 2011-03 asc, v1.5 note: after a hardware reset operation, the two asc modules are disabled. note: the number of module clock cycles (wait states) which are required for a ?destructive read? access (means: flags/bits are set/reset by one read access) to asc module register depends on the selected clc clock frequency, which is selected via bit field rmc in the clc register. therefore, increasing asc0_clc.rmc may result in a longer fpi bus read cycle access time. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-35 v1.1, 2011-03 asc, v1.5 20.3.2.2 peripheral input select register the asc0/asc1 modules include a peripheral input select registers that are used to switch the rxd input lines of the asc0/asc1 module kernels between different pairs of pins of port 5 and port 6 as shown in figure 20-14 . register asc0_pisel controls the rxd input selection for asc0, and asc1_pisel controls the rxd input selection for asc1. figure 20-14 rxd input line selection of the asc modules asc0 module (kernel) asc1 module (kernel) mca05775_mod p5.0 / rxd0a p5.1 / txd0 rxd_i1 rxd_o pisel rxd_i0 port 5 control txd_o p5.2 / rxd1a p5.3 / txd1 rxd_i1 rxd_o pisel rxd_i0 txd_o p6.8 / rxd0b 6.9 / txd0 port 6 control p6.10 / rxd1b p6.11 / txd1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-36 v1.1, 2011-03 asc, v1.5 asc0_pisel asc0 peripheral input select register (04 h ) reset value: 0000 0000 h 31 10 0 r i s rrw field bits type description ris 0rw receive input select 0 b asc0 receiver input rxd0a (p5.0) selected 1 b asc0 receiver input rxd0b (p6.8) selected 0 [31:1] 0 reserved read as 0; should be written with 0. asc1_pisel asc1 peripheral input select register (04 h ) reset value: 0000 0000 h 31 10 0 r i s rrw field bits type description ris 0rw receive input select 0 b asc1 receiver input rxd1a (p5.2) selected 1 b asc1 receiver input rxd1b (p6.10) selected 0 [31:1] 0 reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-37 v1.1, 2011-03 asc, v1.5 20.3.2.3 port control registers as shown in figure 20-14 , the i/o lines of the asc modules are connected to class a2 port pins of port 3. additionally to the pisel register programming, the required asc port lines must be programmed by software for the desired asc input/output functionality. two selections must be executed: ? input/output function selection (controlled by the port input/output control registers iocr) ? pad driver characteristics selection for the outputs (controlled by the port pad driver mode register pdr) input/output function selection the port input/output control registers contain the 4-bit wide bit fields that select the digital output and input driver characteristics such as pull-up/down devices, port direction (input/output), open-drain, and alternate output selections individually for each pin. the i/o lines for the asc modules are controlled by the port input/output control registers p5_iocr0 and p6_iocr8. table 20-8 shows how bits and bit fields must be programmed for the required i/o functionality of the asc i/o lines. this table also shows the values of the peripheral input select registers. table 20-8 asc0/asc1 i/o control selection and setup module related asc interrupt dma request line description i/o asc0 p5.0/rxd0a asc0_pisel.ris = 0 p5_iocr0.pc0 = 0xxx b input ? p5_iocr0.pc0 = 1x01 b output 1) 1) applicable in synchronous mode only. p6.8/rxd0b asc0_pisel.ris = 1 p6_iocr8.pc8 = 0xxx b input ? p6_iocr8.pc8 = 1x10 b output 1) p5.1/txd0 ? p5_iocr0.pc1 = 1x01 b output p6.9/txd0 p6_iocr8.pc9 = 1x10 b output asc1 p5.2/rxd1a asc1_pisel.ris = 0 p5_iocr0.pc2 = 0xxx b input ? p5_iocr0.pc2 = 1x01 b output 1) p6.10/rxd1b asc1_pisel.ris = 1 p6_iocr8.pc10 = 0xxx b input ? p6_iocr8.pc10 = 1x10 b output 1) p5.3/txd1 ? p5_iocr0.pc3 = 1x01 b output p6.11/txd1 p6_iocr8.pc11 = 1x10 b output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-38 v1.1, 2011-03 asc, v1.5 note: in synchronous operating mode of the asc, the type of the selected rxd port pin (input or output) is not automatically controlled by the asc but must be defined by a user program by writing the appropr iate bit field in the iocr registers. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-39 v1.1, 2011-03 asc, v1.5 20.3.2.4 interrupt control registers the eight interrupts of the asc0 and asc1 modules are controlled by the following service request control registers: ? asc0_tsrc, asc1_tsrc: control the transmit interrupts ? asc0_rsrc, asc1_rsrc: control the receive interrupts ? asc0_esrc, asc1_esrc: control the error interrupts ? asc0_tbsrc, asc1_tbsrc: control the transmit buffer empty interrupts tsrc transmit interrupt service request control register (f0 h ) reset value: 0000 0000 h rsrc receive interrupt service request control register (f4 h ) reset value: 0000 0000 h esrc error interrupt service request control register (f8 h ) reset value: 0000 0000 h tbsrc transmit buffer inte rrupt service request control register (fc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-40 v1.1, 2011-03 asc, v1.5 20.3.3 dma requests the dma request output lines of the asc0/asc1 modules become active whenever the related asc interrupt line becomes activated. the dma request lines are connected to the dma controller as shown in table 20-9 . 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. table 20-9 dma request lines of asc0/asc1 module related asc interrupt dma request line description asc0 rir asc0_rdr dma channel 00 request input 5 dma channel 10 request input 5 dma channel 06 request input 5 dma channel 16 request input 5 tir asc0_tdr dma channel 02 request input 5 dma channel 12 request input 5 dma channel 04 request input 5 dma channel 14 request input 5 tbir asc0_tbdr dma channel 02 request input 12 dma channel 12 request input 12 dma channel 04 request input 12 dma channel 14 request input 12 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-41 v1.1, 2011-03 asc, v1.5 note: further details on dma handling and processing are described in the chapter ?dma controller? of the TC1798 system units users manual. asc1 rir asc1_rdr dma channel 01 request input 5 dma channel 11 request input 5 dma channel 07 request input 5 dma channel 17 request input 5 tir asc1_tdr dma channel 03 request input 5 dma channel 13 request input 5 dma channel 05 request input 5 dma channel 15 request input 5 tbir asc1_tbdr dma channel 03 request input 12 dma channel 13 request input 12 dma channel 05 request input 12 dma channel 15 request input 12 table 20-9 dma request lines of asc0/asc1 (cont?d) module related asc interrupt dma request line description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-42 v1.1, 2011-03 asc, v1.5 20.3.4 address map an absolute register address is given by th e offset address of the register (given in table 20-7 ) plus the module base address (given in table 20-6 ). table 20-10 address map of asc0/asc1 short name description address access mode reset value read write async./sync. serial interface 0 (asc0) asc0_ clc asc0 clock control register f000 0a00 h u, sv sv, e 0000 0003 h asc0_ pisel asc0 peripheral input select register f000 0a04 h u, sv u, sv 0000 0000 h asc0_ id asc0 module identification register f000 0a08 h u, sv be 0000 44xx h ? reserved f000 0a0c h be be ? asc0_ con asc0 control register f000 0a10 h u, sv u, sv 0000 0000 h asc0_ bg asc0 baud rate/timer reload register f000 0a14 h u, sv u, sv 0000 0000 h asc0_ fdv asc0 fractional divider register f000 0a18 h u, sv u, sv 0000 0000 h ? reserved f000 0a1c h be be ? asc0_ tbuf asc0 transmit buffer register f000 0a20 h u, sv u, sv 0000 0000 h asc0_ rbuf asc0 receive buffer register f000 0a24 h u, sv u, sv 0000 0000 h ? reserved f000 0a28 h - f000 0a4c h be be ? asc0_ whbcon asc0 write hardware bits control register f000 0a50 h u, sv u, sv 0000 0000 h ? reserved f000 0a54 h - f000 0aec h be be ? asc0_ tsrc asc0 transmit interrupt service req. control reg. f000 0af0 h u, sv u, sv 0000 0000 h asc0_ rsrc asc0 receive interrupt service req. control reg. f000 0af4 h u, sv u, sv 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-43 v1.1, 2011-03 asc, v1.5 asc0_ esrc asc0 error interrupt service req. control reg. f000 0af8 h u, sv u, sv 0000 0000 h asc0_ tbsrc asc0 transmit buffer interrupt service req. control reg. f000 0afc h u, sv u, sv 0000 0000 h async./sync. serial interface 1 (asc1) ? reserved f000 0b00 h be be ? asc1_ pisel asc1 peripheral input select register f000 0b04 h u, sv u, sv 0000 0000 h asc1_ id asc1 module identification register f000 0b08 h u, sv be 0000 44xx h ? reserved f000 0b0c h be be ? asc1_ con asc1 control register f000 0b10 h u, sv u, sv 0000 0000 h asc1_ bg asc1 baud rate/timer reload register f000 0b14 h u, sv u, sv 0000 0000 h asc1_ fdv asc1 fractional divider register f000 0b18 h u, sv u, sv 0000 0000 h ? reserved f000 0b1c h be be ? asc1_ tbuf asc1 transmit buffer register f000 0b20 h u, sv u, sv 0000 0000 h asc1_ rbuf asc1 receive buffer register f000 0b24 h u, sv u, sv 0000 0000 h ? reserved f000 0b28 h - f000 0b4c h be be ? asc1_ whbcon asc1 write hardware bits control register f000 0b50 h u, sv u, sv 0000 0000 h ? reserved f000 0b54 h - f000 0bec h be be ? asc1_ tsrc asc1 transmit interrupt service req. control reg. f000 0bf0 h u, sv u, sv 0000 0000 h asc1_ rsrc asc1 receive interrupt service req. control reg. f000 0bf4 h u, sv u, sv 0000 0000 h table 20-10 address map of asc0/asc1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 asynchronous/synchronous serial interface (asc) users manual 20-44 v1.1, 2011-03 asc, v1.5 20.3.5 application hint regarding the atm feature if the asc0 is operated under certain conditions, the communication can be affected by the atm functionality overlaid to the rxd0b pin. the conditions are: ? asc communication is using the pin where can rxdcan0 is mapped to as well ? asc protocol uses only one stop bit ? start bit follows immediately after stop bit of previous data byte ? block transfer with more than 100 bytes ? data is 0xaa for all bytes ? asc baud rate is higher than xtal1 frequency / 14 (for example, 1.42 mbaud for a 20 mhz crystal) there are two options to prevent the effect: ? add a wait cycle between start and stop bit after 100 or less transferred bytes. ? disable (temporarily) the atm feature from within the scu module ? use 0x55, 0xaa55 or 0x55aa instead of 0xaa as fill or test data pattern asc1_ esrc asc1 error interrupt service req. control reg. f000 0bf8 h u, sv u, sv 0000 0000 h asc1_ tbsrc asc1 transmit buffer interrupt service req. control reg. f000 0bfc h u, sv u, sv 0000 0000 h table 20-10 address map of asc0/asc1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-1 v1.1, 2011-03 ssc, v1.5 21 synchronous serial interface (ssc) this chapter describes the four ssc synchr onous serial interfaces ssc0, ssc1, ssc2 and ssc3 of the TC1798. it contains the following sections: ? functional description of the ssc kernel, valid for ssc0, ssc1, ssc2 and ssc3 (see page 21-1 ). ? ssc kernel register description, descr ibes all ssc kernel specific registers (see page 21-27 ). ? TC1798 implementation-specific details and registers of the ssc0/ssc1/ssc2 modules (port connections and control, in terrupt control, address decoding, clock control, see page 21-43 ). note: the ssc kernel register names described in section 21.2 are referenced in the TC1798 users manual by the module name prefix ?ssc0_? for the ssc0 interface, by ?ssc1_? for the ssc1 in terface, and by ?ssc2_? for the ssc2 interface. 21.1 ssc kernel description figure 21-1 shows a global view of the ssc interface. figure 21-1 general block diagram of the ssc interface mcb06058_mod clock control address decoder interrupt control f ssc ssc module (kernel) mrstb mtsr master rir tir eir slsi[7:1] slsi[7:1] slso[7:0] slso[7:0] mrst mtsr sclk mrsta mtsrb mrst mtsra sclkb sclk sclka slave slave master slave master port control f clc enable m/s select dma requests slsoando[7:0] slsoando[7:0] slsoandi[7:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-2 v1.1, 2011-03 ssc, v1.5 21.1.1 overview the ssc supports full-duplex and half-duplex serial synchronous communication up to 55.0 mbit/s (@ 110.0 mhz module clock, mast er mode). the serial clock signal can be generated by the ssc itself (master mode) or can be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data is double-buffered. a shift clock generator provides the ssc with a separate serial clock signal. seven slave select inputs ar e available for slave mode operation. eight programmable slave select outputs (chip selects) are supported in master mode. features: ? master and slave mode operation ? full-duplex or half-duplex operation ? automatic pad control possible ? flexible data format ? programmable number of data bits: 2 to 16 data bits (with parity: 1 to 15 data bits) ? programmable shift direction: lsb or msb shift first ? programmable clock polarity: idle low or idle high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock ? baud rate generation ? master mode: 33.25 mbit/s to 507.4 bit/s (@ 66.5 mhz module clock) ? master mode: 55.0 mbit/s to 839.3 bit/s (@ 110 mhz module clock) ? slave mode: 16.625 mbit/s to 507.4 bit/s (@ 66.5 mhz module clock) ? slave mode: 27.5 mbit/s to 839.3 bit/s (@ 110 mhz module clock) ? interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baud rate, transmit error, parity error) ? queued ssc mode supports control and data handling by the dma controller ? flexible ssc pin configuration ? hardware supported parity mode ? individually selectable for transmit and receive frames ? even/odd parity selection ? seven slave select inputs slsi[7:1] in slave mode ? eight programmable slave select outputs slso[7:0] in master mode ? automatic slso generation with programmable timing ? programmable active level and enable control ? combinable with slso output signals from other ssc modules www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-3 v1.1, 2011-03 ssc, v1.5 21.1.2 general operation the ssc supports full-duplex and half-duplex synchronous communication up to 55.0 mbit/s (@ 110.0 mhz module clock). the serial clock signal can be generated by the ssc itself (master mode) or be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data are double-buffered. a shift clock generator prov ides the ssc with a separate serial clock signal. configuration of the high-speed synchronous serial interface is very flexible, so it can work with other synchronous serial interfaces, can serve master/slave or multi-master interconnections, or can operate compatibly with the popular spi interface. it can be used to communicate with sh ift registers (i/o expansio n), peripherals (e.g. eeproms etc.), or other controllers (networking). t he ssc supports half-duplex and full-duplex communication. data is transmitted or rece ived on pins mtsr (master transmit/slave receive) and mrst (master receive/slave trans mit). the clock signal is output or input via pin sclk (serial clock). these three pins are typically used for alternate output functions of port pins. if they are implemente d as dedicated bi-directional pins, they can be directly controlled by the ssc. in slave mode, the ssc can be selected from a master via dedicated slave select input lines (slsi) . in master mode, automatic generation of slave select output lines (slso) is supported. in master mode, control and data handling of transfers can be also be controlled independently by the dma controller (queued ssc mode). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-4 v1.1, 2011-03 ssc, v1.5 figure 21-2 synchronous serial channel ssc block diagram 16- bit shift register pin control logic ssc control block (registers con/stat/efm) clock control baud rate generator mcb06214a_mod error int . request internal bus status control receive int . request transmit int . request tir rir eir shift clock f ssc slso[7:0] 1) mtsrb mrst mtsra mrstb 1) mtsr 1) mrsta 1) sclkb sclk 1) sclka 1) these signals are used in master mode only f clc slsi[7:1] ssc enabled m/s selected 7 receive buffer register rb transmit buffer register tb slave select output generation unit slsoando[7:0] 1) slsoandi[7:0] 1) parity checker parity generator www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-5 v1.1, 2011-03 ssc, v1.5 21.1.2.1 operating mode selection the operating mode of the serial channel ssc is controlled by its control register, con. status information is contained in its status register, stat. the shift register of the ssc is connected to both the transmit pin and the receive pin via the pin control logic (see block diagram in figure 21-2 ). transmission and reception of serial data are synchronized and take place at the same time, that is, the same number of transmitted bits is also received. transmit data is written into the transmit buffer tb. it is moved to the shift register as soon as this is empty, including the generated parity bit for the transmit data if transmit parity mode is enabled (con.parten = 1). an ssc master (con.ms = 1) immediately begins transmitting, while an ssc slave (con.ms = 0) will wait for an active shift cl ock. when the transfer starts, the busy flag stat.bsy is set, and the transmit interrupt request line (tir) will be activated to indicate that the transmit buffer register (tb) may be reloaded. when the number of bits as programmed in con.bm have been received, the data bits of the shift register are moved to the receive buffer register (rb) right-aligned, the receive parity bit (if enabled by con.parren = 1) is loaded into stat.parrval, and the receive interrupt request line (rir) will be activated. if no further tran sfer is to take place (tb is empty), stat.bsy will be cleared at the same time. software should not modi fy stat.bsy, as this flag is hardware-controlled. note: only one ssc can be master at a given time. the following features of the serial data bit transfer can be programmed: ? the data width can be selected from 2 to 16 data bits (with parity: 1 to 15 data bits) ? a transfer may start with the lsb or the msb of the data bits ? the shift clock may be idle low or idle high ? the data bits may be shifted with the leading or trailing edge of the clock signal ? the baud rate (shift clock) can be set from 839.3 bit/s up to 55.0mbit/s (@ 110 mhz module clock) ? the shift clock can be generated (master) or received (slave) these features allow the ssc to be adapted to a wide range of applications that require serial data transfer. the data width selection supports the transfer of frames of any data length from 2-bit ?characters? up to 16-bit ?characters?. if pari ty is enabled, the maximum number of data bits of a frame is 15-bit. starting the serial data bit transfer with the lsb (con.hb = 0) allows communication with devices such as an ssc device in synchr onous mode, or 8051-like serial interfaces. if parity mode is enabled, the parity bit preceeds the serial data bit transfer (see page 21-12 ). starting with the msb (con.hb = 1) allows operation compatible with the spi interface. if parity mode is enabled, the parity bit follows the serial data bit transfer (see page 21-12 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-6 v1.1, 2011-03 ssc, v1.5 regardless of the selected data width and whether the msb or the lsb is transmitted first, the transfer data is always right-aligned in registers tb and rb, with the lsb of the transfer data in bit 0 of these registers. th e data bits are rearranged for transfer by the internal shift register logic. the unselected bits of tb are ignored, and the unselected bits of rb will not be valid and should be ignored by the receiver service routine. the clock control allows the adaptation of transmit and receive behavior of the ssc to a variety of serial interfaces. a specific clo ck edge (rising or falling) is used to shift out transmit data, while the other clock edge is used to latch in receive data. bit con.ph selects the leading edge or the trailing edge for each function. bit con.po selects the level of the clock line in the idle state. for an idle-high clock, the leading edge is a falling one, a 1-to-0 transition (see figure 21-3 ). figure 21-3 serial clock sclk phase and polarity options 21.1.2.2 full-duplex operation the description in this section assumes that the ssc is used with software controlled bi- directional gpio port lines that have open-drain capability (see also section 21.1.2.6 ). the various devices are connected through th ree lines. the definition of these lines is always determined by the master. the line c onnected to the master?s data output pin mtsr is the transmit line, the receive line is connected to its data input line mrst, and the clock line is connected to pin sclk. only the device selected for master operation generates and outputs the serial clock on pin sclk. all slaves receive this clock, so their mct06215_mod shift clock sclk if: transmit data first bit 1) shift data latch data last bit ssc pins mtsr / mrst con.po = 0 con.ph = 0 con.po = 0 con.ph = 1 1) con.po = 1 con.ph = 0 con.po = 1 con.ph = 1 1) 1.) first bit on mrst is replaced by pisel.stip in slave mode if con.ph=1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-7 v1.1, 2011-03 ssc, v1.5 pin sclk must be switched to input mode. the output of the master?s shift register is connected to the external transmit line, which in turn is connected to the slaves? shift register input. the output of the slaves? shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave. the external connections are hard-wired, with the function and direction of these pins determined by the master or slave operation of the individual device. note: the shift direction shown in figure 21-4 applies to both msb-first and lsb-first operation. when initializing the devices in this configuration, one device must be selected for master operation while all other devices must be programmed for slave operation. initialization includes the operating mode of the device?s ssc and also the function of the respective port lines. figure 21-4 ssc full-duplex configuration the data output pins mrst of all slave devices are connected onto one receive line in this configuration. during a transfer, each sl ave shifts out data from its shift register. there are two ways to avoid collisions on the receive line due to different slave data: mtsr mrst clk clock mtsr mrst clk clock mca06216 shift register device #2 slave mtsr mrst clk clock shift register device #1 master shift register device #3 slav e clock receive transmit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-8 v1.1, 2011-03 ssc, v1.5 ? only one slave drives the line and enables the driver of its mrst pin. all the other slaves must program their mrst pins to in put. therefore, only one slave can put its data onto the master?s receive line. only reception of data from the master is possible. the master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. the selected slave then switches its mrst line to output until it gets a de-selection signal or command. ? the slaves use open drain output on mrst. this forms a wired-and connection. the receive line needs an external pull-up in this case. corruption of the data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master send only 1s. sinc e this high level is not actively driven onto the line, but is only held through the pull-up device, the selected slave can pull this line actively to a low level when transmitting a zero bit. the master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. after performing all necessary initializations of the ssc, the serial interfaces can be enabled. for a master device, the alternat e clock line will now go to its programmed polarity. the altern ate data line will go to eith er 0 or 1, until the fi rst transfer starts. after a transfer, the alternate data line will always remain at the logic level of the last transmitted data bit. when the serial interfaces are enabled, the master device can initiate the first data transfer by writing the transmit data into register tb. this value is copied into the shift register (assumed to be empty at this time), and the selected first bit of the transmit data will be placed onto the mtsr line on the next clock from the shift clock generator (transmission only starts, if con.en = 1). depending on the selected clock phase, a clock pulse is generated on the sclk line. with the opposite clock edge, the master simultaneously latches and shifts in the data detected at its input line mrst. this ?exchanges? the transmit data with the receive data. because the clock line is connected to all slaves, their shift registers will be shifted synchronously with the master?s shift register, shifting out the data contained in the registers, and shifting in the data detected at the input line. after the pre-programmed nu mber of clock pulses (via the data width selection), the data transmitted by the master is contained in all slaves? shift registers, while the master?s shift register holds the data of the selected slave. in the master and all slaves, the content of the shift register is copied into the receive buffer (rb) and the receive interrupt line (rir) is activated. a slave device will immediately output the selected first bit (m sb or lsb of the transfer data) at pin mrst when the contents of the transmit buffer are copied into the slave?s shift register. bit stat.bsy is not set until the first clock edge at sclk appears. the slave device will not wait for the next clock from the shift clock generator ? as the master does ? because the first clock edge generated by the master may be already used to clock in the first data bit, depending on the selected clock phase. so the slave?s first data bit must already be valid at this time. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-9 v1.1, 2011-03 ssc, v1.5 note: on the ssc, a transmission and a reception always take place at the same time, regardless whether valid data has been transmitted or received. 21.1.2.3 half-duplex operation the description in this section assumes that the ssc is used with software controlled bi- directional gpio port lines that provide open-drain capability (see also section 21.1.2.6 ). in a half-duplex configuration, only one data line is necessary for both receiving and transmitting data. the data exchange line is connected to both pins mtsr and mrst of each device, and the clock line is connected to the sclk pin. the master device controls the data transfer by generating the shift clock, while the slave devices receive it. due to the fact that all transmit and receive pins are connected to the one data exchange line, serial data may be moved between arbitrary stations. as in full-duplex mode, there are two ways to avoid collisions on the data exchange line: ? only the transmitting device may enable its transmit pin driver ? the non-transmitting devices use open-drain output and send only 1s because the data inputs and outputs are conn ected together, a transmitting device will clock in its own data at the input pin (mrst for a master device, mtsr for a slave). in this way, any corruption is detected on the common data exchange line when the received data is not equal to the transmitted data. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-10 v1.1, 2011-03 ssc, v1.5 figure 21-5 ssc half-duplex configuration 21.1.2.4 continuous transfers when the transmit interrupt request flag is set, it indicates that the transmit buffer (tb) is empty and is ready to be loaded with the next transmit data. if the tb has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the nex t transmission can start without any additional delay (according to the selected slso timings). on the data line, there is no gap between the two successive frames if no delays are selected. for example, two byte transfers would look the same as one word transfer. this feature can be used to interface with devices that can operate with (or require more than) 16 data bits per transfer. it is just a matter for software how long a total data frame length can be. this option can also be used, e.g., to interface to byte-wide and word-wide devices on the same serial bus. note: this option can only happen in multiples of the selected basic data width, because it would require disabling/enabling of th e ssc to reprogram the basic data width on-the-fly. mtsr mrst clk clock mtsr mrst clk clock mtsr mrst clk clock mca0621 7 shift register device #2 slave shift register device #1 master shift register device #3 slav e common transmit/ receive line clock www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-11 v1.1, 2011-03 ssc, v1.5 note: in master mode, the transm it buffer register tb is lo aded with new data for the following transmission just at the end of the current transmission and a leading delay > 0 is selected (ssotc.lead not equal 00 b ), a slightly enlarged leading delay (< one sclk shift clock period) is generated for the following transmission. 21.1.2.5 parity mode the ssc allows to add a parity bit to a serial frame. the parity mode can be enabled individually for frame transmission (con.parten) and frame reception (con.parren). the type of parity (even/odd parity) can be selected, valid for transmit and receive parity. if transmit parity is enabled (con.parten = 1), the shift register is loaded for a frame transmission by the content of the transmit buffer tb, the parity bit becomes calculated and stored in stat.partval. depending on bit con.hb, the parity bit preceeds or follows the transmitted data bits. if receive parity is enabled (con.parren = 1) and the last bit of a frame has been received, the received data of the frame is stored in rb and the received parity bit is stored in stat.parrval. the received and calculated parity bits are now compared. if this comparison fails, a parity error is detected and the error status flag stat.pare is set. if enabled by bit con.pareen, a parity error activates the error interrupt request line eir. figure 21-6 shows how a parity bit is added to the transmitted data bits of a frame. the number of the transmitted bits of a complete frame remains constant without or with parity, assuming that com.bm is not cha nged. therefore, the number of transmitted data bits is reduced by one bit when parity mode is enabled. if the heading control bit con.hb = 0 (lsb first), the parity bit preceeds the data bits in parity mode and is transmitted as the first bit of a frame. if the heading control bit con.hb = 1 (msb first), the parity bit follows the data bits in parity mode and is transmitted as the last bit of a frame. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-12 v1.1, 2011-03 ssc, v1.5 figure 21-6 data frames without/with parity 21.1.2.6 port control the ssc uses three lines to communicate with the external world. pin sclk serves as the clock line, while pins mrst (master receive/slave transmit) and mtsr (master transmit/slave receive) serve as the serial data input/output lines. as shown in figure 21-1 these three lines (sclk as input, master receive, slave receive) have two inputs each at the ssc module kernel. three bits in register pisel determine which of the two kernel inputs (a or b) are connecte d. this feature allows for each of the three ssc communication lines to be connected to two inputs coming from different port pins. operation of the ssc i/o lines depends on the selected operating mode (master or slave). the direction of the port lines depends on the operating mode. the ssc will automatically use the correct kernel output or kernel input line of the ports when parity bit bit bm bit 3 bit 1 ssc_parity1_mod bit 0 parity mode disabled data frame with lsb first (con.hb = 0) (bm+1) bi ts bit 2 bit bm-1 bit bm-1 bit 2 bit 0 parity mode enabled (bm+1) bi ts bit 1 bit bm-2 bit 0 bit 3 bit bm-1 bit bm parity mode disabled data frame with msb first (con.hb = 1) (bm+1) bi ts bit 2 bit 1 parity bit bit 2 bit bm-2 bit bm-1 parity mode enabled (bm+1) bi ts bit 1 bit 0 ti me ti me the bit numbers x (x = 0,1,2, ?. ,bm-1,bm) refer to register bit tb.x in transmit case and to register bit rb.x in receive case . bm is the value of bit field con .bm. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-13 v1.1, 2011-03 ssc, v1.5 switching modes. port pins assigned as ssc i/o lines can be controlled either by hardware or by software. when the ssc i/o lines are connected to dedicated pins, hardware i/o control should typically be used. in this case, two output signals reflect the state of the con.en and con.ms bits directly (the m/s select line is inverted to the con.ms bit definition). when the ssc i/o lines are connected with bi-directional lines of general purpose i/o ports, software i/o control shou ld be typically used. in this case port registers must be programmed for alternate output and input selection. when switching between master and slave mode port registers must be reprogrammed. using the open-drain output feature of port lin es helps to avoid bus contention problems and reduces the need for hard-wired hand-shak ing or slave select lines. in open-drain output mode, it is not always necessary to switch the direction of a port pin. note that in hardware-controlled i/o mode, the availability of open-drain outputs depends on the type of the dedicated output pins that are used. the ssc module itself does not provide any control capability for open-drain control. note: for details of ssc port connections and configuration, see page 21-53 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-14 v1.1, 2011-03 ssc, v1.5 21.1.2.7 baud rate generation the serial channel ssc has its own dedicated 16-bit baud rate generator with 16-bit reload capability, allowing baud rate generation independent of timers. in addition to figure 21-2 , figure 21-7 shows the baud rate generator of the ssc in more detail. figure 21-7 ssc baud rate generator the baud rate generator is clocked with f ssc . the timer counts downwards. register br is the dual-function baud rate generator/reload register. reading br while the ssc is enabled returns the contents of the timer. reading br while the ssc is disabled returns the programmed reload value. in this mode, the desired reload value can be written to br. note: never write to br while the ssc is enabled. the formulas below calculate either the resulting baud rate for a given reload value, or the required reload value for a given baud rate: (21.1) br_value represents the content of the reload register, taken as an unsigned 16-bit integer, while baud rate ssc is equal to f sclk as shown in figure 21-7 . the maximum baud rate that can be achieved with f ssc = 110 mhz is 55.0 mbit/s in master mode (with br_value = 0000 h ) and 275.0 mbit/s in slave mode (with br_value = 0001 h ). table 21-1 lists some possible baud rates together with the required reload values and the resulting bit times, assuming a module clock f ssc of 110 mhz. mca06218 16-bit counter 16-bit reload register f sclk f ssc / 2 f sclk max in master mode f ssc / 4 f sclk max in slave mode f ssc 2 baud rate ssc f ssc 2 br_value 1 + () ------------------------------------------------------- = br_value f ssc 2 baud rate ssc -------------------------------------------- 1 ? = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-15 v1.1, 2011-03 ssc, v1.5 in the TC1798, the module clock f ssc is generated outside the ssc module kernel. therefore, for baud rate calculations the dependencies of f ssc from f fpi must be taken into account. on describes these dependencies in detail. table 21-1 typical asynchronous baud rates using fixed input clock dividers reload value baud rate (= f sclk ) deviation 0000 h 55 mbit/s (only in master mode) 0.0% 0001 h 27.5 mbit/s 0.0% 0003 h 13.75 mbit/s 0.0% 0036 h 1 mbit/s 0.0% 006d h 500 kbit/s 0.0% 0225 h 100 kbit/s 0.0% 157b h 10 kbit/s 0.0% d6d7 h 1 kbit/s 0.0% ffff h 839.3 bit/s 0.0% www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-16 v1.1, 2011-03 ssc, v1.5 21.1.2.8 slave select input operation for systems with multiple slaves, the ssc module provides seven slsi slave select input lines, that permit enabling or disabling of the sclk, mtsr, and mrst signals in slave mode. slave mode is selected by con.ms = 0. the slsi input logic shown in figure 21-8 is controlled by register pisel and con. note: in the following description, only one of the seven slsi input lines is mentioned. the remaining six slsi input lines are connected to the other six inputs of the input multiplexer, which is co ntrolled by pisel.slsis. figure 21-8 slave select input logic with pisel.slsis = 000 b and slave mode selected, the slsi input line does not control the ssc i/o lines. the slave receive inpu t signal mtsra or mtsrb (selected by pisel.sris) and the slave clock input signal sclka or sclkb (selected by pisel.scis) are passed further as mtrsi and sclki to the internal ssc control logic. the slave transmit signal mrsti from the internal ssc control logic mrsti is passed directly to mrst. with pisel.slsis = 001 b , input signal slsi controls the operation of the ssc i/o lines as a slave select signal as follows: ?slsi = 1: ssc slave is not selected. ? the slave receive input signals, mtsr a or mtsrb are connected to mtsri, depending on pisel.sris (slave mode receive input select). mca06219 slsi pisel.stip con.po 0 1 ssc kernel slave mode to/from internal control 0 mrst pisel.slsis port contro l sclki mtsri mrsti 000 001 pisel.sris mtsra mtsrb sclka sclkb pisel.scis 0 1 0 1 0 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-17 v1.1, 2011-03 ssc, v1.5 ? mrst is driven with the logic level of bit pisel.stip (slave transmit idle state). ? sclki is driven with the logic leve l of con.po (clock polarity control). ?slsi = 0: ssc is selected as slave. ? the slave receive input signals mtsr a or mtsrb are connected to mtsri, depending on pisel.sris (slave mode receive input select). ? mrst is directly driven with the slave transmit output signal mrsti. ? the slave clock input signals sclka or sclkb are connected to sclki, depending on pisel.scis (slave mode clock input select). 21.1.2.9 slave select output generation unit in master mode, the slave select output generation unit of the ssc automatically generates up to eight slave select output lines slso[7:0] for serial transmit operations. the slave select output generation unit further makes it possible to adjust the chip select timing parameters. the active/inactive state of a slave select output as well as the enable/disable state can be controlled individually for each slave select output (see figure 21-10 ). the basic slave select ou tput timing is shown in figure 21-9 , assuming a low active level of the slson lines. figure 21-9 ssc slave select output timing a slave select output period always starts after a write operation to register tb. with a tb write operation, all timing parameters stored in register ssotc (lead, trail, first bit t slsol invalid invalid mct06220_mod slson t slsol t slsoi t slsot mtsr t slsoact last bit slave select output period t sclk data frame note: this timing example is based on the following setup: con.ph = 0; con.po = 1 mrst sclk first bit last bit sample points first bit first bit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-18 v1.1, 2011-03 ssc, v1.5 inact, and slso7mod) and register ssoc (aoln and oenn) are latched and remain valid for the consecutive transmission. following that, slson becomes active (low) for a number of sclk cycles (leading delay cycl es) before the first bit of the serial data stream occurs at mtsr. after the transmission of the data frame, slson remains active (low) for a number of sclk cycles (traili ng delay cycles) before it becomes inactive again. this inactive state of slson is valid at least for a number of sclk cycles (inactive delay cycles) before a new chip select period can be started. note: when operating in master mode with con.ph = 1 and sampling data from a slave device that becomes enabled by an slson output, a leading delay of at least one leading delay clock cycle should be select ed. the reason is that with con.ph = 1, the first sclk edge already latches the first data bit at mrst. the three parameters of a chip select period are controlled by bit fields in the slave select output timing control register ssotc. each of these bit fields can contain a value from 0 to 3 defining delay cycles of 0 to 3 multiples of the t sclk shift clock period. the three parameters are: 1. number of leading delay cycles ( t slsol = ssotc.lead t sclk ) 2. number of trailing delay cycles ( t slsot = ssotc.trail t sclk ) 3. number of inactive delay cycles ( t slsoi = ssotc.inact t sclk ) if ssotc.inact = 00 b and register tb has already been loaded with the data for the next data frame, the next chip select period is started with its leading delay phase without slson going inactive. if, in this case, tb has not been loaded in time with the data for the next data frame, slson becomes inactive again. slave select output control each slave select output slson can be enabled individually. when ssoc.oenn = 1, slson is enabled. furthermore, active and inactive levels of the slson outputs are programmable. bit ssoc.aoln determines the state of the active level of slson. figure 21-10 slave select output control logic mca06221_mod ssoc.aoln 0 ssoc.oenn slson slave select output timing control 0: inactive 1: active 1 0 1 0 & slsoandon slsoandin n = 0-7 slave select output generation unit ssotc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-19 v1.1, 2011-03 ssc, v1.5 as a special feature, each slson output signal can be combined (anded) by an external signal slsoandin coming from another ssc to an output signal slsandon. this and gate can be used for example to combine two slave select output signals from two sscs to one common slson output signal. note that this functionality only works for low active slson signals (ssoc.aoln = 0). slave select output 7 delayed mode in the slso7 delayed mode (ssotc.slso7mod = 1), the timing of the slave select output slso7 as programmed by the three parameters in ssotc (number of trailing, leading, and inactive delay clock cycles) is delayed by one shift clock period for the inactive-to-active edge. the active-to-inactive edge is not delayed. the timing of slso7 in the delayed mode is shown in figure 21-11 . the bold lines show the timing of slso7 in normal operating mode, and the dotted lines show the timing of slso7 in delayed mode. figure 21-11 slso7 delayed mode slave select register update at the start of an internal transmit sequenc e (with the tb register write operation), the parameters in registers ssoc and ssotc are latched. this means that they remain stable while a serial transmission is in prog ress. therefore, it is always guaranteed that the data of one serial transmission is always transmitted with a constant slave select configuration setup. a configuration change by reprogramming ssoc or ssotc during a serial transmission will first become vali d with the start of the subsequent serial transmission. mct06222 s clk s lso7 with l ead = 11 b data frame s lso7 with l ead = 10 b s lso7 with l ead = 01 b s lso7 with l ead = 00 b t slsoact n ote: the timing is valid for clock polarity control bit con.po = 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-20 v1.1, 2011-03 ssc, v1.5 21.1.2.10 error detection mechanisms the ssc is able to detect four different error conditions. receive error and phase error are detected in all modes, while transmit error and baud rate error apply to slave mode only. in case of a transmit error or receiv e error, the respective error flags are always set and the error interrupt reques ts will be generated by activa ting the eir lin e only if the corresponding error enable bits have been set (see figure 21-12 ). the error interrupt handler may then check the error flags to determine the cause of the error interrupt. the error flags are not cleared automatically, bu t must be cleared via register efm after servicing. this allows servicing of some e rror conditions via interrupt, while others may be polled by software. the error status flags can be set and cleared by software via the error flag modification register efm. note: the error interrupt hand ler must clear the associated (enabled) error flag(s) to prevent repeated interrupt requests. the setting of an error flag by software does not generate an interrupt request. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-21 v1.1, 2011-03 ssc, v1.5 figure 21-12 ssc erro r interrupt control a receive error (master or slave mode) is detected when a new data frame is completely received, but the previous data was not read out of the receive buffer register rb. if enabled via con.ren, this condition sets the error flag stat.re and activates the error interrupt request line eir. this condition sets the error flag stat.re and, if enabled via con.ren, sets the error interrupt request line eir. the old data in the receive buffer rb will be overwritten with the new value and is irretrievably lost. a phase error (master or slave mode) is detected when the incoming data at pin mrst (master mode) or mtsr (slave mode), sampled with the same frequency as the module mca05789a_mod_ist error interrupt eir 1 efm.sette efm.clrte efm.setre efm.clrre efm.setpe efm.clrpe efm.setbe efm.clrbe con.ten & stat.te set clear transmit error receive error phase error baud rate error set con.ren & stat.re set clear con.pen & stat.pe set clear set con.ben & stat.be set clear set set efm.setpare efm.clrpare parity error con. pareen & stat.pare set clear set www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-22 v1.1, 2011-03 ssc, v1.5 clock, changes betwe en one cycle before and two cycles after the latching edge of the shift clock signal sclk. this condition sets the error status flag stat.pe and, if enabled via con.pen, the error interrupt request line eir. note: when con.ph = 1, the data output signa l may be disturbed shortly when the slave select input signal is changed after a serial transmission, resulting in a phase error. a baud rate error (slave mode) is detected when the incoming clock signal deviates from the programmed baud rate (shift clock) by more than 100%, meaning it is either more than double or less than half the expected baud rate. this condition sets the error status flag stat.be and, if enabled via con.ben, the eir line. using this error detection capability requires that the slave? s shift clock generator is programmed to the same baud rate as the master device. this feature detects false additional pulses or missing pulses on the clock line (within a certain frame). note: if this error condition occurs and bi t con.aren = 1, an auto matic reset of the ssc will be performed. this is done to re-initialize the ssc, if too few or too many clock pulses have been detected. note: the baud rate error can occur in slave mode after any transfer if the communication is stopped by the master. th is is the case due to the fact that ssc module supports back-to-back transfers for multiple transfers. in order to handle this the baud rate detection logic expects after a finished transfer immediately a next clock cycle for a new transfer. if baud rate error is enabled and the transmit buffer of the slave ssc is loaded with a new value for the next data frame while the current data frame is not yet finished (while stat.bsy = 1), the slave ssc expects continuation of the clock pulses for the next data frame transmission immediately after finishing the current data frame. any write to tbuf of the slave ssc while stat.bsy = 1 initiates or sustains a continuous transmission in the slave. therefore, the master (shift) clock must be continued after the current frame transmission. otherwise, the slave ssc will detect a baud rate error. note that the master ssc does not necessarily send out a continuous shift clock in the case that its transmit buffer is not yet filled with new data or transmission delays occur. further details on continuous transfers are described in section 21.1.2.4 on page 21-10 . a transmit error (slave mode) is detected when a transfer was initiated by the master (shift clock gets active), but the transmit buff er (tb) of the slave was not updated since the last transfer. if enabled via con.ten, this condition sets the error status flag stat.te and activates the eir line. this c ondition sets the error status flag stat.te and, if enabled via con.ten, the eir line. if a transfer starts while the transmit buffer is not updated, the slave will shift out the ?old? contents of the shift register, which is normally the data received during the last transfer. this may lead to the corruption of the data on the transmit/receive line in half-duplex mode (open drain configuration) if this slave is not selected for transmission. this mode requires that slaves not selected for www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-23 v1.1, 2011-03 ssc, v1.5 transmission only shift out ones; thus, their transmit buffers must be loaded with ffff h prior to any transfer. a parity error (master or slave mode) is detected when the data frame is completely received and the generated parity bit for the received data is not equal to the calculated parity bit. this condition sets the error status flag stat.pare and, if enabled via con.pareen, the error interrupt request line eir. note: a slave with push/pull ou tput drivers not selected fo r transmission will normally have its output drivers swit ched off. however, to avoid possible conflicts or misinterpretations, it is recommended to always load the slave's transmit buffer prior to any transfer. the cause of an error interrupt request (receive, phase, baud rate, transmit error) can be identified by the error status flags in control register con. note: in contrast to the eir line, the erro r status flags stat.t e, stat.re, stat.pe, and stat.be, are not automatically cleared upon entry into the error interrupt service routine, but must be cleared by software. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-24 v1.1, 2011-03 ssc, v1.5 21.1.2.11 queued ssc mode in queued ssc mode, the enable/disable control of the ssc is possible by two bit locations, one control bit in register con and one additional control bit in register ssotc. this double-enable control capability allows control and data operations of the ssc to be completely handled by a dma controller. the bits for queued ssc mode are: ? bit ssctc.qsmen: queued ssc mode enable ? bit ssctc.en: enable ssc (functio nality identical with bit con.en) note: both register bits, con.en and ssotc .en, control one common flip-flop for enable/disable control. figure 21-13 shows how the queued ssc mode control logic. reading ssotc returns the state of con.en for ssotc.en. writing to ssotc with qsmen = 1, sets con.en if ssotc.en is written with 1 and clears con.en if ssotc.en is written with 0. compared to the timing parameters stored in register ssotc (lead, trail, inact, and slso7mod), the queued ssc mode control bits qsmen and en are a not latched and directly control the receive/transmit functionality. but note that con.en should only be cleared by software (either by a con or ssotc write operation) while no transfer is in progress (stat.bsy = 0). table 21-2 queued ssc mode control write ssotc register ssc module enable/disable control bit qsmen bit en 0 x enable/disable control of ssc is only possible via bit con.en (queued ssc mode disabled). 1 0 enable/disable control of ssc is possible via bits ssotc.en and con.en (queued ssc mode enabled). ssc is disabled 1 ssc is enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-25 v1.1, 2011-03 ssc, v1.5 figure 21-13 queued ssc mode control application for queued ssc mode example : the ssc operates in master mode and controls multiple ssc slave devices with different frame settings and baud rates. for controlling such an application task, that can be time critical when cpu is used for ssc control, the queued ssc mode is applicable. in this case, the control and data handling for an ssc slave is handled by three dma channels. ? dma channel 1 one dma transaction consists of four co nsecutive dma write transfers, programming registers con, br, ssoc, and ssotc. al l these registers are on consecutive addresses with an offset of 4. with the con write operation, con.en is set to 0 (ssc disabled). the br, ssoc, and ssotc write operations program the ssc slave parameters such as baud rate, frame layout, and slave select output timing. the fourth write operation to ssotc enables again the ssc by writing ssotc.qsmen = 1 and ssotc.en = 1. after dma channel 1 has finished this 4-byte control setup transaction it can be programmed to start automatically data transactions via dma channel 2 or 3 (depending on the application). ? dma channel 2 this dma channel is setup to write the transmit buffer register tb. ? dma channel 3 this dma channel is setup to read the receive buffer register rb. depending on the details of the application, the write or read dma channel may be unnecessary. ssc_qsm con.en enable /disable receiver / transmitter ssotc & en qsm en shadow latch slso 7mod lead trail inact www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-26 v1.1, 2011-03 ssc, v1.5 figure 21-14 ssc erro r interrupt control queuedsscmode dma channel 1 con dma channel 2 control tasks transmit data task en=0 br ssoc ssotc en=1 qsmen=1 10 h offset addr. 14 h 18 h 1c h tb 20 h dma channel 3 receive data task tb 24 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-27 v1.1, 2011-03 ssc, v1.5 21.2 ssc kernel registers this section describes the kernel registers of the ssc module. all ssc kernel register names described in this section will be referenced in other parts of the TC1798 users manual by the module name prefix ?ssc0_? for the ssc0 interface and ?ssc1_? for the ssc1 interface. all registers in the ssc address spaces are reset with the application reset (definition see scu section ?reset operation?). ssc kernel register overview figure 21-15 ssc kernel registers the complete and detailed address map of the ssc modules is described at the end of this chapter. table 21-3 registers address space - ssc kernel registers module base address end address note ssc0 f031 0000 h f031 00ff h ? ssc1 f031 0100 h f031 01ff h ? ssc2 f031 0200 h f031 02ff h ? ssc3 f031 0300 h f031 03ff h ? con br mca05790a_mod tb control registers data registers rb stat efm ssoc ssotc pisel identification register id www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-28 v1.1, 2011-03 ssc, v1.5 21.2.1 module identification register the ssc module identification register id contains read-only information about the module version. table 21-4 registers overview - ssc kernel registers register short name register long name offset address 1) 1) the absolute register address is calculated as follows: module base address ( table 21-3 ) + offset address (shown in this column) description see pisel port input select register 04 h page 21-29 id module identification register 08 h page 21-28 con control register 10 h page 21-31 br baud rate timer reload register 14 h page 21-41 stat status register 28 h page 21-34 efm error flag modification register 2c h page 21-36 ssoc slave select output control register 18 h page 21-38 ssotc slave select output timing control register 1c h page 21-39 tb transmit buffer register 20 h page 21-42 rb receive buffer register 24 h page 21-42 id module identificat ion register (08 h ) reset value: 0000 45xx h 31 16 15 8 7 0 0 modnum modrev rrr field bits type description modrev [7:0] r module revision number modrev defines the module revision number. the value of a module revision starts with 01 h (first revision). modnum [15:8] r module number value this bit field defines the module identification number for the ssc: 45 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-29 v1.1, 2011-03 ssc, v1.5 note: implementation specific de tails (e.g. rese t value) see ?module identification registers? on page 21-43 . 21.2.2 control registers the pisel register controls the input signal selection of the ssc module. each input of the module kernel receive, transmit and clock signals has associated two input lines (marked by suffix a and b). 0 [31:16] r reserved read as 0. pisel port input select register (04 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 stip 0 slsis scis sris mri s r rw r rw rw rw rw field bits type description mris 0rw master mode rece ive input select mris selects the receive i nput line in master mode. 0 b receive input line mrsta is selected 1 b receive input line mrstb is selected sris 1rw slave mode receive input select sris selects receive input line in slave mode. 0 b receive input line mtsra is selected 1 b receive input line mtsrb is selected scis 2rw slave mode clock input select scis selects the module kernel sclk input line that is used as clock input line in slave mode. 0 b slave mode clock input line sclka is selected 1 b slave mode clock input line sclkb is selected field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-30 v1.1, 2011-03 ssc, v1.5 slsis [5:3] rw slave mode slave select input selection 000 b slave select input lines are deselected; ssc is operating without slave select input functionality. 001 b slsi input line 1 is selected for operation. 010 b slsi input line 2 is selected for operation. 011 b slsi input line 3 is selected for operation. 100 b slsi input line 4 is selected for operation. 101 b slsi input line 5 is selected for operation. 110 b slsi input line 6 is selected for operation. 111 b slsi input line 7 is selected for operation. in the TC1798, other combinations of slsis except 000 b and 001 b are reserved and must not be used. stip 8rw slave transmit idle state polarity this bit determines the logic level of the slave mode transmit signal mrst when the ssc slave select input signals are inactive (pisel.slsis 000 b ). 0 b mrst = 0 when ssc is deselected in slave mode. 1 b mrst = 1 when ssc is deselected in slave mode. 0 [7:6], [31:9] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-31 v1.1, 2011-03 ssc, v1.5 the operating modes of the ssc are controlled by the control register con. this register contains control bits for mode and error check selection. note: whenever operating mode parameters in the con register are changed by software, no transfer should be in progress (stat.bsy = 0) and the ssc should be disabled (con.en = 0) and afterwards enabled again (con.en = 1). con control register (10 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 par een par typ par ren par ten r rwrwrwrw 1514131211109876543210 en ms 0 a ren ben pen ren ten lb po ph hb bm rwrw r rwrwrwrwrwrwrwrwrw rw field bits type description bm [3:0] rw frame width selection bm determines the number of bits of the serial frame. paren = 0, parity mode disabled : 0000 b reserved; do not use this combination. 0001 b frame width is 2 bits (2 data bits). 0010 b frame width is 3 bits (3 data bits). ... b ... 1110 b frame width is 15 bits (15 data bits). 1111 b frame width is 16 bits (16 data bits). paren = 1, parity mode enabled : 0000 b reserved; do not use this combination. 0001 b frame width is 2 bits (1 data bit + parity bit. 0010 b frame width is 3 bits (2 data bits + parity bit). ... b ... 1110 b frame width is 15 bits (14 data bits + parity bit). 1111 b frame width is 16 bits (15 data bits + parity bit). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-32 v1.1, 2011-03 ssc, v1.5 hb 4rw heading bit control 0 b transmit/receive lsb first 1 b transmit/receive msb first ph 5rw clock phase control 0 b shift transmit data on the leading clock edge, latch on trailing edge 1 b latch receive data on leading clock edge, shift on trailing edge po 6rw clock polarity control 0 b idle clock line is low, the leading clock edge is low-to-high transition 1 b idle clock line is high, the leading clock edge is high-to-low transition lb 7rw loop-back control 0 b normal output 1 b receive input is connected to transmit output (half-duplex mode) ten 8rw transmit error enable 0 b ignore transmit errors 1 b check transmit errors ren 9rw receive error enable 0 b ignore receive errors 1 b check receive errors pen 10 rw phase error enable 0 b ignore phase errors 1 b check phase errors ben 11 rw baud rate error enable 0 b ignore baud rate errors 1 b check baud rate errors aren 12 rw automatic reset enable 0 b no additional action upon a baud rate error 1 b ssc is automatically reset on a baud rate error field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-33 v1.1, 2011-03 ssc, v1.5 ms 14 rw master select 0 b slave mode. operate on shift clock received via sclk 1 b master mode. generate shift clock and output it via sclk the inverted state of this bit is available on module output line ?m/s selected? (see figure 21-2 ). en 15 rw enable bit 0 b transmission and reception are disabled. 1 b transmission and reception are enabled. this bit is available as module output line ?ssc enabled? (see figure 21-2 ). note that en should only be cleared by software while no transfer is in progress (stat.bsy = 0). note that the transmission/reception enable can also be controlled in queued ssc mode by bit ssotc.en (see page 21-24 ). parten 16 rw parity transmit enable bit this bit enables the parity mode for the transmission of frames. 0 b parity mode for transmission is disabled. 1 b parity mode for transmission is enabled. parren 17 rw parity receive enable bit this bit enables the parity mode for the reception of frames. 0 b parity mode for reception is disabled. 1 b parity mode for reception is enabled. partyp 18 rw parity type bit if paren = 1, this bit defines the type of parity to be generated or checked. 0 b even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data). 1 b odd parity selected (parity bit = 1 on even number of 1s in data, parity bit = 0 on odd number of 1s in data) pareen 19 rw parity error enable 0 b ignore receive parity errors 1 b check receive parity errors field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-34 v1.1, 2011-03 ssc, v1.5 the status register stat contains status flags for error identification, the busy flag, and a bit field that indicates the current shift counter status. 0 13, [31:20] r reserved read as 0; should be written with 0. stat status register (28 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 bsy be pe re te 0 par r val par t val par e bc r rhrhrhrhrh r rhrhrh rh field bits type description bc [3:0] rh bit count status bc indicates the current status of the shift counter. the shift counter is updated with every shifted bit. pare 4rh parity error flag 0 b no error 1 b received parity bit is wrong. partval 5rh parity transmit value if parity mode is enabled, this bit indicates the calculated parity bit for the transmission of the actual serial frame. partval is written with the transmit parity value when the shift register is loaded from tb. partval is reset when con.paren is reset. parrval 6rh parity receive value if parity mode is enabled, this bit parrval is loaded when the received data is written into rb. parrval is reset when con.paren is reset. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-35 v1.1, 2011-03 ssc, v1.5 te 8rh transmit error flag 0 b no error 1 b transfer starts with the slave?s transmit buffer not being updated re 9rh receive error flag 0 b no error 1 b reception completed before the receive buffer was read pe 10 rh phase error flag 0 b no error 1 b received data changes during the sampling clock edge be 11 rh baud rate error flag 0 b no error 1 b there is more than factor 2 or less than factor 0.5 between the slave?s actual and the expected baud rate. bsy 12 rh busy flag bsy is set while a transfer is in progress. 0 7, [31:13] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-36 v1.1, 2011-03 ssc, v1.5 the error flag modification register efm is required for clearing or setting the four error flags which are located in register stat. efm error flag modification register (2c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set be set pe set re set te clr be clr pe clr re clr te 0 set par e 0 clr par e wwwwwwww r w r w field bits type description clrpare 0w clear parity error flag 0 b no effect 1 b bit stat.pare is cleared. bit is always read as 0. setpare 4w set parity error flag 0 b no effect 1 b bit stat.pare is set. bit is always read as 0. clrte 8w clear transmit error flag 0 b no effect 1 b bit stat.te is cleared. bit is always read as 0. clrre 9w clear receive error flag 0 b no effect 1 b bit stat.re is cleared. bit is always read as 0. clrpe 10 w clear phase error flag 0 b no effect 1 b bit stat.pe is cleared. bit is always read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-37 v1.1, 2011-03 ssc, v1.5 note: when the set and clear bits for an error flag are set at the same time during an efm write operation (e.g setpe = clrpe = 1), the error flag in stat is not affected. clrbe 11 w clear baud rate error flag 0 b no effect 1 b bit stat.be is cleared. bit is always read as 0. sette 12 w set transmit error flag 0 b no effect 1 b bit stat.te is set. bit is always read as 0. setre 13 w set receive error flag 0 b no effect 1 b bit stat.re is set. bit is always read as 0. setpe 14 w set phase error flag 0 b no effect 1 b bit stat.pe is set. bit is always read as 0. setbe 15 w set baud rate error flag 0 b no effect 1 b bit stat.be is set. bit is always read as 0. 0 [3:1], [7:5], [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-38 v1.1, 2011-03 ssc, v1.5 the slave select output control register controls the operation of the chip select output generation unit. note: the ssoc register content is latched by each tb register write operation and remains latched during the cons ecutive serial transmission. ssoc slave select output control register (18 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 oen 7 oen 6 oen 5 oen 4 oen 3 oen 2 oen 1 oen 0 aol 7 aol 6 aol 5 aol 4 aol 3 aol 2 aol 1 aol 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description aoln (n = 0-7) nrw active output level 0 b slson is at low level during the chip select active time t slsoact . the high level is the inactive level of slson. 1 b slso line n is at high level during the chip select active time t slsoact . the low level is the inactive level of slson. oenn (n = 0-7) 8+n rw output n enable control 0 b slson output is disabled; slson is always at inactive level as defined by aoln. 1 b slson output is enabled. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-39 v1.1, 2011-03 ssc, v1.5 the slave select output timing control register controls the operation of the slave select output generation unit. ssotc slave select output timing control register (1c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 en qsm en 0 sls o7 mod 0 inact trail lead rww r rwr rwrwrw field bits type description lead [1:0] rw slave output select leading delay this bit field determines the number of leading delay clock cycles. a leading delay clock cycle is always a multiple of an sclk shift clock period. 00 b zero leading delay clock cycle selected 1) 01 b one leading delay clock cycle selected 10 b two leading delay clock cycles selected 11 b three leading delay clock cycles selected trail [3:2] rw slave output select trailing delay this bit field determines the number of trailing delay clock cycles. a trailing delay clock cycle is always a multiple of an sclk shift clock period. 00 b zero trailing delay clock cycle selected 1) 01 b one trailing delay clock cycle selected 10 b two trailing delay clock cycles selected 11 b three trailing delay clock cycles selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-40 v1.1, 2011-03 ssc, v1.5 note: the ssotc register timing paramet ers lead, trail, inact, and slso7mod are latched by each tb register write operation and remain latched during a consecutive serial transmission. bits qs men and en of register ssotc are not latched. inact [5:4] rw slave output select inactive delay this bit field determines the number of inactive delay clock cycles. an inactive delay clock cycle is always a multiple of an sclk shift clock period. 00 b zero inactive delay clock cycle selected 1) 01 b one inactive delay clock cycle selected 10 b two inactive delay clock cycles selected 11 b three inactive delay clock cycles selected slso7mod 8rw slso7 delayed mode selection this bit selects the delayed mode for the slso7 slave select output. 0 b normal mode selected for slso7 1 b delayed mode selected for slso7 qsmen 14 w queued ssc mode enabled 0 b when qsmen is written with 0, the state of bit ssotc.en is don?t care. in this case, the enable/disable of the ssc is controlled by bit con.en only. note that en should only be cleared by software while no transfer is in progress (stat.bsy = 0). 1 b when qsmen is written with 1, queued ssc mode is enabled, and the state of bit ssotc.en is copied to con.en. qsmen is always read as 0. en 15 rw enable bit 0 b transmission and reception are disabled. 1 b transmission and reception are enabled. note that the transmission/reception enable can also be controlled in queued ssc mode by bit con.en. 0 [7:6], [13:9], [31:16] r reserved read as 0; should be written with 0. 1) for getting a best case timing with no timing delays (see figure 21-9 ), this bit field value should be set when the slson outputs are disabled (ssoc.oenn bits set to 0). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-41 v1.1, 2011-03 ssc, v1.5 the baud rate timer reload register br contains the 16-bit reload value for the baud rate timer. br baud rate timer reload register (14 h ) reset value: 0000 0000 h 31 16 15 0 0 br_value rrw field bits type description br_value [15:0] rw baud rate timer/reload register value reading br returns the 16-bit content of the baud rate timer. writing br loads the baud rate timer reload register with br_value. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-42 v1.1, 2011-03 ssc, v1.5 21.2.3 data registers the transmit buffer register tb contains t he transmit data value. a tb write operation latches all timing parameters stored in register ssotc. the receive buffer register rb contains the receive data value. tb transmit buffer register (20 h ) reset value: 0000 0000 h 31 16 15 0 0tb_value rrw field bits type description tb_value [15:0] rw transmit data register value register tb stores the data value to be transmitted tb_value. unused bits of tb_value (as defined by con.bm) are ignored during transmission. 0 [31:16] r reserved read as 0; should be written with 0. rb receive buffer register (24 h ) reset value: 0000 0000 h 31 16 15 0 0 rb_value rrh field bits type description rb_value [15:0] rh receive data register value register rb contains the received data value rb_value (without the parity bit in parity mode) right aligned. unused bits of rb_value (as defined by con.bm) will not be valid and should be ignored. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-43 v1.1, 2011-03 ssc, v1.5 21.3 ssc0/ssc1/ssc2/ssc3 module implementation this section describes ssc0/ssc1/ssc2/ssc3 module interfaces with the clock control, port connections, interrupt control, and address decoding. 21.3.1 module identification registers the reset values of the sscx_id module identification registers are 0000 4512 h . 21.3.2 interfaces of the ssc modules figure 21-16 and figure 21-17 show the TC1798-specific implementation details and interconnections of the ssc0/ssc1/ssc2/ssc3 modules. each of the ssc modules is supplied with a separate clock control, interrupt control, and address decoding logic. two interrupt output s can be used to generate dma requests. the ssc0/ssc1/ssc2/ssc3 i/o lines are connected to port 1, port 2, port 4, port 6, port 7, port 10 and port 18. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-44 v1.1, 2011-03 ssc, v1.5 figure 21-16 ssc0/ssc1 module implementation and interconnections port 10 control mca05791a_mod clock control address decoder interrupt control f ssc 0 address decoder interrupt control to dma f clc0 f ssc 1 f clc1 clock control ssc0_rdr ssc0_tdr to dma ssc1_rdr ssc1_tdr port 2 control . . . mrstb mtsr master slsi1 mrsta mtsrb mrst mtsra sclkb sclk sclka slave slave master slave master port 6 control mrstb mtsr master mrsta mtsrb mrst mtsra sclkb sclk sclka slave slave master master p10 .1 / mtsr0 p10 .0 / mrst0 p10.3 / sclk0 p6.5 / mrst1 p6.4 / mtsr1 p6.6 / sclk1 p10.2 / slsi0 p2.2 / slso02 / slso12 p2.7 / slso07 / slso17 p6.7 / slsi1 slsi[7:2] 3) slsi1 slave slsi[7:2] 3) p10 .4 / slso00 p10 .5 / slso01 1) these lines are not connected slso[1:0] ssc0 module (kernel ) ssc1 module (kernel ) eir tir rir eir tir rir a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 port 1 control p1.6 / slso10 p1 .9 / slso11 a2 a2 slsoando[7:0] slso[7:2] slsoandi[7:0] 1) 2) 2) these lines are connected to v ss slso[7:2] slsoando[7:2] slsoandi[7:2] slso[1:0] slsoandi[1:0] slsoando[1:0] 1) 2) enable 1) m/s select 1) enable 1) m/s select 1) 3) these lines are connected to v dd www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-45 v1.1, 2011-03 ssc, v1.5 figure 21-17 ssc2/ssc3 module implementation and interconnections a1+ a1+ a1+ a1+ a1+ a1+ mca05791b_mod clock control address decoder interrupt control f ssc2 address decoder interrupt control to dma f clc2 f ssc3 f clc3 clock control ssc2_rdr ssc2_tdr to dma ssc3_rdr ssc3_tdr master 1) these lines are not connected slso[7:0] ssc2 module (kernel) ssc3 module (kernel) eir tir rir eir tir rir slsoando[7:0] slsoandi[7:0] 1) 2) 2) these lines are connected to v ss enable 1) m/s select 1) port 4 control mrsta mtsr master slsi1 mtsra mrst sclk slave slave master slave p4.1 / mtsr0 p4.0 / mrst0 p4.2 / sclk0 p4.9 / slsi0 slsi[7:2] 3) sclka port 18 control mrstb mtsr master mtsrb mrst sclk slave slave master p4.1 / mtsr0 p4.0 / mrst0 p4.2 / sclk0 sclkb a1+ a1 a1+ a1+ port 7 control mrsta, b mtsr master slsi1 mtsra, b mrst sclk slave slave master slave p7.1 / mtsr0 p7.0 / mrst0 p7.2 / sclk0 p1.11 / slsi0 slsi[7:2] 3) sclka,b a1+ master slso[7:0] slsoando[7:0] slsoandi[7:0] 1) 2) port 1 control 3) these lines are connected to v dd www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-46 v1.1, 2011-03 ssc, v1.5 21.3.3 on-chip connections this section describes the on-chip connections of the ssc0/ssc1/ssc2 modules. dma requests the dma request lines of the ssc0/ssc1/ss c2 modules become active whenever the related interrupt line is activated. the dm a request lines are connected to the dma controller as shown in table 21-5 . 21.3.4 ssc0/ssc1/ssc2/ssc3 module related external registers figure 21-18 summarizes the module-related external registers which are required for ssc0/ssc1/ssc2/ssc3 programming (see also figure 21-15 for the module kernel specific registers). table 21-5 dma request lines of ssc0/ssc1/ssc2/ssc3 module ssc interrupt request line dma request line description ssc0 rir ssc0_rdr dma channel 00 request input 4 dma channel 06 request input 4 tir ssc0_tdr dma channel 02 request input 4 dma channel 04 request input 4 ssc1 rir ssc1_rdr dma channel 01 request input 4 dma channel 07 request input 4 tir ssc1_tdr dma channel 03 request input 4 dma channel 05 request input 4 ssc2 rir ssc2_rdr dma channel 00 request input 13 tir ssc2_tdr dma channel 02 request input 13 ssc3 rir ssc2_rdr dma channel 07 request input 12 tir ssc2_tdr dma channel 06 request input 12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-47 v1.1, 2011-03 ssc, v1.5 figure 21-18 ssc0/ssc1/ssc2/ ssc3 implementation-specific special function registers p1_iocr8 mca06226_98_mod ssc0_clc ssc1_clc ssc0_tsrc p2_iocr0 ssc0_rsrc ssc0_esrc ssc1_tsrc ssc1_rsrc ssc1_esrc clock control registers interrupt registers port registers p6_iocr4 ssc0_fdr ssc1_fdr p4_iocr0 p4_iocr8 p1_pdr p2_pdr p4_pdr p2_iocr8 p2_iocr12 ssc2_fdr ssc2_clc p6_pdr p7_pdr p10_pdr ssc2_tsrc ssc2_rsrc ssc2_esrc p10_iocr0 ssc3_tsrc ssc3_rsrc ssc3_esrc ssc3_clc ssc3_fdr p18_pdr p18_iocr0 p7_iocr0 p7_iocr4 p1_iocr4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-48 v1.1, 2011-03 ssc, v1.5 21.3.4.1 clock control each ssc module has two clock signals (x = 0-3): ? f clcx this is the module clock that is used inside the ssc kernel for control purposes such as clocking of control logic and register operations. the frequency of f clcx is always identical to the system clock frequency f fpi . the clock control registers sscx_clc make it possible to enable/disable f clcx under certain conditions. ? f sscx this clock is the module clock that is used in the sscx as input clock of the baud rate generator, which finally determines the baud rate of the serial data. the fractional divider registers sscx_fdr control the frequency of f sscx and make it possible to enable/disable it independently of f clcx . the baud rate timer reload register sscx_br define serial data baud rate dependent from the frequency of f sscx . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-49 v1.1, 2011-03 ssc, v1.5 figure 21-19 ssc clock generation output signal can_int_o15 of the multican module can be used for external clock enable control of the fractional divider. mca06227_4_mod clock control register ssc0_clc f clc0 ssc0 clock generation f ssc0 f fpi fractional divider register ssc0_fdr f clc1 ssc1 clock generation f ssc1 ssc0 module kernel baud rate generator ssc0_br ssc1 module kernel baud rate generator ssc1_br multican module int_o15 clock control register ssc1_clc fractional divider register ssc1_fdr f clc2 ssc2 clock generation f ssc2 ssc2 module kernel baud rate generator ssc2_br clock control register ssc2_clc fractional divider register ssc2_fdr f clc3 ssc3 clock generation f ssc3 ssc3 module kernel baud rate generator ssc3_br clock control register ssc3_clc fractional divider register ssc3_fdr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-50 v1.1, 2011-03 ssc, v1.5 the following formulas define the frequency of f sscx . (21.2) (21.3) note: in ssc master mode, the maximu m shift clock frequency is f sscx /2. in ssc slave mode, the maximum shift clock frequency is f sscx /4. combined with the formulas of the baud rate generator (see page 21-14 ) and the fractional divider, the resulting serial data baud rate is defined by: (21.4) (21.5) note: equation (21.2) and equation (21.4) apply to normal divider mode of the fractional divider (fdr.dm = 01 b ). equation (21.3) and equation (21.5) apply to fractional divider mode (fdr.dm = 10 b ). f sscx f fpi 1 n -- - with n = 1024 - fdr.step = f sscx f fpi n 1024 ------------ - with n = 0-1023 = baud rate ssc f fpi 2 br.br_value 1 + () 1024 - fdr.step () ---------------------------------------------------------------------------------------------------------------------------- - = baud rate ssc f fpi fdr.step 2 br.br_value 1 + () 1024 ------------------------------------------------------------------------------------ - with fdr.step = 0-1023 = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-51 v1.1, 2011-03 ssc, v1.5 clock control register each ssc has its own clock control register. the clock control registers sscx_clc make it possible to control (enable/disable) the clock signals f clcx under certain conditions. ssc0_clc ssc0_clock control register (00 h ) reset value: 0000 0003 h ssc1_clc ssc1 clock control register (00 h ) reset value: 0000 0003 h ssc2_clc ssc2 clock control register (00 h ) reset value: 0000 0003 h ssc3_clc ssc3 clock control register (00 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we e dis sp en dis s dis r r rwwrwrw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the module. diss 1r module disable status bit bit indicates the current status of the module. spen 2rw module suspend enable for ocds used to enable the suspend mode. edis 3rw sleep mode en able control used to control module?s sleep mode. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. fsoe 5rw fast switch off enable used to switch off fast clock in suspend mode. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-52 v1.1, 2011-03 ssc, v1.5 note: after a hardware reset operation, the f clcx clocks are disabled , and therefore also the ssc modules are disabled (diss set). fractional divider register each ssc has its own fractional divider re gister. the fractional divider registers sscx_fdr control the clock rate of the shift clocks f sscx . 0 [31:6] r reserved read as 0; should be written with 0. ssc0_fdr ssc0 fractional divider register (0c h ) reset value: 1000 0000 h ssc1_fdr ssc1 fractional divider register (0c h ) reset value: 1000 0000 h ssc2_fdr ssc2 fractional divider register (0c h ) reset value: 1000 0000 h ssc3_fdr ssc3 fractional divider register (0c h ) reset value: 1000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dis clk en hw sus req sus ack 0result rwh rw rh rh r rh 1514131211109876543210 dm sc sm fdis step rw rw rw rw rw field bits type description step [9:0] rw step value reload or addition value for result. fdis 10 rw freeze disable this bit controls the freeze function for this module. 0 b module operates on co rrected clock, with reduced modulation jitter. 1 b module operates on uncorrected clock, with full modulation jitter. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-53 v1.1, 2011-03 ssc, v1.5 21.3.4.2 port control note: the sscs in the TC1798 do not directly control the i/o functionality of pins. therefore, control bi ts con.en and con.ms have no functionality. the interconnections between the ssc modules and the i/o lines/pins are controlled by software in the port logics. the ssc0/ssc1/ssc2 i/o functionality must be selected by the following port control operations (additionally to the pisel programming): ? input/output function selection (iocr registers) ? pad driver characteristics select ion for the outputs (pdr registers) the ssc0/ssc1/ssc2 port input/output control registers contain the bit fields that select the digital output and input driver characte ristics such as pull-up/down devices, port direction (input/output), open-drain, and alternate output selections. sm 11 rw suspend mode sm selects between granted or immediate suspend mode. sc [13:12] rw suspend control this bit field determines the behavior of the fractional divider in suspend mode. dm [15:14] rw divider mode this bit field selects normal divider mode, fractional divider mode, and off-state. result [25:16] rh result value bit field for the addition result. susack 28 rh suspend mode acknowledge indicates state of spndack signal. susreq 29 rh suspend mode request indicates state of spnd signal. enhw 30 rw enable hardware clock control controls operation of ecen input and disclk bit. disclk 31 rwh disable clock hardware-controlled disable for f out signal. 0 [27:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-54 v1.1, 2011-03 ssc, v1.5 figure 21-20 slsi and slso input/output connections TC1798_slso_out ssc0 slso2 slso1 p10.4 / slso00 a1+ a1+ a1+ a1+ slso3 slso4 slso5 slso6 slso7 ssc1 a1+ a1+ slso2 slso3 slso4 slso5 slso6 slso7 slso1 p2.2 / slso2 p2.3 / slso3 p2.4 / slso4 p2.5 / slso5 p2.6 / slso6 p2.7 / slso7 slso0 p10.5 / slso01 a1+ p1.6 / slso10 a2 p1.9 / slso11 a2 slso0 slsoandi2 slsoando2 slsoandi3 slsoando3 slsoandi4 slsoando4 slsoandi5 slsoando5 slsoandi6 slsoando6 slsoandi7 slsoando7 a1+ ssc2 slso2 slso1 p4.3, p18.3 / slso0 a1+ a1+ a1+ a1+ slso3 slso4 p4.5, p18.5 / slso2 p4.6, p18.6 / slso3 p4.7, p18.7 / slso4 slso0 p4.4, p18.4 / slso1 a1+ ssc3 slso2 slso1 p7.3 / slso0 a1+ a1+ a1+ a1+ slso3 slso4 p7.5 / slso2 p7.6 / slso3 p7.7 / slso4 slso0 p7.4 / slso1 a1+ www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-55 v1.1, 2011-03 ssc, v1.5 table 21-6 shows how bits and bit fields must be programmed for the required i/o functionality of the ssc i/o lines. table 21-6 ssc i/o line selection and setup module port lines input/output control register bits i/o ssc0 p10.1 / mtsr0 p10_iocr0.pc1 = 0xxx b input p10_iocr0.pc1 = 1x01 b output p10.0 / mrst0 p10_iocr0.pc0 = 0xxx b input p10_iocr0.pc0 = 1x01 b output p10.3 / sclk0 p10_iocr0.pc3 = 0xxx b input p10_iocr0.pc3 = 1x01 b output p10.2 / slsi0 p10_iocr0.pc4 = 0xxx b input ssc1 p6.4 / mtsr1 p6_iocr4.pc4 = 0xxx b input p6_iocr4.pc4 = 1x01 b output p6.5 / mrst1 p6_iocr4.pc5 = 0xxx b input p6_iocr4.pc5 = 1x01 b output p6.6 / sclk1 p6_iocr4.pc6 = 0xxx b input p6_iocr4.pc6 = 1x01 b output p6.7 / slsi1 p6_iocr4.pc7 = 0xxx b input ssc2 p4.1 / mtsr2 p4_iocr0.pc1 = 0xxx b input p4_iocr0.pc1 = 1x10 b output p4.0 / mrst2 p4_iocr0.pc0 = 0xxx b input p4_iocr0.pc0 = 1x10 b output p4.2 / sclk2 p4_iocr0.pc2 = 0xxx b input p4_iocr0.pc2 = 1x10 b output p4.9 / slsi2 p4_iocr8.pc9 = 0xxx b input ssc2b p18.1 / mtsr2b p18_iocr0.pc1 = 0xxx b input p18_iocr0.pc1 = 1x01 b output p18.0 / mrst2b p18_iocr0.pc0 = 0xxx b input p18_iocr0.pc0 = 1x01 b output p18.2 / sclk2b p4_iocr0.pc2 = 0xxx b input p4_iocr0.pc2 = 1x01 b output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-56 v1.1, 2011-03 ssc, v1.5 ssc3 p7.1 / mtsr3 p7_iocr0.pc1 = 0xxx b input p7_iocr0.pc1 = 1x10 b output p7.0 / mrst3 p7_iocr0.pc0 = 0xxx b input p7_iocr0.pc0 = 1x10 b output p7.2 / sclk3 p7_iocr0.pc2 = 0xxx b input p7_iocr0.pc2 = 1x10 b output p1.11 / slsi3 p1_iocr8.pc11 = 0xxx b input slave select outputs ssc0 p10.4 / slso00 p1 0_iocr4.pc4 = 1x01 b output p10.5 / slso01 p1 0_iocr4.pc5 = 1x01 b output ssc0 p2.2 / slso2 p2_iocr0.pc2 = 1x01 b output ssc1 p2_iocr0.pc2 = 1x10 b ssc0 & ssc1 p2_iocr0.pc2 = 1x11 b ssc0 p2.3 / slso3 p2_iocr0.pc3 = 1x01 b output ssc1 p2_iocr0.pc3 = 1x10 b ssc0 & ssc1 p2_iocr0.pc3 = 1x11 b ssc0 p2.4 / slso4 p2_iocr4.pc4 = 1x01 b output ssc1 p2_iocr4.pc4 = 1x10 b ssc0 & ssc1 p2_iocr4.pc4 = 1x11 b ssc0 p2.5 / slso5 p2_iocr4.pc5 = 1x01 b output ssc1 p2_iocr4.pc5 = 1x10 b ssc0 & ssc1 p2_iocr4.pc5 = 1x11 b ssc0 p2.6 / slso6 p2_iocr4.pc6 = 1x01 b output ssc1 p2_iocr4.pc6 = 1x10 b ssc0 & ssc1 p2_iocr4.pc6 = 1x11 b ssc0 p2.7 / slso7 p2_iocr4.pc7 = 1x01 b output ssc1 p2_iocr4.pc7 = 1x10 b ssc0 & ssc1 p2_iocr4.pc7 = 1x11 b ssc1 p1.6 / slso10 p1_iocr4.pc6 = 1x10 b output p1.9 / slso11 p1_iocr8.pc9 = 1x10 b output table 21-6 ssc i/o line selection and setup (cont?d) module port lines input/output control register bits i/o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-57 v1.1, 2011-03 ssc, v1.5 ssc2 p4.3 / slso20 p4_iocr0.pc3 = 1x10 b output p4.4 / slso21 p4_iocr4.pc4 = 1x10 b p4.5 / slso22 p4_iocr4.pc5 = 1x10 b p4.6 / slso23 p4_iocr4.pc6 = 1x10 b p4.7 / slso24 p4_iocr4.pc7 = 1x10 b p18.3 / slso20 p1 8_iocr4.pc6 = 1x01 b p18.4 / slso20 p1 8_iocr4.pc6 = 1x01 b p18.5 / slso20 p1 8_iocr4.pc6 = 1x01 b p18.6 / slso20 p1 8_iocr4.pc6 = 1x01 b p18.7 / slso20 p1 8_iocr4.pc6 = 1x01 b ssc3 p7.3 / slso30 p7_iocr0.pc3 = 1x10 b output p7.4 / slso31 p7_iocr4.pc4 = 1x10 b p7.5 / slso32 p7_iocr4.pc5 = 1x10 b p7.6 / slso33 p7_iocr4.pc6 = 1x10 b p7.7 / slso34 p7_iocr4.pc7 = 1x10 b table 21-6 ssc i/o line selection and setup (cont?d) module port lines input/output control register bits i/o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-58 v1.1, 2011-03 ssc, v1.5 21.3.4.3 interrupt control registers the 3 3 interrupts of the ssc0/ssc1/ssc2 modules are controlled by the following service request control registers: ? sscx_tsrc (x = 0-3) controls the tr ansmit interrupts of the sscx module ? sscx_rsrc (x = 0-3) controls the receive interrupts of the sscx module ? sscx_esrc (x = 0-3) controls the error interrupts of the sscx module tsrc transmit interrupt service request control register (f4 h ) reset value: 0000 0000 h rsrc receive interrupt service request control register (f8 h ) reset value: 0000 0000 h esrc error interrupt service request control register (fc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-59 v1.1, 2011-03 ssc, v1.5 21.3.5 address map of the ssc modules an absolute register address is given by th e offset address of the register (given in table 21-4 ) plus the module base address (given in table 21-3 ). table 21-7 address map of ssc0/ssc1/ssc2/ssc3 short name description address access mode reset value read write synchronous serial interface 0 (ssc0) ssc0_ clc ssc0 clock control register f031 0000 h u, sv sv, e 0000 0003 h ssc0_ pisel ssc0 port input select register f031 0004 h u, sv u, sv 0000 0000 h ssc0_ id ssc0 module identification register f031 0008 h u, sv be 0000 45xx h ssc0_ fdr ssc0 fractional divider register f031 000c h u, sv sv, e 1000 0000 h ssc0_con ssc0 control register f031 0010 h u, sv u, sv 0000 0000 h ssc0_ br ssc0 baud rate timer reload register f031 0014 h u, sv u, sv 0000 0000 h ssc0_ ssoc ssc0 slave select output control register f031 0018 h u, sv u, sv 0000 0000 h ssc0_ ssotc ssc0 slave select output timing control register f031 001c h u, sv u, sv 0000 0000 h ssc0_ tb ssc0 transmit buffer register f031 0020 h u, sv u, sv 0000 0000 h ssc0_ rb ssc0 receive buffer register f031 0024 h u, sv u, sv 0000 0000 h ssc0_ stat ssc0 status register f031 0028 h u, sv u, sv 0000 0000 h ssc0_ efm ssc0 error flag modification register f031 002c h u, sv u, sv 0000 0000 h ? reserved f031 0030 h - f031 00f0 h be be ? ssc0_ tsrc ssc0 transmit interrupt service req. control reg. f031 00f4 h u, sv sv 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-60 v1.1, 2011-03 ssc, v1.5 ssc0_ rsrc ssc0 receive interrupt service req. control reg. f031 00f8 h u, sv sv 0000 0000 h ssc0_ esrc ssc0 error interrupt service req. control reg. f031 00fc h u, sv sv 0000 0000 h synchronous serial interface 1 (ssc1) ssc1_clc ssc1 clock control register f031 0100 h u, sv sv, e 0000 0003 h ssc1_ pisel ssc1 port input select register f031 0104 h u, sv u, sv 0000 0000 h ssc1_ id ssc1 module identification register f031 0108 h u, sv be 0000 45xx h ssc1_ fdr ssc1 fractional divider register f031 010c h u, sv sv, e 1000 0000 h ssc1_con ssc1 control register f031 0110 h u, sv u, sv 0000 0000 h ssc1_ br ssc1 baud rate timer reload register f031 0114 h u, sv u, sv 0000 0000 h ssc1_ ssoc ssc1 slave select output control register f031 0118 h u, sv u, sv 0000 0000 h ssc1_ ssotc ssc1 slave select output timing control register f031 011c h u, sv u, sv 0000 0000 h ssc1_ tb ssc1 transmit buffer register f031 0120 h u, sv u, sv 0000 0000 h ssc1_ rb ssc1 receive buffer register f031 0124 h u, sv u, sv 0000 0000 h ssc1_stat ssc1 status register f031 0128 h u, sv u, sv 0000 0000 h ssc1_ efm ssc1 error flag modification register f031 012c h u, sv u, sv 0000 0000 h ? reserved f031 0130 h - f031 01f0 h be be ? ssc1_ tsrc ssc1 transmit interrupt service req. control reg. f031 01f4 h u, sv sv 0000 0000 h ssc1_ rsrc ssc1 receive interrupt service req. control reg. f031 01f8 h u, sv sv 0000 0000 h table 21-7 address map of ssc0/ssc1/ssc2/ssc3 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-61 v1.1, 2011-03 ssc, v1.5 ssc1_ esrc ssc1 error interrupt service req. control reg. f031 01fc h u, sv sv 0000 0000 h synchronous serial interface 2 (ssc2) ssc2_clc ssc2 clock control register f031 0300 h u, sv sv, e 0000 0003 h ssc2_ pisel ssc2 port input select register f031 0304 h u, sv u, sv 0000 0000 h ssc2_ id ssc2 module identification register f031 0308 h u, sv be 0000 45xx h ssc2_ fdr ssc2 fractional divider register f031 030c h u, sv sv, e 1000 0000 h ssc2_con ssc2 control register f031 0310 h u, sv u, sv 0000 0000 h ssc2_ br ssc2 baud rate timer reload register f031 0314 h u, sv u, sv 0000 0000 h ssc2_ ssoc ssc2 slave select output control register f031 0318 h u, sv u, sv 0000 0000 h ssc2_ ssotc ssc2 slave select output timing control register f031 031c h u, sv u, sv 0000 0000 h ssc2_ tb ssc2 transmit buffer register f031 0320 h u, sv u, sv 0000 0000 h ssc2_ rb ssc2 receive buffer register f031 0324 h u, sv u, sv 0000 0000 h ssc2_stat ssc2 status register f031 0328 h u, sv u, sv 0000 0000 h ssc2_ efm ssc2 error flag modification register f031 032c h u, sv u, sv 0000 0000 h ? reserved f031 0330 h - f031 03f0 h be be ? ssc2_ tsrc ssc2 transmit interrupt service req. control reg. f031 03f4 h u, sv sv 0000 0000 h ssc2_ rsrc ssc2 receive interrupt service req. control reg. f031 03f8 h u, sv sv 0000 0000 h ssc2_ esrc ssc2 error interrupt service req. control reg. f031 03fc h u, sv sv 0000 0000 h table 21-7 address map of ssc0/ssc1/ssc2/ssc3 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface (ssc) users manual 21-62 v1.1, 2011-03 ssc, v1.5 synchronous serial interface 3 (ssc3) ssc3_clc ssc3 clock control register f031 0400 h u, sv sv, e 0000 0003 h ssc3_ pisel ssc3 port input select register f031 0404 h u, sv u, sv 0000 0000 h ssc3_ id ssc3 module identification register f031 0408 h u, sv be 0000 45xx h ssc3_ fdr ssc3 fractional divider register f031 040c h u, sv sv, e 1000 0000 h ssc3_con ssc3 control register f031 0410 h u, sv u, sv 0000 0000 h ssc3_ br ssc3 baud rate timer reload register f031 0414 h u, sv u, sv 0000 0000 h ssc3_ ssoc ssc3 slave select output control register f031 0418 h u, sv u, sv 0000 0000 h ssc3_ ssotc ssc3 slave select output timing control register f031 041c h u, sv u, sv 0000 0000 h ssc3_ tb ssc3 transmit buffer register f031 0420 h u, sv u, sv 0000 0000 h ssc3_ rb ssc3 receive buffer register f031 0424 h u, sv u, sv 0000 0000 h ssc3_stat ssc3 status register f031 0428 h u, sv u, sv 0000 0000 h ssc3_ efm ssc3 error flag modification register f031 042c h u, sv u, sv 0000 0000 h ? reserved f031 0430 h - f031 04f0 h be be ? ssc3_ tsrc ssc3 transmit interrupt service req. control reg. f031 04f4 h u, sv sv 0000 0000 h ssc3_ rsrc ssc3 receive interrupt service req. control reg. f031 04f8 h u, sv sv 0000 0000 h ssc3_ esrc ssc3 error interrupt service req. control reg. f031 04fc h u, sv sv 0000 0000 h table 21-7 address map of ssc0/ssc1/ssc2/ssc3 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-1 v1.1, 2011-03 sscg, v1.7 22 synchronous serial interface guardian (sscg) this chapter describes one sscg module in top-down fashion. the chapter consists of the following sections: ? overview - providing a description of the subsystem consisting of one ssc module and the corresponding sscg module. ? kernel description, describing how the sscg module works and how it is to be used. ? registers description, providing detailed information on each sscg specific register. ? TC1798 implementation description. 22.1 overview figure 22-1 shows a sub-system consisting of - one ssc module ssc0 - one sscg module sscg0 this sub-system can be analyzed independently of the rest of the chip. one chip can contain one or more such subsystems. figure 22-1 general block diagram of an ssc / sscg sub-system ssc0 pad pad pad sscg0 open sclk mrst mtsr mrst mtsr sclk fpi_clk 1xssc_1xsscg_subsystem.vsd 0 pad slsx 8 8 sclkg slsig 8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-2 v1.1, 2011-03 sscg, v1.7 22.1.1 general operation one sscg monitors one ssc module. the sscg itself can be considered as an ssc module, extended with some additional logic and registers. it is always configured in master mode, that is, the same as the monitored ssc. on the serial communication side, it receives all messages transmitted by the ssc module. on the fpi bus side, its registers inherited from the ssc module are al ways written in parallel to the registers of the ssc and contain identical values. the sscg has an additional compare logic with additional registers which compares a copy of the ideal transmit message with the message that really appears on the pin. if a mismatch occurs, an interrupt is raised. a user software can access the sscg by reading / writing in two address ranges: one address range common to ssc and sscg, and one dedicated to sscg only. the extended sscg registers can be accessed only through the dedicated address range. figure 22-2 an address map of an ssc / sscg sub-system ssc0 sscg0 address map ssc0 sscg0 read/write write snoop (listen) passive write does not drive the bpi outputs read/write f031 0000 h f031 0800 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-3 v1.1, 2011-03 sscg, v1.7 22.2 sscg kernel description this chapter describees the additional fu nctionality provided by the guardian. 22.2.1 details on the operation principles and the architecture the sscg module generates its own clock the same way the ssc does, by using identical but independent hardware. sscg is initialized in parallel to the ssc using the same write accesses for initializing the ssc. the parallel register accesses insure cycle accurate parallel operation of the both modules. once all the common registers are initialize d and the ssc starts to operate, the guardian immediately and transparently to the user starts with comparing the outgoing messages on the pin to the ideally programmed messages written in the transmit buffers of the ssc and the sscg. the ssc and the guardian both transmit the same message in parallel with their state machines operating cycle-synchronously, but whereas the ssc receives messages from the outside world, the sscg receives the message being sent by its ssc. a write to the transmit buffer of the sscg copies in parallel the message to two locations: to the shift register and to the tb1 register . the message shifted out of the guardian ends nowhere, but the ssc transmitted message, which should be the identical one, is shifted into the guardian. the received message is copied from the shift register to the receive buffer and with this copy event a comparison between the sent and the received message is triggered. if a difference is detected, an interrupt is raised, the contents of the tb1 and rb are copied to the snapshot registers tb1snap and rbsnap, and at the same time the sticky error flag snapf is set. the hardware can only set the bit snapf, and the software can reset (or set) this flag. reading this flag by software does not reset this flag automatically. it is reset by a second memory access, a write to the gefm register. message length the message length can vary according to the settings from 2 to 16 bits. the padding bits not belonging to the message filling the maximum length of 16 are undefined, and shall be masked out when performing the comparison. parity bit if the parity bit is set, than the effective message length is one bit shorter, and the total length includes the concatenated parity bit. pa rity error shall be raised by the guardian using the normal parity check mechanisms. the guardian comparison shall be done on effective message length, taking the parity out. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-4 v1.1, 2011-03 sscg, v1.7 snapshots the sscg keeps a snapshot of the information of the last error message in the registers tb1snap and rbsnap. the snapf bit flags that error occurred. the snapshot is sticky, that is it is not destroyed by the consequent correct messages. only a new error message overwrites the snapshot of an old error message. a lost snapshot is not flagged. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-5 v1.1, 2011-03 sscg, v1.7 interrupts the three ssc interrupts, the rx and tx and error interrupts, are not used. there is a dedicated sscg interrupt node, signaling a comparison error and parity error. both errors cause taking a st icky snapshot on tb1 and rb. compare error sets the sticky flag gstat.ce. parity error sets the sticky flag stat.pare. additionally the sscg interupt node signals a phase error and clock and slave select compare errors. phase error sets the sticky flag stat.pe. cl ock and slave select errors set the sticky flags in the gstat register. data comparison error and the parity error trigger the interrupt after the data comparison has been done. the sls and clk comparison errors and the phase error trigger an interrupt immediately. figure 22-3 sscg interrupts ssc0 sscg0 fpi_clk sscg_interrupts_1.vsd tsrc rsrc esrc tsrc rsrc esrc cpu, pcp, dma gsrc compare and parity errors www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-6 v1.1, 2011-03 sscg, v1.7 22.2.1.1 monitoring the slave select and serial clock signals the slave select signals slsx are monitored continuously with the same serial clock edge as the data signals. in contrast to the data signal which is sampled only during the data shift phase, all sls signals are sampled and compared all the time: during the idle, leading delay, data shift, inter word delay, and trailing delay ph ases. the goal is to monitor if the ssc module oper ates properly and to detect stuck-at and ot her failiures in the hardware of the module. the clock signal sclk is monitored continuously in the middle of each half-period. this is achieved by using a double frequency, which is generated by a dedicated clock divider, similar to the main baud-rate generator. the purpose of the monitoring is to assure the corect operation of the ssc baud-rate generator and quickly detect hardware failiures. this concept covers the hardware operation with focus on the digital functionality. checking the timing constraints is not a subject of the monitoring, due to the wide variation of the timings and their dependency on process, voltage, temperature and the capacitive load at the lines. therefore the baud rates are limited to single digit mbaud rates, which is necessary in order to have robust monitoring without timing violations and with stable signals arround the sample points. communication disturbances due to signal glitches and emi effects can not be covered sufficiently using monitoring with digital sampling, and therefore they are not covered. they are covered with the parity bit and taken care of by the customer during the design of the printed circuit board. each of the eight sls signals and the one sclk is associat ed to a sticky flag signaling an occurence of a mismatch between an ssc signal and the corresponding sscg signal. it is set by hardware and can be reset only by software. for test purposes these flags can be set by software , using the gefm register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-7 v1.1, 2011-03 sscg, v1.7 figure 22-4 implementation of the slsx and sclk monitoring registers xor (not equal) s6 s7 s4 s5 s2 s3 s0 s1 rh rh rh rh rh rh rh rh xor (not equal) xor (not equal) . . . 23 22 21 20 19 18 17 16 gstat guardian status register ssc guardian ssc . . . sls0 sls1 sls7 . . . sls0 sls1 sls7 sls0_g sls1_g sls2_g err+ int gefm guardian error flag modification register sct3 sct2 sct1 sct0 rw rw rw rw rw rw rw rw 23 22 21 20 19 18 17 16 sct7 sct6 sct5 sct4 rw rw rw rw rw rw rw rw 31 30 29 28 27 26 25 24 sticky error flags sclk s clk rh 2 set flags reset flags sctc rw rw 3 2 xor (not equal) sclk sclk_g error interrupt on difference baudrate generator 2 f sclk 2 x f sclk sen 7 sen 8 sen 5 sen 6 sen 3 sen 4 sen 1 sen 2 rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 gen guardian enable register enable bits sen 0 rw 0 sls_clk_monitoring_1.vsd www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-8 v1.1, 2011-03 sscg, v1.7 22.3 sscg kernel registers, inherited from ssc this section describes the kernel registers of the ssc module. all ssc kernel register names described in this section will be referenced in other parts of the TC1798 users manual by the module name prefix ?sscg0_? for the sscg0 interface, ?sscg1, 2, 3_? for the sscg1, 2, 3 interfaces. all registers in the sscg address spaces are reset with the application reset (definition see scu section ?reset operation?). ssc kernel register overview figure 22-5 sscg kernel registers the complete address map of the ssc modules is described in table 22-5 on page 22-41 . table 22-1 registers address space - ssc kernel registers module base address end address note sscg0 f031 0800 h f031 09ff h ? sscg1 f031 0a00 h f031 0bff h ? sscg2 f031 0c00 h f031 0dff h ? sscg3 f031 0e00 h f031 0fff h ? con br sscg_kern_regs_1.vsd control registers data registers stat efm ssoc ssotc pisel identification register id tb rb tb1 tb1snap rbsnap gstat sscg01_ sscg0_ sscg0_ gefm gen www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-9 v1.1, 2011-03 sscg, v1.7 table 22-2 registers overview - ssc kernel registers register short name register long name offset address 1) 1) the absolute register address is calculated as follows: module base address ( table 22-1 ) + offset address (shown in this column) description see ssc - inherited registers pisel port input select register 004 h page 22-11 id module identification register 008 h page 22-10 con control register 010 h page 22-13 br baud rate timer reload register 014 h page 22-23 stat status register 028 h page 22-16 efm error flag modification register 02c h page 22-18 ssoc slave select output control register 018 h page 22-20 ssotc slave select output timing control reg. 01c h page 22-21 tb transmit buffer register 020 h page 22-24 rb receive buffer register 024 h page 22-24 sscg - specific registers tb1 transmit buffer compare register 100 h page 22-25 tb1snap transmit buffer snapshot register 104 h page 22-25 rbsnap receive buffer snapshot register 108 h page 22-26 gstat guardian status register 10c h page 22-27 gefm guardian error flag modification register 110 h page 22-28 gen guardian enable register 114 h page 22-29 gsrc guardian service request control reg. 1fc h page 22-39 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-10 v1.1, 2011-03 sscg, v1.7 22.3.1 module identification register the ssc module identification register id contains read-only information about the module version. id module identificat ion register (08 h ) reset value: 0085 c0xx h 31 16 15 8 7 0 modnum modtype modrev rrr field bits type description modrev [7:0] r module revision number this bit field defines the module revision number.. modtype [15:8] r module type this bit field defines the module as a 32-bit module: c0 h modnum [31:16] r module number value this bit field defines the module identification number for the sscg: 0085 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-11 v1.1, 2011-03 sscg, v1.7 22.3.2 control registers the pisel register controls the input signal selection of the ssgc module. each input of the module kernel receive, transmit and clock signals has associated two input lines (marked by suffix a and b). note: they may need to be programmed / initialized differently for ssc / sscg module, depending on the top level connections to the ports and pins. in general, such situation should be avoided, if possible. pisel port input select register (04 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 stip 0 slsis scis sris mri s r rw r rw rw rw rw field bits type description mris 0rw master mode rece ive input select mris selects the receive i nput line in master mode. 0 b receive input line mrsta is selected 1 b receive input line mrstb is selected sris 1rw slave mode receive input select sris selects receive input line in slave mode. 0 b receive input line mtsra is selected 1 b receive input line mtsrb is selected scis 2rw slave mode clock input select scis selects the module kernel sclk input line that is used as clock input line in slave mode. 0 b slave mode clock input line sclka is selected 1 b slave mode clock input line sclkb is selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-12 v1.1, 2011-03 sscg, v1.7 slsis [5:3] rw slave mode slave select input selection 000 b slave select input lines are deselected; ssc is operating without slave select input functionality. 001 b slsi input line 1 is selected for operation. 010 b slsi input line 2 is selected for operation. 011 b slsi input line 3 is selected for operation. 100 b slsi input line 4 is selected for operation. 101 b slsi input line 5 is selected for operation. 110 b slsi input line 6 is selected for operation. 111 b slsi input line 7 is selected for operation. in the TC1798, other combinations of slsis except 000 b and 001 b are reserved and must not be used. stip 8rw slave transmit idle state polarity this bit determines the logic level of the slave mode transmit signal mrst when the ssc slave select input signals are inactive (pisel.slsis 000 b ). 0 b mrst = 0 when ssc is deselected in slave mode. 1 b mrst = 1 when ssc is deselected in slave mode. 0 [7:6], [31:9] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-13 v1.1, 2011-03 sscg, v1.7 the operating modes of the ssc are controlled by the control register con. this register contains control bits for mode and error check selection. note: whenever operating mode parameters in the con register are changed by software, no transfer should be in progress (stat.bsy = 0) and the ssc should be disabled (con.en = 0) and afterwards enabled again (con.en = 1). con control register (10 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 par een par typ par ren par ten r rwrwrwrw 1514131211109876543210 en ms 0 a ren ben pen ren ten lb po ph hb bm rwrw r rwrwrwrwrwrwrwrwrw rw field bits type description bm [3:0] rw frame width selection bm determines the number of bits of the serial frame. frame width without parity : 0000 b reserved; do not use this combination. 0001 b frame width is 2 bits (2 data bits). 0010 b frame width is 3 bits (3 data bits). ... b ... 1110 b frame width is 15 bits (15 data bits). 1111 b frame width is 16 bits (16 data bits). frame width with parity : 0000 b reserved; do not use this combination. 0001 b frame width is 2 bits (1 data bit + parity bit. 0010 b frame width is 3 bits (2 data bits + parity bit). ... b ... 1110 b frame width is 15 bits (14 data bits + parity bit). 1111 b frame width is 16 bits (15 data bits + parity bit). hb 4rw heading bit control 0 b transmit/receive lsb first 1 b transmit/receive msb first www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-14 v1.1, 2011-03 sscg, v1.7 ph 5rw clock phase control 0 b shift transmit data on the leading clock edge, latch on trailing edge 1 b latch receive data on leading clock edge, shift on trailing edge po 6rw clock polarity control 0 b idle clock line is low, th e leading clock edge is low- to-high transition 1 b idle clock line is high, the leading clock edge is high-to-low transition lb 7rw loop-back control 0 b normal output 1 b receive input is connected to transmit output (half-duplex mode) ten 8rw transmit error enable 0 b ignore transmit errors 1 b check transmit errors ren 9rw receive error enable 0 b ignore receive errors 1 b check receive errors pen 10 rw phase error enable 0 b check phase errors 1 b check phase errors in the ssc guardian module, the phase error is always checked, independent of the setting of the enable bit. ben 11 rw baud rate error enable 0 b ignore baud rate errors 1 b check baud rate errors aren 12 rw automatic reset enable 0 b no additional action upon a baud rate error 1 b ssc is automatically reset on a baud rate error ms 14 rw master select 0 b slave mode. operate on sh ift clock received via sclk 1 b master mode. generate shift clock and output it via sclk the inverted state of this bit is available on module output line ?m/s selected?. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-15 v1.1, 2011-03 sscg, v1.7 the status register stat contains status flags for error identification, the busy flag, and a bit field that indicates the current shift counter status. en 15 rw enable bit 0 b transmission and reception are disabled. 1 b transmission and reception are enabled. this bit is available as module output line ?ssc enabled?. note that en should only be cleared by software while no transfer is in progress (stat.bsy = 0). note that the transmission/reception enable can also be controlled in queued ssc mode by bit ssotc.en. parten 16 rw parity transmit enable bit this bit enables the parity mode for transmit frames. 0 b parity mode for transmit frames is disabled. 1 b parity mode for transmit frames is enabled. parren 17 rw parity receive enable bit this bit enables the parity mode for receive frames. 0 b parity mode for receive frames is disabled. 1 b parity mode for receive frames is enabled. partyp 18 rw parity type bit if paren = 1, this bit defines the type of parity to be generated or checked. 0 b even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data). 1 b odd parity selected (parity bit = 1 on even number of 1s in data, parity bit = 0 on odd number of 1s in data) pareen 19 rw parity error enable 0 b ignore receive parity errors 1 b check receive parity errors 0 13, [31:20] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-16 v1.1, 2011-03 sscg, v1.7 stat status register (28 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 bsy be pe re te 0 par r val par t val par e bc r rhrhrhrhrh r rhrhrh rh field bits type description bc [3:0] rh bit count status bc indicates the current status of the shift counter. the shift counter is updated with every shifted bit. pare 4rh parity error flag 0 b no error 1 b received parity bit is wrong. partval 5rh parity transmit value if parity mode is enabled, this bit indicates the calculated parity bit for the transmission of the actual serial frame. partval is written with the transmit parity value when the shift register is loaded from tb. partval is reset when con.paren is reset. parrval 6rh parity receive value if parity mode is enabled, this bit parrval is loaded when the received data is written into rb. parrval is reset when con.paren is reset. te 8rh transmit error flag 0 b no error 1 b transfer starts with the slave?s transmit buffer not being updated re 9rh receive error flag 0 b no error 1 b reception completed before the receive buffer was read www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-17 v1.1, 2011-03 sscg, v1.7 pe 10 rh phase error flag 0 b no error 1 b received data changes during the sampling clock edge be 11 rh baud rate error flag 0 b no error 1 b there is more than factor 2 or less than factor 0.5 between the slave?s actual and the expected baud rate. bsy 12 rh busy flag bsy is set while a transfer is in progress. 0 7, [31:13] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-18 v1.1, 2011-03 sscg, v1.7 the error flag modification register efm is required for clearing or setting the four error flags which are located in register stat. efm error flag modification register (2c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set be set pe set re set te clr be clr pe clr re clr te 0 set par e 0 clr par e wwwwwwww r w r w field bits type description clrpare 0w clear parity error flag 0 b no effect 1 b bit stat.pare is cleared. bit is always read as 0. setpare 4w set parity error flag 0 b no effect 1 b bit stat.pare is set. bit is always read as 0. clrte 8w clear transmit error flag 0 b no effect 1 b bit stat.te is cleared. bit is always read as 0. clrre 9w clear receive error flag 0 b no effect 1 b bit stat.re is cleared. bit is always read as 0. clrpe 10 w clear phase error flag 0 b no effect 1 b bit stat.pe is cleared. bit is always read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-19 v1.1, 2011-03 sscg, v1.7 note: when the set and clear bits for an error flag are set at the same time during an efm write operation (e.g setpe = clrpe = 1), the error flag in stat is not affected. clrbe 11 w clear baud rate error flag 0 b no effect 1 b bit stat.be is cleared. bit is always read as 0. sette 12 w set transmit error flag 0 b no effect 1 b bit stat.te is set. bit is always read as 0. setre 13 w set receive error flag 0 b no effect 1 b bit stat.re is set. bit is always read as 0. setpe 14 w set phase error flag 0 b no effect 1 b bit stat.pe is set. bit is always read as 0. setbe 15 w set baud rate error flag 0 b no effect 1 b bit stat.be is set. bit is always read as 0. 0 [3:1], [7:5], [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-20 v1.1, 2011-03 sscg, v1.7 the slave select output control register controls the operation of the chip select output generation unit. note: the ssoc register content is latched by each tb register write operation and remains latched during the cons ecutive serial transmission. ssoc slave select output control register (18 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 oen 7 oen 6 oen 5 oen 4 oen 3 oen 2 oen 1 oen 0 aol 7 aol 6 aol 5 aol 4 aol 3 aol 2 aol 1 aol 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description aoln (n = 0-7) nrw active output level 0 b slson is at low level during the chip select active time t slsoact . the high level is the inactive level of slson. 1 b slso line n is at high level during the chip select active time t slsoact . the low level is the inactive level of slson. oenn (n = 0-7) 8+n rw output n enable control 0 b slson output is disabled; slson is always at inactive level as defined by aoln. 1 b slson output is enabled. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-21 v1.1, 2011-03 sscg, v1.7 the slave select output timing control register controls the operation of the slave select output generation unit. ssotc slave select output timing control register (1c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 en qsm en 0 sls o7 mod 0 inact trail lead rww r rwr rwrwrw field bits type description lead [1:0] rw slave output select leading delay this bit field determines the number of leading delay clock cycles. a leading delay clock cycle is always a multiple of an sclk shift clock period. 00 b zero leading delay clock cycle selected 1) 01 b one leading delay clock cycle selected 10 b two leading delay clock cycles selected 11 b three leading delay clock cycles selected trail [3:2] rw slave output select trailing delay this bit field determines the number of trailing delay clock cycles. a trailing delay clock cycle is always a multiple of an sclk shift clock period. 00 b zero trailing delay clock cycle selected 1) 01 b one trailing delay clock cycle selected 10 b two trailing delay clock cycles selected 11 b three trailing delay clock cycles selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-22 v1.1, 2011-03 sscg, v1.7 note: the ssotc register timing paramet ers lead, trail, inact, and slso7mod are latched by each tb register write operation and remain latched during a consecutive serial transmission. bits qs men and en of register ssotc are not latched. inact [5:4] rw slave output select inactive delay this bit field determines the number of inactive delay clock cycles. an inactive delay clock cycle is always a multiple of an sclk shift clock period. 00 b zero inactive delay clock cycle selected 1) 01 b one inactive delay clock cycle selected 10 b two inactive delay clock cycles selected 11 b three inactive delay clock cycles selected slso7mod 8rw slso7 delayed mode selection this bit selects the delayed mode for the slso7 slave select output. 0 b normal mode selected for slso7 1 b delayed mode selected for slso7 qsmen 14 w queued ssc mode enabled 0 b when qsmen is written with 0, the state of bit ssotc.en is don?t care. in this case, the enable/disable of the ssc is controlled by bit con.en only. note that en should only be cleared by software while no transfer is in progress (stat.bsy = 0). 1 b when qsmen is written with 1, queued ssc mode is enabled, and the state of bit ssotc.en is copied to con.en. qsmen is always read as 0. en 15 rw enable bit 0 b transmission and reception are disabled. 1 b transmission and reception are enabled. note that the transmission/reception enable can also be controlled in queued ssc mode by bit con.en. 0 [7:6], [13:9], [31:16] r reserved read as 0; should be written with 0. 1) for getting a best case timing with no timing delays, this bit field value should be set when the slson outputs are disabled (ssoc.oenn bits set to 0). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-23 v1.1, 2011-03 sscg, v1.7 the baud rate timer reload register br contains the 16-bit reload value for the baud rate timer. br baud rate timer reload register (14 h ) reset value: 0000 0000 h 31 16 15 0 0 br_value rrw field bits type description br_value [15:0] rw baud rate timer/reload register value reading br returns the 16-bit content of the baud rate timer. writing br loads the baud rate timer reload register with br_value. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-24 v1.1, 2011-03 sscg, v1.7 22.3.3 data registers the transmit buffer register tb contains t he transmit data value. a tb write operation latches all timing parameters stored in register ssotc. the receive buffer register rb contains the receive data value. tb transmit buffer register (20 h ) reset value: 0000 0000 h 31 16 15 0 0tb_value rrw field bits type description tb_value [15:0] rw transmit data register value register tb stores the data value to be transmitted tb_value. unused bits of tb_value (as defined by con.bm) are ignored during transmission. 0 [31:16] r reserved read as 0; should be written with 0. rb receive buffer register (24 h ) reset value: 0000 0000 h 31 16 15 0 0 rb_value rrh field bits type description rb_value [15:0] rh receive data register value register rb contains the received data value rb_value (without the parity bit in parity mode) right aligned. unused bits of rb_value (as defined by con.bm) will not be valid and should be ignored. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-25 v1.1, 2011-03 sscg, v1.7 22.3.4 sscg specific registers the transmit buffer compare register tb1 co ntains a copy of the currently transmitted data value. this register can be written by software. a software write triggers automatically a compare with the receive buffer. this is used for error injection for test purposes, and should not be performed during a real application. this register is writen also by hardware. when transferring the tb value to the shift register, at the same time in parallel, the same data is written to the tb1 register. the transmit buffer snapshot register tb1snap contains the last erroneous transmitted data value. this is a read only register tb1 transmit buffer compare register (100 h ) reset value: 0000 0000 h 31 16 15 0 0tb_value rrwh field bits type description tb_value [15:0] rwh transmit data register value register tb stores the data value to be transmitted tb_value. unused bits of tb_value (as defined by con.bm) are ignored during transmission. 0 [31:16] r reserved read as 0; should be written with 0. tb1snap transmit buffer snapshot register (104 h ) reset value: 0000 0000 h 31 16 15 0 0tb_value rr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-26 v1.1, 2011-03 sscg, v1.7 the receive buffer snapshot register rbsnap contains the last erroneous received data value. this is a read only register. field bits type description tb_value [15:0] rw transmit data snapshot value register tb1snap stores the last erroneous transmitted data tb_value. unused bits of tb_value (as defined by con.bm) are ignored during transmission. 0 [31:16] r reserved read as 0; should be written with 0. rbsnap receive buffer snapshot register (108 h ) reset value: 0000 0000 h 31 16 15 0 0 rb_value rrh field bits type description rb_value [15:0] rh receive snapshot register value register rb contains the last received erroneous data value rb_value right aligned. unused bits of rb_value (as defined by con.bm) will not be valid and should be ignored. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-27 v1.1, 2011-03 sscg, v1.7 the status register gstat contains sticky stat us flags for error identification. they are set by hardware in case of an error, and can be cleared only by software, using the gefm register. they can be set and cleared by software, but can not be cleared by hardware. phase error and parity error are flaged in th e stat register and generate an interrupt. gstat guardian status register (10c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 s7 s6 s5 s4 s3 s2 s1 s0 r rhrhrhrhrhrhrhrh 1514131211109876543210 0 s clk 0ce rrhrrh field bits type description ce 0rh compare error flag 0 b no compare error 1 b compare error has occurred sclk 2rh sclk error flag 0 b no error 1 b error on the sclk signal s0, s1, s2, s3, s4, s5, s6, s7 16, 17, 18, 19, 20, 21, 22, 23 rh slsx error flag 0 b no error 1 b error on the corresponding sls signal 0 1, [15:3], [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-28 v1.1, 2011-03 sscg, v1.7 the guardian error flag modification regist er gefm contains bits for modifying the error flags and injecting errors per software. gefm guardian error flag modification register(110 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sct7 sct6 sct5 sct4 sct3 sct2 sct1 sct0 wwwwwwww 1514131211109876543210 00 set ce 0sctc0 clr ce rrwrwrw field bits type description clrce 0w clear compare error flag 0 b no effect 1 b clear the compare error flag gstat.ce setce 8w set compare error flag 0 b no effect 1 b set the compare error flag gstat.ce sct0, sct1, sct2, sct3, sct4, sct5, sct6, sct7 [17:16], [19:18], [21:20], [23:22], [25:24], [27:26], [29:28], [31:30] w set clear toggle th e slsx error flag 00 b no action 01 b set the slsx error flag gstat.sx. 10 b clear the slsx error flag gstat.sx. 11 b toggle the slsx error flag gstat.sx. reading this bit field deliveres 0. sctc [3:2] w set clear toggle the sclk error flag 00 b no action 01 b set the error flag gstat.sclk. 10 b clear the error flag gstat.sclk. 11 b toggle the error flag gstat.sclk. reading this bit field deliveres 0. 0 1, 9, [7:4], [15:10] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-29 v1.1, 2011-03 sscg, v1.7 the guardian enable register gen contains bits for enabling and disabling the monitoring of the slave select and clock signals. gen guardian enable register (114 h ) reset value: 0000 0100 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0cen sen 7 sen 6 sen 5 sen 4 sen 3 sen 2 sen 1 sen 0 r rwrwrwrwrwrwrwrwrw field bits type description sen0, sen1, sen2, sen3, sen4, sen5, sen6, sen7 0, 1, 2, 3, 4, 5, 6, 7 rw slave select x monitoring enable 0 b disabled (default value) 1 b enabled cen 8w clock monitoring enable 0 b disabled 1 b enabled (default value) 0 [31:9] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-30 v1.1, 2011-03 sscg, v1.7 22.4 sscg0 module implementation this section describes ssc / sscg modules interfaces with the clock control, port connections, interrupt control, and address decoding. 22.4.1 module identification registers the reset values of the sscgx_id module identification register is 0085 c0xx h . 22.4.2 interfaces of the sscg modules figure 22-6 shows the interconnections of the ssc / sscg subsystem. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-31 v1.1, 2011-03 sscg, v1.7 figure 22-6 ssc0/ssc1/sscg01 subsystem interconnections ssc0 pad pad sscg0 open sclka mrsta mrsta, b sclk sclka, b fpi_clk 1xssc_1xsscg_pisels_2.vsd pad mtsr pad mtsr pisel pad mrstb pad pad pad sclk 0 open mtsr 0 mtsra,b pad mtsrb pad mtsra pad mtsr slave master pisel pisel pisel pad sclkb open mrst pisel pisel master slave slsi[7:1] 1 slsoandi[7:0] 0 pad slsx 8 8 sclkg slsigx 8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-32 v1.1, 2011-03 sscg, v1.7 the pisel register of the sscg0 select the particular output used by the ssc in an application which is to be monitored. on the other hand, the pisel registers of the ssc0 selects the inputs of the ssc module which are used in the application. 22.4.3 on-chip connections this section describes the on-chip connections of the ssc0/sscg0 modules. dma requests the sscg does not have its own dma requests. it is always served in parallel by the ssc requests. 22.4.3.1 receive input selection the mrstg inputs (master receive) of the ssc guardian module are mapped to some pins where the mtsr (master transmit) outputs of the corresponding ssc are connected. the alternative inputs a/b of each mrstg are selected via the corresponding pisel register of the ssc guardian. the pisel register of the sscg is normally programmed in parallel with the pisel register of the ssc, but it can be reprogammed afterwards, if needed. table 22-3 receive input selection receive input connected to selected by sscg0_mrstg0 (a/b) p10.1 sscg0_pisel.mris = x b sscg1_mrstg1 (a/b) p6.4 sscg1_pisel.mris = x b sscg2_mrstg2a sscg2_mrstg2b p4.1 p18.1 sscg2_pisel.mris = 0 b sscg2_pisel.mris = 1 b sscg3_mrstg3a sscg3_mrstg3b 0 p7.1 sscg3_pisel.mris = 0 b sscg3_pisel.mris = 1 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-33 v1.1, 2011-03 sscg, v1.7 22.4.4 ssc0/ssc1 module related external registers figure 22-7 summarizes the module-related external registers which are required for ssc0/ssc1 programming (see also figure 22-5 for the module kernel specific registers). figure 22-7 ssc0/ssc1 implementation-spe cific special function registers sscg_ext_regs.vsd sscg0_clc sscg1_clc sscg 0 _ tsrc sscg 0 _ rsrc sscg 0 _ esrc sscg 1 _ tsrc sscg 1 _ rsrc sscg 1 _ esrc clock control registers interrupt registers port registers sscg2_clc sscg3_clc none sscg0_gsrc sscg1_gsrc sscg0_fdr sscg1_fdr sscg2_fdr sscg3_fdr sscg2_gsrc sscg3_gsrc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-34 v1.1, 2011-03 sscg, v1.7 22.4.4.1 clock control each sscg module has two clock signals: ? f clc0 this is the module clock that is used inside the ssc kernel for control purposes such as clocking of control logic and register operations. the frequency of f clc0 and f clc1 is always identical to the system clock frequency f fpi . the clock control registers ssc0_clc and ssc1_clc make it possible to enable/disable f clc0 and f clc1 under certain conditions. ? f sscg0 this clock is the module clock that is used in the sscg as input clock of the baud rat e generator, which fin ally de t ermines the baud rate of the serial data. the fractional divider registers sscg0_fdr and sscg1_fdr control the frequency of f sscg0 and f ssc1 and make it possible to enable/disable it independently of f clc0 and f clc1 . the baud rate timer reload register sscg0_br and sscg1_br define serial data baud rate dependent from the frequency of f sscg0 and f sscg1 . figure 22-8 ssc clock generation output signal can_int_o15 of the multican module can be used for external clock enable control of the fractional divider. mca06227_sscg_1.vsd clock control register ssc0_clc f clc0 ssc0 clock generation f ssc0 f fpi fractional divider register ssc0_fdr f clcg0 sscg0 clock generation f sscg0 ssc0 module kernel baud rate generator ssc0_br sscg0 module kernel baud rate generator sscg0_br multican module int_o15 clock control register sscg0_clc fractional divider register sscg0_fdr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-35 v1.1, 2011-03 sscg, v1.7 the following formulas define the frequency of f ssc0 or f ssc1 (22.1) (22.2) note: in ssc master mode, the maximu m shift clock frequency is f sscx /2. in ssc slave mode, the maximum shift clock frequency is f sscx /4. combined with the formulas of the baud rate generator and the fractional divider, the resulting serial data baud rate is defined by: (22.3) (22.4) note: equation (22.1) and equation (22.3) apply to normal divider mode of the fractional divider (fdr.dm = 01 b ). equation (22.2) and equation (22.4) apply to fractional divider mode (fdr.dm = 10 b ). f sscx f fpi 1 n -- - with n = 1024 - fdr.step = f sscx f fpi n 1024 ------------ - with n = 0-1023 = baud rate ssc f fpi 2 br.br_value 1 + () 1024 - fdr.step () ---------------------------------------------------------------------------------------------------------------------------- - = baud rate ssc f fpi fdr.step 2 br.br_value 1 + () 1024 ------------------------------------------------------------------------------------ - with fdr.step = 0-1023 = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-36 v1.1, 2011-03 sscg, v1.7 clock control register the clock control register sscg0_clc makes it possible to control (enable/disable) the clock signal f clc0 under certain conditions. each ssc has its own clock control register. note: after a hardware reset operation, the f clcx clocks are disabled, and therefore the ssc modules are disabled (diss set) also. clc clock control register (00 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we e dis sp en dis s dis r r rwwrwrw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the module. diss 1r module disable status bit bit indicates the current status of the module. spen 2rw module suspend enable for ocds used to enable the suspend mode. edis 3rw sleep mode en able control used to control module?s sleep mode. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. fsoe 5rw fast switch off enable used to switch off fast clock in suspend mode. 0 [31:6] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-37 v1.1, 2011-03 sscg, v1.7 fractional divider register the fractional divider registers sscg 0_fdr and sscg1_fdr control the clock rate of the shift clock f sscg0 and f sscg1 . each sscg has its own fractional divider register. fdr fractional divider register (0c h ) reset value: 1000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dis clk en hw sus req sus ack 0result rwh rw rh rh r rh 1514131211109876543210 dm sc sm fdis step rw rw rw rw rw field bits type description step [9:0] rw step value reload or addition value for result. fdis 10 rw freeze disable this bit controls the freeze function for this module. 0 b module operates on co rrected clock, with reduced modulation jitter. 1 b module operates on uncorrected clock, with full modulation jitter. sm 11 rw suspend mode sm selects between granted or immediate suspend mode. sc [13:12] rw suspend control this bit field determines the behavior of the fractional divider in suspend mode. dm [15:14] rw divider mode this bit field selects normal divider mode, fractional divider mode, and off-state. result [25:16] rh result value bit field for the addition result. susack 28 rh suspend mode acknowledge indicates state of spndack signal. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-38 v1.1, 2011-03 sscg, v1.7 susreq 29 rh suspend mode request indicates state of spnd signal. enhw 30 rw enable hardware clock control controls operation of ecen input and disclk bit. disclk 31 rwh disable clock hardware-controlled disable for f out signal. 0 [27:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-39 v1.1, 2011-03 sscg, v1.7 22.4.4.2 interrupt control registers the ssc service request control registers ar e removed from the guardian module. their read value is constant ffff ffff h . there is a dedicated guardian service request register gsrc. gsrc guardian interrupt service request control register (1fc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-40 v1.1, 2011-03 sscg, v1.7 22.4.5 sscg address map an absolute register address is given by th e offset address of the register (given in table 22-2 ) plus the module base address (given in table 22-1 ). sscg has two chip-selects, one common with the ssc module, and one common and dedicated at the same time, or-ed inside the module to select the address decoder. additionally, the read signal is combined with the common chip select to suppres a read access parallel to the ssc re ad access. the common interrupt registers can be read as ffff ffff h , but they are not functionally available. write access has no effect and does not cause a bus error. figure 22-9 ssc and sscg address map table 22-4 sscg address overview module base address end address note sscg0 f031 0000 h f031 00ff h shared with ssc0 sscg1 f031 0100 h f031 01ff h shared with ssc1 sscg2 f031 0200 h f031 02ff h shared with ssc2 sscg3 f031 0300 h f031 03ff h shared with ssc3 sscg0 f031 0800 h f031 09ff h dedicated sscg1 f031 0a00 h f031 0bff h dedicated sscg2 f031 0c00 f031 0dff dedicated sscg3 f031 0e00 f031 0fff dedicated ssc0 ssc1 ssc2 ssc3 sscg0 address map ssc0 ssc1 sscg0 sscg1 ssc2 ssc3 sscg2 sscg3 f031 0000 h f031 0100 h f031 0200 h f031 0300 h f031 0800 h f031 0a00 h f031 0c00 h f031 0e00 h sscg1 sscg2 sscg3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-41 v1.1, 2011-03 sscg, v1.7 table 22-5 address maps of sscgx, x = 0 to 3 short name description address offset access mode reset value read write address location shared with ssc0, writable in user and supervisor mode sscgx_clc sscgx clock control register 000 h u, sv sv, e 0000 0003 h sscgx_pisel sscgx port input select register 004 h u, sv u, sv 0000 0000 h sscgx_id sscgx module identification register 008 h u, sv be 0085 c0xx h sscgx_fdr sscgx fractional divider register 00c h u, sv sv, e 1000 0000 h sscgx_con sscgx control register 010 h u, sv u, sv 0000 0000 h sscgx_br sscgx baud rate timer reload reg. 014 h u, sv u, sv 0000 0000 h sscgx_ssoc sscgx slave select output control reg 018 h u, sv u, sv 0000 0000 h sscgx_ssotc slave select output timing control reg. 01c h u, sv u, sv 0000 0000 h sscgx_tb sscgx transmit buffer register 020 h u, sv u, sv 0000 0000 h sscgx_rb sscgx receive buffer register 024 h u, sv u, sv 0000 0000 h sscgx_stat sscgx status register 028 h u, sv u, sv 0000 0000 h sscgx_efm sscgx error flag modification register 02c h u, sv u, sv 0000 0000 h ? reserved 030 h - 0f0 h be be ? sscgx_tsrc transmit int. service req. control reg. 0f4 h u, sv nbe ffff ffff h sscgx_rsrc receive int. service req. control reg. 0f8 h u, sv nbe ffff ffff h sscgx_esrc error int. service req. control reg. 0fc h u, sv nbe ffff ffff h address location dedicated to sscgx, writable only in supervisor mode sscgx_tb1 sscgx transmit buffer 1 100 h u, sv sv 0000 0000 h sscgx_tb1snap sscgx transmit buffer 1 snapshot 104 h u, sv sv 0000 0000 h sscgx_rbsnap sscgx receive buffer snapshot 108 h u, sv sv 0000 0000 h sscgx_gstat sscgx guardian status register 10c h u, sv sv 0000 0000 h sscgx_gefm sscgx guardian error flag modification 110 h u, sv sv 0000 0000 h sscgx_gen sscgx enable register 114 h u, sv sv 0000 0100 h ? reserved 118 h - 1ec h be be ? sscgx_gsrc guardian int. service req. control reg. 1fc h sv sv 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 synchronous serial interface guardian (sscg) users manual 22-42 v1.1, 2011-03 sscg, v1.7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-1 v1.1, 2011-03 msc, v1.40 23 micro second channel (msc) this chapter describes the micro second channel interface s, msc0 and msc1, of the TC1798. it contains the following sections: ? functional description of the msc kernel (see page 23-3 ) ? msc kernel register descriptions (see page 23-36 ) ? TC1798 implementation-specific details and registers of the msc module (port connections and control, interrupt control, address decoding, and clock control, see page 23-62 ) note: the msc kernel register names described in section 23.2 are also referenced in the TC1798 users manual by the mo dule name prefix ?msc0_? for the msc0 module and by ?msc1_? for the msc1 module. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-2 v1.1, 2011-03 msc, v1.40 msc applications the msc is a serial interface that is especially designed to connect external power devices to the TC1798. the serial data transmission capability minimize s the number of pins required to connect such external power devices. parallel data information (coming from the timer units) or command information is sent out to the power device via a high- speed synchronous serial data stream (downstream channel). the msc receives data and status back from the power device via a low-speed asynchronous serial data stream (upstream channel). figure 23-1 shows a typical TC1798 application in which an msc interface controls two power devices. output data is provided by the gpta module. figure 23-1 msc to external power device connection some applications are: ? control of the external power switching unit via the downstream channel ? receiving information back from power switching unit ? serial connections of the TC1798 to other peripheral devices mca06228_mod msc gpta module data power device 1 downstream channel upstream channel data clock select select data power device 2 16 16 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-3 v1.1, 2011-03 msc, v1.40 23.1 msc kernel description this section describes the functionality of the msc kernel. 23.1.1 overview the msc interface provides a serial communication link typically used to connect power switches or other peripheral devices. the serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel. figure 23-2 shows a global view of the msc interface signals. figure 23-2 general block diag ram of the msc interface the downstream and upstream channels of the msc module communicate with the external world via nine i/o lines. eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). one out of eight input lines sdi[7:0] is used as serial data input signal for the upstream channel. the source of the serial data to be transmitted by the downstream channel can be msc register contents or data that is provided at the altinl/altinh input lines. these input lines are typically connected to other on-chip peripheral units (for example with a timer unit like the gpta). an emergency stop input signal makes it possible to set bits of the serial data stream to dedicated values in emergency case. 4 msc module (kernel) mcb06059 fcln clock control address decoder interrupt control f msc f clc downstream channel upstream channel fclp en0 en1 en2 en3 son sop sdi[7: 0] sr[3:0] emgstopmsc altinl[15:0] altinh[15:0] to dma 16 16 8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-4 v1.1, 2011-03 msc, v1.40 clock control, address decoding, and interrupt service request control are managed outside the msc module kernel. service reques t outputs are able to trigger an interrupt or a dma request. features ? fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses ? high-speed synchronous serial transmission on downstream channel ? serial output clock frequency: f fcl = f msc /2 ( f mscmax = 110 mhz) ? fractional clock divider for precise frequency control of serial clock f msc ? command, data, and passive frame types ? start of serial frame: software-controlled, timer-controlled, or free-running ? transmission with or without sel bit ? flexible chip select generation indicates status during serial frame transmission ? emergency stop without cpu intervention ? low-speed asynchronous serial reception on upstream channel ? baud rate: f msc divided by 4, 8, 16, 32, 64, 128, or 256 ( f mscmax = 110 mhz) ? standard asynchronous serial frames ? programmable upstream data frame length (16 or 12 bits) ? parity error checker ? 8-to-1 input multiplexer for sdi lines ? built-in spike filter on sdi lines ? selectable pin types of downstream channel interface: four lvds differential output drivers or four digital gpio pins www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-5 v1.1, 2011-03 msc, v1.40 23.1.2 downstream channel the downstream channel performs a high-s peed synchronous serial transmission of data to external devices. its 32-bit shift register is divided into two 16-bit parts, srl and srh. each bit of srl and srh can be selected to be delivered by the downstream data register dd, by the downstream command register dc, or by two 16-bit wide input signal buses altinl and altinh. figure 23-3 is a diagram of the msc downstream channel. figure 23-3 downstream channel block diagram the enable signals enl, enh, and enc indicate certain phases of the serial transmission in relation to the serial clock fcl. in the i/o control logic, these signals can be combined to four enable/select outputs en[3:0]. for supporting differential output drivers, the serial clock output fcl and the serial data output so are available in both polarities, indicated by the signal name suffix ?p? and ?n?. 32-bit shift register srh (16-bit) srl (16-bit) mux mux 15 downstream channel control edi eci tfi en[3: 0] enl enh son so fcl e mgstopmsc altinh[15:0] altinl[15:0] msc downstream channel f msc mcb06229 interrupts sop fcln fclp enc i/o control 31 16 0 downstream data register dd 31 15 16 0 downstream command register dc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-6 v1.1, 2011-03 msc, v1.40 the emergency stop input line emgstopmsc is used to indicate an emergency stop condition of a power device. in emergency case, shift register bits can be loaded bit-wise from the downstream data register instead from the altinl and altinh buses. 23.1.2.1 frame formats and definitions this section describes the frame formats and definitions of the msc. basic definitions figure 23-4 shows the layout and definitions of a downstream frame. a downstream frame is composed of an active phase and a passive phase. during the active phase, data transmission takes place and during the passive phase no data is transmitted at so. the active phase is split into two part s: the srl active phase in which the content of the shift register low part srl is transmitted, and the srh active phase in which the content of the shift register high part srh is transmitted. at the beginning of the srl and srh active phase, a selection bit (sell) can be optionally inserted into the serial data stream. in the frame shown in figure 23-4 , sell is generated at the beginning of the srl active phase (not for the srh active phase). the least significant bits of srl and srh are sent out first. figure 23-4 downstream channel frame the msc downstream channel uses three types of frame formats for operation: ? command frames, indicated by sell = 1 ? data frames, indicated by sell = 0 or sell bit insertion disabled ? passive time frame, indicated by enl = enh = 0 selection bit mct06230 active phase srl.0 srl.n srh.m srl active phase srh active phase passive phase srl.1 srh.1 t fcl min. 2 t fcl srh.0 sell downstream frame f cl s o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-7 v1.1, 2011-03 msc, v1.40 command frames a command frame has two active phase parts , srl active phase and srh active phase. the command frame always starts with a high-level selection bit, independently whether the selection bit insertion (as defined by bit dsc.ensell) is enabled or not. the number of the bits transmitted during srl and srh active phases (except the selection bit) is defined by bit field dsc.nbc. srl and srh are combined to a 32-bit value whose length can be selected from 0 up to 32 bits. in other words, whenever bits of srh are transmitted, they are always preceded by the transmission of the complete srl content. during the active phase of a command frame, the enable output signal enc becomes active. the enable output signals enl and enh remain inactive. the passive phase of a command frame always has a fixed length of 2 t fcl . the diagram shown in figure 23-5 assumes that the fcl clock is only generated during the active phase of the command frame (ocr.clkctrl = 0). figure 23-5 command frame layout selection bit mct0623 1 length defined by dsc.nbc srl.0 srl.15 srh.15 srl active phase passive phase srl.1 srh.1 f cl s o e nc t fcl srh.0 1 command frame srh active phase 2 t fcl active phase 1) interrupt generation possible 1) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-8 v1.1, 2011-03 msc, v1.40 table 23-1 shows the programming of the bits to be transmitted and the resulting length of the complete command frame. table 23-1 command frame length dsc.nbc srl/srh bits th at are transmitted in active phase command frame length in t fcl periods 000000 b no bit shifted out 1+0+2=3 000001 b srl[0] shifted out 1 + 1 + 2 = 4 000010 b srl[1:0] shifted out 1 + 2 + 2 = 5 000011 b srl[2:0] shifted out 1 + 3 + 2 = 6 ?? ? 001111 b srl[14:0] shifted out 1 + 15 + 2 = 18 010000 b srl[15:0] shifted out 1 + 16 + 2 = 19 010001 b srl[15:0] and srh[0] shifted out 1 + 17 + 2 = 20 010010 b srl[15:0] and srh[1:0] shifted out 1 + 18 + 2 = 21 010011 b srl[15:0] and srh[2:0] shifted out 1 + 19 + 2 = 22 ?? ? 011111 b srl[15:0] and srh[14:0] shifted out 1 + 31 + 2 = 34 100000 b srl[15:0] and srh[15:0] shifted out 1 + 32 + 2 = 35 other nbc combinations reserved; do not use these bit combinations. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-9 v1.1, 2011-03 msc, v1.40 data frames a data frame has two active phase parts, srl active phase and srh active phase. the number of bits that are transmitted can be programmed separately for each of these two phases. bit field dsc.ndbl determines the number of srl bits that are transmitted during the srl active phase and dsc.ndbh determines the number of srh bits that are transmitted during the srh active phase. srl and srh active phases can start with a low-level selection bit when enabled by bits dsc.ensell or dsc.enselh. during the srl active phase of a data frame, the enable output signal enl becomes active and during the srh active phase of a data frame, the enable output signal enh becomes active. the enable output signal enc remains inactive. the length of the data frame?s passive phase is variable and is defined by bit field dsc.ppd. it can be within a range of 2 t fcl up to 31 t fcl . the diagram shown in figure 23-6 assumes that the fcl clock is only generated during the active phase of the data frame (ocr.clkctrl = 0). table 23-2 , table 23-3 , and table 23-4 show the definitions of the five data frame parameters that determine the layout of the data frame. figure 23-6 data frame layout mct06232 srl.0 srl.n passive phase f cl s o e nh e nl t fcl srh.0 0 data frame active phase length defined by dsc.ppd 0srl.m length defined by dsc.ndbh length defined by dsc.ndbl srl active phase srh active phase 1) interrupt generation possible 1) 1) selection bit selection bit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-10 v1.1, 2011-03 msc, v1.40 table 23-2 data frame selection bit parameters dsc.ensell selection bit d sc.enselh selection bit 0 no selection bit inserted at the beginning of the srl active phase 0 no selection bit inserted at the beginning of the srh active phase 1 a low level selection bit is inserted at the beginning of the srl active phase 1 a low level selection bit is inserted at the beginning of the srh active phase table 23-3 data frame srl/srh length parameters dsc.ndbl srl bits transmitted in srl active phase dsc.ndbh srh bits transmitted in srh active phase 00000 b no srl bit transmitted 00000 b no srh bit transmitted 00001 b srl[0] 00001 b srhl[0] 00010 b srl[1:0] 00010 b srh[1:0] 00011 b srl[2:0] 00011 b srh[2:0] ?? ?? 01111 b srl[14:0] 01111 b srh[14:0] 10000 b srl[15:0] 10000 b srh[15:0] other bit combinations reserved; do not use these bit combinations. other bit combinations reserved; do not use these bit combinations. table 23-4 data frame passive phase length dsc.ppd passive phase length 00000 b 2 t fcl 00001 b 2 t fcl 00010 b 2 t fcl 00011 b 3 t fcl ?? 01110 b 30 t fcl 01111 b 31 t fcl www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-11 v1.1, 2011-03 msc, v1.40 the following formula determines the number of t fcl cycles of a data frame: all parameters (bits and bit fields) are located in register dsc. (23.1) note that in the formula above, ppd must be set to 2 when dsc.ppd 00010 b . passive time frames a passive time frame has the length defined by the five data frame parameters according equation (23.1) . they are generated only in data repetition mode. under special conditions (command frame insertion), pa ssive time frames can be shortened (see figure 23-9 ). during passive time frames, the data output so have to be considered as invalid at the receiving device and the clock output fcl may toggle or not (as selected by bit ocr.clkctrl). the enl and enh enable signals remain at low level during a passive time frame. number of cycles = ensell + ndbl + enselh + ndbh + ppd www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-12 v1.1, 2011-03 msc, v1.40 23.1.2.2 shift register operation this section describes the srl and srh shift register loading. srl shift register loading during the srl/srh shift register load operation at the beginning of each downstream frame transmission, several parameters determine which information is loaded into the bits of the shift register. figure 23-7 shows the logic that is implemented for the srl shift register loading operation. the logic for the srh shift register loading operation is equivalent to the one for the srl register. its differences in data sources and register controls are described later in this section. figure 23-7 srl shift register data loading control mca0623 3 altinl[x] to srl bit x slx dsdsl ddh 32 15 16 0 ddl[x] ddl downstream data register dd ddh[x] dch 32 15 16 0 x = 0-15 dcl downstream command register dc dcl[x] dch[x] emgstopmsc cp dsc 0 1 1 0 & enlx esr x = 0-15 cp = 0: load for data frame cp = 1: load for command fram e 00 10 11 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-13 v1.1, 2011-03 msc, v1.40 four data sources can be selected for each srl bit by using several control bits and one control signal: ? altinl input line (non-inverted) ? altinl input line (inverted) ? bit of dd.ddl (downstream data register) ? bit of dc.dcl (downstream control register) when srl is loaded for data frame transmission (dsc.cp = 0), bit fields dsdsl.slx determine bit-wise which data is loaded into srl bit x. the data source selection as controlled by dsdsl.slx will only be effect ive when emgstopmsc is inactive (at low level). when emgstopmsc = 1 (active) during the load operation, all srl[x] bits that are enabled for the emergency stop feature (bit esr.enlx = 1) are loaded directly with the corresponding bit ddl[x] of the downstream data register dd. when srl is loaded for command frame transmission (dsc.cp = 1), always the lower 16-bit part dcl of the downstream control register is loaded completely into srl. table 23-5 summarizes all srl data source selection capabilities (x = 0-15). srh shift register loading the srh shift register load operation is equivalent to the srl shift register load operation. the following differences must be taken into account for srh shift register loading: ? input lines altinh are connected instead of altinl input lines. ? dsdsh register bits control data source selection instead of dsdsl register. ? emergency stop is enabled by esr.enhx bits instead of esr.enlx bits. ? bits of the downstream data register high part ddh are selected instead of ddl. ? downstream control register high part dch is selected instead of dcl. table 23-5 srl data source selection capabilities dsc. cp dsdsl. slx esr. enlx emgstopmsc selection 000 b 0 ? bit dd.ddl[x] is loaded into srl[x]. 01 b reserved. 10 b state of altinl[x] input is loaded into srl[x]. 11 b inverted state of altinl[x] input is loaded into srl[x]. xx b 1 1 bit dd.ddl[x] is loaded into srl[x]. 1xx b x x bit fields dcl and dch are completely loaded into srl and srh, respectively. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-14 v1.1, 2011-03 msc, v1.40 23.1.2.3 transmission modes the downstream channel of the msc makes it possible to select between two transmission modes: ? triggered mode, selected by dsc.tm = 0, or ? data repetition mode, selected by dsc.tm = 1 triggered mode in triggered mode, command frames or data frames are sent out as a result of a software event. when a frame transmission has been finished and no further frame transmission has been requested, the downstream channel returns to idle state and waits for the next frame transmission to be triggered by software. when the downstream command register dc is written, the command pending bit dsc.cp becomes set and a command frame will be immediately started and sent out if the downstream channel is idle. if a data or command frame is currently processed and output, the command frame transmission is delayed, and started when the active downstream frame has been finished. the command pending bit dsc.cp becomes cleared by hardware when the first bi t of the command frame is sent out. if the downstream channel is idle and the dat a pending bit dsc.dp is set by writing bit isc.sdp with 1, a data frame will be immediately started and sent out if the downstream channel is idle. if a data frame or a command frame is currently processed and output, the data frame transmission is delayed and started when the active downstream frame has been finished. the data pending bit dsc.dp becomes cleared by hardware when the first bit of the data frame is sent out. a command frame always has priority over the da ta frame. this means that if both frame pending bits are set (dsc.dp = dsc.cp = 1), the command frame will always be sent first. therefore, a p ending data frame transmission w ill be delayed as long as no further command frame transmission is running or requested. figure 23-8 is a flow diagram of the triggered mode. this diagram especially shows the behavior of the data and command pending bits dsc.dp and dsc.cp. if both frame pending bits are set (dsc.dp = dsc.cp = 1), the command frame will always be sent first, followed by the data frame (assuming no further command frame has been requested). the type of the active frame that is currently processed and output is indicated by two status flags: dss.dfa is set during a data frame transmission and dss.cfa is set during a command frame transmission. further, the downstream counter dss.dc indicates the number of shift clock periods that have been elapsed since the start of the current frame. in triggered mode, the shift register loading event as described in section 23.1.2.2 occurs just before a command or data frame transmission is started. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-15 v1.1, 2011-03 msc, v1.40 figure 23-8 triggered mode flow diagram data repeti tion mode in data repetition mode, data frames are sent out continuously without any software interaction. in the time gap between two consecutive data frames, passive time frames can be inserted. the number of passive time frames to be inserted (0 to 15) is defined by bit field dss.nptf. the duration of data frame ( t df ) and passive time frames ( t ptf ) is determined by the five data frame parameters (see equation (23.1) ). these parameters determine time reference points (trp) at whic h a data or passive time frames is started (see diagram a in figure 23-9 ). the automatic data frame generation is cont rolled by the data pending bit dsc.dp. this bit is set near the end of the last transmitted passive time frame. at the next trp, a data frame is started (if no command frame has been requested) and dsc.dp is cleared again by hardware after the data frame ha s been started. data frames are always aligned to time reference points. this means they always start at a trp. passive time frames can be shortened. this is especi ally the case when command frames are inserted. continuous data frame transmission can be interrupted by insertion of command frames. command frames are initiated by software. when the downstream control register dsc is written, the command pending bit dsc.cp is set by hardware. cp = 1 indicates that the msc starts a command frame at the next trp, independently of whether a data mca06234 starting triggered mode (writing dsc.tm=0) dsc.cp = 1? dsc.dp = 1? no yes load shift register for command frame transmission start command frame dsc.cp = 0 1) load shift register for data frame transmission start data frame dsc.dp = 0 1) no yes 1) done by hardware www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-16 v1.1, 2011-03 msc, v1.40 frame (indicated by dsc.dp = 1) or passive time frame should be started with the next trp. this means also that command frames are always aligned to time reference points. figure 23-9 data repetiti on mode frame examples with dss.nptf = 0011 b diagrams b to f in figure 23-9 show the command frame insertion in data repetition mode. in diagram b, a command frame has been requested during the first passive time frame after the data frame, and is inserted at the next trp. in diagrams c and d, a command frame has been requested during the second passive time frame, and is inserted at the time reference point of the last nominal passive time frame. when the command frame and data frame is not of the same length (this is the case in diagram b to f), a shortened passive time frame is inserted until the next trp is reached. this ensures that the next data or normal passive time frame is again aligned to a trp. figure 23-10 is a flow diagram of the data repetition mode. this diagram especially shows the behavior of the data and command pending bits dsc.dp and dsc.cp. if both frame pending bits are set (dsc.dp = dsc. cp = 1), the command frame will always be t ptf t df 1) 1) 1) 1) 1) c d e f a mct0623 5 df ptf cf ptf ptf ptf df ptf = passive time frame df = data frame cf = command frame trp = time reference point b ptf ptf ptf df ptf df ptf ptf ptf df ptf ptf ptf df ptf cf df ptf ptf ptf df ptf ptf df ptf df ptf ptf ptf ptf df ptf ptf ptf cf p tf df ptf df ptf ptf ptf df ptf ptf ptf cf df ptf df ptf ptf ptf df ptf ptf ptf cf p tf ptf df trp trp trp trp trp trp trp trp trp trp trp tr p t cf 1) these passive time frames are shortened www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-17 v1.1, 2011-03 msc, v1.40 sent first, followed by the data frame when the next trp is reached (assuming no further command frame has been requested). when the last passive frame is transmitted, dsc.dp becomes set by hardware. this triggers the start of a data frame when the next trp is reached. figure 23-10 data repetiti on mode flow diagram the type of the active frame (data or comm and frame) that is currently processed and output is indicated by two status flags: dss.dfa is set during a data frame transmission and dss.cfa is set during a command frame transmission. further, the downstream counter dss.dc indicates the number of shift clock periods that have been elapsed since the start of the current data, command, or passive time frame. mca06236 starting data repetition mode (writing dsc.tm = 1) dsc.cp = 1? yes no trp reached? dsc.dp = 1? start passive time frame no yes load shift register for command frame transmission start command frame cmd. frame finished? no dsc.cp = 0 1) load shift register for data frame transmission start data frame dsc.dp = 0 1) last passive time frame? no dsc.dp = 1 1) yes yes no yes start shortened passive time frame 1) done by hardware www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-18 v1.1, 2011-03 msc, v1.40 as in triggered mode, the shift register loading event as described in section 23.1.2.2 occurs in data repetition mode just before a trp, this means shortly before a command or data frame transmission is started. passive frame counter in data repetition mode in data repetition mode, a passive time frame counter dss.pfc indicates how many time frames have been already transmitted af ter the last regular data frame occurrence. the passive time frame counter counts up from 0000 b to the value which has been written into bit field dss.nptf (number of passive time frames). dss.pfc = 0000 b indicates that a data frame is requested for transmission. figure 23-11 passive frame counter operation (with dss.nptf = 0101 b ) mct0623 7 df ptf ptf ptf ptf df ptf = passive time frame df = data frame trp = time reference point ptf ptf trp trp trp trp trp trp trp trp trp ptf tr p 0000 b 0001 b 0010 b 0011 b 0100 b 0101 b 0000 b 0101 b 0001 b t ransmitted f rames p assive frame c ounter d ss.pfc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-19 v1.1, 2011-03 msc, v1.40 23.1.2.4 downstream counter and enable signals during downstream channel operation, a 7- bit downstream counter dss.dc is counting fcl shift clock periods. with the loading of the shift register, the downstream counter is reset to 00 h and started for counting up to the end of the downstream frame (end of passive phase). in triggered mode, the downstream counter stops counting at the end of the passive phase and waits until a new downstream frame is started. in repetition mode, the downstream counter does not stop at the end of the passive phase but is reset and starts counting up again with the next frame, independently whether a data frame, command frame, or passive time frame is started as next frame. figure 23-12 shows an example of downstream channel data frame transmission. in this example, the selection bit for the srl active frame is enabled (ensell = 1), and the selection bit for the srh active frame is disabled (enselh = 0). with loading of the shift register srl/srh, the downstream counter is reset and then starts counting up with each fcl clock until the end of the passive phase. enl is set to high level at the beginning of the srl active frame selection bit. figure 23-12 shift clock co unting: data frame with ensell = 1 and enselh = 0 mct06238 passive phase e nh t fcl downstream frame srl active phase srh active phase 1 0 2 m+1 e nl f cl s tate of d ss.dc srl.0 0 srl.m m s o srh.0 m+2 m+3 dc max srl/srh loading srl.1 3 srh.n srh.1 m+4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-20 v1.1, 2011-03 msc, v1.40 when the selection bit for the srl active frame is disabled (ensell = 0, see figure 23-13 ), the loading of the shift register srl/srh (and reset of the downstream counter) occurs one fcl clock cycle before the first data bit srl.0 is output. enl is set to high level with the beginning of the first data bit srl.0. figure 23-13 shift clock co unting: data frame with ensell = 0 and enselh = 0 23.1.2.5 baud rate the baud rate of the downstream channel?s serial transmission is defined by the frequency of the serial clock fcl, and is always f msc /2. the f msc generation is device specific and depends on the implementatio n of the msc module. the TC1798 specific clock generation is described on page 23-65 . 23.1.2.6 abort of frames only a reset condition of the device can abort a current transmission. the msc module does not start a new frame transmission when the downstream channel becomes disabled, the suspend mode is requested, or the sleep mode is entered. if one of these three conditions becomes active during a running frame transmission, the frame transmission is completely finished before the requested abort state is entered. note that in this case no time frame finished interrupt is generated any more. mct06239 passive phase t fcl downstream frame srl active phase srh active phase 1 0 2 m+1 srl.0 srl.m m srh.0 m+2 m+3 dc max srl/srh loading srl.1 3 srh.n srh.1 m+4 e nh e nl f cl s tate of d ss.dc s o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-21 v1.1, 2011-03 msc, v1.40 23.1.3 upstream channel the msc upstream channel is an asynchronous serial receiver based on the standard asynchronous data transfer protocol. it is dedicated to receive a serial data stream from a peripheral device via its serial data input sdi, using two specific data frame formats. figure 23-14 is a block diagram of the msc upstream channel. figure 23-14 upstream channel block diagram the incoming data at si is sampled after it has been filtered for spikes. the detected logic states of the serial input are clocked into a shift register. after the complete reception of the serial data frame, the content of the shift register is transferred into one of the four data registers, and an interrupt can be generated optionally. the reception baud rate is directly coupled to the module clock f msc , and can be within a range of f msc /4 up to f msc /256. upstream data registers serial receive buffer upstream channel control rdi sdi[7: 0] f msc mcb06240 samp- ling ud0 ud1 ud2 ud3 shift register spike filter si input control interrupt sdi m u x www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-22 v1.1, 2011-03 msc, v1.40 23.1.3.1 data frames the asynchronous data frames used by the up stream channel include four basic parts: 1. one start bit, always at low level 2. an 8-bit data field d[7:0] with lsb first 3. an optional 4-bit address field a[3:0] with lsb first 4. one parity bit and two stop bits, that are always at high level as shown in figure 23-15 , the 16-bit upstream data frame includes an additional 4-bit address field. the upstream frame type is selected by bit usr.uft. ? usr.uft = 0: 12-bit upstream data frame selected ? usr.uft = 1: 16-bit upstream data frame with 4-bit address field selected figure 23-15 upstream channel frame types 23.1.3.2 parity checking the incoming parity bit of the data frames can be checked by the upstream channel. when a parity error is detected, the parity error flag perr in the related upstream data register udx is set. note that a setting of the parity error flag perr does not generate an interrupt. the perr bits must be checked by software. the udx registers also store the parity bit of the incoming data frame (udx .p) and the parity bit that is generated internally (udx.ipf). bit usr.pctr determines the parity mode, ev en or odd, that is selected for parity checking. with usr.pctr = 0, even parity mode is selected. even parity means that the parity bit is set on an odd number of 1s in the data field (12-bit upstream data frame) or in the address plus data field (16-bit upstream data frame). with usr.pctr = 1, odd parity mode is selected. in odd parity mode, the parity bit is set on an even number of 1s of the related data. mct06241 d5 d0 lsb d3 d1 d2 d4 d7 msb d6 start bit parity bit stop bit stop bit 12-bit upstream data frame d5 d0 lsb d3 d1 d2 d4 d7 msb d6 start bit parity bit stop bit stop bit 8-bit data field 16-bit upstream data frame a0 lsb a3 msb a1 a2 4-bit address field 8-bit data field www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-23 v1.1, 2011-03 msc, v1.40 the parity checking logic in the upstream channel also controls whether start bit and the two stop bits of the upstream data frame are at correct logic level. if the start bit is not at low level and the two stop bits are not at high level at the end of the frame reception, the parity error flag udx.perr is set, too. 23.1.3.3 data reception the reception of the upstream frame is started with a falling edge (1-to-0 transition) on the si line. when the start bit is detected, serial reception is enabled and the receive circuit begins to sample the incoming serial data and to buffer it in the receive buffer. after the second stop bit has been detected, the content of the receive buffer is transferred to one of four upstream data registers udx. the receive circuit then waits for the next start bit (1-to-0 transition) at the si line. when the content of the receive buffer has been transferred to udx, the valid bit udx.v is set by hardware, and a receive interrupt can be generated. note: the si input line is the filter ed non-inverted (ocr.ilp = 0) or inverted (ocr.ilp = 1) sdi input signal. the si input signal selection is described on page 23-30 ). frame reception with address field frame reception for a 16-bit data frame (see figure 23-16 ) is selected by usr.uft = 1. when the content of the receive buffer has been received completely, it is transferred to one of the four udx registers. the two most significant address bits a[3:2] of the received 4-bit address field select the number x of register udx in which the received frame content is stored. register udx is loaded with the two least significant address bits a0 and a1 (udx.labf), the 8-bit data (udx.dat a), the received parity bit (udx.p), the calculated parity bit (udx.ipf), and the parit y checking result (udx.perr). finally, the valid bit udx.v is set to indicate that the udx register contains valid data. the current state of the frame reception is indicated by the content of an upstream counter that is readable via bit field usr. uc. the upstream counter is a 5-bit counter that counts the upstream frame bits during reception. as shown in figure 23-16 , the upstream counter is loaded with 10000 b at the detection of a start bit. it counts down and is again at 00000 b when the second stop bit has been detected and the frame reception is finished. the state of the serial input data line si is sampled in the middle of a bit cell and shifted into the receive buffer at the end of the bit cell. the frequency of the shift clock f shift depends the selected baud rate (see page 23-25 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-24 v1.1, 2011-03 msc, v1.40 figure 23-16 16-bit upstream reception data reception without address field frame reception for a 12-bit data frame is selected by usr.uft = 0. the reception scheme is comparable with that of the 16-bit data frame reception but there are a few differences: ? the upstream counter is initially loaded with 01100 b . ? the received frame content is always stored in register ud0. ? bit field ud0.labf is always loaded with 00 b when the frame is stored. mct06242 d0 d1 d7 d6 start p 16-bit upstream data frame a3 a2 stop stop 16 15 14 13 12 11 10 4 3 2 1 0 0 a1 5 sampling shifting a0 si receive enabled f br uc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-25 v1.1, 2011-03 msc, v1.40 23.1.3.4 baud rate the baud rate of the upstream channel is derived from the msc module clock f msc . figure 23-17 shows the configuration of the upstream channel clock circuitry. figure 23-17 upstream channel clock circuitry the serial data input si is evaluated with the baud rate clock f br in the middle of each bit cell, and latched in case of a data bit. the baud rate clock f br is derived from f msc by a programmable clock divider. the frequency of f br determines the width of a received bit cell and therefore the baud rate for the received data. the content of bit field usr.urr selects the baud rate according table 23-6 . the resulting baud rate formula is: (23.2) note: with the usr.urr = 000 b the upstream channel is disabled and data reception is not possible. table 23-6 upstream channel divide factor df selection & baud rate usr.urr divide factor df baud rate 000 b reception disabled ? 001 b 4 f msc /4 010 b 8 f msc /8 011 b 16 f msc /16 100 b 32 f msc /32 101 b 64 f msc /64 110 b 128 f msc /128 111 b 256 f msc /256 mca06243 programmable clock divider f br f msc urr usr receive buffer s i baud rate msc upstream channel f msc df ----------- = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-26 v1.1, 2011-03 msc, v1.40 the content of bit field usr.urr determines the operation of an internal sampling reload counter that is clocked with f msc . figure 23-18 shows the operation of the sampling counter at the beginning of an upstream frame with a divide factor df of 8 (usr.urr = 010 b is equal to df = 8) which mean s eight sampling clocks per each frame bit cell. when the upstream channel is in idle state, it waits for a falling edge (1-to-0 transition) at si. therefore, the sample counter starts counting up and is reset when the selected divide factor df as shown in table 23-6 is reached. in the middle of the sampling counter?s count range, the logic state at si is evaluated and, in case of a data bit, latched in the receive buffer?s shift register. with the reload of the sampling counter, the shift register is shifted by one bit position. figure 23-18 upstream channel sampling with urr = 010 b 23.1.3.5 spike filter the upstream channel input line sdi is sampled using a built-in spike filter with synchronization stage, both clocked with f msc . the spike filter is a chain of flip-flops with a majority decision logic (2 out of 3). a sampled value that is found at least twice in three samples is taken as data input value for si. 1 mct0624 4 start bit si reception enabled f br sampling counter d0 sampling shifting 0235 467 f msc 1 0235 467 d1 2 01 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-27 v1.1, 2011-03 msc, v1.40 23.1.4 i/o control the types of i/o control logic for the msc module i/o lines are shown in figure 23-19 . the downstream channel generates five output signals that control eight msc module outputs, split into four chip select outputs, two clock output s, and two serial data outputs. the upstream channel has one input signal. figure 23-19 i/o control the msc module i/o signals is controlled by bit fields that are located in the output control register ocr. 23.1.4.1 downstream ch annel output control as shown in figure 23-5 and figure 23-6 , the active phases during downstream channel operation are indicated by three enable signals: ? enl indicates the srl active phase of a data frame ? enh indicates the srh active phase of a data frame ? enc indicates the active phase of a command frame the chip select output control logic of the msc uses a signal compressing scheme (similar to the interrupt request compressing scheme in figure 23-27 ) that allows each of the three enable signals to be directed via a 2-bit selector to one of the four chip enable mca06245 downstream channel clock & data output control fclp fcln sop son fcl so en0 en1 en2 en3 chip select output control data input control sdi[7: 0] si upstream channel enl enh enc msc module www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-28 v1.1, 2011-03 msc, v1.40 outputs en[3:0]. this also makes it possible to connect more than one internal enable signal (enl, enh, enc) to one chip enable output enx. three bit fields in register ocr (csl, csh, and csc) determine which chip enable output becomes active on a valid internal enable signal. in the msc, enable signals are high-level active signals. if required in a specific application, all chip enable outputs enx can be assigned for low-level active polarity by setting bit ocr.cslp. figure 23-20 downstream channel: chip enable output control mca06246 csl ocr e nl csh ocr csc ocr en 0 e nh e nc 1 0 1 0 1 0 1 0 cslp ocr en 1 en 2 en 3 2 2 2 1 1 1 1 01 10 11 00 01 10 11 00 01 10 11 00 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-29 v1.1, 2011-03 msc, v1.40 at the msc downstream channel, the internal serial clock output fcl and data output line so are available outside the msc module as two signal pairs with inverted signal polarity, fclp/fcln and sop/son. both, clock and data outputs, are generated from the module internal signals fcl and so according to figure 23-21 . figure 23-21 downstream channel: clock and data output control with ocr.clp = 0, fclp has identical and fcln has inverted polarity compared to fcl. setting ocr.clp, exchanges the signal polarities of fclp and fcln. an equivalent control capability is available for the sop and son data outputs (controlled by ocr.slp). one additional control capability not shown in figure 23-21 is available for the fcl signal. with ocr.clkctrl = 1, the fc l clock signal will always be generated, independently whether a downstream frame is currently transmitted or not. if ocr.clkctrl = 0, fcl becomes only active during the active phases of data or command frames (not during passive time frames). mca06247 1 0 clp ocr f cl fcl p 1 0 fcl n 1 0 s o sop 1 0 son slp www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-30 v1.1, 2011-03 msc, v1.40 23.1.4.2 upstream channel as shown in figure 23-22 , the msc upstream channel can be connected to up to eight sdi[7:0] serial inputs. bit field ocr.sdisel selects one out of these input lines (input signal sdi). if ocr.ilp = 0, sdi is directly connected to the serial receive buffer input si. if ocr.ilp = 1, sdi is connected to input si via an inverter. figure 23-22 upstream channel serial data input control mca06248 ilp ocr 1 0 s i sdi sdi[7: 0] sdisel ocr 3 8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-31 v1.1, 2011-03 msc, v1.40 23.1.5 msc interrupts the msc module has four interrupt sources an d four service request outputs. a service request output is able to generate interrupts (controlled by a service request control register) or dma requests. the service re quest output assignment, interrupt or dma request, is specific for each microcontroller th at is using the msc. in this section, the term ?interrupt request? has the meaning of ?service request? that is able to handle interrupt or dma requests. each interrupt source is provided with a stat us flag, enable bit(s) with software set/clear capability, and an interrupt node pointer. an interrupt event, internally generated as a request pulse, is always stored in an interrupt status flag that is located in the interrupt status register isr. all interrupt status flag can be set or cleared individually by software via the interrupt set clear register isc. software-controlled interrupt generation can be initiated by setting the interrupt status flag of the corresponding interrupt. each interrupt source can be enabled or disabled individual ly. when an interrupt event is enabled, a 2-bit interrupt node pointer determines whic h of the service request outputs will be activated. table 23-7 shows the four msc interrupt sources. table 23-7 msc interrupts interrupt type generated by data frame interrupt downstream channel command frame interrupt time frame finished interrupt receive data interrupt upstream channel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-32 v1.1, 2011-03 msc, v1.40 23.1.5.1 data frame interrupt a data frame interrupt can be generated when either the first or the last data bit of the downstream channel is shifted out and becomes available at the so output line (see also figure 23-6 ). bit icr.ediei selects which case is selected. note: if icr.edie = 10 b , an interrupt at the first data bit is only generated if dsc.ndbl is not equal 00000 b . this means, at least one srl bit must be shifted out for the first data bit shifted interrupt to become active. figure 23-23 data frame interrupt control 23.1.5.2 command frame interrupt a command frame interrupt can be generated at the end of a downstream channel command frame (see also figure 23-5 ). figure 23-24 command frame interrupt control isc sdedi cdedi software clear software set edie = 00, 11 hardware set edie icr first data bit shifted last data bit shifted 01 10 1 mca06249_mod dedi isr data frame interrupt (to int. comp.) edi set 2 end of a command frame detected isc sdeci cdeci software clear software set hardware set mca06250_mod ecie icr command frame interrupt (to int. comp.) eci deci isr set 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-33 v1.1, 2011-03 msc, v1.40 23.1.5.3 time frame finished interrupt a time frame finished interrupt can be generated at the end of a downstream channel passive time phase. figure 23-25 time frame interrupt control tfie icr tfi dtfi isr software set set mca06251_mod time frame interrupt (to int. comp.) time frame finished isc sdtfi cdtfi software set hardware set 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-34 v1.1, 2011-03 msc, v1.40 23.1.5.4 receive data interrupt whenever the upstream channel receives data in registers udx (x = 0-3), the msc is able to generate an interrupt. three interrupt generation conditions can be selected for the receive data interrupt: ? each update of udx (x = 0-3) generates a receive data interrupt. ? each update of udx (x = 0-3) generates a receive data interrupt when the updated value is not equal 00 h . ? only an update of register ud3 generates a receive data interrupt. the selection of the interrupt generation condition is controlled by bit field icr.rdie. setting icr.rdie = 0 disables the receive data interrupt in general. isr.urdi is the interrupt status flag that can be set or clear when writing bits isc.surdi or isc.curdi with a 1. figure 23-26 receive data interrupt control isc surdi curdi software clear software set rdie = 00 hardware set mca06252_mod urdi isr receive data interrupt (to int. comp.) rdi set rdie icr data is received and not equal 00 h data is received data is received in ud 3 01 10 11 2 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-35 v1.1, 2011-03 msc, v1.40 23.1.5.5 interrupt request compressor the interrupt control logic of the msc uses an interrupt compressing scheme that allows high flexibility in interrupt processing. each of the four interrupt sources can be directed via a 2-bit interrupt node pointer to one of the four service request outputs sr[3:0]. this also makes it possible to connect more than one interrupt source to one interrupt output srx. figure 23-27 msc interrupt request compressor note: the number of available msc interrupt outputs depends on the implementation of the msc module(s) in the specific product (see page 23-74 for TC1798 details). mca0625 3 edip icr d ata frame i nterrupt r eceive data i nterrupt rdi edi 2 2 ecip icr c ommand f rame interrupt eci 2 tfip icr t ime frame i nterrupt tfi 2 rdip icr 1 1 1 1 service reque st output sr0 service reque st output sr1 service reque st output sr2 service reque st output sr3 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-36 v1.1, 2011-03 msc, v1.40 23.2 msc kernel registers this section describes the kernel registers of the msc module. all msc kernel register names described in this section will be referenced in other parts of the TC1798 users manual by the module name prefix ?msc0_? for the msc0 interface and ?msc1_? for the msc1 interface. all registers in the msc address spaces are reset with the application reset (definition see scu section ?reset operation?). msc kernel register overview figure 23-28 msc kernel registers the complete and detailed address map of the msc0 module is described in table 23-12 on page 23-75 . table 23-8 registers address sp ace - msc0 kernel registers module base address end address note msc0 f000 0800 h f000 08ff h ? msc1 f000 0900 h f000 09ff h ? mca05822_mod dd data registers usr dsc status and control registers dss dc udx dsdsl dsdsh esr x = 0-3 icr isr iscr ocr identification register id www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-37 v1.1, 2011-03 msc, v1.40 table 23-9 registers overview - msc kernel registers register short name register long name offset address 1) 1) the absolute register address is calculated as follows: module base address ( table 23-8 ) + offset address (shown in this column) description see id module identification register 08 h page 23-38 usr upstream status register 10 h page 23-39 dsc downstream control register 14 h page 23-41 dss downstream status register 18 h page 23-44 dd downstream data register 1c h page 23-59 dc downstream command register 20 h page 23-59 dsdsl downstream select data source low register 24 h page 23-46 dsdsh downstream select data source high register 28 h page 23-47 esr emergency stop register 2c h page 23-48 ud0 upstream data register 0 30 h page 23-60 ud1 upstream data register 1 34 h ud2 upstream data register 2 38 h ud3 upstream data register 3 3c h icr interrupt control register 40 h page 23-49 isr interrupt status register 44 h page 23-52 isc interrupt set clear register 48 h page 23-54 ocr output control register 4c h page 23-56 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-38 v1.1, 2011-03 msc, v1.40 23.2.1 module identification register the msc module identification register id contains read-only information about the module version. id module identificat ion register (08 h ) reset value: 0028 c0xx h 31 16 15 8 7 0 modnum modtype modrev rrr field bits type description modrev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). modtype [15:8] r module type this bit field defines the module as a 32-bit module: c0 h modnum [31:16] r module number value this bit field defines the module identification number for the msc: 0028 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-39 v1.1, 2011-03 msc, v1.40 23.2.2 status and control registers the upstream status register is used to configure the upstream channel data format, baud rate, and parity type. it also provides the status information of the upstream counter (uc). usr upstream status register (10 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0uc rrh 1514131211109876543210 0 p ctr urr uft r rwrwrw field bits type description uft 0rw upstream channel frame type this bit determines the frame type used by the upstream channel for data reception. 0 b 12-bit upstream frame selected 1 b 16-bit upstream frame selected (with 4-bit address field) urr [3:1] rw upstream channel receiving rate this bit field determines the baud rate for the upstream channel. 000 b upstream channel disabled; no reception is possible 001 b baud rate = f msc /4 010 b baud rate = f msc /8 011 b baud rate = f msc /16 100 b baud rate = f msc /32 101 b baud rate = f msc /64 110 b baud rate = f msc /128 111 b baud rate = f msc /256 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-40 v1.1, 2011-03 msc, v1.40 pctr 4rw parity control this bit determines the parity mode used by the upstream channel for data reception. 0 b even parity mode is selected. a parity bit is set on an odd number of 1s in the serial address/data stream. 1 b odd parity mode is selected. a parity bit is set on an even number of 1s in the serial address/data stream. uc [20:16] rh upstream counter this bit field indicates the content of the upstream counter that counts the bits during upstream channel reception. 0 [15:5], [31:21] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-41 v1.1, 2011-03 msc, v1.40 the downstream control register is used to control the operation mode and frame layout of the downstream channel transmission. it also contains the two pending status bits. dsc downstream control register (14 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 ppd 0 nbc rrwrrw 1514131211109876543210 ds dis en sel h en sel l ndbh ndbl dp cp tm rh rw rw rw rw rh rh rw field bits type description tm 0rw transmission mode this bit selects the transmission mode of the downstream channel. 0 b triggered mode selected 1 b data repetition mode selected cp 1rh command pending this bit is set when the downstream command register dc is written. cp is cleared when the first bit of the related command frame is sent out. dp 2rh data pending in triggered mode, this bit is set when the set data pending bit isc.sdp is set by software. in data repetition mode, this bit is set by hardware at the last passive time frame. at the start of the data frame, dp is cleared by hardware. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-42 v1.1, 2011-03 msc, v1.40 ndbl [7:3] rw number of srl bits sh ifted at data frames ndbl determines the number of shift register low part (srl) bits that are shifted out on so during a data frame. 00000 b no srl bit shifted 00001 b srl[0] shifted 00010 b srl[1:0] shifted ... b ... 01111 b srl[14:0] shifted 10000 b srl[15:0] shifted other bit combinations are reserved; do not use these bit combinations. ndbh [12:8] rw number of srh bits sh ifted at data frames ndbh determines the number of shift register high part (srh) bits that are shifted out on so during a data frame. 00000 b no srh bit shifted; no selection bit is generated, the srh active phase is completely skipped. 00001 b srh[0] shifted 00010 b srh[1:0] shifted ... b ... 01111 b srh[14:0] shifted 10000 b srh[15:0] shifted other bit combinations are reserved; do not use these bit combinations. ensell 13 rw enable srl active phase selection bit this bit determines whether a low level selection bit is inserted at the beginning of a data frame?s srl active phase. 0 b no selection bit inserted. 1 b low level selection bit inserted. enselh 14 rw enable srh active phase selection bit this bit determines whether a low level selection bit is inserted at the beginning of a data frame?s srh active phase. 0 b no selection bit inserted. 1 b low level selection bit inserted. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-43 v1.1, 2011-03 msc, v1.40 note: the ?rw? bits in the dsc register are buffered in a shadow buffer at the start of a corresponding frame transmission. dsdis 15 rh downstream disable this bit indicates the state of the downstream channel operation. 0 b the downstream channel is enabled. a frame transmission can take pl ace (triggered mode) or takes place (data repetition mode). 1 b downstream counter becomes disabled. no new frame transmission is started. a running frame transmission is always completed. nbc [21:16] rw number of bits shifted at command frames this bit field determines how many bits of the srl/srh shift registers are shifted out during transmission of a command frame. 000000 b no bit shifted 000001 b srl[0] shifted 000010 b srl[1:0] shifted 000011 b srl[2:0] shifted ... b ... 010000 b srl[15:0] shifted 010001 b srl[15:0] and srh[0] shifted 010010 b srl[15:0] and srh[1:0] shifted ... b ... 011111 b srl[15:0] and srh[14:0] shifted 100000 b srl[15:0] and srh[15:0] shifted other bit combinations are reserved; do not use these bit combinations ppd [28:24] rw passive phase length at data frames this bit field determines the length of the passive phase of a data frame. 00000 b passive phase length is 2 t fcl 00001 b passive phase length is 2 t fcl 00010 b passive phase length is 2 t fcl 00011 b passive phase length is 3 t fcl ? b ? 11111 b passive phase length is 31 t fcl 0 [23:22], [31:29] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-44 v1.1, 2011-03 msc, v1.40 the downstream status register dss contains counter bit fields, status bits, and indicates the number of passive time frames. dss downstream status register (18 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 cfa dfa 0 dc rrhrhr rh 1514131211109876543210 0 nptf 0 pfc rrwrrh field bits type description pfc [3:0] rh passive time frame counter in data repetition mode, this bit field indicates the count of passive time frames that are currently transmitted. in triggered mode pfc remains at 0000 b . 0000 b data frame is transmitted. 0001 b first passive time frame is transmitted. 0010 b second passive time frame is transmitted. ... b ... 1111 b fifteenth passive time frame is transmitted. nptf [11:8] rw number of passive time frames this bit field indicates the number of passive time frames that are inserted in data repetition mode between two data frames. 0000 b no passive time frame inserted. 0001 b one passive time frame inserted. 0010 b two passive time frames inserted. ... b ... 1111 b fifteen passive time frames inserted. note: nptf is buffered in a shadow buffer at the start of each data frame. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-45 v1.1, 2011-03 msc, v1.40 dc [22:16] rh downstream counter this bit field indicates the number of downstream shift clock periods that have been elapsed since the start of the current frame. 00 h no shift clock elapsed (after counter reset). 01 h 1 shift clock elapsed. ? h ? 7f h 127 shift clocks elapsed. dc is reset at the end of a downstream frame. dfa 24 rh data frame active this bit indicates if a data frame is currently sent out. 0 b no data frame is currently sent out. 1 b a data frame is currently sent out. cfa 25 rh command frame active this bit indicates if a command frame is currently sent out. 0 b no command frame is currently sent out. 1 b a command frame is currently sent out. 0 [7:4], [15:12], 23, [31:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-46 v1.1, 2011-03 msc, v1.40 the bit fields of the downstream select data low register dsdsl determine the data source for each bit in shift register srl. dsdsl downstream select data source low register (24 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sl15 sl14 sl13 sl12 sl11 sl10 sl9 sl8 rw rw rw rw rw rw rw rw 1514131211109876543210 sl7 sl6 sl5 sl4 sl3 sl2 sl1 sl0 rw rw rw rw rw rw rw rw field bits type description slx (x = 0-15) [2*x+1: 2*x] rw select source for srl slx determines which data source is used for the shift register bit srl[x] during data frame transmission. 00 b srl[x] is taken from data register dd.ddl[x]. 01 b reserved. 10 b srl[x] is taken from the altinl input line x. 11 b srl[x] is taken from the altinl input line x in inverted state. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-47 v1.1, 2011-03 msc, v1.40 the bit fields of the downstream select data source high register dsdsh determine the data source for each bit in shift register srh. dsdsh downstream select data source high register (28 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sh15 sh14 sh13 sh12 sh11 sh10 sh9 sh8 rw rw rw rw rw rw rw rw 1514131211109876543210 sh7sh6sh5sh4sh3sh2sh1sh0 rw rw rw rw rw rw rw rw field bits type description shx (x = 0-15) [2*x+1: 2*x] rw select source for srh shx determines which data source is used for the shift register bit srh[x] during data frame transmission. 00 b srh[x] is taken from data register dd.ddh[x]. 01 b reserved. 10 b srh[x] is taken from the altinh input line x. 11 b srh[x] is taken from the altinh input line x in inverted state. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-48 v1.1, 2011-03 msc, v1.40 the emergency stop register esr determines which bits of srl and srh are enabled for emergency operation. esr emergency stop register (2c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 enh 15 enh 14 enh 13 enh 12 enh 11 enh 10 enh 9 enh 8 enh 7 enh 6 enh 5 enh 4 enh 3 enh 2 enh 1 enh 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 enl 15 enl 14 enl 13 enl 12 enl 11 enl 10 enl 9 enl 8 enl 7 enl 6 enl 5 enl 4 enl 3 enl 2 enl 1 enl 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description enlx (x = 0-15) xrw emergency stop enable for bit x in srl this bit enables the emergency stop feature selectively for each srl bit. if the emergency stop condition is met and enabled (enlx = 1), the srl[x] bit is of the data register dd.ddl[x] is used for the shift register load operation. 0 b emergency stop feature for bit srl[x] is disabled. 1 b the emergency stop feature for bit srl[x] is enabled. enhx (x = 0-15) x+16 rw emergency stop enable for bit x in srh this bit enables the emergency stop feature selectively for each srh bit. if the emergency stop condition is met and enabled (enhx = 1), the srh[x] bit of the data register dd.ddh[x] is used for the shift register load operation. 0 b emergency stop feature for bit srh[x] is disabled. 1 b the emergency stop feature for bit srh[x] is enabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-49 v1.1, 2011-03 msc, v1.40 the interrupt control register icr holds the interrupt enable bits and interrupt pointers of all four msc interrupts. icr interrupt contro l register (40 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 rdie rdip tfie 0 tfip ecie 0 ecip edie edip rw rw rw r rw rw r rw rw rw field bits type description edip [1:0] rw data frame interr upt node pointer edip selects the service request output line srn (n = 0-3) for the data frame interrupt. 00 b service request output sr0 selected 01 b service request output sr1 selected 10 b service request output sr2 selected 11 b service request output sr3 selected edie [3:2] rw data frame interrupt enable this bit field determines the enable conditions for the data frame interrupt. 00 b interrupt generation disabled 01 b an interrupt is generated when the last data bit has been shifted out. 10 b an interrupt is generated when the first data bit has been shifted out, but only if dsc.ndbl is not equal 00000 b . this means, at least one srl bit must be shifted out for the first data bit shifted interrupt to become active. 11 b interrupt generation disabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-50 v1.1, 2011-03 msc, v1.40 ecip [5:4] rw command frame interrupt node pointer ecip selects the service request output line srn (n = 0-3) for the command frame interrupt. 00 b service request output sr0 selected 01 b service request output sr1 selected 10 b service request output sr2 selected 11 b service request output sr3 selected ecie 7rw command frame interrupt enable this bit enables the command frame interrupt. 0 b interrupt generation disabled. 1 b interrupt generation enabled. tfip [9:8] rw time frame interrupt pointer tfip selects the service request output line srn (n = 3-0) for the time frame interrupt. 00 b service request output sr0 selected 01 b service request output sr1 selected 10 b service request output sr2 selected 11 b service request output sr3 selected tfie 11 rw time frame interrupt enable this bit enables the time frame interrupt. 0 b interrupt generation disabled. 1 b interrupt generation enabled. rdip [13:12] rw receive data interrupt pointer rdip selects the service request output line srn (n = 3-0) for the receive data interrupt. 00 b service request output sr0 selected 01 b service request output sr1 selected 10 b service request output sr2 selected 11 b service request output sr3 selected field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-51 v1.1, 2011-03 msc, v1.40 rdie [15:14] rw receive data interrupt enable this bit field determines the enable conditions for the receive data interrupt. 00 b interrupt generation disabled. 01 b an interrupt is generated when data is received and written into the upstream data registers udx (x = 0-3). 10 b an interrupt is generated as with rdie = 01 b but only if the received data is not equal to 00 h . 11 b an interrupt is generated when data is received and written into register ud3. 0 6, 10, [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-52 v1.1, 2011-03 msc, v1.40 the interrupt status register isr holds the interrupt status flags that indicate an interrupt occurrence in downstream and upstream channels. isr interrupt status register (44 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 urdi dtfi deci dedi r rhrhrhrh field bits type description dedi 0rh data frame interrupt flag this flag is always set by hardware when a downstream channel data frame interrupt is generated. dedi can be set or cleared by software when writing to register isc with the appropriate bits isc.sdedi or isc.cdedi set. deci 1rh command frame interrupt flag this flag is always set by hardware when a downstream channel command frame interrupt is generated, whether or not it is enabled. deci can be set or cleared by software when writing to register isc with the appropriate bits sdeci or cdeci set. dtfi 2rh time frame interrupt flag this flag is always set by hardware when a downstream channel time frame interrupt is generated, whether or not it is enabled. dtfi can be set or cleared by software when writing to register isc with the appropriate bi ts sdtfi or cdtfi set. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-53 v1.1, 2011-03 msc, v1.40 urdi 3rh receive data interrupt flag this flag is always set by hardware when an upstream channel receive data interrupt is generated, whether or not it is enabled. urdi can be set or cleared by software when writing to register isc with the appropriate bits surdi or curdi set. 0 [31:4] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-54 v1.1, 2011-03 msc, v1.40 the interrupt set clear register isc is used to set or clear the msc interrupt flags located in the interrupt status register isr. reading isc always returns 0000 0000 h . isc interrupt set clear register (48 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 s ddis s cp s dp s urdi s dtfi s deci s dedi r wwwwwww 1514131211109876543210 0 c ddis c cp c dp c urdi c dtfi c deci c dedi r wwwwwww field bits type description cdedi 0w clear dedi flag 0 b no operation 1 b bit isr.dedi is cleared. cdeci 1w clear deci flag 0 b no operation 1 b bit isr.deci is cleared. cdtfi 2w clear dtfi flag 0 b no operation 1 b bit isr.dtfi is cleared. curdi 3w clear urdi flag 0 b no operation 1 b bit isr.urdi is cleared. cdp 4w clear dp flag 0 b no operation 1 b bit dsc.dp is cleared. ccp 5w clear cp flag 0 b no operation 1 b bit dsc.cp is cleared. cddis 6w clear dsdis flag 0 b no operation 1 b bit dsc.dsdis is cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-55 v1.1, 2011-03 msc, v1.40 note: when the isc register is written with both bits (set and reset bit) for a specific interrupt flag, the clear operation takes place and the set operation is ignored. sdedi 16 w set dedi flag 0 b no operation 1 b bit isr.dedi is set. sdeci 17 w set deci flag 0 b no operation 1 b bit isr.deci is set. sdtfi 18 w set dtfi flag 0 b no operation 1 b bit isr.dtfi is set. surdi 19 w set urdi flag 0 b no operation 1 b bit isr.urdi is set. sdp 20 w set dp bit 0 b no effect 1 b bit dsc.dp is set. scp 21 w set cp flag 0 b no operation 1 b bit dsc.cp is set. sddis 22 w set dsdis flag 0 b no operation 1 b bit dsc.dsdis is set. 0 [15:7], [31:23] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-56 v1.1, 2011-03 msc, v1.40 the output control register ocr determines the msc input/output signal polarities, the chip select output signal assignment, and the serial output clock generation. ocr output control register (4c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 sdisel rrw 1514131211109876543210 0 csc csh csl clk ctr l 0ilp cs lp slp clp r rw rw rw rw r rw rw rw rw field bits type description clp 0rw fclp line polarity 0 b fclp and fcl signal polarity is identical. fcln signal has inverted fcl signal polarity. 1 b fclp signal has inverted fcl signal polarity. fcln and fcl signal polarities are identical. slp 1rw sop line polarity 0 b sop and so signal polarity is identical. son signal has inverted so signal polarity. 1 b sop signal has inverted so signal polarity. son and so signal polarities are identical. cslp 2rw chip selection lines polarity 0 b en[3:0] and enl, enh, enc signal polarities are identical (high active). 1 b en[3:0] signal polarities are inverted (low active) to the enl, enh, enc signal polarities. bit cslp is buffered during a frame transmission. this means that any change of cslp becomes valid first with the start of the next frame transmission. ilp 3rw sdi line polarity 0 b sdi and si signal polarities are identical. 1 b sdi and si signal polarities are inverted. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-57 v1.1, 2011-03 msc, v1.40 clkctrl 8rw clock control this bit determines the activation of clock output fcl. 0 b fcl is activated only during the active phases of data or command frames (not during passive time frames). 1 b fcl is always active whether or not a downstream frame is currently transmitted. csl [10:9] rw chip enable selection for enl this bit field selects the chip enable output enx that becomes active during the srl active phase (enl = 1) of a data frame. the active level of enx is defined by bit cslp. 00 b en0 line is selected for enl. 01 b en1 line is selected for enl. 10 b en2 line is selected for enl. 11 b en3 line is selected for enl. csh [12:11] rw chip enable selection for enh this bit field selects the chip enable output enx that becomes active during the srh active phase (enh = 1) of a data frame. the active level of enx is defined by bit cslp. 00 b en0 line is selected for enh. 01 b en1 line is selected for enh. 10 b en2 line is selected for enh. 11 b en3 line is selected for enh. csc [14:13] rw chip enable selection for enc this bit field selects the chip enable output enx that becomes active during the active phase (enc = 1) of a command frame. the active level of enx is defined by bit cslp. 00 b en0 line is selected for enc. 01 b en1 line is selected for enc. 10 b en2 line is selected for enc. 11 b en3 line is selected for enc. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-58 v1.1, 2011-03 msc, v1.40 sdisel [18:16] rw serial data input selection this bit field selects the source for the serial data input sdi of the upstream channel. 000 b sdi0 input is selected for sdi. 001 b sdi1 input is selected for sdi. 010 b sdi2 input is selected for sdi. 011 b sdi3 input is selected for sdi. 100 b sdi4 input is selected for sdi. 101 b sdi5 input is selected for sdi. 110 b sdi6 input is selected for sdi. 111 b sdi7 input is selected for sdi. 0 [7:4], 15, [31:19] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-59 v1.1, 2011-03 msc, v1.40 23.2.3 data registers the downstream data register dd contains data to be transmitted during data frames. the downstream command register dc contains command information to be transmitted during command frames. dd downstream data register (1c h ) reset value: 0000 0000 h 31 16 15 0 ddh ddl rw rw field bits type description ddl [15:0] rw downstream data for srl shift register contains the data bits to be transmitted during the srl active phase of a data frame. ddh [31:16] rw downstream data fo r srh shift register contains the data bits to be transmitted during the srh active phase of a data frame. dc downstream command register (20 h ) reset value: 0000 0000 h 31 16 15 0 dch dcl rw rw field bits type description dcl [15:0] rw downstream command fo r srl shift register contains the data bits to be transmitted during the srl active phase of a command frame. dch [31:16] rw downstream command fo r srh shift register contains the data bits to be transmitted during the srh active phase of a command frame. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-60 v1.1, 2011-03 msc, v1.40 the four upstream data registers udx stor e the content (data, addresses, received and calculated parity bit, parity error bit) of a received upstream channel data frame. udx (x = 0-3) upstream data register x (30 h +x*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 p err ipf labf c p v rrhrhrhwrhrh 1514131211109876543210 0 data rrh field bits type description data [7:0] rh received data this bit field contains the 8-bit receive data. v 16 rh valid bit this bit is set by hardware when the received data is written to udx. writing bit c = 1 clears v. if hardware setting and software clearing of the valid bit occur simultaneously, bit v will be cleared. p 17 rh parity bit this flag contains the parity bit that has been received with the data frame. c 18 w clear bit 0 b no operation. 1 b bit v is cleared. c is always read as 0. labf [20:19] rh lower address bit field this bit field contains the two address bits a[1:0] of the 4-bit address field (16-bit data frame). if 12-bit data frame is selected, labf is always set to 00 b . ipf 21 rh internal parity flag this bit contains the parity bit that has been calculated in the msc during data frame reception. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-61 v1.1, 2011-03 msc, v1.40 perr 22 rh parity error this bit indicates if a start bit error, parity error, or stop bit error occurred during frame reception. 0 b no error detected. 1 b error detected. 0 [15:8], [31:23] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-62 v1.1, 2011-03 msc, v1.40 23.3 msc module implementation this section describes the msc module interface as implemented in the TC1798. it especially covers clock control, port and on-chip connections, interrupt control, and address decoding. 23.3.1 interface connections of the msc modules figure 23-29 shows the tc798-specific implementation details and interconnections of the msc0 and msc1 modules. each msc module is supplied with a separate clock control, address decoding, and interrupt control logic. two of the four modules? service request outputs are connected with interrupt nodes, and two with the dma controller. outputs of the gpta module are connected to the alternate input buses altinl/altinh. the emergency stop output from the scu controls the corresponding inputs of both msc modules. the serial data and clock outputs of the downstream channels of each msc module are connected to combined gpio/lvds differential output drivers. details about these eight port 5 pins are defined in the ports chapter (see also table 23-10 ). additionally, the positive serial clock (fclp) and positive data output (sop) are available at gpio lines of port 9. the dev ice select outputs (enxy) are wired to gpio lines of port 5 and port 9. one port 5 input line is connected to the upstream channel serial data input. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-63 v1.1, 2011-03 msc, v1.40 figure 23-29 msc0 and msc1 module implementations and interconnections msc0 module (kernel ) fcln clock control address decoder interrupt control downstream channel upstr. cha nnel fclp en0 en1 en2 en3 son sop sdi0 sr[1:0] emgstopmsc altinl[15:0] 16 altinh[15:0] to dma p5.5 / sdi0 p5.8 / son0 p5.9 / sop0a p9.4 / en03 p9.5 / en02 p9.6 / en01 p5.4 / en00 p5.10 / fcln0 p5.11 / fclp0a p9.8 / fclp0b p9.7 / sop0b sr[3:2] (from gpta) (from scu) msc1 module (kernel ) mca05823_mod_TC1798 fcln clock control address decoder interrupt control f msc 1 f clc1 downstream ch an nel upstr. channe l fclp en0 en1 en2 son sop sdi0 sr[1:0] altinl[15:0] altinh[15:0] to dma sr[3:2] (from gpta) p5.7 / sdi1 p5.12 / son1 p5 .13 / s op1a p9.0 / en12 p9.1 / en11 p5.6 / en10 p5.14 / fcln1 p5.15 / fclp1a p9.3 / fclp1b p9.2 / sop1b f msc 0 f clc0 sr15 ( from can) 16 16 16 port 5 & port 9 control f a2 f f f a2 a2 a2 a2 a2 port 5 & port 9 control a2 a2 a2 a2 a2 f f f f f = a1 or lvds f = a1 or lvds sdi[7:1] 1) 1) these inputs are connected to high level . 2) this output is not connected . en3 2) sdi[7:1] 1) a1+ a1+ www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-64 v1.1, 2011-03 msc, v1.40 23.3.2 msc0/msc1 module-related external registers figure 23-30 summarizes the module-related external registers which are required for msc programming (see also figure 23-28 for the module kernel specific registers). these registers are described in the following sections. figure 23-30 msc implementation-specific special function registers mca05824_mod msc0_srcx interrupt registers port registers clock control registers msc0 _clc x = 1, 0 msc1 _clc msc0_fdr msc1_fdr msc1_srcx p 5_iocr4 p 9_iocr0 p 9_iocr4 p 9_iocr8 p 9_pdr0 p 5_iocr8 p 5_iocr12 p 5_pdr0, 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-65 v1.1, 2011-03 msc, v1.40 23.3.3 clock control the msc modules are provided with two independent clock signals ( figure 23-31 ): ? f clc0 and f clc1 these are the module clocks that are used inside the msc kernel for control purposes such as clocking of control logic and register operations. the frequency of f clc0 and f clc1 is always identical to the system clock frequency f fpi . the clock control registers msc0_clc and msc1_clc make it possible to enable/disable f clc0 and f clc1 under certain conditions. ? f msc0 and f msc1 these clocks are the module clocks that are used inside the msc for baud rate generation of the serial upstream and downs tream channel. the fractional divider registers msc0_fdr and msc1_fdr control the frequency of f msc0 and f msc1 and make it possible to enable/disable it independently of f clc0 and f clc1 . for module test purposes only, the serv ice request output sr15 of the multican controller makes it possible to synchronize the fractional divider clock generation of both msc modules to external events. this feature should not be used for normal msc operation. figure 23-31 msc module clock generation msc1 module kernel downstream channel upstream channel urr mca05825_max.vsd clock control register msc0 _clc f clc0 msc0 clock generation f msc 0 f fpi fractional divider register msc0_fdr clock control register msc1 _clc f clc1 msc1 clock generation f msc 1 fractional divider register msc1_fdr msc0 module kernel downstream channel upstream channel ecen ecen multican module sr15 urr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-66 v1.1, 2011-03 msc, v1.40 the following two formulas define the frequency of f msc0 : (23.3) (23.4) downstream channel baud rate as the clock signal fcl of the synchronous downstream channel is always half the frequency of f msc0 , the resulting downstream channel baud rate is defined by: (23.5) (23.6) upstream channel baud rate the baud rate of the asynchronous upstream channel is derived from the module clock f msc0 by a programmable clock divider selected by bit field msc0_usr.urr (see also equation (23.2) on page 23-25 ). the divide factor df can be at minimum 4 and at maximum 256. (23.7) (23.8) equation (23.3) , equation (23.5) , and equation (23.7) are valid for normal divider mode (msc0.fdr.dm = 01 b ). equation (23.4) , equation (23.6) , and equation (23.8) are valid for fractional divider mode (msc0.fdr.dm = 10 b ). f msc0 f fpi 1 n -- - with n = 1024 - msc0.fdr.step = f msc0 f fpi n 1024 ------------ - with n = 0-1023 = baud rate msc0 f fpi 1 2 1024 - msc0.fdr.step () -------------------------------------------------------------------------------- - = baud rate msc0 f fpi msc0.fdr.step 2 1024 ----------------------------------------------- - = baud rate msc0 f fpi 1 df 1024 - msc0.fdr.step () ------------------------------------------------------------------------------------- - = baud rate msc0 f fpi msc0.fdr.step df 1024 ----------------------------------------------- - = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-67 v1.1, 2011-03 msc, v1.40 23.3.3.1 clock control register the clock control register allows the progra mmer to control (enable/disable) the clock signals to the msc0 module under certain conditions. the diagram below shows the clock control register functionality as is implemented for the msc0 and msc1 modules. note: after a hardware reset operation, the f clc0 and f msc0 clocks are switched off and the msc modules are disabled (diss set). msc0_clc msc0 clock control register (00 h ) reset value: 0000 0003 h msc1_clc msc1 clock control register (00 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we e dis sp en dis s dis r r rwwrwrw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the module. diss 1r module disable status bit bit indicates the current status of the module. spen 2rw module suspend enable for ocds used to enable the suspend mode edis 3rw sleep mode en able control used to control module?s sleep mode. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. fsoe 5rw fast switch off enable used to switch off fast clock in suspend mode. 0 [31:6] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-68 v1.1, 2011-03 msc, v1.40 23.3.3.2 fractional divider register the fractional divider registers control the clock rate of the shift clock f msc0 and f msc1 . each msc module has its own fractional divider register. msc0_fdr msc0 fractional divider register (0c h ) reset value: 0000 0000 h msc1_fdr msc1 fractional divider register (0c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dis clk en hw sus req sus ack 0result rwh rw rh rh r rh 1514131211109876543210 dm sc sm fdis step rw rw rw rw rw field bits type description step [9:0] rw step value reload or addition value for result. fdis 10 rw freeze disable this bit controls the freeze function for this module. 0 b module operates on co rrected clock, with reduced modulation jitter. 1 b module operates on uncorrected clock, with full modulation jitter. sm 11 rw suspend mode sm selects between granted or immediate suspend mode. sc [13:12] rw suspend control this bit field determines the behavior of the fractional divider in suspend mode. dm [15:14] rw divider mode dm selects normal or fractional divider mode. result [25:16] rh result value bit field for the addition result. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-69 v1.1, 2011-03 msc, v1.40 23.3.4 port control msc0 and msc1 clock and data output lines are connected to dedicated differential output drivers. some of the msc module i/o lines are connected to i/o ports and therefore controlled in the port logic (see also figure 23-29 ). the following port control operations selections must be executed for these i/o lines: ? input/output function selection (iocr registers) ? pad driver characteristics select ion for the outputs (pdr registers) 23.3.4.1 input/output function selection the port input/output control registers contain the bit fields that select the digital output and input driver characteristics such as port direction (input/output) with alternate output selection, pull-up/down devices, and open-drain selections. the i/o lines for the msc modules are controlled by the port 5 and port 9 input/output control registers. table 23-10 shows in an overview how bits and bit fields must be programmed for the required i/o functionality of the msc i/o lines. susack 28 rh suspend mode acknowledge indicates state of spndack signal. susreq 29 rh suspend mode request indicates state of spnd signal. enhw 30 rw enable hardware clock control controls operation of ecen input and disclk bit. disclk 31 rwh disable clock hardware controlled disable for f out signal. 0 [27:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-70 v1.1, 2011-03 msc, v1.40 table 23-10 msc0 and msc1 i/o line selection and setup module port lines input/output control register bits i/o msc0 p5.8 / son0 p5_iocr8.pc8 = 1x01 b p5_pdr1.pd8 = 0xx b cmos output 1) p5_iocr8.pc8 = 1xxx b p5_pdr1.pd8 = 1xx b lvds output p5.9 / sop0a p5_iocr8.pc9 = 1x01 b p5_pdr1.pd8 = 0xx b cmos output 1) p5_iocr8.pc9 = 1xxx1 b p5_pdr1.pd8 = 1xx b lvds output p5.10 / fcln0 p5_iocr8.pc10 = 1x01 b p5_pdr1.pd10 = 0xx b cmos output 1) p5_iocr8.pc10 = 1xxx b p5_pdr1.pd10 = 1xx b lvds output p5.11 / fclp0a p5_iocr8.pc11 = 1x01 b p5_pdr1.pd10 = 0xx b cmos output 1) p5_iocr8.pc11 = 1xxx b p5_pdr1.pd10 = 1xx b lvds output p5.4 / en00 p5_iocr4.pc12 = 1x01 b output p5.5 / sdi0 2) p5_iocr4.pc5 = 0xxx b input p9.4 / en03 p9_iocr4.pc4 = 1x11 b output p9.5 / en02 p9_iocr4.pc5 = 1x11 b output p9.6 / en01 p9_iocr4.pc6 = 1x11 b output p9.7 / sop0b p9_iocr4.pc7 = 1x11 b output p9.8 / fclp0b p9_iocr8.pc8 = 1x01 b output p9_iocr8.pc8 = 1x10 b p9_iocr8.pc8 = 1x11 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-71 v1.1, 2011-03 msc, v1.40 msc1 3) p5.12 / son1 p5_iocr12.pc12 = 1x01 b p5_pdr1.pd12 = 0xx b cmos output 1) p5_iocr12.pc12 = 1xxx b p5_pdr1.pd12 = 1xx b lvds output p5.13 / sop1a p5_iocr12.pc13 = 1x01 b p5_pdr1.pd12 = 0xx b cmos output 1) p5_iocr12.pc13 = 1xxx b p5_pdr1.pd12 = 1xx b lvds output p5.14 / fcln1 p5_iocr12.pc14 = 1x01 b p5_pdr1.pd14 = 0xx b cmos output 1) p5_iocr12.pc14 = 1xxx1 b p5_pdr1.pd14 = 1xx b lvds output p5.15 / fclp1a p5_iocr12.pc15 = 1x01 b p5_pdr1.pd14 = 0xx b cmos output 1) p5_iocr12.pc15 = 1xxx b p5_pdr1.pd14 = 1xx b lvds output p5.6 / en10 p5_iocr4.pc6 = 1x01 b output p5.7 / sdi1 2) p5_iocr4.pc7 = 0xxx b input p9.0 / en12 p9_iocr0.pc0 = 1x11 b output p9.1 / en11 p9_iocr0.pc1 = 1x11 b output p9.2 / sop1b p9_iocr0.pc2 = 1x10 b output p9.3 / fclp1b p9_iocr0.pc3 = 1x10 b output 1) default after reset. 2) for the upstream channel serial data inputs, additi onally bit fields msc0_ocr.sdisel (for sdi0) and msc1_ocr.sdisel (for msc1) must be set to 000 b . 3) chip enable output 3 (en3) of the msc1 module is not connected in the TC1798. table 23-10 msc0 and msc1 i/o line selection and setup (cont?d) module port lines input/output control register bits i/o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-72 v1.1, 2011-03 msc, v1.40 23.3.5 on-chip connections this section describes the on-chip connections of the msc0/msc1 modules. 23.3.5.1 emgstopmsc signal (from scu) the emergency stop input signals emgstopmsc of both msc modules are connected to the output signal of the emergency stop input control logic. this logic is located in the scu. its functionality is controlled by the scu emergency stop register. 23.3.5.2 altinh and altinl connections in the TC1798, output lines of gpta0, gpta1, and ltca2 are connected to altinh and altinl inputs of the msc0/msc1 downstream channels as shown in figure 23-32 . the setting of the gpta-to-msc multiplexer determines which output of the three gpta sub-modules is connected to a specific altinl/altinh line. please note that the upper eight msc1 input lines altinh[15:8] are connected to logic 0 level. figure 23-32 altinl/altinh connections of the msc0/msc1 mca05826 altinl[15:0] gpta-to-msc multiplexer altinh[15:0] gpta0 gpta1 ltca2 gpta msc1 altinh[15:8] altinl[15:0] altinh[7:0] 0 msc0 control data data data www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-73 v1.1, 2011-03 msc, v1.40 23.3.5.3 dma controll er service requests two service request outputs (sr[3:2]) of each msc module are connected as dma request input to the dma controller. the dma request lines are connected to the dma controller as shown in table 23-11 . table 23-11 service request lines of msc0/msc1 module service request line connected to description msc0 sr0 msc0_src0 msc0 service request node 0 sr1 msc0_src1 msc0 service request node 1 sr2 ch02_reqi6 dma channel 02 request input 6 ch04_reqi6 dma channel 04 request input 6 sr3 ch03_reqi6 dma channel 03 request input 6 ch05_reqi6 dma channel 05 request input 6 msc1 sr0 msc1_src0 msc1 service request node 0 sr1 msc1_src1 msc1 service request node 1 sr2 ch12_reqi14 dma channel 12 request input 14 ch14_reqi14 dma channel 14 request input 14 sr3 ch13_reqi14 dma channel 13 request input 14 ch15_reqi14 dma channel 15 request input 14 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-74 v1.1, 2011-03 msc, v1.40 23.3.6 interrupt control registers in the TC1798, the two service request outputs sr[1:0] of each msc module are connected to one interrupt node. the upper two service request outputs sr[3:2] of each msc module are not connected to interrupt nodes, but can be used as dma requests (see table 23-11 ). src1 service request control register 1 (f8 h ) reset value: 0000 0000 h src0 service request control register 0 (fc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-75 v1.1, 2011-03 msc, v1.40 23.3.7 msc0/msc1 address map an absolute register address is given by th e offset address of the register (given in table 23-9 ) plus the module base address (given in table 23-8 ). table 23-12 address map of msc0/msc1 short name description address access mode reset value read write microsecond bus controller 0 (msc0) msc0_ clc msc0 clock control register f000 0800 h u, sv sv, e 0000 0003 h ? reserved f000 0804 h be be ? msc0_ id msc0 module identification register f000 0808 h u, sv be 0028 c0xx h msc0_ fdr msc0 fractional divider register f000 080c h u, sv sv, e 0000 0000 h msc0_ usr msc0 upstream status register f000 0810 h u, sv u, sv 0000 0000 h msc0_ dsc msc0 downstream control register f000 0814 h u, sv u, sv 0000 0000 h msc0_ dss msc0 downstream status register f000 0818 h u, sv u, sv 0000 0000 h msc0_ dd msc0 downstream data register f000 081c h u, sv u, sv 0000 0000 h msc0_ dc msc0 downstream command register f000 0820 h u, sv u, sv 0000 0000 h msc0_ dsdsl msc0 downstream select data source low register f000 0824 h u, sv u, sv 0000 0000 h msc0_ dsdsh msc0 downstream select data source high register f000 0828 h u, sv u, sv 0000 0000 h msc0_ esr msc0 emergency stop register f000 082c h u, sv u, sv 0000 0000 h msc0_ ud0 msc0 upstream data register 0 f000 0830 h u, sv u, sv 0000 0000 h msc0_ ud1 msc0 upstream data register 1 f000 0834 h u, sv u, sv 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-76 v1.1, 2011-03 msc, v1.40 msc0_ ud2 msc0 upstream data register 2 f000 0838 h u, sv u, sv 0000 0000 h msc0_ ud3 msc0 upstream data register 3 f000 083c h u, sv u, sv 0000 0000 h msc0_ icr msc0 interrupt control register f000 0840 h u, sv u, sv 0000 0000 h msc0_ isr msc0 interrupt status register f000 0844 h u, sv u, sv 0000 0000 h msc0_ isc msc0 interrupt set clear register f000 0848 h u, sv u, sv 0000 0000 h msc0_ ocr msc0 output control register f000 084c h u, sv u, sv 0000 0000 h ? reserved f000 0850 h - f000 0854 h nbe nbe ? f000 0858 h - f000 08f4 h be be ? msc0_ src1 msc0 service request control register 1 f000 08f8 h u, sv u, sv 0000 0000 h msc0_ src0 msc0 service request control register 0 f000 08fc h u, sv u, sv 0000 0000 h micro second channel 1 (msc1) msc1_ clc msc1 clock control register f000 0900 h u, sv sv, e 0000 0003 h ? reserved f000 0904 h be be ? msc1_ id msc1 module identification register f000 0908 h u, sv be 0000 44xx h msc1_ fdr msc1 fractional divider register f000 090c h u, sv sv, e 0000 0000 h msc1_ usr msc1 upstream status register f000 0910 h u, sv u, sv 0000 0000 h msc1_ dsc msc1 downstream control register f000 0914 h u, sv u, sv 0000 0000 h table 23-12 address map of msc0/msc1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-77 v1.1, 2011-03 msc, v1.40 msc1_ dss msc1 downstream status register f000 0918 h u, sv u, sv 0000 0000 h msc1_ dd msc1 downstream data register f000 091c h u, sv u, sv 0000 0000 h msc1_ dc msc1 downstream command register f000 0920 h u, sv u, sv 0000 0000 h msc1_ dsdsl msc1 downstream select data source low register f000 0924 h u, sv u, sv 0000 0000 h msc1_ dsdsh msc1 downstream select data source high register f000 0928 h u, sv u, sv 0000 0000 h msc1_ esr msc1 emergency stop register f000 092c h u, sv u, sv 0000 0000 h msc1_ ud0 msc1 upstream data register 0 f000 0930 h u, sv u, sv 0000 0000 h msc1_ ud1 msc1 upstream data register 1 f000 0934 h u, sv u, sv 0000 0000 h msc1_ ud2 msc1 upstream data register 2 f000 0938 h u, sv u, sv 0000 0000 h msc1_ ud3 msc1 upstream data register 3 f000 093c h u, sv u, sv 0000 0000 h msc1_ icr msc1 interrupt control register f000 0940 h u, sv u, sv 0000 0000 h msc1_ isr msc1 interrupt status register f000 0944 h u, sv u, sv 0000 0000 h msc1_ isc msc1 interrupt set clear register f000 0948 h u, sv u, sv 0000 0000 h msc1_ ocr msc1 output control register f000 094c h u, sv u, sv 0000 0000 h ? reserved f000 0950 h - f000 0954 h nbe nbe ? table 23-12 address map of msc0/msc1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro second channel (msc) users manual 23-78 v1.1, 2011-03 msc, v1.40 msc1_ src1 msc1 service request control register 1 f000 09f8 h u, sv u, sv 0000 0000 h msc1_ src0 msc1 service request control register 0 f000 09fc h u, sv u, sv 0000 0000 h table 23-12 address map of msc0/msc1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-1 v1.1, 2011-03 multican, v3.0 24 controller area networ k controller (multican) this chapter describes the multican controller of the TC1798. it contains the following sections: ? can basics (see page 24-2 ) ? overview of the can module in the TC1798 (see page 24-14 ) ? functional description of the multican kernel (see page 24-18 ) ? multican kernel register description (see page 24-60 ) ? functional description of the ttcan extension (see page 24-117 ) ? ttcan extension register description (see page 24-157 ) ? TC1798 implementation-specific details (port connections and control, interrupt control, address decoding, clock control, see page 24-202 ). note: the multican register names described in this chapter are referenced in the TC1798 users manual by the module name prefix ?can_?. table 24-1 fixed module constants constant description n_objects number of message objects available. n_interrupts number of interrupt output lines available. n_pendings n_pendingregs number of message pending bits available. there are n_pendings/32 message pending registers. n_lists number of lists available for allocation of message objects. n_nodes number of can nodes available as each can node has it?s own list in addition to the list of un- allocated elements, the relation n_nodes < n_lists is true. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-2 v1.1, 2011-03 multican, v3.0 24.1 can basics can is an asynchronous serial bus system wi th one logical bus line. it has an open, linear bus structure with equal bus participants called nodes. a can bus consists of two or more nodes. the bus logic corresponds to a ?wired-and? mechanism. recessive bits (equivalent to the logic 1 level) are overwritten by dominant bits (logic 0 level). as long as no bus node is sending a dominant bit, the bus is in the recessive state. in this state, a dominant bit from any bus node generates a dominant bus state. the maximum can bus speed is, by definition, 1 mbit/s. this speed limits the can bus to a length of up to 40 m. for bus lengths longer than 40 m, the bus speed must be reduced. the binary data of a can frame is coded in nrz code (non-return-to-zero). to ensure re-synchronization of all bus nodes, bit stuffing is used. this means that during the transmission of a message, a maximum of five consecutive bits can have the same polarity. whenever five consecutive bits of the same polarity have been transmitted, the transmitter will insert one additional bit (stuff bit) of the opposite polarity into the bit stream before transmitting fu rther bits. the receiver also checks the number of bits with the same polarity and removes the stuff bits from the bit stream (= destuffing). 24.1.1 addressing and bus arbitration in the can protocol, address information is defined in the identifier field of a message. the identifier indicates the contents of the message and its priority. the lower the binary value of the identifier, the higher is the priority of the message. for bus arbitration, csma/cd with nda (c arrier sense multiple access/collision detection with non-destructive arbitration) is used. if bus node a attempts to transmit a message across the network, it first checks that the bus is in the idle state (?carrier sense?) i.e. no node is currently transmitti ng. if this is the case (and no other node wishes to start a transmission at the same moment), node a becomes the bus master and sends its message. all other nodes switch to receive mode during the first transmitted bit (start-of-frame bit). after correct reception of the message (acknowledged by each node), each bus node checks the message identifier and stores the message, if required. otherwise, the message is discarded. if two or more bus nodes start their transmission at the same time (?multiple access?), bus collision of the messages is avoided by bit-wise arbi tration (?collision detection / non-destructive arbitration? together wi th the ?wired-and? mechanism, dominant bits override recessive bits). each node that sends also reads back the bus level. when a recessive bit is sent but a dominant one is read back, bus arbitration is lost and the transmitting node switches to receive mode. this condition occurs for example when the message identifier of a competing node has a lower binary value and therefore sends a message with a higher priority. in this way, the bus node with the highest priority message wins arbitration without losing time by having to repeat the message. other nodes that lost ar bitration will automa tically try to repeat their transmission once the bus www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-3 v1.1, 2011-03 multican, v3.0 returns to idle state. therefore, the same i dentifier can be sent in a data frame only by one node in the system. there must not be more than one node programmed to send data frames with the same identifier. standard message identifier has a length of 11 bits. can specification 2.0b extends the message identifier lengths to 29 bits, i.e. the extended identifier. 24.1.2 can frame formats there are three types of can frames: ? data frames ? remote frames ? error frames a data frame contains a data field of 0 to 8 bytes in length. a remote frame contains no data field and is typically generated as a request for data (e.g. from a sensor). data and remote frames can use an 11-bit ?s tandard? identifier or a 29-bit ?extended? identifier. an error frame can be generated by any node that detects a can bus error. 24.1.2.1 data frames there are two types of data frames defined (see figure 24-1 ): ? standard data frame ? extended data frame standard data frame a data frame begins with the start-of-frame bit (sof = dominant level) for hard synchronization of all nodes. the sof is followed by the arbitration field consisting of 12 bits, the 11-bit identifier (reflecting the contents and priority of the message), and the rtr (remote transmission request) bit. with rtr at dominant level, the frame is marked as data frame. with rtr at recessive level, the frame is defined as a remote frame. the next field is the control field consisting of 6 bits. the first bit of this field is the ide (identifier extension) bit and is at dominant level for the standard data frame. the following bit is reserved and defined as a dominant bit. the remaining 4 bits of the control field are the data length code (dlc) that specifies the number of bytes in the data field. the data field can be 0 to 8 bytes wide. the cyclic redundancy (crc) field that follows the data bytes is used to detect possible transmission errors. it consists of a 15-bit crc sequence, completed by a recessive crc delimiter bit. the final field is the acknowledge field. during the ack slot, the transmitting node sends out a recessive bit. any node that has received an error free frame acknowledges the correct reception of the frame by sending back a dominant bit, regardless of whether or not the node is configured to accept that specific message. this behavior assigns the www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-4 v1.1, 2011-03 multican, v3.0 can protocol to the ?in-bit-response? group of protocols. the recessive ack delimiter bit, which must not be overwritten by a dominant bit, completes the acknowledge field. seven recessive end-of -frame (eof) bits finish the data frame. between any two consecutive frames, the bus must remain in the recessive state for at least 3 bit times (called inter frame space). if after the inte r frame space, no other nodes attempt to transmit the bus remains in idle state with a recessive level. figure 24-1 can data frame extended data frame in the extended can data frame, the message identifier of the standard frame has been extended to 29-bit. a split of the extended identifier into two parts, an 11-bit least bus idle dominant level recessive level bus idle bus idle dominant level recessive level mct06258 11 standard data frame ack delimiter ack slot crc delimiter crc sequence data field reserved (d) ide bit (d) rtr bit (d) identifier 4 1 1 11 1 1 15 start of frame control field arbitration field (12 bit ) 1 7 3 inter frame space end of frame (eof) acknowledg e field crc field 1 1 1 15 7 3 extended data frame srr bit (r) ide bit (r) 29-bit identfier arbitration field (32 bit ) rtr bit (d) 2 reserved (d) 0 - 64 bus idle 11 4 2 1 1 0 - 64 data length code 18 1 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-5 v1.1, 2011-03 multican, v3.0 significant section (as in standard can frame) and an 18-bit most significant section, ensures that the identifier extension bit (ide) can remain at the same bit position in both standard and extended frames. in the extended can data frame, the sof bit is followed by the 32-bit arbitration field. the first 11 bits are the least significant bits of the 29-bit identifier (?base-id?). these 11 bits are followed by the recessive substitute remote request (srr) bit. the srr is further followed by the recessive ide bit, which indicates the frame to be an extended can frame. if arbitration remains unresolved after transmission of the first 11 bits of the identifier, and if one of the nodes involved in arbitration is sending a standard can frame, then the standard can frame will win arbitration due to the assertion of its dominant ide bit. therefore, the srr bit in an extended can frame is recessive to allow the assertion of a dominant rtr bit by a node that is sending a standard can remote frame. the srr and ide bits are followed by the remaining 18 bits of the extended identifier and the rtr bit. control field and frame termination is identical to the standard data frame. 24.1.2.2 remote frames normally, data transmission is performed on an autonomous basis with the data source node (e.g. a sensor) sending out a data frame. it is also possible, however, for a destination node (or nodes) to request the data from the source. for this purpose, the destination node sends a remote frame with an identifier that matches the identifier of the required data frame. the ap propriate data source node will then send a data frame as a response to this remote request. there are 2 differences between a remote frame and a data frame. ? the rtr bit is in the recessi ve state in a remote frame. ? there is no data field in a remote frame. if a data frame and a remote frame with the same identifier are transmitted at the same time, the data frame wins arbitration due to the dominant rtr bit following the identifier. in this way, the node that transmitted the remote frame receives the requested data immediately. the format of a standard and extended remote frames is shown in figure 24-2 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-6 v1.1, 2011-03 multican, v3.0 figure 24-2 can remote frame bus idle bus idle dominant level recessive level bus idle bus idle dominant level recessive level mct06259 11 standard remote frame ack delimiter ack slot crc delimiter crc sequence data length code reserved (d) ide bit (d) rtr bit (d) identifier 4 1 1 11 1 1 15 start of frame control fiel d arbitration field (12 bit ) 1 7 3 inter frame space end of frame (eof) acknowledg e field crc field 11 4 1 11 1 1 15 1 7 3 18 2 1 extended remote frame srr bit (r) ide bit (r) 29-bit identfier arbitration field (32 bit ) rtr bit (d) 2 reserved (d) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-7 v1.1, 2011-03 multican, v3.0 24.1.2.3 error frames an error frame is generated by any node that detects a bus error. an error frame consists of two fields, an error flag field followed by an error delimiter field. the error delimiter field consists of 8 recessive bits and allows the bus nodes to restart bus communications after an error. there are, however, two forms of error flag fields. the form of the error flag field depends on the error status of the node that detects the error. when an error-active node detects a bus error, the node generates an error frame with an active-error flag. the error-active flag is composed of six consecutive dominant bits that actively violate the bit-stuffing rule. all other stations recognize a bit-stuffing error and generate error frames themselves. the resulting error flag field on the can bus therefore consists of six to twelve consecut ive dominant bits (generated by one or more nodes). the error delimiter field completes the error frame. after completion of the error frame, bus activity returns to normal and the interrupted node attempts to re-send the aborted message. if an error-passive node detects a bus error, the node transmits an error-passive flag followed, again, by the error delimiter field. the error-passive flag consists of six consecutive recessive bits, and therefore the error frame (for an error-passive node) consists of 14 recessive bits (i.e. no domi nant bits). therefore, the transmission of an error frame by an error-passive node will not affect any other node on the network, unless the bus error is detected by the node that is actually transmitting (i.e. the bus master). if the bus master node generates an error-passive flag, this may cause other nodes to generate error frames due to the resulting bit-stuffing violation. after transmission of an error frame an error-passive node must wait for 6 consecutive recessive bits on the bus before attempting to rejoin bus communications. figure 24-3 can error frames bus idle bus idle dominant leve l recessive lev el mct06260 error frame of "error active" node 6 8 error delimiter field error flag field bus idle bus idle dominant leve l recessive lev el 6 8 error frame of "error passive" node www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-8 v1.1, 2011-03 multican, v3.0 24.1.3 the nominal bit time one bit cell (this means one high or low pulse of the nrz code) is composed by four segments. each segment is an integer multiple of time quanta t q . the time quanta is the smallest discrete timing resolution used by a can node. the nominal bit time definition with its segments is shown in figure 24-4 . figure 24-4 partition of nominal bit time the synchronization segment (sync_seg) is used to synchronize the various bus nodes. if there is a bit state change between the previous bit and the current bit, then the bus state change is expected to occur within this segment. the length of this segment is always 1 t q . the propagation segment (prop_seg) is used to compensate for signal delays across the network. these delays are caused by signal propagation delay on the bus line and through the electronic interface circuits of the bus nodes. the phase segments 1 and 2 (phase_seg1, phase_seg2) are used to compensate for edge phase errors. these segments can be lengthened or shortened by re- synchronization. phase_seg2 is reserved for calculation of the subsequent bit level, and is 2 t q . at the sample point, the bus level is read and interpreted as the value of the bit cell. it occurs at the end of phase_seg1. the total number of t q in a bit time is between 8 and 25. as a result of re-synchronization, phase_seg1 can be lengthened or phase_seg2 can be shortened. the amount of lengthening or shortening the phase buffer segments has an upper limit given by the re-synchr onization jump width. the re-synchronization jump width may be between 1 and 4 t q , but it may not be longer than phase_seg1. mca06261 sample point synchronisation segment (sync_seg) propagation segment (prop_seg) phase buffer segment 1 (phase_seg1) phase buffer segment 2 (phase_seg2) nominal bit time www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-9 v1.1, 2011-03 multican, v3.0 24.1.4 error detection and error handling the can protocol has sophisticated error detection mechanisms. the following errors can be detected: ? cyclic redundancy check (crc) error with the cyclic redundancy check, the transmitter calculates special check bits for the bit sequence from the start of a frame until the end of the data field. this crc sequence is transmitted in the crc field. the receiving node also calculates the crc sequence using the same formula, and performs a comparison to the received sequence. if a mismatch is detected, a crc error has occurred and an error frame is generated. the message is repeated. ? acknowledge error in the acknowledge field of a message, the transmitter checks whether a dominant bit is read during the acknowledge slot (that is sent out as a recessive bit). if not, no other node has received the frame correctly, an acknowledge error has occurred, and the message must be repeated. no error frame is generated. ? form error if a transmitter detects a dominant bit in one of the four segments end of frame, interframe space, acknowledge delimiter, or crc delimiter, a form error has occurred, and an error frame is generated. the message is repeated. ? bit error a bit error occurs if a) a transmitter sends a dominant bit and detects a recessive bit or b) if the transmitter sends a recessive bit and detects a dominant bit when monitoring the actual bus level and comparing it to the just transmitted bit. in case b), no error occurs during the arbitration field (id, rtr, ide) and the acknowledge slot. ? stuff error if between start of frame and crc delimiter, six consecutive bits with the same polarity are detected, the bit-stuffing rule has been violated. a stuff error occurs and an error frame is generated. the message is repeated. detected errors are made public to all other nodes via error frames (except acknowledge errors). the transmission of the erroneous message is aborted and the frame is repeated as soon as possible. furthermore, each can node is in one of the three error states (error-active, error-passive or bus-off) according to the value of the internal error counters. the error-active state is the usual state where the bus node can transmit messages and active-error frames (made of dominant bits) without any restrictions. in the error-passive state, messages and passive-error frames (made of recessive bits) may be transmitted. the bus-of f state makes it temporarily impossible for the node to participate in the bus communica tion. during this state, messages can be neither received nor transmitted. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-10 v1.1, 2011-03 multican, v3.0 basic can, full can there is one more can characteristic that is related to the interface of a can module (controller) and the host cpu: basic-can and full-can functionality. in basic-can devices, only basic functions of the protocol are implemented in hardware, such as the generation and the check of the bit stream. the decision, whether a received message has to be stored or not (acceptance filtering), and the complete message management must be done by software. norma lly, the can device also provides only one transmit buffer and one or two receive buffe rs. therefore, the host cpu load is quite high when using basic-can modules. the ma in advantage of basic-can is a reduced chip size leading to low costs of these devices. full-can devices (this is the case for the multican controller as implemented in TC1798) manage the whole bus protocol in hardware, including the acceptance filtering and message management. full-can devices contain message objects that handle autonomously the identifier, the data, the direction (receive or transmit) and the information of standard can/extended can operation. during the initialization of the device, the host cpu determines which messages are to be sent and which are to be received. the host cpu is informed by interrupt if the identifier of a received message matches with one of the programmed (receive-) message objects. the cpu load of full- can devices is greatly reduced. when using full-can devices, high baud rates and high bus loads with many messages can be handled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-11 v1.1, 2011-03 multican, v3.0 24.2 ttcan basics in general, a can network is event-oriented due to the error handling and bus arbitration. the exact time for a message to be transferred is difficult to determine. in order to allow deterministic message transfers, the event-driven mechanism has been changed into a time-driven mechanism by a ttcan extension, with ?tt? standing for time-triggered. ttcan is a higher-layer protocol above the standard can protocol that synchronizes the communication schedules of all can nodes in a can network, and that provides a global system time. when can nodes are sy nchronized, messages can be transmitted at a specific time slot, without competing with other messages for the bus. thus, the loss of arbitration is avoided, and the latency time becomes predictable. apart from the synchronized communication schedule, ttcan-compliant nodes operate according to the standard can protocol as defined by iso 11898-4. 24.2.1 time reference in ttcan networks, a global time reference makes it possible to synchronize the activities of all can nodes. each can node has its own local time represented by a counter that is incremented with each networ k time unit (ntu). the ntu is derived from the node?s local clock and local time unit ratio (tur). in ttcan, synchronization is achieved by a periodic transmission of a reference message. this reference message (transmitted by a time master) restarts the cycle time in each node. the reference message can be ea sily recognized by its identifier. within ttcan level 1, the reference message holds control information in one byte of the message data field. in ttcan level 2, the reference message provides additional control information in four bytes of the message data field (e.g. the global time information of the current ttcan time master) with downwards compatibility. 24.2.2 basic cycle a reference message starts a new basic cycle and resets the cycle time. the cycle time counts the time since the start of the basi c cycle. a basic cycle consists of several non- overlapping time windows of different size s. the sequence of the time windows is described by time marks that determine when a time window begins. time marks are compared to the cycle time, and particula r actions are triggered when the cycle time matches the time mark. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-12 v1.1, 2011-03 multican, v3.0 figure 24-5 ttcan basic cycle the structure of the basic cycle is defined once for the whole ttcan network. several different basic cycles are combined to build a matrix cycle or the system matrix. the sequence of basic cycles in the matrix cycl e is controlled by th e reference messages. all possible messages in the ttcan system ar e assigned to time windows of the system matrix. a time window can be: ? an exclusive time window, in which only one particular message can be transmitted. ? an arbitrating time window, in which messages can arbitrate for bus access. ? a free time window, reserved for future extensions. in exclusive time windows automatic retransmission of messages is disabled. this guarantees that messages are not delayed by other bus traffic. 24.2.3 global system time level 2 of ttcan supports a global system ti me. the time master establishes its own local time as global time by transmitting reference message. the other can nodes in the network operate as time slaves that calculate their local time offset to the global time by comparing their local time with the received global time. to compensate for slightly different clock drifts in the can nodes and to provide a consistent view of the global time, the nodes can perform a drift compensation operation. they compare the length of the basic cycle in local time to the length of the basic cycle in global time. the difference (quotient) of the two values gives the adapted tur. 24.2.4 the system matrix typical can applications includ e many control loops and tasks with different periods. all of them need individual sending patterns for their information. one ttcan basic cycle would not offer enough flexibility to sa tisfy this needs. therefore, the ttcan specification also makes it possible to use more than one basic cycle to build the communication matrix or system matrix. seve ral different basic cycles are connected together to build the matrix cycle. most comb inations of basic cycles are possible, such mca0583 1 reference message tim e basic cycle exclusive window arbitration window free window exclusive window reference message time windows www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-13 v1.1, 2011-03 multican, v3.0 as sending every basic cycle, sending ever y second basic cycle, or sending only once within the matrix cycle. 24.2.5 generation of the network time unit (ntu) the granularity of any timing information wi thin ttcan is the ntu. the cycle time is measured in ntu that is based on the nominal can bit time (ttcan level 1), or on the time quantum t q (ttcan level 2), or on the can input frequency. in level 2, the node?s local relation between the physical oscillator of a ttcan controller and the system wide ntu must be established. a clock signal in the node provides the system clock to a frequency divider. this fr equency divider gener ates the system-wide ntu while a node local tur takes care for the correct re lationship between the system clock and ntu. ntu now can be used to calculate a local time and to build the global time. 24.2.6 global time genera tion and drift correction the node sending the reference message is the time master in the ttcan network. the reference message includes the time master?s (by definition correct) global time value for frame synchronization. all nodes take a snap-shot of their time values at the sof bit sample point of the received reference message. after reference message reception, each node can calculate its local offset that indicates the difference between the master global time value and the own local time value. in the current basic cycle, the node can compute the global time fo r the next basic cycle by: global time = local time + local offset this equation ensures that all nodes have a consistent global time. due to slightly different clock drifts of the different nodes in a can network, a mechanism is established that guarantees that local and global time run in parallel. this mechanism is the continuous update of the tur. the initial value of tur is locally known in the node by the node clock signal specification. during node operation, the node locally measures the length between two successive reference messages in number of oscillator periods and in local time. the quotient of these two values gives the actual tur. the achievable precision determines a reasonable choice of the ntu value in physical seconds. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-14 v1.1, 2011-03 multican, v3.0 24.3 overview this section describes the serial communication module called multican (can = controller area network) of the TC1798. a multican module can contain between two and eight independent can nodes, depending on the device, each representing one serial communication interface. figure 24-6 overview of the mult ican module with ttcan extension multica n module k ernel multican_overview_notsingle_v2.vsd clock control a ddress decoder interrupt control f fpi port control can node 1 can control message object buffer m objects txdc0 rxdc0 timing control and s ynchronization s cheduler s chedule memory time - triggered e xtension can node 0 can node n - 1 txdc1 rxdc1 txdc n-1 linked list control ectt[7:1] rxdc n-1 . . . . . . . . . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-15 v1.1, 2011-03 multican, v3.0 24.3.1 multican module the multican module contains independently operating can nodes with full-can functionality that are able to exchange data and remote frames via a gateway function. transmission and reception of can fram es is handled in accordance with can specification v2.0 b (active). each can node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. both can nodes share a common set of message objects. each message object can be individually allocated to one of the can nodes. besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the can nodes or to setup a fifo buffer. the message objects are organized in doubl e-chained linked lists, where each can node has its own list of message objects. a can node stores frames only into message objects that are allocated to the message object list of the can node, and it transmits only messages belonging to this message obj ect list. a powerful, command-driven list controller performs all message object list operations. the bit timings for the can nodes are derived from the module timer clock ( f can ), and are programmable up to a data rate of 1 mbit/s. external bus transceivers are connected to a can node via a pair of receive and transmit pins. features ? compliant with iso 11898 ? can functionality according to can specification v2.0 b active ? dedicated control registers for each can node ? data transfer rates up to 1 mbit/s ? flexible and powerful message transfer control and error handling capabilities ? advanced can bus bit timing analysis and baud rate detection for each can node via a frame counter ? full-can functionality: a set of message objects can be individually ? allocated (assigned) to any can node ? configured as transmit or receive object ? set up to handle frames with 11-bit or 29-bit identifier ? identified by a timestamp via a frame counter ? configured to remote monitoring mode ? advanced acceptance filtering ? each message object provides an individual acceptance mask to filter incoming frames ? a message object can be configured to a ccept standard or extended frames or to accept both standard and extended frames ? message objects can be grouped into four priority classes for transmission and reception www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-16 v1.1, 2011-03 multican, v3.0 ? the selection of the message to be transmitted first can be based on frame identifier, ide bit and rtr bit according to can arbitration rules, or according to its order in the list ? advanced message object functionality ? message objects can be combined to build fifo message buffers of arbitrary size, limited only by the total number of message objects ? message objects can be linked to form a gateway that automatically transfers frames between two different can buses. a single gateway can link any two can nodes. an arbitrary number of gateways can be defined. ? advanced data management ? the message objects are organized in double-chained lists ? list reorganizations can be performed at an y time, even during full operation of the can nodes ? a powerful, command-driven list controller manages the organization of the list structure and ensures consistency of the list ? message fifos are based on the list structure and can easily be scaled in size during can operation ? static allocation commands offer compatibility with twincan applications that are not list-based ? advanced interrupt handling ? up to 16 interrupt output lines are available. interrupt requests can be routed individually to one of the 16 interrupt output lines ? message post-processing notifications can be mapped flexibly using dedicated registers consisting of notification bits www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-17 v1.1, 2011-03 multican, v3.0 24.4 time-triggered extension (ttcan) in addition to the event-driven can functionality, a deterministic behavior can be achieved for can node 0 by an extension module that supports ttcan functionality. the ttcan protocol is compliant with t he confirmed standardization proposal for iso 11898-4 and fully conforms to the existing can protocol. the time-triggered functionality is added as higher-layer extension (session layer) to the can protocol in order to be able to operat e in safety-critical applications. the new features allow for deterministic behavior of a can network and the synchronization of networks. global time information is availabl e. the time-triggered extension is based on a scheduler mechanism with a timing control unit and a dedicated timing data part. ttcan features ? full support of basic cycle and system matrix functionality ? support of reference messages level 1 and level 2 ? usable as time master ? arbitration windows supported in time-triggered mode ? global time information available ? can node 0 can be configured either for event-driven or time-triggered mode ? built-in scheduler mechanism and a timing synchronization unit ? write protection for scheduler timing data memory ? timing-related interrupt functionality ? parity protection for scheduler memory www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-18 v1.1, 2011-03 multican, v3.0 24.5 multican kernel functional de scription this section describes the functionality of the multican module. 24.5.1 module structure figure 24-7 shows the general structure of the multican module. figure 24-7 multican block diagram can nodes each can node consists of several sub-units. ? bitstream processor the bitstream processor performs data, remote, error and overload frame processing according to the iso 11898 standard. this includes conversion between the serial data stream and the input/output registers. ? bit timing unit the bit timing unit determines the length of a bit time and the location of the sample point according to the user settings, taking into account propagation delays and phase shift errors. the bit timing unit also performs resynchronization. mult ican_blockdiag_x. vsd can bus 0 message controller can node 0 can bus 1 can node 1 . . . can bus x-1 list control logic message ram address decoder interrupt control logic can node x-1 b itstream processor bit timing unit error handling unit node control unit frame counter interrupt control unit bus interface interrupt control . . . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-19 v1.1, 2011-03 multican, v3.0 ? error handling unit the error handling unit manages the receive and transmit error counter. depending on the contents of both counters, the can node is set into an error-active, error passive or bus-off state. ? node control unit the node control unit coordinates the operation of the can node: ? enable/disable can transfer of the node ? enable/disable and generate node-specific events that lead to an interrupt request (can bus errors, successful frame transfers etc.) ? administration of the frame counter ? interrupt control unit the interrupt control unit in the can node controls the interrupt generation for the different conditions that can occur in the can node. message controller the message controller handles the exchange of can frames between the can nodes and the message objects that are stored in the message ram. the message controller performs several functions: ? receive acceptance filtering to determine the correct message object for storing of a received can frame ? transmit acceptance filtering to determine the message object to be transmitted first, individually for each can node ? transfer contents between message objects and the can nodes, taking into account the status/control bits of the message objects ? handling of the fifo buffering and gateway functionality ? aggregation of message-pending notification bits list controller the list controller performs all operations that lead to a modification of the double- chained message object lists. only the list c ontroller is allowed to modify the list structure. the allocation/deallocation or reallocation of a message object can be requested via a user command interface (c ommand panel). the list controller state machine then performs the requested command autonomously. interrupt control the general interrupt structure is shown in figure 24-9 . the interrupt event can trigger the interrupt generation. the interrupt pulse is generated independently of the interrupt flag in the interrupt status register. the interrupt flag can be reset by software by writing a 0 to it. if enabled by the related interrupt enable bit in the interrupt enable register, an interrupt pulse can be generated at one of the 16 interrupt output lines int_om of the multican www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-20 v1.1, 2011-03 multican, v3.0 module. if more than one interrupt source is connected to the same interrupt node pointer (in the interrupt node pointer register), the requests are combined to one common line. figure 24-8 general interrupt structure mca06264 interrupt flag writing 0 interrupt enable & interrupt event set reset other interrupt s ources on the same inp inp 1 to int_o0 to int_o1 ..... to int_o1 5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-21 v1.1, 2011-03 multican, v3.0 24.5.2 clock control the can module timer clock f can of the functional blocks of the multican module is derived from the module control clock f clc . the fractional divider is used to generate f can used for bit timing calculation, the generation of the ntu, and the local time of the ttcan part. the frequency of f can is identical for all can nodes. the register file and the ttcan scheduler operate with the module control clock f clc . see also ?module clock generation? on page 24-204 . the output clock f can of the fractional divider is based on the system clock f clc , but only every n-th clock pulse is taken. the suspend signal (coming as acknowledge from the multican module in response to a ocds suspend request) freezes or resets the fractional divider. figure 24-9 multican clock generation mca06265 fractional divider module kernel f can clock control register f clc f fpi baud rate prescalers register file www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-22 v1.1, 2011-03 multican, v3.0 figure 24-10 multican with ttcan clock generation table 24-2 indicates the minimum operating frequencies in mhz for f clc that are required for a baud rate of 1 mbit/s for the active can nodes. if a lower baud rate is desired, the values can be scaled linearly (e.g. for a maximum of 500 kbit/s, 50% of the indicated value are required). the values imply that the cpu (or dma) executes maximum accesses to the multican module. the values may contain rounding effects. mca05835 fractional divider baud rate prescalers module k ernel local time control f can clock control register f clc f fpi register file ttcan s cheduler t q www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-23 v1.1, 2011-03 multican, v3.0 the baud rate generation of the multican being based on f fpi , this frequency has to be chosen carefully to allow correct can bit timing. the required value of f fpi is given by an integer multiple (n) of the can baud rate multiplied by the number of time quanta per can bit time. for example, to reach 1 mbit/s with 20 tq per bit time, possible values of f fpi are given by formula [n 20] mhz, with n being an integer value, starting at 1. in order to minimize jitter, it is not recommended to use the fractional divider mode for high baud rates. 24.5.3 port input control it is possible to select the input lines for the rxdcanx inputs for the can nodes. the selected input is connected to the can node and is also available to wake-up the system. more details are defined in section 24.11.4.2 on page 24-208 . 24.5.4 suspend mode the suspend mode can be triggered by the ocds in order to freeze the state of the module and to permit access to the registers (at least for read actions). the multican module provides two types of suspend modes: ? all actions are immediately stopped (hard suspend mode): the module clocks f clc and f can are switched off as soon as the suspend request becomes active. read and write operations to the module are no longer possible. this means that the can registers cannot be accessed anymore. in this mode, there is a very high probability that the communication with other can devices is made table 24-2 minimum operating frequencies [mhz] number of allocated message objects mo 1) , with or without ttcan functionality 1) only those message objects have to be taken into account that are allocated to a can node. the unallocated message objects have no influence on the minimum operating frequency. 1 can node active 2 can nodes active 3 can nodes active 4 can nodes active 16 mo, without ttcan 12 19 26 33 16 mo, with 1 ttcan 14 21 28 35 32 mo, without ttcan 15 23 30 37 32 mo, with 1 ttcan 17 25 32 39 64 mo, without ttcan 21 28 37 46 64 mo, with 1 ttcan 23 30 39 48 128 mo, without ttcan 40 45 50 55 128 mo, with 1 ttcan 42 47 52 57 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-24 v1.1, 2011-03 multican, v3.0 impossible, and that the can bus is blocked (e.g. if the suspended can module just sends a dominant level). a reset operation must be executed to leave hard suspend mode. ? the current action is finished (soft suspend mode): the module clock f clc keeps running. module functions are stopped automatically after internal actions have been finished (f or example, after a can frame has been sent out). the end of the internal actions is indicated to the fractional divider by a suspend mode acknowledged signal. due to this behavior, the communication network is not blocked. furthermore, all registers are accessible for read and write actions. as a result, the debugger can stop the module actions and modify registers. these modifications are taken into account after the suspend mode is left. the hard suspend mode can be enabled/disabled only for the complete multican module. the soft suspend mode can be individually enabled for each can node. the fractional divider disables module clock f can only if all can nodes signal that they can be suspended. a can node that is not active can always be suspended. the user has to be aware that the soft suspend mode can corrupt the ttcan timing values, because the counter clock can be dis abled. in order to guarantee correct ttcan behavior, a ttcan node should not enter any suspend mode if the consistency of the timing data must be ensured. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-25 v1.1, 2011-03 multican, v3.0 24.5.5 can node control each can node may be configured and run independently of the other can node. each can node is equipped with its own node control logic to configure the global behavior and to provide status information. note: in the following descriptions, index ?x? stands for the node number and index ?n? represents the message object number. configuration mode is activated when bit ncrx .cce is set to 1. this mode allows can bit timing parameters and the error counter registers to be modified. can analyze mode is activated when bit ncrx. calm is set to 1. in this operation mode, data and remote frames are monitored withou t active participation in any can transfer (can transmit pin is held on recessive level). incoming remote frames are stored in a corresponding transmit message object, while arriving data frames are saved in a matching receive message object. in can analyze mode, the entire configuration information of the received frame is stored in the corresponding message object, and can be evaluated by the cpu to determine their identifier, xtd bit information and data length code (id and dlc optionally if the remote monitoring mode is active, bit mofcrn.rmm = 1). incoming frames are not acknowledged, and no error frames are generated. if can analyze mode is enabled, remote frames are not responded to by the corresponding data frame, and data frames cannot be transmitted by setting the transmit request bit mostatn.txrq. receive interrupts are gen erated in can analyze mode (if enabled) for all error free received frames. the node-specific interrupt configuration is also defined by the node control logic via the ncrx register bits trie, alie and lecie: ? if control bit trie is set to 1, a transfer interrupt is generated when the nsrx register has been updated (after each successfully completed message transfer). ? if control bit alie is set to 1, an error interrupt is generated when a ?bus-off? condition has been recognized or the error warn ing level has been e xceeded or under-run. additionally, list or object errors lead to this type of interrupt. ? if control bit lecie is set to 1, a last error code interrupt is generated when an error code > 0 is written into bit field nsrx.lec by hardware. the node x status register nsrx provides an overview about the current state of the respective can node x, comprising information about can transfers, can node status, and error conditions. the can frame counter can be used to check the transfer sequence of message objects or to obtain information about the instant a frame has been transmitted or received from the associated can bus. can frame co unting is performed by a 16-bit counter, controlled by register nfcrx. bit fields nfcrx.cfmod and nfcrx.cfsel determine the operation mode and the trigger event incrementing the frame counter. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-26 v1.1, 2011-03 multican, v3.0 24.5.5.1 bit timing unit according to the iso 11898 standard, a can bit time is subdivided into different segments ( figure 24-11 ). each segment consists of multiples of a time quantum t q . the magnitude of t q is adjusted by node x bit timing register bit fields nbtrx.brp and nbtrx.div8, both controlling the baud rate prescaler (register nbtrx is described on page 24-87 ). the baud rate prescaler is driven by the module timer clock f can (generation and control of f can is described on page 24-204 ). figure 24-11 can bus bi t timing standard the synchronization segment (t sync ) allows a phase synchronization between transmitter and receiver time base. the synchronization segment length is always one t q . the propagation time segment (t prop ) takes into account the physical propagation delay in the transmitter output driver on the can bus line and in the transceiver circuit. for a working collision detection mechanism, t prop must be two times the sum of all propagation delay quantities rounded up to a multiple of t q . the phase buffer segments 1 and 2 (t b1 , t b2 ) before and after the signal sample point are used to compensate for a mismatch between transmitter and receiver clock phases detected in the synchronization segment. the maximum number of time quanta allowed for re-synchronization is defined by bit field nbtrx.sjw. the propagation time se gment and the phase buffer segment 1 are combined to parameter t seg1 , which is defined by the value nbtrx.tseg1. a minimum of 3 time quanta is demanded by the iso standard. parameter t seg2 , which is defined by the value of nbtrx.tseg2, covers the phase buffer segment 2. a minimum of 2 time quanta is demanded by the iso standard. according to iso standard, a can bit time, calculated as the sum of t sync , t seg1 and t seg2 , must not fall below 8 time quanta. mct06266 sync. seg t sync t prop t b1 t b2 t seg2 t seg1 1 bit time sample point transmit poi nt 1 time quantum ( t q ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-27 v1.1, 2011-03 multican, v3.0 calculation of the bit time: to compensate phase shifts between clocks of different can controllers, the can controller must synchronize on any edge from the recessive to the dominant bus level. if the hard synchronization is enabled (at the start of frame), the bit time is restarted at the synchronization segment. otherwise, the re-synchronization jump width t sjw defines the maximum number of time quanta, a bit time may be shortened or lengthened by one re-synchronization. the value of sjw is defined by bit field nbtrx.sjw. the maximum relative tolerance for f can depends on the phase buffer segments and the re-synchronization jump width. a valid can bit timing must be written to the can node bit timing register nbtr before resetting the init bit in the node control register, i.e. before enabling the operation of the can node. the node bit timing register may be written only if bit cce (configuration change enable) is set in the corresponding node control register. 24.5.5.2 bitstream processor based on the message objects in the message buffer, the bitstream processor generates the remote and data frames to be tr ansmitted via the can bus. it controls the crc generator and adds the checksum information to the new remote or data frame. after including the sof bit and the eof field, the bitstream processor starts the can t q = (brp + 1) / f can if div8 = 0 = 8 (brp + 1) / f can if div8 = 1 t sync = 1 t q t seg1 = (tseg1 + 1) t q (min. 3 t q ) t seg2 = (tseg2 + 1) t q (min. 2 t q ) bit time = t sync + t seg1 + t seg2 (min. 8 t q ) t sjw = (sjw + 1) t q t seg1 t sjw + t prop t seg2 t sjw d f can min (t b1 , t b2 ) / 2 (13 bit time - t b2 )and d f can t sjw / 20 bit time www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-28 v1.1, 2011-03 multican, v3.0 bus arbitration procedure and continues with the frame transmission when the bus was found in idle state. while the data transmission is running, the bitstream processor continuously monitors the i/o line. if (o utside the can bus arbitration phase or the acknowledge slot) a mismatch is detected between the voltage level on the i/o line and the logic state of the bit currently sent out by the transmit shift register, a can error interrupt request is generated, and the error code is indicated by the node x status register bit field nsrx.lec. the data consistency of an incoming frame is verified by checking the associated crc field. when an error has been detected, a can error interrupt request is generated and the associated error code is presented in the node x status register nsrx. furthermore, an error frame is generat ed and transmitted on the can bus. after decomposing a faultless frame into identifier and data portion, the received information is transferred to the message buffer executing remote and data frame handling, interrupt generation and status processing. 24.5.5.3 error handling unit the error handling unit of a can node x is responsible for the fault confinement of the can device. its two counters, the receive error counter rec and the transmit error counter tec (bit fields of the node x error counter register necntx, see page 24-89 ) are incremented and decremented by commands from the bitstream processor. if the bitstream processor itself detects an error while a transmit operation is running, the transmit error counter is incremented by 8. an increment of 1 is used when the error condition was reported by an external can node via an error frame generation. for error analysis, the transfer direction of the disturbed message and the node that recognizes the transfer error are indicated for the respective can node x in register necntx. depending on the values of the error counters, the can node is set into error- active, error-passive, or bus-off state. the can node is in error-active state if both error counters are below the error-passive limit of 128. the can node is in error-passive state, if at least one of the error counters is equal to or greater than 128. the bus-off state is activated if the transmit error counter is equal to or greater than the bus-off limit of 256. this state is reported for can node x by the node x status register flag nsrx.boff. the device remains in this state, until the ?bus-off? recovery sequence is finished. additionally, node x status regi ster flag nsrx.ewrn is set when at least one of the error counters is equal to or greater than the error warning limit defined by the node x error count register bit field necntx.ewrnlvl. bit nsrx.ewrn is reset if both error counters fall below the error warning limit again (see page 24-77 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-29 v1.1, 2011-03 multican, v3.0 24.5.5.4 can frame counter each can node is equipped with a frame coun ter that counts transmitted/received can frames or obtains information about the time when a frame has been started to transmit or be received by the can node. can frame counting/bit time counting is performed by a 16-bit counter that is controlled by no de x frame counter register nfcrx (see page 24-90 ). bit field nfcrx.cfsel determines the operation mode of the frame counter: ? frame count mode: after the successful transmission and/or reception of a can frame, the frame counter is copied into the cfcval bit field of the moiprn register of the message object involved in the transfer. afterwards, the frame counter is incremented. ? time stamp mode: the frame counter is incremented with the beginning of a new bit time. when the transmission/reception of a frame starts, the value of the frame counter is captured and stored to the cfc bit field of the nfcrx register. after the successful transfer of the frame the captured value is copied to the cfcval bit field of the moiprn register of the message object involved in the transfer. ? bit timing mode: used for baud rate detection and analysis of the bit timing ( chapter 24.5.7.3 ). 24.5.5.5 can node interrupts each can node has four hardware triggered interrupt request types that are able to generate an interrupt request upon: ? the successful transmission or reception of a frame ? a can protocol error with a last error code ? an alert condition: transmit/receive error counters reach the warning limit, bus-off state changes, a list length error occurs, or a list object error occurs ? an overflow of the frame counter besides the hardware generated interrupts, software initiated interrupts can be generated using the module interrupt trigger register mitr. writing a 1 to bit n of bit field mitr.it generates an interrupt request signal on the corresponding interrupt output line int_on. when writing mitr.it more than one bit can be set resulting in activation of multiple int_on interrupt output lines at the same time. see also ?interrupt control? on page 24-211 for further processing of the can node interrupts. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-30 v1.1, 2011-03 multican, v3.0 figure 24-12 can node interrupts mca06267 trie trinp txok rxok receive transmit c orrect message o bject transfer lecie lecinp lec can error ewrn boff alinp alie alert lle loe l ist length error l ist object error cfcie cfcinp cfcov f rame counter o verflow/event nsrx nsrx ncrx niprx niprx niprx niprx nsrx nsrx ncrx ncrx nsrx nsrx nsrx nfcrx nfcrx 1 1 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-31 v1.1, 2011-03 multican, v3.0 24.5.6 message object list structure this section describes the structure of the message object lists in the multican module. 24.5.6.1 basics the message objects of the multican module are organized in double-chained lists, where each message object has a pointer to the previous message object in the list as well as a pointer to the next message object in the list. the multican module provides eight lists. each message object is allocated to one of these lists. in the example in figure 24-13 , the three message objects (3, 5, and 16) are allocated to the list with index 2 (list register list2). figure 24-13 example allocation of message objects to a list bit field begin in the list register (for definition, see page 24-71 ) points to the first element in the list (object 5 in the example), and bit field end points to the last element in the list (object 3 in the example). the number of elements in the list is indicated by bit field size of the list register (size = number of list elements - 1, thus size = 2 for the 3 elements in the example). the empty bit of the list register indicates whether or not a list is empty (empty = 0 in the example, because list 2 is not empty). each message object n has a pointer pnext in its message object n control register moctrn (see page 24-94 ) that points to the next message object in the list, and a pointer pprev that points to the previous message object in the list. pprev of the first message object points to the message object itself because the first message object has no predecessor (in the example message object 5 is the first message object in the list, mca06268 message object 5 message object 16 message object 3 pprev = 16 pnext = 3 list = 2 register list2 empty = 0 begin = 5 end = 3 size = 2 pprev = 5 pnext = 3 list = 2 pprev = 5 pnext = 16 list = 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-32 v1.1, 2011-03 multican, v3.0 indicated by pprev = 5). pnext of the last message object also points to the message object itself because the last message object has no successor (in the example, object 3 is the last message object in the list, indicated by pnext = 3). bit field moctrn.list indicates the list i ndex number to which the message object is currently allocated. the message object of th e example are allocated to list 2. therefore, all list bit fields for the message objects assigned to list 2 are set to list = 2. 24.5.6.2 list of unallocated elements the list with list index 0 has a special meaning: it is the list of all unallocated elements. an element is called unallocated if it belo ngs to list 0 (moctrn.list = 0). it is called allocated if it belongs to a list with an index not equal to 0 (moctrn.list > 0). after reset, all message objects are unallocated. this means that they are assigned to the list of unallocated elements with moctrn.list = 0. after this initial allocation of the message objects caused by reset, the list of all unallocated message objects is ordered by message number (predecessor of message object n is object n-1, successor of object n is object n+1). 24.5.6.3 connection to the can nodes each can node is linked to one unique list of message objects. a can node performs message transfer only with the message objects that are allocated to the list of the can node. this is illustrated in figure 24-14 . frames that are received on a can node may only be stored in one of the message objects that belongs to the can node; frames to be transmitted on a can node are selected only from the message objects that are allocated to that node, as indicated by the vertical arrows. there are more lists (eight) than can nodes (two). this means that some lists are not linked to one of the can nodes. a message object that is allocated to one of these unlinked lists cannot receive messages directly from a can node and it may not transmit messages. fifo and gateway mechanisms refer to message numbers and not directly to a specific list. the user must take care that the message objects targeted by fifo/gateway belong to the desired list. the mechanisms make it possible to work with lists that do not belong to the can node. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-33 v1.1, 2011-03 multican, v3.0 figure 24-14 message objects linked to can nodes 24.5.6.4 list command panel the list structure cannot be modified directly by write accesses to the list registers and the pprev, pnext and list bit fields in the message object control registers, as they are read only. the list structure is managed by and limited to the list controller inside the multican module. the list controller is controlled via a command panel allowing the user to issue list allocation commands to the list controller. the list controller has two main purposes: 1. ensure that all operations that modify the list structure result in a consistent list structure. 2. present maximum ease of us e and flexibility to the user. the list controller and the associated command panel allows the programmer to concentrate on the final properties of the lis t, which are characterized by the allocation of message objects to a can node, and the ordering relation between objects that are allocated to the same list. the process of list (re-)building is done in the list controller. mult ican_list _t o_can_x. vsd can node 0 1st object in list 1 2nd object in list 1 last object in list 1 can node 1 1st object in list 2 2nd object in list 2 last object in list 2 can node x-1 1st object in list x 2nd object in list x last object in list x can bus 0 can bus 1 . . . can bus x-1 . . . list of all unallocated elements 1st object in list 0 2nd object in list 0 last object in list 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-34 v1.1, 2011-03 multican, v3.0 table 24-3 gives an overview on the available panel commands while table 24-7 on page 24-66 describes the panel commands in more detail. a panel command is started by writing the respective command code into the panel control register bit field panctr.pancmd (see page 24-65 ). the corresponding command arguments must be written into bit fields panctr.panar1 and panctr.panar2 before writing the command code, or latest along with the command code in a single 32-bit write access to the panel control register. with the write operation of a valid command code, the panctr.busy flag is set and further write accesses to the panel control register are ignored. the busy flag remains active and the control panel remains locked until the execution of the requested command has been completed. after a reset, the list controller builds up list 0. during this operation, busy is set and other accesses to the can ram are forbidden. the can ram can be accessed again wh en busy becomes inactive. note: the can ram is automatically initializ ed after reset by the list controller in order to ensure correct list pointers in each message object. the end of this can ram initialization is indicated by bit panctr.busy becoming inactive. in case of a dynamic allocation command that takes an element from the list of unallocated objects, the panctr.rbusy bit is also set along with the busy bit table 24-3 panel commands overview command name description no operation no new command is started. initialize lists run the initialization sequence to reset the ctrl and list field of all message objects. static allocate allocate message object to a list. dynamic allocate allocate the first message object of the list of unallocated objects to the selected list. static insert before remove a message object (source object) from the list that it currently belongs to, and insert it before a given destination object into the list structure of the destination object. dynamic insert before insert a new message object before a given destination object. static insert behind remove a message object (source object) from the list that it currently belongs to, and insert it behind a given destination object into the list structure of the destination object. dynamic insert behind insert a new message object behind a given destination object. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-35 v1.1, 2011-03 multican, v3.0 (rbusy = busy = 1). this indicates that bit fields panar1 and panar2 are going to be updated by the list controller in the following way: 1. the message number of the message object taken from the list of unallocated elements is written to panar1. 2. if err (bit 7 of panar2) is set to 1, the list of unallocated elements was empty and the command is aborted. if err is 0, the list was not empty and the command will be performed successfully. the results of a dynamic allocation command are written before the list controller starts the actual allocation process. as soon as the results are available, rbusy becomes inactive (rbusy = 0) again, while busy sti ll remains active unt il completion of the command. this allows the user to set up the new message object while it is still in the process of list allocation. the access to message objects is not limited during ongoing list operations. however, any access to a register resource located inside the ram delays the ongoing allocation process by one access cycle. as soon as the command is finished, the busy flag becomes inactive (busy = 0) and write accesses to the panel control register are enabled again. also, the ?no operation? command code is automatically written to the panctr.pancmd field. a new command may be started any time when busy = 0. all fields of the panel control register panctr except busy and rbusy may be written by the user. this makes it possible to save and restore the panel control register if the command panel is used within independent (mutually interruptible) interrupt service routines. if this is the case, any task that uses the command panel and that may interrupt another task that also uses the command panel should poll the busy flag until it becomes inactive and save the whole panctr register to a memory location before issuing a command. at the end of the interrupt service routine, the task should restore panctr from the memory location. before a message object that is allocated to the list of an active can node shall be moved to another list or to another positio n within the same list, bit moctrn.msgval (?message valid?) of message object n must be cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-36 v1.1, 2011-03 multican, v3.0 24.5.7 can node analysis features the chapter describes the can node analysis capabilities of the multican module. 24.5.7.1 analyze mode the can analyze mode makes it possible to monitor the can traffic for each can node individually without affecting the logical state of the can bus. the can analyze mode for can node x is selected by setting node x control register bit ncrx.calm. in can analyze mode, the transmit pin of a can node is held at a recessive level permanently. the can node may receive frames (data, remote, and error frames) but is not allowed to transmit. received data /remote frames are not acknowledged (i.e. acknowledge slot is sent recessive) but w ill be received and stored in matching message objects as long as there is any other node that acknowledges the frame. the complete message object functionality is available, but no transmit request will be executed. 24.5.7.2 loop-back mode the multican module provides a loop-back mode to enable an in-system test of the multican module as well as the development of can driver software without access to an external can bus. the loop-back feature consists of an internal can bus (inside the multican module) and a bus select switch for each can node (see figure 24-15 ). with the switch, each can node can be connected either to the internal can bus (loop-back mode activated) or the external can bus, respectively to transmi t and receive pins (normal operation). the can bus that is not currently selected is driven recessive; this means the transmit pin is held at 1, and the receive pin is ignored by the can nodes that are in loop-back mode. the loop-back mode is selected for can node x by setting the node x port control register bit npcrx.lbm. all can nodes that are in loop-back mode may communicate together via the internal can bus without affecting the normal operation of the other can nodes that are not in loop-back mode. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-37 v1.1, 2011-03 multican, v3.0 figure 24-15 loop-back mode 24.5.7.3 bit timing analysis detailed analysis of the bit timing can be performed for each can node using the analysis modes of the can frame counter. the bit timing analysis functionality of the frame counter may be used for automatic detection of the can baud rate, as well as to analyze the timing of the can network. bit timing analysis for can node x is selected when bit field nfcrx.cfmod = 10 b . bit timing analysis does not affect the operation of the can node. the bit timing measurement results are writ ten into the nfcrx.cfc bit field. whenever nfcrx.cfc is updated in bit timing anal ysis mode, bit nfcrx.cfcov is also set to indicate the cfc update event. if nfcrx.cfcie is set, an interrupt request can be generated (see figure 24-12 ). can node 0 npcr0.lbm c a internal can bus 0 1 can node 1 npcr1.lbm c a 0 npcrx.lbm ca 0 1 . . . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-38 v1.1, 2011-03 multican, v3.0 automatic baud rate detection for automatic baud rate detection, the time between the observation of subsequent dominant edges on the can bus must be meas ured. this measurement is automatically performed if bit field nfcrx.cfsel = 000 b . with each dominant edge monitored on the can receive input line, the time (measured in f can clock cycles) between this edge and the most recent dominant edge is stored in the nfcrx.cfc bit field. synchronization analysis the bit time synchronization is monitored if nfcrx.cfsel = 010 b . the time between the first dominant edge and the sample point is measured and stored in the nfcrx.cfc bit field. the bit timing synchronization offset may be derived from this time as the first edge after the sample point triggers synchronization and there is only one synchronization between consecutive sample points. synchronization analysis can be used, for ex ample, for fine tuning of the baud rate during reception of the first can frame with the measured baud rate. driver delay measurement the delay between a transmitted edge and the corresponding received edge is measured when nfcrx.cfsel = 011 b (dominant to dominant) and nfcrx.cfsel = 100 b (recessive to recessive). these delays indicate the time needed to represent a new bit value on the physical implementation of the can bus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-39 v1.1, 2011-03 multican, v3.0 24.5.8 message acceptance filtering the chapter describes the message acceptance filtering capabilities of the multican module. 24.5.8.1 receive acceptance filtering when a can frame is received by a can node, a unique message object is determined in which the received frame is stored after successful frame reception. a message object is qualified for reception of a frame if the following six conditions are met. ? the message object is allocated to the message object list of the can node by which the frame is received. ? bit mostatn.msgval in the message status register (see page 24-97 ) is set. ? bit mostatn.rxen is set. ? bit mostatn.dir is equal to bit rtr of the received frame. if bit mostatn.dir = 1 (transmit object), the message object accepts only remote frames. if bit mostatn.dir = 0 (receive object), the message object accepts only data frames. ? if bit moamrn.mide = 1, the ide bit of the received frame becomes evaluated in the following way: if moarn.ide = 1, the ide bit of the received frame must be set (indicates extended identifier). if moarn.ide = 0, the ide bit of the received frame must be cleared (indicates standard identifier). if bit moamrn.mide = 0, the ide bit of the received frame is ?don?t care?. in this case, message objects with standard and extended frames are accepted. ? the identifier of the received frame matche s the identifier stored in the arbitration register of the message object as qualified by the acceptance mask in the moamrn register. this means that each bit of the received message object identifier is equal to the bit field moarn.id, except those bits for which the corresponding acceptance mask bits in bit field moamrn.am are cleared . these identifier bits are ?don?t care? for reception. figure 24-16 illustrates this receive message identifier check. among all messages that fulfill all six qualifying criteria the message object with the highest receive priority wins receive acceptance filtering and becomes selected to store the received frame. all other message objects lose receive acceptance filtering. the following priority scheme is defined for the message objects: a message object a (moa) has higher receive priority than a message object b (mob) if the following two conditions are fulfilled (see page 24-113 ): 1. moa has a higher priority class than mob. this means, the 2-bit priority bit field moara.pri must be equal or less than bit field moarb.pri. 2. if both message objects have the same priority class (moara.pri = moarb.pri), mob is a list successor of moa. this means that mob can be reached by means of successively stepping forward in the list, starting from a. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-40 v1.1, 2011-03 multican, v3.0 figure 24-16 received message identifier acceptance check 24.5.8.2 transmit ac ceptance filtering a message is requested for transmission by setting a transmit request in the message object that holds the message. if more than one message object have a valid transmit request for the same can node, one of these message objects is chosen for transmission, because only a single message object can be transmitted at one time on a can bus. a message object is qualified for transmission on a can node if the following four conditions are met (see also figure 24-17 ). 1. the message object is allocated to the message object list of the can node. 2. bit mostatn.msgval is set. 3. bit mostatn.txrq is set. 4. bit mostatn.txen0 and mostatn.txen1 are set. a priority scheme determines which one of all qualifying message objects is transmitted first. it is assumed that message object a (moa) and message object b (mob) are two message objects qualified for transmission. mob is a list successor of moa. for both message objects, can messages cana and canb are defined (identifier, ide, and rtr are taken from the message-specific bit fi elds and bits moarn.id, moarn.ide and moctrn.dir). if both message objects belong to the same priority class (identical pri bit field in register moarn), moa has a higher transmit priority than mob if one of the following conditions is fulfilled. ?pri=10 b and can message moa has higher or equal priority than can message mob with respect to can arbitration rules (see table 24-13 on page 24-114 ). ?pri=01 b or pri = 11 b (priority by list order). mca06271 identifier of received frame identifier of message object acceptance mask of message object bitwise xor bitwise and 0 = bit match 1 = no match id match = 0: id of the received frame fits to message object id match > 0: id of the received frame does not fit to message object id matc h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-41 v1.1, 2011-03 multican, v3.0 ?pri=00 b and the actual matrix position in a ttcan network matches the matrix position(s) given in moamrn of moa, i.e. cycle & mcycle = cyctmr.bcc & mcycle and column & mcolumn = cyctmr.csm & mcolumn a message object with pri = 00 b can be transmitted only by an active ttcan node. the message object that is qualified for transmission and has highest transmit priority wins the transmit acceptance filtering, and will be transmitted fi rst. all other message objects lose the current transmit acceptance filtering round. they get a new chance in subsequent acceptance filtering rounds. the three priority rules listed before are valid for normal can operation (without ttcan functionality) as well as for arbitration windows within a ttcan system matrix. figure 24-17 effective transmit request of message object transmission acceptance filtering in ttcan exclusive windows in exclusive windows of a ttcan, transm it acceptance filtering is performed as described in the previous section but with the exception that only message objects with moarn.pri = 00 b can be transmitted. message objects with other pri values are not taken into account. hence the transmit acceptance filtering process selects the first message object in the list that meets the following conditions: 1. moarn.pri = 00 b a) msgval & txrq & txen0 & txen1 = 1 (i.e. the message object qualifies for transmission) b) the actual matrix position in a ttca n network matches the matrix position(s) given in moamr of moa, i.e. cycle & mcycle = cyctmr.bcc & mcycle and column & mcolumn = cyctmr.csm & mcolumn mca0627 2 msgval 0 = object will not be transmitted 1 = object is requested for transmissio n txrq txen0 txen1 & www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-42 v1.1, 2011-03 multican, v3.0 24.5.9 message postprocessing after a message object has successfully received or transmitted a frame, the cpu can be notified to perform a postprocessing on the message object. the postprocessing of the multican module consists of two elements: 1. message interrupts to trigger postprocessing. 2. message pending registers to collect pending message interrupts into a common structure for postprocessing. 24.5.9.1 message ob ject interrupts when the storage of a received frame into a message object or the successful transmission of a frame is completed, a message interrupt can be issued. for each message object, a transmit and a receive interrupt can be generated and routed to one of the sixteen can interrupt output lines (see figure 24-18 ). a receive interrupt occurs also after a frame storage event that has been induced by a fifo or a gateway action. the status bits txpnd and rxpnd in the message object n status register are always set after a successful transmission/recepti on, whether or not the respective message interrupt is enabled. a third fifo full interrupt condition of a message object is provided. if bit field mofcrn.ovie (overflow interrupt enable) is set, the fifo full interrupt will be activated depending on the actual message object type. in case of a receive fifo base object (mofcrn.mmc = 0001 b ), the fifo full interrupt is routed to the interrupt output line int_om as defined by the transmit interrupt node pointer moiprn.txinp. in case of a transmit fifo base object (mofcrn.mmc = 0010 b ), the fifo full interrupt becomes routed to the interrupt output line int_om as defined by the receive interrupt node pointer moiprn.rxinp. see also ?interrupt control? on page 24-211 for further processing of the message object interrupts. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-43 v1.1, 2011-03 multican, v3.0 figure 24-18 message interrupt request routing mca0627 3 txie txinp txpnd rxinp mostatn mofcrn moiprn moiprn ovie rxie rxpnd mmc & & = 0001 b = 0010 b m mc = 0001 b : message object n is a receive fifo base object m mc = 0010 b : message object n is a transmit fifo base object 1 1 m essage n r eceived m essage n t ransmitted m essage n f ifo full www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-44 v1.1, 2011-03 multican, v3.0 24.5.9.2 pending messages when a message interrupt request is generated, a message pending bit is set in one of the message pending registers. there are 8 message pending registers, mspndk (k = 0-7 ) with 32 pending bits available each. the general figure 24-19 shows the allocation of the message pending bits in case that the maximum possible number of eight message pending registers are implemented and available on the chip. figure 24-19 message pending bit allocation 255 224 mca0627 4 7 6 5 4 3 2 1 0 mpn message object n interrupt pointer register moiprn[15:0] 3 2 1 0 txinp 3 2 1 0 rxinp 1 5 d e m u x 0 7 d e m u x 0 31 31 0 . . . . . . . . . . . . . . . . . . . . . . . 3 2 1 0 mpsel modul control register mcr[31:0] msb message pending registers 01 01 01 01 0 = transmit event 1 = receive event 0 223 159 191 127 95 63 192 160 128 96 64 32 mspnd0 mspnd1 mspnd2 mspnd3 mspnd4 mspnd5 mspnd6 mspnd7 2 1 0 4 3:0 0 1 0 1 0 1 0 1 5 4 31 0 6 7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-45 v1.1, 2011-03 multican, v3.0 the location of a pending bit is defined by two demultiplexers selecting the number k of the mspndk registers (3-bit demux), and the bit location within the corresponding mspndk register (5-bit demux). allocation case 1 in this allocation case , bit field mcr.mpsel = 0000 b (see page 24-69 ). the location selection consists of 2 parts: ? the upper three bits of moiprn.mpn (mpn[7:5]) select the number k of a message pending register mspndk in which the pending bit will be set. ? the lower five bits of moiprn.mpn (mpn[4:0]) select the bit position (0-31) in mspndk for the pending bit to be set. allocation case 2 in this allocation case, bit field mcr.mpsel is taken into account for pending bit allocation. bit field mcr.mpsel makes it po ssible to include the interrupt request node pointer for reception (moiprn.rxinp) or transmission (moiprn.txinp) for pending bit allocation in such a way that different target locations for the pending bits are used in receive and transmit case. if mpsel = 1111 b , the location selection operates in the following way: ? at a transmit event, the upper 3 bits of txinp determine the number k of a message pending register mspndk in which the pending bit will be set. at a receive event, the upper 3 bits of rxinp determine the number k. ? the bit position (0-31) in mspndk for the pending bit to be set is selected by the lowest bit of txinp or rxinp (selects between low and high half-word of mspndk) and the four least significant bits of mpn. general hints the message pending registers mspndk can be written by software. bits that are written with 1 are left unchanged, and bits which are written with 0 are cleared. this makes it possible to clear individual mspndk bits with a single register write access. therefore, access conflicts are avoided when the multican module (hardware) sets another pending bit at the same time when software writes to the register. each message pending register mspndk is associated with a message index register msidk (see page 24-74 ) which indicates the lowest bit position of all set (1) bits in message pending register k. the msidk regist er is a read-only register that is updated immediately when a value in the corresponding message pending register k is changed by software or hardware. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-46 v1.1, 2011-03 multican, v3.0 24.5.10 message obje ct data handling this chapter describes the handling capabilities for the message object data of the multican module. 24.5.10.1 frame reception after the reception of a message, it is stored in a message object according to the scheme shown in figure 24-20 . the multican module not only copies the received data into the message object, and it provides advanced features to enable consistent data exchange between multican and cpu. msgval bit msgval (message valid) in the message object n status register mostatn is the main switch of the message object. during the frame reception, information is stored in the message object only when msgval = 1. if bit msgval is reset by the cpu, the multican module stops all ongoing write accesses to the message object. now the message object can be re-configured by the cpu with subsequent write accesses to it without being disturbed by the multican. rtsel when the cpu re-configures a message object during can operation (for example, clears msgval, modifies the message object and sets msgval again), the following scenario can occur: 1. the message object wins receive acceptance filtering. 2. the cpu clears msgval to re-configure the message object. 3. the cpu sets msgval again after re-configuration. 4. the end of the received frame is reached. as msgval is set, the received data is stored in the message object, a message interrupt request is generated, gateway and fifo actions are processed, etc. after the re-configuration of the message object (after step 3 above) the storage of further received data may be undesirable. this can be achieved through bit moctrn.rtsel (receive/trans mit selected) that makes it possible to disconnect a message object from an ongoing frame reception. when a message object wins the receive accept ance filtering, its rtsel bit is set by the multican module to indicate an upcoming frame delivery. the multican module checks rtsel whether it is set on successful frame reception to verify that the object is still ready for receiving the frame. the received frame is then stored in the message object (along with all subsequent actions such as message interrupts, fifo & gateway actions, flag updates) only if rtsel = 1. when a message object is invalidated during can operation (resetting bit msgval), rtsel should be cleared before setting msgval again (latest with the same write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-47 v1.1, 2011-03 multican, v3.0 access that sets msgval) to prevent the storage of a frame that belongs to the old context of the message object. therefore, a message object re-configuration should consist of the following steps: 1. clear msgval bit 2. re-configure the message object while msgval = 0 3. clear rtsel bit and set msgval again rxen bit mostatn.rxen enables a message object for frame reception. a message object can receive can messages from the can bus only if rxen = 1. the multican module evaluates rxen only during receive acceptance filtering. after receive acceptance filtering, rxen is ignored and has no further influence on the actual storage of a received message in a message object. bit rxen enables the ?soft phase out? of a message object: after clearing rxen, a currently received can message for whic h the message object has won acceptance filtering is still stored in the message object but for subsequent messages the message object no longer wins receive acceptance filtering. rxupd, newdat and msglst an ongoing frame storage process is indica ted by the rxupd (receive updating) flag in the mostatn register. rxupd is set with the start and cleared with the end of a message object update, which consists of frame storage as well as flag updates. after storing the received frame (identifier, ide bit, dlc; including the data field for data frames), the newdat (new data) bit of the message object is set. if newdat was already set before it becomes set again, bit msglst (message lost) is set to indicate a data loss condition. the rxupd and newdat flags can help to read consistent frame data from the message object during an ongoing can operation. the following steps are recommended to be executed: 1. clear newdat bit. 2. read message content (identifier, data etc.) from the message object. 3. check that both, newdat and rxupd, are cleared. if this is not the case, go back to step 1. 4. when step 3 was successful, the message object contents are consistent and has not been updated by the multican module while reading. bits rxupd, newdat and msglst have the same behavior for the reception of data as well as remote frames. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-48 v1.1, 2011-03 multican, v3.0 figure 24-20 reception of a message object mca06275 object wins acc. filtering ? yes yes no no can rec. successful ? msgval & rtsel = 1? msgval = 1? dir = 1? newdat = 1? rxie = 1? rtsel := 1 rxupd := 1 copy frame to message object txrq := 1 in this or in foreign objects copy frame to message object rxupd := 1 msglst := 1 yes newdat := 1 rxupd := 0 rxpnd := 1 no no yes yes no interrupt generated no yes 1 2 3 4 no time milestones get data from gateway/fifo source start receiving can frame done yes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-49 v1.1, 2011-03 multican, v3.0 24.5.10.2 frame transmission the process of a message object transmission is shown in figure 24-21 . along with the copy of the message object content to be transmitted (identifier, ide bit, rtr = dir bit, dlc, including the data field for data frames) into the internal transmit buffer of the assigned can node, several status flags are also served and monitored to control consistent data handling. the transmission process of a message object starting after the transmit acceptance filtering is identical for remote and data frames. msgval, txrq, txen0, txen1 a message can only be transmitted if all fo ur bits in registers mostatn, msgval (message valid), txrq (transmit requ est), txen0 (transmit enable 0), txen1 (transmit enable 1) are set as shown in figure 24-17 . although these bits are equivalent with respect to the transmissi on process, they have different semantics: table 24-4 message transmission bit definitions bit description msgval message valid this is the main switch bit of the message object. txrq transmit request this is the standard transmit request bit. this bit must be set whenever a message object should be transmitted. txrq is cleared by hardware at the end of a successful transmission, except when there is new data (indicated by newdat = 1) to be transmitted. when bit mofcrn.stt (?single transmi t trial?) is set, txrq becomes already cleared when the contents of the message object are copied into the transmit frame buffer of the can node. a received remote request (after a re mote frame reception) sets bit txrq to request the transmission of the requested data frame. txen0 transmit enable 0 this bit can be temporarily cleared by software to suppress the transmission of this message object when it writes new content to the data field. this avoids transmission of in consistent frames that consist of a mixture of old and new data. remote requests are still accepted when txen0 = 0, but transmission of the data frame is suspended until transmission is re-enabled by software (setting txen0). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-50 v1.1, 2011-03 multican, v3.0 rtsel when a message object has been identified to be transmitted next after transmission acceptance filtering, bit moctrn.rtsel (receive/transmit selected) is set. when the message object is copied into the internal transmit buffer, bit rtsel is checked, and the message is transmitted only if rtsel = 1. after the successful transmission of the message, bit rtsel is checked again and the message postprocessing is only executed if rtsel = 1. for a complete re-configuration of a valid message object, the following steps should be executed: 1. clear msgval bit 2. re-configure the message object while msgval = 0 3. clear rtsel and set msgval clearing of rtsel ensures that the message object is disconnected from an ongoing/scheduled transmission and no message object processing (copying message to transmit buffer including clearing newdat, clearing txrq, time stamp update, message interrupt, etc.) within the old context of the object can occur after the message object becomes valid again, but within a new context. newdat when the contents of a message object have been transferred to the internal transmit buffer of the can node, bit mostatn.newdat (new data) is cleared by hardware to indicate that the transmit message object data is no longer new. when the transmission of the frame is successful and newdat is still cleared (if no new data has been copied into the message object meanwhile), txrq (transmit request) is cleared automatically by hardware. if, however, the newdat bit has been set again by the software (because a new frame should be transmitted), txrq is not clear ed to enable the transmission of the new data. txen1 transmit enable 1 this bit is used in transmit fifos to select the message object that is transmit active within the fifo structure. for message objects that are not transmit fifo elements, txen1 can either be set permanently to 1 or can be used as a second independent transmission enable bit. table 24-4 message transmission bit definitions (cont?d) bit description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-51 v1.1, 2011-03 multican, v3.0 figure 24-21 transmission of a message object mca06276 rtsel = 1? newdat = 1? txie = 1? rtsel := 1 newdat := 0 no yes 1 2 3 copy message to internal transmit buffer msgval & txrq & txen0 & txen1 = 1 continuously valid request transmission of internal buffer on can bus yes transmission successful ? yes msgval & rtsel = 1? yes txrq := 0 issue interrupt no no no no no time milestone s done object wins transmit acc. filtering yes yes www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-52 v1.1, 2011-03 multican, v3.0 24.5.11 message object functionality this chapter describes the functionality of the message objects in the multican module. 24.5.11.1 standard message object a message object is selected as standard message object when bit field mofcrn.mmc = 0000 b (see page 24-90 ). the standard message object can transmit and receive can frames according to the basic rules described in the previous sections. additional services such as single data tr ansfer mode or single transmit trial (see following sections) are available and can be individually selected. 24.5.11.2 single data transfer mode single data transfer mode is a useful feat ure in order to broadcast data over the can bus without unintended duplication of information. single data transfer mode is selected via bit mofcrn.sdt. message reception when a received message stored in a message object is overwritten by a new received message, the contents of the first message are lost and replaced with the contents of the new received message (indicated by msglst = 1). if sdt is set (single data transfer mode activated), bit msgval of the message object is automatically cleared by hardware after the storage of a received data frame. this prevents the reception of further messages. after the reception of a remote frame, bit msgval is not automatically cleared. message transmission when a message object receives a series of multiple remote requests, it transmits several data frames in response to the remote requests. if the data within the message object has not been updated in the time between the transmissions, the same data can be sent more than once on the can bus. in single data transfer mode (sdt = 1), this is avoided because msgval is automatically cleared after the successful transmission of a data frame. after the transmission of a remote frame, bit msgval is not automatically cleared. 24.5.11.3 single transmit trial if the bit stt in the message object function register is set (stt = 1), the transmission request is cleared (txrq = 0) when the frame contents of the message object have been copied to the internal transmit buffer of the can node. thus, the transmission of the message object is not tried again when it fails due to can bus errors. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-53 v1.1, 2011-03 multican, v3.0 24.5.11.4 message object fifo structure in case of high cpu load it may be difficult to process a series of can frames in time. this may happen if multiple messages are received or must be transmitted in short time. therefore, a fifo buffer structure is available to avoid loss of incoming messages and to minimize the setup time for outgoing messages. the fifo structure can also be used to automate the reception or transmission of a series of can messages and to generate a single message interrupt when the whole can frame series is done. there can be several fifos in parallel. the number of fifos and their size are limited only by the number of available message obj ects. a fifo can be installed, resized and de-installed at any time, even during can operation. the basic structure of a fifo is shown in figure 24-22 . a fifo consists of one base object and n slave objects. the slave objects are chained together in a list structure (similar as in message object lists). the base object may be allocated to any list. although figure 24-22 shows the base object as a separate part beside the slave objects, it is also possible to integrate the base object at any place into the chain of slave objects. this means that the base object is slave object, too (not possible for gateways). the absolute object numbers of the message objects have no impact on the operation of the fifo. the base object does not need to be allocated to the same list as the slave objects. only the slave object must be allocated to a common list (as they are chained together). several pointers (bot, cur and top) that are located in the message object n fifo/gateway pointer register mofgprn link the base object to the slave objects, regardless whether the base object is allocated to the same or to another list than the slave objects. the smallest fifo would be a single message object which is both, fifo base and fifo slave (not very useful). the biggest possib le fifo structure would include all message objects of the multican module. any fifo sizes between these limits are possible. in the fifo base object, the fifo boundaries are defined. bit field mofgprn.bot of the base object points to (includes the number of) the bottom slave object in the fifo structure. the mofgprn.top bit field points to (includes the number of) the top slave object in the fifo structure. the mofgprn.cur bit field points to (includes the number of) the slave object that is actually selected by the multican module for message transfer. when a message transfer takes plac e with this object, cur is set to the next message object in the list structure of the slave objects (cur = pnext of current object). if cur was equal to top (top of the fifo reached), the next update of cur will result in cur = bot (wrap-around from the top to the bottom of the fifo). this scheme represents a circular fifo structure where the bit fields bot and top establish the link from the last to the first element. bit field mofgprn.sel of the base object can be used for monitoring purposes. it makes it possible to define a slave object within the list at which a message interrupt is www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-54 v1.1, 2011-03 multican, v3.0 generated whenever the cur pointer reaches the value of the sel pointer. thus sel makes it possible to detect the end of a predefined message transfer series or to issue a warning interrupt when the fifo becomes full. figure 24-22 fifo structure with fifo base object and n fifo slave objects mca06277 . . . . . . . . slave object fi pprev = f[i-1] pnext = f[i+1] slave object fn pprev = f[n-1] pnext slave object f2 pprev = f1 pnext = f3 slave object f1 pprev pnext = f2 base object pprev pnext top = fn cur = fi bot = f1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-55 v1.1, 2011-03 multican, v3.0 24.5.11.5 receive fifo the receive fifo structure is used to buffer incoming (received) remote or data frames. a receive fifo is selected by setting mofcrn.mmc = 0001 b in the fifo base object. this mmc code automatically designates a message object as fifo base object. the message modes of the fifo slave objects are not relevant for the operation of the receive fifo. when the fifo base object receives a frame fr om the can node it belongs to, the frame is not stored in the base object itself but in the message object that is selected by the base object?s mofgprn.cur pointer. this message object receives the can message as if it is the direct receiver of the message. however, mofcrn.mmc = 0000 b is implicitly assumed for the fifo slave object, and a standard message delivery is performed. the actual message mode (mmc sett ing) of the fifo slave object is ignored. for the slave object, no acceptance filtering takes place that checks the received frame for a match with the identifier, ide bit, and dir bit. with the reception of a can frame, the current pointer cur of the base object is set to the number of the next message object in the fifo structure. this message object will then be used to store the next incoming message. if bit field mofcrn.ovie (?overflow interrupt en able?) of the fifo base object is set and the current pointer mofgprn.cur becomes equal to mofgprn.sel, a fifo overflow interrupt request is generated. this interrupt request is generated on interrupt node txinp of the base object immediately after the storage of the received frame in the slave object. transmit interrupts are still generated if txie is set. a can message is stored in fifo base and slave object only if msgval = 1. in order to avoid direct reception of a message by a slave message object, as if it was an independent message object and not a part of a fifo, the bit rxen of each slave object must be cleared. the setting of the bit rxen is ?don?t care? only if the slave object is located in a list not assigned to a can node. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-56 v1.1, 2011-03 multican, v3.0 24.5.11.6 transmit fifo the transmit fifo structure is used to buffer a series of data or remote frames that must be transmitted. a transmit fifo consists of one base message object and one or more slave message objects. a transmit fifo is selected by setting mofcrn.mmc = 0010 b in the fifo base object. unlike the receive fifo, slave objects assigned to the transmit fifo must explicitly set their bit fields mofcrn.mmc = 0011 b . the cur pointer in all slave objects must point back to the transmit fifo base object (to be initialized by software). the mostatn.txen1 bits (tra nsmit enable 1) of all message objects except the one which is selected by the cur pointer of the base object must be cleared by software. txen1 of the message (slave) object selected by cur must be set. cur (of the base object) may be initialized to any fifo slave object. when tagging the message objects of the fifo as valid to start the operation of the fifo, then the base object must be tagged valid (msgval = 1) first. before a transmit fifo becomes de-installed during operation, its slave objects must be tagged invalid (msgval = 0). the transmit fifo uses the txen1 bit in th e message object control register of all fifo elements to select the actual message for transmission. transmit acceptance filtering evaluates txen1 for each mess age object and a message object can win transmit acceptance filtering only if its txen1 bit is set. when a fifo object has transmitted a message, the hardware clears its txen1 bit in addition to standard transmit postprocessing (clear txrq, transmit interrupt etc.), and moves the cur pointer in the next fifo base object to be tr ansmitted. txen1 is set automatically (by hardware) in the next message object. t hus, txen1 moves along the transmit fifo structure as a token that selects the active element. if bit field mofcrn.ovie (?overflow interrupt en able?) of the fifo base object is set and the current pointer cur becomes equal to mofgprn.sel, a fifo overflow interrupt request is generated. the interrupt request is generated on interrupt node rxinp of the base object after postprocessing of the received frame. receive interrupts are still generated for the transmit fifo base object if bit rxie is set. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-57 v1.1, 2011-03 multican, v3.0 24.5.11.7 gateway mode the gateway mode makes it possible to establish an automatic information transfer between two independent can buses without cpu interaction. the gateway mode operates on message object level. in gateway mode, information is transferred between two message objects, resulting in an information transfer between the two can nodes to which the message objects are allocated. a gateway may be established with any pair of can nodes, and there can be as many gateways as there are message objects available to build the gateway structure. gateway mode is selected by setting mofcrs.mmc = 0100 b for the gateway source object s. the gateway destination object d is selected by the mofgprd.cur pointer of the source object. the gateway destination object only needs to be valid (its msgval = 1). all other settings are not relevant for the information transfer from the source object to the destination object. gateway source object behaves as a standar d message object with the difference that some additional actions are performed by the multican module when a can frame has been received and stored in the source object (see figure 24-23 ): 1. if bit mofcrs.dlcc is set, the data leng th code mofcrs.dlc is copied from the gateway source object to the gateway destination object. 2. if bit mofcrs.idc is set, the identifi er moars.id and the identifier extension moars.ide are copied from the gateway source object to the gateway destination object. 3. if bit mofcrs.datc is set, the data bytes stored in the two data registers modatals and modatahs are copied from the gateway source object to the gateway destination object. all 8 data bytes are copied, even if mofcrs.dlc indicates less than 8 data bytes. 4. if bit mofcrs.gdfs is set, the transmit request flag mostatd.txrq is set in the gateway destination object. 5. the receive pending bit mostatd.rxpnd and the new data bit mostatd.newdat are set in the gateway destination object. 6. a message interrupt request is generated for the gateway destination object if its mostatd.rxie is set. 7. the current object pointer mofgprs.cur of the gateway source object is moved to the next destination object according to the fifo rules as described on page 24-53 . a gateway with a single (static) destination object is obtained by setting mofgprs.top = mofgprs.bot = mofg prs.cur = destination object. the link from the gateway source object to the gateway destination object works in the same way as the link from a fifo base to a fifo slave. this means that a gateway with an integrated destination fifo may be created; in figure 24-22 , the object on the left is the gateway source object and the message object on the right side is the gateway destination objects. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-58 v1.1, 2011-03 multican, v3.0 the gateway operates equivalent for the reception of data frames (source object is receive object, i.e. dir = 0) as well as for t he reception of remote frames (source object is transmit object). figure 24-23 gateway transfer from source to destination mca06278 copy if idc source = 1 pointer to destination message object destination can bus source can bus set cur identifier + ide dlc data source message object mmc = 0100 b copy if dlcc source = 1 copy if datc source = 1 set if gdfs source = 1 identifier + ide dlc data txrq newdat txrq destination message object set www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-59 v1.1, 2011-03 multican, v3.0 24.5.11.8 foreign remote requests when a remote frame has been received on a can node and is stored in a message object, a transmit request is set to trigger the answer (transmission of a data frame) to the request or to automatically issue a secondary request. if the foreign remote request enable bit mofcrn.frren is clear ed in the message object in which the remote request is stored, mostatn.txrq is set in the same message object. if bit frren is set (frren = 1: foreign remo te request enabled), txrq is set in the message object that is referenced by pointer mofgprn.cur. the value of cur is, however, not changed by this feature. although the foreign remote request feature works independently of the selected message mode, it is especially useful for gateways to issue a remote request on the source bus of a gateway after the reception of a remote request on the gateway destination bus. according to the setting of frren in the gateway destination object, there are two capabilities to handle remote requests that appear on the destination side (assuming that the source object is a receive object and the destination is a transmit object, i.e. dir source = 0 and dir destination =1): frren = 0 in the gateway destination object 1. a remote frame is received by gateway destination object. 2. txrq is set automatically in the gateway destination object. 3. a data frame with the current data stored in the destination object is transmitted on the destination bus. frren = 1 in the gateway destination object 1. a remote frame is received by gateway destination object. 2. txrq is set automatically in the gateway source object (must be referenced by cur pointer of the destination object). 3. a remote request is transmitted by the source object (which is a receive object) on the source can bus. 4. the receiver of the remote request responds with a data frame on the source bus. 5. the data frame is stored in the source object. 6. the data frame is copied to the destination object (gateway action). 7. txrq is set in the destination object (assuming gdfs source =1). 8. the new data stored in the destination object is transmitted on the destination bus, in response to the initial remote request on the destination bus. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-60 v1.1, 2011-03 multican, v3.0 24.6 multican kernel registers this section describes the kernel registers of the multican module. all multican kernel register names described in this section are also referenced in other parts of the TC1798 users manual by the module name prefix ?can_?. multican kernel re gister overview the multican kernel includ e three blocks of registers: ? global module registers ? node registers, for each can node x ? message object registers, for each message object n figure 24-24 multican kernel registers the registers of the multican module kernel are listed below. table 24-5 registers address space - multican kernel registers module base address end address note can f000 4000 h f000 7fff h - lis ti mspndk msidk ncrx global module registers can node registers nsrx msimask panctr niprx npcrx nbtrx necntx mofcrn message o bj e registers mofgp r mcr mestat 1) moiprn moamr n i0t(lit1) moarn modat a modat a moctrn mostat 0t ( m nfcrx ntccrx ntrtrx ntattx mitr mecr 1) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-61 v1.1, 2011-03 multican, v3.0 table 24-6 registers overview - multican kernel registers register short name register long name offset address 1) description see listi list register i 0100 h + i 4 h page 24-71 mspndk message pending register k 0140 h + k 4 h page 24-73 msidk message index register k 0180 h + k 4 h page 24-74 msimask message index mask register 01c0 h page 24-75 id module identification register 008 h page 24-64 panctr panel control register 01c4 h page 24-65 mcr module control register 01c8 h page 24-69 mitr module interrupt trigger reg. 01cc h page 24-70 ncrx node x control register 0200 h + x 100 h page 24-76 nsrx node x status register 0204 h + x 100 h page 24-80 niprx node x interrupt pointer reg. 0208 h + x 100 h page 24-84 npcrx node x port control register 020c h + x 100 h page 24-86 nbtrx node x bit timing register 0210 h + x 100 h page 24-87 necntx node x error counter register 0214 h + x 100 h page 24-89 nfcrx node x frame counter register 0218 h + x 100 h page 24-90 mofcrn message object n function control register 1000 h + n 20 h page 24-104 mofgprn message object n fifo/gateway pointer register 1004 h + n 20 h page 24-109 moiprn message object n interrupt pointer register 1008 h + n 20 h page 24-102 moamrn message object n acceptance mask register 100c h + n 20 h page 24-110 modataln message object n data register low 1010 h + n 20 h page 24-115 modatahn message object n data register high 1014 h + n 20 h page 24-116 moarn message object n arbitration register 1018 h + n 20 h page 24-112 moctrn mostatn message object n control reg. message object n status reg. 101c h + n 20 h page 24-94 page 24-97 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-62 v1.1, 2011-03 multican, v3.0 figure 24-25 shows the multican register address map, without ttcan registers. they are shown in figure 24-38 . 1) the absolute register address is calculated as follows: module base address ( table 24-5 ) + offset address (shown in this column) further, the following ranges for parameters i, k, x, and n are valid: i = 0- 7 , k = 0- 7 , x = 0- 3 , n = 0- 127 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-63 v1.1, 2011-03 multican, v3.0 figure 24-25 multican register address map 24.6.1 global module registers all list operations such as allocation, de-allocation and relocation of message objects within the list structure are performed via the command panel. it is not possible to modify the list structure directly by software by writing to the message objects and the list registers. mca06280_n 000 h +100 h +200 h list registers i msg. index mask register + c0 h + c4 h panel control register module control register + 00 h msg. pending registers k msg. index registers k module interrupt trg. reg. + 40 h + 80 h + c8 h + cc h node 0 registers node x control register node x status register no = node, x = 0 to (number of nodes - 1) node x interrupt ptr. reg. node x port control reg. node x bit timing reg. node x error counter reg. node x frame counter reg. +300 h node 1 registers no base + 00 h message object registers mo n function control reg. mo n fifo/gtw. p tr. reg . mo = message object; n = 0 to (number of message objects-1) mo n interrupt ptr. reg. mo n accept. mask reg. mo n arbitration reg. mo n data register low mo n data register high mo base + 14 h +1000 h message object 0 +1020 h +mo base . . . . . . . . . . . . . . . . mo n control/status reg. mo base + 1c h mo base + 18 h mo base + 10 h mo base + 08 h mo base + 0c h mo base + 00 h mo base + 04 h +3fff h mo base = 400 h + n * 20 h no base + 04 h no base + 08 h no base + 0c h no base + 10 h no base + 14 h no base + 18 h message object 1 +1040 h +mo base + 20 h +280 h no base = 200 h + x * 100 h i = 0-7, k = 0-7 +1d0 h message object n-1 global module control +no base node x registers www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-64 v1.1, 2011-03 multican, v3.0 module identification register . id module identificat ion register (008 h ) reset value: 002b c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mode_rev rrwh field bits type description mod_rev [7:0] r module revision number mod_rev defines the revision number. the value of a module revision starts with 01 h (first revision). mod_type [15:8] r module type c0 h define the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines the multican module identification number (=002bh) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-65 v1.1, 2011-03 multican, v3.0 the panel control register panctr is used to start a new command by writing the command arguments and the command code into its bit fields. panctr panel control register (1c4 h ) reset value: 0000 0301 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 panar2 panar1 rwh rwh 1514131211109876543210 0 rbu sy bus y pancmd rrhrh rwh field bits type description pancmd [7:0] rwh panel command this bit field is used to start a new command by writing a panel command code into it. at the end of a panel command, the nop (no operation) command code is automatically written into pancmd. the coding of pancmd is defined in table 24-7 . busy 8rh panel busy flag 0 b panel has finished command and is ready to accept a new command. 1 b panel operation is in progress. rbusy 9rh result busy flag 0 b no update of panar1 and panar2 is scheduled by the list controller. 1 b a list command is running (busy = 1) that will write results to panar1 and panar2, but the results are not yet available. panar1 [23:16] rwh panel argument 1 see table 24-7 . panar2 [31:24] rwh panel argument 2 see table 24-7 . 0 [15:10] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-66 v1.1, 2011-03 multican, v3.0 panel commands a panel operation consists of a comma nd code (pancmd) and up to two panel arguments (panar1, panar2). commands that have a return value deliver it to the panar1 bit field. commands that return an error flag deliver it to bit 31 of the panel control register, this means bit 7 of panar2. table 24-7 panel commands pancmd panar2 panar1 command description 00 h ?? no operation writing 00 h to pancmd has no effect. no new command is started. 01 h result: bit 7: err bit 6-0: undefined ? initialize lists run the initialization sequence to reset the ctrl and list fields of all message objects. list register s list[7:0] are set to their reset values. this results in the de- allocation of all message objects. the initialization command requires that bits ncrx.init and ncrx.cce are set for all can nodes. bit 7 of panar2 (err) reports the success of the operation: 0 b initialization was successful 1 b not all ncrx.init and ncrx.cce bits are set. therefore, no initialization is performed. the initialize lists command is automatically performed with each reset of the multican module, but with the exception that all message object registers are reset, too. 02 h argument: list index argument: message object number static allocate allocate message object to a list. the message object is removed from the list that it currently belongs to, and appended to the end of the list, given by panar2. this command is also used to deallocate a message object. in th is case, the target list is the list of unallocated elements (panar2 = 0). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-67 v1.1, 2011-03 multican, v3.0 03 h argument: list index result: bit 7: err bit 6-0: undefined result: message object number dynamic allocate allocate the first message object of the list of unallocated ob jects to the selected list. the message object is appended to the end of the list. the message number of the message object is returned in panar1. an err bit (bit 7 of panar2) reports the success of the operation: 0 b success. 1 b the operation has not been performed because the list of unallocated elements was empty. 04 h argument: destination object number argument: source object number static insert before remove a message object (source object) from the list that it currently belongs to, and insert it before a given destination object into the list structure of the destination object. the source object thus becomes the predecessor of the destination object. 05 h argument: destination object number result: bit 7: err bit 6-0: undefined result: object number of inserted object dynamic insert before insert a new message object before a given destination object. the new object is taken from the list of unallocated elements (the first element is chosen). the number of the new object is delivered as a result to panar1. an err bit (bit 7 of panar2) reports the success of the operation: 0 b success. 1 b the operation has not been performed because the list of unallocated elements was empty. table 24-7 panel commands (cont?d) pancmd panar2 panar1 command description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-68 v1.1, 2011-03 multican, v3.0 06 h argument: destination object number argument: source object number static insert behind remove a message object (source object) from the list that it currently belongs to, and insert it behind a given destination object into the list structure of the destination object. the source object thus becomes the successor of the destination object. 07 h argument: destination object number result: bit 7: err bit 6-0: undefined result: object number of inserted object dynamic insert behind insert a new message object behind a given destination object. the new object is taken from the list of unallocated elements (the first element is chosen). the number of the new object is delivered as result to panar1. an err bit (bit 7 of panar2) reports the success of the operation: 0 b success. 1 b the operation has not been performed because the list of unallocated elements was empty. 08 h -ff h ?? reserved table 24-7 panel commands (cont?d) pancmd panar2 panar1 command description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-69 v1.1, 2011-03 multican, v3.0 the module control register mcr contains basic settings that determine the operation of the multican module. mcr module control register (1c8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 mpsel 0 rw r field bits type description mpsel [15:12] rw message pending selector bit field mpsel makes it possible to select the bit position of the message pending bit after a message reception/transmission by a mixture of the moiprn register bit fields rxinp, txinp, and mpn. selection details are given in figure 24-19 on page 24-44 . 0 [31:16], [11:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-70 v1.1, 2011-03 multican, v3.0 the interrupt trigger register itr is used to trigger interrupt requests on each interrupt output line by software. mitr module interrupt trigger register (1cc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 it w field bits type description it [15 :0] w interrupt trigger writing a 1 to it[n] (n = 0-15 ) generates an interrupt request on interrupt output line int_o[n]. writing a 0 to it[n] has no effect. bit field it is always read as 0. multiple interrupt requests can be generated with a single write operation to mitr by writing a 1 to several bit positions of it. 0 [31:16 ]r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-71 v1.1, 2011-03 multican, v3.0 list pointer and list register each can node has a list that determines the allocated message objects. additionally, a list of all unallocated objects is available. furthermore, general purpose lists are available which are not associated to a can node. the list registers are assigned in the following way: ? list0 provides the list of all unallocated objects ? list1 provides the list for can node 0 ? list2 provides the list for can node 1 ? list3 provides the list for can node 2 ? list[7:4] are not associated to a can node (free lists) list0 list register 0 (100 h ) reset value: 007f 7f00 h listx (x = 1-7 ) list register x (100 h +x*4 h ) reset value: 0100 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 emp ty size rrh rh 1514131211109876543210 end begin rh rh field bits type description begin [7:0] rh list begin begin indicates the number of the first message object in list i. end [15:8] rh list end end indicates the number of the last message object in list i. size [23:16] rh list size size indicates the number of elements in the list i. size = number of list elements - 1 size = 0 indicates that list x is empty. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-72 v1.1, 2011-03 multican, v3.0 empty 24 rh list empty indication 0 b at least one message object is allocated to list i. 1 b no message object is alloca ted to the list x. list x is empty. 0 [31:25] r reserved read as 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-73 v1.1, 2011-03 multican, v3.0 message notifications when a message object n generates an in terrupt request upon the transmission or reception of a message, then the request is routed to the interrupt output line selected by the bit field moiprn.txinp or moiprn.rxinp of the message object n. as there are more message objects than interrupt output lines, an interrupt routine typically processes requests from more than one message objec t. therefore, a priority selection mechanism is implemented in the multican module to select the highest priority object within a collection of message objects. the message pending register mspndk cont ains the pending interrupt notification of list i. mspndk (k = 0-7 ) message pending register k (140 h +k*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pnd rwh 1514131211109876543210 pnd rwh field bits type description pnd [31:0] rwh message pending when a message interrupt occurs, the message object sets a bit in one of the mspnd register, where the bit position is given by the mpn[4:0] field of the ipr register of the message object. the register selection n is given by the higher bits of mpn. the register bits can be cleared by software (write 0). writing a 1 has no effect. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-74 v1.1, 2011-03 multican, v3.0 each message pending register has a message index register msidk associated with it. the message index register shows the active (set) pending bit with lowest bit position within groups of pending bits. msidk (k = 0-7 ) message index register k (180 h +k*4 h ) reset value: 0000 0020 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 index rrh field bits type description index [5:0] rh message pending index the value of index is given by the bit position i of the pending bit of mspndk with the following properties: 1. mspndk[i] & im[i] = 1 2. i = 0 or mspndk[i-1:0] & im[i-1:0] = 0 if no bit of mspndk satisfies these conditions then index reads 100000 b . thus index shows the position of the first pending bit of mspndk, in which only those bits of mspndk that are selected in the message index mask register are taken into account. 0 [31:6] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-75 v1.1, 2011-03 multican, v3.0 the message index mask regist er msimask selects individual bits for the calculation of the message pending index. the message index mask register is used commonly for all message pending registers and their associated message index registers. msimask message index mask register (1c0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 im rw 1514131211109876543210 im rw field bits type description im [31:0] rw message index mask only those bits in mspndk for which the corresponding index mask bits are set contribute to the calculation of the message index. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-76 v1.1, 2011-03 multican, v3.0 24.6.2 can node registers the can node registers are built in for each can node of the multican module. they contain information that is directly related to the operation of the can nodes and are shared among the nodes. the node control register contains basic settings that determine the operation of the can node. ncrx (x = 0-3 ) node x control register (200 h +x*100 h ) reset value: 0000 0001 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 sus en cal m cce 0 can dis alie leci e trie init r rw rw rw r rw rw rw rw rwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-77 v1.1, 2011-03 multican, v3.0 field bits type description init 0rwh node initialization 0 b resetting bit init enables the participation of the node in the can traffic. if the can node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the init bit) is continued. with the end of the bus-off recovery sequence the can node is allowed to take part in the can traffic. if the can node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the can traffic. 1 b setting this bit terminates the participation of this node in the can traffic. any ongoing frame transfer is cancelled and the transmit line goes recessive. if the can node is in the bus-off state, then the running bus-off recovery sequence is continued. if the init bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the can node leaves the bus-off state but remains inactive as long as init remains set. bit init is automatically set when the can node enters the bus-off state (see page 24-28 ). trie 1rw transfer interrupt enable trie enables the transfer interrupt of can node x. this interrupt is generated after the successful reception or transmission of a can frame in node x. 0 b transfer interrupt is disabled. 1 b transfer interrupt is enabled. bit field niprx.trinp selects the interrupt output line which becomes activated at this type of interrupt. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-78 v1.1, 2011-03 multican, v3.0 lecie 2rw lec indicated error interrupt enable lecie enables the last error code interrupt of can node x. this interrupt is generated with each update of bit field nsrx.lec with lec > 0 (can protocol error). 0 b last error code interrupt is disabled. 1 b last error code interrupt is enabled. bit field niprx.lecinp selects the interrupt output line which becomes activated at this type of interrupt. alie 3rw alert interrupt enable alie enables the alert interrupt of can node x. this interrupt is generated by any one of the following events: ? a change of bit nsrx.boff ? a change of bit nsrx.ewrn ? a list length error, which also sets bit nsrx.lle ? a list object error, wh ich also sets bit nsrx.loe ? a bit init is set by hardware 0 b alert interrupt is disabled. 1 b alert interrupt is enabled. bit field niprx.alinp selects the interrupt output line which becomes activated at this type of interrupt. candis 4rw can disable setting this bit disables the can node. the can node first waits until it is bus-idle or bus-off. then bit init is automatically set, and an alert interrupt is generated if bit alie is set. cce 6rw configuration change enable 0 b the bit timing register, the port control register, and the error counter register may only be read. all attempts to modify them are ignored. 1 b the bit timing register, the port control register, and the error counter register may be read and written. calm 7rw can analyze mode if this bit is set, then the can node operates in analyze mode. this means that messages may be received, but not transmitted. no acknowledge is sent on the can bus upon frame reception. active-error flags are sent recessive instead of dominant. the transmit line is continuously held at recessive (1) level. bit calm can be written only while bit init is set. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-79 v1.1, 2011-03 multican, v3.0 susen 8rw suspend enable this bit makes it possible to set the can node into suspend mode via ocds (on chip debug support): 0 b an ocds suspend trigger is ignored by the can node. 1 b an ocds suspend trigger disables the can node: as soon as the can node becomes bus-idle or bus-off, bit init is internally forced to 1 to disable the can node. the actual value of bit init remains unchanged. bit susen is reset via ocds reset. 0 [31:9], 5 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-80 v1.1, 2011-03 multican, v3.0 the node status register nsrx reports erro rs as well as successfully transferred can frames. nsrx (x = 0-3 ) node x status register (204 h +x*100 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 sus ack loe lle bof f ewr n ale rt rxo k txo k lec r rh rwh rwh rh rh rwh rwh rwh rwh field bits type description lec [2:0] rwh last error code this bit field indicates the type of the last (most recent) can error. the encoding of this bit field is described in table 24-8 . txok 3rwh message transmitted successfully 0 b no successful transmission since last (most recent) flag reset. 1 b a message has been transmitted successfully (error-free and acknowledged by at least another node). txok must be reset by software (write 0). writing 1 has no effect. rxok 4rwh message received successfully 0 b no successful reception since last (most recent) flag reset. 1 b a message has been received successfully. rxok must be reset by software (write 0). writing 1 has no effect. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-81 v1.1, 2011-03 multican, v3.0 alert 5rwh alert warning the alert bit is set upon the occurrence of one of the following events (the same events which also trigger an alert interrupt if alie is set): ? a change of bit nsrx.boff ? a change of bit nsrx.ewrn ? a list length error, which also sets bit nsrx.lle ? a list object error, which also sets bit nsrx.loe ? bit init has been set by hardware alert must be reset by software (write 0). writing 1 has no effect. ewrn 6rh error warning status 0 b no warning limit exceeded. 1 b one of the error counters rec or tec reached the warning limit ewrnlvl. boff 7rh bus-off status 0 b can controller is not in the bus-off state. 1 b can controller is in the bus-off state. lle 8rwh list length error 0 b no list length error since last (most recent) flag reset. 1 b a list length error has been detected during message acceptance filtering. the number of elements in the list that belongs to this can node differs from the list size given in the list termination pointer. lle must be reset by software (write 0). writing 1 has no effect. loe 9rwh list object error 0 b no list object error sinc e last (most recent) flag reset. 1 b a list object error has been detected during message acceptance filtering. a message object with wrong list index entry in the message object control register has been detected. loe must be reset by software (write 0). writing 1 has no effect. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-82 v1.1, 2011-03 multican, v3.0 encoding of the lec bit field susack 10 rh suspend acknowledge 0 b the can node is not in suspend mode or a suspend request is pending, but the can node has not yet reached bus-idle or bus-off. 1 b the can node is in suspend mode: the can node is inactive (bit ncr.init internally forced to 1) due to an ocds suspend request. 0 [31:11] r reserved read as 0; should be written with 0. table 24-8 encoding of the lec bit field lec value signification 000 b no error: no error was detected for the last (most recent) message on the can bus. 001 b stuff error: more than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 010 b form error: a fixed format part of a received frame has the wrong format. 011 b ack error: the transmitted message was not acknowledged by another node. 100 b bit1 error: during a message transmission, the can node tried to send a recessive level (1) outside the arbitration field and the acknowledge slot, but the monitored bus value was dominant. 101 b bit0 error: two different conditions are signaled by this code: 1. during transmission of a message (or acknowledge bit, active-error flag, overload flag), the can node tried to send a dominant level (0), but the monitored bus value was recessive. 2. during bus-off recovery, this code is set each time a sequence of 11 recessive bits has been monitored. the cpu may use this code as indication that the bus is not continuously disturbed. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-83 v1.1, 2011-03 multican, v3.0 110 b crc error: the crc checksum of the received message was incorrect. 111 b cpu write to lec: whenever the the cpu writes the value 111 to lec, it takes the value 111. whenever the cpu writes another value to lec, the written lec value is ignored. table 24-8 encoding of the lec bit field (cont?d) lec value signification www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-84 v1.1, 2011-03 multican, v3.0 the four interrupt pointers in the node interrupt pointer register niprx select one out of the sixteen interrupt outputs individually for each type of can node interrupt. see also page 24-29 for more can node interrupt details. niprx (x = 0-3 ) node x interrupt pointer register (208 h +x*100 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 cfcinp trinp lecinp alinp rw rw rw rw field bits type description alinp [3:0] rw alert interrupt node pointer alinp selects the interrupt output line int_om (m = 0-15 ) for an alert interrupt of can node x. 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. lecinp [7:4] rw last error code interrupt node pointer lecinp selects the interrupt output line int_om (m = 0-15 ) for an lec interrupt of can node x. 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-85 v1.1, 2011-03 multican, v3.0 trinp [11:8] rw transfer ok interrupt node pointer trinp selects the interrupt output line int_om (m = 0-15 ) for a transfer ok interrupt of can node x. 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. cfcinp [15:12] rw frame counter interrupt node pointer cfcinp selects the interrupt output line int_om (m = 0-15 ) for a transfer ok interrupt of can node x. 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-86 v1.1, 2011-03 multican, v3.0 the node port control register npcrx configures the can bus transmit/receive ports. npcrx can be written only if bit ncrx.cce is set. npcrx (x = 0-3 ) node x port control register (20c h +x*100 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 lbm 0 rxsel rrwrrw field bits type description rxsel [2:0] rw receive select rxsel selects one out of 8 possible receive inputs. the can receive signal is performed only through the selected input. note: in TC1798, only specific combinations of rxsel are available (see also ?receive input selection? on page 24-209 ). lbm 8rw loop-back mode 0 b loop-back mode is disabled. 1 b loop-back mode is enabled. this node is connected to an internal (virtual) loop-back can bus. all can nodes which are in loop- back mode are connected to this virtual can bus so that they can communicate with each other internally. the external transmit line is forced recessive in loop-back mode. 0 [7:3], [31:9] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-87 v1.1, 2011-03 multican, v3.0 the node bit timing register nbtrx contains all parameters to set up the bit timing for the can transfer. nbtrx can be written only if bit ncrx.cce is set. nbtrx (x = 0-3 ) node x bit timing register (210 h +x*100 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 div8 tseg2 tseg1 sjw brp rw rw rw rw rw field bits type description brp [5:0] rw baud rate prescaler the duration of one time quantum is given by (brp + 1) clock cycles if div8 = 0. the duration of one time quantum is given by 8 (brp + 1) clock cycles if div8 = 1. sjw [7:6] rw (re) synchronization jump width (sjw + 1) time quanta are allowed for re- synchronization. tseg1 [11:8] rw time segment befo re sample point (tseg1 + 1) time quanta is the user-defined nominal time between the end of the synchronization segment and the sample point. it includes the propagation segment, which takes into account signal propagation delays. the time segment may be lengthened due to re-synchronization. valid values for tseg1 are 2 to 15. tseg2 [14:12] rw time segment afte r sample point (tseg2 + 1) time quanta is the user-defined nominal time between the sample point and the start of the next synchronization segment. it may be shortened due to re-synchronization. valid values for tseg2 are 1 to 7. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-88 v1.1, 2011-03 multican, v3.0 div8 15 rw divide prescaler clock by 8 0 b a time quantum lasts (brp+1) clock cycles. 1 b a time quantum lasts 8 (brp+1) clock cycles. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-89 v1.1, 2011-03 multican, v3.0 the node error counter register necntx contains the can receive and transmit error counter as well as some additional bits to ease error analysis. necntx can be written only if bit ncrx.cce is set. necntx (x = 0-3 ) node x error counter register (214 h +x*100 h ) reset value: 0060 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 lein c let d ewrnlvl rrhrh rw 1514131211109876543210 tec rec rwh rwh field bits type description rec [7:0] rwh receive error counter bit field rec contains the value of the receive error counter of can node x. tec [15:8] rwh transmit error counter bit field tec contains the value of the transmit error counter of can node x. ewrnlvl [23:16] rw error warning level bit field ewrnlvl determines the threshold value (warning level, default 96) to be reached in order to set the corresponding error warning bit ewrn. letd 24 rh last error transfer direction 0 b the last error occurred while the can node x was receiver (rec has been incremented). 1 b the last error occurred while the can node x was transmitter (tec has been incremented). leinc 25 rh last error increment 0 b the last error led to an error counter increment of 1. 1 b the last error led to an error counter increment of 8. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-90 v1.1, 2011-03 multican, v3.0 the node frame counter register nfcrx contains the actual value of the frame counter as well as control and status bits of the frame counter. 0 [31:26] r reserved read as 0; should be written with 0. nfcrx (x = 0-3 ) node x frame counter register (218 h +x*100 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 cfc ov cfci e 0cfmod cfsel rrwhrwrrwrw 1514131211109876543210 cfc rwh field bits type description cfc [15:0] rwh can frame counter in frame count mode (cfmod = 00 b ), this bit field contains the frame count value. in time stamp mode (cfmod = 01 b ), this bit field contains the captured bit time count value, captured with the start of a new frame. in all bit timing analysis modes (cfmod = 10 b ), cfc always displays the number of f clc clock cycles (measurement result) minus 1. example: a cfc value of 34 in measurement mode cfsel = 000 b means that 35 f clc clock cycles have been elapsed between the most recent two dominant edges on the receive input. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-91 v1.1, 2011-03 multican, v3.0 cfsel [18:16] rw can frame count selection this bit field selects the function of the frame counter for the chosen frame count mode. frame count mode bit 0 if bit 0 of cfsel is set, then cfc is incremented each time a foreign frame (i.e. a frame not matching to a message object) has been received on the can bus. bit 1 if bit 1 of cfsel is set, then cfc is incremented each time a frame matching to a message object has been received on the can bus. bit 2 if bit 2 of cfsel is set, then cfc is incremented each time a frame has been transmitted successfully by the node. time stamp mode 000 b the frame counter is incremented (internally) at the beginning of a new bit time. the value is sampled during the sof bit of a new frame. the sampled value is visible in the cfc field. bit timing mode the available bit timing meas urement modes are shown in table 24-9 . if cfcie is set, then an interrupt on request node x (where x is the can node number) is generated with a cfc update. cfmod [20:19] rw can frame counter mode this bit field determines the operation mode of the frame counter. 00 b frame count mode: the fram e counter is incremented upon the reception and transmission of frames. 01 b time stamp mode: the frame counter is used to count bit times. 10 b bit timing mode: the frame counter is used for analysis of the bit timing. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-92 v1.1, 2011-03 multican, v3.0 bit timing analysis modes cfcie 22 rw can frame count interrupt enable cfcie enables the can frame counter overflow interrupt of can node x. 0 b can frame counter overflow interrupt is disabled. 1 b can frame counter overflow interrupt is enabled. bit field niprx.cfcinp selects the interrupt output line that is activated at this type of interrupt. cfcov 23 rwh can frame counter overflow flag flag cfcov is set upon a frame counter overflow (transition from ffff h to 0000 h ). in bit timing analysis mode, cfcov is set upon an update of cfc. an interrupt request is generated if cfcie = 1. 0 b no overflow has occurred since last flag reset. 1 b an overflow has occurred since last flag reset. cfcov must be reset by software. 0 21, [31:24] r reserved read as 0; should be written with 0. table 24-9 bit timing analysis modes (cfmod = 10) cfsel measurement 000 b whenever a dominant edge (transition from 1 to 0) is monitored on the receive input, the time (measured in clock cycles) between this edge and the most recent dominant edge is stored in cfc. 001 b whenever a recessive edge (transition from 0 to 1) is monitored on the receive input the time (measured in clock cycles) between this edge and the most recent dominant edge is stored in cfc. 010 b whenever a dominant edge is received as a result of a transmitted dominant edge, the time (clock cycles) between both edges is stored in cfc. 011 b whenever a recessive edge is received as a result of a transmitted recessive edge, the time (clock cycles) between both edges is stored in cfc. 100 b whenever a dominant edge that qualifies for synchronization is monitored on the receive input, the time (measured in clock cycles) between this edge and the most recent sample point is stored in cfc. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-93 v1.1, 2011-03 multican, v3.0 101 b with each sample point, the time (measured in clock cycles) between the start of the new bit time and the start of the previous bit time is stored in cfc[11:0]. additional information is written to cfc[15:12] at each sample point: cfc[15]: transmit value of actual bit time cfc[14]: receive sample value of actual bit time cfc[13:12]: can bus information (see table 24-10 ) 110 b reserved, do not use this combination. 111 b reserved, do not use this combination. table 24-10 can bus state information cfc[13:12] can bus state 00 b nobit the can bus is idle, performs bit (de-) stuffing or is in one of the following frame segments: sof, srr, crc, delimiters, first 6 eof bits, ifs. 01 b newbit this code represents the first bit of a new frame segment. the current bit is the first bit in one of the following frame segments: bit 10 (msb) of standard id (transmit only), rtr, reserved bits, ide, dlc(msb), bit 7 (msb) in each data byte and the first bit of the id extension. 10 b bit this code represents a bit inside a frame segment with a length of more than one bit (not the first bit of those frame segments that is indicated by newbit). the current bit is processed within one of the following frame segments: id bits (except first bit of standard id for transmission and first bit of id extension), dlc (3 lsb) and bits 6-0 in each data byte. 11 b done the current bit is in one of the following frame segments: acknowledge slot, last bit of eof, active/passive-error frame, overload frame. two or more directly consecutive done codes signal an error frame. table 24-9 bit timing analysis modes (cfmod = 10) (cont?d) cfsel measurement www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-94 v1.1, 2011-03 multican, v3.0 24.6.3 message object registers the message object control register moctrn and the message object status register mostatn are located at the same address offset within a message object address block (offset address 1c h ). the moctrn is a write-only register that makes it possible to set/reset can transfer related control bits through software. moctr0 message object 0 control register (101c h ) reset value: 0100 0000 h moctr127 message object 127 control register(1ffc h ) reset value: 7f7e 0000 h moctrn (n = 1-126 ) message object n control register (101c h +n*20 h ) reset value: ((n+1)*01000000 h )+((n-1)*00010000 h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 set dir set txe n1 set txe n0 set txr q set rxe n set rts el set msg val set msg lst set new dat set rxu pd set txp nd set rxp nd w wwwwwwwwwwww 1514131211109876543210 0 res dir res txe n1 res txe n0 res txr q res rxe n res rts el res msg val res msg lst res new dat res rxu pd res txp nd res rxp nd w wwwwwwwwwwww field bits type description resrxpnd, setrxpnd 0, 16 w reset/set receive pending these bits control the set/reset condition for rxpnd (see table 24-11 ). restxpnd, settxpnd 1, 17 w reset/set transmit pending these bits control the set/reset condition for txpnd (see table 24-11 ). resrxupd, setrxupd 2, 18 w reset/set receive updating these bits control the set/reset condition for rxupd (see table 24-11 ). resnewdat, setnewdat 3, 19 w reset/set new data these bits control the set/reset condition for newdat (see table 24-11 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-95 v1.1, 2011-03 multican, v3.0 resmsglst, setmsglst 4, 20 w reset/set message lost these bits control the set/reset condition for msglst (see table 24-11 ). resmsgval, setmsgval 5, 21 w reset/set message valid these bits control the set/reset condition for msgval (see table 24-11 ). resrtsel, setrtsel 6, 22 w reset/set receive/transmit selected these bits control the set/reset condition for rtsel (see table 24-11 ). resrxen, setrxen 7, 23 w reset/set receive enable these bits control the set/reset condition for rxen (see table 24-11 ). restxrq, settxrq 8, 24 w reset/set transmit request these bits control the set/reset condition for txrq (see table 24-11 ). restxen0, settxen0 9, 25 w reset/set transmit enable 0 these bits control the set/reset condition for txen0 (see table 24-11 ). restxen1, settxen1 10, 26 w reset/set transmit enable 1 these bits control the set/reset condition for txen1 (see table 24-11 ). resdir, setdir 11, 27 w reset/set message direction these bits control the set/reset condition for dir (see table 24-11 ). 0 [15:12], [31:28] w reserved should be written with 0. table 24-11 reset/set conditions for bits in register moctrn resy bit 1) sety bit action on write write 0 write 0 leave element unchanged no write no write write 0 write 1 write 1 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-96 v1.1, 2011-03 multican, v3.0 write 1 write 0 reset element no write write 0 write 1 set element no write 1) the parameter ?y? stands for the second part of the bit name (?rxpnd?, ?txpnd?, ? up to ?dir?). table 24-11 reset/set conditions for bits in register moctrn (cont?d) resy bit 1) sety bit action on write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-97 v1.1, 2011-03 multican, v3.0 the mostatn is a read-only register that indicates message object list status information such as the number of the current message object predecessor and successor message object, as well as the list number to which the message object is assigned. mostat0 message object 0 status register (101c h ) reset value: 0100 0000 h mostat127 message object 127 status register (1ffc h ) reset value: 7f7e 0000 h mostatn (n = 1-126 ) message object n status register (101c h +n*20 h ) rest value: ((n+1)*01000000 h )+((n-1)*00010000 h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pnext pprev rh rh 1514131211109876543210 list dir tx en1 tx en0 tx rq rx en rts el msg val msg lst new dat rx upd tx pnd rx pnd rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description rxpnd 0rh receive pending 0 b no can message has been received. 1 b a can message has been received by the message object n, either directly or via gateway copy action. rxpnd is not reset by hardware but must be reset by software. txpnd 1rh transmit pending 0 b no can message has been transmitted. 1 b a can message from message object n has been transmitted successfully over the can bus. txpnd is reset by hardware but must be reset by software. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-98 v1.1, 2011-03 multican, v3.0 rxupd 2rh receive updating 0 b no receive update ongoing. 1 b message identifier, dlc, and data of the message object are currently updated. newdat 3rh new data 0 b no update of the message object n since last flag reset. 1 b message object n has been updated. newdat is set by hardware after a received can frame has been stored in message object n. newdat is cleared by hardware when a can transmission of message object n has been started. newdat should be set by software after the new transmit data has been stored in message object n to prevent the automatic reset of txrq at the end of an ongoing transmission. msglst 4rh message lost 0 b no can message is lost. 1 b a can message is lost because newdat has become set again when it has already been set. msgval 5rh message valid 0 b message object n is not valid. 1 b message object n is valid. only a valid message object takes part in can transfers. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-99 v1.1, 2011-03 multican, v3.0 rtsel 6rh receive/transmit selected 0 b message object n is not selected for receive or transmit operation. 1 b message object n is selected for receive or transmit operation. frame reception: rtsel is set by hardware when message object n has been identified for storage of a can frame that is currently received. before a received frame becomes finally stored in message object n, a check is performed to determine if rtsel is set. thus the cpu can suppress a scheduled frame delivery to this message object n by clearing rtsel by software. frame transmission: rtsel is set by hardware when message object n has been identified to be transmitted next. a check is performed to determine if rtsel is still set before message object n is actually set up for transmission and bit newdat is cleared. it is also checked that rtsel is still set before its message object n is verified due to the successful transmission of a frame. rtsel needs to be checked only when the context of message object n changes, and a conflict with an ongoing frame transfer shall be avoided. in all other cases, rtsel can be ignored. rtsel has no impact on message acceptance filtering. rtsel is not cleared by hardware. rxen 7rh receive enable 0 b message object n is not enabled for frame reception. 1 b message object n is enabled for frame reception. rxen is evaluated for receive acceptance filtering only. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-100 v1.1, 2011-03 multican, v3.0 txrq 8rh transmit request 0 b no transmission of message object n is requested. 1 b transmission of message object n on the can bus is requested. the transmit request becomes valid only if txrq, txen0, txen1 and msgval are set. txrq is set by hardware if a matching remote frame has been received correctly. txrq is reset by hardware if message object n has been transmitted successfully and newdat is not set again by software. txen0 9rh transmit enable 0 0 b message object n is not enabled for frame transmission. 1 b message object n is enabled for frame transmission. message object n can be transmitted only if both bits, txen0 and txen1, are set. the user may clear txen0 in order to inhibit the transmission of a message that is currently updated, or to disable automatic response of remote frames. txen1 10 rh transmit enable 1 0 b message object n is not enabled for frame transmission. 1 b message object n is enabled for frame transmission. message object n can be transmitted only if both bits, txen0 and txen1, are set. txen1 is used by the mult ican module for selecting the active message object in the transmit fifos. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-101 v1.1, 2011-03 multican, v3.0 dir 11 rh message direction 0 b receive object selected: with txrq = 1, a remote frame with the identifier of message object n is scheduled for transmission. on reception of a data frame with matching identifier, the message is stored in message object n. 1 b transmit object selected: if txrq = 1, message object n is scheduled for transmission of a data frame. on reception of a remote frame with matching identifier, bit txrq is set. list [15:12] rh list allocation list indicates the number of the message list to which message object n is allocated. list is updated by hardware when the list allocation of the object is modified by a panel command. pprev [23:16] rh pointer to previous message object pprev holds the message object number of the previous message object in a message list structure. pnext [31:24] rh pointer to next message object pnext holds the message object number of the next message object in a message list structure. table 24-12 mostatn reset values message object pnext pprev reset value 0 1 0 0100 0000 h 1 2 0 0200 0000 h 2 3 1 0301 0000 h 3 4 2 0402 0000 h ???? 60 61 59 3d3b 0000 h 61 62 60 3e3c 0000 h 62 63 61 3f3d 0000 h 63 63 62 3f3e 0000 h field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-102 v1.1, 2011-03 multican, v3.0 the message object interrupt pointer register moiprn holds the message interrupt pointers, the message pending number, and the frame counter value of message object n. moiprn (n = 0-127 ) message object n interrupt pointer register (1008 h +n*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cfcval rwh 1514131211109876543210 mpn txinp rxinp rw rw rw field bits type description rxinp [3:0] rw receive interrupt node pointer rxinp selects the interrupt output line int_om (m = 0-15 ) for a receive interrupt event of message object n. rxinp can also be taken for message pending bit selection (see page 24-44 ). 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. txinp [7:4] rw transmit interrupt node pointer txinp selects the interrupt output line int_om (m = 0-15 ) for a transmit interrupt event of message object n. txinp can also be taken for message pending bit selection (see page 24-44 ). 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-103 v1.1, 2011-03 multican, v3.0 mpn [15:8] rw message pending number this bit field selects the bit position of the bit in the message pending register that is set upon a message object n receive/transmit interrupt. cfcval [31:16] rwh can frame counter value when a message is stored in message object n or message object n has been successfully transmitted, the can frame counter value nfcrx.cfc is then copied to cfcval. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-104 v1.1, 2011-03 multican, v3.0 the message object function control register mofcrn contains bits that select and configure the function of the message object. it also holds the can data length code. mofcrn (n = 0-127 ) message object n function control register (1000 h +n*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0dlcsttsdtrmm frr en 0 ovie txie rxie rw rwh rwrwrwrwrwrwrwrw 1514131211109876543210 0 dat c dlc c idc gdf s 0 mmc rw rw rw rw rw rw rw field bits type description mmc [3:0] rw message mode control mmc controls the message mode of message object n. 0000 b standard message object 0001 b receive fifo base object 0010 b transmit fifo base object 0011 b transmit fifo slave object 0100 b gateway source object ... b reserved gdfs 8rw gateway data frame send 0 b txrq is unchanged in the destination object. 1 b txrq is set in the gateway destination object after the internal transfer from the gateway source to the gateway destination object. applicable only to a gateway source object; ignored in other nodes. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-105 v1.1, 2011-03 multican, v3.0 idc 9rw identifier copy 0 b the identifier of the gateway source object is not copied. 1 b the identifier of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. applicable only to a gateway source object; ignored in other nodes. dlcc 10 rw data length code copy 0 b data length code is not copied. 1 b data length code of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object. applicable only to a gateway source object; ignored in other nodes. datc 11 rw data copy 0 b data fields are not copied. 1 b data fields in registers modataln and modatahn of the gateway source object (after storing the received frame in the source) are copied to the gateway destination. applicable only to a gateway source object; ignored in other nodes. rxie 16 rw receive interrupt enable rxie enables the message receive interrupt of message object n. this interrupt is generated after reception of a can message (independent of whether the can message is received directly or indirectly via a gateway action). 0 b message receive interrupt is disabled. 1 b message receive interrupt is enabled. bit field moiprn.rxinp selects the interrupt output line which becomes activated at this type of interrupt. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-106 v1.1, 2011-03 multican, v3.0 txie 17 rw transmit interrupt enable txie enables the message transmit interrupt of message object n. this interrupt is generated after the transmission of a can message. 0 b message transmit interrupt is disabled. 1 b message transmit interrupt is enabled. bit field moiprn.txinp selects the interrupt output line which becomes activated at this type of interrupt. ovie 18 rw overflow inte rrupt enable ovie enables the fifo full interrupt of message object n. this interrupt is generated when the pointer to the current message object (cur) reaches the value of sel in the fifo/gateway pointer register. 0 b fifo full interrupt is disabled. 1 b fifo full interrupt is enabled. if message object n is a receive fifo base object, bit field moiprn.txinp selects the interrupt output line which becomes activated at this type of interrupt. if message object n is a transmit fifo base object, bit field moiprn.rxinp selects the interrupt output line which becomes activated at this type of interrupt. for all other message object modes, bit ovie has no effect. frren 20 rw foreign remote request enable specifies whether the txrq bit is set in message object n or in a foreign message object referenced by the pointer cur. 0 b txrq of message object n is set on reception of a matching remote frame. 1 b txrq of the message object referenced by the pointer cur is set on reception of a matching remote frame. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-107 v1.1, 2011-03 multican, v3.0 rmm 21 rw transmit object remote monitoring 0 b remote monitoring is disabled: identifier, ide bit, and dlc of message object n remain unchanged upon the reception of a matching remote frame. 1 b remote monitoring is enabled: identifier, ide bit, and dlc of a matching remote frame are copied to transmit object n in order to monitor incoming remote frames. bit rmm applies only to transmit objects and has no effect on receive objects. sdt 22 rw single data transfer if sdt = 1 and message object n is not a fifo base object, then msgval is reset when this object has taken part in a successful data transfer (receive or transmit). if sdt = 1 and message object n is a fifo base object, then msgval is reset when the pointer to the current object cur reaches the value of sel in the fifo/gateway pointer register. with sdt = 0, bit msgval is not affected. stt 23 rw single transmit trial if this bit is set, then txrq is cleared on transmission start of message object n. thus, no transmission retry is performed in case of transmission failure. dlc [27:24] rwh data length code bit field determines the number of data bytes for message object n. valid values for dlc are 0 to 8. a value of dlc > 8 results in a data length of 8 data bytes. if a frame with dlc > 8 is received, the received value is stored in the message object. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-108 v1.1, 2011-03 multican, v3.0 msc [31:28] rwh message status count (ttcan only) msc can have values between 0000 b and 0111 b . an increment of msc = 0111 b results in msc = 0111 b (no overflow). a decrement of msc = 0000 b results in msc = 0000 b (no underflow). transmission: when message object n is scheduled for transmission in an exclusive time window and the transmission is successful within this time window and the ttcan is in error state s0 or s1, msc is decremented by one. if the transmission fails, bit field msc is incremented by one. if the ttcan is in error state s2 and detects can bus-idle during the transmit enable window for message object n, msc is decremented by one (although this message object is not transmitted). reception: when message object n is scheduled for reception in an exclusive time window and the reception is successful within this time window, msc is decremented by one. if the reception does not take place within this time window, msc is incremented by one. if ttcan function is not available/enabled, bit field msc is unchanged. 0 [7:4], [15:12], 19 rw reserved read as 0 after reset; value last written is read back; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-109 v1.1, 2011-03 multican, v3.0 the message object fifo/gateway pointer register mofgprn contains a set of message object link pointers that are used for fifo and gateway operations. mofgprn (n = 0-127 ) message object n fifo/gateway pointer register (1004 h +n*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sel cur rw rwh 1514131211109876543210 top bot rw rw field bits type description bot [7:0] rw bottom pointer bit field bot points to the first element in a fifo structure. top [15:8] rw top pointer bit field top points to the last element in a fifo structure. cur [23:16] rwh current object pointer bit field cur points to the actual target object within a fifo/gateway structure. after a fifo/gateway operation cur is updated with the message number of the next message object in the list structure (given by pnext of the message control register) until it reaches the fifo top element (given by top) when it is reset to the bottom element (given by bot). sel [31:24] rw object select pointer bit field sel is the second (software) pointer to complement the hardware pointer cur in the fifo structure. sel is used for monitoring purposes (fifo interrupt generation). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-110 v1.1, 2011-03 multican, v3.0 message object n acceptance mask register moamrn contains the mask bits for the acceptance filtering of the message object n. moamrn (n = 0-127 ) message object n acceptance mask register (100c h +n*20 h ) reset value: 3fff ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 mid e am rw rw rw 1514131211109876543210 am rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-111 v1.1, 2011-03 multican, v3.0 field bits type description am [28:0] rw acceptance mask for message identifier bit field am is the 29-bit mask for filtering incoming messages with standard identifiers (am[28:18]) or extended identifiers (am[28:0]). for standard identifiers, bits am[17:0] are ?don?t care?. for ttc based transmit acceptance filtering (moarn.pri = 00 b ) register moamrn is used to specify the transmit column/row in which this message object may be transmitted in a time- triggered communication. it is then no longer used as an identifier mask. this means that all identifier bits are used for receive acceptance filtering. in this case amr contains the following information: ? moamr[5:0] = cycle ? moamr[13:8] = mcycle ? moamr[21:16] = column ? moamr[29:24] = mcolumn where cycle is the cycle count (transmit row) and column is the transmission column of the system matrix. mcycle and mcolumn are acceptance masks for matching cycle and column against the actual position within the system matrix of the time-triggered communication network. message object n may be transmitted only if cycle and column match the actual matrix position (given by cyctmr.bcc and cyctmr.csm). if more than one object with valid transmit request matches a given matrix position, the actually transmitted message object is chosen by list order. mide 29 rw acceptance mask bit for message ide bit 0 b message object n accepts the reception of both, standard and extended frames. 1 b message object n receives frames only with matching ide bit. 0 [31:30] rw reserved read as 0 after reset; value last written is read back; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-112 v1.1, 2011-03 multican, v3.0 message object n arbitration register mo arn contains the can identifier of the message object. moarn (n = 0-127 ) message object n arbitration register (1018 h +n*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pri ide id rw rwh rwh 1514131211109876543210 id rwh field bits type description id [28:0] rwh can identifier of message object n identifier of a standard message (id[28:18]) or an extended message (id[28:0]). for standard identifiers, bits id[17:0] are ?don?t care?. ide 29 rwh identifier extension bit of message object n 0 b message object n handles standard frames with 11-bit identifier. 1 b message object n handles extended frames with 29-bit identifier. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-113 v1.1, 2011-03 multican, v3.0 pri [31:30] rw priority class pri assigns one of the four priority classes 0, 1, 2, 3 to message object n. a lower pri number defines a higher priority. message objects with lower pri value always win acceptance filtering for frame reception and transmission over mess age objects with higher pri value. acceptance filtering based on identifier/mask and list position is performed only between message objects of the same priority class. pri also determines the acceptance filtering method for transmission: 00 b time-triggered can (ttcan): the message object mask register specifies the position(s) within the transmission matrix at which the message object n may be transmitted. transmit acceptance filtering is based on the list order. this means that message object n is considered for transmission only if there is no other message object with valid transmit request (msgval & txen 0 & txen1 = 1) that matches the actual position within the transmission matrix somewhere before this object in the list. 01 b transmit acceptance filtering is based on the list order. this means that message object n is considered for transmission only if there is no other message object with valid transmit request (msgval & txen0 & txen1 = 1) somewhere before this object in the list. 10 b transmit acceptance filtering is based on the can identifier. this means, message object n is considered for transmission only if there is no other message object with higher priority identifier + ide + dir (with respect to can arbitration rules) somewhere in the list (see table 24-13 ). 11 b transmit acceptance filtering is based on the list order (as pri = 01 b ). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-114 v1.1, 2011-03 multican, v3.0 transmit priority of msg. obj ects based on can arbitration rules table 24-13 transmit priority of msg. objects based on can arbitration rules settings of arbitrarily chosen message objects a and b, (a has higher transm it priority than b) comment a.moar[28:18] < b.moar[28:18] (11-bit standard identifier of a less than 11-bit standard identifier of b) messages with lower standard identifier have higher priority than messages with higher standard identifier. moar[28] is the most significant bit (msb) of the standard identifier. moar[18] is the least significant bit of the standard identifier. a.moar[28:18] = b.moar[28:18] a.moar.ide = 0 (send standard frame) b.moar.ide = 1 (send extended frame) standard frames have higher transmit priority than extended frames with equal standard identifier. a.moar[28:18] = b.moar[28:18] a.moar.ide = b.moar.ide = 0 a.moctr.dir = 1 (send data frame) b.moctr.dir = 0 (send remote fame) standard data frames have higher transmit priority than standard remote frames with equal identifier. a.moar[28:0] = b.moar[28:0] a.moar.ide = b.moar.ide = 1 a.moctr.dir = 1 (send data frame) b.moctr.dir = 0 (send remote frame) extended data frames have higher transmit priority than extended remote frames with equal identifier. a.moar[28:0] < b.moar[28:0] a.moar.ide = b.moar.ide = 1 (29-bit identifier) extended frames with lower identifier have higher transmit priority than extended frames with higher identifier. moar[28] is the most significant bit (msb) of the overall identifier (standard identifier moar[28:18] and identifier extension moar[17:0]). moar[0] is the least significant bit (lsb) of the overall identifier. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-115 v1.1, 2011-03 multican, v3.0 message object n data register low modataln contains the lowest four data bytes of message object n. unused data bytes are set to zero upon reception and ignored for transmission. modataln (n = 0-127 ) message object n data register low (1010 h +n*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 db3 db2 rwh rwh 1514131211109876543210 db1 db0 rwh rwh field bits type description db0 [7:0] rwh data byte 0 of message object n db1 [15:8] rwh data byte 1 of message object n db2 [23:16] rwh data byte 2 of message object n db3 [31:24] rwh data byte 3 of message object n www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-116 v1.1, 2011-03 multican, v3.0 message object n data register high modatah contains the highest four data bytes of message object n. unused data bytes are set to zero upon reception and ignored for transmission. modatahn (n = 0-127 ) message object n data register high (1014 h +n*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 db7 db6 rwh rwh 1514131211109876543210 db5 db4 rwh rwh field bits type description db4 [7:0] rwh data byte 4 of message object n db5 [15:8] rwh data byte 5 of message object n db6 [23:16] rwh data byte 6 of message object n db7 [31:24] rwh data byte 7 of message object n www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-117 v1.1, 2011-03 multican, v3.0 24.7 time-triggered extension (ttcan controller) 24.7.1 generation of the local time the nominal time unit (ntu) of the ttcan controller is generated by the ntu timer with a clock derived from the fractional divider (an ntu timer action takes place with t q or with a multiple of 1/ f can ). the sum of the ntu is the local time lt, which is a 16-bit value (to be considered as integer number) and a fractional part ltfr. figure 24-26 generation of the local time mca0585 1 lrefm 16 lrefmfr refm refmfr 7 16 synm synmfr 7 16 lt ltfr 7 reference message correctly transferred frame_sync (sof) 16 16 10 10 increment by 1 adder tur turadj ntu timer control new basic cycle 10 ttcan level t q nominal can bit time f can ltur www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-118 v1.1, 2011-03 multican, v3.0 note: register ltur is used for the internal automatic calculation of the new turadj value. it is not visible for the user. in ttcan level 1, the lt counter is incr emented once per can bit time. the fractional part ltfr of the local time and the tur are not taken into account. in ttcan level 2, the lt is extended by its fractional part ltfr. the tur value is added to the ltfr value with the update period t upd in order to generate a new lt value. if an overflow occurs (carry active) after an addition of ltfr and tur, the value of lt is incremented by 1. as a result, the value of lt can change only in steps of 1, whereas the value of ltfr changes in steps of tur. in order to cover a wide range of can baud rates with the same counting range of the local timer, the counting can take place every can time quantum t q ( t upd = t q ). if another resolution of the ntu is desired, the local time generation can also be based on the clock f can , divided by a programmable factor that is independent from the can bit timing. after the update period t upd has elapsed n times, the difference in local time d t has elapsed to: d t = turr.tur/1024 n t upd . 24.7.2 automatic tur adjust it is possible to automatically calculate t he new value written to turadj for adjusting the correct value for the local time on ttcan level 2. each time a new reference message is correctly received, the difference is calculated between the time values in the reference message (gmr) and the previous reference message (lgmr). this difference, divided by the amount of own ntus for a complete basic cycle multiplied by ltur, provides the turadj value (including fractional parts). turadj = ltur (gm - lgm) / (refm - lrefm) the automatic tur adjust is not made when a discontinuity has been signaled between the reference messages. the automatic calculation of the new value for turadj takes place during the basic cycle. the value of tur is updated at the beginn ing of each basic cycle. the new value that is written to tur to adjust the timing is stored in the bit field turadj. 24.7.3 cycle time the cycle time is always positive and represents the time elapsed in the current basic cycle, starting from 0. 24.7.3.1 local time and synchronization marks the cycle time is the difference between the lo cal time (stored in bi t field lt) and its last reference mark (stored in bit field refm). the result is available in the bit field cyctm. the value of the local time lt is captured at the start of each message as a synchronization mark synm. if the correctly received message has been a reference www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-119 v1.1, 2011-03 multican, v3.0 message, the captured value becomes the re ference mark refm. the refm value of the previous reference mark is stored in lrefm. the cycle time is still incremented while the reference message is re ceived. after the end of the correctly received reference message, the cycle time takes the value corresponding to the length of this reference message. as a result, the cycle time seems to start from zero each time a reference me ssage starts (= with each new basic cycle). figure 24-27 generation of the cycle time the cycle control unit also delivers the va lues for the basic cycle and matrix cycle handling, and provides the possibility to gen erate an interrupt if a new basic cycle has started or a new matrix cycle has started. if the ttcan node receives a reference message, the value for bcc is taken from the reference message. 24.7.3.2 time marks each time a reference message is received correctly, the cycle control unit starts again comparing the cycle time to the first time mark (tm 1). if one time mark is reached, it continues with the next one. in order to be able to do an ?equal-to? comparison, the time marks have to be programmed in increasing order and the first time mark must not be lower than the maximum length of the reference message plus 5 bit times. the cycle time is used to determine the diff erent columns of the s ystem matrix (csm = column of the system matrix). these columns are defined by the time marks. these time marks can be programmed and are valid for all columns of the system matrix. the cycle control unit also checks the number of the current basic cycle that is indicated by the basic cycle count bcc. the value of bcc and the value of csm, take n together, clearly identify each time window in the matrix cycle. in master mode, the value bcc is transmi tted as part of the reference message. mca05852 equal ? scheduler cycle control unit m u x tm 2 tm 1 . . . . csm bcc tm n cyctm lt ltfr refm refmfr subtract 16 7 16 (msb) r eference message c orrectly transferred 16 16 7 6 6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-120 v1.1, 2011-03 multican, v3.0 24.7.3.3 watch trigger the watch trigger is used to check if the elapsed time since the last reference message was received is too long. this is done by comparing the programmed watch trigger value to the cycle time. this information can generate an in terrupt to the system. the watch trigger value is defined by the schedul er entry for the end of the basic cycle. 24.7.4 master reference mark (level 2 only) the time master sends the sum of its refe rence mark synm (integer part) and synmfr (fractional part) and its local offset lof (integer part) and loffr (fractional part) as master reference mark (mrm), which is stored in the global mark register gmr. if the master?s clock or its local time has been corrected and a discontinuity has been introduced, the discontinuity bit disc is automatically set until the next reference message is started. the discontinuity bit is set if a write access to lof or loffr occurs. as a result, the reference message will contain the new reference mark and the discontinuity bit disc set for the current time master. 24.7.5 transmit enable window the transmit enable window determines the number of can bit times that may elapse between the transmit trigger event (time marks in the scheduler) and the real start of the message on the bus. if this time expires wit hout starting the transmission of the triggered message, no new transmission attempt will be made in this time window (if it was an exclusive one or a short arbitration one). th e transmit trigger is deleted and an interrupt may be generated. if the time window is a long, merged arbitration window, the transmit enable window is not taken into account. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-121 v1.1, 2011-03 multican, v3.0 24.7.6 local offset and global time on ttcan level 2, the local offset of a ttcan node (not of the time master) is defined as the difference between the master_ref_m ark (also named global_ref_mark) and the node?s reference mark ref_mark. for the time master, the sum of the local time and the local offset is stored as global_sync_mark when the frame synchronization is reached. the global_sync_mark (for the time master) and the global_ref_mark (for all other nodes) are stored in the global mark regist er gmr. the local_offset is stored in the local offset register lor. when a ttcan node receives a reference mess age, the global mark register is updated by the received value. the value that has been received in the previous reference message is automatically transferred from the gl obal mark register to the last global mark register. the difference between these two values represents the time elapsed between the last two reference messages from the time master?s point of view. figure 24-28 local offset and global time mca05853 r eference m essage c orrectly t ransferred refm refmfr synm synmfr lt ltfr a ny f rame_sync gm gmfr add lof loffr lof loffr subtract 16 7 lgm lgmfr gm gmfr for reception of ref. msg. for transmission of ref. msg. f rame-sync o f ref. msg 16 7 16 7 16 7 16 7 16 7 16 7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-122 v1.1, 2011-03 multican, v3.0 due to possible variations of the lof values from one reference mark to the other, the current global time may contain discontinuities. in order to get a smooth (continuous) behavior, a sw filter can be used for receiving nodes. the global time can be calculated as shown below: ? local time + local offset or ? cycle time + reference mark + local offset 24.7.7 transmit trigger the ttcan feature of a can node implies the counting of transmission requests for messages to be sent in exclusive time windows. the number of messages to be transmitted in exclusive time windows is de fined by system applic ation design for the entire system matrix (expected transmit trig gers exptt). this theoretical value is used to verify if the real ttcan node also requests the same amount of transmissions. if fewer or more transmit triggers have been counted by the transmit trigger counter ttcnt at the end of a system matrix, a transmit trigger error interrupt can be generated (if enabled by ttien). this is indicated by th e bits transmit trigger underflow ttuf and transmit trigger overflow ttof. figure 24-29 transmit trigger monitoring mca05854 ttcnt equal ? exptt ttof control transmit trigg er error interrupt & ttuf ttien new matrix c ycle i nterrupt r equest 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-123 v1.1, 2011-03 multican, v3.0 24.7.8 reference message the reference message object has a special role in the ttcan system. it is the first entry in the message object list for the ttcan node (node 0 in the TC1798). 24.7.8.1 differences to normal can messages there are several differences between the behavior of a reference message and a normal can message: ? if a reference message is disturbed by an error during transmission, it is retransmitted immediately. ? if a reference message loses arbitration, it is not retransmitted, but the message on the bus is received (arbitration of potential time masters). ? for reception, no identifier bits (except the 3 least significant bits id[2:0]) use an acceptance mask (must be set by software). the entire identifier of the latest correct reference message on the bus is stored in the reference message object. ? for reception, the 3 least significant bits of the identifier always use the acceptance mask 000 b (must be set by software). ? its transmission request, indicated by th e flag ttsr.reftrg, is related only to a reference time mark or to an external event (for synchronization). if a correct reference message is received while reftrg is set, reftrg is automatically cleared. ? for transmission, the identifier bits of the reference message object are taken, except the 3 least significant bits (id[2:0]). they are taken from the bit field tmcr.tmprio. ? the corresponding parts of its eight data bytes are directly connected to the ttcan internal values (cycle_count, master_ref_mark, etc.) acco rding to the selected level of the ttcan protocol. the remainin g bytes are available for free use. ? the dlc of a reference message to be sent out is determined by the bit field ttcr.rmdlc. this bit field must be at least 1 in ttcan level 1 and at least 4 in ttcan level 2. a reference message object is used by a time master, a potential time master, and a receiving device (not a time master). the reference message object must be initialized as a receive object (but the transmission of this object leads to the refer ence frame). this is due to the fact that the reception of a reference message is determined by the normal receive acceptance filtering, whereas the transmission is a specific action, triggered by the ttcan extension. reference messages can also be transmitted by time masters that are in s2 error state or after the init_watch_trigger has been reached. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-124 v1.1, 2011-03 multican, v3.0 24.7.8.2 transmit trigger for a reference message the transmission of a reference message can be triggered by a time mark or by an external event. if it is triggered by a time mark, the ?next is gap? bit (ttsr.nig) of the previous reference message has been 0. if it is triggered by an external event, the ?next is gap? bit of the previous reference message has been 1. the software can set bit ttsr.nig in order to initiate the synchronization of a reference message to an event. this event can be an edge at an external input or a software action (write bit ttfmr.ste = 1, software trigger event). when ttsr.nig is set, it will be transmitted with the next reference message in order to indicate the following synchronization gap to the other can nodes. the value of ttsr.nig is copied to bit ttsr.etr (external trigger request) and cleared automatically when the reference message has been correctly transmitted. bit ttsr.etr = 1 indicates that the next reference message will be transferred as soon as the corresponding time mark is reached (respecting the gap), or when the selected trigger event (etrev) is pending. the evaluation of etrev is started after the end of the transmit enable window of the last transfer window (valid rme found). the transmit trigger generation logic for the reference message is shown in figure 24-30 . the edge detection for ecttx contains a synchronization stage. the trigger event can be selected by bit field etesel (external trigger event selection). only trigger events are taken into account for the transfer of a reference message that have been detected after the start of the current basic cycle. the synchronization of more than one ttcan node to other ttcan nodes can be achieved by setting etesel = 00 b . in this case, the trigger of the reference message of ttcan nodes 0-7 (trmcx) is used to trigger the transmission of the reference message. as a result, the reference messages can be synchronized between several ttcan nodes of the multican/ttcan. if not all possible ttcan nodes are implemented, the trmcx of not implemented nodes are 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-125 v1.1, 2011-03 multican, v3.0 figure 24-30 external trigger generation an transmit trigger for the reference message . . . . mca05855_a.vsd etr nig etssel 0 ectt1 ectt7 000 001 . . . 111 ste = 1 etesel trmcx s end reference message rme trigger trigger by reference mark of this ca n node ( x) reference message transferred correctly or reset by software set/reset by s w & . . . . trmc 0 000 001 . . . 111 trmc 1 trmc 7 trigger for reference mark of another ttca n node (input x for this ttca n node = 0) set 00 01 10 11 etrev 0 1 etm reset trigger e vent reference message transmitted correctly reference message received correctly or reset by software valid rme entry found transmit enable window closed reset no other message can be started last transmit window reached 1 1 reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-126 v1.1, 2011-03 multican, v3.0 24.8 ttcan scheduler 24.8.1 overview the message transmission and reception of the time-triggered part ttcan is controlled by a scheduler mechanism. this scheduler is based on the cycle time and delivers the time marks. the time marks are defined by the time mark entries tmex. whenever a time mark is reached, programmable actions (defined by scheduler memory instruction entries instrxy) can take place. typical instructions include, for example, starting the transmission of a message, checking if a message has been received, opening or closing arbitration windows, or generating interrupts. figure 24-31 scheduler overview the instructions following a time mark are read by the scheduler until the next time mark entry is found. then, the instruction collection process is stopped until the next time mark is reached. note: the time mark values in the scheduler entries must be in increasing order. mca0585 6 . . . . . instrn0 tmen . . . . . instr20 tme2 instr21 . . . . . instr10 tme1 instr11 scheduler memory tm n 16 equal ? refm 16 .... scheduler cycle control unit bcc csm scheduler addressing scheduler instruction unit update msc update wte transmit trigge rs arb interrupts reference message trigger trmcx mux www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-127 v1.1, 2011-03 multican, v3.0 24.8.2 scheduler memory the scheduler contains a memory block in wh ich the time mark entries (tmex) and the scheduler instruction entries (instrnx) ar e stored. each time mark entry can be followed by a number of scheduler instruct ions. the scheduler memory is organized as a 32-bit wide memory holding the 32-bit wide time mark entries and the 32-bit wide scheduler instruction entries. the total number of time mark entries and scheduler instruction entries that can be stored is limited by the size of the scheduler memory. in the TC1798, the scheduler memory has a size of 128 words (32-bits). figure 24-32 ttcan scheduler memory the last word address of the scheduler memory is reserved for the start pointer stptr0. the value written at this address determines th e start location of the first entry for the ttcan node (= can node 0 in the TC1798). st ptr0 indicates how many 32-bit (word) entries below sptr0 the first time mark entry (tme1) is located. when the basic cycle end entry bce (with gm = 0) is read by the scheduler, it prepares the next scheduler instructions (read from scheduler memory) starting again with tme1. mca05857 stptr0 = start pointer to the first entry of each b asic cycle = tme1 stptr0 bce . . . . . instrnz . . . . . instrn0 tmen . . . . . instr30 tme3 instr2y . . . . . instr20 tme2 instr21 instr1x . . . . . instr10 tme1 instr11 scheduler memory scheduler entrie s for ttcan of can node 0 end address of the schedule r memory www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-128 v1.1, 2011-03 multican, v3.0 therefore, the first entry read after bce is stptr0 in order to obtain the address where tme1 is located. 24.8.2.1 scheduler entry types the scheduler instruction entries are located after the time mark entry. the time mark entry determines the behavior of the ttcan when the next time mark is reached. the scheduler instructions after the time mark entry are valid for the time mark they follow. the scheduler control reads the time mark entry and sets up the compare action (compare between the new time mark with the cycle time). then, the scheduler reads the following instructions and sets up the transfer behavior of the ttcan node. the scheduler stops reading from the scheduler memory when a new time mark entry is found. the transfer behavior set up can change with each scheduler instruction. there is no built-in consistency check for scheduler instructions. previously read scheduler instructions can be overwritten by subsequent ones. with each time mark, the settings are cleared and must be set up by new scheduler instructions (if desired). the complete scheduler inform ation must be finished with a basic cycle end entry that fixes the value for the watch trigger event. each entry in the scheduler memory contains a 4-bit wide code field that determines the type of the entry. the possible scheduler memory entry types are listed in table 24-14 . the general transmit trigger control for the message objects to be transmitted when a time mark is reached is performed by th e message objects themselves. in order to increase the flexibility, the result of the acceptance filtering done with the message objects can be overruled by control entries. a reference message can be transmitted only when the ttcan node is enabled as time master. table 24-14 scheduler memory entry types entry code ec bits [31:28] short name entry type defined at 0001 b tme time mark entry see page 24-129 0010 b ice interrupt control entry see page 24-132 0011 b arbe arbitration entry see page 24-134 0100 b tce transmit control entry see page 24-136 0101 b rce receive control entry see page 24-139 0110 b rme reference message entry see page 24-141 0111 b bce basic cycle end entry see page 24-143 other combinations eos end of scheduler memory entry see page 24-144 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-129 v1.1, 2011-03 multican, v3.0 note: the number of scheduler entries following a time mark should not exceed the number of 10. in order to minimize the required accesses to the scheduler memory by the scheduler control part, the user should set up the system carefully. 24.8.2.2 scheduler entr y type description time mark entry a time mark entry is defined as follows: tme time mark entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0001 0 arbm ien rec f1 ien rec f0 ien tra f1 ien tra f0 inp rw rw rw rw r rw rw rw rw rw rw 1514131211109876543210 tmv rw field bits type description tmv 1) [15:0] rw time mark value this bit field determines the compare value used for the next compare action with the cycle time. inp [19:16] rw interrupt node pointer inp selects the interrupt output line int_om (m = 0-15) that will be activated when a match is detected between the cycle ti me and the time mark value defined by tmv and if at least one of the four interrupt conditions is met and enabled. 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-130 v1.1, 2011-03 multican, v3.0 ientraf0 20 rw interrupt enable if traf = 0 this bit enables the generation of an interrupt when bit ttsr.traf = 0 and a match is detected between the cycle time and the time mark value defined by tmv. 0 b interrupt generation is disabled. 1 b interrupt generation is enabled. ientraf1 21 rw interrupt enable if traf = 1 this bit enables the generation of an interrupt when bit ttsr.traf = 1 and a match is detected between the cycle time and the time mark value defined by tmv. 0 b interrupt generation is disabled. 1 b interrupt generation is enabled. ienrecf0 22 rw interrupt enable if recf = 0 this bit enables the generation of an interrupt when when bit ttsr.recf = 0 and a match is detected between the cycle time and the time mark value defined by tmv. 0 b interrupt generation is disabled. 1 b interrupt generation is enabled. ienrecf1 23 rw interrupt enable if recf = 1 this bit enables the generation of an interrupt when when bit ttsr.recf = 1 and a match is detected between the cycle time and the time mark value defined by tmv. 0 b interrupt generation is disabled. 1 b interrupt generation is enabled. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-131 v1.1, 2011-03 multican, v3.0 note: the interrupt settings given by the time mark entry can be overruled by a subsequent valid interrupt control entry. the settings are valid until the next time mark is reached. for the time after the next time mark, the settings read from the next time mark entry become valid. arbm [25:24] rw arbitration mode this bit field determines the action that is taken with an arbitration window. 00 b no action taken; the status of the arbitration window is not changed. 01 b a merged (long) arbitration window will be opened. if it is already opened, it is kept open. 10 b a merged (long) transfer window will be closed. closing a merged transfer window leads to a single (short) arbitration window (transmission possible only during the transmit enable window). the short arbitration window is automatically closed after one time window. if there is no arbitration window open, this entry will be ignored. 11 b a single (short) arbitration window (transmission possible only during the transmit enable window) is opened. a short arbitration window is automatically closed after one time window. ec [31:28] rw entry code the entry code ec = 0001 b defines this scheduler memory entry as a time mark entry. 0 [27:26] r reserved; read as 0; should be written with 0. bits are ?don?t care? for scheduler operation when ec = 0001 b . 1) in order to be able to detect each time mark correctly, the first time mark of a basic cycle must not be set to a value below the length of the reference message under worst case conditions. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-132 v1.1, 2011-03 multican, v3.0 interrupt co ntrol entry an interrupt control entry is defined as follows: ice interrupt control entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0010 0 ien rec f1 ien rec f0 ien tra f1 ien tra f0 inp rw rw rw rw r rw rw rw rw rw 1514131211109876543210 0 mcycle 0 cycle rrw rrw field bits type description cycle [5:0] rw basic cycle number this bit field determines the number of the basic cycle during which this interrupt control entry is valid. the value of cycle is compared (bit-wise) to the current value of the bit field cyctmr.bcc. the result is then masked with the value given by the bit field mcycle in order to determine the repetition rate for this scheduler en try inside the matrix cycle. this bit field is equivalent to the corresponding part of the moamrn.am bit field (see page 24-110 ). mcycle [13:8] rw mask for cycle comparison this bit field determines the mask that is used to determine the repetition rate for this scheduler entry. this bit field is equivalent to the corresponding part of the moamrn.am bit field (see page 24-110 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-133 v1.1, 2011-03 multican, v3.0 inp [19:16] rw interrupt node pointer inp selects the interrupt output line int_om (m = 0-15) that will be activated when a match is detected between the cycle ti me and the time mark value defined by tmv and if at least one of the four interrupt conditions is met and enabled. 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ?? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. ientraf0 20 rw interrupt enable if traf = 0 this bit enables the generation of an interrupt when a match is detected between the cycle time and the time mark value defined by tmv and bit traf = 0. 0 b an interrupt will not be generated. 1 b an interrupt will be generated. ientraf1 21 rw interrupt enable if traf = 1 this bit enables the generation of an interrupt when a match is detected between the cycle time and the time mark value defined by tmv and bit traf = 1. 0 b an interrupt will not be generated. 1 b an interrupt will be generated. ienrecf0 22 rw interrupt enable if recf = 0 this bit enables the generation of an interrupt when a match is detected between the cycle time and the time mark value defined by tmv and bit recf = 0. 0 b an interrupt will not be generated. 1 b an interrupt will be generated. ienrecf1 23 rw interrupt enable if recf = 1 this bit enables the generation of an interrupt when a match is detected between the cycle time and the time mark value defined by tmv and bit recf = 1. 0 b an interrupt will not be generated. 1 b an interrupt will be generated. ec [31:28] rw entry code the entry code ec = 0010 b defines this scheduler memory entry as an interrupt control entry. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-134 v1.1, 2011-03 multican, v3.0 note: the interrupt settings of a valid inte rrupt control entry ov errule the previously stored interrupt settings for the next time mark. as a result, the use of more than one valid interrupt control entry between two time mark entries should be avoided. arbitration entry the arbitration entry is defined as follows: 0 [7:6], [15:14], [27:24] r reserved; read as 0; should be written with 0. bits are ?don?t care? for scheduler operation when ec = 0011 b . arbe arbitration entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0011 0 arbm 0 rw rw rw rw r rw r 1514131211109876543210 0 mcycle 0 cycle rrw rrw field bits type description cycle [5:0] rw basic cycle number this bit field determines the number of the basic cycle during which this arbitr ation entry is valid. the value of cycle is compared (bit-wise) with the current value of bit field cyctmr.bcc. the result is then masked with the value given by the bit field mcycle in order to determine the repetition rate for this scheduler entry inside the matrix cycle. this bit field is equivalent to the corresponding part of the moamrn.am bit field (see page 24-110 ). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-135 v1.1, 2011-03 multican, v3.0 note: the arbitration settings of a valid arbi tration entry overrule the previously stored arbitration settings for the next time mark . as a result, the use of more than one valid arbitration entry between two time mark entries should be avoided. mcycle [13:8] rw mask for cycle comparison this bit field determines the mask used to determine the repetition rate for this arbitration entry. this bit field is equivalent to the corresponding part of the moamrn.am bit field (see page 24-110 ). arbm [25:24] rw arbitration mode this bit field determines the action that is taken with an arbitration window. 00 b no action is taken; the status of the window is not changed. 01 b a merged (long) arbitration window will be opened. if it is already opened, it is kept open. 10 b a merged (long) transfer window will be closed. closing a merged transfer window leads to a single (short) arbitration window (transmission possible only during the transmit enable window). the short arbitration window is automatically closed after one time window. 11 b a single (short) arbitration window (transmission possible only during the transmit enable window) is opened. a short arbitration window is automatically closed after one time window. ec [31:28] rw entry code the entry code ec = 0011 b defines this scheduler memory entry as an arbitration entry. 0 [7:6], [23:14], [27:26] r reserved; read as 0; should be written with 0. bits are ?don?t care? for scheduler operation when ec = 0011 b . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-136 v1.1, 2011-03 multican, v3.0 transmit control entry the transmit control entry is defined as follows: tce transmit control entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 01000 alt msg tr en tcemsgnr rw rw rw rw r rw rw rw 1514131211109876543210 0 mcycle 0 cycle rrw rrw field bits type description cycle [5:0] rw basic cycle number this bit field determines the number of the basic cycle during which this transm it control entry is valid. the value of cycle is compared (bit-wise) to the current value of the bit field cyctmr.bcc. the result is then masked with the value given by the bit field mcycle in order to determine the repetition rate for this transmit control entry inside the matrix cycle. this bit field is equivalent to the corresponding part of the moamrn.am bit field (see page 24-110 ). mcycle [13:8] rw mask for cycle comparison this bit field determines the mask that is used to determine the repetition rate for this transmit control entry. this bit field is equivalent to the corresponding part of the moamrn.am bit field (see page 24-110 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-137 v1.1, 2011-03 multican, v3.0 tcemsgnr [23:16] rw tce message number this bit field determines the number of the message object to be transmitted when the next time mark is reached. the object will be transferred only if it is tagged valid for transmission. with this scheduler instruction, the number of the message object is defined directly, without taking into account to which can node it is currently assigned. even if it is assigned to another can node, the selected message object will be transmitted. if the can message transmit acceptance filtering delivers an object number to be transmitted, it is overruled by a valid transmit control entry according to altmsg. if the message object delivered by the transmit control entry is not valid for transmission, no transmission will be started. tren 24 rw transmission enable this bit enables transmissi on of a message object in the next time window due to the ttcan transmit trigger. 0 b neither a ttcan transmit trigger nor the message object transmit acceptance will lead to a transmission of a message object in the next time window. 1 b if a ttcan transmit trigger occurs or the message object transmit acceptance filtering delivers a valid message object, the transmission of a message object in the next time window is enabled. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-138 v1.1, 2011-03 multican, v3.0 note: the message transmit settings of a valid transmit control entry overrule the previously stored transmit se ttings and may also overrule the transmit acceptance filtering of the message obj ects for the next time mark (depending on bit altmsg). as a result, the use of more than one valid transmit control entry between two time mark entries should be avoided. altmsg [26:25] rw alternative message this bit field determines which message object will be transmitted. 00 b if the message object number delivered by this entry is not valid for transmission, no message will be sent. 01 b the message object number delivered by this entry is not taken into account for transmission, the message object found by the transmit acceptance filtering will be sent if it is valid. 10 b if the message object delivered by this entry is not valid for transmission, while the message object transmit acceptance filtering delivered a valid object, the latter one will be sent out. 11 b reserved ec [31:28] rw entry code the entry code ec = 0100 b defines this scheduler memory entry as a transmit control entry. 0 [7:6], [15:14], 27 r reserved; read as 0; should be written with 0. bits are ?don?t care? for scheduler operation when ec = 0100 b . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-139 v1.1, 2011-03 multican, v3.0 receive control entry the receive control entry is defined as follows: rce receive control entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0101 0 ch en rcemsgnr rw rw rw rw r rw rw 1514131211109876543210 0 mcycle 0 cycle rrw rrw field bits type description cycle [5:0] rw basic cycle number this bit field determines the number of the basic cycle during which this rece ive control entry is valid. the value of cycle is compared (bit-wise) to the current value of the bit field cyctmr.bcc. the result is then masked with the value given by the bit field mcycle in order to determine the repetition rate for this scheduler en try inside the matrix cycle. this bit field is equivalent to the corresponding part of the moamrn.am bit field (see page 24-110 ). mcycle [13:8] rw mask for cycle comparison this bit field determines the mask that is used to determine the repetition rate for this scheduler entry. this bit field is equivalent to the corresponding part of the moamrn.am bit field (see page 24-110 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-140 v1.1, 2011-03 multican, v3.0 note: the settings of a valid receive cont rol entry overrule the previously stored information. as a result, the use of more than one valid receive control entry between two time mark entries should be avoided. note: if no receive control entry has been found valid for the current time window, the reception and storage of messages depen ds only on the message object receive acceptance filtering. only message ob jects receiving messages with a valid receive control entry modify their msc bit field accordingly. the msc bit field of a receiving object is not modified wi thout a valid receive control entry. rcemsgnr [23:16] rw rce message number this bit field determines the number of the message object that is checked for correct reception of a message during the last transfer window. a received message is alwa ys stored in the message object that is determined by acceptance filtering. when reaching a new time mark, an rce can be used to check if a desired message has actually been received in the desired message object. chen 24 rw check enable only time windows with an active receive control entry with chen=1 will handle the update of the msc bit field in the message object indicated by rcemsgnr. if a frame has been received correctly and also stored in the indicated message object, then the reception is considered as correct; otherwise, it is an error. 0 b the msc bit field of the indicated message object is not updated. 1 b the msc bit field of the indicated message object is updated. ec [31:28] rw entry code the entry code ec = 0101 b defines this scheduler memory entry as a receive control entry. 0 [7:6], [15:14], [27:25] r reserved; read as 0; should be written with 0. bits are ?don?t care? for scheduler operation when ec = 0101 b . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-141 v1.1, 2011-03 multican, v3.0 reference message entry the reference message is defined as follows: rme reference message entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0110gm 0 rw rw rw rw rw r 1514131211109876543210 tmv rw field bits type description tmv [15:0] rw time mark value these bits determine the compare value for the next time mark. this value is used for the next compare action with the cycle time. if the can node is a time master, the reference message will be sent out when the time mark is reached (see also tmr.rto). gm 27 rw gap mode this bit determines how the scheduler of a time master proceeds if the ttcan node is ?in a gap?. 0 b the reference message will be sent according to this rme entry (without respecting a possible gap). 1 b if the ttcan node is ?in a gap?, this rme entry is discarded and the following entries are read. ec [31:28] rw entry code the entry code ec = 0110 b defines this scheduler memory entry as a reference message entry. 0 [26:16] r reserved; read as 0; should be written with 0. bits are ?don?t care? for scheduler operation when ec = 0110 b . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-142 v1.1, 2011-03 multican, v3.0 note: this entry is taken into account for a time master. in the ca se that more valid reference message entries ar e detected, the settings of the previously found reference message entries are overruled by a subsequent one. if the ttcan node is not configured as time master and the scheduler reads an rme, a configuration error is generated. while the system is in the synchronization st ate, an rme entry with gm = 1 is not taken into account. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-143 v1.1, 2011-03 multican, v3.0 basic cycle end entry the basic cycle end entry defines the time mark value that is used as a watch trigger time mark. in the case that the ttcan system is waiting for a reference message while the system is normally synchronized (not in a gap = not waiting for another event to synchronize). if the system is in a gap with gm set, the fo llowing entries can be read. the basic cycle end is defined as follows: bce basic cycle end entry 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0111gm 0 rw rw rw rw rw r 1514131211109876543210 tmv rw field bits type description tmv [15:0] rw time mark value this bit field determines the compare value for the next time mark that is used for the next compare action with the cycle time. tmv determines the watch trigger that is used to generate a watch trigger event wte when the cycle time reaches tmv. the value written into tmv must meet the condition that a minimum of one can frame length is in between the last time mark and the basic cycle end entry. for this calculation, the reference trigger offset tmr.rto for the reference message entry must also be taken into account. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-144 v1.1, 2011-03 multican, v3.0 note: the bce determines the end of the scheduler entries in the scheduler memory when the system is normally synchronized. when the time mark of this entry is reached, the ttcan node will automatically enter the configuration mode. it will continue with the first time mark when a reference message has been correctly transferred on the can bus. while the system is in the synchronization state, a bce entry with gm = 1 is not taken into account. 24.8.2.3 end of scheduler memory entry the end of scheduler memory entry eos is defined by entry codes ec = 0000 b or ec = 1xxx b (see table 24-14 ). an eos immediately stops the reading of entries in the scheduler memory and sets the ttcan node into configuration mode. eos can be regarded as a kind of emergency stop entry. it should not be used to control the scheduler itself but represents a security mechanism for the case that a scheduler entry does not show a valid ec bit field. gm 27 rw gap mode this bit determines how the scheduler proceeds when the ttcan node is ?in a gap? and waits for a trigger event to send the reference message (for the current time master) or when it waits for the reception of a reference message. 0 b the watch trigger event will be generated according to this bce entry (without respecting a possible gap). 1 b if the ttcan node is ?in a gap?, this basic cycle end entry is discarded and the following entries are read. ec [31:28] rw entry code the entry code ec = 0111 b defines this scheduler memory entry as a basic cycle end entry. 0 [26:16] r reserved; read as 0; should be written with 0. bits are ?don?t care? for scheduler operation when ec = 0111 b . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-145 v1.1, 2011-03 multican, v3.0 24.8.3 setup of the scheduler entries the entries in the scheduler memory can be set up only when all bits ncrx.cce of the ttcan nodes sharing the scheduler memory ar e set at the same time. write actions to the scheduler memory while not all corresponding bits ncrx.cce = 1 are not taken into account. the scheduler entries can always be read out for verification purposes. 24.8.4 reading the scheduler entries after a time mark has been reached, the scheduler instructions for the following time window are read by the scheduler. this ?colle cted? information can be read out from the scheduler timing status and from the scheduler instruction status register. the information becomes valid when the next time mark is reached. the information collected between time mark n-1 and time mark n becomes valid when the time mark n is reached. figure 24-33 collecting the instructions 24.8.4.1 instructions during a basic cycle the handling of entries collected between the time marks n-1 and n is defined as follows: ? time mark entry: the time mark value is defining the compare value for the time mark n. ? interrupt entry: valid interrupt information (inp+ 4 enable bits) can generate an interrupt when the time mark n is reached, depending on the flags recf and traf (they are mct05858 instructions for window n-1 instructions for window n-1 time window n-1 time window n frame reception frame transmisstion transmit enable window t ime mark n-1 time mark n time mar k n+1 collect instructions collect instructions arbitration arbitration www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-146 v1.1, 2011-03 multican, v3.0 automatically cleared when the time mark is reached). as a result, this interrupt indicates that a (no) message has been sent /received in the time window between the time marks n-1 and n. ? receive control entry: valid receive control inform ation (chen, rcemsgnr) controls the storage of a message in the time window between the time marks n-1 and n. ? arbitration entry: valid arbitration information (arbm) determines the behavior of the time window starting with the time mark n. ? transmit control entry: valid transmit control in formation (tren, altmsg , tcemsgnr) defines a message to be transmitted after the time ma rk n. the transmission start is possible while the transmit enable window is active for an exclusive window or for a short (single) arbitration window or for the e nd of a merged arbitration window. for a merged (long) arbitration window, the transmission can start during the complete time window. ? reference message entry: not used in this time window ? basic cycle end entry: not used in this time window the tmv value collected after time mark n-1 will become the new compare value for the time mark n. the value of cyctmr.csm equals the time mark number of the last time mark reached (csm = n after time mark n has been re ached). the value of cyctmr.bcc is number of the current basic cycle. this information is needed to correctly set up the scheduler entries (bit fields cycle, mcycle) and the message objects (bit fields cycle, mcycle, column, mcolumn). 24.8.4.2 instructions at the end of a basic cycle the collection of instructions for the last time window of a basic cycle starts when the time mark before is reached and stops when the entry tme2 is found. handling of the entries collected duri ng the last time window of a basic cycle: ? time mark entry: after a valid bce has been read, the first time mark tme1 is read and its value is defining the compare value for the time mark 1 (first time mark after the reference message = start of a new basic cycle). ? interrupt entry: valid interrupt information (inp+ 4 enable bits) collected during the last time window of a basic cycle can generat e an interrupt when the time mark 1 is reached, depending on the flags recf and traf (they are automatically cleared when the time mark is reached). these flags do not apply to the reference message (the www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-147 v1.1, 2011-03 multican, v3.0 transfer of a reference message does not modify these flags). as a result, this interrupt indicates that a (no) message has been sent /received in the last time window of the basic cycle. the ice for the last time window of a basic cycle must be written into the scheduler memory after the entry tme1. ? receive control entry: valid receive control inform ation (chen, rcemsgnr) collected during the last time window of a basic cycle contro ls the storage of a message in the last time window (not applicable to reference message). the rce for the last time window of a basic cycle must be written into the scheduler memory after the entry tme1. ? arbitration entry: valid arbitration information (arbm) determines the behavior of the time window starting with the time mark 1. this entry must be written into the scheduler memory after the entry tme1. ? transmit control entry: valid transmit control in formation (tren, altmsg , tcemsgnr) defines a message to be transmitted after the time ma rk 1. the transmission start is possible while the transmit enable window is active for an exclusive window or for a short (single) arbitration window. for a merged (long) arbitration window, the transmission can start during the complete time window. this entry must be written into the scheduler memory after the entry tme1. ? reference message entry: the time mark value of a valid rme is defining the compare value for the reference time mark. when this reference time mark pl us the reference trigger offset is reached, a reference message will be sent out (de pending on the gap st ate of the system). this entry must be written into the scheduler memory before a valid entry bce. ? basic cycle end entry: the time mark value of a valid bce is defining the compare value for the watch trigger event. when this time value is reached, a watch trigger event can be generated (depending on the gap state of the system). a valid bce always finishes the scheduler entries for each ttcan node. before the reference message has been correctly transferred: the value of cyctmr.csm equals the time mark number of the last time mark reached (csm = n after time mark n has been re ached). the value of cyctmr.bcc is number of the current basic cycle. this information is needed to correctly set up the scheduler entries rce and ice (bit fields cycle, mcycle). after the reference message has been correctly transferred, but the time mark 1 has not yet been reached: the value of cyctmr.csm is 0. the valu e of cyctmr.bcc is number of the new basic cycle. this information is needed to correctly set up the scheduler entries arbe and tce (bit fields cycle, mcycle) and the message objects (bit fields cycle, mcycle, column, mcolumn). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-148 v1.1, 2011-03 multican, v3.0 as a result, the ice and the rce describing the reception / transmission of a message in the last time window of a basic cycle lead to actions (int errupts, etc.) when time mark 1 is reached. 24.8.5 scheduler in struction sequence 24.8.5.1 bcc and csm in order to set up the scheduler instructions correctly, the values of csm and bcc in register cyctmr must be respected carefully, especially for the last time window of a basic cycle. in order to set up the scheduler instructions correctly, the values of csm and bcc in register cyctmr must be respected carefully, especially for the last time window of a basic cycle. when leaving the configurat ion mode, bcc and csm are 0 and the scheduler starts with time mark 1. the values for bcc and csm in figure 24-34 represent the internal values that are updated after the correct transfer of a reference message. the message triggered by the last time reference mark in a basic cycle is the reference message (see rme description). in figure 24-34 , this corresponds to the message after the time window n. the reference time mark follows after the time window n and the reference messa ge starts a new basic cycle. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-149 v1.1, 2011-03 multican, v3.0 figure 24-34 bcc and csm in a matrix cycle the cycle time of each basic cycle starts with 0 (virtual value). the start of a new basic cycle can only be detected after the correct tran sfer of a reference message. as a result, the cycle time value can be considered as valid after the reference message has been correctly transferred. 24.8.5.2 general instru ction sequence rules the settings of already read scheduler instructions can be overwritten by following valid scheduler instructions. the following order of scheduler entry types must be respected to set up the scheduler correctly (starting with the first): ? tme then rce or ice or tce or arbe ? rme then bce (for time masters) ? bce (for slave devices) the scheduler entries must always be closed with a bce with gm = 0. for time masters, the following sequence can be set up to close the scheduler entries: ? rme (gm = 1) then bce (gm = 1) then rme (gm = 0) then bce (gm = 0) (the entries rme(gm = 0) and bce(gm = 0) are mandatory) if the system is in-a-gap, the first rme and bc e entries (both with gm = 1) are not taken into account. with these entries, the standard (not in-a-gap) timing values can be adjusted. a second rme (with gm = 0) can be set up to send an emergency reference message while the system is in-a-gap and the synchronizati on event takes too long. the mca05859_mod reference message message 11 message 1n reference message message 21 message 2n reference message message m1 message mn bcc = 0 csm = 0 bcc = m csm = n bcc = 0 csm = 1 bcc = 0 csm = n time mark 1 time mark 2 time mark n bcc = 0 csm = n bcc = 1 csm = 1 bcc = 1 csm = n bcc = m csm = 1 bcc = m csm = n eof configuration mode left reference window time window 1 time window n bcc = m csm = n bcc = 0 csm = 0 bcc = 1 csm = 0 bcc = m csm = 0 reference time mark n 0 cycle time www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-150 v1.1, 2011-03 multican, v3.0 scheduler entries are then closed again with a bce with gm = 0 (e.g. with a longer timing value as a time-out criteria for a missing synchronization event). 24.8.5.3 scheduler sequence example the values given for csm and bcc (both bit fields are located in register cyctmr) lead to valid scheduler entries rce, tce, ice and arbe (bit fields cycle, mcycle) and the transmit control of the message objects (bit fields cycle, mcycle, column, mcolumn). in the case that the programmed values for cycle, mcycle, etc. do not match the given values of csm and bcc, the respective entry is considered invalid and its information is not taken into account for the corresponding time window. the following example shows a scheduler inst ruction sequence for the basic cycle m with n time mark entries: ?tme1 ? rce, ice (csm = n, bcc = m-1 or csm = bcc = 0 when the configuration mode is left) ? tce, arbe (csm = 0, bcc = m) ?tme2 ? rce, ice (csm = 1, bcc = m) ? tce, arbe (csm = 1, bcc = m) ?tme3 ? rce, ice (csm = 2, bcc = m) ? tce, arbe (csm = 2, bcc = m) ? other time marks and instructions ?tmen ? rce, ice (csm = n-1, bcc = m) ? tce, arbe (csm = n-1, bcc = m) ? rme (gm = 1, only for time masters) ? bce (gm = 1, for time masters and slaves) ? rme (gm = 0, only for time masters) ? bce (gm = 0, for time masters and slaves) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-151 v1.1, 2011-03 multican, v3.0 24.9 ttcan operation 24.9.1 configuration after a reset operation, the ttcan extensio n must be configured. the configuration mode is entered automatically after reset or can be initiated through software by writing ttfmr.cfgmel = 01 b . the configuration mode can be left only by software by writing ttfmr.cfgmel = 10 b . the status flag ttsr.cfgm indicates whether or not the configuration mode is active. this flag is automatically set when the corresponding can node turns off its clock (disable request). in configuration mode of the ttcan node (can node 0 in TC1798), the following actions must be performed, as indicated, by software or hardware: for all nodes: ? the local time, the global time, and t he cycle time are set to 0 (hardware). ? transmission or reception of messages of ttcan node is not possible, because the results of the acceptance filtering are not enabled (hardware). ? an appropriate tur value must be written to bit field turr.turadj (software). this value is automatically transferred to turr.tur (hardware). ? the scheduler memory entries must be initialized (software). ? the ttcan control information (id of reference message, etc.) and the ttcan node itself must be set up completely and enabled for can message transfer (software). ? after the complete configuration (softw are), ttfmr.cfgmel must be set to 10 b (software). ? the local time starts after leaving the configuration mode (hardware). ? the synchronization phase is entered automatically when the configuration mode is left (hardware). this is indicated by bit field ttsr.syncs = 01 b (hardware). ? for time masters, the transmission of the reference messages is scheduled as in a gap while the ttcan node is in the ?synchronizing? state. the scheduler entries rme with gm = 1 are taken into account only while the ttcan node is in the ?in schedule? state. ? for time masters and for time slaves, the scheduler entries bce with gm = 1 are taken into account only while the ttcan node is in the ?in schedule? state. 24.9.2 configuration error during the scheduler actions, some conditions lead to a configuration error: ? at the end of a basic cycle, a merged arbitration window is still open. ? an rme entry is found for a slave device. ? no time mark is found du ring instruction collection. ? an rce, ice, tce or arbe has been found before tme1 (after start or at the end of a basic cycle). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-152 v1.1, 2011-03 multican, v3.0 ? another entry (except eos) than an rme or a bce has been found after the first rme. ? a reference message object is not valid when it is requested for transmission. 24.9.3 synchronization phase when starting a ttcan system (e.g. afte r reset), the entire system must be synchronized after completing the configuration phase. during the synchronization phase (indicated by bit field ttsr.syncs = 01 b ), the following actions must be taken (or are taken automatically): the init_watch_trigger is taken into account until the first message is correctly received or transmitted. an init_watch_trigger event is detected when the cycle time reaches the value of 2 16 -1. this event is indicated by iwte = 1 and it only leads to an interrupt. the watch trigger value given by the basic cycle end entry is taken into account only after the first correct transfer of a message. when a watch trigger event occurs after transferring a message correctly on the bus, the transmission and the reception of data frames or remote frames are disabled (the ttcan node is set to configuration mode). during the synchronization phase, the scheduler entries rme or bce with gm = 1 are not taken into account. 24.9.4 time masters 24.9.4.1 state of a time master a potential time master is a device that can transmit a reference message. a backup time master is a potential time master that has received a reference message that was not its own. the current time master is the device that has successfully sent its own reference message. there is only one current time master in a ttcan system. if the current time master receives a reference message that is not its own, then it becomes a backup time master. if a backup time master has successfully transmitted its own reference message, it becomes the new current time master. when a priority conflict between the ttcan nod e and the actual time master is detected, the value of rto is automatically modified (dec rement by 1). this means that the priority of the actual time master (given by bits id[2:0]) of the latest received reference message is lower than the programmed tmprio value. 24.9.4.2 strictly ti me-triggered behavior a strictly time-triggered behavior (gaps are not allowed) can be achieved if the scheduler entries rme and bce with gm = 0 are only used. in this case, the gap condition is ?ignored? for the transfer of a referenc e message. in order to avoid unintentional www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-153 v1.1, 2011-03 multican, v3.0 transfers of reference messages, the external trigger generation should be switched off in this case. 24.9.5 error handling the ttcan error handling distinguishes among four levels of error severity: ?s0: no error: normal functionality ?s1: warning: only notification of the application by an interrupt (errs1). source: scheduling error 1 (mscmax - mscmin > 2 or when msc of a receive object equal 7), tx_underflow ?s2: error: notification of the application by an interrupt (errs2). all transmissions are disabled (except for reference messages), ttcfgr.rto is set to 127. source: scheduling error 2 (msc of a transmit object reaches 7), tx_overflow impact: the transmit enable window will not be opened (for exclusive and for arbitration windows). ?s3: severe error: notification of the application by an interrupt (errs3). all can bus actions are stopped (no dominant values are transmitted on the bus). the configuration phase is entered automatically (cfgm is set). source: application watchdog, bus off, config error, watch trigger event impact: bit init of the can node will be se t (the can node stops actions on the bus). note: any change of the error state can generate an interrupt. 24.9.6 application watchdog the application watchdog provides the possibility of checking for the ttcan module if the main system is still running. the app lication watchdog counter counts in steps of 256 ntus. each time 256 ntus have elapsed, the value awdr.awdv is decremented by one. if the value 0 is reached after decrementing, an s3 error is signaled by bit awderr. the falling edge of bit ltr.lt.7 (transition from 1 to 0) indicates that the time of 256 ntus has elapsed and the application watch dog value is decremented. the application watchdog is serviced by the program by writing a new value to the bit field awdr.awde. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-154 v1.1, 2011-03 multican, v3.0 24.9.7 msc handling the msc bit field is updated only for those message objects that are indicated by the valid rce or tce entry while the corresponding bit msgval is set. the message number taken into account for an update is defined in the respective bit fields rcemsgnr or tcemsgnr. checking for the receive/transmit condition takes place when the end of the transmit enable window of the following time marks is reached. because the transmit enable window length is known after each time mark (even if no message shall be sent out), this point in time can be used for the receive and the transmit check. this feature makes it possible to have a positive check result even if the message in the preceding time window finishes during the transmit enable window. a transmission attempt is defined as failed if a message object valid for transmission could not be transferred on the can bus. a tr ansmit trigger being active without a valid message object being found is not considered as a transmission attempt. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-155 v1.1, 2011-03 multican, v3.0 24.9.8 ttcan interrupt control figure 24-35 and figure 24-36 show the configurations of the three ttcan interrupts. figure 24-35 new basic cycle and notification interrupt structure mca0586 0 nbcinp nbc new matrix cycle new basic cycle new basic cycle interrup t ttirr ttinpr 01 10 11 00 nmc nbcie 2 ttier state change ttsr wfe disc syncsc msrc errsc ttirr last reference message indicates next-is-gap ttirr last reference message indicates discontinuity notifie errscie msrcie syncscie ttier ttier notifinp ttinpr notification interrupt 2 2 2 1 1 state change state change errs msr syncs 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-156 v1.1, 2011-03 multican, v3.0 figure 24-36 error interrupt structure see also ?interrupt control? on page 24-211 for further processing of the ttcan interrupts. mca0586 1 t ransmit enable w indow error i nterrupt tenwer ttirr tenwerie t ransmit t rigger e rror i nterrupt ttof ttuf tterie overflow underflow w atch trigger e vent interrupt iwte wte wteie ttier ttirr ttier ttirr ttier a pplication w atchdog i nterrupt awderr ttirr awdie ttier s cheduler error i nterrupts: cfgerr serr2 ttirr e rror type 2 c onfiguration error e os entry read e rror type 1 serr1 eos seie ttier errinp ttinpr error interrupt t ur adjust error turerr ttirr 1 1 1 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-157 v1.1, 2011-03 multican, v3.0 24.10 ttcan registers all ttcan register names described in this section are referenced by the module name prefix ?can_? in other parts of the document. ttcan register overview figure 24-37 ttcan registers table 24-15 ttcan registers register short name register long name offset address description see ltr local time register 280 h page 24-162 synmr synchronization mark register 284 h page 24-163 refmr reference mark register 288 h page 24-164 lrefmr last reference mark register 28c h page 24-165 turr time unit ratio register 290 h page 24-160 cyctmr cycle time register 294 h page 24-166 lor local offset register 298 h page 24-167 gmr global mark register 29c h page 24-169 lgmr last global mark register 2a0 h page 24-170 awdr application watchdog register 2a4 h page 24-171 turr ltr synmr mca0586 2 ttcr ttcan timing registers ttcan control/ status/config. registers ttcfgr refmr lrefmr ttsr ttfmr ttirr ttier ttinpr stptr0 ttcan scheduler registers stsrl cyctmr lor gmr lgmr awdr stsrh sisr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-158 v1.1, 2011-03 multican, v3.0 ttcr time trigger control register 2c0 h page 24-172 ttcfgr time trigger configuration register 2c4 h page 24-176 ttsr time trigger status register 2c8 h page 24-178 ttfmr time trigger flag modification register 2cc h page 24-183 ttirr time trigger interrupt request register 2d0 h page 24-185 ttier time trigger interrupt enable register 2d4 h page 24-189 ttinpr time trigger interrupt node pointer register 2d8 h page 24-193 stsrl scheduler timing status register low 2f0 h page 24-196 stsrh scheduler timing status register high 2f4 h page 24-197 sisr scheduler instruction status register 2f8 h page 24-198 stptr0 scheduler start pointer node 0 register 3ffc h page 24-195 table 24-15 ttcan registers (cont?d) register short name register long name offset address description see www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-159 v1.1, 2011-03 multican, v3.0 figure 24-38 shows the ttcan register address map. figure 24-38 ttcan register address map mca05863_3fff.vsd time trigger control register time trigger config. register time trigger status register time trigger int. request reg. time trigger flag modif. reg. time trigger int. node ptr. reg. time trigger int. enable reg. local time register synch. mark register reference mark register time unit ratio register cycle time register global mark register local offset register application watchdog reg. last global mark register last reference mark register + 280 h + 284 h + 288 h + 28c h + 290 h + 294 h + 298 h + 29c h + 2a0 h + 2a4 h + 2c0 h + 2c4 h + 2c8 h + 2cc h + 2d0 h + 2d4 h + 2d8 h ttcan timing registers for node 0 +280 h ttcan control / status / config. registers for node 0 ttcan scheduler registers for node 0 ttcan scheduler memory sched. start ptr.reg.node 0 + 3ffc h sched. timing stat. reg. 1 sched. instruct. stat. reg. + 2f4 h + 2f8 h +2c0 h +2f0 h +3e00 h +3fff h sched. timing stat. reg. 0 + 2f0 h +2ff h ttcan registers www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-160 v1.1, 2011-03 multican, v3.0 24.10.1 ttcan timing registers turr time unit ratio register (290 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 tur 0 ltdiv lt cs val rh r rw rw rh 1514131211109876543210 turadj 0 adj en rwh r rwh field bits type description adjen 0rwh adjust enable this bit enables automatic calculation of a new turadj value when a new reference message has been received (not for the current time master). a time unit ratio adjust error interrupt will be generated and bit adjen will be automatically cleared when an overflow or an underflow of the automatically calculated value occurs. 0 b the automatic tur calculation is disabled. the new value for time unit ratio for turadj must be calculated and written by software. 1 b the automatic tur calculation is enabled. after receiving a reference message, a new value for turadj is calculated by hardware. the calculated value is checked for overflow or underflow. turadj [15:6] rwh time unit ratio adjust this bit field holds the time unit ratio value that will be used for the next basic cycl e. in the case of an automatic time unit ratio calculation with an underflow (overflow), turadj is written with all 0s (1s), adjen is cleared and a time unit ratio adjust error interrupt is generated. a hardware calculated turadj value can be overwritten by software. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-161 v1.1, 2011-03 multican, v3.0 val 16 rh valid this bit indicates that a new value of turadj is available. val becomes set when the hardware has finished its automatic calculation (with a correct result without overflow or underflow) or when the software writes to turadj. an automatic calculation does not take place while val = 1. val is cleared when the value of turadj is copied to tur. 0 b the value of turadj has not been updated and no automatic update of tur by the value of turadj takes place. 1 b the value of turadj has been updated by software or by hardware and it will be copied to tur at the st art of the next basic cycle. ltcs 17 rw local time clock source this bit determines the clock source for the local time generation (addition of tur to lt, ltfr) for ttcan level 2. 0 b a new local time value is generated with each time quantum t q of the corresponding can node (depending on the can bit timing). 1 b the local time generation is based on the can module clock f can (independent from the can bit timing). the update rate t upd is based on the divider factor given by the bit field ltdiv according to: t upd = 2 ltdiv / f can ltdiv [20:18] rw local time divider this bit field determines the divider factor for the local time generation (if f can is selected by ltcs = 1). the divider factor is given by 2 ltdiv . 000 b divider factor = 1 selected. 001 b divider factor = 2 selected. ... b ... 111 b divider factor = 128 selected. tur [31:22] rh tur this bit field contains the currently active time unit ratio value. 0 [5:1], 21 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-162 v1.1, 2011-03 multican, v3.0 ltr local time register (280 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lt rh 1514131211109876543210 ltfr 0 rh r field bits type description ltfr [15:6] rh local time fraction this bit field contains the fractional part of the ntu counter (ttcan level 2 only). in the case of an overflow after the addition of the tur value, the value of lt is incremented by one. lt [31:16] rh local time this bit field contains the integer part of the ntu counter. in ttcan level 1, it is incremented with each can bit time, in level 2 it is incremented each time the fractional part ltfr has an overflow. 0 [5:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-163 v1.1, 2011-03 multican, v3.0 note: if the can node is time master, the co ntents of register synmr are used as timing data transferred in the reference message. synmr synchronization mark register (284 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 synm rh 1514131211109876543210 synmfr 0 rh r field bits type description synmfr [15:9] rh synchronization mark fraction this bit field contains the fractional part of the synchronization mark. synmfr is the bit field ltr.ltfr captured with the frame synchronization pulse. synm [31:16] rh synchronization mark this bit field contains the integer part of the synchronization mark. synm is the bit field ltr.lt captured with the frame synchronization pulse. 0 [8:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-164 v1.1, 2011-03 multican, v3.0 refmr reference mark register (288 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 refm rh 1514131211109876543210 refmfr 0 rh r field bits type description refmfr [15:9] rh reference mark fraction this bit field contains the fractional part of the reference mark. refmfr is the bit field synmr.synmfr captured with the correct end of the reference message. refm [31:16] rh reference mark this bit field contains the integer part of the reference mark. refm is the bit field synmr.synm captured with the correct end of the reference message. 0 [8:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-165 v1.1, 2011-03 multican, v3.0 lrefmr last reference mark register (28c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lrefm rh 1514131211109876543210 lrefmfr 0 rh r field bits type description lrefmfr [15:9] rh last reference mark fraction this bit field contains the fractional part of the last reference mark. lrefmfr is the bit field refmr.refmfr captured with the correct end of the reference message. lrefm [31:16] rh last reference mark this bit field contains the integer part of the last reference mark. lrefm is the bit field refmr.refm captured with the correct end of the reference message. 0 [8:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-166 v1.1, 2011-03 multican, v3.0 note: with a reference message, the coun ting of the columns restarts at 0. cyctmr cycle time register (294 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 csm 0 bcc rrhrrh 1514131211109876543210 cyctm rh field bits type description cyctm [15:0] rh cycle time the cycle time indicates the time already elapsed in the current basic cycle. it is calculated by ltr.lt - refmr.refm. in the case of a negative result (overflow of ltr.lt), the result is corrected. bcc [21:16] rh basic cycle count this bit field indicates the number of the current basic cycle. it is incremented after each correctly transferred reference message. csm [29:24] rh column of system matrix this bit field indicates the number of the current column of the system matrix . it is incremented when the current cycle time becomes equal to the stored time mark (indicating the start of the next column). 0 [23:22], [31:30] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-167 v1.1, 2011-03 multican, v3.0 lor local offset register (298 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lof rwh 1514131211109876543210 loffr 0 disc new disc rwh r rh rh field bits type description newdisc 0rh new discontinuity bit this bit indicates that the register lor has been the target of a write access for a time master (and that the contents of lof or loffr could have been changed). this bit indicates that the next reference message will be sent with a discontinuity in the reference mark. it is set automatically when a write action to lor is detected. it is cleared when the local time is captured (at sof) for the transmission of the reference message. 0 b a write access to lor has not occurred. 1 b a write access to lor has occurred. disc 1rh discontinuity bit this bit contains the disc bit of the reference message that is sent out (taken into account for a time master). this bit is set if the newdisc bit is 1 when the global time is captured (at sof) for the transmission of the reference message. it is cleared when the reference message has been transferred correctly. 0 b the disc bit in the reference message of the current time master is 0. 1 b the disc bit in the reference message of the current time master is 1. loffr [15:9] rwh local offset fraction this bit field contains the fractional part of the local offset. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-168 v1.1, 2011-03 multican, v3.0 note: register lor can be written by software only if the can node is the current time master or in configuration mode; otherwis e, the write action is not taken into account. because the written local offs et is only taken into account for the transmission of the reference message , bit disc is set automatically. lof [31:16] rwh local offset this bit field contains the integer part of the local offset. time master (transmitting reference messages): the sum of the local offset and the local time is stored as global time in the register gmr. not time master (receiv ing reference messages): the local offset is the received global time information minus the local reference mark (in refmr). 0 [8:2] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-169 v1.1, 2011-03 multican, v3.0 gmr global mark register (29c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gm rh 1514131211109876543210 gmfr 0 rh r field bits type description gmfr [15:9] rh global mark fraction this bit field contains the fractional part of the global mark. gm [31:16] rh global mark this bit field contains the integer part of the global mark. time master (transmitting reference messages): the sum of the local offset and the local time is stored as global time (global_sync_mark) in register gmr at the beginning of the reference message. not time master (receiv ing reference messages): the global time information in gmr is received as global_ref_mark by reference message. 0 [8:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-170 v1.1, 2011-03 multican, v3.0 note: the difference between the actual gl obal mark and the last one can be used to determine the value required for the t urr.tur update (not for the actual time master). lgmr last global mark register (2a0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lgm rh 1514131211109876543210 lgmfr 0 rh r field bits type description lgmfr [15:9] rh last global mark fraction this bit field contains the value of gmfr of the last reference mark. lgm [31:16] rh last global mark this bit field contains the value of gm of the last reference mark. 0 [8:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-171 v1.1, 2011-03 multican, v3.0 the application watchdog event occurs when the value of awdv is decremented and reaches zero. when writing 0 to awdv by software, the application watchdog is switched off without generating an application watchdog event. awdr application watchdog register (2a4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0awdv rrwh field bits type description awdv [7:0] rwh application watchdog value this bit field contains the current value of the application watchdog. the falling edge of bit ltr.lt[7] (1-to-0 transition) indicates that the time of 256 ntus has elapsed and the application watchdog value is automatically decremented by 1. if the value 0 is reached after decrementing, an s3 error is signaled by bit ttirr. awderr. awdv is not decremented below 0. the application watchdog is serviced by the program by writing a new value to the bit field awdv. in the case of a collision between the write by software and the automatic decrement, the write is taken into account. due to the fact that the counter counting the ntu (register ltr) is not reset when the application watchdog is serviced, the total time between the write to awdv and the signaling of an s3 error has an uncertainty of one step of awdv. 0 [31:8] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-172 v1.1, 2011-03 multican, v3.0 24.10.2 ttcan control / status / configuration registers ttcr time trigger control register (2c0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rmdlc tenw 0 cycle rw rw r rw 1514131211109876543210 0tmprio 0 tt lvl etm etssel etesel ttm r rw r rw rw rw rw rw field bits type description ttm [1:0] rw time trigger mode this bit determines the behavior of the ttcan node concerning the time trigger and the time master functionality. 00 b can node is disabled for ttcan operation and operates in event triggered mode (other settings for ttcan are inactive). the reference message object operates for reception or transmission as any other message object. 01 b can node is enabled for ttcan operation as a receiving device. reference messages cannot be transmitted by the can node. 10 b can node is enabled for ttcan operation as the actual or a potential time master. the can node is able to transmit the reference message. 11 b reserved; do not use this combination. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-173 v1.1, 2011-03 multican, v3.0 etesel [3:2] rw external trigger event selection this bit field determines the source of the external trigger event that can be used to trigger a transmission of the reference message. the transmission of the reference message will be triggered only when the external event is detected and the external trigger request bit ttsr.etr is set (= 1). 00 b reserved; external trigger does not trigger the transmission of the reference message. 01 b a negative edge at an external trigger input ecttx (as selected by etssel) triggers the transmission of the reference message. 10 b a positive edge at an external trigger input ecttx (as selected by etssel) triggers the transmission of the reference message. 11 b a negative or positive edge at an external trigger input ecttx (as selected by etssel) triggers the transmission of the reference message. etssel [6:4] rw external trigger source selection this bit fields selects the input source for the external reference message trigger. 000 b no external trigger possible. 001 b external trigger input line ectt1 selected. 010 b external trigger input line ectt2 selected. 010 b external trigger input line ectt3 selected. 100 b external trigger input line ectt4 selected. 101 b external trigger input line ectt5 selected. 110 b external trigger input line ectt6 selected. 111 b external trigger input line ectt7 selected. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-174 v1.1, 2011-03 multican, v3.0 etm 7rw external trigger mode this bit determines the external trigger mode. the transfer of a reference message is started if the selected trigger condition is met when the bus is idle after the end of the transmit enable window of the last time window of a basic cycle. the trigger event is stored in etrev. 0 b the trigger event itself is taken into account if it occurs after the end of the transmit enable window of the last time window of a basic cycle. 1 b the trigger event stor ed in etrev is taken into account after the end of the transmit enable window of the last time window of a basic cycle. ttlvl 8rw time trigger level this bit determines the level of the ttcan functionality. 0 b ttcan level 1 is selected. 1 b ttcan level 2 is selected. tmprio [14:12] rw time master priority this bit field determines the priority of the potential time master. this valu e will be used for the transmission of the id bits [2:0] of the reference message. in the case that the ttcan node looses arbitration against another reference mark on the bus or receives a reference mark while its own reference trigger is set, the reference trigger is reset and the received id is stored in the reference message object?s id bit field. cycle [21:16] rw basic cycle number this bit field determines the number of the last basic cycle in the matrix cycle. for time masters, the value of cycle is compared to the current value of the bit field cyctmr.bcc. if the comparison detects a match, the reference message is sent out with a new basic cycle count of 0. for slave devices, the value is used to detect the expected end of a matrix cycle. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-175 v1.1, 2011-03 multican, v3.0 tenw [27:24] rw transmit enable window this bit field determines how many can bit times can elapse before a pending transmit trigger is discarded. 0000 b one can bit time can elapse. 0001 b two can bit times can elapse. ... b ... 1110 b fifteen can bit times can elapse. 1111 b sixteen can bit times can elapse. rmdlc [31:28] rw reference message dlc this bit field determines the data length code dlc of reference messages sent out by this can node if it is a time master. the dlc bit field in the reference message object contains the dlc of the previously received reference message. note that rmdlc must be programmed only to values from 1 to 8 for ttcan level 1 and to values from 4 to 8 for ttcan level 2. other values must not be programmed. 0 [11:9], 15, [23:22] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-176 v1.1, 2011-03 multican, v3.0 ttcfgr time trigger configuration register (2c4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ttcnt rto rh rh 1514131211109876543210 exptt 0 iro rw r rw field bits type description iro [6:0] rw initial reference offset this bit field determines the initial reference trigger offset. the value is considered as 2?s complement and can reach values between 0 and 127. exptt [15:8] rw expected transmit triggers this bit field determines how many transmit requests are expected in a matrix cycle. rto [23:16] rh reference trigger offset this bit field indicates the actual reference trigger offset. this value is considered as 2?s complement and can reach values between -127 and 127. it is added to the time mark (given by the basic cycle end entry in the scheduler memory) for the trigger of the reference message. the modification and the corresponding conditions are listed in table 24-16 . ttcnt [31:24] rh transmit trigger counter the transmit trigger counter is incremented by 1 each time a transmit trigger is requested for a ttcan node. when reaching the value of exptt, it is no longer incremented and further transmit requests are not serviced (messages are not transferred). it is reset at the beginnin g of each new matrix cycle (after correct transfer on the reference message of basic cycle 0). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-177 v1.1, 2011-03 multican, v3.0 0 7r reserved read as 0; should be written with 0. table 24-16 modification by hardware of bit field rto modification condition set to ttcfgr.iro during reset (ttcfgr.iro = 0) and configuration mode (write of ttcfgr.iro by software) set to ttcfgr.iro each time a potential time master receives a reference message with a higher priority than its own decrement by 1 each time a potential time master receives a reference message with a lower priority than its own until -127 is reached set to 127 when the s2 state is entered set to 0 when the ttcan node has correctly transmitted its reference message (it is the current time master) or when a potential master receives a reference message with a priority lower than its own and its rto is positive field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-178 v1.1, 2011-03 multican, v3.0 the time trigger status register ttsr contai ns the time trigger status information that does not lead directly to interrupt events. ttsr time trigger status register (2c8 h ) reset value: 0000 1000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 etr ev etr nig 0 mscmax 0 mscmin r rhrhrh r rh r rh 1514131211109876543210 rec f tra f tm pc cfg m arb ref trg eff efi 0 syncs msr errs rh rh rh rh rh rh rh rh r rh rh rh field bits type description errs [1:0] rh error state this bit field indicates the current error severity level. 00 b no error 01 b warning 10 b error 11 b severe error msr [3:2] rh master-slave relation this bit field indicates the current master to slave relation of the ttcan node. 00 b master off 01 b slave (receiving device) 10 b potential time master 11 b current time master syncs [5:4] rh synchronization state this bit field indicates the current synchronization state of the ttcan node. 00 b sync off 01 b synchronizing 10 b in gap 11 b in schedule www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-179 v1.1, 2011-03 multican, v3.0 efi 8rh error frame indication this bit is set when an error condition in the bitstream of a can frame is detected and an error frame will be sent out. it is automatically cleared when the next time mark is reached and its status at this moment is monitored by bit eff. 0 b since the last time mark, the can node has detected no error condition in the can bitstream. 1 b since the last time mark, the can node has detected an error condition in the can bitstream. when efi becomes set, a lec interrupt can be generated by the can node. eff 9rh error frame flag this bit monitors the error frame indication efi when a time mark is reached. 0 b no can error has been detected in the last time window. 1 b a can error has been detected in the last time window. reftrg 10 rh reference trigger flag this bit is set when the reference message of a ttcan node is intended to be sent. it is cleared when the reference message has been sent out correctly or a reference message has been received correctly (sent by another time master). arb 11 rh arbitration window flag this bit is set when an arbitration window is opened. it is cleared when the arbitration window is closed. 0 b the current time window is a time-triggered window. 1 b the current time window is an arbitration window. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-180 v1.1, 2011-03 multican, v3.0 cfgm 12 rh configuration mode flag this bit indicates whether or not configuration mode is active. 0 b the ttcan node is not in configuration mode. 1 b the ttcan node is in configuration mode. it will not transmit messages and it will not update the msc bit fields. tmpc 13 rh time master priority conflict this bit indicates if there is a priority conflict between the current time master and this ttcan node. a priority conflict occurs if the current time master has a lower priority than the ttcan node itself (potential time master). 0 b a priority conflict has not been detected for the last reference message. 1 b the ttcan node is a potential time master with a priority conflict (the last reference message has been received with a lower priority than ttcr.tmprio). traf 14 rh transmission finished flag this bit is set when the can node correctly finishes a transmission of a message that is not the reference message. it is reset when the next time mark is reached. this flag is used for the interrupt generation of the time mark entries and the interrupt entries. 0 b since the last time mark has been reached, the can node has not yet correctly finished a transmission. 1 b since the last time mark has been reached, the can node has correctly finished a transmission (it is not set by the transmission of a reference message). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-181 v1.1, 2011-03 multican, v3.0 recf 15 rh reception finished flag tthis bit is set when the can node correctly finishes a reception of a message (= a correct message has been seen on the bus) that is not the reference message. it is reset when the next time mark is reached. this flag is used for the interrupt generation of the time mark entries and the interrupt entries. 0 b since the last time mark has been reached, the can node has not yet received a message. 1 b since the last time mark has been reached, the can node has received a message (it is not set by the reference message). mscmin [18:16] rh minimum of msc bit fields this bit field indicates the minimum value of the msc bit fields of the message objects activated in exclusive time windows. this value is set to 7 at the beginning of a new matrix cycle. it is updated according to: note: if msc_cur < mscmin then mscmin:= msc_cur the value msc_cur is the msc value of the currently activated message object. mscmax [22:20] rh maximum of msc bit fields this bit field indicates the maximum value of the msc bit fields of the message objects activated in exclusive time windows. this value is set to 0 at the beginning of a new matrix cycle. it is updated according to: note: if msc_cur > mscmax then mscmax:= msc_cur the value msc_cur is the msc value of the currently activated message object. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-182 v1.1, 2011-03 multican, v3.0 nig 24 rh next is gap this bit indicates the condition leading to the transmission of the reference message coming after the next one (only for the current time master). this bit will be transmitted with the next reference message. 0 b the reference message after the next one will be transmitted when the corresponding time mark is reached. 1 b the reference message after the next one will be transmitted when the selected trigger event occurs. bit nig will be cleared and bit etr will be set when the next reference message is correctly transferred (received or transmitted). etr 25 rh external trigger request this bit indicates the condition leading to the transmission of the next reference message (only for the current time master).the value of nig is copied to etr when a reference message is correctly transmitted. it will be cleared automatically when the next reference message is correctly received. 0 b the next referenc e message will be transmitted when the corresponding time mark is reached. 1 b the next referenc e message will be transmitted when the selected trigger or the rme trigger event occurs. etrev 26 rh external trigger event this bit indicates that the external trigger event has been detected. it is automatically cleared when a reference message has been transferred correctly on the bus. 0 b the selected external trigger event has not yet been detected. 1 b the selected external trigger event has been detected. 0 [7:6], 19, 23, [31:27] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-183 v1.1, 2011-03 multican, v3.0 ttcan status bits/flags can be modified when executing a write operation to the time trigger flag modification register ttfmr. ttfmr time trigger flag modification register (2cc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 etr evr ste nigsr cfgmel rwwww field bits type description cfgmel [1:0] w configuration mode enter/leave this bit field is used to enter/leave the configuration mode. 00 b no action 01 b the configuration mode will be entered (set ttsr.cfgm). 10 b the configuration mode will be left (clear ttsr.cfgm). 11 b no action nigsr [3:2] w next is gap flag set/reset this bit field can set/clear the bit ttsr.nig and can clear the bit ttsr.etr. 00 b no action 01 b bit ttsr.nig will be set. 10 b bits ttsr.nig and ttsr.etr will be cleared. 11 b no action www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-184 v1.1, 2011-03 multican, v3.0 ste 4w software trigger event this bit can be used to synchronize a ttcan node by software. 0 b no action 1 b the transmission of a reference message is triggered if ttcr.etesel = 11 and the system is in-a-gap. etrevr 5w reset external trigger event this bit clears the external trigger event flag. 0 b no action. 1 b the bit ttsr.etrev is cleared. 0 [31:6] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-185 v1.1, 2011-03 multican, v3.0 the time trigger interrupt request register ttirr contains the time trigger status information related to interrupt events. note that all bits in ttirr can be cleared by software by writing 0 to it. writing a 1 to the bits has no effect. ttirr time trigger interrupt request register (2d0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 tur err cfg err rrwhrwh 1514131211109876543210 ser r2 ser r1 disc wfe eos syn csc msr c err sc awd err i wte wte tt of tt uf ten wer nbc nmc rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description nmc 0rwh new matrix cycle this bit indicates that a new matrix cycle has started. it is set when a reference message with the cycle count = 0 has been transferred correctly. 0 b a new matrix cycle has not yet been detected. 1 b a new matrix cycle has been detected. nbc 1rwh new basic cycle this bit indicates that a new basic cycle has started. 0 b a new basic cycle has not yet been detected. 1 b a new basic cycle has been detected. tenwer 2rwh transmit enable window error this bit indicates that the specified time elapsed after the transmit trigger withou t starting the transmission of a message. 0 b the triggered messages have been sent out before the transmit enable window elapsed. 1 b a triggered message was not started before the transmit enable window elapsed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-186 v1.1, 2011-03 multican, v3.0 ttuf 3rwh transmit trigger underflow this bit indicates that fewer transmit triggers have been requested during a matrix cycle than specified in ttcfgr.exptt. 0 b the expected number or more transmit triggers have been requested. 1 b less transmit triggers have been requested. ttof 4rwh transmit trigger overflow this bit indicates that more transmit triggers have been requested during a matrix cycle than specified in ttcfgr.exptt. 0 b the expected number or less transmit triggers have been requested. 1 b more transmit triggers have been requested. wte 5rwh watch trigger event 1) this bit indicates a watch trigger event wte. this event is detected when the cycle time in cyctmr.cyctm becomes equal to the watch trigger value given by the time mark of the bce entry. 0 b the cycle time has not been equal to wtv. 1 b the cycle time has been equal to wtv. iwte 6rwh init watch trigger event 2) this bit indicates a watch trigger event wte with the value of the init_watch_trigger. this event is detected when the cycle time in cyctmr.cyctm becomes equal to the init watch trigger value of 2 16 - 1. 0 b the cycle time has not been equal to 2 16 - 1. 1 b the cycle time has been equal to 2 16 - 1. awderr 7rwh application watchdog error this bit indicates that the application watchdog has been decremented to 0 without being serviced. 0 b awdr.awdv has not yet reached 00 h . 1 b awdr.awdv has reached 00 h . this is an s3 error condition. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-187 v1.1, 2011-03 multican, v3.0 errsc 8rwh error state change this bit indicates that the bit field ttsr.errs has changed. 0 b ttsr.errs has not changed. 1 b ttsr.errs has changed. msrc 9rwh master-slave relation change this bit indicates that the bit field msr has changed. 0 b ttsr.msr has not changed. 1 b ttsr.msr has changed. syncsc 10 rwh synchronization state change this bit indicates that the bit field ttsr.syncs has changed. 0 b ttsr.syncs has not changed. 1 b ttsr.syncs has changed. eos 11 rwh end of scheduler entry flag this bit is set when the ttcan scheduler reads an eos entry. in this case, bit ttsr.cfgm is automatically set. 0 b the ttcan scheduler has not yet read an eos entry. 1 b the ttcan scheduler has read an eos entry. wfe 12 rwh wait for event flag this bit is set when a reference message is received indicating a next-is-gap (not for the current time master). this event can generate a notification interrupt. 0 b the last reference message received was not indicating next-is-gap. 1 b the last reference message received was indicating next-is-gap. disc 13 rwh discontinuity flag this bit is set when a reference message is received indicating a discontinuity (not for the current time master). this event can generate a notification interrupt. 0 b the last reference message received was not indicating a discontinuity. 1 b the last reference message received was indicating a discontinuity. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-188 v1.1, 2011-03 multican, v3.0 serr1 14 rwh scheduler error 1 flag this bit is set when a scheduler error type 1 is detected. the scheduler error can change the ttcan error state and, as a result, can be indicated by an error state change interrupt. 0 b a scheduler error type 1 has not been detected. 1 b a scheduler error type 1 has been detected. serr2 15 rwh scheduler error 2 flag this bit is set when a scheduler error type 2 is detected. the scheduler error can change the ttcan error state and, as a result, can be indicated by an error state change interrupt. 0 b a scheduler error type 2 has not been detected. 1 b a scheduler error type 2 has been detected. cfgerr 16 rwh configuration error this bit indicates that a configuration error has been detected by the scheduler. a configuration error is detected when an arbitration window is not closed when the bce is reached. when rme.tmv is reached, no other scheduler entries as rme and bce are allowed. see also eoserr. 0 b a configuration error has not been detected. 1 b a configuration error has been detected (s3 error condition). turerr 17 rwh tur adjust error this bit indicates that a tur adjust error has been detected. a tur adjust error is detected when the automatic tur adjustment is enabled and an overflow or an underflow of the calculated turadj value occurs. 0 b a tur adjust error has not been detected. 1 b a tur adjust error has been detected. 0 [31:18] r reserved read as 0; should be written with 0. 1) the wte can be generated only after the fi rst message has been transferred on the bus. 2) the iwte can be generated only until the first message has been transferred on the bus. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-189 v1.1, 2011-03 multican, v3.0 ttier time trigger interrupt enable register (2d4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 not if ie se ie syn csc ie msr c ie err sc ie awd ie wte ie 0 tt er ie ten wer ie nbc ie r rwrwrwrwrwrwrw r rwrw rw field bits type description nbcie [1:0] rw new basic cycle interrupt enable nbcie enables the new basic or matrix cycle interrupt. this interrupt is generated when either bit ttirr.nbc or bit ttirr.nmc become set (independent of its current state). 00 b a new basic or matrix cycle interrupt is disabled. 01 b a basic cycle interrupt is generated whenever ttirr.nbc becomes set. 10 b a matrix cycle interrupt is generated whenever ttirr.nmc becomes set. 11 b reserved bit field ttinpr.nbcinp selects the interrupt output line that becomes activated at this type of interrupt. tenwerie 2rw transmit enable window error interrupt enable tenwerie enables the transmit enable window error interrupt. this interrupt is generated when bit ttirr.tenwer is set. 0 b transmit enable window error interrupt is disabled. 1 b transmit enable window error interrupt is enabled. bit field ttinpr.errinp selects the interrupt output line that becomes activated at this type of interrupt. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-190 v1.1, 2011-03 multican, v3.0 tterie 3rw transmit trigger error interrupt enable tterie enables the transmit trigger error interrupt. this interrupt is generated when ttirr.ttof or ttirr.ttuf become set (independent of its current state). 0 b transmit trigger error in terrupt is disabled. 1 b transmit trigger error interrupt is enabled. bit field ttinpr.errinp selects the interrupt output line that becomes activated at this type of interrupt. wteie 6rw watch trigger even t interrupt enable wteie enables the watch trigger event interrupt. this interrupt is generated when ttirr.iwte or ttirr.wte become set (independent of its current state). 0 b watch trigger event interrupt is disabled. 1 b watch trigger event interrupt is enabled. bit field ttinpr.errinp selects the interrupt output line that becomes activated at this type of interrupt. awdie 7rw application watchdog interrupt enable awdie enables the application watchdog interrupt. this interrupt is generated when ttirr.awderr becomes set (independent of its current state). 0 b application watchdog interrupt is disabled. 1 b application watchdog interrupt is enabled. bit field ttinpr.errinp selects the interrupt output line that becomes activated at this type of interrupt. errscie 8rw error state change interrupt enable errscie enables the error state change interrupt. this interrupt is generated when bit field ttsr.errsc changes its state. 0 b error state change interrupt is disabled. 1 b error state change interrupt is enabled. bit field ttinpr.notifinp selects the interrupt output line that becomes activated at this type of interrupt. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-191 v1.1, 2011-03 multican, v3.0 msrcie 9rw master slave relation change interrupt enable msrscie enables the master slave relation change interrupt. this interrupt is generated when bit field ttsr.msrc changes its state. 0 b master slave relation change interrupt is disabled. 1 b master slave relation change interrupt is enabled. bit field ttinpr.notifinp selects the interrupt output line that becomes activated at this type of interrupt. syncscie 10 rw synchronization state change interrupt enable syncscie enables the synchronization state change interrupt. this interrupt is generated when bit field ttsr.syncsc changes its state. 0 b synchronization state change interrupt is disabled. 1 b synchronization state change interrupt is enabled. bit field ttinpr.notifinp selects the interrupt output line that becomes activated at this type of interrupt. seie 11 rw scheduler error interrupt enable seie enables the scheduler error interrupt. this interrupt is generated whenever bits eos or serr1 or serr2 or cfgerr of r egister ttsr are set by hardware. 0 b scheduler error interrupt generation is disabled. 1 b scheduler error interrupt generation is enabled. bit field ttinpr.errinp selects the interrupt output line that becomes activated at this type of interrupt. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-192 v1.1, 2011-03 multican, v3.0 notifie 12 rw notification in terrupt enable notifie enables the notification interrupt. this interrupt is generated when ever bits ttirr.wfe or ttirr.disc are set by hardware. 0 b notification interrupt is disabled. 1 b notification interrupt is enabled. bit field ttinpr.notifinp selects the interrupt output line which becomes activated at this type of interrupt. 0 [5:4], [31:13] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-193 v1.1, 2011-03 multican, v3.0 ttinpr time trigger interrupt node pointer register (2d8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 notifinp nbcinp errinp r rwrwrw field bits type description errinp [3:0] rw error interrupt node pointer errinp selects the interrupt output line int_om (m = 0-15) for an error in terrupt. possible error events for this interrupt node pointer are: ? transmit enable window error event ? transmit trigger error event ? (initial) watch trigger event ? application watchdog event ? tur adjust error ? scheduler error event 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. nbcinp [7:4] rw new basic cycle interrupt node pointer nbcinp selects the interrupt output line int_om (m = 0-15) for a new basic or matrix cycle interrupt. 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-194 v1.1, 2011-03 multican, v3.0 notifinp [11:8] rw notification interrupt no de pointer notifinp selects the interrupt output line int_om (m = 0-15) for a notification interrupt. possible notification events for this interrupt node pointer are: ? bit field ttsr.errs changes ? bit field ttsr.msr changes ? bit field ttsr.syncs changes ? bit ttirr.wfe is set ? bit ttirr.disc is set 0000 b interrupt output line int_o0 is selected. 0001 b interrupt output line int_o1 is selected. ? b ? 1110 b interrupt output line int_o14 is selected. 1111 b interrupt output line int_o15 is selected. 0 [31:12] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-195 v1.1, 2011-03 multican, v3.0 24.10.3 scheduler registers stptr0 scheduler start poin ter node 0 register (3ffc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 stptr rrw field bits type description stptr [6:0] rh start pointer this bit field determines the location of the first scheduler entry for ttcan node 0. the value determines how many entries (counted in units of 32 bits) the first tme entry (tme1) for this ttcan node is located below the last address of the scheduler memory. if two or more ttcan nodes are implemented, all start pointers refer to the end (last address) of the scheduler memory. 0 [31:7] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-196 v1.1, 2011-03 multican, v3.0 the tmv bit fields in the scheduler timing status registers monitor the time mark information for the start of the next time window after the instruction collection phase of the scheduler (collected from the tme, rme or bce entries). stsrl scheduler timing status register low (2f0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bcetmv rh 1514131211109876543210 rmetmv rh field bits type description rmetmv [15:0] rh time mark value from rme this bit field indicates the compare value for the next time mark defined by an rme. this value is valid only if sisr.icf = 1 and sisr.rmev = 1. bcetmv [31:16] rh time mark value from bce this bit field indicates the compare value for the next time mark defined by an bce. this value is valid only if sisr.icf = 1 and sisr.bcev = 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-197 v1.1, 2011-03 multican, v3.0 stsrh scheduler timing status register high (2f4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 tcemsgnr rcemsgnr rh rh 1514131211109876543210 tmetmv rh field bits type description tmetmv [15:0] rh time mark value from tme this bit field indicates the compare value for the next time mark defined by an tme. this value is valid only if sisr.icf = 1 and sisr.tmev = 1. rcemsgnr [23:16] rh receive control entry message number this bit field indicates the collected rcemsgnr information from an rce. this value is taken into account only if sisr.icf = 1 and sisr.rcev = 1. tcemsgnr [31:24] rh transmit control entry message number this bit field indicates the collected tcemsgnr information from an tce. this value is taken into account only if sisr.icf = 1 and sisr.tcev = 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-198 v1.1, 2011-03 multican, v3.0 the bits in the scheduler instruction status register monitor the information during and after the instruction collection phase of the scheduler. these values will become valid when the next time mark is reached. sisr scheduler instruction status register (2f8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 bce v rme v tme v arb v ice v tce v rce v r rhrhrhrhrhrhrh 1514131211109876543210 icf gm arbm altmsg tr en ch en ien rec f1 ien rec f0 ien tra f1 ien tra f0 inp rh rh rh rh rh rh rh rh rh rh rh field bits type description inp [3:0] rh interrupt node pointer this bit field indicates the collected inp information. this value is taken into account only when at least one of the four interrupt requests is enabled. ientraf0 4rh interrupt enable if traf = 0 this bit field indicates the collected ientraf0 information. ientraf1 5rh interrupt enable if traf = 1 this bit field indicates the collected ientraf1 information. ienrecf0 6rh interrupt enable if recf = 0 this bit field indicates the collected ienrecf0 information. ienrecf1 7rh interrupt enable if recf = 1 this bit field indicates the collected ienrecf1 information. chen 8rh check enable this bit field indicates the collected chen information from an rce. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-199 v1.1, 2011-03 multican, v3.0 tren 9rh transmit enable this bit field indicates the collected tren information from an tce. altmsg [11:10] rh alternative message this bit field indicates the collected altmsg information from an tce. arbm [13:12] rh arbitration mode this bit field indicates the collected arbm information from an tme or an arbe. gm 14 rh gap mode this bit field indicates the collected gm information from an rme or an bce (only valid if rme or a bce has been found). icf 15 rh instruction collection finished this bit field indicates that the instruction collection is finished for a time window. it is automatically cleared when a time mark is reached. it is set when the instruction collection is terminated. 0 b the instruction collection is not yet terminated. all other values in re gisters sisr, stsrl and stsr4 are invalid. 1 b the instruction collection is terminated. all other values in registers sisr, stsrl and stsrh are valid. rcev 16 rh receive control entry valid this bit indicates that a valid receive control information has been found during the instruction collection for this time window. it is automatically cleared when a time mark is reached. 0 b the bit fields chen and rcemsgnr are invalid. they are not taken into account for the next time window. 1 b the bit fields chen and rcemsgnr are valid. they are taken into account for the next time window. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-200 v1.1, 2011-03 multican, v3.0 tcev 17 rh transmit control entry valid this bit indicates that valid transmit control information has been found during the instruction collection for this time window. it is automatically cleared when a time mark is reached. 0 b the bit fields tren, altmsg and tcemsgnr are invalid. they are not taken into account for the next time window. 1 b the bit fields tren, altmsg and tcemsgnr are valid. they are taken into account for the next time window. icev 18 rh interrupt contro l entry valid this bit indicates that a valid interrupt control entry has been found during the instruction collection for this time window. it is automatically cleared when a time mark is reached. 0 b no valid ice has been found 1 b a valid ice has been found arbv 19 rh arbitration entry valid this bit indicates that a valid arbitration entry has been found during the instruction collection for this time window. it is automatically cleared when a time mark is reached. 0 b no valid arbe has been found 1 b a valid arbe has been found tmev 20 rh time mark entry valid this bit indicates that a valid time mark entry has been found during the instruction collection for this time window. it is automatically cleared when a time mark is reached. 0 b no valid tme has been found 1 b a valid tme has been found rmev 21 rh reference mark entry valid this bit indicates that a valid reference mark entry has been found during the instruction collection for this time window. it is automatically cleared when a time mark is reached. 0 b no valid rme has been found 1 b a valid rme has been found field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-201 v1.1, 2011-03 multican, v3.0 note: this register is reset at the st art of a new instruction collection phase. bcev 22 rh basic cycle end entry valid this bit indicates that a valid basic cycle end entry has been found during the instruction collection for this time window. it is automatically cleared when a time mark is reached. 0 b no valid bce has been found 1 b a valid bce has been found 0 [31:23] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-202 v1.1, 2011-03 multican, v3.0 24.11 multican module implementation this section describes can module interfaces with the clock control, port connections, interrupt control, and address decoding. 24.11.1 interf aces of the mu ltican module figure 24-39 shows the TC1798 specific implementation details and interconnections of the multican module. the four i/o lines of the multican module (two i/o lines of each can node) are connected to i/o lines of port 3. the multican module is also supplied by clock control, interrupt control, and address decoding logic. multican interrupts can be directed to the dma controller and the gpta modules. can interrupts are able to trigger dma transfers and gpta operations. figure 24-39 can with ttcan extensio n, implementation / interconnections multican module kernel mca06281b_4ttcan_128_mo.vsd interrupt control f can can control f clc clock control address decoder dma int_o [1:0] int_o [15:2] message object buffer 128 objects linked list control timing control and synchronization scheduler schedule memory time - triggered extension port 9 control p9.13 p9.14 / req15 a1 a1 ectt1 ectt2 gpta0 ectt3 scu eru ectt4 ectt5 int_o_15 port 3 control txdc0 rxdc0 txdc1 rxdc1 p6.11 / txdcan1 p6.10 / rxdcan1 can node 0 can node 1 a2 a2 a2 a2 p6.13 / txdcan2 p6.12 / rxdcan2 a2 a2 txdc2 rxdc2 can node 2 txdc3 rxdc3 can node 3 p6.15 / txdcan3 p6.14 / rxdcan3 a2 a2 p6.9 / txdcan0 p6.8 / rxdcan0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-203 v1.1, 2011-03 multican, v3.0 24.11.2 multican module external registers the registers listed in figure 24-40 are not included in the multican module kernel but must be programmed for proper operation of the multican module. figure 24-40 can implementation-speci fic special function registers can_clc mca05865 p6_iocr8 clock control registers port registers p6_iocr12 p6_pdr can_scrm interrupt registers can_fdr m = 0-15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-204 v1.1, 2011-03 multican, v3.0 24.11.3 module clock generation as shown in figure 24-41 , the clock signals for the multican module are generated and controlled by a clock control unit. this clock generation unit is responsible for the enable/disable control, the clock frequency adjustment, and the debug clock control. this unit includes two registers: ? can_clc: generation of the module control clock f clc ? can_fdr: frequency control of the module timer clock f can figure 24-41 multican module clock generation the module control clock f clc is used inside the multican module for control purposes such as clocking of control logic and register operations. the frequency of f clc is identical to the system clock frequency f fpi . the clock control re gister can_clc makes it possible to enable/disable f clc under certain conditions. the module timer clock f can is used inside the multican module as input clock for all timing relevant operations (e.g. bit timing). the settings in the can_fdr register determine the frequency of the module timer clock f can according the following two formulas: (24.1) (24.2) equation (24.1) applies to normal divider mode (can_fdr.dm = 01 b ) of the fractional divider. equation (24.2) applies to fractional divider mode (can_fdr.dm = 10 b ). note: the can module is disabled after reset. in general, after reset, the module control clock f clc must be switched on (writing to register can_clc) before the frequency of the module timer clock f can is defined (writing to register can_fdr). mca06283 clock control register can_clc f clc multica n clock control f can fractional divider register can_fdr f fpi f can f fpi 1 n -- - with n = 1024 - can_fdr.step = f can f fpi n 1024 ------------ - with n = 0-1023 = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-205 v1.1, 2011-03 multican, v3.0 24.11.3.1 can clock control register the clock control registers makes it possible to control (enable/disable) the module control clock f clc . note: in disabled state, no registers of can module can be read or written except the can_clc register. the fractional divider register allows the programmer to control the clock rate of the module timer clock f can . can_clc can clock control register (000 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we e dis sp en dis s dis r r rwwrwrw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the module. diss 1r module disable status bit bit indicates the current status of the module. spen 2rw module suspend enable for ocds used to enable the suspend mode. edis 3rw sleep mode en able control used to control module?s sleep mode. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. fsoe 5rw fast switch off enable used to switch off fast clock in suspend mode. 0 [31:6] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-206 v1.1, 2011-03 multican, v3.0 can_fdr can fractional divider register (00c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dis clk en hw sus req sus ack 0result rwh rw rh rh r rh 1514131211109876543210 dm sc sm fdis step rw rw rw rw rw field bits type description step [9:0] rw step value reload or addition value for result. fdis 10 rw freeze disable this bit controls the freeze function for this module. 0 b module operates on co rrected clock, with reduced modulation jitter. 1 b module operates on uncorrected clock, with full modulation jitter. sm 11 rw suspend mode sm selects between granted or immediate suspend mode. sc [13:12] rw suspend control this bit field determines the behavior of the fractional divider in suspend mode. dm [15:14] rw divider mode this bit field selects normal divider mode, fractional divider mode, and off-state. result [25:16] rh result value bit field for the addition result. susack 28 rh suspend mode acknowledge indicates state of spndack signal. susreq 29 rh suspend mode request indicates state of spnd signal. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-207 v1.1, 2011-03 multican, v3.0 enhw 30 rw enable hardware clock control controls operation of ecen input and disclk bit. disclk 31 rwh disable clock hardware controlled disable for f out signal. 0 [27:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-208 v1.1, 2011-03 multican, v3.0 24.11.4 port and i/o line control the interconnections between the multican module and the port i/o lines are controlled in the port logic. additionally to the port input selection, the following port control operations must be executed: ? input/output function selection (iocr registers) ? pad driver characteristics select ion for the outputs (pdr registers) 24.11.4.1 input/output function selection in ports the port input/output control registers contain the bit fields that select the digital output and input driver characteristics such as pull-up/down devices, port direction (input/output), open-drain, and alternate output selections. the i/o lines for the multican module are controlled by the port input/output control registers p6_iocr8 and p6_iocr12. table 24-17 shows how bits and bit fields must be programmed for the required i/o functionality of the can i/o lines. 24.11.4.2 node receiv e input selection additionally to the i/o control selection, as defined in table 24-17 , the selection of a can node?s receive input line requires that bit field rxsel in its node port control register npcrx must be set according to table 24-18 . values for npcrx.rxsel other than those of table 24-18 result in a recessive receive input for node x. this feature allows, for example, a can node which operates in analyzer mode to monitor the receive operations of its neighbor can node. the default setting after reset of a node?s npcrx.rxsel bit field connect node x with rxdcanx i/o line (x = 0-2). table 24-17 multican i/o control selection and setup module port lines input/output control register bits i/o can p6.8 / rxdcan0 p6_iocr8.pc8 = 0xxx b input p6.9 / txdcan0 p6_iocr8.pc9 = 1x01 b output p6.10 / rxdcan1 p6_iocr8.pc10 = 0xxx b input p6.11 / txdcan1 p6_iocr8.pc11 = 1x01 b output p6.12 / rxdcan2 p6_iocr12.pc12 = 0xxx b input p6.13 / txdcan2 p6_iocr12.pc13 = 1x01 b output p6.14 / rxdcan3 p6_iocr12.pc14 = 0xxx b input p6.15 / txdcan3 p6_iocr12.pc15 = 1x01 b output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-209 v1.1, 2011-03 multican, v3.0 24.11.4.3 external can time trigger inputs the external can time trigger inputs ectt[7:1] can be used as a transmit trigger for a reference message. in the TC1798, these input lines are connected as shown in table 24-19 . 24.11.4.4 dma request outputs the interrupt output lines int_o0 to int_o1 of the multican module can be used as a dma requestor and are able to trigger dma tr ansfers. int_o[1:0] are connected to the dma controller as shown in table 24-20 . table 24-18 receive input selection receive input of connected to selected by can node 0 p6.8 / rxdcan0 npcr0.rxsel = 000 b p6.10 / rxdcan1 npcr0.rxsel = 001 b can node 1 p6.10 / rxdcan1 npcr1.rxsel = 000 b p6.12 / rxdcan2 npcr1.rxsel = 001 b can node 2 p6.12 / rxdcan2 npcr2.rxsel = 000 b p6.14 / rxdcan3 npcr2.rxsel = 001 b can node 3 p6.14 / rxdcan3 npcr3.rxsel = 000 b p6.8 / rxdcan0 npcr3.rxsel = 001 b table 24-19 external can time trigger inputs receive input connected to from module ectt1 p9.13 port 9 ectt2 p9.14 / req15 input port 9 / external request unit (scu) ectt3 output out5 gpta0 ectt4 output iout2 external request unit (scu) ectt5 output iout3 external request unit (scu) ectt6 - - ectt7 - - www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-210 v1.1, 2011-03 multican, v3.0 24.11.4.5 connectons to gpta0 inputs the interrupt output line int_o15 is connected to the gpta module, see table 24-21 . table 24-20 can-to-dma request connections dma channel connected to can interrupt output selected in dma controller by programming 06 int_o0 chcr06.prsel = 011 b 07 int_o1 chcr07.prsel = 010 b table 24-21 can-to-gpta0 request connections gpta input connected to can interrupt output int0 int_o15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-211 v1.1, 2011-03 multican, v3.0 24.11.5 interrupt control the interrupt control logic in the multican module uses an interrupt compressing scheme that allows high flexibility in in terrupt processing. there are 140 hardware interrupt sources and one software interrupt source available: ? can node interrupts: ? four different interrupt sources for each of the three can nodes = 12 interrupt sources ? message object interrupts: ? two interrupt source for each message object = 128 interrupt sources ? one software in itiated interrupt (register mitr) each of the 140 hardware initiated interrupt sources is controlled by a 4-bit interrupt pointer that directs the interrupt source to one of the sixteen interrupt outputs int_om (m = 0-15). this makes it possible to connec t more than one interrupt source (between one and all) to one interrupt output line. the interrupt wiring matrix shown in figure 24-42 is built up according to the following rules: ? each output of the 4-bit interrupt pointer demultiplexer is connected to exactly one or-gate input of the int_om line. the number ?m? of the corresponding selected int_om interrupt output line is defined by the interrupt pointer value. ? each int_om output line has an input or gate which is connected to all interrupt pointer demultiplexer outputs which are selected by an identical 4-bit pointer value. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-212 v1.1, 2011-03 multican, v3.0 figure 24-42 interrupt compressor mca06284_4tt_128.vsd . . . . . . 16 register mitr can node 0 4 4 can node 1 int_o14 int_o15 1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . int_o0 int_o1 1 1 interrupt wiring matrix 2 message object 0 2 message object 128 4 can node 2 ttcan 4 can node 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-213 v1.1, 2011-03 multican, v3.0 24.11.5.1 can service request control register each of the sixteen interrupt outputs int_om of the multican module is controlled by its service request control registers. note: additional details on service reques t nodes and the service request control registers are described in section ?service request nodes? of the TC1798 system units part. some of the sixteen interrupt outputs of the multican module can be used to trigger operations in the dma controller. can_srcm (m = 0-15 ) can service request control register m (0fc h -m*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-214 v1.1, 2011-03 multican, v3.0 24.11.6 multican module re gister address map in addition to the multican register address map from page 24-63 , the complete multican module register address map of figure 24-43 also shows the general implementation-specific registers for clock control, module identification, and interrupt service request control and adds the absolute address information. the address map of ttcan registers only is shown in figure 24-38 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-215 v1.1, 2011-03 multican, v3.0 figure 24-43 multican module register map mca06285_ttn general module control global module control 000 h 100 h 200 h list registers i msg. index mask register + c0 h + c4 h panel control register module control register + 00 h msg. pending registers k msg. index registers k module interrupt trg. reg. + 40 h + 80 h + c8 h + cc h clock control register module identification reg. fractional divider register + 00 h + 08 h + 0c h node 0 registers node x control registers node x status registers no = can node, x = 0 to (number of can nodes -1) node x interrupt ptr. reg. node x port control reg. node x bit timing reg. node x error counter reg. node x frame counter reg. 300 h node 1 registers no base + 00 h message object registers mo n function control reg. mo n fifo/gtw. ptr. reg. mo = message object; n = 0 to (number of message objects -1) mo n interrupt ptr. reg. mo n accept. mask reg. mo n arbitration reg. mo n data register low mo n data register high mo base + 14 h 1000 h message object 0 message object n-1 1020 h mo base . . . . . . . . . . . . . . . . mo n control register mo base + 1c h mo base + 18 h mo base + 10 h mo base + 08 h mo base + 0c h mo base + 00 h mo base + 04 h 3fff h mo base = 1000 h + n * 20 h interrupt service request control registers 0 - 15 + c0 h + fc h . . no base + 04 h no base + 08 h no base + 0c h no base + 10 h no base + 14 h no base + 18 h message object 1 1040 h mo base + 20 h no base = 200 h + x * 100 h i = 0-7, k = 0-7 no base node x registers node 0 ttcan registers 280 h 2ff h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 controller area networ k controller (multican) users manual 24-216 v1.1, 2011-03 multican, v3.0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-1 v1.1, 2011-03 sent, v1.9 25 single edge nibble transmission (sent) this chapter describes the sent interface of the TC1798. it contains the following sections: ? functional description of the sent kernel (see ?overview? on page 25-2 ) ? sent kernel register descriptions (see ?sent kernel registers? on page 25-22 ) ? TC1798 implementation-specific details and registers of the sent module (port connections and control, interrupt control, address decoding, and clock control, see ?sent module implementation? on page 25-64 25.1 sent kernel description figure 25-1 shows a global view of the sent interface. figure 25-1 general block di agram of the sent interface the sent module communicates with the external world via one i/o line for each channel. the stx lines are the receive data in put signals. they can overlay adc inputs. if the optional spc mode is used, they can be used on a port configured with an open drain transistor. this way the optional spc data can be transmitted and the line is used bidirectionally. in case of an external transceiver, receive and transmit path can be routed to two different ports. dma sent_block_diagram.vsd address decoder interrupt control sent module (kernel ) channel 0 port control . . . timer clock control channel n sensor data spc control sensor data spc control trigger input st0 stm f sent f fpi www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-2 v1.1, 2011-03 sent, v1.9 25.1.1 overview the sent interface provides a serial communication link typically used to connect sensors or other peripheral devices. clock control, address decoding, and serv ice request control are managed by the sent module kernel. the sent ip-module performs communication according to the sent specification j2716 feb2008 rev. 3 2009-06-24. while staying compliant to this standard, it is able to cover as well the short pwm code (spc) protocol extensions. this enhances the standardized sent protocol defined by j2716 feb2008 rev. 3 2009-06-24. spc en ables the use of enhanced protocol functionality like ?synchronous?, ?range sele ction? and ?id selection? protocol mode. receive data on a sent channel can be set up according to the underlying application. in particular the number of nibbles forming one value is configurable. the message storage consists of two 32-bi t registers for each channel, representing a flexible double buffer system. in spc mode, maintaining the sample and transmission schedule as well as providing message status information is support. the register set of the sent module can be accessed directly by the cpu for configuration, data read out and status query. the sent ip-module supports the following features: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-3 v1.1, 2011-03 sent, v1.9 features ? conformance with sent protocol specification j2716 feb2008 rev. 3 2009-06-24 ? data rates of up to 65,8 kbit/s at 3 s tick length and 6 data nibbles on each channel ? support of standard tick times (3 s through 90 s) and ? message tick time programmable between 1 s and 90 s ? 8 sent channels working independently in parallel ? status nibble optionally included in the checksum (default not included) ? sticky interrupt flags, error interrupt optional (default disabled) ? configurable frame length (default is 24 bit), max data size is 32 bits ? serial data processing optional (default: disabled) ? option for bigger frame lengths (must still be fix for each application) ? transparent mode (nibble crcs are written to the receive control register for sw processing) ? support of spc ? support of trailing pause nibble of any length (even longer than 70 ticks) ? indication of system status: stop , initialized, running, synchronized ? the receiver module will monitor the message for the following error conditions: ? calibration pulse length deviates more than +/-25% from the nominal 56 ticks ? too many or too few nibbles between calibration pulses. ? checksum error. ? successive calibration pulse differ by more than 1.5625% ? any nibble data values measured as < 0 or >15. ? when any of those errors is detected, the receiver module shall declare that a message error has occurred and ignore the entire message. ? any of those errors shall cause the receiver to begin searching for a valid calibration pulse to re synchronize. ? option to enable/disable the check of the next calibration pulse before validation of received data ? digital glitch filter suppressing noise ? buffer overrun detection ? optional output inversion for use of external open drain transistor ? optional input inversion for use of external open transistor for level shifting ? interrupt on status nibble violation ? programmable nibble sorting to support lsn or hsn first and relief cpu www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-4 v1.1, 2011-03 sent, v1.9 25.1.2 general operation the single edge nibble transmission encodin g scheme (sent) is intended for use in applications where high resolution sensor data needs to be communicated from a sensor to an engine control unit (ecu). it is intended as a replacement for the lower resolution methods of 10 bit a/d converters and pwm and as a simpler low cost alternative to can or lin. the implementation assumes that t he sensor is a smart sensor containing a microprocessor or dedicated logic dev ice (asic) to create the signal. figure 25-3 shows a typical TC1798 application in which a sent interface reads a sensor device. figure 25-2 sent to extern al device connection sent communication is unidirectional from sensor to controller without any synchronization. the sensor signal is transmi tted as a series of pwm blocks measured as falling to falling edge times. the short pwm code (spc) extension overcomes the drawback of unidirectionality as said above while keeping conformance to the standard. figure 25-3 shows a typical TC1798 application in which an spc enabled sent ecu reads an spc enabled sent sensor device. sent_circuit.vsd sent module sensor r input output st out st in sensor data www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-5 v1.1, 2011-03 sent, v1.9 figure 25-3 sent spc to external device connection some applications are: ? read out of the external throttle position sensor (e.g. sent enabled linear hall sensor) ? receiving pedal position ? synchronize sampling and read out of up to four sensors on one single line (spc) ? selection of 1 out of 4 sensors connected to a single sent channel. ? serial connections of the TC1798 to other peripheral devices 25.1.2.1 definitions sent: single edge nibble transmission nibble: four bit value between 0 and 15 = half a byte = one character in hex (0 to f) spc: short pwm code pwm: pulse width modulation asic: application specific integrated circuit can: controller area network lin: local interconnect network iso: international organization for standardization ecu: electronic control unit fsm: finite state machine sent_spc_circuit.vsd sent module sensor r output st out spc output st in sensor data spc data input spc input www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-6 v1.1, 2011-03 sent, v1.9 25.1.3 standard sent operation standard sent mode supports communication fully compliant to j2716 feb2008 rev. 3 2009-06-24, in which only the external dev ice is sending and the ecu is receiving. in this unidirectional communication, both transmitter and receiver use the same data frame format and have the same baud rate. these settings are defined at system integration time and do not change for a given application. data is received on pin st. figure 25-4 shows the block diagram of the sent module when operating in standard sent mode. figure 25-4 standard sent mode operation serial data reception receive data registers receive channel control sent_receive_channel_block.vsd rdrx a rdrx b view (nibble collate ) rdrx baud rate auto adjust baud rate range check baud rate drift check mode control crc check / validate nibble collate nibble count /value check interrupt f sent f fracdiv serial data control 13 node pointer 16 rsrx serial receive r st[x:0 ] samp- ling pulse measurement spike filter st input control st m u x opt. invert. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-7 v1.1, 2011-03 sent, v1.9 25.1.3.1 frame formats and definitions this section describes the frame formats and definitions of the sent protocol. basic definitions figure 25-5 shows the layout and definitions of a standard sent frame. note that the sent standard does not specify whether the most significant nibble or the least significant nibble is sent out first. figure 25-5 standard encoding frame standard serial data encoding the serial data is transmitted bit wise per frame in bit 2 of the status and communication nibbles of consecutive messages from the transmitter. figure 25-6 standard se rial data encoding sent_frame.vsd 5 ticks 56 ticks 12 ticks 12 - 27 ticks sync. / calibration status & communication (4 bit data) 12 ticks 12 - 27 ticks nibble 1 (4 bit data) 5 ticks 5 ticks 12 - 27 ticks nibble 2 (4 bit data) . . . 12 - 27 ticks crc check (4 bit data) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-8 v1.1, 2011-03 sent, v1.9 standard serial data frame serial data is communicated in a 16-bit sequence as shown in figure 25-7 . the staring bit of a serial message is indicated by a 1 in bit 3 o the status and communication nibble. that sent message and the next 15 must be successfully transmitted (no errors) for the serial value to be received. the crc generation is identical with the crc generation on the data nibbles. figure 25-7 serial data frame crc calculation the signal data and the serial data is secured with a 4 bit crc. the standard crc calculation method is well defined in the j2716 feb2008 rev. 3 2009-06-24. note: rcr.crz defines, if a zero nibbl e is added for calculation or not. the alternative checksum nibble is a 4-bit crc of the data nibbles (including the status nibble if rcr.sni is set, as used in s ensor tle4998). the crc is calculated using a polynomial x^4 +x^3 + x^2 + 1 with a seed value of 0101. in order to facilitate crc implementations and to avoid ambiguities, an example implementation of the alternative 4-bit crc is given below. this is used e.g. in the sensor tle4998 for the signal data. see figure 25-8 for details. // fast way for any c with low memory and compute capabilities // contains input data (status nibble, 6 data nibble, crc) char data[8] = {?}; // required variables and lut char checksum, i; char crclookup[16] = {0, 13, 7, 10, 14, 3, 9, 4, 1, 12, 6, 11, 15, 2, 8, 5}; checksum= 5; // initialize checksum with seed ?0101? for (i=0; i<7; i++) { checksum = checksum ^ data[i]; checksum = crclookup[checksum]; }; // finally check if data[7] is equal to checksum note: for the ?extended serial message frame format?, an own 6-bit crc calculation method is defined by the standard. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-9 v1.1, 2011-03 sent, v1.9 figure 25-8 alternate vs. sae crc calculation generator = 1101 seed = 0101 , use this constant as old crc value at first call preinit: value xor seed xor only if msb = 1 value 0 0 0 0 seed 0 0 0 0 0 0 0 0 0 <<1 genpoly 0 0 0 0 xor value xor seed 4x alt. crc calculation seed 0 0 0 0 0 0 0 0 value 0 0 0 0 0 <<1 genpoly 0 0 0 0 seed 4x sae crc calculation or value xor only if msb = 1 2nd nibble 1st nibble 2nd nibble 1st nibble www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-10 v1.1, 2011-03 sent, v1.9 extended serial data encoding the serial data is transmitted bit wise per frame in bits [3:2] of the status and communication nibbles of 18 consecutive messages from the transmitter. figure 25-9 extended se rial data encoding extended serial data frame serial data is communicated in a 18-bit sequence as shown in figure 25-10 . the frame start of a serial message is indicated by the unique pattern ?01111110? in bit #3 of the status and communication nibble. the first ?1? in a series of six ones (after a ?0?) indicates the first nibble of a serial message frame. serial data bit #3 of serial communication nibbles 1 - 6 are set to ?1?. serial data bit #3 of serial communication nibbles 7, 13 and 18 are set to ?0?. 18 consecutive sent messages must be successfully transmitted (no errors) for the serial value to be received. the crc generation is different from the crc generation on the data nibbles. (see sent standard) the serial message frame contains 21 bits of message data and a 6-bit frame-check sequence. two different configurations can be chosen: ? 12-bit data and 8-bit message id ? 16-bit data and 4-bit message id a configuration bit (serial data bit #3, serial communication nibble no. 8) determines the configuration of the enhanced serial message frame. it determines how the sent module automatically interprets the serial data. ? configuration bit = 0: 12-bit data and 8-bit message id ? configuration bit = 1: 16-bit data and 4-bit message id 0 1 1 11 11 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-11 v1.1, 2011-03 sent, v1.9 figure 25-10 extended serial data frame figure 25-11 shows in detail the frame structure for extended serial data frames with configuration bit = 0. figure 25-11 configuration bit = 0 figure 25-12 shows in detail the frame structure for extended serial data frames with configuration bit = 1. figure 25-12 configuration bit = 1 agreements of sent taskforce may 13, 2009 serial communicat ion nibble receive no. serial data (bit # 3) serial data (bit # 2) 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 12-bit data field 6-bit crc 1 1 1 1 1 1 0 c 0 0 0 0 0 0 0 0 0 0 8-bit id (3-0 ) or 4-bit data 8-bit id (7-4) optional: 4 additional data bits instead of id bits configuration bit 0: 12-bit data, 8-bit id 1: 16-bit data, 4-bit id serial communication ni bble receive no. serial data (bit # 3) serial data (bit # 2) 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15 16 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 17 18 0 0 8- bi t id ( 3 -0) 12-bit data field 6-bit crc 8-bit id (7-4) 8-bit message id id 7 (msb) id 6 id 5 id 4 id 3 id 2 id 1 id 0 (lsb) 12-bit data d 7 d 6 d 11 (msb) d 10 d 9 d 8 d 5 d 4 d 3 d 2 d 1 d 0 (lsb) crc 5 (msb) crc 4 cr c 3 cr c 2 cr c 1 cr c 0 (lsb) c configuration bit 6-bit crc serial communication nibble receive no. serial data (bit # 3) serial data (bit # 2) 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15 16 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 17 18 0 0 8- bi t id ( 3-0) 12-bit data field 6-bit crc 8-bit id (7-4) 4-bit message id id 3 (msb) id 2 id 1 id 0 (lsb) 12 -b it d ata d 7 d 6 d 11 d 10 d 9 d 8 d 5 d 4 d 3 d 2 d 1 d 0 (lsb) crc 5 (msb) crc 4 cr c 3 cr c 2 cr c 1 cr c 0 (lsb) c configur ati on bit 6-bit crc d 15 (msb) d 14 d 13 d 12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-12 v1.1, 2011-03 sent, v1.9 25.1.4 spc operation the module supports a spc (short pwm code) protocol, which enhances the standardized sent protocol (single edge nibble transmission) defined by j2716 feb2008 rev. 3 2009-06-24. spc enables the use of enhanced protocol functionality due to the ability to select between ?syn chronous?, ?range select ion? and ?id selection? protocol mode or even ?bidirectional transmit mode?. 25.1.4.1 synchronous transmission in the ?synchronous? mode, the sensor (slave) starts to transfer a complete data frame only after a low pulse is forced by the master on the out pin. this means that the data line is bidirectional - an open drain output of the micro controller (master) sends the trigger pulse. the sensor then initiates a sync pulse and starts to calculate the new output data value. after the synchronization period, the data follows in form of a standard sent frame, starting with the status, data and crc nibbles. at the end, an end pulse allows the crc nibble decoding and indicates that the data line is idle again. the timing diagram in figure 25-13 visualizes a synchronous transmission figure 25-13 synchronous transmission (spc) 25.1.4.2 range selection the low time duration of the master can be used to select the range of the sensor in spc dynamic range selection mode. out synchronization frame status nibble generated synchronization frame generated status nibble delay delay delay ecu trigger pulse sensor initiates synchronization frame zero nibble time www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-13 v1.1, 2011-03 sent, v1.9 figure 25-14 range (spc) 25.1.4.3 id selection this functionality is similar to the previous mode, but instead of switching the range of one sensor, one of up to four sensors are selectable on a bus (bus mode, 1 master with up to 4 slaves). this allows parallel connect ion of up to 4 sensors using only three lines (vdd, gnd, out), as illustrated in figure 25-15 . figure 25-15 id selection (spc) out synchronization frame status nibble generated synchronization frame generated status nibble delay delay delay fixed delay sensor initiates synchronization frame www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-14 v1.1, 2011-03 sent, v1.9 25.1.4.4 bidirectional transmit mode after addressing the sensor the ecu interrupts the sens or sync pulse by pulling down the line. the ecu starts to transmit own nibbl es on the time base of the selected sensor. the ecu has to adapt the sensors timing from an earlier received cycle. the sensor detects the falling edge that infr inges the protocol and switches to receive mode as illustrated in figure 25-16 . figure 25-16 bidirectional transmit mode (spc) 25.1.4.5 spc timing an spc transmission is initiated by a master pulse on the out pin. to detect a low level on the out pin, the voltage must be below a threshold vthf. the sensor detects that the out line has been released as soon as vthr is crossed. figure 25-17 shows the timing definitions for the master pulse. the master low time tmlow as well as the total trigger time tmtr are individual for the different spc modes and are given in the sensors specifications.it is recommended to chose the typical master low time exactly between the minimum and the maximum possible time given by the connected sensor: tmlow,typ = (tmlow,min + tmlow,max) / 2. out delay fixed delay sensor initiates synchronization frame ecu interrupts and initiates own transmission sync frame status nibble www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-15 v1.1, 2011-03 sent, v1.9 figure 25-17 timing (spc) 25.1.4.6 abort of frames only a reset condition of the device or choosing mode 0 by clearing bit field scrx.trig can abort a current transmission. the sent module does not start a new frame transmission when the channel becomes disabled, the suspend mode is requested, or the sleep mode is entered. if one of these three conditions becomes active during a running frame transmission, the frame transmission is completely finished before the requested abort state is entered. note that in this case no frame finished interrupt is generated any more. note: received frames are aborted immediatel y on a disable, suspend or sleep request. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-16 v1.1, 2011-03 sent, v1.9 25.1.5 baud rate generation the nominal baud rate of each channel is individually adjustable. this is required as it is depending from the connected sensor and its current deviation from nominal frequency. the actual baud rate of the channel follows automatically the baud rate of the connected device and its current deviation from nominal frequency. the adaptation range is +- 25% as specified in j2716 feb2008 rev. 3 2009-06-24. chapter 25.1.5 shows in detail how the baud rate for each channel is adjusted. 1 / f tick_x defines the resulting tick length. in the first stage, a global fractional divider serves as pre divider. its intermediate frequency f fracdiv can be set up so that it is handy as input frequency for the different sent channels. the clock signal f pdiv of a channel must always be at least 20 times the nominal tick frequency of the channel. this is to allow for the highly flexible and big tolerance of +-25% versus the sending device. in addition the module must be able to detect a deviation in the length of 2 consecutive sync hronization / calibration pulses of 1.5625% (1/64) and adapt the own baud rate. the tick time is typically 3 s but can vary by standard and take values up to 10 s. future application might require even shorter tick times for higher repetition rates. this is why this implementation allows for an even extended range of 1 ? 90 s. to achieve this each channel has its own fractional divider. this allows to downscale the frequency of f tick precisely to the required tick frequency. for details on the principles of a fractional divider, please refer to the scu chapter of TC1798 section ?clock control?. the sent module provides two clock signals to the channels ( figure 25-18 ): ? f sent this is the module clock that is used inside the sent kernel for control purposes such as clocking of control logic and register operations. the frequency of f sent is always identical to the system clock frequency f fpi . the clock control register sent_clc makes it possible to enable/disable f sent under certain conditions. ? f fracdiv this clock is the module clock that is used inside the sent kernel for baud rate generation of the serial channels. the fractional divider register sent_fdr controls the frequency of f fracdiv . usually not required and set to 1. the channels generate two local clock signals: ? f pdiv_x this clock is the channel clock that is used inside the sent channel x for baud rate generation of the serial channel. the divider register sent_cpdrx controls the frequency of f pdiv_x . ? f tick_x this clock is the channel clock that is used inside the sent channel as the baud rate frequency. the fractional divider register sent_cfdrx controls the frequency of www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-17 v1.1, 2011-03 sent, v1.9 f tick_x .the higher the value of div the higher the precision with which the synchronization / calibration pulse and the deviation in the length of 2 consecutive synchronization / calibration pulses (drift) can be measured. div must be set in an interval of [560, 3276]. ? each time a synchronization / calibration pulse starts divm is measured. divm is the result of measuring the calibration pulse duration with f pdiv_x . at the end of the synchronization / calibration pulse this val ue is taken as new divider of the cfdr. each time a pulse starts, the internal accumulator of the cfdr is preset with divm / 2. this is required to center the data eye and to make the margin symmetrical. figure 25-18 sent module clock generation the following two formulas define the frequency of f fracdiv : f fracdiv = f sent / (1024 - sent_fdr.step); fdr.dm = 01 b (25.1) f fracdiv = f sent x sent_fdr.step / 1024 with step = 0 ? 1023; fdr.dm = 10 b (25.2) the following formula defines the frequency of f pdiv_x : f pdiv_x = f fracdiv / (sent_cpdrx.pdiv + 1) (25.3) the following formula defines the nominal frequency of f tick_x . for the actual frequency of f tick_x div is replaced by divm after the current sensor frequency was validly measured. f tick_x = f pdiv_x x 56 / sent_cfdrx.div with div = 560 ? 3276 (25.4) sent_clock_gen.vsd clock control register sent_clc sent clock generation f fpi fractional divider register sent_fdr sent channel x of n predivider channel fd f sent f fracdiv f pdiv_x f sen t f tick _x www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-18 v1.1, 2011-03 sent, v1.9 25.1.6 error detect ion capabilities each sent channel can detect and signal the following error conditions: protocol level: ? calibration pulse length deviates more than +/-25% from the nominal 56 ticks ? too many or too few nibbles between calibration pulses ? checksum error ? successive calibration pulse differ by more than 1.5625% ? any nibble data values measured as < 0 or >15 ? wrong status and communication nibbles ? serial communication crc error transfer management level: ? receive data buffer overrun ? spc data buffer underrun www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-19 v1.1, 2011-03 sent, v1.9 25.1.7 digital glitch filter very slow slopes and signal noise can lead to fast transitions of the input signal. these unwanted transitions are suppressed by a digital glitch filter similar to a filter and prescaler cell (fpc) of infineons gpta? in delayed debounce filter mode with up and down (no reset). it is built for filtering very fast transitions only. the filter calculates the integral of the signal. if the integral reaches a programmable saturation point, the signal change is notified to the pulse measurement unit. thus it helps to find the exact pulse length for said slow slopes in noisy environment. the glitch filter is clocked with f pdiv . if the state of the input sample differs from the current output signal value, the internal counter is incremented by one. when the state of the input sample matches the current output signal value and the timer is not in idle, the timer is decremented by one. when the timer matches the compare value stored in iocrx.depth, the level of the output signal line is inverted. the timer will be reset and set to idle state again. the depth of the filter can be programmed to a value between 1 and 15. typically a depth of 3 to 5 t pdiv is sufficient. by default it is cleared. if iocrx.depth is cleared the filter is inactive. nevertheless, the input signal is sampled with f pdiv . the internal signal after the filter will change value not before the new value was sampled depth times. if during this period a spike occurs, it takes 2 x t pdiv times longer for the internal signal to change value. the filters principal implies a delay of the signal by (depth x t pdiv ). upon detection of glitch during rising or falling edge, iocrx.reg or iocrx.feg is set. the rising / falling edge glitch flags must be reset by software. figure 25-19 shows the digital glitch filter: figure 25-19 digital glitch filter sent _fpcdeldec.vsd signal input timer value signal output timer threshold total signal delay www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-20 v1.1, 2011-03 sent, v1.9 25.1.8 interrupts 4 interrupt sources are available for the sen t module. four interrupt sources for any 8 channels are provided by the sent module. rdi indicates a receive data interrupt. it is activated when a received frame is moved to a receive data register rdr. rsi indicates a receive frame success interrupt, i.e. the crc was successful. both rdi and rsi will be issued together in normal use cases where the frame size is not bigger than 8 nibbles and crc is correct. rbi indicates a receive buffer overrun interrupt. it is activated when a new frame is transferred to a receive data register rdr while the old value was still not read by the host (?overwrite?), i.e. the kernel wants to set any of the two interrupts rsi and rdi and finds any of these two interrupts already set. tdi indi cates a transmit interrupt. it is activated when data is moved from a scr to a transmit shift register. tbi indicates a transfer buffer under run interrupt. it is set after data has been completely transferred (plen exceeded) and no new data was written to scrx. in addition the protocol error interrupts are available: fri, fdi, nni, nvi, crci. if one of the protocol interrupts is activated, data is to be treated as invalid according to j2716 feb2008 rev. 3 2009-06-24. wsi, sdi scri treat the interrupts referring to the status and communication nibble. for acceleration of the interrupt service routine, a register intov for any 32 channels is implemented that holds a flag for each channel. this flag is automatically set if there is an interrupt pending for the channel which is enabled. it is automatically reset, if no more enabled interrupt is pending for this channel. the interrupt structure is shown in figure 25-20 . the interrupt request or the corresponding interrupt set bit (in register intset) can trigger the interrupt generation at the selected interrupt node. the service request pulse is generated independently from the interrupt flag in register intstatx. the interrupt flag can be cleared by software by writing to the corresponding bit in register intclr. if more than one interrupt source is connected to the same interrupt node pointer (in register inpx), the requests are combined to one common line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-21 v1.1, 2011-03 sent, v1.9 figure 25-20 interrupt generation 25.1.9 trigger outputs any interrupt source can be used as tri gger output trigo outside the module. each trigo is connected to a dma input. see table 25-3 ?service request lines of sent? on page 25-65 . inp_struct .vsd o r int_event sw_set a n d int_flag sw_clear inp o r other interrupt sources on the same inp o r o r o r other interrupt sources a n d int_enable a n d www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-22 v1.1, 2011-03 sent, v1.9 25.2 sent kernel registers this section describes the kernel registers of the sent module. all sent kernel register names described in this section will be referenced in other parts of the TC1798 users manual by the module name prefix ?sent_? for the sent interface. all registers in the sent address spaces are reset with the application reset (definition see scu section ?reset operation?). sent kernel register overview figure 25-21 sent kernel registers the complete and detailed address map of the sent module is described in table 25-1 on page 25-22 . note: x can take the values 0 ? 7 table 25-1 registers address space - sent kernel registers module base address end address note sent f032 1000 h f032 19ff h ? x=0?7 sent_kernel_regs.vsd data registers rcrx channel status and control registers scrx rdrx intov intstatx intsetx iocrx kernel registers id intclrx intenx inpx rsrx cpdrx cfdrx viewx fdr sdsx www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-23 v1.1, 2011-03 sent, v1.9 table 25-2 registers overview - sent kernel registers register short name register long name offset address 1) access mode description see read write sent_clc sent clock control register 00 h sv, u sv, e page 25-26 - reserved 04 h - 07 h nbe nbe sent_id module identification register 08 h sv, u nbe page 25-25 sent_fdr module fractional divider 0c h sv, u e page 25-27 - reserved 10 h nbe nbe sent_intov interrupt overview register 14 h sv, u sv, u page 25-48 - reserved 18 h - 7c h nbe nbe sent_rdrx receive data register 0 80 h - 9c h sv, u sv, u page 25-42 - reserved a0 h - fc h nbe nbe sent_cpdrx channel pre divider register 0 100 h + x * 40 h sv, u sv, u page 25-29 sent_cfdrx channel fractional divider register 0 104 h + x * 40 h sv, u sv, u page 25-30 sent_rcrx receiver control register 0 108 h + x * 40 h sv, u sv, u page 25-31 sent_rsrx receive status register 0 10c h + x * 40 h sv, u sv, u page 25-37 sent_sdsx serial data and status register 0 110 h + x * 40 h sv, u sv, u page 25-38 sent_iocrx input and output control register 0 114 h + x * 40 h sv, u sv, u page 25-39 sent_scrx spc control register 0 118 h + x * 40 h sv, u sv, u page 25-46 sent_viewx receive data view register 0 11c h + x * 40 h sv, u sv, u page 25-44 sent_intstatx interrupt status register 0 120 h + x * 40 h sv, u sv, u page 25-49 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-24 v1.1, 2011-03 sent, v1.9 sent_intsetx interrupt set register 0 124 h + x * 40 h sv, u sv, u page 25-55 sent_intclrx interrupt clear register 0 128 h + x * 40 h sv, u sv, u page 25-57 sent_intenx interrupt enable register 0 12c h + x * 40 h sv, u sv, u page 25-59 sent_inpx interrupt node pointer register 0 130 h + x * 40 h sv, u sv, u page 25-62 - reserved 134 h + x * 40 h - 13f h + x * 40 h nbe nbe sent_src3 service request control 3 register 9f0 h sv, u sv, u page 25-71 sent_src2 service request control 2 register 9f4 h sv, u sv, u page 25-71 sent_src1 service request control 1 register 9f8 h sv, u sv, u page 25-71 sent_src0 service request control 0 register 9fc h sv, u sv, u page 25-71 1) the absolute register address is calculated as follows: module base address ( table 25-1 ) + offset address (shown in this column) table 25-2 registers overview - sent kernel registers (cont?d) register short name register long name offset address 1) access mode description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-25 v1.1, 2011-03 sent, v1.9 25.2.1 module control module identification register the sent module identification register id contains read-only information about the module version. id module identificat ion register (08 h ) reset value: 0080 c0xx h 31 16 15 8 7 0 modnum modtype modrev rrr field bits type description modrev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). modtype [15:8] r module type this bit field defines the module as a 32-bit module: c0 h modnum [31:16] r module number value this bit field defines the module identification number for the sent: 0080 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-26 v1.1, 2011-03 sent, v1.9 clock control register this chapter summarizes the features of clock control. clc controls in general switching on and off of the module. please refer to chapter ?module clock generation? of TC1798 for more details. note: after a hardware reset operation, the f sent and f fracdiv clocks are switched off and the sent module is disabled (diss set). sent_clc sent clock control register (00 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we e dis sp en dis s dis r r rwwrwrw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the module. diss 1r module disable status bit bit indicates the current status of the module. spen 2rw module suspend enable for ocds used to enable the suspend mode edis 3rw sleep mode en able control used to control module?s sleep mode. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. fsoe 5rw fast switch off enable used to switch off fast clock in suspend mode. 0 [31:6] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-27 v1.1, 2011-03 sent, v1.9 fractional divider register the fractional divider register controls the input clock f fracdiv of all sent channels. sent_fdr sent fractional divider register (0c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0result rrh 1514131211109876543210 dm 0 fdis step rw rw rw rw field bits type description step [9:0] rw step value reload or addition value for result. fdis 10 rw freeze disable this bit controls the freeze function for this module. for more details please refer to scu chapter, section clock control. 0 b module operates on co rrected clock, with reduced modulation jitter (default) 1 b module operates on uncorrected clock with full modulation jitter dm [15:14] rw divider mode dm selects normal or fractional divider mode. 00 b fractional divider is switched off; no output clock is generated. the reset external divider signal is 1. result is not updated (default after system reset). 01 b normal divider mode selected. 10 b fractional divider mode selected. 11 b fractional divider is switched off; no output clock is generated. result is not updated. result [25:16] rh result value bit field for the addition result. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-28 v1.1, 2011-03 sent, v1.9 0 [13:11], [31:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-29 v1.1, 2011-03 sent, v1.9 25.2.2 channel baud rate registers channel pre divider register the channel pre divider register cpdrx contains the pre divider that is related to the sent channel baud rate. see equation (25.3) cpdrx (x = 0-7) channel pre divider register x (100 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0pdiv rrw field bits type description pdiv [11:0] rw divider factor of pre divider for channel x divides f fracdiv by (pdiv + 1) and delivers f pdiv_x to the channel fractional divider. rcr.cen must be cleared before changing cpdr.pdiv or cfdr.div. 0 [31:12] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-30 v1.1, 2011-03 sent, v1.9 channel fractional divider register the channel fractional divider register cfdrx contains control bits/bit fields that are related to the sent channel baud rate. see equation (25.4) in chapter 25.1.5 for a detailed description. cfdrx (x = 0-7) channel fractional divider register x(104 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0divm rrh 1514131211109876543210 0div rrw field bits type description div [11:0] rw divider value initial and reference divider value for the cfdr. div must be programmed > 0. if cleared, div becomes 1. if written, divm is updated automatically with the same value.rcr.cen must be cleared before changing cpdr.pdiv or cfdr.div. divm [27:16] rh measured divider value divm is automatically updated by hw to adjust the receiver frequency to the current sender frequency. this value is kept automatically in the range of 75% div < divm < 125% div write data is ignored. 0 [15:12], [31:28] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-31 v1.1, 2011-03 sent, v1.9 25.2.3 receiver control and status registers receiver control register the receiver control register rcrx contains control bits/bit fields that are related to the sent receiver operation. rcrx (x = 0-7) receiver control register x (108 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 sus en ide esf crz r rwrwrwrw 1514131211109876543210 frl cfc cdis sc dis sdp sni ace iep cen rw rw rw rw rw rw rw rw rw field bits type description cen 0rw channel enable when cen is set, the receiver of channel x is enabled. the internal receiver state ma chine can be initialized by switching the channel off and on. this does not change the current register content. 0 b channel x disabled (default) 1 b channel x enabled iep 1rw ignore end pulse when iep is set, an end pulse is ignored. an end pulse can be generated in spc mode or as pause pulse. 0 b end pulse not ignored (default) 1 b end pulse ignored for systems with an end pulse, during synchronize or re-synchronize of reception, if calibration pulses are detected one immediately following the other, the first calibration pulse shall be ignored as it may be a pause pulse with duration matching the calibration pulse range. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-32 v1.1, 2011-03 sent, v1.9 ace 2rw alternative crc mode enable when ace is set, the crc is calculated in an alternative way for both: fast (signal) and slow (serial message) data path. note: if esf is set, the standard 6 bit crc is always used for the serial message and ace is ignored. 0 b serial crc calculation as specified in j2716 feb2008 rev. 3 2009-06-24 (default) 1 b alternative: 4 bit in parallel crc calculation as used e.g. in hall sensor tle4998c. sni 3rw status nibble included in crc when sni is set, the status nibble is included in (signal data) crc. 0 b status nibble not included in crc (default) 1 b status nibble included in crc (as used e.g. in hall sensor tle4998c). sdp 4rw serial data processing mode this bit switches automatic serial data processing on. 0 b automatic serial data processing is disabled. status and communication nibble can be read from rsrx for sw processing. (default) 1 b automatic serial data processing is enabled. status and communication nibble can be read from rsrx; message id, serial data and scrc can be read from sdsx after serial data interrupt sdi is activated. scdis 5rw crc for serial data disabled mode this bit selects the crc disabled mode. 00 b crc is enabled (default) 01 b crc is disabled crc nibble can be read from sdsx. the cpu must perform the crc on the current data by sw. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-33 v1.1, 2011-03 sent, v1.9 cdis 6rw crc disabled mode this bit selects the crc disabled mode. 00 b crc is enabled (default) 01 b crc is disabled crc nibble can be read from rsrx. the cpu must perform the crc on the current data by sw. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-34 v1.1, 2011-03 sent, v1.9 cfc 7rw consecutive frame check this bit determines the way the most recently received frame buffer is indicated as valid. 0 b check against past sync pulse the current synchronization / calibration pulse is compared to the synchronization / calibration pulse received immediately before. the whole frame is invalid if the synchronization / calibration pulse length differs from the length of the synchronization / calibration pulse before by more than 1.5625%. in this case of error, its length is not used as new reference. in case the check passes and no other error occurs the frame buffer is indicated valid immediately after crc calculation result is correct. resynchronization: on the th ird successive calibration pulse error, the current calibration pulse value is considered as valid and the message accepted unless the message frame contains other errors. in both cases a receive data interrupt (rdi), or a referring error inte rrupt is issued. 1 b check against future sync pulse the current synchronization / calibration pulse is compared with the synchronization / calibration pulse received immediately after the current frame. the whole frame is invalid if the synchronization / calibration pulse length differs from the length of the following synchronization / calibration pulse by more than 1.5625%. resynchronization: in this ca se of error, the current length is used as new reference. note: the whole frame can be indicated valid only after additionally measuring the synchronization / calibration pulse of the successive frame. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-35 v1.1, 2011-03 sent, v1.9 frl [15:8] rw frame length frl determines the number of data nibbles per frame that the sent channel x is setup for. note that frl does not include the synchronization / calibration pulse, the status and communication nibble, the crc nibble nor the additional zero length nibble that might be introduced by use of spc. 00000000 b no data nibble 00000001 b 1 data nibble 00000010 b 2 data nibbles 00000011 b 3 nibbles ? b ? 00001000 b 8 nibbles maximum in normal length mode ? b ? 11111111 b 255 nibbles if more than 8 nibbles are configured, please note: in addition to the receive success interrupt rsi at the successfully received end of a frame, a receive data interrupt rdi is issued each time 8 nibbles have been transferred to the receive data register rdrx. at the end of a frame, rdi is issued if rsi is issued. if an error occurred, rdi is not set at the end of a frame. if no crc has been received at the point in time where rdi is issued, the receive data interrupt is no indication whether or not the transf er was successful so far. a crc error interrupt is issued at the end of the frame if automatic crc check is enabled and the crc is wrong. crz 16 rw crc with zero nibble for serial data this bit selects the crc method. if set, a zero nibble at the end of crc calculation (and only in calculation) is added. e.g. as 7th nibble (in case of 6 data nibbles) 00 b trailing zero nibble added in calculation, recommended by standard (default) 01 b no trailing zero nibble added in calculation, legacy mode by standard. background: if the common slope of last nibble and crc moves in error, the error correction is worse for the last nibble than for all other nibbles. setting crz overcomes this problem. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-36 v1.1, 2011-03 sent, v1.9 esf 17 rw extended serial frame mode this bit selects the serial frame structure. 0 b standard (16 frames, 4 bit id, 8 bit data, 4 bit crc) 1 b extended (18 frames, 4 or 8 bit id, 12 or 16 bit data, 6 bit crc) ide 18 rw ignore drift error mode this bit selects if drift errors lead to frame rejection and if an interrupt (intstat.fdi) is generated. used, if sensors are triggered by spc. during a long pause period the accumulated drift could be more than 1.5625%. in this special case setting ide is useful. 0 b drift errors enabled (default) 1 b drift errors disabled susen 19 rw suspend enable this bit makes it possible to set the sent channel into suspend mode via ocds (on chip debug support): 0 b an ocds suspend trigger is ignored by this sent channel. 1 b an ocds suspend trigger disables the sent channel: as soon as the spc sender logic of the sent channel becomes idle, the module is stopped while all registers of the channel stay readable. the receiver is stopped unconditionally. a partly received frame is discarded. bit susen is reset via ocds reset. 0 [31:20] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-37 v1.1, 2011-03 sent, v1.9 receiver status register the receive status register provides the status information of channel x. rsrx (x = 0-7) receive status register x (10c h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 scn 0 cst crc rrrrr field bits type description crc [3:0] r crc of last frame. crc 0 is on bit position 0. cst [5:4] r channel status cst shows the current status of channel x. 00 b stop channel is disabled and can be configured 01 b initialized channel is configured and enabled and no synchronization / calibration pulse was received since last enable. 10 b running one or more synchronization / calibration pulses were received and frequency range or frequency drift not or no longer in range. fallback status from synchronized. 11 b synchronized frequency range and frequency drift in range scn [11:8] r status and communication nibble of last frame. scn 0 is on bit position 8. 0 [7:6], [31:12] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-38 v1.1, 2011-03 sent, v1.9 serial data and status register the serial (receive) data and status register provides the data and status information of channel x. sdsx (x = 0-7) serial data and status register x (110 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 con 0 scrc mid rr r r 1514131211109876543210 sd r field bits type description sd [15:0] r serial data of last serial data frame. sd 0 is on bit position 0. if rcr.esf is cleared 8 bits of data are available and bits [15:8] are zero. if rcr.esf is set and if sds.con is cleared 12 bits of data are available and bits [15:12] are zero. mid [23:16] r message id of last serial data frame. id 0 is on bit position 16. if rcr.esf is cleared, or if sds.con is set, bits [23:20] are zero. scrc [29:24] r scrc crc of last serial data frame. crc 0 is on position 24. if rcr.esf is cleared, bits [29:28] are always zero. con 31 r configuration bit of last serial frame. 0 b 12-bit data and 8-bit message id 1 b 16-bit data and 4-bit message id 0 30 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-39 v1.1, 2011-03 sent, v1.9 25.2.4 input and output control input and output control register functions the input and output control register iocrx determines for the sent channel x: for the receiver: ? the alternate input ? the filter depth ? the input signal polarity for the spc unit ? the trigger source ? the output signal polarity iocrx (x = 0-7) input and output control register x(114 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 txm rxm trm ctr 0 ets rh rh rh rw r rw 1514131211109876543210 c feg c reg feg reg 0 iie oie depth 0 alti rw rw rh rh r rw rw rw r rw field bits type description alti [1:0] rw alternate input select selects the alternate input for channel y: 0000 b alternate input 0 selected 0001 b alternate input 1 selected ? b ? 0011 b alternate input 3 selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-40 v1.1, 2011-03 sent, v1.9 depth [7:4] rw digital glitch filter depth depth determines the number of port input samples clocked with f pdiv that are taken into account for the calculation of the floating average. the higher depth is chosen to be, the longer the glitches that are suppressed and the longer the delay of the input signal introduced by this filter. 0000 b off, default 0001 b 1 t pdiv 0010 b 2 0011 b 3 ? b ? 1111 b 15 oie 8rw output inverter enable channel x selects the pulse polarity of the output of channel x 0 b pulse polarity is active low 1 b pulse polarity is active high iie 9rw input inverter enable channel x selects the pulse polarity of the input of channel x 0 b pulse polarity is active low 1 b pulse polarity is active high reg 12 rh rising edge glitch flag for channel x shows the status of the glitch detection of channel x 0 b no glitch detected on rising edge 1 b glitch detected on rising edge reg is cleared by setting creg. feg 13 rh falling edge glitch flag for channel x shows the status of the glitch detection of channel x 0 b no glitch detected on falling edge 1 b glitch detected on falling edge feg is cleared by setting cfeg. creg 14 rw clear rising edge glitch flag for channel x clears the status flag reg 0 b reg is not cleared 1 b reg is cleared creg always read zero. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-41 v1.1, 2011-03 sent, v1.9 cfeg 15 rw clear falling edge glitch flag for channel x clears the status flag feg 0 b feg is not cleared 1 b feg is cleared cfeg always read zero. ets [18:16] rw external trigger select selects the external trig ger line if scrx.trig is programmed to 11 b . 000 b trig0 001 b trig1 ? b ? 111 b trig7 ctr 28 rw clear trigger monitor flag for channel x clears the status flag trm 0 b trm is not cleared 1 b trm is cleared ctr always read zero. trm 29 rh trigger monitor flag for channel x shows the status of the trigger detection of channel x 0 b no trigger detected 1 b trigger detected (one or several) trm is cleared by setting ctr. rxm 30 rh receive monitor for channel x shows the status of the receive signal of channel x after glitch filtering and inverted as specified by iie. 0 b current signal is low. 1 b current signal is high. txm 31 rh transmit monitor for channel x shows the status of the transmit signal of channel x inverted as specified by oie. 0 b current signal is low. 1 b current signal is high. 0 [3:2], [11:10] , [27:19] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-42 v1.1, 2011-03 sent, v1.9 25.2.5 receive data registers receive data registers rdrx the receive data registers rdrx for channel x shows the data content of a received data frame. register viewx is used to sort the nibbles. note: register view must be set up correctly to see all data nibbles of the frame! by default the application software set view to 7654 3210 h . note: the internal receive buffer is always cleared (0x0000 0000 h ) at each frame start. thus unused nibbles are always read as zero. rdrx (x = 0-7) receive data register x (80 h +x*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rd7 rd6 rd5 rd4 rh rh rh rh 1514131211109876543210 rd3 rd2 rd1 rd0 rh rh rh rh field bits type description rdy (y = 0-7) [4*y+3 :4*y] rh receive data nibble y rdy shows the nibble from the received frame that is sorted to this position. it can be selected by any of viewx.rdnpy (y = 0-7). by default all nibbles are sorted to rd0 as the reset value of view is 0x0000 0000 h . i.e. at the end of frame reception rd0 contains the last data nibble of the frame. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-43 v1.1, 2011-03 sent, v1.9 receive data view register viewx the receive data view registers viewx stores the nibble pointers. they determine the sequence in which the received data nibbles are presented to the host. this reduces the sw effort to sort the nibbles. the data nibble that is received first in the received frame is moved to the location given in register view.rdnp0, the second to view.rdnp1 and so on until view.rdnp7. if more than one view.rdnpx point to a certain location in rdr, the last one will overwrite the previous ones. example: two 12 bit values are transmitted. on e with highest significant nibble first and one with lowest significant nibble first. the frame looks like this: 456321 h . note that the 1 is received as first data nibble and the 4 comes in as last data nibble. the actual signal values are 0x123 h and 0x456 h . by using viewx this can be sorted out into two 16bit values by hw. in the example viewx would be set to: 73 654 012 h . 73 is a dummy value and is not regarded if not more than 6 nibbles are received in a frame. the register rdrx looks like this: 0x0456 0123 h to the host. in the example rdr nibbles 3 and 7 contain 0x0000 b as the receive buffer is always cleared (0x0000 0000 h ) before new data is received. if a frame contains more than eight nibbles and the sorting can not be specified statically, view can be set to e.g. 7654 3210 h . figure 25-22 functionality of view register sen t_ view.vsd 1 2 3 4 5 6 0 0 1 2 3 4 5 6 0 0 2 1 0 4 3 6 7 5 2 1 0 4 3 6 7 5 view rdr received frame nibble position nibble position nibble position 2 1 0 6 5 4 7 3 2 1 0 4 3 6 7 5 (0 = first received ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-44 v1.1, 2011-03 sent, v1.9 viewx (x = 0-7) receive data view register x (11c h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 rdnp7 0 rdnp6 0 rdnp5 0 rdnp4 rrwrrwrrwrrw 1514131211109876543210 0 rdnp3 0 rdnp2 0 rdnp1 0 rdnp0 rrwrrwrrwrrw field bits type description rdnpy (y = 0-7) [4*y+2 :4*y] rw receive data target nibble pointer y rdnpy points to the nibble in receive data register rdrx where the nibble y from the received frame is sorted to. nibble 0 is the first data nibble in the frame. it gets moved to the position defined in rdnp0. and on. 000 b nibble 0 selected 001 b nibble 1 selected ? b ? 111 b nibble 7 selected note: rdnpy must be written before first frame reception. all rdnpy must have different values. (higher rdnpy overwrite lower rdnpy.) 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-45 v1.1, 2011-03 sent, v1.9 25.2.6 spc control spc control registers scrx the spc control register scr contains data to be transmitted during the sync pulse of the data frames. it contains as well the trigger control bits required for sending nibbles from the sent module to the sensor / external sent device. the spc control register is used to control the trigger mode and time base of the spc channel transmission. data and the control bits are collected in this single register to ease transfer of multiple pulses in cases where dynamic switchi ng of the trigger condition is required. the spc control register is build to control single pulse transfers only. thus it is possible to change the control settings of an individual channel from pulse to pulse as it is required in spc mode ?bidirectional transmit?. here it might be considered useful to change trigger mode between mode 1 (immediately) and mode 2 (falling edge of next synchronization / calibratio n pulse with programmable delay). in addition repeating transfers with the same control settings are supported. for a pulse transfer to be initiated a synchronization signal can be sufficient and no further sw intervention is required. here the data can be changed (?id-selection? mode) or simply left constant (?sync? mode). only a hw trigger needs to be set up. in mode 0, spc is deactivated for this channel. a write access to scrx does not initiate an spc pulse transmission. all state transmitter machines are initialized. in mode 1, an spc pulse is sent, each time spc control register scrx is written to. if a transfer is ongoing, the channel waits automatically until the internal transmission register is ready. transmit buffer underflow bit tbix is set after data has been completely transferred (plen exceeded) and no new data was written to scrx. after the data was transferred to the internal transmission register, interrupt tdix signals that a new value can be written. intstatx.tdix must be cleared by sw. independently from this interrupt pending bit, a new interrupt pulse is generated on each transfer of an spc pulse. this mode is important for back to back transfers of several nibbles as in bidirectional spc mode. in mode 2, an spc pulse is sent, each time the first falling edge of any synchronization / calibration pulse is received. in this mode, the programmable delay del is most useful. in spc mode ?bidirectional transmit? th is mode is useful to synchronize the transmission. tdix and tbix work as in mode 1. in mode 3, an spc pulse is sent (with current del and plen) after each external trigger event (defined by iocrx.ets). this is most useful in spc ?sync? mode. tdix and tbix work as in mode 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-46 v1.1, 2011-03 sent, v1.9 scrx (x = 0-7) spc control register x (118 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 trq bas e del trig plen rrwrwrwrw field bits type description plen [5:0] rw pulse length defines the length of the pulse in tick times. the time base is the measured tick time of the latest received frame if selected so by base. in case this measured tick time was invalid or not already available after enable of the channel, the nominal time base of the module is used. 000000 b pulse length is 0 ticks 000001 b pulse length is 1 tick ... ... 111111 b pulse length is 63 ticks www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-47 v1.1, 2011-03 sent, v1.9 trig [7:6] rw trigger source and mode selection selects the trigger source and mode. the internal sender state machine can be initialized by switching the channel off (trig is cleared) and on. this does not change the current register content. 00 b no pulse is generated, off when cleared, an ongoing transfer is stopped immediately and the transmit output is driven recessive. 01 b pulse starts immediately (no auto repetition) 10 b pulse starts each time the first falling edge of any synchronization / calibration pulse is received (auto repetition on next sync. / cal. pulses) 11 b pulse starts after each external trigger event. (auto repetition on next trigger) iocrx.ets selects the source of this event. del [13:8] rw delay length selects how long the spc pulse is delayed after the trigger condition. the time base is the measured tick time of the latest received frame if selected so by base. in case this measured tick time was invalid or not already available after enable of the channel, the nominal time base of the module is used. 000000 b pulse is not delayed 000001 b pulse is delayed by 1 tick ... ... 111111 b pulse is delayed by 63 ticks base 14 rw time base selects the pulse time base 0 b pulse is based on measured frequency of last synchronization/calibration pulse 1 b pulse is based on nominal frequency trq 15 r transfer request in progress while an spc pulse is being sent this bit is set. write access is ignored. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-48 v1.1, 2011-03 sent, v1.9 25.2.7 interrupt control registers intov interrupt overview register (14 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ipc 7 ipc 6 ipc 5 ipc 4 ipc 3 ipc 2 ipc 1 ipc 0 r rhrhrhrhrhrhrhrh field bits type description ipcy (y = 0-7) yrh interrupt pending on channel y if any interrupt requested flag is set for channel y in register intstaty and the referring interrupt is enabled in intenx then ipcy is set. it is automatically reset if all flags in intstaty are cleared for which the referring interrupt is enabled in intenx. 0 [31:8] r reserved read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-49 v1.1, 2011-03 sent, v1.9 interrupt status register the interrupt status register intstatx contains status bits that show the status of any interrupt of sent channel x. note: the bits are set independently from th e referring interrupt enable in register intenx. thus they can be used as status bits as well e.g. by a sw based on polling. intstatx (x = 0-7) interrupt status register x (120 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 0 0 scri sdi wsi crci nvi nni fdi fri tbi tdi rbi rdi rsi r r r rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description rsi 0rh receive success interrupt request flag this bit is set at the successfully received end of a frame. depending on bit rcrx.cdis this indicates a successful check of the crc. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.rsi. this bit can be set by bit intsetx.rsi. this bit is set independently from intenx. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-50 v1.1, 2011-03 sent, v1.9 rdi 1rh receive data inte rrupt request flag rdi is activated when a received frame is moved to a receive data register rdr. both rdi and rsi will be issued together in normal use cases where the frame size is not bigger than 8 nibbles and crc is correct or not checked (if rcrx.cdis is cleared). 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.rdi. this bit can be set by bit intsetx.rdi. this bit is set independently from intenx. rbi 2rh receive buffer ov erflow interrup t request flag this bit is set after a frame has been received while the old one was not read from rdrx. i.e. the kernel wants to set any of the two interrupts rsi and rdi and finds any of these two interrupts already set.the old data is overwritten by the new data. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit is not cleared by reading rdrx. this bit can be cleared by bit intclrx.rbi. this bit can be set by bit intsetx.rbi. this bit is set independently from intenx. tdi 3rh transfer data inte rrupt request flag this bit is set after the trigger condition was detected. data to be transferred has been moved internally. thus a new value can be written to scrx. this can be used for back to back transfers. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit is automatically cleared by writing scrx. this bit can be cleared by bit intclrx.tdi. this bit can be set by bit intsetx.tdi. this bit is set independently from intenx. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-51 v1.1, 2011-03 sent, v1.9 tbi 4rh transmit buffer underf low interrupt request flag this bit is set after data has been completely transferred (plen exceeded) and no new data was written to scrx. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit is not cleared by writing scrx. this bit can be cleared by bit intclrx.tbi. this bit can be set by bit intsetx.tbi. this bit is set independently from intenx. fri 5rh frequency range interrupt request flag this bit is set after a synchronization / calibration pulse was received that deviates more than +- 25% from the nominal value. the referring data is ignored. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.fri. this bit can be set by bit intsetx.fri. this bit is set independently from intenx. fdi 6rh frequency drift inte rrupt request flag this bit is set after a subsequent synchronization / calibration pulse was received that deviates more than 0.15625% (1/64) from its predecessor. (see rcr.cfc) 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.fdi. this bit can be set by bit intsetx.fri. this bit is set independently from intenx. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-52 v1.1, 2011-03 sent, v1.9 nni 7rh number of nibbles wrong request flag this bit is set after a more nibbles have been received than expected or a synchronization / calibration pulse is received too early thus too few nibbles have been received. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.nni. this bit can be set by bit intsetx.nni. this bit is set independently from intenx. nvi 8rh nibbles value out of range request flag this bit is set after a too long or too short nibble pulse has been received. i.e. value < 0 or value > 15. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.nvi. this bit can be set by bit intsetx.nvi. this bit is set independently from intenx. crci 9rh crc error request flag this bit is set if the crc fails. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.crci. this bit can be set by bit intsetx.crci. this bit is set independently from intenx. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-53 v1.1, 2011-03 sent, v1.9 wsi 10 rh wrong status and communication nibble error request flag in standard serial frame mode (rcr.esf is cleared), this bit is set if the status and communication nibble shows a start bit in a frame other than frame number n x 16. in extended serial frame mode this bit is without function. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.wsi. this bit can be set by bit intsetx.wsi. this bit is set independently from intenx. sdi 11 rh serial data receive interrupt request flag this bit is set after all serial data bits have been received via the status and communication nibble. depending on bit rcrx.scdis this indicates a successful check of the crc. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.sdi. this bit can be set by bit intsetx.sdi. this bit is set independently from intenx. scri 12 rh serial data crc error request flag this bit is set if the crc of the serial message fails. in extended serial message format, this includes a check of the serial communication nibble for correct 0 values of bit 3 in frames 7, 13 and 18. 0 b no interrupt was requested since this bit was cleared the last time 1 b an interrupt was requested since this bit was cleared the last time this bit can be cleared by bit intclrx.scri. this bit can be set by bit intsetx.scri. this bit is set independently from intenx. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-54 v1.1, 2011-03 sent, v1.9 0 [31:13] r reserved read as 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-55 v1.1, 2011-03 sent, v1.9 interrupt set register the interrupt set register intsetx contains control bits that trigger an interrupt pulse for any interrupt of sent channel x. intsetx (x = 0-7) interrupt set register x (124 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 0 0 scri sdi wsi crci nvi nni fdi fri tbi tdi rbi rdi rsi r r r wwwwwwwwwwwww field bits type description rsi 0w set interrupt request flag rsi setting this bit set bit intstatx.rsi. clearing this bit has no effect. reading this bit re turns always zero. rdi 1w set interrupt request flag rdi setting this bit set bit intstatx.rdi. clearing this bit has no effect. reading this bit re turns always zero. rbi 2w set interrupt request flag rbi setting this bit set bit intstatx.rbi. clearing this bit has no effect. reading this bit re turns always zero. tdi 3w set interrupt request flag tdi setting this bit set bit intstatx.tdi. clearing this bit has no effect. reading this bit re turns always zero. tbi 4w set interrupt request flag tbi setting this bit set bit intstatx.tbi. clearing this bit has no effect. reading this bit re turns always zero. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-56 v1.1, 2011-03 sent, v1.9 fri 5w set interrupt request flag fri setting this bit set bit intstatx.fri. clearing this bit has no effect. reading this bit re turns always zero. fdi 6w set interrupt request flag fdi setting this bit set bit intstatx.fdi. clearing this bit has no effect. reading this bit re turns always zero. nni 7w set interrupt request flag nni setting this bit set bit intstatx.nni. clearing this bit has no effect. reading this bit re turns always zero. nvi 8w set interrupt request flag nvi setting this bit set bit intstatx.nvi. clearing this bit has no effect. reading this bit re turns always zero. crci 9w set interrupt request flag crci setting this bit set bit intstatx.crci. clearing this bit has no effect. reading this bit re turns always zero. wsi 10 w set interrupt request flag wsi setting this bit set bit intstatx.wsi. clearing this bit has no effect. reading this bit re turns always zero. sdi 11 w set interrupt request flag sdi setting this bit set bit intstatx.sdi. clearing this bit has no effect. reading this bit re turns always zero. scri 12 w set interrupt request flag scri setting this bit set bit intstatx.scri. clearing this bit has no effect. reading this bit re turns always zero. 0 [31:13] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-57 v1.1, 2011-03 sent, v1.9 interrupt cl ear register the interrupt clear register intclrx contains control bits that clear the status of any interrupt of sent channel x. intclrx (x = 0-7) interrupt clear register x (128 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 0 0 scri sdi wsi crci nvi nni fdi fri tbi tdi rbi rdi rsi r r r wwwwwwwwwwwww field bits type description rsi 0w clear interrupt request flag rsi setting this bit clears bit intstatx.rsi. clearing this bit has no effect. reading this bit re turns always zero. rdi 1w clear interrupt request flag rdi setting this bit clears bit intstatx.rdi. clearing this bit has no effect. reading this bit re turns always zero. rbi 2w clear interrupt request flag rbi setting this bit clears bit intstatx.rbi. clearing this bit has no effect. reading this bit re turns always zero. tdi 3w clear interrupt request flag tdi setting this bit clears bit intstatx.tdi. clearing this bit has no effect. reading this bit re turns always zero. tbi 4w clear interrupt request flag tbi setting this bit clears bit intstatx.tbi. clearing this bit has no effect. reading this bit re turns always zero. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-58 v1.1, 2011-03 sent, v1.9 fri 5w clear interrupt request flag fri setting this bit clears bit intstatx.fri. clearing this bit has no effect. reading this bit re turns always zero. fdi 6w clear interrupt request flag fdi setting this bit clears bit intstatx.fdi. clearing this bit has no effect. reading this bit re turns always zero. nni 7w clear interrupt request flag nmi setting this bit clears bit intstatx.nmi. clearing this bit has no effect. reading this bit re turns always zero. nvi 8w clear interrupt request flag nvi setting this bit clears bit intstatx.nvi. clearing this bit has no effect. reading this bit re turns always zero. crci 9w clear interrupt request flag crci setting this bit clears bit intstatx.crci. clearing this bit has no effect. reading this bit re turns always zero. wsi 10 w clear interrupt request flag wsi setting this bit clears bit intstatx.wsi. clearing this bit has no effect. reading this bit re turns always zero. sdi 11 w clear interrupt request flag sdi setting this bit clears bit intstatx.sdi. clearing this bit has no effect. reading this bit re turns always zero. scri 12 w clear interrupt request flag scri setting this bit clears bit intstatx.scri. clearing this bit has no effect. reading this bit re turns always zero. 0 [31:13] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-59 v1.1, 2011-03 sent, v1.9 interrupt enable register the interrupt enable register intenx contains control bits that enable the interrupt source of any interrupt of sent channel x. note: the interrupt status bits in regist er intstatx are set independently from the interrupt enable in register intenx. intenx (x = 0-7) interrupt enable register x (12c h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 scri sdi wsi crci nvi nni fdi fri tbi tdi rbi rdi rsi r rwrwrwrwrwrwrwrwrwrwrwrwrw field bits type description rsi 0rw enable interrupt request rsi 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source rdi 1rw enable interrupt request rdi 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source rbi 2rw enable interrupt request rbi 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-60 v1.1, 2011-03 sent, v1.9 tdi 3rw enable interrupt request tdi 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source tbi 4rw enable interrupt request tbi 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source fri 5rw enable interrupt request fri 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source fdi 6rw enable interrupt request fdi 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source nni 7rw enable interrupt request nni 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source nvi 8rw enable interrupt request nvi 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source crci 9rw enable interrupt request crci 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-61 v1.1, 2011-03 sent, v1.9 wsi 10 rw enable interrupt request wsi 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source sdi 11 rw enable interrupt request sdi 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source scri 12 rw enable interrupt request scri 0 b no interrupt request can be generated for this source 1 b an interrupt request can be generated for this source 0 [31:13] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-62 v1.1, 2011-03 sent, v1.9 interrupt node pointer register the interrupt node pointer register inpx contains the node pointers of sent channel x. note: node pointer erri is one single node pointer for the following error interrupts: ?fri ?fdi ? nni ?nvi ? crci ?wsi ? scri inpx (x = 0-7) interrupt node pointer register x (130 h +40 h *x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 sdi erri tbi r rwrwrw 1514131211109876543210 tdi rbi rdi rsi rw rw rw rw field bits type description rsi [3:0] rw interrupt node pointe r for interrupt rsi this bit field defines the interrupt node, that is requested due to the set condition for bit intstatx.rsi (if enabled by bit intenx.rsi). 0000 b interrupt node 0 is selected 0001 b interrupt node 1 is selected 0010 b interrupt node 2 is selected 0011 b interrupt node 3 is selected 0100 b trigger output trigo 0 is selected 0101 b trigger output trigo 1 is selected ... ... 1101 b trigger output trigo 7 is selected 1110 b reserved ... ... 1111 b reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-63 v1.1, 2011-03 sent, v1.9 rdi [7:4] rw interrupt node pointer for interrupt rdi this bit field defines the interrupt node, that is requested due to the set condition for bit intstatx.rdi (if enabled by bit intenx.rdi). for bit field definition, see rsi. rbi [11:8] rw interrupt node pointer for interrupt rbi this bit field defines the interrupt node, that is requested due to the set condition for bit intstatx.rbi (if enabled by bit intenx.rbi). for bit field definition, see rsi. tdi [15:12] rw interrupt node pointe r for interrupt tdi this bit field defines the interrupt node, that is requested due to the set condition for bit intstatx.tdi (if enabled by bit intenx.tdi). for bit field definition, see rsi. tbi [19:16] rw interrupt node pointe r for interrupt tbi this bit field defines the interrupt node, that is requested due to the set condition for bit intstatx.tbi (if enabled by bit intenx.tbi). for bit field definition, see rsi. erri [23:20] rw interrupt node pointer for interrupt fri, fdi, nni, nvi, crci, wsi, scri this bit field defines the interrupt node, that is requested due to the set condition for bit intstatx.fri (if enabled by bit intenx.fri) or intstatx.fdi (if enabled by bit intenx.fdi) or intstatx.nni (if enabled by bit intenx.nni) or intstatx.nvi (if enabled by bit intenx.nvi) or intstatx.crci (if enabled by bit intenx.crci) or intstatx.wsi (if enabled by bit intenx.wsi) or intstatx.scri (if enabled by bit intenx.scri) for bit field definition, see rsi. sdi [27:24] rw interrupt node pointe r for interrupt sdi this bit field defines the interrupt node, that is requested due to the set condition for bit intstatx.sdi (if enabled by bit intenx.sdi). for bit field definition, see rsi. 0 [31:28] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-64 v1.1, 2011-03 sent, v1.9 25.3 sent module implementation this section describes the sent module interface as it is implemented in the TC1798. it especially covers clock control, port and on-chip connections, interrupt control, and address decoding. 25.3.1 interface connecti ons of the sent module figure 25-23 shows the TC1798-specific implementation details and interconnections of the sent module. the sent module is supplied with a separate clock control, address decoding, and interrupt control logic. the 4 modules? service request outputs are connected with interrupt nodes, and each of the 8 channels with the dma controller. outputs of the gpta module are connected to the 8 timer inputs. the serial data inputs of the receive channels of the sent module as well as the spc outputs (spcn) are connected to gpio lines . if spc outputs are used, they are usually mapped to the same port pin like the referring sent data input line as this minimizes the pin count requirement. figure 25-23 sent module implem entation and in terconnections dmax sent_implemtation_overview.vsd address decoder interrupt control sent module (kernel ) sr0 channel 0 port control . . . clock control st0_0 spc0 . . . trigo 0 . . . gpta trig0 trign . . . . . . f sent f spb sr1 sr2 sr3 st0_1 st0_2 st0_3 spc0_0 spc0_1 spc0_2 spc0_3 hw_dir_0 st0_0 st0_1 st0_2 st0_3 channel n stn_0 spcn stn_1 stn_2 stn_3 spcn_0 spcn_1 spcn_2 spcn_3 hw_dir_0 stn_0 stn_1 stn_2 stn_3 trigo n www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-65 v1.1, 2011-03 sent, v1.9 25.3.2 on-chip connections this section describes the on-chip connections of the sent module. 25.3.2.1 interrupt and dma c ontroller service requests the module has 4 service request nodes connecting it to the interrupt system. the trigger outputs of the sent module are connected as dma request input to the dma controller. the dma request lines are connected to the dma controller as shown in table 25-3 . table 25-3 service request lines of sent inp value request line connected to description 0000 b sr0 sent_src0 sent service request node 0 0001 b sr1 sent_src1 sent service request node 1 0010 b sr2 sent_src2 sent service request node 2 0011 b sr3 sent_src3 sent service request node 3 0100 b trigo0 ch00_reqi02 sdma channel 00 request input 2 0101 b trigo1 ch01_reqi02 sdma channel 01 request input 2 0110 b trigo2 ch02_reqi02 sdma channel 02 request input 2 0111 b trigo3 ch03_reqi02 sdma channel 03 request input 2 1000 b trigo4 ch04_reqi02 sdma channel 04 request input 2 1001 b trigo5 ch05_reqi02 sdma channel 05 request input 2 1010 b trigo6 ch06_reqi02 sdma channel 06 request input 2 1011 b trigo7 ch07_reqi02 sdma channel 07 request input 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-66 v1.1, 2011-03 sent, v1.9 25.3.2.2 trigger inputs the module has 8 sent channels and the same number of trigger inputs which can be randomly chosen by programm ing iocrx.ets. the trigger inputs (trig[7:0]) of the sent module are connected to the gpta as shown in table 25-4 . table 25-4 trigger input lines of sent request line connec ted to description trig0 trig0 gpta trigger line trig0 trig1 trig1 gpta trigger line trig1 trig2 trig2 gpta trigger line trig2 trig3 trig3 gpta trigger line trig3 trig4 trig4 gpta trigger line trig4 trig5 trig5 gpta trigger line trig5 trig6 trig6 gpta trigger line trig6 trig7 trig7 gpta trigger line trig7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-67 v1.1, 2011-03 sent, v1.9 25.3.3 sent module-related external registers the registers listed in figure 25-24 are not included in the sent module kernel but must be programmed for proper operation of the sent module. figure 25-24 sent implementation-specific special function registers 25.3.3.1 port control the sent input channels are overlaid with standard adc channels as they are replacing former analog signals. each channel is connected to two adc channels that can be chosen alternatively. in addition each channel is connected to general purpose i//o lines as well. each channel is connected to two different general purpose i/o lines that can be chosen alternatively. the selection from on of these 4 alternatives is done by application sw by programming sent_iocrx.alti respectively. the spc output lines are connected to the same i/o ports as the referring input channel. the adc channels do not provide output functionality. the spc i/o ports are controlled in the port logic (see also figure 25-23 ). the following port control operations and selections must be executed for these i/o lines: ? input/output function selection (port iocr registers) ? pad driver characteristics selection for the outputs (port pdr registers) input/output function selection sent can be used in three different ways: ? adc input (dedicated for adc) overlaid with sent digital input and no output option on this pin. ? sent configured digital i/o lines (open drain, no push/pull, uses sdir, single pin hardware direction control hw_dir, sdir is controlled by the data value: 0 = active out, 1 = passive/open drain, input) ? standard general purpose input/output function on two lines for each channel (input on adc alternative 1 or 2, or on i/o port alternative 1 while the output is chosen to be on i/o ports alternative 2. sent_implemtation_external_sfrs.vsd sent_srcn interrupt registers port registers clock control registers sent_ clc px_iocry px_iocry px_pdr n=0?3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-68 v1.1, 2011-03 sent, v1.9 the sent module overlays dedicated analog to digital converter (adc) pins as digital input port. note: note that only the adc input pins ar e 5v capable while the standard digital i/o provides 3.3v inputs. the sent module can be configured to use input/output ports configured for use with sent. these control settings for the port pi ns differ from the standard general purpose i/o lines in so far as ? they are controlled by the sent module output data via their hw_dir line ? they are configured to use no push/pull devices and to work in open drain mode if the output function is selected by the hw_dir line of the port the sent module can be configured to use standard (push pull) general purpose i/o lines as well. different port pins can be selected for input and for output. this allows the use of external transceiver devices. the port input/output control registers contain the bit fields that select the digital output and input driver characteristics such as port direction (input/output) with alternate output selection, pull-up/down devices, and open-drai n selections. the i/o lines for the sent module are controlled by the port input/output control registers shown below. table 25-5 shows an overview how bits and bit fields must be programmed for the required i/o functionality of the sent i/o lines. table 25-5 sent i/o control selection and setup sent channel port lines input select register input/output control register bits i/ o 0 st0/an8 sent_iocr0.alti = 0000 b p17_pdisc.pdis0 = 0 b i st0/an36 sent_iocr0.alti = 0001 b p17_pdisc.pdis8 = 0 b i st0/p8.0 sent_iocr0.alti = 0010 b p8_iocr0.pc0 = 0xxx b i st0/p9.9 sent_iocr0.alti = 0011 b p9_iocr8.pc9 = 0xxx b i st0/p9.9 not applicable p9_iocr8.pc9 = 1x10 b o 1 st1/an9 sent_iocr1.alti = 0000 b p17_pdisc.pdis1 = 0 b i st1/an37 sent_iocr1.alti = 0001 b p17_pdisc.pdis9 = 0 b i st1/p8.1 sent_iocr1.alti = 0010 b p8_iocr0.pc1 = 0xxx b i st1/p9.5 sent_iocr1.alti = 0011 b p9_iocr4.pc5 = 0xxx b i st1/p8.1 not applicable p8_iocr0.pc1 = 1x11 b o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-69 v1.1, 2011-03 sent, v1.9 2 st2/an10 sent_iocr2.alti = 0000 b p17_pdisc.pdis2 = 0 b i st2/an38 sent_iocr2.alti = 0001 b p17_pdisc.pdis10 = 0 b i st2/p8.2 sent_iocr2.alti = 0010 b p8_iocr0.pc2 = 0xxx b i st2/p9.11 sent_iocr2.alti = 0011 b p9_iocr8.pc11 = 0xxx b i st2/p9.11 not applicable p9_iocr8.pc11 = 1x10 b o 3 st3/an11 sent_iocr3.alti = 0000 b p17_pdisc.pdis3 = 0 b i st3/an39 sent_iocr3.alti = 0001 b p17_pdisc.pdis11 = 0 b i st3/p8.3 sent_iocr3.alti = 0010 b p8_iocr0.pc3 = 0xxx b i st3/p9.6 sent_iocr3.alti = 0011 b p9_iocr4.pc6 = 0xxx b i st3/p9.6 not applicable p9_iocr4.pc6 = 1x10 b o 4 st4/an12 sent_iocr4.alti = 0000 b p17_pdisc.pdis4 = 0 b i st4/an40 sent_iocr4.alti = 0001 b p17_pdisc.pdis12 = 0 b i st4/p8.4 sent_iocr4.alti = 0010 b p8_iocr4.pc4 = 0xxx b i st4/p9.7 sent_iocr4.alti = 0011 b p9_iocr4.pc7 = 0xxx b i st4/p9.7 not applicable p9_iocr4.pc7 = 1x10 b o 5 st5/an13 sent_iocr05alti = 0000 b p17_pdisc.pdis5 = 0 b i st5/an41 sent_iocr5.alti = 0001 b p17_pdisc.pdis13 = 0 b i st5/p8.5 sent_iocr5.alti = 0010 b p8_iocr4.pc5 = 0xxx b i st5/p9.12 sent_iocr5.alti = 0011 b p9_iocr12.pc12 = 0xxx b i st5/p9.12 not applicable p9_iocr12.pc12 = 1x10 b o 6 st6/an14 sent_iocr6.alti = 0000 b p17_pdisc.pdis6 = 0 b i st6/an42 sent_iocr6.alti = 0001 b p17_pdisc.pdis14 = 0 b i st6/p8.6 sent_iocr6.alti = 0010 b p8_iocr4.pc6 = 0xxx b i st6/p9.8 sent_iocr6.alti = 0011 b p9_iocr8.pc8 = 0xxx b i st6/p9.8 not applicable p9_iocr8.pc8 = 1x10 b o table 25-5 sent i/o control selection and setup (cont?d) sent channel port lines input select register input/output control register bits i/ o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-70 v1.1, 2011-03 sent, v1.9 7 st7/an15 sent_iocr7.alti = 0000 b p17_pdisc.pdis7 = 0 b i st7/an43 sent_iocr7.alti = 0001 b p17_pdisc.pdis15 = 0 b i st7/p8.7 sent_iocr7.alti = 0010 b p8_iocr4.pc7 = 0xxx b i st7/p9.10 sent_iocr7.alti = 0011 b p9_iocr8.pc10 = 0xxx b i st7/p9.10 not applicable p9_iocr8.pc10 = 1x10 b o table 25-5 sent i/o control selection and setup (cont?d) sent channel port lines input select register input/output control register bits i/ o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-71 v1.1, 2011-03 sent, v1.9 25.3.3.2 service request control registers the service request co ntrol registers contain the system specific service control bits. src0 service request control 0 register (9fc h ) reset value: 0000 0000 h src1 service request control 1 register (9f8 h ) reset value: 0000 0000 h src2 service request control 2 register (9f4 h ) reset value: 0000 0000 h src3 service request control 3 register (9f0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number 00 h service request is never serviced 01 h service request is on lowest priority ... ff h service request is on highest priority tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp request is initiated sre 12 rw service request enable 0 b service request is disabled 1 b service request is enabled srr 13 rh service request flag 0 b no service request is pending 1 b a service request is pending www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-72 v1.1, 2011-03 sent, v1.9 clrr 14 w request clear bit clrr is required to clear srr. 0 b no action 1 b clear srr; bit value is not stored; read always returns 0; no action if setr is set also. setr 15 w request set bit setr is required to set srr. 0 b no action 1 b set srr; bit value is not stored; read always returns 0; no action if clrr is set also. 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-73 v1.1, 2011-03 sent, v1.9 25.3.4 sent register address map the sent register map shown in figure 25-25 . figure 25-25 sent register map sent_address_8channels.vsd reserved +014 h 000 h +080 h +0a0 h +100 h general module control receive data reserved communication controller control registers reserved interrupt service request control registers rdr2 rdr1 rdr0 id intov clc rdr3 rdr4 rdr5 rdr6 rdr7 fdr src3 src2 src1 src0 +9 ff h rcrx scrx intstatx intsetx iocrx intclrx intenx inpx rsrx cpdrx cfdrx viewx sdsx +9 f0 h +330 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-74 v1.1, 2011-03 sent, v1.9 25.4 revision history this users manual is based on: sae standard ?sent revision j2716 feb2008 rev. 3 2009-06-24 ?. table 25-6 revision history version number changes to previous version rev_0.1d first draft (bullet points ++) rev_0.2d second draft (bullet points ++) rev_0.3d first review version rev_0.4d ? rcrx.nint removed as unnecessary fifo support ? spelling checked ? renamed intnp to inp (request de) ? one common error node pointer in inp for fri, fdi, nni, nvi, crci, wsi, scri (reduce de effort) ? interrupt node pointer in inpx increased from 2 bit to 4 bit ? renamed pval to pdiv in register cpdrx ? rcrx.asp ?additional sync/cal pulse expected? deleted, not required ? rcrx.ace ?alternate crc mode? added, request customer ? cleanup register scr ? isr0 (input select register) deleted ? altin and filter depth moved to iocrx ? scrx.del moved to sdrx ? scrx deleted, base and trq moved to sdr ? restructured chapters (interrupts after functional registers, implementation chapter cleaned up) ? simplified baud rate generation (fdtick removed) rev_0.5d ? clean up glitch filter chapter ? detailed baud rate generation ? added address overview table www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-75 v1.1, 2011-03 sent, v1.9 rev_0.6d ? channel fractional divider with variable divider instead of variable dividend ? glitch filter based on f_pdiv and no longer on f_sent ? glitch detection added ? pre divider = pdiv and no longer pdiv + 1 ? compressed address overview table ? interrupt generation updated figure 25-20 ?interrupt generation? on page 25-21 ? trigger outputs renamed (rsi and sdi, no more trigo) and completed ? rdi simplified - now independent from rsi ? ets wording corrected ? intov now only updated for enabled interrupts (before: any change) ? renamed ?spc data register sdr? to ?spc control register scr?, it contains both data and control information ? tdi wording optimized ? external registers overview corrected ? kscfg removed rev_1.0d first complete revision (to be done) rev_1.1d ? moved base address to f032_1000 - f032_19ff (10x256 bytes) ? serial message id added. sdsx.scn moved to [19:16], sdsx.scrc moved to [15:12], sdsx.mid placed at [11:8]. ? rsi and tdi as trigger outputs replaced by 8 trigger outputs programmable in the inps. ? implemented first port mapping proposal from product rev_1.2 ? added hint to rcr.cen that fsms are initialized during enable ? port mapping updated to latest changes of cw08/47 table 25-6 revision history (cont?d) version number changes to previous version www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-76 v1.1, 2011-03 sent, v1.9 rev_1.3 ? fixed intenx bit descriptions: all bits are rw and high active (typo) ? added to feature list: ?programmable nibble sorting to support lsn or hsn first and relief cpu? (was missing) ? sent_fdr.dm[1:0] added description of all 4 states of this bit field. (same as system level) ? iocr.depth corrected f sent sent to f pdiv (longer glitch tolerance) ? add freeze-disable bit [10] to sent_fdr (system requirement) ? pre divider factor is (pdiv + 1) and no longer pdiv (ease design) ? resulting channel fractional divider is (div + 1) and no longer div ? add iocr.txm, rxm and trm moni tor bits (ease of validation) ? rdrx added explanation: unused nibbles are shown as '0' (for clarity) ? rdi and rsi: read clears these bits not (request from ae) ? renamed transmit buffer overflow to under-flow with change to respective functionality (data completely transmitted without new write) ? rcrx.cfc: wording improved and details added rev_1.4 ? added column access modes to register table ? updated figure 25-2 , figure 25-3 , figure 25-4 (beautification) ? the clock signal f pdiv of a channel must always be at least 20 (old value 10) times the nominal tick frequency, to cater for worst case. ? inpx: added reserved values ?corrected figure 25-20 , no more separate dma trigo lines. ? rcrx, viewx and cfdrx reset value corrected to 0x0000 0000 hex ? added explanations to rdrx and viewx ? ai00050230 - sent_fdr register located at ?unusual? address: moved clc to offset 0x0ch for consistency with other modules ? reduced ets to 3 bit and alti to 2 bit width ? ?zero nibble insertion in crc? covered. see rcr.crz. ? utp ai00050205 - ?extended serial frame? covered. added description of extended serial frame. sds.scn moved to rsr.scn (allows for an aligned representation of id and data as well as a fixed position for scn) sds.sd, sds.mid, sds.scrc enlarged (to 16, 8 and 6 bit width) sds.con and rcr.esf added ? resulting channel fractional divider is div and no longer (div + 1) table 25-6 revision history (cont?d) version number changes to previous version www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-77 v1.1, 2011-03 sent, v1.9 rev_1.5 ? corrected tbix description on page 50. ? scr.trq corrected (deleted ?reads back zero?) ? added hint to definition of alternate crc mode (ace) ? detailed rbi behavior. it is set if kernel wants to set rsi or rdi and finds rsi or rdi already set. ? detailed that rcr.cen resets the receiver state machines only while scr.trig resets the sender state machines. ? rcr.wsi updated wrt. the special case ?extended serial frame? (2009- 06-24) ? instat.scri detailed wrt.: crc che ck must include check for correct 0 values in extended serial frame format (2009-06-24) ? message tick time prolonged to 90 s according to new standard (2009-06-24) ? rcr.cfc (successive calibration pulse detection) adopted to new standard. (2009-06-24) ? updated intstat.fdi wrt.: new additional error diagnostics (total frame length variation and ration calibration pulse/total frame length) in new standard. (2009-06-24) rev_1.6 ? added bit rcr.ide (ignore drift error) to cater for rare triggers by spc. ? removed sv protection from sent_fdr. ? view.rdnp must be set before reception. ? scr.trq spec? ed not active from request to pulse start. ? added ?alternative crc? spec from tle4998 . ? changed wording for rbi. ? new additional error diagnostics (total frame length variation and ration calibration pulse/total frame length) removed. rev_1.7 ? added note: rcr.cen must be cleared before changing cpdr.pdiv or cfdr.div. ? scri typo: frame 8, not 7 contains a zero value. ? chapter 25.1.5 typo corrected: replaced f sent with f fracdiv ? chapter 25.1.3.1 note added on rcr.crz. ? added hint to chapter ?module clock generation? for details on clc. ? updated port connections and trigger output connections rev_1.8 ? changed functionality of view. ? changed functionality of wsi. table 25-6 revision history (cont?d) version number changes to previous version www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 single edge nibble transmission (sent) users manual 25-78 v1.1, 2011-03 sent, v1.9 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-1 v1.1, 2011-03 e-ray, v3.12 eray_overview_fpi.vsd address decoder ir eray module (kernel ) channel a channel b port control external request unit stop watch trigger select stpw mt external clock output f mt rxdb txdb txenb rxda txda txena clock control f c l c_er ay f sc l k f pl l_ er ay f fpi port x.y 10 extclk0 26 flexray? protocol controller (e-ray) the e-ray ip-module performs communication according to the flexray? 1) protocol specification v2.1. with maximum specified clock the bitrate can be programmed to values up to 10 mbit/s. additional bus driver (bd) hardware is required for connection to the physical layer. 26.1 e-ray kernel description figure 26-1 shows a global view of the e-ray interface. figure 26-1 general block diag ram of the e-ray interface the e-ray module communicates with the external world via three i/o lines each channel. the rxdax and rxdbx lines are the receive data input signals, txda and 1) infineon ? , infineon technologies ? , are trademarks of infineon technologies ag. flexray? is a trademark of flexray consortium. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-2 v1.1, 2011-03 e-ray, v3.12 txdb lines are the transmit output signals, txena and txenb the transmit enable signals. clock control, address decoding, and servic e request control are managed outside the e-ray module kernel. 26.2 overview for communication on a flexray? network, individual message buffers with up to 254 data byte are configurable. the message storage consists of a single-ported message ram that holds up to 128 message buffers. all functions concerning the handling of messages are implemented in the message handler. those functions are the acceptance filtering, the transfer of messages between the two flexray? channel protocol controllers and the message ram, maintaining the transmission schedule as well as providing message status information. the register set of the e-ray ip-module can be accessed directly by an external host via the module?s host interface. these regist ers are used to control/configure/monitor the flexray? channel protocol controllers, message handler, global time unit, system universal control, frame and symbol processing, network management, service request control, and to access the message ram via input / output buffer. the e-ray ip-module supports the following features: ? conformance with flexray? protocol specification v2.1 ? data rates of up to 10 mbit/s on each channel ? up to 128 message buffers configurable ? 8 kbyte of message ram for storage of e.g. 128 message buffers with max. 48 byte data field or up to 30 message buffers with 254 byte data sections ? configuration of message buffers with different payload lengths possible ? one configurable receive fifo ? each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive fifo ? host access to message buffers via input and output buffer. input buffer: holds message to be transferred to the message ram output buffer: holds message read from the message ram ? filtering for slot counter, cycle counter, and channel ? maskable module service requests ? network management supported ? four service request lines ? automatic delayed read access to output command request register (obcr) if a data transfer from message ram to output shadow buffer (initiated by a previous write access to the obcr) is ongoing. ? automatic delayed read access to input command request register (ibcr) if a data transfer from input shadow buffer to me ssage ram to (initiated by a previous write access to the ibcr) is ongoing. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-3 v1.1, 2011-03 e-ray, v3.12 ? four input buffer for building up transmission frames in parallel. ? flag indicating which input buffer is currently accessible by the host. 26.3 definitions flexray? frame: header segment + payload segment message buffer: header section + data section message ram: header partition + data partition data frame: flexray? frame that is not a null frame 26.4 block diagram the e-ray is built up by the following main submodules: figure 26-2 e-ray block diagram customer host interface (cif) connects the fpi bus to the e-ray ip-module via the generic host interface. generic host interface (gif) the e-ray ip-module is provided with an 8/16 /32-bit generic host interface prepared for the connection to a wide range of customer-specific hosts. configuration registers, status registers, and service request regist ers are attached to the respective blocks and can be accessed via the generic host interface. generic host if message handler rxda tdaa control data addr control prt a prt b service nem message ram tbf a gtu tbf b suc ibf obf physical layer crossbar switch rxdb txdb smif customer host if int fsp request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-4 v1.1, 2011-03 e-ray, v3.12 input buffer (ibf) for write access to the message buffers configured in the message ram, the host can write the header and data section for a specific message buffer to the input buffer. the message handler then transfers the data from the input buffer to the selected message buffer in the message ram. because the input buffer (ibf) scheme does only allow to write the entire message frame, not only parts of it, the number of ib f has been increased from originally 2 to 4. this enables to fill the buffer partly and at the end request transfer into message ram. therefore 2 extra bits allow to switch betwe en the two banks of ibf and one status bit signals the ibf currently active for host writes. output buffer (obf) for read access to a message buffer configured in the message ram the message handler transfers the selected message buffer to the output buffer. after the transfer has completed, the host can read the header and data section of the transferred message buffer from the output buffer. message handler (mhd) the e-ray message handler controls data transfers between the following components: ? input / output buffer and message ram ? transient buffer rams of the two flexray? protocol controllers and message ram message ram (mram) the message ram consists of a single-ported ram that stores up to 128 flexray? message buffers together with the related configuration data (header and data partition). transient buffer ram (tbf 1/2) stores the data section of two complete messages. flexray? channel protocol controller (prt a/b) the flexray? channel protocol controllers consist of shift register and flexray? protocol fsm. they are connected to t he transient buffer rams for intermediate message storage and to the physical layer via bus driver bd. they perform the following functionality: ? control and check of bit timing ? reception and transmission of flexray? frames and symbols ? check of header crc ? generation / check of frame crc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-5 v1.1, 2011-03 e-ray, v3.12 ? interfacing to bus driver the flexray? channel protocol controllers have interfaces to: ? physical layer (bus driver) ? transient buffer ram ? message handler ? global time unit ? system universal control ? frame and symbol processing ? network management ? service request control global time unit (gtu) the global time unit performs the following functions: ? generation of microtick ? generation of macrotick ? fault tolerant clock synchronization by ftm algorithm ? rate correction ? offset correction ? cycle counter ? timing control of static segment ? timing control of dynamic segment (minislotting) ? support of external clock correction system universal control (suc) the system universal control controls the following functions: ? configuration ?wakeup ?startup ? normal operation ? passive operation ? monitor mode frame and symbol processing (fsp) the frame and symbol processing controls the following functions: ? checks the correct timing of frames and symbols ? tests the syntactical and semantical correctness of received frames ? sets the slot status flags network management (nem) handles of the network management vector www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-6 v1.1, 2011-03 e-ray, v3.12 service request control (int) the service request controller performs the following functions: ? provides error and status service request flags ? enables and disables service request sources ? assignment of service request sources to one of the two module service request lines ? enables and disables module service request lines ? manages the two service request timers ? stop watch time capturing 26.5 programmer?s model the programmer?s model of the e-ray module follows the principle of memory mapped peripheral. some portion of the memory follows the principle of segmented/paged memory organization. 26.5.1 register map the e-ray module allocates an address space of 4 kbyte (000 h to ffff h ). the registers are organized as 32-bit registers. 8/16-bit accesses are also supported. host access to the message ram is done via the input and output buffers. they buffer data to be transferred to and from the message ram under control of the message handler, avoiding conflicts between host accesses and message reception / transmission. addresses 0004 h - 000f h ,03c8 h - 03ec h and 0800 h - 0fff h are reserved for customer specific purposes. all functions related to these addresses are located in the customer host interface. the test registers located on address 0010 h and 0014 h are writable only under the conditions described in ?special registers? on page 26-23 . the assignment of the message buffers is done according to the scheme shown in table 26-1 below. the number n of available message buffers depends on the payload length of the configured message buffers. the maximum number of message buffers is 128. the maximum payload length supported is 254 byte. the message buffers are separated into three consecutive groups: ? static buffers: transmit / receive buffers assigned to static segment ? static and dynamic buffers: transmit / receive buffers assigned to static or dynamic segment ? fifo- receive fifo the message buffer separation configuration can be changed only in ?default_config? or ?config? state only by programming the message ram configuration register (mrc). the first group starts with message buffer 0 and consists of static message buffers only. message buffer 0 is dedicated to hold the st artup / sync frame or the single slot frame, if node transmit one, as configured by succ1.txst, succ1.txsy, and succ1.tsm www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-7 v1.1, 2011-03 e-ray, v3.12 in the suc configuration register 1 (succ1). in addition, message buffer 1 may be used for sync frame transmission in case that sync frames or single-slot frames should have different payloads on the two channels. in this case bit mrc.splm has to be programmed to 1 and message buffers 0 a nd 1 have to be configured with the key slot id and can be (re)configured in ?def ault_config? or ?config? state only. the second group consists of message buffers assigned to the static or to the dynamic segment. message buffers belonging to this group may be reconfigured during run time from dynamic to static or vice versa depending on the state of mrc.sec. the message buffers belonging to the third group are concatenated to a single receive fifo. table 26-1 assignment of message buffers message buffer 0 ? static buffers message buffer 1 ? ? static + dynamic buffers ? fdb ? fifo ? ffb message buffer n-1 message buffer n ? lcb www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-8 v1.1, 2011-03 e-ray, v3.12 26.5.2 e-ray kernel registers this chapter describes all registers of the e-ray kernel. table 26-2 registers address space e-ray kernel register address space module base address end address note eray f0010000 h f0010fff h 4kbyte table 26-3 registers overvi ewe-ray kernel registers register short name register long name offset addr. 1) access mode reset class description see read write customer registers eray_clc e-ray clock control register 0000 h sv,u sv,e 3 page 26-268 cust1 busy and input buffer control register 0004 h sv,u sv,u 3 page 26-17 id module identification register 0008 h sv,u sv,u 3 page 26-16 cust3 customer interface timeout counter 000c h sv,u sv,u 3 page 26-20 special registers test1 test register 1 0010 h sv,u sv,u 3 page 26-23 test2 test register 2 0014 h sv,u sv,u 3 page 26-28 - reserved 0018 h nbe nbe - - lck lock register 001c h sv,u sv,u 3 page 26-39 service request registers eir error service request register 0020 h sv,u sv,u 3 page 26-41 sir status service request register 0024 h sv,u sv,u 3 page 26-47 eils error service request line select 0028 h sv,u sv,u 3 page 26-52 sils status service request line select 002c h sv,u sv,u 3 page 26-56 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-9 v1.1, 2011-03 e-ray, v3.12 eies error service request enable set 0030 h sv,u sv,u 3 page 26-60 eier error service request enable reset 0034 h sv,u sv,u 3 page 26-65 sies status service request enable set 0038 h sv,u sv,u 3 page 26-70 sier status service request enable reset 003c h sv,u sv,u 3 page 26-75 ile service request line enable 0040 h sv,u sv,u 3 page 26-80 t0c timer 0 configuration 0044 h sv,u sv,u 3 page 26-81 t1c timer 1 configuration 0048 h sv,u sv,u 3 page 26-83 stpw1 stop watch register 1 004c h sv,u sv,u 3 page 26-85 stpw2 stop watch register 2 0050 h sv,u sv,u 3 page 26-87 - reserved 0054 h - 007c h nbe nbe - - communication controlle r control registers succ1 suc configuration register 1 0080 h sv,u sv,u 3 page 26-88 succ2 suc configuration register 2 0084 h sv,u sv,u 3 page 26-96 succ3 suc configuration register 3 0088 h sv,u sv,u 3 page 26-97 nemc nem configuration register 008c h sv,u sv,u 3 page 26-98 prtc1 prt configuration register 1 0090 h sv,u sv,u 3 page 26-99 prtc2 prt configuration register 2 0094 h sv,u sv,u 3 page 26-101 mhdc mhd configuration register 0098 h sv,u sv,u 3 page 26-102 - reserved 009c h nbe nbe - - table 26-3 registers overvi ewe-ray kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-10 v1.1, 2011-03 e-ray, v3.12 gtuc01 gtu configuration register 1 00a0 h sv,u sv,u page 26-103 gtuc02 gtu configuration register 2 00a4 h sv,u sv,u 3 page 26-104 gtuc03 gtu configuration register 3 00a8 h sv,u sv,u 3 page 26-105 gtuc04 gtu configuration register 4 00ac h sv,u sv,u 3 page 26-106 gtuc05 gtu configuration register 5 00b0 h sv,u sv,u 3 page 26-107 gtuc06 gtu configuration register 6 00b4 h sv,u sv,u 3 page 26-108 gtuc07 gtu configuration register 7 00b8 h sv,u sv,u 3 page 26-109 gtuc08 gtu configuration register 8 00bc h sv,u sv,u 3 page 26-110 gtuc09 gtu configuration register 9 00c0 h sv,u sv,u 3 page 26-111 gtuc10 gtu configuration register 10 00c4 h sv,u sv,u 3 page 26-112 gtuc11 gtu configuration register 11 00c8 h sv,u sv,u 3 page 26-113 - reserved 00cc h - 00fc h nbe nbe - - communication controller status registers ccsv communication controller status vector 0100 h sv,u nbe 3 page 26-115 ccev communication controller error vector 0104 h sv,u nbe 3 page 26-120 - reserved 0108 h nbe nbe - - - reserved 010c h nbe nbe - - scv slot counter value 0110 h sv,u nbe 3 page 26-121 table 26-3 registers overvi ewe-ray kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-11 v1.1, 2011-03 e-ray, v3.12 mtccv macrotick and cycle counter value 0114 h sv,u nbe 3 page 26-122 rcv rate correction value 0118 h sv,u nbe 3 page 26-123 ocv offset correction value 011c h sv,u nbe 3 page 26-124 sfs sync frame status 0120 h sv,u nbe 3 page 26-125 swnit symbol window and network idle time status 0124 h sv,u nbe 3 page 26-127 acs aggregated channel status 0128 h sv,u sv,u 3 page 26-130 - reserved 012c h nbe nbe - - esidnn even sync id symbol window nn 0130 h - 0168 h sv,u nbe 3 page 26-133 - reserved 016c h sv,u nbe - - osidnn odd sync id symbol window nn 0170 h - 01a8 h sv,u nbe 3 page 26-135 - reserved 01ac h sv,u nbe - - nmvx network management vector [1 3] 01b0 h - 01b8 h sv,u nbe 3 page 26-137 - reserved 01bc h - 02fc h nbe nbe - - message buffer control registers mrc message ram configuration 0300 h sv,u sv,u 3 page 26-138 frf fifo rejection filter 0304 h sv,u sv,u 3 page 26-141 frfm fifo rejection filter mask 0308 h sv,u sv,u 3 page 26-143 fcl fifo critical level 030c h sv,u sv,u 3 page 26-144 message buffer status registers mhds message handler status 0310 h sv,u sv,u 3 page 26-145 ldts last dynamic transmit slot 0314 h sv,u sv,u 3 page 26-148 table 26-3 registers overvi ewe-ray kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-12 v1.1, 2011-03 e-ray, v3.12 fsr fifo status register 0318 h sv,u sv,u 3 page 26-149 mhdf message handler constraints flags 031c h sv,u nbe 3 page 26-151 txrq1 transmission request register 1 0320 h sv,u nbe 3 page 26-154 txrq2 transmission request register 2 0324 h sv,u nbe 3 page 26-155 txrq3 transmission request register 3 0328 h sv,u nbe 3 page 26-156 txrq4 transmission request register 4 032c h sv,u nbe 3 page 26-157 ndat1 new data register 1 0330 h sv,u nbe 3 page 26-158 ndat2 new data register 2 0334 h sv,u nbe 3 page 26-159 ndat3 new data register 3 0338 h sv,u nbe 3 page 26-160 ndat4 new data register 4 033c h sv,u nbe 3 page 26-161 mbsc1 message buffer status changed 1 0340 h sv,u nbe 3 page 26-162 mbsc2 message buffer status changed 2 0344 h sv,u nbe 3 page 26-163 mbsc3 message buffer status changed 3 0348 h sv,u nbe 3 page 26-164 mbsc4 message buffer status changed 4 034c h sv,u nbe 3 page 26-165 - reserved 0350 h - 03 a4 h nbe nbe - - ndic1 new data interrupt control 1 03a8 h sv,u sv,u 3 page 26-270 ndic2 new data interrupt control 2 03ac h sv,u sv,u 3 page 26-271 ndic3 new data interrupt control 3 03b0 h sv,u sv,u 3 page 26-272 table 26-3 registers overvi ewe-ray kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-13 v1.1, 2011-03 e-ray, v3.12 ndic4 new data interrupt control 4 03b4 h sv,u sv,u 3 page 26-273 msic1 message buffer status changed interrupt control 1 03b8 h sv,u sv,u 3 page 26-274 msic2 message buffer status changed interrupt control 2 03bc h sv,u sv,u 3 page 26-275 msic3 message buffer status changed interrupt control 3 03c0 h sv,u sv,u 3 page 26-276 msic4 message buffer status changed interrupt control 4 03c4 h sv,u sv,u 3 page 26-273 ibusysrc input buffer busy service request control register 03c8 h sv,u sv,u 3 page 26-279 obusysrc output buffer busy service request control register 03cc h sv,u sv,u 3 page 26-279 mbsc1src message buffer status changed 1 service request control register 03d0 h sv,u sv,u 3 page 26-279 mbsc0src message buffer status changed 0 service request control register 03d4 h sv,u sv,u 3 page 26-279 ndat1src new data 1 service request control register 03d8 h sv,u sv,u 3 page 26-279 ndat0src new data 0 service request control register 03dc h sv,u sv,u 3 page 26-279 tint1src timer interrupt 1 service request control register 03e0 h sv,u sv,u 3 page 26-279 tint0src timer interrupt 0 service request control register 03e4 h sv,u sv,u 3 page 26-279 table 26-3 registers overvi ewe-ray kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-14 v1.1, 2011-03 e-ray, v3.12 int1src interrupt 1 service request control register 03e8 h sv,u sv,u 3 page 26-279 int0src interrupt 0 service request control register 03ec h sv,u sv,u 3 page 26-279 identification registers crel core release registers 03f0 h sv,u nbe 3 page 26-166 endn endian register 03f4 h sv,u nbe 3 page 26-168 - reserved 03f6 h - 03fc h nbe nbe - - input buffer wrdsn write data section [1 64] 0400 h - 04fc h sv,u sv,u 3 page 26-169 wrhs1 write header section 1 0500 h sv,u sv,u 3 page 26-170 wrhs2 write header section 2 0504 h sv,u sv,u 3 page 26-173 wrhs3 write header section 3 0508 h sv,u sv,u 3 page 26-174 reserved 050c h nbe nbe - ibcm input buffer command mask 0510 h sv,u sv,u 3 page 26-175 ibcr input buffer command request 0514 h sv,u sv,u 3 page 26-177 reserved 0518 h - 05fc h nbe nbe - output buffer rddsn read data section [1 64] 0600 h - 06fc h sv,u nbe 3 page 26-179 rdhs1 read header section 1 0700 h sv,u nbe 3 page 26-180 rdhs2 read header section 2 0704 h sv,u nbe 3 page 26-182 rdhs3 read header section 3 0708 h sv,u nbe 3 page 26-184 mbs message buffer status 070c h sv,u nbe 3 page 26-186 obcm output buffer command mask 0710 h sv,u sv,u 3 page 26-191 table 26-3 registers overvi ewe-ray kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-15 v1.1, 2011-03 e-ray, v3.12 obcr output buffer command request 0714 h sv,u sv,u 3 page 26-194 reserved 0718 h -nbe nbe - - ecc control seccon single bit error correction control 0800 h sv,u sv,e 3 page 26-31 sedcon single bit error detection control 0804 h sv,u sv,e 3 page 26-33 dedcon double bit error correction control 0808 h sv,u sv,e 3 page 26-35 eccr ecc data read 080c h sv,u sv,u 3 page 26-37 eccw ecc data write 0810 h sv,u sv,u 3 page 26-38 reserved 0814 h - nbe nbe - - 1) the absolute register addres s is calculated as follows: module base address + offset address (shown in this column) table 26-3 registers overvi ewe-ray kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-16 v1.1, 2011-03 e-ray, v3.12 26.5.2.1 customer registers the addresses 0004 h - 000f h ,03c8 h - 03ec h and 0800 h - 0fff h are reserved for customer-specific registers. module identification register (id) this register contains bit fields identifying the e-ray module in infineons module portfolio and is read only. id module identification register (0008 h ) reset value: 0044 c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision number mod_rev defines the module revision number. the value of a module revision starts with 01 h (first revision). mod_type [15:8] r module type the value of this bit field is c0 h . it defines the module as a 32-bit module. mod_number [31:16] r module number value this bit field defines a module identification number. for the e-ray module the module identification number is 44 h . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-17 v1.1, 2011-03 e-ray, v3.12 busy control register (cust1) the busy control register enables the automatic delay scheme. furthermore it signals a time-out service request for the automatic delay scheme. cust1 busy and input buffer control register (0004 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 stpwts risb risa 0 ibf2 pag 0 ibf1 pag ibfs ien oen int0 rw rw rw r rw r rw rh rw rw rwh field bits type description int0 0rwh cif timeout service request status int0 will be set if a timeout has occurred during the auto delay scheme and must be reset by writing zero to int0. note: in case hardware sets int0 and at the same point of time software clears int0, int0 is cleared. oen 1rw enable auto delay scheme for output buffer control register (obcr) this control bit controls the delay scheme for output buffer control register (o bcr) read accesses. 0 b disable auto delay scheme for output buffer control register (obcr) 1 b enable auto delay scheme for output buffer control register (obcr) ien 2rw enable auto delay scheme for input buffer control register (ibcr) this control bit controls the auto delay scheme for input buffer control register (ibcr) read accesses. 0 b disable auto delay scheme for input buffer control register (ibcr) 1 b enable auto delay scheme for input buffer control register (ibcr) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-18 v1.1, 2011-03 e-ray, v3.12 ibfs 3rh input buffer status register this status bit indicates which of the two input buffer rams (ibf) is accessible by the host (via cif) as input buffer. the other non accessible buffer ram is currently used as shadow buffer ram by the eray message handler and therefore not accessible by the host. 0 b input buffer ram 2 (ibf2) is accessible as input buffer by the host (cif) 1 b input buffer ram 1 (ibf1) is accessible as input buffer by the host (cif) ibf1pag 4rw input buffer 1 page select register this control bit selects if the upper page or lower page of input buffer 1 (ibf1) currently active. read: 0 b lower page (256 bytes) of input buffer ram 1 selected 1 b upper page (256 bytes) of input buffer ram 1 selected write: 0 b select lower page (256 bytes) of input buffer ram 1 1 b select upper page (256 bytes) of input buffer ram 1 note: write is only possible, if input buffer ram 1 is currently accessible by the host (via cif) and therefore ibfs set. ibf2pag 7rw input buffer 2 page select register this control bit selects if the upper page or lower page of input buffer 2 (ibf2) currently active. read: 0 b lower page (256 bytes) of input buffer ram 2 selected 1 b upper page (256 bytes) of input buffer ram 2 selected write: 0 b select lower page (256 bytes) of input buffer ram 2 1 b select upper page (256 byte) of input buffer ram 2 note: write is only possible, if input buffer ram 2 is currently accessible by the host (via cif) and therefore ibfs cleared. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-19 v1.1, 2011-03 e-ray, v3.12 risa [11:10] rw receive input select channel a 00 b channel a receiver input rxda0 selected 01 b channel a receiver input rxda1 selected 10 b channel a receiver input rxda2 selected 11 b channel a receiver input rxda3 selected risb [13:12] rw receive input select channel b 00 b channel b receiver input rxdb0 selected 01 b channel b receiver input rxdb1 selected 10 b channel b receiver input rxdb2 selected 11 b channel b receiver input rxdb3 selected stpwts [15:14] rw stop watch trigger input select 00 b stop watch trigger input stpwt0 selected 01 b stop watch trigger input stpwt1 selected 10 b stop watch trigger input stpwt2 selected 11 b stop watch trigger input stpwt3 selected 0 [6:5], [9:8], [31:16] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-20 v1.1, 2011-03 e-ray, v3.12 customer interface time-out counter register (cust3) the time-out counter register is realizing th e time-out counter reload (startup) value for the automatic delay scheme (not the time-out down counter itself). automatic delayed write access to obcr and ibcr write and read accesses to the output buffer control register (obcr) can be automatically stalled due to a ongoing transfer from the message buffer to the output buffer. also write and read accesses to the input buffer control register (ibcr) may be automatically delayed due to a ongoing transfer from the input buffer to the message buffer. this delay scheme can be controlled (enabled or disabled) by cust1.ien and cust1.oen. the maximum time to stall a write or read access is determined by a single time-out counter preluded with the 32-bit value specified in the bit field cust3.to. if the time-out counter counts down to zero before the transfer to/from the message buffer is completed, the access (read or write) will be canceled and a service request will be generated. a canceled read access provides a 0 value. a canceled write access does not modify any bits in the obcr or ibcr. in addition the bit cust1.int0 of the service request status register will be set and must be reset by the host to disable the service request line. the read and write access to the output buffer control register (obcr) may be configured without automatic delay by clearing cust1.oen. setting obcr.req and immediately afterwards reading or writing ob cr, e.g. to set obcr.view will lead to a canceled read or write operation, e.g. obcr. view remains cleared, and an error is signalled by a set eir.ioba. besides canceling the erroneous read or write operation, and setting the error bit, no further state change happens. so full operation is granted. obcr remains read and write inaccessible until the transfer of data from the message buffer to the output buffer (mbf ? obf) is completed. during this time span all read and cust3 customer interface timeout counter (000c h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 to rw field bits type description to [31:0] rw cif timeout reload value the 32-bit down counter reload (start-up) value must be setup for the automatic delay scheme. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-21 v1.1, 2011-03 e-ray, v3.12 write accesses to the output buffer contro l register (obcr) are canceled. the transfer is completed when obcr.obsys is cleared. additionally signa l tobc may be used, e.g. for service request triggering, dma triggering, or driving a pin, to communicate the access status. the read and write access to the output buffer control register (obcr) may be configured to be automatic delayed by se tting cust1.oen and configuring cust3.to to the maximum stall time acceptable to the system. if setting obcr.req and immediately afterwards reading or writing to obcr, e.g. to set the obcr.view bit, this read or write will be stalled until either the maximum delay time elapsed (in this case the read or write operation is cancelled after the stall time, e.g. obcr.view remains cleared, and an error is signalled by setting eir.ioba) or the read or write completes normally, e.g. set obcr.view after the transfer of data from the message buffer to the output buffer (mbf ? obf) is finalized. during this time the bus is locked and no further access to the e-ray module is possible due to the ongoing stalled read or write operation. because no access is possible to the e-ray module, read or write stall may only be detected through the signal tobc or due to other not processed read or write accesses to the e-ray module. the read and write access to the input buffer control register (ibcr) may also be configured without automatic delay by cleari ng cust1.ien. by writing to ibcr.ibrh the input buffers are swapped (shadow ibf changes to host ibf and host ibf to shadow ibf), the content of the shadow ibf is copied into the mbf (ibf ? mbf), and ibcr.ibsys is set. writing to ibcr.ibrh a second time while ibcr.ibsys remained set (previously initia ted copy process ibf ? mbf ongoing) will correctly update ibcr.ibrh and set ibcr.ibsyh. this will set the signal ibusy. a third access, read or write, to ibcr while ibcr.ibsyh remains set will cancel this third access and an error is signalled by setting eir.iiba. besides canc eling this last access to ibcr and setting the error bit, no further state change happens. so full operation is granted. ibcr remains read and write inaccessible until the transfer of data from the input shadow buffer to the message buffer (ibf ? mbf) is completed and once more the input buffers are swapped (shadow ibf changes to host ibf and host ibf to shadow ibf). during this time span all read and write accesses to the input buffer control register (ibcr) are canceled. the transfer is completed when ibcr.ibsyh is cleared. additionally signal tibc may be used, e.g. for service request triggering, dma triggering, or driving a pin, to communicate the access status. the read and write access to the input buffer control register (ibcr) may be configured for being automatically delayed by setting cust1.ien and configuring cust3.to to the maximum stall time acceptable to the system. by writing to ibcr.ib rh the input buffers are swapped (shadow ibf changes to host ibf and host ibf to shadow ibf), the content of the shadow ibf co pied into the mbf, and ibcr.i bsys is set. writing to ibcr.ibrh a second time while ibcr.ibsys remains se t (previously initiated copy process ongoing) will correctly update ibcr.ibrh and set ibcr.i bsyh. a third access to ibcr while ibcr.ibsyh remains set will stall this re ad or write until either the maximum delay www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-22 v1.1, 2011-03 e-ray, v3.12 time elapsed (in this case the read or write operation is cancelled after the stall time and an error is signalled by setting eir.ioba) or the read or write completes normally, after the transfer of data from the input shadow buffer to the message buffer (ibf ? mbf) is finalized and once more the input buffers are swapped (shadow ibf changes to host ibf and host ibf to shadow ibf). during this time the bus is locked and no further access to e-ray module is possible due to the ongoing stalled read or write operation. because no access is possible to the e-ray module, read or write stall may only be detected through the signal tibc or due to other not processed read or write accesses to the e-ray module. so setting cust3.to = ffffffff h , cust1.ien = 1, and cust1.oen = 1 will always grant a consistent data access of the host to the output and input buffers without the need of reading and taking into account the st atus of obcr.obsys or ibcr.ibsyh. but this simplified access may cause system latencies and system performance loss. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-23 v1.1, 2011-03 e-ray, v3.12 26.5.2.2 special registers test register 1 (test1) the test register 1 holds the control bits to configure the test modes of the e-ray module. write access to these bits is only possible if bit test1.wrten is set. the test register 1 bits therefore can be used to test the interface to the physical layer (connectivity test) by driving / reading the respective pins. when the e-ray ip is operated in one of its test modes that requires test1.wrten to be set (ram test mode, i/o test mode, asynchronous transmit mode, and loop back mode) only the selected test mode functionality is available. the test functions are not available in addition to the normal operational mode functions, they change the functions of parts of t he e-ray module. therefore normal operation as specified outside this chapter and as required by the flexray? protocol specification and the flexray? conformance test is not possible. test mode functions may not be combined with each other or with flexray? protocol functions. the test mode features are intended for hardw are testing or for flexray? bus analyzer tools. they are not intended to be used in flexray? applications test1 test register 1 (0010 h ) reset value: 0000 0300 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cerb cera 0 txe nb txe na txb txa rxb rxa rh rh r rwh rwh rwh rwh rh rh 1514131211109876543210 0aobaoa0tmc0 elb e wrt en rrhrhrrwrrwrw field bits type description wrten 0rw write test register enable enables write access to the test registers. to set the bit from 0 to 1 the test mode key has to be written as defined on ?lock register (lck)? on page 26-39 . the unlock sequence is not required when test1.wrten is kept at 1 while other bits of the register are changed. the bit can be reset to 0 at any time. 0 b write access to test registers disabled. 1 b write access to test registers enabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-24 v1.1, 2011-03 e-ray, v3.12 elbe 1rw external loop back enable there are two possibilities to perform a loop back test. external loop back via physical layer or internal loop back for in-system self-test (default). in case of an internal loop back pins txena and txenb are in their inactive state, pins txda and txdb are set to high, pins rxda and rxdb are not evaluated. bit elbe is evaluated only when poc is in loop back mode and test multiplexer control is in non multiplexed mode tmc = 00. 0 b internal loop back (default) 1 b external loop back tmc [5:4] rw test multiplexer control 00 b normal signal path (default). 01 b ram test mode: internal busses are multiplexed to make all ram blocks of the e-ray module directly accessible by the host. this mode is intended to enable testing of the embedded ra m blocks during production testing. 10 b i/o test mode: output pins are driven to the values defined by bits txa, txb, txena , txenb . the values applied to the input pins can be read from register bits rxa and rxb. 11 b reserved; should not be used. aoa 8rh activity on a the channel idle condition is specified in the flexray? protocol spec v2.1, chapter 3, bitstrb process (zchannelidle). 0 b no activity detected, channel a idle 1 b activity detected, channel a not idle aob 9rh activity on b the channel idle condition is specified in the flexray? protocol spec v2.1, chapter 3, bitstrb process (zchannelidle). 0 b no activity detected, channel b idle 1 b activity detected, channel b not idle rxa 16 rh read channel a receive pin 0 b rxda = 0 1 b rxda = 1 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-25 v1.1, 2011-03 e-ray, v3.12 rxb 17 rh read channel b receive pin 0 b rxdb = 0 1 b rxdb = 1 txa 18 rwh read or write to channel a transmit pin 0 b txda = 0 1 b txda = 1 txb 19 rwh read or write to channel b transmit pin 0 b txdb = 0 1 b txdb = 1 txena 20 rwh read or write to channel a transmit enable pin 0 b txena = 0 1 b txena = 1 txenb 21 rwh read or write to channel b transmit enable pin 0 b txenb = 0 1 b txenb = 1 cera [27:24] rh coding error report channel a 1) set when a coding error is detected on channel a. reset to zero when register test1 is read or written. once the cera is set it will remain unchanged until the host accesses the test1 register. 0000 b no coding error detected 0001 b header crc error detected 0010 b frame crc error detected 0011 b frame start sequence fss too long 0100 b first bit of byte st art sequence bss seen low 0101 b second bit of byte start sequence bss seen high 0110 b first bit of frame end sequence fes seen high 0111 b second bit of frame end sequence fes seen low 1000 b cas / mts symbol seen too short 1001 b cas / mts symbol seen too long other combinations are reserved. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-26 v1.1, 2011-03 e-ray, v3.12 asynchronous transmit mode (atm) the asynchronous transmit mode is entered by writing 1110 b to the chi command vector succ1.cmd in the suc configuration register 1 (chi command: atm) while the communication controller is in ?config? state and bit test1.wrten in the test register 1 is set. this write operation ha s to be directly preceded by two consecutive write accesses to the configuration lock key (unlock sequence). when called in any other state or when bit test1.wrten is not set, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. ccsv.pocs in the communication controller status vector will return 1110 b while the e-ray module is in atm mode. asynchronous transmit mode can be left by writing 0001 b (chi command: ?config?) to the chi command vector succ1.cmd in the suc configuration register 1. in atm mode transmission of a flexray? fr ame is triggered by writing the number of the respective message buffer to the input buffer command request register (ibcr.ibrh) while bit ibcm.stxrs in the input buffer command mask register is set to 1. in this mode wake-up, startup, and clock synchronization are bypassed. the chi command send_mts results in the immediate transmission of an mts symbol. cerb [31:28] rh coding error report channel b 1) set when a coding error is detected on channel b. reset to zero when register test1 is read or written. once the cerb is set it will remain unchanged until the host accesses the test1 register. 0000 b no coding error detected 0001 b header crc error detected 0010 b frame crc error detected 0011 b frame start sequence fss too long 0100 b first bit of byte st art sequence bss seen low 0101 b second bit of byte start sequence bss seen high 0110 b first bit of frame end sequence fes seen high 0111 b second bit of frame end sequence fes seen low 1000 b cas / mts symbol seen too short 1001 b cas / mts symbol seen too long other combinations are reserved. 0 [3:2], [7:6], [15:10], [23:22] r reserved returns 0 if read; should be written with 0. 1) coding errors are also signalled when the communica tion controller is in ?m onitor_mode?. the error codes regarding cas / mts symbols concern only the mo nitored bit pattern, irrelevant whether those bit patterns are seen in the symbol window or elsewhere. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-27 v1.1, 2011-03 e-ray, v3.12 the cycle counter value of frames send in atm mode can be programmed via mtccv.ccv (writable in atm and loop back mode only). loop back mode the loop back mode is entered by writing 1111 b to the chi command vector succ1.cmd in the suc configuration register 1 (chi command: loop_back) while the communication controller is in ?config? state and bit test1.wrten in the test register 1 is set. this write operation ha s to be directly preceded by two consecutive write accesses to the configuration lock key (unlock sequence). when called in any other state or when bit test1.wrten is not set, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. ccsv.pocs in the communication controller status vector will show 0000 1101 h while the e-ray module is in loop back mode. loop back mode can be left by writing 0001 b (chi command: ?config?) to the chi command vector succ1.cmd in the suc configuration register 1. the loop back test mode is intended to check the module?s internal data paths. normal, time triggered operation is not possible in loop back mode. there are two possibilities to perform a l oop back test. external loop back via physical layer (test1.elbe = 1) or in ternal loop back for in-system self-test (test1.elbe = 0). in case of an internal loop back pins txena , txenb are in their inactive state, pins txda and txdb are set to high, pins rxdan and rxdbn are not evaluated. when the communication controller is in loop back mode, a loop back test is started by the host writing a message to the input buffer and requesting the transmission by writing to the input buffer command request register ibcr. the message handler will transfer the message into the message ram and then into the transient buffer of the selected channel. the channel protocol controller (prt ) will read (in 32-bit words) the message from the transmit part of the transient buffer and load it into its rx / tx shift register. the serial transmission is looped back into the shift register; its content is written into the receive part of the channels?s transient buffer before the next word is loaded. the prt and the message handler will then treat this transmitted message like a received message, perform an acceptance filtering on frame id and receive channel, and store the message into the message ram if it passed acceptance filtering. the loop back test ends with the host requesting this received message from the message ram and then checking the contents of the output buffer. each flexray? channel is tested separately. the e-ray cannot receive messages from the flexray? bus while it is in the loop back mode. the cycle counter value of frames used in loop back mode can be programmed via mtccv.ccv (writable in atm and loop back mode only). note that in case of an odd payload the last two bytes of the looped-back payload will be shifted by 16 bits to the right inside the last 32-bit data word. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-28 v1.1, 2011-03 e-ray, v3.12 test register 2 (test2) the test register 2 holds all bits required for the ram test of the seven embedded ram blocks of the e-ray module. write access to this register is only possible when test1.wrten in the test register 1 is set to 1. test2 test register 2 (0014 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 wr ecc 0 ssel 0 rs rrw r rw r rw field bits type description rs [2:0] rw ram select in ram test mode the ram blocks selected by rs are mapped to module address 0000 0400 h to 0000 07ff h (1024 byte addresses). 000 b input buffer ram 1 (ibf1) 001 b input buffer ram 2 (ibf2) 010 b output buffer ram 1 (obf1) 011 b output buffer ram 2 (obf2) 100 b transient buffer ram a (tbf1) 101 b transient buffer ram b (tbf2) 110 b message ram (mbf) 111 b reserved; should not be used. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-29 v1.1, 2011-03 e-ray, v3.12 ssel [6:4] rw segment select to enable access to the complete message ram (8192 byte addresses) the message ram is segmented. 000 b access to ram byte 0000 h to 03ff h enabled 001 b access to ram byte 0400 h to 07ff h enabled 010 b access to ram byte 0800 h to 0bff h enabled 011 b access to ram byte 0c00 h to 0fff h enabled 100 b access to ram byte 1000 h to 11ff h enabled 101 b access to ram byte 1400 h to 17ff h enabled 110 b access to ram byte 1800 h to 1bff h enabled 111 b access to ram byte 1c00 h to 1fff h enabled wr ecc 14 rw write ecc data enable content of eccw is transferred to the ram: 0 b disabled 1 b enabled note: test mode must be entered. see ?test register 1 (test1)? on page 26-23 0 3, [13:7], 15, [31:16] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-30 v1.1, 2011-03 e-ray, v3.12 ram test mode in ram test mode (test1.tmc = 1), one of the seven ram blocks can be selected for direct rd/wr access by programming test2.rs. for external access the selected ram block is mapped to address space 400 h to 7ff h (1024 byte addresses or 256 word addresses). because the length of the message ram exceeds the available address space, the message ram is segmented into segments of 1024 byte. the segments can be selected by programming test2.ssel in the test register 2. figure 26-3 ram test mode access to e-ray ram blocks normal operation ram test obf2 tbf1 tbf2 rs = 010 b 011 b 100 b ssel = 000 b 000 h 3fc h 400 h 000 b 001 b 010 b 011 b mbf 100 b addr[10:0] 7fc h obf1 101 b 110 b ibf2 ibf1 0 b 0 b ibf2 ibf1 1 b 1 b = 101 b 110 b 111 b mbf ibf1pag 001 b = ibf2pag www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-31 v1.1, 2011-03 e-ray, v3.12 seccon the single bit error correction control register holds the bits required for enabling the single bit error correction for each respective ram block of the e-ray module. it can only be written if prdcfg2.senav is set. in TC1798 this prdcfg2 bit is reset by ssw from a parameter stored in the config sector. thus the user has not access to turn on/off single error correction. in TC1798 the sec bits are tied to ?enabled?. it is supervisor and endinit protected. seccon sec control (0800 h ) reset value: 0000 007f h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 sec i2 en sec i1 en sec o2 en sec o1 en sec t2 en sec t1 en sec m en r rwrwrwrwrwrwrw field bits type description sec m en 0rw single bit error correction for message buffer (mbf) ram enable/test disable 0 b off 1 b on sec t1 en 1rw single bit error correction for transfer buffer 1 (tbf1) rams enable/test disable 0 b off 1 b on sec t2 en 2rw single bit error correction for transfer buffer 2 (tbf2) rams enable/test disable 0 b off 1 b on sec o1 en 3rw single bit error correction fo r output buffer 1 (obf1) ram enable/test disable 0 b off 1 b on www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-32 v1.1, 2011-03 e-ray, v3.12 sec o2 en 4rw single bit error correction fo r output buffer 2(obf2) ram enable/test disable 0 b off 1 b on sec i1 en 5rw single bit error correction fo r input buffer 1 (ibf1) ram enable/test disable 0 b off 1 b on sec i2 en 6rw single bit error correction fo r input buffer 2 (ibf2) ram enable/test disable 0 b off 1 b on 0 [31:7] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-33 v1.1, 2011-03 e-ray, v3.12 sedcon the single bit error detection control register holds the bits required for enabling the single bit error detection for each respective ram block of the e-ray module. it can only be written if prdcfg2.senav is set. in TC1798 this prdcfg2 bit is reset by ssw from a parameter stored in the config sector. thus the user has not access to turn on/off single error detection. in TC1798 the sed bits are tied to ?disabled?. the register is supervisor and endinit protected. sedcon sed control (0804 h ) reset value: 0000 007f h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 sed i2 en sed i1 en sed o2 en sed o1 en sed t2 en sed t1 en sed m en r rwrwrwrwrwrwrw field bits type description sed m en 0rw single bit error detection for message buffer (mbf) ram enable/test disable 0 b off 1 b on sed t1 en 1rw single bit error detection fo r transfer buffer 1 (tbf1) rams enable/test disable 0 b off 1 b on sed t2 en 2rw single bit error detection fo r transfer buffer 2 (tbf2) rams enable/test disable 0 b off 1 b on sed o1 en 3rw single bit error detection fo r output buffer 1 (obf1) ram enable/test disable 0 b off 1 b on www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-34 v1.1, 2011-03 e-ray, v3.12 sed o2 en 4rw single bit error detection fo r output buffer 2(obf2) ram enable/test disable 0 b off 1 b on sed i1 en 5rw single bit error detection fo r input buffer 1 (ibf1) ram enable/test disable 0 b off 1 b on sed i2 en 6rw single bit error detection fo r input buffer 2 (ibf2) ram enable/test disable 0 b off 1 b on 0 [31:7] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-35 v1.1, 2011-03 e-ray, v3.12 dedcon the double bit error detection control register holds the bits required for enabling the double bit error detection for each respective ram block of the e-ray module. dedcon ded control (0808 h ) reset value: 0000 007f h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ded i2 en ded i1 en ded o2 en ded o1 en ded t2 en ded t1 en ded m en r rwrwrwrwrwrwrw field bits type description ded m en 0rw double bit error detection for message buffer (mbf) ram enable/test disable 0 b off 1 b on ded t1 en 1rw double bit error detection fo r transfer buffer 1 (tbf1) rams enable/test disable 0 b off 1 b on ded t2 en 2rw double bit error detection fo r transfer buffer 2 (tbf2) rams enable/test disable 0 b off 1 b on ded o1 en 3rw double bit error detection for output buffer 1 (obf1) ram enable/test disable 0 b off 1 b on ded o2 en 4rw double bit error detection fo r output buffer 2(obf2) ram enable/test disable 0 b off 1 b on www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-36 v1.1, 2011-03 e-ray, v3.12 ded i1 en 5rw double bit error detection fo r input buffer 1 (ibf1) ram enable/test disable 0 b off 1 b on ded i2 en 6rw double bit error detection fo r input buffer 2 (ibf2) ram enable/test disable 0 b off 1 b on 0 [31:7] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-37 v1.1, 2011-03 e-ray, v3.12 eccr the ecc data read register always holds the ecc bits referring to the last accessed ram address. in normal operation ram can not be accessed by the cpu. for dedicated ram access to selected addresses by the cpu, test mode must be entered. see ?test register 2 (test2)? on page 26-28 eccr ecc data read register (080c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0ecc rrh field bits type description ecc [6:0] rh error correction data of the last accessed ram address 0 [31:7] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-38 v1.1, 2011-03 e-ray, v3.12 eccw the ecc data write register holds the ecc bits to be written together with the next ram access. these bits are written to the ecc bit field referring to the ram address accessed next. in normal operation e-ray ram can not be accessed by the cpu. the content of eccw is not transferred to the ram ecc data field in normal operation. for eccw to become effective (and for dedicated ram access to selected addresses by the cpu), test mode must be entered. see ?test register 1 (test1)? on page 26-23 . the referring ram must be selected. see ?test register 2 (test2)? on page 26-28 . note: content of eccw is transferred to the ram only if test2.wrecc is set! eccw ecc data write register (0810 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0ecc rrw field bits type description ecc [6:0] rw error correction data writte n with next ram address written next 0 [31:7] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-39 v1.1, 2011-03 e-ray, v3.12 lock register (lck) the lock register is write-only. reading the register will return 0000 0000 h . lck lock register (001c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 tmk clk ww field bits type description clk [7:0] w configuration lock key to leave ?config? state by writing to succ1.cmd commands ready, monitor_mode, atm, loop_back) in the suc configuration register 1, the write operation has to be directly preceded by two consecutive write accesses to the configuration lock key (unlock sequence). if the write sequence below is interrupted by other write accesses between the second write to the configuration lock key and the write access to the succ1 register, the communication controller remains in ?config? state and the sequence has to be repeated. first write: lck.clk = ce h = 1100 1110 b second write: lck.clk = 31 h = 0011 0001 b third write: succ1.cmd returns 0 if read www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-40 v1.1, 2011-03 e-ray, v3.12 note: in case the host uses 8/16-bit accesses to write the listed bit fields, the programmer has to ensure that no ?dum my accesses? e.g. to the remaining register bytes / words are inserted by the compiler. to exit ?config? state by writing to succ1.cmd in the suc configuration register 1, the write operation has to be directly preceded by two consecutive write accesses to the configuration lock key. if this write sequence is service requested by read accesses or write accesses to other locations, the communication controller remains in ?config? state and the sequence has to be repeated. first write: lck.clk = ce h = 1100 1110 b second write: lck.clk = 31 h = 0011 0001 b tmk [15:8] w test mode key to set bit test1.wrten the write operation has to be directly preceded by two consecutive write accesses to the test mode key. if the write sequence is interrupted by other write accesses between the second write to the test mode key and the write access to the test1 register, bi t test1.wrten is not set to 1 and the sequence has to be repeated. first write: lck.tmk = 75 h = 0111 0101 b second write: lck.tmk = 8a h = 1000 1010 b second write: test1.wrten = 1 returns 0 if read 0 [31:16] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-41 v1.1, 2011-03 e-ray, v3.12 26.5.2.3 service request registers the address space from 0020 h to 007f h is reserved for service request registers. error service request select (eir) the flags are set when the communication controller detects one of the listed error conditions. they remain set until the host clea rs them. a flag is cleared by writing a 1 to the corresponding bit position. writing a 0 has no effect on the flag. an application reset will also clear the register. eir error service request register (0020 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 tab b ltv b edb 0 tab a ltv a eda rrwhrwhrwhrrwhrwhrwh 1514131211109876543210 0mhf io ba ii ba efa rfo eer r ccl ccf sfo sfb m cna pem c r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description pemc 0rwh poc error mo de changed this flag is set whenever the error mode signalled by ccev.errm in the communication controller error vector register has changed. 0 b error mode has not changed 1 b error mode has changed this flag is cleared by writing a 1. cna 1rwh command not accepted the flag signals that the write access to the chi command vector succ1.cmd in the suc configuration register 1 was not successful because the requested command was not valid in the actual poc state, or because the chi command was locked (ccl = 1). 0 b chi command accepted 1 b chi command not accepted this flag is cleared by writing a 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-42 v1.1, 2011-03 e-ray, v3.12 sfbm 2rwh sync frames below minimum this flag signals that the number of sync frames received during the last communication cycle was below the limit required by the flexray? protocol. may be set during startup and therefore should be cleared by the host after the communication controller entered ?normal_active? state. 0 b sync node: 1 or more sync frames received non-sync node: 2 or more sync frames received 1 b less than the required mi nimum of sync frames received this flag is cleared by writing a 1. sfo 3rwh sync frame overflow set when either the number of sync frames received during the last communication cycle or the total number of sync frames received during the last double cycle exceeds the maximum number of sync frames as defined by gtuc02.snm in the gtu configuration register 2. 0 b number of received sync frames gtuc02.snm 1 b more sync frames received than configured by gtuc02.snm this flag is cleared by writing a 1. ccf 4rwh clock correction failure this flag is set at the end of the cycle whenever one of the following errors occurred: ? missing offset and / or rate correction ? clock correction limit reached the clock correction status is monitored in registers ccev and sfs. a failure may occur du ring startup, therefore bit ccf should be cleared by the host after the communication controller entered ?normal_active? state. 0 b clock correction successful so far 1 b clock correction failed this flag is cleared by writing a 1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-43 v1.1, 2011-03 e-ray, v3.12 ccl 5rwh chi command locked the flag signals that the write access to the chi command vector succ1.cmd was not successful because the execution of the previous chi command has not yet completed. in this case bi t eir.cna is also set to 1. 0 b chi command accepted 1 b chi command not accepted this flag is cleared by writing a 1. eerr 6rh ecc error the flag signals an ecc error to the host. it is set whenever one of the flags mhds.eibf, mhds.eobf, mhds.emr, mhds.etbf1, mhds.etbf2 changes from 0 to 1. see also ?message handler status (mhds)? on page 26-145 . 0 b no error detected 1 b error detected rfo 7rh receive fifo overrun the flag is set by the communication controller when a receive fifo overrun is detected. when a receive fifo overrun occurs, the oldest message is overwritten with the actual received message. the actual state of the fifo is monitored in register fsr. 0 b no receive fifo overrun detected 1 b a receive fifo overrun has been detected efa 8rwh empty fifo access this flag is set by the communication controller when the host requests the transfer of a message from the receive fifo via output buffer while the receive fifo is empty. 0 b no host access to empty fifo occurred 1 b host access to empty fifo occurred field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-44 v1.1, 2011-03 e-ray, v3.12 iiba 9rwh illegal input buffer access this flag is set by the communication controller when the host wants to modify a message buffer via input buffer while the communication controller is not in ?config? or ?default_config? state and one of the following conditions applies: 1. the host writes to the input buffer command request register to modify the: a) header section of message buffer 0, 1 if configured for transmission in key slot b) header section of static message buffers with buffer number < mrc.fdb while mrc.sec = 01 b c) header section of any static or dynamic message buffer while mrc.sec = 1x b d) header and / or data section of any message buffer belonging to the receive fifo 2. the host writes to any register of the input buffer while ibcr.ibsys is set. 0 b no illegal host access to input buffer occurred 1 b illegal host access to input buffer occurred ioba 10 rwh illegal output buffer access this flag is set by the communication controller when the host requests the transfer of a message buffer from the message ram to the output buffer while obcr.obsys is set to 1. 0 b no illegal host access to output buffer occurred 1 b illegal host access to output buffer occurred mhf 11 rwh message handler constraints flag the flag signals a message handler constraints violation condition. it is set whenever one of the flags mhdf.snua, mhdf.snub, mhdf.fnfa, mhdf.fnfb, mhdf.tbfa, mhdf.tbfb, mhdf.tnsa, mhdf.tnsb, mhdf.wahp changes from 0 to 1. 0 b no message handler failure detected 1 b message handler failure detected field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-45 v1.1, 2011-03 e-ray, v3.12 eda 16 rwh error detected on channel a this bit is set whenever one of the flags acs.seda, acs.ceda, acs.cia, acs.sb va changes from 0 to 1. 0 b no error detected on channel a 1 b error detected on channel a this flag is cleared by writing a 1. ltva 17 rwh latest transmit violation channel a the flag signals a latest transmit violation on channel a to the host. 0 b no latest transmit violation detected on channel a 1 b latest transmit violation detected on channel a this flag is cleared by writing a 1. taba 18 rwh transmission across boundary channel a the flag signals to the host that a transmission across a slot boundary occurred for channel a. 0 b no transmission across slot boundary detected on channel a 1 b transmission across slot boundary detected on channel a this flag is cleared by writing a 1. edb 24 rwh error detected on channel b this bit is set whenever one of the flags acs.sedb, acs.cedb, acs.cib, acs.sb vb changes from 0 to 1. 0 b no error detected on channel b 1 b error detected on channel b this flag is cleared by writing a 1. ltvb 25 rwh latest transmit violation channel b the flag signals a latest transmit violation on channel b to the host. 0 b no latest transmit violation detected on channel b 1 b latest transmit violation detected on channel b this flag is cleared by writing a 1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-46 v1.1, 2011-03 e-ray, v3.12 tabb 26 rwh transmission across boundary channel b the flag signals to the host that a transmission across a slot boundary occurred for channel b. 0 b no transmission across slot boundary detected on channel b 1 b transmission across slot boundary detected on channel b this flag is cleared by writing a 1. 0 [15:12], [23:19], [31:27] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-47 v1.1, 2011-03 e-ray, v3.12 status service request register (sir) the flags are set whenever the communication controller detects one of the listed events. the flags remain set until the host clears them. a flag is cleared by writing a 1 to the corresponding bit position. writing a 0 has no effect on the flag. an application reset will also clear the register. sir status service request register (0024 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 mts b wup b 0 mts a wup a r rwh rwh r rwh rwh 1514131211109876543210 sds mbs i suc s swe tob c tibc ti1 ti0 nmv c rf cl rf ne rxi txi cyc s cas wst rwhrwhrwhrwhrwhrwhrwhrwhrwh rh rh rwhrwhrwhrwhrwh field bits type description wst 0rwh wakeup status this flag is set when the wakeup status vector ccsv.wsv in the communication controller status vector register changes to a value other than undefined. 0 b wake-up status unmodified 1 b wake-up status modified (and not undefined) this flag is cleared by writing a 1. cas 1rwh collision avoidance symbol this flag is set by the communication controller during startup state when a cas or potential cas was received. 0 b no bit pattern matching the cas symbol received 1 b bit pattern matching the cas symbol received this flag is cleared by writing a 1. cycs 2rwh cycle start service request this flag is set by the communication controller when a communication cycle starts 0 b no communicatio n cycle started 1 b communication cycle started this flag is cleared by writing a 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-48 v1.1, 2011-03 e-ray, v3.12 txi 3rwh transmit service request this flag is set by the communication controller at the end of frame transmission if bit wrhs1.mbi in the respective message buffer is set (see table 26-24 ). 0 b no frame transmitted from a transmit buffer with wrhs1.mbi = 1 1 b at least one frame was transmitted from a transmit buffer with wrhs1.mbi = 1 this flag is cleared by writing a 1. rxi 4rwh receive service request this flag is set by the communication controller whenever the set condition of a message buffer nd flag is fulfilled and if bit wrhs1.mbi of that message buffer is set to 1(see table 26-24 ). 0 b no nd flag of a receive buffer with wrhs1.mbi = 1 has been set to 1 1 b at least one nd flag of a receive buffer with wrhs1.mbi = 1 has been set to 1 this flag is cleared by writing a 1. rfne 5rh receive fifo not empty this flag is set by the communication controller when a received valid frame was stor ed into the empty receive fifo.m the actual state of the receive fifo is monitored in register fsr 0 b receive fifo is empty 1 b receive fifo is not empty rfcl 6rh receive fifo critical level this flag is set when a valid receive fifo fill level fsr.rffl is equal or greater than the critical level as configured by fcl.cl. 0 b receive fifo below critical level 1 b receive fifo crit ical level reached nmvc 7rwh network management vector changed this service request flag signals a change in the network management vector visible to the host. 0 b no change in the network management vector 1 b network management vector changed this flag is cleared by writing a 1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-49 v1.1, 2011-03 e-ray, v3.12 ti0 8rwh timer service request 0 this flag is set whenever timer 0 matches the conditions configured in the timer service request 0 configuration register t0c. a timer service request 0 is also signalled by tint0src. 0 b no timer service request 0 1 b timer service request 0 occurred this flag is cleared by writing a 1. ti1 9rwh timer service request 1 this flag is set whenever the conditions programmed in the timer service request 1 configuration register t1c are met. a timer service request 1 is also signalled by tint1src. 0 b no timer service request 1 1 b timer service request 1 occurred this flag is cleared by writing a 1. tibc 10 rwh transfer input buffer completed this flag is set whenever a transfer from input buffer to the message ram has completed and bit ibcr.ibsys in the input buffer command request register has been reset by the message handler. 0 b no transfer completed 1 b transfer between input buffer and message ram completed this flag is cleared by writing a 1. tobc 11 rwh transfer output buffer completed this flag is set whenever a transfer from message ram to the output buffer has complet ed and bit obcr.obsys in the output buffer command request register has been reset by the message handler. 0 b no transfer completed 1 b transfer between message ram and the output buffer completed this flag is cleared by writing a 1. swe 12 rwh stop watch event this flag is set after a stop watch activation when the current cycle counter and macrotick value are stored in the stop watch register 1 (stpw1). 0 b no stop watch event 1 b stop watch event occurred this flag is cleared by writing a 1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-50 v1.1, 2011-03 e-ray, v3.12 sucs 13 rwh startup completed successfully this flag is set whenever a startup completed successfully and the communication controller entered ?normal_active? state. 0 b no startup comp leted successfully 1 b startup completed successfully this flag is cleared by writing a 1. mbsi 14 rwh message buffer status service request this flag is set by the communication controller when the message buffer status mbs has changed and if bit rdhs1.mbi of that message buffer is set (see table 26-24 ). 0 b no message buffer status change of message buffer with rdhs1.mbi= 1 has changed 1 b message buffer status of at least one message buffer with rdhs1.mbi= 1 has changed this flag is cleared by writing a 1. sds 15 rwh start of dynamic segment this flag is set by the communication controller when the dynamic segment starts. 0 b dynamic segment not yet started 1 b dynamic segment started wupa 16 rwh wakeup pattern channel a this flag is set by the communication controller when a wakeup pattern was received on channel a. only set when the communication controller is in ?wakeup?, ?ready?, or ?startup? state, or when in monitor mode. 0 b no wake-up pattern received on channel a 1 b wake-up pattern received on channel a this flag is cleared by writing a 1. mtsa 17 rwh mts received on channel a (vss!validmtsa) media access test symbol received on channel a during the proceeding symbol window. updated by the communication controller for each channel at the end of the symbol window. 0 b no mts symbol received on channel a 1 b mts symbol received on channel a this flag is cleared by writing a 1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-51 v1.1, 2011-03 e-ray, v3.12 wupb 24 rwh wakeup pattern channel b this flag is set by the communication controller when a wakeup pattern was received on channel b. only set when the communication controller is in ?wakeup?, ?ready?, or ?startup? state, or when in monitor mode. 0 b no wake-up pattern received on channel b 1 b wake-up pattern received on channel b this flag is cleared by writing a 1. mtsb 25 rwh mts received on channel b (vss!validmtsb) media access test symbol received on channel b during the proceeding symbol window. updated by the communication controller for each channel at the end of the symbol window. 0 b no mts symbol received on channel b 1 b mts symbol received on channel b this flag is cleared by writing a 1. 0 [23:18], [31:26] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-52 v1.1, 2011-03 e-ray, v3.12 error service request line select (eils) the error service request line select register assigns a service request generated by a specific error service request flag from regi ster eir to one of the two module service request lines int0src or int1src: 0 = interrupt assigned to interrupt line (int0src) 1 = interrupt assigned to interrupt line (int1src) eils error service request line select (0028 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 tab bl ltv bl edb l 0 tab al ltv al eda l r rwrwrw r rwrwrw 1514131211109876543210 0 mhf l iob al iiba l efa l rfo l eer rl ccl l ccf l sfo l sfb ml cna l pem cl r rwrwrwrwrwrwrwrwrwrwrwrw field bits type description pemcl 0rw poc error mode changed service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src cnal 1rw command not accepted service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src sfbml 2rw sync frames below minimum service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-53 v1.1, 2011-03 e-ray, v3.12 sfol 3rw sync frame overflow service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src ccfl 4rw clock correction failure service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src ccll 5rw chi command locked service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src eerrl 6rw ecc error servi ce request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src rfol 7rw receive fifo overrun service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src efal 8rw empty fifo access service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src iibal 9rw illegal input buffer access service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-54 v1.1, 2011-03 e-ray, v3.12 iobal 10 rw illegal output buffer access service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src mhfl 11 rw message handler constrains flag service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src edal 16 rw error detected on channel a service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src ltval 17 rw latest transmit violation channel a service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src tabal 18 rw transmission across boundary channel a service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src edbl 24 rw error detected on channel b service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src ltvbl 25 rw latest transmit violation channel b service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-55 v1.1, 2011-03 e-ray, v3.12 tabbl 26 rw transmission across boundary channel a service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src 0 [15:12], [23:19], [31:27] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-56 v1.1, 2011-03 e-ray, v3.12 status service reques t line select (sils) the status service request line select regi ster assign an service request generated by a specific status service request flag from re gister sir to one of the two module service request lines int0src or int1src: 0 = interrupt assigned to interrupt line int0src 1 = interrupt assigned to interrupt line int1src sils status service request line select (002c h ) reset value: 0303 ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 mts bl wup bl 0 mts al wup al rrwrwrrwrw 1514131211109876543210 sds l mbs il suc sl swe l tob cl tibc l ti1l ti0l nmv cl rfc ll rfn el rxil txil cyc sl cas l wst l rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description wstl 0rw wakeup status service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src casl 1rw collision avoidance symbol service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src cycsl 2rw cycle start service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-57 v1.1, 2011-03 e-ray, v3.12 txil 3rw transmit service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src rxil 4rw receive service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src rfnel 5rw receive fifo not empty service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src rfcll 6rw receive fifo critical level service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src nmvcl 7rw network management vector changed service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src ti0l 8rw timer service request 0 line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src ti1l 9rw timer service request 1 line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-58 v1.1, 2011-03 e-ray, v3.12 tibcl 10 rw transfer input buffer completed service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src tobcl 11 rw transfer output buffer completed service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src swel 12 rw stop watch event service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src sucsl 13 rw startup completed successfully service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src mbsil 14 rw message buffer status service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src sdsl 15 rw start of dynamic segment service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src wupal 16 rw wakeup pattern channel a service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-59 v1.1, 2011-03 e-ray, v3.12 mtsal 17 rw media access test symbol channel a service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src wupbl 24 rw wakeup pattern channel b service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src mtsbl 25 rw media access test symbol channel b service request line 0 b service request assigned to service request line int0src 1 b service request assigned to service request line int1src 0 [23:18], [31:26] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-60 v1.1, 2011-03 e-ray, v3.12 error service reques t enable set (eies) the settings in the error service request enable register determine which status changes in the error service request regist er will result in an service request. the enable bits are set by writing to eies and reset by writing to eier. writing a 1 sets the specific enable bit, a 0 has no effect. eies error service request enable set (0030 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 tab be ltv be edb e 0 tab ae ltv ae eda e rrwhrwhrwhrrwhrwhrwh 1514131211109876543210 0 mhf e iob ae iiba e efa e rfo e eer re ccl e ccf e sfo e sfb me cna e pem ce r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description pemce 0rwh poc error mode changed service request enable read: 0 b protocol error mode changed service request disabled 1 b protocol error mode changed service request enabled write: 0 b unchanged 1 b enable protocol error mode changed service request cnae 1rwh command not accepted service request enable read: 0 b command not valid service request disabled 1 b command not valid service request enabled write: 0 b unchanged 1 b enable command not valid service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-61 v1.1, 2011-03 e-ray, v3.12 sfbme 2rwh sync frames below minimum service request enable read: 0 b sync frames below minimum service request disabled 1 b sync frames below minimum service request enabled write: 0 b unchanged 1 b enable sync frames below minimum service request sfoe 3rwh sync frame overflow service request enable read: 0 b sync frame overflow service request disabled 1 b sync frame overflow service request enabled write: 0 b unchanged 1 b enable protocol error mode changed service request ccfe 4rwh clock correction failure service request enable read: 0 b clock correction failure service request disabled 1 b clock correction failure service request enabled write: 0 b unchanged 1 b enable clock correction failure service request ccle 5rwh chi command locked service request enable read: 0 b chi command locked service request disabled 1 b chi command locked service request enabled write: 0 b unchanged 1 b enable chi command locked service request eerre 6rwh ecc error service request enable read: 0 b ecc error service request disabled 1 b ecc error service request enabled write: 0 b unchanged 1 b enable ecc error service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-62 v1.1, 2011-03 e-ray, v3.12 rfoe 7rwh receive fifo overrun service request enable read: 0 b receive fifo overrun service request disabled 1 b receive fifo overrun service request enabled write: 0 b unchanged 1 b enable receive fifo overrun service request efae 8rwh empty fifo access service request enable read: 0 b empty fifo access service request disabled 1 b empty fifo access service request enabled write: 0 b unchanged 1 b enable empty fifo access service request iibae 9rwh illegal input buffer access service request enable read: 0 b illegal input buffer access service request disabled 1 b illegal input buffer access service request enabled write: 0 b unchanged 1 b enable illegal input buffer access service request iobae 10 rwh illegal output buffer access service request enable read: 0 b illegal output buffer access service request disabled 1 b illegal output buffer access service request enabled write: 0 b unchanged 1 b enable illegal output buffer access service request mhfe 11 rwh message handler constraints flag service request enable read: 0 b message handler constraints flag service request disabled 1 b message handler constraints flag service request enabled write: 0 b unchanged 1 b enable message handler constraints flag service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-63 v1.1, 2011-03 e-ray, v3.12 edae 16 rwh error detected on channel a service request enable read: 0 b error detected on channel a service request disabled 1 b error detected on channel a service request enabled write: 0 b unchanged 1 b enable error detected on channel a service request ltvae 17 rwh latest transmit violation channel a service request enable read: 0 b latest transmit violation channel a service request disabled 1 b latest transmit violation channel a service request enabled write: 0 b unchanged 1 b enable latest transmit violation channel a service request tabae 18 rwh transmission across boundary channel a service request enable read: 0 b transmission across boundary channel a service request disabled 1 b transmission across boundary channel a service request enabled write: 0 b unchanged 1 b enable transmission across boundary channel a service request edbe 24 rwh error detected on channel b service request enable read: 0 b error detected on channel b service request disabled 1 b error detected on channel b service request enabled write: 0 b unchanged 1 b enable error detected on channel b service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-64 v1.1, 2011-03 e-ray, v3.12 ltvbe 25 rwh latest transmit violation channel b service request enable read: 0 b latest transmit violation channel b service request disabled 1 b latest transmit violation channel b service request enabled write: 0 b unchanged 1 b enable latest transmit violation channel b service request tabbe 26 rwh transmission across boundary channel b service request enable read: 0 b transmission across boundary channel b service request disabled 1 b transmission across boundary channel b service request enabled write: 0 b unchanged 1 b enable transmission across boundary channel b service request 0 [15:12], [23:19], [31:27] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-65 v1.1, 2011-03 e-ray, v3.12 error service request enable reset (eier) the settings in the error service request enable register determine which status changes in the error service request register will result in a service request. the enable bits are set by writing to eies and reset by writing to eier. writing a 1 resets the specific enable bit, a 0 has no effect. eier error service request enable reset (0034 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 tab be ltv be edb e 0 tab ae ltv ae eda e rrwhrwhrwhrrwhrwhrwh 1514131211109876543210 0 mhf e iob ae iiba e efa e rfo e eer re ccl e ccf e sfo e sfb me cna e pem ce r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description pemce 0rwh poc error mode changed service request enable read: 0 b protocol error mode changed service request disabled 1 b protocol error mode changed service request enabled write: 0 b unchanged 1 b disable protocol error mode changed service request cnae 1rwh command not accepted service request enable read: 0 b command not accepted service request disabled 1 b command not accepted service request enabled write: 0 b unchanged 1 b disable command not accepted service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-66 v1.1, 2011-03 e-ray, v3.12 sfbme 2rwh sync frames below minimum service request enable read: 0 b sync frames below minimum service request disabled 1 b sync frames below minimum service request enabled write: 0 b unchanged 1 b disable sync frames below minimum service request sfoe 3rwh sync frame overflow service request enable read: 0 b sync frame overflow service request disabled 1 b sync frame overflow service request enabled write: 0 b unchanged 1 b disable protocol error mode changed service request ccfe 4rwh clock correction failure service request enable read: 0 b clock correction failure service request disabled 1 b clock correction failure service request enabled write: 0 b unchanged 1 b disable clock correction failure service request ccle 5rwh chi command locked service request enable read: 0 b chi command locked service request disabled 1 b chi command locked service request enabled write: 0 b unchanged 1 b disable chi command locked service request eerre 6rwh ecc error service request enable read: 0 b ecc error service request disabled 1 b ecc error service request enabled write: 0 b unchanged 1 b disable ecc error service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-67 v1.1, 2011-03 e-ray, v3.12 rfoe 7rwh receive fifo overrun service request enable read: 0 b receive fifo overrun service request disabled 1 b receive fifo overrun service request enabled write: 0 b unchanged 1 b disable receive fifo overrun service request efae 8rwh empty fifo access service request enable read: 0 b empty fifo access service request disabled 1 b empty fifo access service request enabled write: 0 b unchanged 1 b disable empty fifo access service request iibae 9rwh illegal input buffer access service request enable read: 0 b illegal input buffer access service request disabled 1 b illegal input buffer access service request enabled write: 0 b unchanged 1 b disable illegal input buffer access service request iobae 10 rwh illegal output buffer access service request enable read: 0 b illegal output buffer access service request disabled 1 b illegal output buffer access service request enabled write: 0 b unchanged 1 b disable illegal output buffer access service request mhfe 11 rwh message handler constraints flag service request enable read: 0 b message handler constraints flag service request disabled 1 b message handler constraints flag service request enabled write: 0 b unchanged 1 b disable message handler constraints flag service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-68 v1.1, 2011-03 e-ray, v3.12 edae 16 rwh error detected on channel a service request enable read: 0 b error detected on channel a service request disabled 1 b error detected on channel a service request enabled write: 0 b unchanged 1 b disable error detected on channel a service request ltvae 17 rwh latest transmit violation channel a service request enable read: 0 b latest transmit violation channel a service request disabled 1 b latest transmit violation channel a service request enabled write: 0 b unchanged 1 b disable latest transmit violation channel a service request tabae 18 rwh transmission across boundary channel a service request enable read: 0 b transmission across boundary channel a service request disabled 1 b transmission across boundary channel a service request enabled write: 0 b unchanged 1 b enable transmission across boundary channel a service request edbe 24 rwh error detected on channel b service request enable read: 0 b error detected on channel b service request disabled 1 b error detected on channel b service request enabled write: 0 b unchanged 1 b disable error detected on channel b service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-69 v1.1, 2011-03 e-ray, v3.12 ltvbe 25 rwh latest transmit violation channel b service request enable read: 0 b latest transmit violation channel b service request disabled 1 b latest transmit violation channel b service request enabled write: 0 b unchanged 1 b disable latest transmit violation channel b service request tabbe 26 rwh transmission across boundary channel b service request enable read: 0 b transmission across boundary channel b service request disabled 1 b transmission across boundary channel b service request enabled write: 0 b unchanged 1 b disable transmission across boundary channel b service request 0 [15:12], [23:19], [31:27] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-70 v1.1, 2011-03 e-ray, v3.12 status service reques t enable set (sies) the settings in the status service request enable set register determine which status changes in the status service request register will result in a service request. the enable bits are set by writing to sies and reset by writing to sier. writing a 1 sets the specific enable bit, a 0 has no effect. sies status service request enable set (0038 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 mts be wup be 0 mts ae wup ae r rwh rwh r rwh rwh 1514131211109876543210 sds e mbs ie suc se swe e tob ce tibc e ti1e ti0e nmv ce rfc le rfn ee rxie txie cyc se cas e wst e rwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwh field bits type description wste 0rwh wakeup status service request enable read: 0 b wake-up status service request disabled 1 b wake-up status service request enabled write: 0 b unchanged 1 b enable wakeup status service request case 1rwh collision avoidance symbol service request enable read: 0 b collision avoidance symbol service request disabled 1 b collision avoidance symbol service request enabled write: 0 b unchanged 1 b enable collision avoidance symbol service request cycse 2rwh cycle start service request enable read: 0 b cycle start service request disabled 1 b cycle start service request enabled write: 0 b unchanged 1 b enable cycle start service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-71 v1.1, 2011-03 e-ray, v3.12 txie 3rwh transmit service request enable read: 0 b transmit service request disabled 1 b transmit service request enabled write: 0 b unchanged 1 b enable transmit service request rxie 4rwh receive service request enable read: 0 b receive service request disabled 1 b receive service request enabled write: 0 b unchanged 1 b enable receive service request rfnee 5rwh receive fifo not empty service request enable read: 0 b receive fifo not empty service request disabled 1 b receive fifo not empty service request enabled write: 0 b unchanged 1 b enable receive fifo not empty service request rfcle 6rwh receive fifo critical level service request enable read: 0 b receive fifo critical level service request disabled 1 b receive fifo critical level service request enabled write: 0 b unchanged 1 b enable receive fifo critic al level service request nmvce 7rwh network management vector changed service request enable read: 0 b network management vector changed service request disabled 1 b network management vector changed service request enabled write: 0 b unchanged 1 b enable network management vector changed service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-72 v1.1, 2011-03 e-ray, v3.12 ti0e 8rwh timer service request 0 enable read: 0 b timer service request 0disabled 1 b timer service request 0 enabled write: 0 b unchanged 1 b enable timer service request 0 ti1e 9rwh timer service request 1 enable read: 0 b timer service request 1disabled 1 b timer service request 1 enabled write: 0 b unchanged 1 b enable timer service request 1 tibce 10 rwh transfer input buffer completed service request enable read: 0 b wakeup status service request disabled 1 b wakeup status service request enabled write: 0 b unchanged 1 b enable wakeup status service request tobce 11 rwh transfer output buffer co mpleted service request enable read: 0 b transfer input buffer completed service request disabled 1 b transfer input buffer completed service request enabled write: 0 b unchanged 1 b enable transfer input buffer completed service request swee 12 rwh stop watch event serv ice request enable read: 0 b stop watch event service request disabled 1 b stop watch event service request enabled write: 0 b unchanged 1 b enable stop watch event service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-73 v1.1, 2011-03 e-ray, v3.12 sucse 13 rwh startup completed successfully service request enable read: 0 b startup completed successfully service request disabled 1 b startup completed successfully service request enabled write: 0 b unchanged 1 b enable startup completed successfully service request mbsie 14 rwh message buffer status service request enable read: 0 b message buffer status service request disabled 1 b message buffer status service request enabled write: 0 b unchanged 1 b enable message buffer status service request sdse 15 rwh start of dynamic segment service request enable read: 0 b start of dynamic service request disabled 1 b start of dynamic service request enabled write: 0 b unchanged 1 b enable start of dynamic service request wupae 16 rwh wakeup pattern channel a service request enable read: 0 b wakeup pattern channel a service request disabled 1 b wakeup pattern channel a service request enabled write: 0 b unchanged 1 b enable wakeup pattern channel a service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-74 v1.1, 2011-03 e-ray, v3.12 mtsae 17 rwh media access test symbol channel a service request enable read: 0 b media access test symbol channel a service request disabled 1 b media access test symbol channel a service request enabled write: 0 b unchanged 1 b enable media access test symbol channel a service request wupbe 24 rwh wakeup pattern channel b service request enable read: 0 b wakeup pattern channel b service request disabled 1 b wakeup pattern channel b service request enabled write: 0 b unchanged 1 b enable wakeup pattern channel a service request mtsbe 25 rwh media access test symbol channel b service request enable read: 0 b media access test symbol channel b service request disabled 1 b media access test symbol channel b service request enabled write: 0 b unchanged 1 b enable media access test symbol channel b service request 0 [23:18], [31:26] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-75 v1.1, 2011-03 e-ray, v3.12 status service request enable reset (sier) the settings in the status service request enable reset register determine which status changes in the status service request register will result in a service request. the enable bits are set by writing to sies and reset by writing to sier. writing a 1 resets the specific enable bit, a 0 has no effect. sier status service request enable reset(003c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 mts be wup be 0 mts ae wup ae r rwh rwh r rwh rwh 1514131211109876543210 sds e mbs ie suc se swe e tob ce tibc e ti1e ti0e nmv ce rfc le rfn ee rxie txie cyc se cas e wst e rwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwhrwh field bits type description wste 0rwh wakeup status service request enable read: 0 b wakeup status service request disabled 1 b wakeup status service request enabled write: 0 b unchanged 1 b disable wakeup status service request case 1rwh collision avoidance symbol service request enable read: 0 b collision avoidance symbol service request disabled 1 b collision avoidance symbol service request enabled write: 0 b unchanged 1 b disable collision avoidance symbol service request cycse 2rwh cycle start service request enable read: 0 b cycle start service request disabled 1 b cycle start service request enabled write: 0 b unchanged 1 b disable cycle start service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-76 v1.1, 2011-03 e-ray, v3.12 txie 3rwh transmit service request enable read: 0 b transmit service request disabled 1 b transmit service request enabled write: 0 b unchanged 1 b disable transmit service request rxie 4rwh receive service request enable read: 0 b receive service request disabled 1 b receive service request enabled write: 0 b unchanged 1 b disable receive service request rfnee 5rwh receive fifo not empty service request enable read: 0 b receive fifo not empty service request disabled 1 b receive fifo not empty service request enabled write: 0 b unchanged 1 b disable receive fifo not empty service request rfcle 6rwh receive fifo critical level service request enable read: 0 b service request disabled 1 b receive fifo critical level service request enabled write: 0 b unchanged 1 b disable receive fifo critical level service request nmvce 7rwh network management vector changed service request enable read: 0 b network management vector changed service request disabled 1 b network management vector changed service request enabled write: 0 b unchanged 1 b disable network management vector changed service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-77 v1.1, 2011-03 e-ray, v3.12 ti0e 8rwh timer service request 0 enable read: 0 b timer service request 0 disabled 1 b timer service request 0 enabled write: 0 b unchanged 1 b disable service request 0 ti1e 9rwh timer service request 1 enable read: 0 b timer service request 1 disabled 1 b timer service request 1 enabled write: 0 b unchanged 1 b disable timer service request 1 tibce 10 rwh transfer input buffer completed service request enable read: 0 b wakeup status service request disabled 1 b wakeup status service request enabled write: 0 b unchanged 1 b disable wakeup status service request tobce 11 rwh transfer output buffer co mpleted service request enable read: 0 b transfer input buffer completed service request disabled 1 b transfer input buffer completed service request enabled write: 0 b unchanged 1 b disable transfer input buffer completed service request swee 12 rwh stop watch event serv ice request enable read: 0 b stop watch event service request disabled 1 b stop watch event service request enabled write: 0 b unchanged 1 b disable stop watch event service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-78 v1.1, 2011-03 e-ray, v3.12 sucse 13 rwh startup completed successfully service request enable read: 0 b startup completed successfully service request disabled 1 b startup completed successfully service request enabled write: 0 b unchanged 1 b disable startup completed successfully service request mbsie 14 rwh message buffer status service request enable read: 0 b message buffer status service request disabled 1 b message buffer status service request enabled write: 0 b unchanged 1 b disable message buffer status service request sdse 15 rwh start of dynamic segment service request enable read: 0 b start of dynamic service request disabled 1 b start of dynamic service request enabled write: 0 b unchanged 1 b disable start of dynamic service request wupae 16 rwh wakeup pattern channel a service request enable read: 0 b wakeup pattern channel a service request disabled 1 b wakeup pattern channel a service request enabled write: 0 b unchanged 1 b disable wakeup pattern channel a service request field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-79 v1.1, 2011-03 e-ray, v3.12 mtsae 17 rwh media access test symbol channel a service request enable read: 0 b media access test symbol channel a service request disabled 1 b media access test symbol channel a service request enabled write: 0 b unchanged 1 b disable media access test symbol channel a service request wupbe 24 rwh wakeup pattern channel b service request enable read: 0 b wakeup pattern channel b service request disabled 1 b wakeup pattern channel b service request enabled write: 0 b unchanged 1 b disable wakeup pattern channel a service request mtsbe 25 rwh media access test symbol channel b service request enable read: 0 b media access test symbol channel b service request disabled 1 b media access test symbol channel b service request enabled write: 0 b unchanged 1 b disable media access test symbol channel b service request 0 [23:18], [31:26] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-80 v1.1, 2011-03 e-ray, v3.12 service request line enable (ile) each of the two service request lines to the host int0src, int1src can be enabled / disabled separately by prog ramming bit eint0 and eint1. ile service request line enable (0040 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 eint 1 eint 0 rrwrw field bits type description eint0 0rw enable service request line 0 (int0src) 0 b service request line disabled 1 b service request line enabled eint1 1rw enable service request line 1 (int1src) 0 b service request line disabled 1 b service request line enabled 0 [31:2] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-81 v1.1, 2011-03 e-ray, v3.12 timer 0 configuration (t0c) absolute timer. specifies in terms of cycle count and macr otick the point in time when the timer 0 service request occurs. when the timer 0 service request is asserted, output signal tint0sr is set to 1 for the duration of one macrotick and sir.ti0 is set to 1. timer 0 can be activated as long as the poc is either in ?normal_active? state or in ?normal_passive? state. timer 0 is deac tivated when leaving ?normal_active? state or ?normal_passive? st ate except for transitions between the two states. before reconfiguration of the timer, the timer has to be halted first by writing 0 to bit t0rc. t0c timer 0 configuration (0044 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0t0mo rrw 1514131211109876543210 0t0cc 0 t0m s t0r c r rw r rw rwh field bits type description t0rc 0rwh timer 0 run control 0 b timer 0 halted 1 b timer 0 running t0ms 1rw timer 0 mode select 0 b single-shot mode 1 b continuous mode t0cc [14:8] rw timer 0 cycle code the 7-bit timer 0 cycle code determines the cycle set used for generation of the timer 0 service request. for details about the configuration of the cycle code see ?cycle counter filtering? on page 26-224 . t0mo [29:16] rw timer 0 macrotick offset configures the macrot ick offset from the beginning of the cycle where the service request is to occur. the timer 0 service request occurs at this offset for each cycle of the cycle set. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-82 v1.1, 2011-03 e-ray, v3.12 note: the configuration of timer 0 is compared against the macrotick counter value, there is no separate counter for timer 0. in case the communication controller leaves ?normal_active? or ?normal_passi ve? state, or if timer 0 is halted by host command, output signal tint0sr is reset to 0 immediately. 0 [7:2], 15, [31:30] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-83 v1.1, 2011-03 e-ray, v3.12 timer 1 configuration (t1c) relative timer. after the spec ified number of macroticks has expired, the timer 1 service request is asserted, output signal tint1sr is set to 1 for the duration of one macrotick and sir.ti1 is set to 1. timer 1 can be activated as long as the poc is either in ?normal_active? state or in ?normal_passive? state. timer 1 is deac tivated when leaving ?normal_active? state or ?normal_passive? st ate except for transitions between the two states. before reconfiguration of the timer, the timer has to be halted first by resetting bit t1rc to 0. t1c timer 1 configuration (0048 h ) reset value: 0002 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0t1mc rrw 1514131211109876543210 0 t1m s t1r c rrwrwh field bits type description t1rc 0rwh timer 1 run control 0 b timer 1 halted 1 b timer 1 running t1ms 1rw timer 1 mode select 0 b single-shot mode 1 b continuous mode t1mc [29:16] rw timer 1 macrotick count when the configured macrotick count is reached the timer 1 service request is generated. valid values are: 2 h ?3fff h macroticks in continuous mode 1 h ?3fff h macroticks in single-shot mode 0 [15:2], [31:30] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-84 v1.1, 2011-03 e-ray, v3.12 note: in case the communication cont roller leaves ?normal_active? or ?normal_passive? state, or if timer 1 is halted by ho st command, ou tput signal tint1sr is reset to 0 immediately. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-85 v1.1, 2011-03 e-ray, v3.12 stop watch register 1 (stpw1) the stop watch is activated by a rising or falling edge on signal stpw, by a service request 0 or 1 event (rising edge on signal in t0sr or int1sr) or by the host by writing bit stpw1.sswt to 1. with the macrotick counter increment following next to the stop watch activation the actual cycle counter and macrotick value are captured in the stop watch register 1 stpw1 while the slot coun ter values for channel a and b are captured in the stop watch register 2 stpw2. stpw1 stop watch register 1 (004c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0smtv rrh 1514131211109876543210 0 sccv 0 eint 1 eint 0 eet p ssw t edg e swm s esw t r rh r rw rw rw rwh rw rw rwh field bits type description eswt 0rwh enable stop watch trigger if enabled an edge on input stpw or a service request 0 or 1 event (rising edge on signal int0sr or int1sr) activates the stop watch. in single-shot mode this bit is reset to 0 after the actual cycle counter and macrotick value are stored in the stop watch register. 0 b stop watch trigger disabled 1 b stop watch trigger enabled swms 1rw stop watch mode select it is not possible to change the stop watch mode during enabled stop watch trigger (stpw1.eswt) 0 b single-shot mode 1 b continuous mode edge 2rw stop watch trigger edge select 0 b falling edge 1 b rising edge www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-86 v1.1, 2011-03 e-ray, v3.12 note: bits eswt and sswt cannot be set to 1 simultaneously. in this case the write access is ignored, and both bits keep their previous values. therefore either the external stop watch triggers or the so ftware stop watch trigger may be used. sswt 3rwh software stop watch trigger when the host writes this bit to 1 the stop watch is activated. after the actual cycle counter and macrotick value are stored in the stop watch register this bit is reset to 0. the bit is only writeable while eswt = 0. 0 b software trigger reset 1 b stop watch activated by software trigger eetp 4rw enable external trigger pin enables stop watch trigger event via signal stpw if eswt = 1. 0 b stop watch trigger via signal stpw disabled 1 b edge on signal stpw triggers stop watch eint0 5rw enable service request 0 trigger enables stop watch trigger by service request 0 event if eswt = 1. 0 b stop watch trigger by service request 0 disabled 1 b service request 0 event triggers stop watch eint1 6rw enable service request 1 trigger enables stop watch trigger by service request 1 event if eswt = 1. 0 b stop watch trigger by service request 1 disabled 1 b service request 1 event triggers stop watch sccv [13:8] rh stopped cycle counter value state of the cycle coun ter when the stop wa tch event occurred. valid values are: 0?3f h valid values smtv [29:16] rh stopped macrotick value state of the macrotick counter when the stop watch event occurred. valid values are: 0?3f h valid values 0 7, [15:14], [31:30] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-87 v1.1, 2011-03 e-ray, v3.12 stop watch register 2 (stpw2) stpw2 stop watch register 2 (0050 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 0sscvb0sscva rrhrrh field bits type description sscva [10:0] rh stop watch captured slot counter value channel a state of the slot counter for channel a when the stop watch event occurred. valid values are 0 to 2047 (0 h to 7ff h ). sscvb [26:16] rh stop watch captured slot counter value channel b state of the slot counter for channel b when the stop watch event occurred. valid values are 0 to 2047 (0 h to 7ff h ). 0 [15:11], [31:27] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-88 v1.1, 2011-03 e-ray, v3.12 26.5.2.4 communication controller control registers this section describes the registers provi ded by the communication controller to allow the host to control the operation of the communication controller. the flexray? protocol specification requires the host to write application configuration data in ?config? state only. please consider that th e configuration registers are not locked for writing in ?default_config? state. the configuration data is reset when ?default_config? state is entered from application reset. to change poc state fr om ?default_config? to ?config? state the host has to apply chi command ?config?. if the host wants the communication controller to leave ?config? state, the host has to proceed as described on ?lock register (lck)? on page 26-39 . suc configuration register 1 (succ1) succ1 suc configuration register 1 (0080 h ) reset value: 0c40 1080 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 cch b cch a mts b mts a hcs e tsm wuc s pta r rwrwrwrwrwrwrw rw 1514131211109876543210 csa 0 txs y txs t p bsy 0cmd rw r rw rw rh r rwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-89 v1.1, 2011-03 e-ray, v3.12 field bits type description cmd [3:0] rwh chi command vector the host may write any chi command at any time, but certain commands are only enabled in specific poc states. a disabled command will not be executed, the chi command vector cmd will be reset to 0000 b = ?command_not_accepted?, and flag eir.cna in the error service request register will be set to 1. in case the previous chi command has not yet completed, eir.ccl is set to 1 together with eir.cna; the chi command needs to be repeated. except for halt state, poc state change command applied while the communication controller is already in the requested poc state will be ignored. 0000 b command_not_accepted? 0001 b config 0010 b ready 0011 b wakeup 0100 b run 0101 b all_slots 0110 b halt 0111 b freeze 1000 b send_mts 1001 b allow_coldstart 1010 b reset_status_indicators 1011 b monitor_mode 1100 b clear_rams 1101 b reserved 1110 b reserved 1111 b reserved reading succ1.cmd shows whether the last chi command was accepted. ccsv.pocs monitors the actual poc state. the reserved chi commands code hardware test functions. pbsy 7rh poc busy signals that the poc is busy and cannot accept a command from the host. succ1.cmd is locked against write accesses. set to 1 after hard reset during initialization of internal ram blocks. 0 b poc not busy, succ1.cmd writable 1 b poc is busy, succ1.cmd locked www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-90 v1.1, 2011-03 e-ray, v3.12 txst 8rw transmit startup frame in key slot 1) 2) (pkeyslotusedforstartup) defines whether the key slot is used to transmit startup frames. the bit can be modified in ?d efault_config? or ?config? state only. 0 b no startup frame transmission in key slot, node is non- coldstarter 1 b key slot used to transmit startup frame, node is leading or following coldstarter txsy 9rw transmit sync frame in key slot 1) 2) (pkeyslotusedforsync) defines whether the key slot is used to transmit sync frames. the bit can be modified in ?d efault_config? or ?config? state only. 0 b no sync frame transmission in key slot, node is neither sync nor coldstart node 1 b key slot used to transmit sync frames, node is sync node csa [15:11] rw cold start attempts 1) (gcoldstartattempts) configures the maximum number of attempts that a cold starting node is permitted to try to start up the network without receiving any valid response from another node. it can be modified in ?default_config? or ?config? state only. must be identical in all nodes of a cluster. valid values are 2 to 31. pta [20:16] rw passive to active 1) (pallowpassivetoactive) defines the number of consecutive even / odd cycle pairs that must have valid clock correction terms before the communication controller is allowed to transit from ?normal_passive? to ?normal_ac tive? state. if set to 00000 b the communication controller is not allowed to transit from ?normal_passive? to ?nor mal_active? state. it can be modified in ?default_confi g? or ?config? state only. valid values are 0 to 31 even / odd cycle pairs. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-91 v1.1, 2011-03 e-ray, v3.12 wucs 21 rw wakeup channel select 1) (pwakeupchannel) with this bit the host selects the channel on which the communication controller sends the wakeup pattern. the communication controller ignores any attempt to change the status of this bit when not in ?default_config? or ?config? state. 0 b send wakeup pattern on channel a 1 b send wakeup pattern on channel b tsm 22 rw transmission slot mode 1) (psingleslotenabled) selects the initial transmission slot mode. in single slot mode the communication controller may only transmit in the preconfigured key slot. the key slot id is configured in the header section of message buffer 0 respectively message buffers 0 and 1 depending on bit mrc.splm. in case succ1.tsm = 1, message buffer 0 respectively message buffers 0,1 can be (re)configured in ?default_config? or ?config? state only. in all slot mode the communication controller may transmit in all slots. the bit can be written in ?default_config? or ?c onfig? state only. the communication controller changes to all slot mode when the host successfully applied the all_slots command by writing succ1.cmd = 0101 b in poc states ?normal_active? or ?normal_passive?. the actual sl ot mode is monitored by ccsv.slm. 0 b all slot mode 1 b single slot mode (default after application reset) hcse 23 rw halt due to clock sync error 1) (pallowhaltduetoclock) controls the transition to ?halt? state due to a clock synchronization error. the bit can be modified in ?default_config? or ?config? state only. 0 b communication controller wi ll enter / remain in ?normal_passive? 1 b communication controller will enter ?halt? state mtsa 24 rw select channel a for mts transmission 1) 3) the bit selects channel a for mts symbol transmission. the flag is reset by default and may be modified only in ?default_config? or ?config? state. 0 b channel a disabled for mts transmission 1 b channel a selected for mts transmission field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-92 v1.1, 2011-03 e-ray, v3.12 command_not_accepted succ1.cmd is reset to 0000 b due to one of the following conditions: ? illegal command applied by the host ? host writes command_not_accepted ? host applied new command while execution of the previous host command has not completed when succ1.cmd is reset to 0000 b , bit eir.cna in the error service request register is set, and - if enabled - an service request is generated. commands which are not accepted are not executed. config go to poc state ?config? when called in poc states ?default_config?, ?ready?, or in ?monitor_mode?. when called in ?halt? state transits to poc state mtsb 25 rw select channel b for mts transmission 1) 3) the bit selects channel b for mts symbol transmission. the flag is reset by default and may be modified only in ?default_config? or ?config? state. 0 b channel b disabled for mts transmission 1 b channel b selected for mts transmission ccha 26 rw connected to channel a 1) (pchannels) configures whether the node is connected to channel a. 0 b not connected to channel a 1 b node connected to channel a (default after application reset) cchb 27 rw connected to channel b 1) (pchannels) configures whether the node is connected to channel b. 0 b not connected to channel b 1 b node connected to channel b (default after application reset) 0 [6:4], 10, [31:28] r reserved returns 0 if read; should be written with 0. 1) this bit can be updated in ?defau lt_config? or ?config? state only! 2) the protocol requires that both bits t xst and txsy are set for coldstart nodes. 3) mtsa and mtsb may also be changed outside ?defau lt_config? or ?config? state when the write to succ1 register is directly preceded by the unlock se quence as described in lock register (lck). this may be combined with chi command ?send_mts?. if both bits mtsa and mtsb are set to 1 an mts symbol will be transmitted on both channels when requested by writing succ1.cmd = 1000 b . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-93 v1.1, 2011-03 e-ray, v3.12 ?default_config?. when called in any other state, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. ready go to poc state ?ready? when called in poc states ?config?, ?normal_active?, ?normal_passive?, ?startup?, or ?wakeup?. when calle d in any other state, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. wakeup go to poc state wakeup when called in poc state ?ready?. when called in any other state, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. run go to poc state ?startup? when called in poc state ?ready?. when called in any other state, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. all_slots leave single slot mode after successful startup / integration at the next end of cycle when called in poc states ?normal_ac tive? or ?normal_ passive?. when called in any other state, su cc1.cmd will be reset to 0000 b = ?command_not_accepted?. halt set the halt request ccsv.hrq bit in the communication controller status vector register and go to poc state ?halt? at the next end of cycle when call ed in poc states ?normal_active? or ?normal_passive? . when called in any other state, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. freeze set the freeze status indicator ccsv.fsi and go to poc state ?halt? immediately. can be called from any state. send_mts send single mts symbol during the next following symbol window on the channel configured by succ1.mtsa, succ1.mtsb, when called in poc state ?normal_active?. when called in any other state, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-94 v1.1, 2011-03 e-ray, v3.12 allow_coldstart the command resets bit ccsv.csi to enable the node to become cold starter. when called in states ?default_config?, ?c onfig?, ?halt?, or ?monitor_mode?. succ1.cmd will be reset to 0000 b = ?command_not_accepted?. to become leading coldstarter it is also requ ired that both txst and txsy are set. reset_status_indicators resets status flags ccsv.csni, ccsv.csa i, ccsv.wsv to their default values. may be called in poc state ready. when called in any other state, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. monitor_mode enter monitor_mode when called in poc state config. in this mode the communication controller is able to receive flexray? frames and wakeup pattern. it is also able to detect coding errors. the temporal integrity of received frames is not checked. this mode can be used for debugging purposes, e.g. in case that the startup of a flexray? network fails. when called in any other state, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. for details see ?monitor_mode? on page 26-208 . clear_rams sets bit mhds.cram in the message handler status register when called in ?default_config? or ?config? state. when called in any other state, succ1.cmd will be reset to 0000 b = ?command_not_accepted?. mhds.cram is also set when the communication controller leaves application reset. by setting mhds.cram all internal ram blocks are initia lized to zero. note that only the current ly active ibf bank is cleared. to clear the 2nd bank as well, cust1.ibf1pag and cust1.ibf2pag need to be set and command clear_rams need to be issued again. this is required in particular after an application reset. if the 2n d bank of ibf is left unused, this procedure is not required. during the initialization of the rams, succ1.pbsy will show poc busy. access to the configuration and status registers is possible during execution of chi command clear_rams. the initialization of the e-ray internal ra m blocks requires 2048 f clc_eray cycles. there should be no host access to ibf or obf during initialization of the internal ram blocks after application reset or after assertion of chi command clear_rams. before asserting chi command clear_rams the host should make sure that no transfer between message ram and ibf / obf or the transient buffer rams is ongoing. this command also resets the message buffer st atus registers mhds, ldts, fsr, mhdf, txrq1, txrq2, txrq3, txrq4, ndat1, ndat2, ndat3, ndat4, mbsc1, mbsc2, mbsc3, and mbsc4. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-95 v1.1, 2011-03 e-ray, v3.12 note: all accepted commands with exception of clear_rams and send_mts will cause a change of register ccsv after at most 8 cycles of the slower of the two clocks f clc_eray and f sclk , assumed that poc was no t busy when the command was applied and that no poc state change was forced by bus activity in that time frame. reading register ccsv will show data that is delayed by synchronization from f sclk to f clc_eray domain and by the host-specific cpu interface. table 26-4 below references the chi commands from the flexray? protocol specification v2.1 (section 2.2.1.1, table 2-2) to the e-ray chi command vector cmd.] table 26-4 reference to chi host comma nd summary from flexray? protocol specification chi command where processed (poc state) chi command vector cmd all_slot poc:normal_active, poc:normal_passive all_slots allow_coldstart all except poc:default_config, poc:config, poc:halt allow_coldstart config poc:default_config, poc:ready config config_complete poc:config unlock sequence & ready default_config poc:halt config freeze all freeze halt poc:normal_active, poc:normal_passive halt ready all except poc:default_config, poc:config, poc:ready, poc:halt ready run poc:ready run wakeup poc:ready wakeup www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-96 v1.1, 2011-03 e-ray, v3.12 suc configuration register 2 (succ2) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. note: the wakeup / startup noise time-out is calculated as follows: the wakeup / startup noise time- out = pdlistentimeout ? glistennoise = lt ? (ltn+ 1) succ2 suc configuration register 2 (0084 h ) reset value: 0100 0504 h 313029282726252423222120191817161514131211109876543210 0ltn0 lt rrwr rw field bits type description lt [20:0] rw listen timeout 1) (pdlistentimeout) configures wakeup / startup list en timeout in microticks. the range for wakeup / startup list en timeout (pdlistentimeout) is 1284 to 1283846 (504 h to 139706 h ) microticks 1) this bit can be updated in ?defau lt_config? or ?config? state only! ltn [27:24] rw listen time-out noise 1) (glistennoise - 1) configures the upper limit for startup and wakeup listen timeout in the presence of noise expressed as a multiple of the cluster constant pdlistentimeout. the range of pdlistentimeout 2 to 16. ltn must be configured identical in all nodes of a cluster. 1 h listen time-out noise is equal 2 2 h listen time-out noise is equal 3 ... h ... f h listen time-out noise is equal 16 0 [23:21], [31:28] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-97 v1.1, 2011-03 e-ray, v3.12 suc configuration register 3 (succ3) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. succ3 suc configuration register 3 (0088 h ) reset value: 0000 0011 h 313029282726252423222120191817161514131211109876543210 0wcfwcp rrwrw field bits type description wcp [3:0] rw maximum without clock correction passive 1) (gmaxwithoutclockcorrectionpassive) defines the number of consecutive even / odd cycle pairs with missing clock correction terms t hat will cause a transition from ?normal_active? to ?normal_ passive? state. must be identical in all nodes of a cluster. valid values are 1 to 15 (1 h to f h ) cycle pairs. 1) this bit can be updated in ?defau lt_config? or ?config? state only! wcf [7:4] rw maximum without cloc k correction fatal 1) (gmaxwithoutclockcorrectionfatal) defines the number of consecutive even / odd cycle pairs with missing clock correction terms t hat will cause a transition from ?normal_active? or ?normal_ passive? to ?halt? state. must be identical in all nodes of a cluster. valid values are 1 to 15 (1 h to f h )cycle pairs. 0 [31:8] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-98 v1.1, 2011-03 e-ray, v3.12 nem configuration register (nemc) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. nemc nem configuration register (008c h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 0nml rrw field bits type description nml [3:0] rw network management vector length 1) (gnetworkmanagementvectorlength) these bits configure the length of the nm vector. the configured length must be identical in all nodes of a cluster. valid values are 0 to 12 (0 h to c h ) bytes. 1) this bit can be updated in ?defau lt_config? or ?config? state only! 0 [31:4] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-99 v1.1, 2011-03 e-ray, v3.12 prt configuration register 1 (prtc1) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. prtc1 prt configuration register 1 (0090 h ) reset value: 084c 0633 h 313029282726252423222120191817161514131211109876543210 rwp 0 rxw brp spp 0 1 casm tsst rw r rw rw rw r r rw rw field bits type description tsst [3:0] rw transmission start sequence transmitter 1) (gdtsstransmitter) configures the duration of the transmission start sequence (tss) in terms of bit times (1 bit time = 4 microticks = 100ns at 10mbps). must be identical in all nodes of a cluster. valid values are 3 to 15 (3 h to f h ) bit times. casm [10:4] rw collision avoidance symbol maximum 1) (gdcasrxlowmax) configures the upper limit of the acceptance window for a collision avoidance symbol (cas). valid values are 67 to 99 (43 h to 63 h ). most significant bit of casm is hard wired to 1 and can not be modified. spp [13:12] rw strobe point position 1) defines the sample count value for strobing. the strobed bit value is set to the voted value when the sample count is incremented to the va lue configured by spp. 00 b sample 5 (default) 01 b sample 4 10 b sample 6 11 b reserved; should not be used. note: the current revision 2.1 of the flexray? protocol requires that spp = 00 b . the alternate strobe point positions could be used to compensate for asymmetries in the physical layer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-100 v1.1, 2011-03 e-ray, v3.12 brp [15:14] rw baud rate prescaler 1) (gdsampleclockperiod, psamplepermicrotick) the baud rate prescaler configures the baud rate on the flexray? bus. the baud rates listed below are valid with a sample clock f sclk = 80 mhz. one bit time always consists of 8 samples independent of the configured baud rate. 00 b 10 mbit/s (1 microtick= 25 ns; twice sampled with f sclk ) gdsampleclockperiod = 12.5 ns = 1 / f sclk psamplespermicrotick = 2 01 b 5 mbit/s (1 microtick= 25ns; single sampled with f sclk /2) gdsampleclockperiod = 25 ns = 2 / f sclk psamplespermicrotick = 1 10 b 2.5 mbit/s (1 microtick = 50ns; single sampled with f sclk /4) gdsampleclockperiod = 50 ns = 4 / f sclk psamplespermicrotick = 1 11 b reserved; should not be used (2.5 mbit/s (1 microtick = 50 ns; single sampled with f sclk /4) gdsampleclockperiod = 50 ns = 4 / f sclk psamplespermicrotick = 1 rxw [24:16] rw wakeup symbol receive window length 1) (gdwakeupsymbolrxwindow ) configures the number of bit times used by the node to test the duration of the received wakeup pattern. must be identical in all nodes of a cluster. valid values are 76 to 301 (4c h to 12d h ) bit times. rwp [31:26] rw repetitions of tx wakeup pattern 1) (pwakeuppattern) configures the number of repetitions (sequences) of the tx wakeup symbol. valid values are 2 to 63 (2 h to 3f h ). 0 11, 25 r reserved returns 0 if read; should be written with 0. 1) this bit can be updated in ?defau lt_config? or ?config? state only! field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-101 v1.1, 2011-03 e-ray, v3.12 prt configuration register 2 (prtc2) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. prtc2 prt configuration register 2 (0094 h ) reset value: 0f2d 0a0e h 313029282726252423222120191817161514131211109876543210 0txl txi 0rxl0 rxi rrw rw rrwrrw field bits type description rxi [5:0] rw wakeup symbol receive idle 1) (gdwakeupsymbolrxidle) configures the number of bit times used by the node to test the duration of the idle phase of the received wakeup symbol. must be identical in all nodes of a cluster. valid values are 14 to 59 (e h to 3b h ) bit times. 1) this bit can be updated in ?defau lt_config? or ?config? state only! rxl [13:8] rw wakeup symbol receive low 1) (gdwakeupsymbolrxlow) configures the number of bit times used by the node to test the duration of the low phase of the received wakeup symbol. must be identical in all nodes of a cluster. valid values are 10 to 55 (a h to 37 h ) bit times. txi [23:16] rw wakeup symbol transmit idle 1) (gdwakeupsymboltxidle) configures the number of bit times used by the node to transmit the idle phase of the wakeup symbol. must be identical in all nodes of a cluster. valid values are 45 to 180 (2d h to b4 h )bit times. txl [29:24] rw wakeup symbol transmit low 1) (gdwakeupsymboltxlow) configures the number of bit times used by the node to transmit the low phase of the wakeup symbol. must be identical in all nodes of a cluster. valid values are 15 to 60 (f h to 3c h ) bit times. 0 [7:6], [15:14], [31:30] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-102 v1.1, 2011-03 e-ray, v3.12 mhd configuration register (mhdc) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. mhdc mhd configuration register (0098 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 0 slt 0 sfdl rrw rrw field bits type description sfdl [6:0] rw static frame data length (gpayloadlengthstatic) 1) configures the cluster-wide payload length for all frames sent in the static segment in double byte. the payload length must be identical in all nodes of a cluster. valid values are 0 to 127 (0 to 7f h ). 1) this bit can be updated in ?defau lt_config? or ?config? state only! slt [28:16] rw start of latest transmit (platesttx) 1) configures the maximum minislot value allowed before inhibiting frame transmission in the dynami c segment of the cycle. there is no transmission dynamic segment if slt is reset to zero. valid values are 0 to 7981 (0 to 1f2d h ) minislots. 0 [15:7], [31:29] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-103 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 1 (gtuc01) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. gtuc01 gtu configuration register 1 (00a0 h ) reset value: 0000 0280 h 313029282726252423222120191817161514131211109876543210 0ut rrw field bits type description ut [19:0] rw microtick per cycle (pmicropercycle) 1) configures the durati on of the communicati on cycle in microticks. valid values are 640 to 640000 (280 h to 9c400 h ) microticks. 1) this bit can be updated in ?defau lt_config? or ?config? state only! 0 [31:20] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-104 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 2 (gtuc02) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. gtuc02 gtu configuration register 2 (00a4 h ) reset value: 0002 000a h 313029282726252423222120191817161514131211109876543210 0snm0mpc rrwrrw field bits type description mpc [13:0] rw macrotick per cycle (gmacropercycle) 1) configures the duration of one communication cycle in macroticks. the cycle length must be identical in all nodes of a cluster. valid values are 10 to 16000 (a h to 3e80 h ) macroticks. 1) this bit can be updated in ?defau lt_config? or ?config? state only! snm [19:16] rw sync node max (gsyncnodemax) 1) maximum number of frames within a cluster with sync frame indicator bit syn set to 1. must be identical in all nodes of a cluster. valid values are 2 to 15 (2 h to f h ). 0 [15:14], [31:20] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-105 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 3 (gtuc03) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. gtuc03 gtu configuration register 3 (00a8 h ) reset value: 0202 0000 h 313029282726252423222120191817161514131211109876543210 0 miob 0 mioa uiob uioa r rw r rw rw rw field bits type description uioa [7:0] rw microtick initial offset channel a 1) (pmicroinitialoffset[a]) configures the number of microticks between the actual time reference point on channel a and the subsequent macrotick boundary of the secondary time reference point. the parameter depends on pdelaycompensation[a] and therefore has to be set for each channel independently. valid values are 0 to 240 (0 h to f0 h ) microticks. uiob [15:8] rw microtick initial offset channel b 1) (pmicroinitialoffset[b]) configures the number of microticks between the actual time reference point on channel b and the subsequent macrotick boundary of the secondary time reference point. the parameter depends on pdelaycompensation[b] and therefore has to be set for each channel independently. valid values are 0 to 240 (0 h to f0 h ) microticks. mioa [22:16] rw macrotick initial offset channel a (gmacroinitialoffset[a]) 1) configures the number of macroticks between the static slot boundary and the subsequent macrotick boundary of the secondary time reference point based on the nominal macrotick duration. must be identical in all nodes of a cluster. valid values are 2 to 72 (2 h to 48 h ) macroticks. miob [30:24] rw macrotick initial offset channel b (gmacroinitialoffset[b]) 1) configures the number of macroticks between the static slot boundary and the subsequent macrotick boundary of the secondary time reference point based on the nominal macrotick duration. must be identical in all nodes of a cluster. valid values are 2 to 72 (2 h to 48 h ) macroticks. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-106 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 4 (gtuc04) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. for details about configuration of nit and ocs see ?configuration of network idle time (nit) start and offset correction start? on page 26-197 . 0 23, 31 r reserved returns 0 if read; should be written with 0. 1) this bit can be updated in ?defau lt_config? or ?config? state only! gtuc04 gtu configuration register 4 (00ac h ) reset value: 0008 0007 h 313029282726252423222120191817161514131211109876543210 0ocs0 nit rrwrrw field bits type description nit [13:0] rw network idle time start 1) (gmacropercycle - gdnit - 1) configures the starting point of the network idle time (nit) at the end of the communication cycle expressed in terms of macroticks from the beginning of the cycle. the st art of network idle time (nit) is recognized if macrotick = gmacropercycle - gdnit -1 and the increment pulse of macrotick is set. must be identical in all nodes of a cluster. valid values are 7 to 15997 (7 h to 3e7d h ) macroticks. 1) this bit can be updated in ?defau lt_config? or ?config? state only! ocs [29:16] rw offset correction start 1) (goffsetcorrectionstart - 1) determines the start of the offset correction within the network idle time (nit) phase, calculated from start of cycle. must be identical in all nodes of a cluster. for cluster consisting of e-ray implementations only, it is sufficient to program ocs = nit + 1. valid values are 8 to 15998 (8 h to 3e7e h ) macroticks. 0 [15:14], [31:30] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-107 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 5 (gtuc05) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. gtuc05 gtu configuration register 5 (00b0 h ) reset value: 0e00 0000 h 313029282726252423222120191817161514131211109876543210 dec 0 cdd dcb dca rw r rw rw rw field bits type description dca [7:0] rw delay compensation channel a 1) (pdelaycompensation[a]) used to compensate for reception delays on channel a. this covers assumed propagation delay up to cpropagationdelaymax for microticks in the range of 0.0125 s to 0.05 s. in practice, the minimum of the propagation delays of all sync nodes should be applied. valid values are 0 to 200 (0 h to c8 h ) microticks. 1) this bit can be updated in ?defau lt_config? or ?config? state only! dcb [15:8] rw delay compensation channel b 1) (pdelaycompensation[b]) used to compensate for reception delays on channel b. this covers assumed propagation delay up to cpropagationdelaymax for microticks in the ra nge of 0.0125 to 0.05 s. in practice, the minimum of the propagation delays of all sync nodes should be applied. valid values are 0 to 200 (0 h to c8 h ) microticks. cdd [20:16] rw cluster dri ft damping (pclusterdriftdamping) 1) configures the cluster drift damping value used in clock synchronization to minimize accumulation of rounding errors. valid values are 0 to 20 (0 h to 14 h ) microticks. dec [31:24] rw decoding correction (pdecodingcorrection) 1) configures the decoding correction value used to determine the primary time reference point. valid values are 14 to 143 (e h to 8f h ) microticks. 0 [23:21] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-108 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 6 (gtuc06) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. gtuc06 gtu configuration register 6 (00b4 h ) reset value: 0002 0000 h 313029282726252423222120191817161514131211109876543210 0mod0 asr rrwrrw field bits type description asr [10:0] rw accepted startup range 1) (pdacceptedstartuprange) number of microticks constituting the expanded range of measured deviation for startup frames during integration. valid values are 0 to 1875 (0 h to 753 h ) microticks. 1) this bit can be updated in ?defau lt_config? or ?config? state only! mod [26:16] rw maximum oscillator drift (pdmaxdrift) 1) maximum drift offset between two nodes that operate with unsynchronized clocks over one communication cycle in microticks. valid values are 2 to 1923 (2 h to 783 h ) microticks. 0 [15:11], [31:27] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-109 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 7 (gtuc07) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. gtuc07 gtu configuration register 7 (00b8 h ) reset value: 0002 0004 h 313029282726252423222120191817161514131211109876543210 0 nss 0 ssl rrwrrw field bits type description ssl [9:0] rw static slot length (gdstaticslot) 1) configures the duration of a static slot in macroticks. the static slot length must be identical in all nodes of a cluster. valid values are 4 to 659 (4 h to 293 h ) macroticks. 1) this bit can be updated in ?defau lt_config? or ?config? state only! nss [25:16] rw number of static slots (gnumberofstaticslots) 1) configures the number of static slots in a cycle. at least 2 coldstart nodes must be configured to startup a flexray? network. the number of static slots must be identical in all nodes of a cluster. valid values are 2 to 1023 (2 h to 3ff h ). 0 [15:10], [31:26] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-110 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 8 (gtuc08) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. gtuc08 gtu configuration register 8 (00bc h ) reset value: 0000 0002 h 313029282726252423222120191817161514131211109876543210 0nms 0msl rrw rrw field bits type description msl [5:0] rw minislot length (gdminislot) 1) configures the duration of a mini slot in macroti cks. the minislot length must be identical in all nodes of a cluster. valid values are 2 to 63 (2 h to 3f h ) macroticks. 1) this bit can be updated in ?defau lt_config? or ?config? state only! nms [28:16] rw number of minislots (gnumberofminislots) 1) configures the number of minislots within the dynamic segment of a cycle. the number of minislots must be identical in all nodes of a cluster. valid values are 0 to 7986 (0 h to 1f32 h ). 0 [15:6], [31:29] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-111 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 9 (gtuc09) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. gtuc09 gtu configuration register 9 (00c0 h ) reset value: 0000 0101 h 313029282726252423222120191817161514131211109876543210 0 dsi 0 mapo 0 apo rrwrrwrrw field bits type description apo [5:0] rw action po int offset (gdactionpointoffset) 1) configures the action point offset in macroticks within static slots and symbol window. must be identical in all nodes of a cluster. valid values are 1 to 63 (1 h to 3f h ) macroticks. 1) this bit can be updated in ?defau lt_config? or ?config? state only! mapo [12:8] rw minislot action point offset 1) (gdminislotactionpointoffset) configures the action point offset in macroticks within the minislots of the dynamic segment. must be identical in all nodes of a cluster. valid values are 1 to 31 (1 h to 1f h ) macroticks. dsi [17:16] rw dynamic slot idle phase 1) (gddynamicslotidlephase) the duration of the dynamic slot idle phase has to be greater or equal than the idle detection time. must be identical in all nodes of a cluster. valid values are 0 to 2 minislot. 0 [7:6], [15:13], [31:18] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-112 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 10 (gtuc10) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. gtuc10 gtu configuration register 10 (00c4 h ) reset value: 0002 0005 h 313029282726252423222120191817161514131211109876543210 0mrc0moc rrwrrw field bits type description moc [13:0] rw maximum offset correction 1) (poffsetcorrectionout) holds the maximum permitted offset correction value to be applied by the internal clock synchronization algorithm (absolute value). the communication contro ller checks only the internal offset correction value against the maximum offset correction value. valid values are 5 to 15266 (5 h to 3ba2 h ) microticks. 1) this bit can be updated in ?defau lt_config? or ?config? state only! mrc [26:16] rw maximum rate correction 1) (pratecorrectionout) holds the maximum permitted rate correction value to be applied by the internal clock synchronization algorithm. the communication controller checks only the internal rate correction value against the maximum rate correction value (absolute value). valid values are 2 to 1923 (2 h to 783 h ) microticks. 0 [15:14], [31:27] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-113 v1.1, 2011-03 e-ray, v3.12 gtu configuration register 11 (gtuc11) gtuc11 gtu configuration register 11 (00c8 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 0erc0eoc 0 erc c 0 eoc c rrwrrw rrwrwrw field bits type description eocc [1:0] rw external offset correction control (pexternoffsetcontrol) by writing to eocc the external offset correction is enabled as specified below. should be modified only outside network idle time (nit). 00 b no external clock correction 01 b no external clock correction 10 b external offset correction value subtracted from calculated offset correction value 11 b external offset correction value added to calculated offset corre ction value ercc [9:8] rw external rate correction control (pexternratecontrol) by writing to ercc the external rate correction is enabled as specified below. should be modified only outside network idle time (nit). 00 b no external rate correction 01 b no external rate correction 10 b external rate correction value subtracted from calculated rate correction value 11 b external rate correction value added to calculated rate correction value eoc [18:16] rw external offset correction 1) (pexternoffsetcorrection) holds the external clock offset co rrection value in microticks to be applied by the internal synchronization algorithm. the value is subtracted / added from / to the calculated offset correction value. the value is applied during network idle time (nit). may be modified in ?default_confi g? or ?config? state only. valid values are 0 to 7 microticks. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-114 v1.1, 2011-03 e-ray, v3.12 erc [26:24] rw external rate correction 1) (pexternratecorrection) holds the external rate correct ion value in microticks to be applied by the internal clock synchronization algorithm. the value is subtracted / added from / to the calculated rate correction value. the value is applied during network idle time (nit). may be modified in ?default_config? or ?config? state only. valid values are 0 to 7 microticks. 0 [7:2], [15:10], [23:19], [31:27] r reserved returns 0 if read; should be written with 0. 1) this bit can be updated in ?defau lt_config? or ?config? state only! field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-115 v1.1, 2011-03 e-ray, v3.12 26.5.2.5 communication controller status registers during 8/16-bit accesses to status variables coded with more than 8/16-bit, the variable might be updated by the communication controller between two accesses (non-atomic read accesses). the status vector may change faster than the host can poll the status vector, depending on f clc_eray frequency. communication controller status vector (ccsv) ccsv communication controller status vector(0100 h ) reset value: 0010 4000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0psl rcawsv rrh rhrh 1514131211109876543210 0 csi csai csni 0 slm hrq fsi pocs r rh rh rh r rh rh rh rh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-116 v1.1, 2011-03 e-ray, v3.12 field bits type description pocs [5:0] rh protocol operation control status indicates the actual state of operation of the communication controller protocol operation control 000000 b ?default_config? state 000001 b ?ready? state 000010 b ?normal_active? state 000011 b ?normal_passive? state 000100 b ?halt? state 000101 b ?monitor_mode? state 000110 b ? 001110 b are reserved. 001111 b ?config? state indicates the actual state of operation of the poc in the wakeup path 010000 b wakeup_standby state 010001 b ?wakeup_listen? state 010010 b ?wakeup_send? state 010011 b ?wakeup_detect? state 010100 b ? 011111 b are reserved. indicates the actual state of operation of the poc in the startup path 100000 b ?startup_prepare? state 100001 b ?coldstart_listen? state 100010 b ?coldstart_collision_resolution state 100011 b ?coldstart_consistency_check? state 100100 b ?coldstart_gap state 100101 b ?coldstart_join? state 100110 b ?integration_coldstart_check? state 100111 b ?integration_listen? state 101000 b ?integration_consistency_check? state 101001 b ?initialize_schedule? state 101010 b ?abort_startup? state 101011 b ?startup_success? state 101100 b ? 111111 b are reserved. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-117 v1.1, 2011-03 e-ray, v3.12 fsi 6rh freeze status indicator (vpoc!freeze ) indicates that the poc has entered the ?halt? state due to chi command ?freeze? or due to an error condition requiring an immediate poc halt. reset by transition from ?halt? to ?default_config? state. hrq 7rh halt request (vpoc!chihaltrequest) indicates that a request from the host has been received to halt the poc at the end of the communication cycle. reset by transition from ?halt? to ?default_config? state or when entering ?ready? state. slm [9:8] rh slot mode (vpoc!slotmode) indicates the actual slot mode of the poc in states ready, wakeup, startup, normal_active, and normal_passive. default is ?single?. changes to ?all?, depending on configuration bit succ1.tsm. in ?normal_active? or ?normal_passive? state the chi command ?all_slots? will change the slot mode from ?single? over ?all_pending? to ?all?. set to single in all other states. 00 b single 01 b reserved 10 b all_pending 11 b all csni 12 rh coldstart noise indicator (vpoc!coldstartnoise) indicates that the cold start procedure occurred under noisy conditions. reset by chi command ?reset_status_indicators? or by transition from ?halt? to ?default_config? state or from ?ready? to ?startup? state. csai 13 rh coldstart abort indicator coldstart aborted. reset by chi command ?reset_status_indicators? or by transition from ?halt? to ?default_config? state or from ?ready? to ?startup? state. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-118 v1.1, 2011-03 e-ray, v3.12 csi 14 rh cold start inhibit (vcoldstartinhibit) indicates that the node is disabled from cold starting. the flag is set whenever the poc enters ?ready? state due to chi command ?ready?. the flag has to be reset under control of the host by chi command ?allow_coldstart? (succ1.cmd = 1001 b ). 0 b cold starting of node enabled 1 b cold starting of node disabled wsv [18:16] rh wakeup status (vpoc!wakeupstatus) indicates the status of the current wakeup attempt. reset by chi command ?reset_status_indicators? or by transition from ?halt? to ?default_config? state. 000 b undefined. wakeup not yet executed by the communication controller. 001 b received_header. set wh en the communication controller finishes wakeup due to the reception of a frame header without coding violation on either channel in ?wakeup_listen? state. 010 b received_wup. set when the communication controller finishes wakeup due to the reception of a valid wakeup pattern on the configured wakeup channel in ?wakeup_listen? state. 011 b collision_header. set when the communication controller stops wakeup due to a detected collision during wakeup pattern transmission by receiving a valid header on either channel. 100 b collision_wup. set when the communication controller stops wakeup due to a detected collision during wakeup pattern transmission by receiving a valid wakeup pattern on the configured wakeup channel. 101 b collision_unknown. set when the communication controller stops wakeup by leaving ?wakeup_detect? state af ter expiration of the wakeup timer without receiving a valid wakeup pattern or a valid frame header. 110 b transmitted. set when the communication controller has successfully completed the transmission of the wakeup pattern. 111 b reserved field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-119 v1.1, 2011-03 e-ray, v3.12 rca [23:19] rh remaining coldstart attempts (vremainingcoldstartattempts) indicates the number of remaining coldstart attempts. the run command resets this counter to the maximum number of coldstart attempts as configured by succ1.csa. psl [29:24] rh poc status log status of ccsv.pocs immediately before entering ?halt? state. set when entering ?halt? state. set to ?halt? when freeze command is applied during ?halt? state. reset to 000000 b when leaving ?halt? state. 0 [11:10], 15, [31:30] rh reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-120 v1.1, 2011-03 e-ray, v3.12 communication controller error vector (ccev) reset by transition from ?halt? to ?default_config? state or when entering ?ready? state. ccev communication controller error vector (0104 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ptac errm 0 ccfc rrhrhrrh field bits type description ccfc [3:0] rh clock correction failed counter (vclockcorre ctionfailed) the clock correction failed counter is incremented by one at the end of any odd communication cycle where either the missing offset correction error or missing rate correction error are active. the clock correction failed counter is reset to 0 at the end of an odd communication cycle if neither the offset correction failed nor the rate correction failed errors are active. the clock correction failed counter stops at 15. errm [7:6] rh error mode (vpoc!errormode) indicates the actual error mode of the poc. 00 b ?active? (green) 01 b ?passive? (yellow) 10 b ?comm_halt? (red) 11 b reserved ptac [12:8] rh passive to active count (vallowpassivetoactive) indicates the number of consecutive even / odd cycle pairs that have passed with valid rate and offset correction terms, while the node is wait ing to transit from ?n ormal_passive? state to ?normal_active? state. the transition takes place when ptac equals succ1.pta. 0 [5:4], [31:13] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-121 v1.1, 2011-03 e-ray, v3.12 slot counter value (scv) scv slot counter value (0110 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 sccb rrh 1514131211109876543210 0 scca rrh field bits type description scca [10:0] rh slot counter channel a (vslotcounter[a] ) current slot counter value on channel a. the value is incremented by the communication controller and reset at the start of a communication cycle. valid values are 0 to 2047 (0 h to 7fd h ). sccb [26:16] rh slot counter channel b (vslotcounter[b] ) current slot counter value on channel b. the value is incremented by the communication controller and reset at the start of a communication cycle. valid values are 0 to 2047 (0 h to 7fd h ). 0 [15:11], [31:27] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-122 v1.1, 2011-03 e-ray, v3.12 macrotick and cycle counter value (mtccv) mtccv macrotick and cycle counter value (0114 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 ccv rrh 1514131211109876543210 0mtv rrh field bits type description mtv [13:0] rh macrotick value (vmacrotick) current macrotick value. the value is incremented by the communication controller and reset at the start of a communication cycle. valid values are 0 to 16000 (0 h to 3e80 h ). ccv [21:16] rh cycle counter value (vcyclecounter) current cycle counter value. the value is incremented by the communication controller at the start of a communication cycle. valid values are 0 to 63 (0 h to 3f h ). 0 [15:14], [31:22] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-123 v1.1, 2011-03 e-ray, v3.12 rate correction value (rcv) rcv rate correction value (0118 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 rcv rrh field bits type description rcv [11:0] rh rate correction value (vratecorrection) rate correction value (two?s comp lement). calculated internal rate correction value before limitation. if the rcv value exceeds the limits defined by gtuc10.mrc, flag sfs.rclr is set to 1. 0 [31:12] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-124 v1.1, 2011-03 e-ray, v3.12 offset correction value (ocv) note: the external rate / offset correcti on value is added to the limited rate / offset correction value. ocv offset correction value (011c h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 0ocv rrh field bits type description ocv [18:0] rh offset correction value (voffsetcorrection) offset correction value (two?s complement). calculated internal offset correction value before limitation. if the ocv value exceeds the limits defined by gtuc10.moc flag sfs.oclr is set to 1. 0 [31:19] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-125 v1.1, 2011-03 e-ray, v3.12 sync frame status (sfs) the maximum number of valid sync frames in a communication cycle is 15. sfs sync frame status (0120 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 rc lr mr cs oc lr mo cs r rhrhrhrh 1514131211109876543210 vsbo vsbe vsao vsae rh rh rh rh field bits type description vsae [3:0] rh valid sync frames channel a, even communication cycle holds the number of valid sync frames received on channel a in the even communication cycle. if transmission of sync frames is enabled by succ1. txsy the value is incremented by one. the value is updated during the network idle time (nit) of each even communication cycle. th is bit field is only valid if the channel a is assigned to the communication controller by succ1.ccha. vsao [7:4] rh valid sync frames channel a, odd communication cycle holds the number of valid sync frames received on channel a in the odd communication cycle. if transmission of sync frames is enabled by succ1. txsy the value is incremented by one. the value is updated during the network idle time (nit) of each odd communicatio n cycle. this bit field is only valid if the channel a is assigned to the communication controller by succ1.ccha. vsbe [11:8] rh valid sync frames channel b, even communication cycle holds the number of valid sync frames received on channel b in the even communication cycle. if transmission of sync frames is enabled by succ1. txsy the value is incremented by one. the value is updated during the network idle time (nit) of each even communication cycle. th is bit field is only valid if the channel b is assigned to the communication controller by succ1.cchb. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-126 v1.1, 2011-03 e-ray, v3.12 vsbo [15:12] rh valid sync frames channel b, odd communication cycle holds the number of valid sync frames received on channel b in the odd communication cycle. if transmission of sync frames is enabled by succ1. txsy the value is incremented by one. the value is updated during the network idle time (nit) of each odd communicatio n cycle. this bit field is only valid if the channel b is assigned to the communication controller by succ1.cchb. mocs 16 rh missing offset correction signal the missing offset correction flag signals to the host, that no offset correction calculation can be performed because no sync frames were received. the flag is updated by the communication controller at start of offset correction phase. 0 b offset correction signal valid 1 b missing offset correction signal oclr 17 rh offset correction limit reached the offset correction limit reached flag signals to the host, that the offset correction value has exceeded its limit as defined by gtuc10.moc. the flag is updated by the communication controller at start of offset correction phase. 0 b offset correction below limit 1 b offset correction limit reached mrcs 18 rh missing rate correction signal the missing rate correction flag signals to the host, that no rate correction calculation can be performed because no pairs of even / odd sync frames were received. the flag is updated by the communication controller at start of offset correction phase. 0 b rate correctio n signal valid 1 b missing rate correction signal rclr 19 rh rate correction limit reached the rate correction limit reached flag signals to the host, that the rate correction value has exceeded its limit.as defined by gtuc10.mrc. the flag is updated by the communication controller at start of offset correction phase. 0 b rate correction below limit 1 b rate correctio n limit reached 0 [31:20] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-127 v1.1, 2011-03 e-ray, v3.12 symbol window and network idle time (nit) status (swnit) symbol window related status information. updated by the communication controller at the end of the symbol window for each channel. during startup the status data is not updated. note: mtsa and mtsb may be changed outside ?default_config? or ?config? state when the write to suc configuration register 1 (succ1) register is directly preceded by the unlock sequence as described in ?lock register (lck)? on page 26-39 . this may be combined with chi command send_mts. if both bits mtsa and mtsb are set to 1 an mts symbol will be transmitted on both channels when requested by writing succ1.cmd = 1000 b swnit symbol window and network idle time status (0124 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 sbn b sen b sbn a sen a mts b mts a tcs b sbs b ses b tcs a sbs a ses a r rhrhrhrhrhrhrhrhrhrhrhrh field bits type description sesa 0rh syntax error in symbol window channel a (vss!syntaxerrora) 0 b no syntax error detected 1 b syntax error during symbol window detected on channel a sbsa 1rh slot boundary violation in symbol window channel a (vss!bviolationa) 0 b no slot boundary violation detected 1 b slot boundary violation during symbol window detected on channel a www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-128 v1.1, 2011-03 e-ray, v3.12 tcsa 2rh transmission conflict in symbol window channel a (vss!txconflicta) 0 b no transmission conflict detected 1 b transmission conflict in symbol window detected on channel a sesb 3rh syntax error in symbol window channel b (vss!syntaxerrorb) 0 b no syntax error detected 1 b syntax error during symbol window detected on channel b sbsb 4rh slot boundary violation in symbol window channel b (vss!bviolationb) 0 b no slot boundary violation detected 1 b slot boundary violation during symbol window detected on channel b tcsb 5rh transmission conflict in symbol window channel b (vss!txconflictb) 0 b no transmission conflict detected 1 b transmission conflict in symbol window detected on channel b mtsa 6rh mts received on channel a (vss!validmtsa) 1) media access test symbol received on channel a during the proceeding symbol window. updated by the communication controller for each channel at the end of the symbol window. when this bit is set to 1, also interrupt flag sir.mtsa is set to 1. 0 b no mts symbol received on channel a 1 b mts symbol received on channel a mtsb 7rh mts received on channel b (vss!validmtsb) 1) media access test symbol received on channel b during the proceeding symbol window. updated by the communication controller for each channel at the end of the symbol window. when this bit is set to 1, also interrupt flag sir.mtsb is set to 1. 0 b no mts symbol received on channel b 1 b mts symbol received on channel b field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-129 v1.1, 2011-03 e-ray, v3.12 sena 8rh syntax error during network idle time (nit) channel a (vss!syntaxerrora) updated by the communication controller channel a at the end of the nit. 0 b no syntax error detected 1 b syntax error during network idle time (nit) detected on channel a sbna 9rh slot boundary violation during network idle time (nit) channel a (vss!bviolationa) updated by the communication controller channel a at the end of the nit. 0 b no slot boundary violation detected 1 b slot boundary violation during network idle time (nit) detected on channel a senb 10 rh syntax error during network idle time (nit) channel b (vss!syntaxerrorb) updated by the communication controller channel b at the end of the nit. 0 b no syntax error detected 1 b syntax error during network idle time (nit) detected on channel b sbnb 11 rh slot boundary violation during network idle time (nit) channel b (vss!bviolationb) updated by the communication controller channel b at the end of the nit. 0 b no slot boundary violation detected 1 b slot boundary violation during network idle time (nit) detected on channel b 0 [31:12] r reserved returns 0 if read; should be written with 0. 1) mtsa and mtsb may also be changed outside ?defau lt_config? or ?config? state when the write to succ1 register is directly preceded by the unlock seq uence as described in ?lock register (lck)?. this may be combined with chi command send_mts. if both bits mtsa and mtsb are set to 1 an mts symbol will be transmitted on both channels when requested by writing succ1.cmd = 1000 b . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-130 v1.1, 2011-03 e-ray, v3.12 aggregated channel status (acs) the aggregated channel status provides the host with an accrued status of channel activity for all communication slots regardless of whether they are assigned for transmission or subscribed for reception. the aggregated channel status also includes status data from the symbol window and the network idle time. the status data is updated (set) after each slot and aggregated until it is reset by the host. during startup the status data is not updated. a flag is cleared by writing a 1 to the corresponding bit position. writing a 0 has no effect on the flag. an application reset will also clear the register. acs aggregated channel status (0128 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 sbv b cib ced b sed b vfr b 0 sbv a cia ced a sed a vfr a r rwhrwhrwhrwhrwh r rwhrwhrwhrwhrwh field bits type description vfra 0rwh valid frame received on channel a (vss!validframea) one or more valid frames were received on channel a in any static or dynamic slot during the observation period. 0 b no valid frame received 1 b valid frame(s) received on channel a seda 1rwh syntax error detected on channel a (vss!syntaxerrora) one or more syntax errors in st atic or dynamic slots, symbol window, and network idle time (nit) were observed on channel a. 0 b no syntax error observed 1 b syntax error(s) observed on channel a ceda 2rwh content error detected on channel a (vss!contenterrora) one or more frames with a content error were received on channel a in any static or dynamic slot during the observation period. 0 b no frame with content error received 1 b frame(s) with content error received on channel a www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-131 v1.1, 2011-03 e-ray, v3.12 cia 3rwh communication indicator channel a one or more valid frames were received on channel a in slots that also contained any additional communication during the observation period, i.e. one or more slots received a valid frame and had any combination of either syntax error or content error or slot boundary violation. 0 b no valid frame(s) received in slots containing any additional communication 1 b valid frame(s) received on channel a in slots containing any additional communication sbva 4rwh slot boundary violation on channel a (vss!bviolationa) one or more slot boundary violations were observed on channel a at any time during the observation period (static or dynamic slots, symbol window, and network idle time nit). 0 b no slot boundary violation observed 1 b slot boundary violation(s) observed on channel a vfrb 8rwh valid frame received on channel b (vss!validframeb) one or more valid frames were received on channel b in any static or dynamic slot during the observation period. 0 b no valid frame received 1 b valid frame(s) received on channel b sedb 9rwh syntax error detected on channel b (vss!syntaxerrorb) one or more syntax errors in st atic or dynamic slots, symbol window, and network idle time (nit) were observed on channel b. 0 b no syntax error observed 1 b syntax error(s) observed on channel b cedb 10 rwh content error detected on channel b (vss!contenterrorb) one or more frames with a content error were received on channel b in any static or dynamic slot during the observation period. 0 b no frame with content error received 1 b frame(s) with content error received on channel b field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-132 v1.1, 2011-03 e-ray, v3.12 note: the set condition of flags cia and cib is also fulfilled if there is only one single frame in the slot and the sl ot boundary at the end of t he slot is reached during the frames channel idle recognition phase. wh en one of the flags sedb, cedb, cib, sbvb changes from 0 to 1, service reques t flag eir.edb is set to 1.when one of the flags seda, ceda, cia, sbva changes from 0 to 1, service request flag eir.eda is set to 1. cib 11 rwh communication indicator channel b one or more valid frames were received on channel b in slots that also contained any additional communication during the observation period, i.e. one or more slots received a valid frame and had any combination of either syntax error or content error or slot boundary violation. 0 b no valid frame(s) received in slots containing any additional communication 1 b valid frame(s) received on channel b in slots containing any additional communication sbvb 12 rwh slot boundary violation on channel b (vss!bviolationb) one or more slot boundary violations were observed on channel b at any time during the observation period (static or dynamic slots, symbol window, and network idle time nit). 0 b no slot boundary violation observed 1 b slot boundary violation(s) observed on channel b 0 [7:5], [31:13] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-133 v1.1, 2011-03 e-ray, v3.12 even sync id [01 15] (esidnn) registers even sync id nn (esidnn, nn=01-15) hold the frame ids of the sync frames received in even communication cycles, sorted in ascending order, with register esid01 holding the lowest received sync frame id. if the node itself transmits a sync frame in an even communication cycle, register esid01 holds the respective sync frame id as configured in message buffer 0 and the flags rxea, rxeb are set. the value is updated during the network idle time (nit) of each even communication cycle. esidnn (nn = 01-15) even sync id symbol window nn (012c h + nn * 4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 rxe b rxe a 0eid rh rh r rh field bits type description eid [9:0] rh even sync id (vssyncidlista,b even) sync frame id even communication cycle. rxea 14 rh received/configured even sync id on channel a signals that a sync frame corresponding to the stored even sync id was received on channel a or that the node is configured to be a sync node with key slot = eid (esid1 only). 0 b sync frame not received on channel a / node configured to transmit sync frames 1 b sync frame received on channel a/ node not configured to transmit sync frames rxeb 15 rh received/configured even sync id on channel b signals that a sync frame corresponding to the stored even sync id was received on channel b or that the node is configured to be a sync node with key slot = eid (esid1 only). 0 b sync frame not received on channel b / node configured to transmit sync frames 1 b sync frame received on channel b / node not configured to transmit sync frames www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-134 v1.1, 2011-03 e-ray, v3.12 0 [13:10], [31:16] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-135 v1.1, 2011-03 e-ray, v3.12 odd sync id [01 15] (osidnn) he odd sync id nn (osidnn, nn=01-15) hold the frame ids of the sync frames received in odd communication cycles, sorted in asc ending order, with register osid01 holding the lowest received sync frame id. if the node itself transmits a sync frame in an odd communication cycle, register osid01 holds the respective sync frame id as configured in message buffer 0 and flags rxoa, rxob are set. the value is updated during the network idle time (nit ) of each odd communication cycle. osidnn (nn = 01-15) odd sync id symbol window nn(016c h + nn * 4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 rxo b rxo a 0oid rh rh r rh field bits type description oid [9:0] rh odd sync id (vssyncidlista,b odd) sync frame id even communication cycle. rxoa 14 rh received odd sync id on channel a signals that a sync frame corresponding to the stored odd sync id was received on channel a or that the node is configured to be a sync node with key slot = oid (osid1 only). 0 b sync frame not received on channel a/ node configured to transmit sync frames 1 b sync frame received on channel a/ node not configured to transmit sync frames rxob 15 rh received odd sync id on channel b signals that a sync frame corresponding to the stored odd sync id was received on channel b or that the node is configured to be a sync node with key slot = oid (osid1 only) 0 b sync frame not received on channel b/ node configured to transmit sync frames 1 b sync frame received on channel b/ node not configured to transmit sync frames www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-136 v1.1, 2011-03 e-ray, v3.12 0 [13:10], [31:16] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-137 v1.1, 2011-03 e-ray, v3.12 network management vector [1 3] (nmvx) the three network management vectors n (nmvx, x=1-3) registers hold the accrued network management (nm) vector (configurab le 0 to 12 byte). the accrued network management (nm) vector is generated by the communication controller by bit-wise oring each network management (nm) vector received (valid static frames with ppi = 1) on each channel (see ?network management? on page 26-222 ). the communication controller updates the network management (nm) vector at the end of each communication cycle as long as the communication controller is either in ?normal_active? or ?normal_passive? state. nmvx-bytes exceeding the configured network management (nm) vector length are not valid. table 26-5 below shows the assignment of the received payload?s data byte to the network management vector. nmvx (x = 1-3) network management vector x (01ac h + x * 4) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 nm rh field bits type description nm [31:0] rh network management vector table 26-5 assignment of data byte to network management vector bit word 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 nm1 data3 data2 data1 data0 nm2 data7 data6 data5 data4 nm3 data11 data10 data9 data8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-138 v1.1, 2011-03 e-ray, v3.12 26.5.2.6 message buffer control registers message ram configuration (mrc) the message ram configuration register defines the number of message buffers assigned to the static segment, dynamic segmen t, and fifo. the register can be written during ?default_config? or ?config? state only. mrc message ram configuration (0300 h ) reset value: 0180 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 sp lm sec lcb rrwrw rw 1514131211109876543210 ffb fdb rw rw field bits type description fdb [7:0] rw first dynamic buffer may be modified in ?default_config? or ?config? state only. 00 h no group of message buffers exclusively for the static segment configured 01 h ?7f h message buffers 0 to fdb-1 reserved for static segment 80 h ?ff h no dynamic message buffers configured ffb [15:8] rw first buffer of fifo may be modified in ?default_config? or ?config? state only. 00 h ?7e h message buffers from ffb to lcb assigned to the fifo 7f h all message buffers assigned to the fifo 80 h ?ff h no message buffers assigned to the fifo www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-139 v1.1, 2011-03 e-ray, v3.12 lcb [23:16] rw last configured buffer may be only modified in ?d efault_config? or ?config? state. 01 h ?7f h number of message buffers is lcb + 1 80 h ?ff h no message buffer configured sec [25:24] rw secure buffers not evaluated when the communication controller is in ?default_config? or ?config? state. for temporary unlocking see ?host handling of errors? on page 26-257 . 00 b reconfiguration of message buffers enabled with numbers < ffb enabled. note: in nodes configured for sync frame transmission or for single slot mode operation message buffer 0 (and if splm = 1, also message buffer 1) reconfiguration of all message buffers is always locked 01 b reconfiguration of message buffers with numbers < fdb and with numbers ffb locked and transmission of message buffers for static segment with numbers fdb disabled 10 b reconfiguration of all message buffers locked 11 b reconfiguration of all message buffers locked and transmission of message buffe rs for static segment with numbers fdb disabled splm 26 rw sync frame payload multiplex this bit is only evaluated if the node is configured as sync node (succ1.txsy = 1) or for single slot mode operation (succ1.tsm = 1). when this bit is set to 1 message buffers 0 and 1 are dedicated for sync frame transmission with different payload data on channel a and b. when this bit is reset to 0, sync frames are transmitted from message buffer 0 with the same payload data on both channels. note that the channel filter configuration for message buffer 0 resp. message buffer 1 has to be chosen accordingly. 0 b only message buffer 0 locked against reconfiguration 1 b both message buffers 0 and 1 are locked against reconfiguration field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-140 v1.1, 2011-03 e-ray, v3.12 note: in case the node is configured as sync node ( succ1 .txsy = 1) or for single slot mode operation ( succ1 .tsm = 1), message buffer 0 resp. 1 is reserved for sync frames or single slot frames a nd have to be configured with the node- specific key slot id. in case the node is neither configured as sync node nor for single slot operation message buffer 0 resp. 1 is treated like all other message buffers. the programmer has to ensure that the configuration defined by fdb, ffb, and lcb is valid. the communication controller does not check for erroneous configurations! note: the maximum number of header sections is 128. this means a maximum of 128 message buffer can be configured. the ma ximum length of a data section is 254 byte. the length of the data section may be configured differently for each message buffer. for details see ?message ram? on page 26-248 . in case two or more message buffers are assigned to slot 1 by use of cycle filtering, all of them must be located either in the ?static buffers? or at the beginning of the ?static + dynamic buffers? section. the payload length configured and the length of the data section need to be configured identically for all message buffers belonging to the fifo via wrhs2.plc and wrhs3.dp. when the communication controller is not in ?default_config? or ?config? state reconfiguration of message buffers belonging to the fifo is locked. 0 [31:27] r reserved returns 0 if read; should be written with 0. table 26-6 usage of the three message buffer pointer message buffer 0 ? static buffers message buffer 1 ? static + dynamic ? fdb buffers fifo configured: ffb > fdb ? fifo ? ffb no fifo configured: ffb 128 message buffer n-1 lcb fdb , lcb ffb message buffer n ? lcb field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-141 v1.1, 2011-03 e-ray, v3.12 fifo rejection filter (frf) the fifo rejection filter defines a user s pecified sequence of bits to which channel, frame id, and cycle count of the incoming frames are compared. together with the fifo rejection filter mask this register determines whether a message is rejected by the fifo. the frf register can be writte n during ?default_config? or ?config? state only. frf fifo rejection filter (0304 h ) reset value: 0180 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 rnf rss cyf rrwrwrw 1514131211109876543210 0fidch rrwrw field bits type description ch [1:0] rw channel filter may be modified in ?default_config? or ?config? state only. 00 b receive on both channels 1) 01 b receive only on channel b 10 b receive only on channel a 11 b no reception fid [12:2] rw frame id filter determines the frame id to be rejected by the fifo. with the additional configuration of register frfm, the corresponding frame id filter bits are ignored, which results in further rejected frame ids. when frfm.mfid is zero, a frame id filter value of zero means that no frame id is rejected. 000 h 7ff h frame id filter values www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-142 v1.1, 2011-03 e-ray, v3.12 cyf [22:16] rw cycle counter filter the 7-bit cycle counter filter de termines the cycle set to which frame id and channel rejection f ilter are applied. in cycles not belonging to the cycle set specified by cyf, all frames are rejected. for details about the c onfiguration of the cycle counter filter see ?cycle counter filtering? on page 26-224 . may be modified in ?default_config? or ?config? state only. rss 23 rw reject in static segment if this bit is set, the fifo is used only be used in dynamic segment. may be modified in ?default_config? or ?config? state only. 0 b fifo also used in static segment 1 b reject messages for static segment rnf 24 rw reject null frames if this bit is set, received null frames are not stored in the fifo. may be modified in ?def ault_config? or ?config? state only. 0 b null frames are stored in the fifo 1 b reject all null frames 0 [15:13], [31:25] r reserved returns 0 if read; should be written with 0. 1) if reception on both channels is configured, also in st atic segment always both frames (from channel a and b) are stored in the fifo, even if they are identical. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-143 v1.1, 2011-03 e-ray, v3.12 fifo rejection filter mask (frfm) the fifo rejection filter mask specifies which of the corresponding frame id filter bits are relevant for rejection filtering. if a bit is set, it indicates that the corresponding bit in the frf register will not be considered for rejection filtering. the frfm register can be written during ?default_config? or ?config? state only. frfm fifo rejection filter mask (0308 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 0mfid0 rrwr field bits type description mfid [12:2] rw mask frame id filter may be modified in ?default_config? or ?config? state only. 0 b corresponding frame id filter bit is used for rejection filtering. 1 b ignore corresponding frame id filter bit. 0 [1:0], [31:13] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-144 v1.1, 2011-03 e-ray, v3.12 fifo critical level (fcl) the communication controller accepts modifications of the register in ?default_config? or ?config? state only. fcl fifo critical level (030c h ) reset value: 0000 0080 h 313029282726252423222120191817161514131211109876543210 0cl rrw field bits type description cl [7:0] rw critical level when the receive fifo fill level fsr.rffl is equal or greater than the critical level configured by cl, the receive fifo critical level flag fsr.rfcl is set. if cl is programmed to values > 128, bit fsr.rfcl is never set. when fsr. rfcl changes from 0 to 1 bit sir . rfcl is set to 1, and if enabled, a service request is generated. 0 [31:8] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-145 v1.1, 2011-03 e-ray, v3.12 26.5.2.7 message buffer status registers message handler status (mhds) the message handler status register gives the host access to the current state of the message handler. a flag is cleared by writing a 1 to the corresponding bit position. writing a 0 has no effect on the flag. an application reset will also clear the register. if one of the flags mhds.eibf, mhds.eob f, mhds.emr, mhds.etbf1, mhds.etbf2 changes from 0 to 1 eir.eerr is set. mhds message handler status (0310 h ) reset value: 0000 0080 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0mbu0mbt rrhrrh 1514131211109876543210 0fmb cra m mfm b fmb d etb f2 etb f1 emr eob f eibf r rh rh rwhrwhrwhrwhrwhrwhrwh field bits type description eibf 0rwh ecc error input buffer ram 1,2 0 b no error 1 b error occurred when reading input buffer ram 1 or input buffer ram 2 eobf 1rwh ecc error output buffer ram 1,2 0 b no error 1 b error occurred when reading output buffer ram 1 or output buffer ram 2 emr 2rwh ecc error message ram 0 b no error 1 b error occurred when reading the message ram etbf1 3rwh ecc error transient buffer ram a 0 b no error 1 b error occurred when reading transient buffer ram a etbf2 4rwh ecc error transient buffer ram b 0 b no error 1 b error occurred when reading transient buffer ram b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-146 v1.1, 2011-03 e-ray, v3.12 fmbd 5rwh faulty message buffer detected 0 b no faulty message buffer 1 b message buffer referenced by mhds.fmb holds faulty data due to a ecc error mfmb 6rwh multiple faulty message buffers detected 0 b no additional faulty message buffer 1 b another faulty message buffer was detected while flag mhds.fmbd is set cram 7rh clear all internal ram?s signals that execution of the chi command clear_rams is ongoing (all bits of all internal ram blocks are written to 0). the bit is set by application reset or by chi command clear_rams. 0 b no execution of the chi command clear_rams 1 b execution of the chi command clear_rams ongoing fmb [14:8] rh faulty message buffer ecc error occurred when reading from the message buffer or when transferring data from input buffer or transient buffer a or transient buffer b to the message buffer referenced by mhds.fmb. value only valid when one of the flags mhds.eibf, mhds.emr, mhds.etbf1, mhds.etbf2, and flag mhds.fmbd is set. updated only after the host has reset flag mhds.fmbd. mbt [22:16] rh message buffer transmitted number of last successfully tran smitted message buffer. if the message buffer is configured for single-shot mode, the respective txr flag in the transmission request registers txrq1 to txrq4 was reset. mbt is reset when the communication controller leaves ?config? state or enters ?startup? state. mbu [30:24] rh message buffer updated number of message buffer that was updated last. for this message buffer the respective ndn (n = 0-31) to ndn (n = 96- 127)and / or mbcn (n = 0-31) to mbcn (n = 96-127) flag in the new data registers ndat1 to ndat4 and the message buffer status changed mbsc1 to mbsc4 registers are also set. mbu is reset when the communication controller leaves ?config? state or enters ?startup? state. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-147 v1.1, 2011-03 e-ray, v3.12 0 15, 23, 31 r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-148 v1.1, 2011-03 e-ray, v3.12 last dynamic transmit slot (ldts) the last dynamic transmit slot register stores the slot counter value at the time of the last frame transmission in the dynamic segment. this register is reset when the communication controller leaves ?config? state or enters ?startup? state. ldts last dynamic transmit slot (0314 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 0ldtb0ldta rrhrrh field bits type description ldta [10:0] rh last dynamic transmission channel a value of (vslotcounter[a]) at the time of the last frame transmission on channel a in the dynamic segment of this node. it is updated at the end of the dynamic segment and is reset to zero if no frame was transmitted during the dynamic segment. ldtb [26:16] rh last dynamic transmission channel b value of (vslotcounter[b]) at the time of the last frame transmission on channel b in the dynamic segment of this node. it is updated at the end of the dynamic segment and is reset to zero if no frame was transmitted during the dynamic segment. 0 [15:11], [31:27] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-149 v1.1, 2011-03 e-ray, v3.12 fifo status register (fsr) the register is reset when the communication controller leaves ?config? state or enters ?startup? state. fsr fifo status register (0318 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 rffl 0 rfo rfc l rfn e rh r rhrhrh field bits type description rfne 0rh receive fifo not empty this flag is set by the communication controller when a received valid frame (data or null frame depending on rejection mask) was stored in the fifo. in addition, service request flag sir.rfne is set. the bit is reset after the host has read all message from the fifo. 0 b receive fifo is empty 1 b receive fifo is not empty rfcl 1rh receive fifo critical level this flag is set when the receive fifo fill level rf fl is equal or greater than the critical level as configured by fcl.cl. the flag is cleared by the communication controller as soon as rffl drops below fcl.cl. when rfcl changes from 0 to 1 bit sir.rfcl is set to 1, and if enabled, an service request is generated. 0 b receive fifo below critical level 1 b receive fifo critical level reached www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-150 v1.1, 2011-03 e-ray, v3.12 rfo 2rh receive fifo overrun the flag is set by the communication controller when a receive fifo overrun is detected. when a receive fifo overrun occurs, the oldest message is overwritt en with the actual received message. in addition, service request flag eir.rfo is set.the flag is cleared by the next fifo read access issued by the host. 0 b no receive fifo overrun detected 1 b a receive fifo overrun has been detected rffl [15:8] rh receive fifo fill level number of fifo buffers filled up with new data not yet read by the host. maximum value is 128. 0 [7:3], [31:16] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-151 v1.1, 2011-03 e-ray, v3.12 message handler constraints flags (mhdf) some constraints exist for the message handler regarding f clc_eray frequency, message ram configuration, and flexray? bus traffic. to simplify software development, constraints violations are reported by setting flags in the mhdf. the register is reset when the communication c ontroller leaves ?config? state or enters ?startup? state. a flag is cleared by setting the corresponding bit position. clearing has no effect on the flag. if any flag in mhdfl is set, interrupt flag eir.mhf is set. mhdf message handler constraints flags (031c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 wah p tns b tns a tbf b tbf a fnf b fnf a snu b snu a r rwhrwhrwhrwhrwhrwhrwhrwhrwh field bits type description snua 0rwh status not updated channel a this flag is set by the communication controller when the message handler, due to overload condition, was not able to update a message buffer?s status mbs with respect to channel a. 0 b no overload condition occurred when updating mbs for channel a 1 b mbs for channel a not updated snub 1rwh status not updated channel b this flag is set by the communication controller when the message handler, due to overload condition, was not able to update a message buffer?s status mbs with respect to channel b. 0 b no overload condition occurred when updating mbs for channel b 1 b mbs for channel b not updated www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-152 v1.1, 2011-03 e-ray, v3.12 fnfa 2rwh find sequence not finished channel a this flag is set by the communication controller when the message handler, due to overload condition, was not able to finish a find sequence (scan of message ram for matching message buffer) with respect to channel a. 0 b no find sequence not finished for channel a 1 b find sequence not finished for channel a fnfb 3rwh find sequence not finished channel b this flag is set by the communication controller when the message handler, due to overload condition, was not able to finish a find sequence (scan of message ram for matching message buffer) with respect to channel b. 0 b no find sequence not finished for channel b 1 b find sequence not finished for channel b tbfa 4rwh transient buffer access failure a this flag is set by the communication controller when a read or write access to transient buffer a requested by prt a could not complete within the available time. 0 b no tbf a access failure 1 b tbf a access failure tbfb 5rwh transient buffer access failure b this flag is set by the communication controller when a read or write access to transient buffer b requested by prt b could not complete within the available time. 0 b no transient buffer b access failure 1 b transient buffer b access failure tnsa 6rwh transmission not started channel a this flag is set by the cc when the message handler was not ready to start a scheduled transmission on channel a at the action point of the configured slot. 0 b no transmission not started on channel a 1 b transmission not started on channel a tnsb 7rwh transmission not started channel b this flag is set by the cc when the message handler was not ready to start a scheduled transmission on channel b at the action point of the configured slot. 0 b no transmission not started on channel b 1 b transmission not started on channel b field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-153 v1.1, 2011-03 e-ray, v3.12 wahp 8rwh write attempt to header partition outside ?default_config? and ?config? state this flag is set by the communication controller when the message handler tries to write message data into the header partition of the message ram due to faulty configuration of a message buffer. the write attempt is not executed, to protect the header partition from unintended write accesses. 0 b no write attempt to header partition 1 b write attempt to header partition 0 [31:9] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-154 v1.1, 2011-03 e-ray, v3.12 transmission request 1 (txrq1) this register reflect the state of the txr flags of the configured message buffers 0 to 31. the flags are evaluated for transmit buffers only. if the number of configured message buffers is less than 31, the remaining txrn flags have no meaning and are read as 0. txrq1 transmission request register 1 (0320 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 txr 31 txr 30 txr 29 txr 28 txr 27 txr 26 txr 25 txr 24 txr 23 txr 22 txr 21 txr 20 txr 19 txr 18 txr 17 txr 16 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 txr 15 txr 14 txr 13 txr 12 txr 11 txr 10 txr 9 txr 8 txr 7 txr 6 txr 5 txr 4 txr 3 txr 2 txr 1 txr 0 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description txrn (n = 0-31) nrh transmission request n (n = 0-31) if the flag is set, the respective message buffer 0 to 31 is ready for transmission respectively transmission of this message buffer is in progress. in single-shot mode the flags are reset after transmission has completed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-155 v1.1, 2011-03 e-ray, v3.12 transmission request register 2 (txrq2) this register reflect the state of the txr flags of the configured message buffers 31 to 63. the flags are evaluated for transmit buffers only. if the number of configured message buffers is less than 63, the remaining txrn flags have no meaning and are read as 0. txrq2 transmission request register 2 (0324 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 txr 63 txr 62 txr 61 txr 60 txr 59 txr 58 txr 57 txr 56 txr 55 txr 54 txr 53 txr 52 txr 51 txr 50 txr 49 txr 48 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 txr 47 txr 46 txr 45 txr 44 txr 43 txr 42 txr 41 txr 40 txr 39 txr 38 txr 37 txr 36 txr 35 txr 34 txr 33 txr 32 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description txrn (n = 32-63) n - 32 rh transmission request n (n = 32-63) if the flag is set, the respective message buffer 32 to 63 is ready for transmission respectively transmission of this message buffer is in progress. in single-shot mode the flags are reset after transmission has completed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-156 v1.1, 2011-03 e-ray, v3.12 transmission request register 3 (txrq3) this register reflect the state of the txr flags of the configured message buffers 64 to 95. the flags are evaluated for transmit buffers only. if the number of configured message buffers is less than 95, the remaining txrn flags have no meaning and are read as 0. txrq3 transmission request register 3 (0328 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 txr 95 txr 94 txr 93 txr 92 txr 91 txr 90 txr 89 txr 88 txr 87 txr 86 txr 85 txr 84 txr 83 txr 82 txr 81 txr 80 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 txr 79 txr 78 txr 77 txr 76 txr 75 txr 74 txr 73 txr 72 txr 71 txr 70 txr 69 txr 68 txr 67 txr 66 txr 65 txr 64 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description txrn (n = 64-95) n - 64 rh transmission request n (n = 64-95) if the flag is set, the respective message buffer 64 to 95 is ready for transmission respectively transmission of this message buffer is in progress. in single-shot mode the flags are reset after transmission has completed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-157 v1.1, 2011-03 e-ray, v3.12 transmission request register 4 (txrq4) this register reflect the state of the txr flags of the configured message buffers 96 to 127. the flags are evaluated for transmit buffers only. if the number of configured message buffers is less than 127, the remaining txrn flags have no meaning and are read as 0. txrq4 transmission request register 4 (032c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 txr 127 txr 126 txr 125 txr 124 txr 123 txr 122 txr 121 txr 120 txr 119 txr 118 txr 117 txr 116 txr 115 txr 114 txr 113 txr 112 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 txr 111 txr 110 txr 109 txr 108 txr 107 txr 106 txr 105 txr 104 txr 103 txr 102 txr 101 txr 100 txr 99 txr 98 txr 97 txr 96 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description txrn (n = 96-127) n - 96 rh transmission request n (n = 96-127) if the flag is set, the respective message buffer 96 to 127 is ready for transmission respectively transmission of this message buffer is in progress. in single-shot mode the flags are reset after transmission has completed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-158 v1.1, 2011-03 e-ray, v3.12 new data register 1 (ndat1) this register reflect the state of the nd flags of all configured message buffers 0 to 31. nd flags assigned to transmit buffers are meaningless. if the number of configured message buffers is less than 31, the remaining ndn flags have no meaning. the registers are reset when the communication co ntroller leaves ?config? state or enters ?startup? state. ndat1 new data register 1 (0330 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nd 31 nd 30 nd 29 nd 28 nd 27 nd 26 nd 25 nd 24 nd 23 nd 22 nd 21 nd 20 nd 19 nd 18 nd 17 nd 16 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 nd 15 nd 14 nd 13 nd 12 nd 11 nd 10 nd9 nd8 nd7 nd6 nd5 nd4 nd3 nd2 nd1 nd0 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description ndn (n = 0-31) nrh new data n (n = 0-31) the flags are set when a valid received data frame matches the message buffer?s filter configuration, independent of the payload length received or the payload length configured for that message buffer. the flags are not set after reception of null frames except for message buffers belonging to the receive fifo. an nd flag is reset when the header section of the corresponding message buffer is reconfigured or when the data section has been transferred to the output buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-159 v1.1, 2011-03 e-ray, v3.12 new data register 2 (ndat2) this register reflect the state of the nd flags of all configured message buffers 32 to 63. nd flags assigned to transmit buffers are meaningless. if the number of configured message buffers is less than 63, the remaining ndn flags have no meaning. the registers are reset when the communication co ntroller leaves ?config? state or enters ?startup? state. ndat2 new data register 2 (0334 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nd 63 nd 62 nd 61 nd 60 nd 59 nd 58 nd 57 nd 56 nd 55 nd 54 nd 53 nd 52 nd 51 nd 50 nd 49 nd 48 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 nd 47 nd 46 nd 45 nd 44 nd 43 nd 42 nd 41 nd 40 nd 39 nd 38 nd 37 nd 36 nd 35 nd 34 nd 33 nd 32 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description ndn (n = 32-63) n - 32 rh new data n (n = 32-63) the flags are set when a valid received data frame matches the message buffer?s filter configuration, independent of the payload length received or the payload length configured for that message buffer. the flags are not set after reception of null frames except for message buffers belonging to the receive fifo. an nd flag is reset when the header section of the corresponding message buffer is reconfigured or when the data section has been transferred to the output buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-160 v1.1, 2011-03 e-ray, v3.12 new data register 3 (ndat3) this register reflect the state of the nd flags of all configured message buffers 64 to 95. nd flags assigned to transmit buffers are meaningless. if the number of configured message buffers is less than 95, the remaining ndn flags have no meaning. the registers are reset when the communication co ntroller leaves ?config? state or enters ?startup? state. ndat3 new data register 3 (0338 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nd 95 nd 94 nd 93 nd 92 nd 91 nd 90 nd 89 nd 88 nd 87 nd 86 nd 85 nd 84 nd 83 nd 82 nd 81 nd 80 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 nd 79 nd 78 nd 77 nd 76 nd 75 nd 74 nd 73 nd 72 nd 71 nd 70 nd 69 nd 68 nd 67 nd 66 nd 65 nd 64 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description ndn (n = 64-95) n - 64 rh new data n (n = 64-95) the flags are set when a valid received data frame matches the message buffer?s filter configuration, independent of the payload length received or the payload length configured for that message buffer. the flags are not set after reception of null frames except for message buffers belonging to the receive fifo. an nd flag is reset when the header section of the corresponding message buffer is reconfigured or when the data section has been transferred to the output buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-161 v1.1, 2011-03 e-ray, v3.12 new data register 4 (ndat4) this register reflect the state of the nd flags of all configured message buffers 96 to 127. nd flags assigned to transmit buffers are meaningless. if the number of configured message buffers is less than 127, the remaining ndn flags have no meaning. the registers are reset when the communication co ntroller leaves ?config? state or enters ?startup? state. ndat4 new data register 4 (033c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nd 127 nd 126 nd 125 nd 124 nd 123 nd 122 nd 121 nd 120 nd 119 nd 118 nd 117 nd 116 nd 115 nd 114 nd 113 nd 112 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 nd 111 nd 110 nd 109 nd 108 nd 107 nd 106 nd 105 nd 104 nd 103 nd 102 nd 101 nd 100 nd 99 nd 98 nd 97 nd 96 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description ndn (n = 96-127) n - 96 rh new data n (n = 96-127) the flags are set when a valid received data frame matches the message buffer?s filter configuration, independent of the payload length received or the payload length configured for that message buffer. the flags are not set after reception of null frames except for message buffers belonging to the receive fifo. an nd flag is reset when the header section of the corresponding message buffer is reconfigured or when the data section has been transferred to the output buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-162 v1.1, 2011-03 e-ray, v3.12 message buffer status changed 1 (mbsc1) this register reflect the state of the mbc flags of all configured message buffers. if the number of configured message buffers is less than 31, the remaining mbcn flags have no meaning. the register is reset when the communication controller leaves ?config? state or enters ?startup? state. mbsc1 message buffer status changed 1 (0340 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mbc 31 mbc 30 mbc 29 mbc 28 mbc 27 mbc 26 mbc 25 mbc 24 mbc 23 mbc 22 mbc 21 mbc 20 mbc 19 mbc 18 mbc 17 mbc 16 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 mbc 15 mbc 14 mbc 13 mbc 12 mbc 11 mbc 10 mbc 9 mbc 8 mbc 7 mbc 6 mbc 5 mbc 4 mbc 3 mbc 2 mbc 1 mbc 0 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description mbcn (n = 0-31) nrh message buffer status changed n (n = 0-31) an mbc flags is set whenever the message handler changes on of the status flags vfra, vfrb, seoa, seob, ceoa, ceob, svoa, svob, tcia, tcib, esa, esb, mlst, fta, ftb in the header section (see ?message buffer status (mbs)? on page 26-186 ) of the respective message buffer 0 to message buffer 31. the flags are reset when the header section of the message buffer is reconfigured or when it has been transferred to the output buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-163 v1.1, 2011-03 e-ray, v3.12 message buffer status changed 2 (mbsc2) this register reflect the state of the mbc flags of all configured message buffers. if the number of configured message buffers is less than 63, the remaining mbcn flags have no meaning. the register is reset when the communication controller leaves ?config? state or enters ?startup? state. mbsc2 message buffer status changed 2 (0344 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mbc 63 mbc 62 mbc 61 mbc 60 mbc 59 mbc 58 mbc 57 mbc 56 mbc 55 mbc 54 mbc 53 mbc 52 mbc 51 mbc 50 mbc 49 mbc 48 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 mbc 47 mbc 46 mbc 45 mbc 44 mbc 43 mbc 42 mbc 41 mbc 40 mbc 39 mbc 38 mbc 37 mbc 36 mbc 35 mbc 34 mbc 33 mbc 32 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description mbcn (n = 32-63) n - 32 rh message buffer status changed n (n = 32-63) an mbc flags is set whenever the message handler changes on of the status flags vfra, vfrb, seoa, seob, ceoa, ceob, svoa, svob, tcia, tcib, esa, esb, mlst, fta, ftb in the header section (see ?message buffer status (mbs)? on page 26-186 ) of the respective message buffer 32 to message buffer 63. the flags are reset when the header section of the message buffer is reconfigured or when it has been transferred to the output buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-164 v1.1, 2011-03 e-ray, v3.12 message buffer status changed 3 (mbsc3) this register reflect the state of the mbc flags of all configured message buffers. if the number of configured message buffers is less than 95, the remaining mbcn flags have no meaning. the register is reset when the communication controller leaves ?config? state or enters ?startup? state. mbsc3 message buffer status changed 3 (0348 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mbc 95 mbc 94 mbc 93 mbc 92 mbc 91 mbc 90 mbc 89 mbc 88 mbc 87 mbc 86 mbc 85 mbc 84 mbc 83 mbc 82 mbc 81 mbc 80 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 mbc 79 mbc 78 mbc 77 mbc 76 mbc 75 mbc 74 mbc 73 mbc 72 mbc 71 mbc 70 mbc 69 mbc 68 mbc 67 mbc 66 mbc 65 mbc 64 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description mbcn (n = 64-95) n - 64 rh message buffer status changed n (n = 64-95) an mbc flags is set whenever the message handler changes on of the status flags vfra, vfrb, seoa, seob, ceoa, ceob, svoa, svob, tcia, tcib, esa, esb, mlst, fta, ftb in the header section (see ?message buffer status (mbs)? on page 26-186 ) of the respective message buffer 64 to message buffer 95. the flags are reset when the header section of the message buffer is reconfigured or when it has been transferred to the output buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-165 v1.1, 2011-03 e-ray, v3.12 message buffer status changed 4 (mbsc4) this register reflect the state of the mbc flags of all configured message buffers. if the number of configured message buffers is less than 127, the remaining mbcn flags have no meaning. the register is reset when the communication controller leaves ?config? state or enters ?startup? state. mbsc4 message buffer status changed 4 (034c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mbc 127 mbc 126 mbc 125 mbc 124 mbc 123 mbc 122 mbc 121 mbc 120 mbc 119 mbc 118 mbc 117 mbc 116 mbc 115 mbc 114 mbc 113 mbc 112 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh 1514131211109876543210 mbc 111 mbc 110 mbc 109 mbc 108 mbc 107 mbc 106 mbc 105 mbc 104 mbc 103 mbc 102 mbc 101 mbc 100 mbc 99 mbc 98 mbc 97 mbc 96 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh field bits type description mbcn (n = 96-127) n - 96 rh message buffer status changed n (n = 96-127) an mbc flags is set whenever the message handler changes on of the status flags vfra, vfrb, seoa, seob, ceoa, ceob, svoa, svob, tcia, tcib, esa, esb, mlst, fta, ftb in the header section (see ?message buffer status (mbs)? on page 26-186 ) of the respective message buffer 96 to message buffer 127. the flags are reset when the header section of the message buffer is reconfigured or when it has been transferred to the output buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-166 v1.1, 2011-03 e-ray, v3.12 26.5.2.8 identifi cation registers core release register (crel) this register contains bit fields about the eray module identification. it is read only. crel core release register (03f0 h ) reset value: xxxx xxxx h 313029282726252423222120191817161514131211109876543210 rel step sub step year mon day rrrr r field bits type description day [7:0] r design time stamp, day two digits, bcd-coded. mon [15:8] r design time stamp, month two digits, bcd-coded. year [19:16] r design time stamp, year one digit, bcd-coded. substep [23:20] r sub-step of core release one digits, bcd-coded. 0 h alpha, pre-beta, pre-beta-update, pre-beta2, pre- beta2-update, beta, beta2, revision 1.0.0 1 h beta_ct, beta-ct-fix1, revision 1.0.1 2 h revision1.0rc1,beta-ct-fix2, revision 1.0rc1 step [27:24] r step of core release one digits, bcd-coded. 0 h revision 1.0.0 1 h alpha 2 h pre-beta 3 h pre-beta-update 4 h pre-beta2 5 h pre-beta2-update 6 h beta 7 h beta2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-167 v1.1, 2011-03 e-ray, v3.12 rel [31:28] r core release one digit, bcd-coded. 0 b alpha?beta2ct 1 b revision 1.0 table 26-7 coding of releases release step sub-step name release date 010 alpha 020 pre-beta 0 3 0 pre-beta-update 0 4 0 pre-beta2 0 5 0 pre-beta2-update 060 beta 0 6 1 beta-ct-fix1 14.10.2005 0 6 2 beta-ct-fix2 14.12.2005 0 7 0 beta2 03.02.2006 0 7 1 beta2ct 24.03.2006 0 7 2 revision 1.0rc1 07.04.2006 1 0 0 release 1.0.0 19.05.2006 1 0 1 release 1.0.1 2006 1 0 2 release 1.0.2 31.10.2007 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-168 v1.1, 2011-03 e-ray, v3.12 endian register (endn) this register may be used to check, if the data of the e-ray is handled by a host with the correct endian format. it is read only. 26.5.2.9 input buffer double buffer structure consisting of input buffer host and input buffer shadow. while the host can write to input buffer host, the transfer to the message ram is done from input buffer shadow. the input buffer holds the header and data sections to be transferred to the selected message buffer in the message ram. it is used to configure the message buffers in the message ram and to update the data sections of transmit buffers. when updating the header section of a message buffer in the message ram from the input buffer, the message buffer status as described in ?message buffer status (mbs)? on page 26-186 is automatically reset to zero. the header sections of message buffers belonging to the receive fifo can only be (re)configured when the communication co ntroller is in ?default_config? or ?config? state. for those message buffers only the payload length configured and the data pointer need to be configured via wrhs2.plc and wrhs2.dp. all information required for acceptance filtering is taken from the fifo rejection filter and the fifo rejection filter mask. the data transfer between input buffer (ibf) and message ram is described in detail in ?data transfer from input buffer to message ram? on page 26-233 . endn endian register (003f4 h ) reset value: 8765 4321 h 313029282726252423222120191817161514131211109876543210 etv r field bits type description etv [31:0] r endianness test value the endianness test value. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-169 v1.1, 2011-03 e-ray, v3.12 write data section [01 - 64] (wrdsnn (nn = 01-64)) the write data section (wrdsnn, nn = 01-64) holds the data words to be transferred to the data section of the addressed message buffer. the data words (dw n ) are written to the message ram in transmission order from dw1 (byte0, byte1) to dw pl (pl = number of data words as defined by the payload length configured by wrhs2.plc). note: 16-bit word 127 is located on wrds64.mdw. in this case wrds64.mdw is unused (no valid data). the input buffer ra ms are initialized to zero when leaving application reset or by chi command clear_rams. note: when writing to the wrdsnn (nn = 01-64), each 32-bit word has to be filled up by one 32-bit access or two consecutive 16- bit accesses or four consecutive 8-bit accesses before the transfer from the input buffer to the message ram is started by writing the number of t he target message buffer in the message ram to the input buffer command request register. if a 32-bit word of the input buffer has been filled with less then tw o consecutive 16-bit accesses or four consecutive 8- bit accesses (less then 32-bit), random data is transferred into the input buffer for every not written 16-bit or 8-bit of a 32-bit word. wrdsnn (nn = 01-64) write data section nn (03fc h + nn * 4) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 mdwbnn3 mdwbnn2 mdwbnn1 mdwbnn0 rw rw rw rw field bits type description mdwb0 [7:0] rw 32-bit word nn, byte 0 mdwb1 [15:8] rw 32-bit word nn, byte 1 mdwb2 [23:16] rw 32-bit word nn, byte 2 mdwb3 [31:24] rw 32-bit word nn, byte 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-170 v1.1, 2011-03 e-ray, v3.12 write header section 1 (wrhs1) wrhs1 write header section 1 (0500 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 mbi txm ppit cfg chb cha 0 cyc r rwrwrwrwrwrw r rw 1514131211109876543210 0fid rrw field bits type description fid [10:0] rw frame id frame id of the selected message buffer. the frame id defines the slot number for transmission / reception of the respective message. message buffers with fr ame id = 0 are considered as not valid. cyc [22:16] rw cycle code the 7-bit cycle code determines the cycle set used for cycle counter filtering. for details about the co nfiguration of the cycle code see section 26.6.7.3 . cha 24 rw channel filter control a the channel filtering field a associated with the buffer serves of channel a as a filter for receive buffers, and as a control field for transmit buffers chb 25 rw channel filter control b the channel filtering field b associated with the buffer serves of channel b as a filter for receive buffers, and as a control field for transmit buffers cfg 26 rw message buffer direction configuration bit this bit is used to configure the corresponding buffer as a transmit buffer or as a rece ive buffer. for message buffers belonging to the receive fifo the bit is not evaluated. 0 b the corresponding buffer is configured as receive buffer 1 b the corresponding buffer is configured as transmit buffer www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-171 v1.1, 2011-03 e-ray, v3.12 note: the input buffer rams are initialized to zero when leaving application reset or by chi command clear_rams. note that only the currently active ibf bank is cleared. to clear the 2nd bank as well, cust1.ibf1pag and cust1.ibf2pag need to be set and command clear_rams need to be issued again. this is required in particular after an application reset. if the 2nd bank of ibf is left unused, this procedure is not required. ppit 27 rw payload preamble indicator transmit this bit is used to control the state of the payload preamble indicator in transmit frames. if the bit is set in a static message buffer, the respective message buffer holds network management information. if the bit is set in a dynamic message buffer the first two byte of the payload segment may be used for message id filtering by the receiver. message id filtering of received flexray? frames is not supported by the e-ray module, but can be done by the host. 0 b payload preamble indicator not set 1 b payload preamble indicator set txm 28 rw transmission mode this bit is used to select the transmission mode (see ?transmit buffers? on page 26-226 ). 0 b continuous mode 1 b single-shot mode mbi 29 rw message buffer service request this bit enables the receive / transmit service request for the corresponding message buffer. after a dedicated receive buffer has been updated by the message handler, flag sir.rxi and /or sir.mbsi in the status service request register are set. after a transmission has completed flag sir.txi is set. 0 b the corresponding message buffer service request is disabled 1 b the corresponding message buffer service request is enabled 0 [15:11], 23, [31:30] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-172 v1.1, 2011-03 e-ray, v3.12 table 26-8 channel filter control bits cha chb transmit buffer transmit frame on receive buffer store frame received from 1 1) 1) if a message buffer is configured for the dynamic segmen t and both bits of the channel filtering field are set to 1, no frames are transmitted resp. received fram es are ignored (same function as cha = chb = 0) 1 1) both channels (static segment only) channel a or b (store first semantically valid frame, static segment only) 1 0 channel a channel a 0 1 channel b channel b 0 0 no transmission ignore frame www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-173 v1.1, 2011-03 e-ray, v3.12 write header section 2 (wrhs2) wrhs2 write header section 2 (0504 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 0 plc 0 crc rrwrrw field bits type description crc [10:0] rw header crc (vrf!header!headercrc) receive buffer: configuration not required transmit buffer: header crc calculated and configured by the host. for calculation of the header crc the payload length of the frame send on the bus has to be considered. in static segment the payload length of all frames is configured by mhdc.sfdl. plc [22:16] rw payload length configured length of data section (number of 2-byte words) as configured by the host. during static segment the static frame payload length as configured by mhdc.sfdl in the mhd configuration register defines the payload length for all static frames. if the payload length configured by plc is shorter than this value padding byte are inserted to ens ure that frames have proper physical length. the padding pattern is logical zero. 0 [15:11], [31:23] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-174 v1.1, 2011-03 e-ray, v3.12 write header section 3 (wrhs3) wrhs3 write header section 3 (0508 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 0dp rrw field bits type description dp [10:0] rw data pointer pointer to the first 32-bit word of the data section of the addressed message buffer in the message ram. 0 [31:11] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-175 v1.1, 2011-03 e-ray, v3.12 input buffer comma nd mask (ibcm) configures how the message buffer in the message ram selected by the input buffer command request register ibcr is updated. if ibf host and ibf shadow are swapped, also masked bits ibcm.lhsh, ibcm.lds h, and ibcm.stxrh are swapped with bits ibcm.lhss, ibcm.ldss, and ibcm.stxrs to keep them attached to the respective input buffer transfer. ibcm input buffer command mask (0510 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 stx rs ld ss lh ss r rhrhrh 1514131211109876543210 0 stx rh ld sh lh sh rrwhrwhrwh field bits type description lhsh 0rwh load header section host 0 b header section is not updated 1 b header section selected for transfer from input buffer to the message ram ldsh 1rwh load data section host 0 b data section is not updated 1 b data section selected for transfer from input buffer to the message ram stxrh 2rwh set transmission request host if this bit is set to 1, the transmission request flag txrq1.txrn (n = 0-31) to txrq4.txrn (n = 0-31) for the selected message buffer is set in the transmission request registers to release the message buffer for transmission. in single-shot mode the flag is cleared by the communication controller after transmission has completed. txrq1.txrn (n = 0-31) to txrq4.txrn (n = 0-31) are evaluated for transmit buffer only. 0 b reset transmission request flag 1 b set transmission request flag, transmit buffer released for transmission www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-176 v1.1, 2011-03 e-ray, v3.12 lhss 16 rh load header section shadow 0 b header section is not updated 1 b header section selected for transfer from input buffer to the message ram (transfer is ongoing of finalized) ldss 17 rh load data section shadow 0 b data section is not updated 1 b data section selected for transfer from input buffer to the message ram (transfer is ongoing of finalized) stxrs 18 rh transmission request shadow if this bit is set to 1, the transmission request flag txrq1.txrn (n = 0-31) to txrq4.txrn (n = 0-31) for the selected message buffer is set in the transmission request registers to release the message buffer for transmission. in single-shot mode the flag is cleared by the communication controller after transmission has completed. txrq1.txrn (n = 0-31) to txrq4.txrn (n = 0-31) are evaluated for transmit buffer only. 0 b reset transmission request flag 1 b set transmission request flag, transmit buffer released for transmission (operation is ongoing of finalized) 0 [15:3], [31:19] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-177 v1.1, 2011-03 e-ray, v3.12 input buffer command request (ibcr) when the host writes the number of the target message buffer in the message ram to ibrh in the input buffer command request register, ibf host and ibf shadow are swapped. in addition the message buffer numbers stored under ibrh and ibrs are also swapped (see also ?data transfer from input buffer to message ram? on page 26-233 ). with this write opera tion the ibsys bit in th e input buffer command request register is set to 1. the message handler then starts to transfer the contents of ibf shadow to the message buffer in the message ram selected by ibrs. while the message handler transfers the data from ibf shadow to the target message buffer in the message ram, the host may write the next message into the ibf host. after the transfer between ibf shadow and the message ram has completed, the ibsys bit is set back to 0 and the next transfer to the message ram may be started by the host by writing the respective target message buffer number to ibrh. if a write access to ibrh occurs while ibsys is 1, ibsyh is set to 1. after completion of the ongoing data transfer from ibf shadow to the message ram, ibf host and ibf shadow are swapped, i bsyh is reset to 0. ibsys remains set to 1, and the next transfer to the message ram is started. in addition the message buffer numbers stored under ibrh and ibrs are also swapped. any write access to an input buffer register while both ibsys and ibsyh are set will cause the error fl ag eir.iiba to be set. in this case the input buffer will not be changed. ibcr input buffer command request (0514 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ib sys 0 ibrs rh r rh 1514131211109876543210 ib syh 0ibrh rh r rwh field bits type description ibrh [6:0] rwh input buffer request host selects the target message buffer in the message ram for data transfer from input buffer. valid values are 00 h to 7f h (0 127). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-178 v1.1, 2011-03 e-ray, v3.12 ibsyh 15 rh input buffer busy host set to 1 by writing ibrh while i bsys is still 1. after the ongoing transfer between ibf shadow and the message ram has completed, the ibsyh is set back to 0. 0 b no request pending 1 b request while transfer between ibf shadow and message ram in progress ibrs [22:16] rh input buffer request shadow number of the target message buffer actually updated/lately updated. valid values are 00 h to 7f h (0 127). ibsys 31 rh input buffer busy shadow set to 1 after writing ibrh. when the transfer between ibf shadow and the message ram has completed, ibsys is set back to 0. 0 b transfer between ibf shadow and message ram completed 1 b transfer between ibf shadow and message ram in progress 0 [14:7], [30:23] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-179 v1.1, 2011-03 e-ray, v3.12 26.5.2.10 output buffer double buffer structure consisting of output buffer host and output buffer shadow. used to read out message buffers from the message ram. while the host can read from output buffer host, the message handler transfers the selected message buffer from message ram to the respective output buffer shadow. the data transfer between message ram and output buffer (obf) is described in ?data transfer from message ram to output buffe r? on page 26-235 . read data section [1 64] (rddsn) the read data section nn (rddsnn, nn = 01-64) holds the data words read from the data section of the addressed message buffer. the data words are read from the message ram in reception order from dw1 (byte0, byte1) to dw pl (pl = number of data words as defined by the payload length). note: dw127 is located on rdds64.mdw. in this case rdds64.mdw is unused (no valid data). the output buffer rams are initialized to zero when leaving application reset or by chi command clear_rams. rddsnn (nn = 01-64) read data section nn (05fc h + nn * 4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mdrb3 mdrb2 rh rh 1514131211109876543210 mdrb1 mdrb0 rh rh field bits type description mdrb0 [7:0] rh 32-bit word nn, byte 0 mdrb1 [15:8] rh 32-bit word nn, byte 1 mdrb2 [23:16] rh 32-bit word nn, byte 2 mdrb3 [31:24] rh 32-bit word nn, byte 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-180 v1.1, 2011-03 e-ray, v3.12 read header section 1 (rdhs1) values as configured by the host via wrhs1 register: note: in case that the message buffer read from the message ram belongs to the receive fifo, fid holds the received frame id, while cyc, cha, chb, cfg, ppit, txm, and mbi are reset to zero. rdhs1 read header section 1 (0700 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 mbi txm ppit cfg chb cha 0 cyc r rhrhrhrhrhrh r rh 1514131211109876543210 0fid rrh field bits type description fid [10:0] rh frame id cyc [22:16] rh cycle code cha 24 rh channel filter control a chb 25 rh channel filter control b cfg 26 rh message buffer direction configuration bit ppit 27 rh payload preamble indicator transmit txm 28 rh transmission mode mbi 29 rh message buffer service request 0 [15:11], 23, [31:30] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-181 v1.1, 2011-03 e-ray, v3.12 table 26-9 channel filter control bits cha chb transmit buffer transmit frame on receive buffer store frame received from 1 1) 1) if a message buffer is configured for the dynamic segmen t and both bits of the channel filtering field are set to 1, no frames are transmitted resp. received fram es are ignored (same function as cha = chb = 0) 1 1) both channels (static segment only) channel a or b (store first semantically valid frame, static segment only) 1 0 channel a channel a 0 1 channel b channel b 0 0 no transmission ignore frame www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-182 v1.1, 2011-03 e-ray, v3.12 read header section 2 (rdhs2) rdhs2 read header section 2 (0704 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0plr0plc rrhrrh 1514131211109876543210 0crc rrh field bits type description crc [10:0] rh header crc (vrf!header!headercrc) receive buffer: configuration not required. header crc updated from receive data frames. transmit buffer: header crc calculated and configured by the host plc [22:16] rh payload length configured length of data section (number of 2-byte words) as configured by the host. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-183 v1.1, 2011-03 e-ray, v3.12 note: the message ram is organized in 4-byte words. when received data is stored into a message buffer?s data section, the number of 2-byte data words written into the message buffer is plc rounded to the next even value. plc should be configured identical for all message buffer s belonging to the receive fifo. header 2 is updated from data frames only. plr [30:24] rh payload length received (vrf!header!length) payload length value updated from received data frame (exception: if message buffer belongs to the receive fifo plr is also updated from received null frames). when a message is stored into a message buffer the following behavior with respect to payload length received and payload length configured is implemented: ? plr > plc: the payload data stored in the message buffer is truncated to the payload length configured for even plc or else truncated to plc + 1. ? plr plc: the received payload data is stored into the message buffers data section. the remaining data bytes of the data section as configured by plc are filled with undefined data. ? plr = 0: the message buffer?s data section is filled with undefined data. ? plc = 0: message buffer has no data section configured. no data is stored into the message buffer?s data section. 0 [15:11], 23, 31 r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-184 v1.1, 2011-03 e-ray, v3.12 read header section 3 (rdhs3) rdhs3 read header section 3 (0708 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 res ppi nfi syn sfi rci 0 rcc r rhrhrhrhrhrh r rh 1514131211109876543210 0dp rrh field bits type description dp [10:0] rh data pointer pointer to the first 32-bit word of the data section of the addressed message buffer in the message ram. rcc [21:16] rh receive cycle count (vrf!header!cyclecount) cycle counter value updated from received data frame. rci 24 rh received on channel indicator (vss!channel) indicates the channel from which the received data frame was taken to update the respective receive buffer. 0 b frame received on channel b 1 b frame received on channel a sfi 25 rh startup frame indicator (vrf!header!sufindicator) a startup frame is marked by the startup frame indicator. 0 b the received frame is not a startup frame 1 b the received frame is a startup frame syn 26 rh sync frame indicator (vrf!header!syfindicator) a sync frame is marked by the sync frame indicator. 0 b the received frame is not a sync frame 1 b the received frame is a sync frame nfi 27 rh null frame indicator (vrf!header!nfindicator) is set to 1 after storage of the first received data frame. 0 b up to now no data frame has been stored into the respective message buffer 1 b at least one data frame has been stored into the respective message buffer www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-185 v1.1, 2011-03 e-ray, v3.12 note: header 3 is updated from data frames only. ppi 28 rh payload preamble indicator (vrf!header!ppindicator) the payload preamble indicator defines whether a network management vector or message id is contained within the payload segment of the received frame. 0 b the payload segment of the received frame does not contain a network management vector nor a message id 1 b static segment: network management vector in the first part of the payload dynamic segment: message id in the first part of the payload res 29 rh reserved bit (vrf!header!reserved) reflects the state of the received reserved bit. the reserved bit is transmitted as 0. 0 [15:11], [23:22], [31:30] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-186 v1.1, 2011-03 e-ray, v3.12 message buffer status (mbs) the message buffer status is updated by the communication controller with respect to the assigned channel(s) latest at the end of the slot following the slot assigned to the message buffer. the flags are updated only when the communication controller is in ?normal_active? or ?normal_passive? state. if only one channel (a or b) is assigned to a message buffer, the channel-speci fic status flags of the other channel are written to zero. if both channels are assigned to a message buffer, the channel-specific status flags of both channels are updated. the message buffer status is updated only when the slot counter reached the configured frame id and when the cycle counter filter matched. when the host updates a message buffer via input buffer, all mbs flags are reset to zero independent of which ibcm bits are set or not. for details about receive / transmit filtering see ?filtering and masking? on page 26-222 , ?transmit process? on page 26-226 , and ?receive process? on page 26-229 . whenever the message handler changes one of the flags vfra, vfrb, seoa, seob, ceoa, ceob, svoa, svob, tcia, tcib, esa, esb, mlst, fta, ftb the respective message buffer?s mbc flag in registers mbsc1 to mbsc4 is set mbs message buffer status (070c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 res s ppis nfis syn s sfis rcis 0 ccs r rhrhrhrhrhrh r rh 1514131211109876543210 ftb fta 0 ml st esb esa tcib tcia sv ob sv oa ce ob ce oa se ob se oa vr fb vr fa rhrh r rhrhrhrhrhrhrhrhrhrhrhrhrh field bits type description vfra 0rh valid frame received on channel a (vss!validframea) a valid frame indication is set if a valid frame was received on channel a. 0 b no valid frame received on channel a 1 b valid frame received on channel a vfrb 1rh valid frame received on channel b (vss!validframeb) a valid frame indication is set if a valid frame was received on channel b. 0 b no valid frame received on channel b 1 b valid frame received on channel b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-187 v1.1, 2011-03 e-ray, v3.12 seoa 2rh syntax error observed on channel a (vss!syntaxerrora) a syntax error was observed in the assigned slot on channel a. 0 b no syntax error observed on channel a 1 b syntax error observed on channel a seob 3rh syntax error observed on channel b (vss!syntaxerrorb) a syntax error was observed in the assigned slot on channel b. 0 b no syntax error observed on channel b 1 b syntax error observed on channel b ceoa 4rh content error observed on channel a (vss!contenterrora) a content error was observed in the assigned slot on channel a. 0 b no content error observed on channel a 1 b content error observed on channel a ceob 5rh content error observed on channel b (vss!contenterrorb) a content error was observed in the assigned slot on channel b. 0 b no content error observed on channel b 1 b content error observed on channel b svoa 6rh slot boundary violation observed on channel a (vss!bviolationa) a slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel a. 0 b no slot boundary violation observed on channel a 1 b slot boundary violation observed on channel a svob 7rh slot boundary violation observed on channel b (vss!bviolationb) a slot boundary violation (channel active at the start or at the end of the assigned slot) was observed on channel b. 0 b no slot boundary violation observed on channel b 1 b slot boundary violation observed on channel b tcia 8rh transmission conflict indication channel a (vss!txconflicta) a transmission conflict indication is set if a transmission conflict has occurred on channel a. 0 b no transmission conflict occurred on channel a 1 b transmission conflict occurred on channel a field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-188 v1.1, 2011-03 e-ray, v3.12 tcib 9rh transmission conflict indication channel b (vss!txconflictb) a transmission conflict indication is set if a transmission conflict has occurred on channel b. 0 b no transmission conflict occurred on channel b 1 b transmission conflict occurred on channel b esa 10 rh empty slot channel a in an empty slot there is no activity detected on the bus. the condition is checked in static and dynamic slots. 0 b bus activity detected in the assigned slot on channel a 1 b no bus activity detected in the assigned slot on channel a esb 11 rh empty slot channel b in an empty slot there is no activity detected on the bus. the condition is checked in static and dynamic slots. 0 b bus activity detected in the assigned slot on channel b 1 b no bus activity detected in the assigned slot on channel b mlst 12 rh message lost the flag is set in case the host did not read the message before the message buffer was updated from a received data frame. not affected by reception of null frames except for message buffers belonging to the receive fifo. the flag is reset by a host write to the message buffer via ibf or when a new message is stored into the message buffer after the message buffers nd flag was reset by reading out the message buffer via obf. 0 b no message lost 1 b unprocessed message was overwritten fta 14 rh frame transmitted on channel a indicates that this node has transmitted a data frame in the assigned slot on channel a. 0 b no transmission transmitted on channel a 1 b data frame transmitted on c hannel a in cycle defined by ccs bit field note: the flexray? protocol spec ification requires that fta can only be reset by the host. therefore the cycle count status ccs for these bits is only valid for the cycle where the bits are set to 1 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-189 v1.1, 2011-03 e-ray, v3.12 ftb 15 rh frame transmitted on channel b indicates that this node has transmitted a data frame in the assigned slot on channel b. 0 b no transmission transmitted on channel b 1 b data frame transmitted on c hannel b in cycle defined by ccs bit field note: the flexray? protocol spec ification requires that ftb can only be reset by the host. therefore the cycle count status ccs for these bits is only valid for the cycle where the bits are set to 1 ccs [21:16] rh cycle count status cycle count when status (mbs register) has been updated. rcis 24 rh received on channel indicator status (vss!channel) indicates the channel on which the frame was received. 0 b frame received on channel b 1 b frame received on channel a note: for receive buffers (cfg = 0) the rcis is updated from both valid data and null frames. if no valid frame was received, the previous value is maintained. for transmit buffers the flags have no meaning and should be ignored. sfis 25 rh startup frame indicator status (vrf!header!sufindicator) a startup frame is marked by the startup frame indicator. 0 b no startup frame received 1 b the received frame is a startup frame note: for receive buffers (cfg = 0) the sfis is updated from both valid data and null frames. if no valid frame was received, the previous value is maintained. for transmit buffers the flags have no meaning and should be ignored. syns 26 rh sync frame indicator status (vrf!header!syfindicator) a startup frame is marked by the startup frame indicator. 0 b no sync frame received 1 b the received frame is a sync frame note: for receive buffers (cfg = 0) the syns is updated from both valid data and null frames. if no valid frame was received, the previous value is maintained. for transmit buffers the flags have no meaning and should be ignored. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-190 v1.1, 2011-03 e-ray, v3.12 nfis 27 rh null frame indicator status (vrf!header!nfindicator) if reset to 0 the payload segment of the received frame contains no usable data. 0 b received frame is a null frame 1 b received frame is not a null frame note: for receive buffers (cfg = 0) the nfis is updated from both valid data and null frames. if no valid frame was received, the previous value is maintained. for transmit buffers the flags have no meaning and should be ignored. ppis 28 rh payload preamble indictor status (vrf!header!ppindicator) the payload preamble indicator defines whether a network management vector or message id is contained within the payload segment of the received frame. static segment: 0 b the payload segment of the received frame does not contain a network management vector or a message id 1 b network management vector at the beginning of the payload dynamic segment: 0 b the payload segment of the received frame does not contain a network management vector or a message id 1 b message id at the beginning of the payload note: for receive buffers (cfg = 0) the ppis is updated from both valid data and null frames. if no valid frame was received, the previous value is maintained. for transmit buffers the flags have no meaning and should be ignored. ress 29 rh reserved bit status (vrf!header!reserved) reflects the state of the received reserved bit. the reserved bit is transmitted as 0. note: for receive buffers (cfg = 0) the ress is updated from both valid data and null frames. if no valid frame was received, the previous value is maintained. for transmit buffers the flags have no meaning and should be ignored. 0 13, [23:22], [31:30] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-191 v1.1, 2011-03 e-ray, v3.12 output buffer command mask (obcm) configures how the output buffer is updated from the message buffer in the message ram selected by the output buffer command request register. if obf host and obf shadow are swapped, also mask bits obcm.rdsh and obcm.rhsh are swapped with bits obcm.rdss and obcm.rhss to keep them attached to the respective output buffer transfer. obcm output buffer command mask (0710 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 rd sh rh sh rrhrh 1514131211109876543210 0 rd ss rh ss rrwhrwh field bits type description rhss 0rwh read header section shadow 0 b header section is not read 1 b header section selected for transfer from message ram to output buffer rdss 1rwh read data section shadow 0 b data section is not read 1 b data section selected for transfer from message ram to output buffer rhsh 16 rh read header section host 0 b header section is not read 1 b header section selected for transfer from message ram to output buffer rdsh 17 rh read data section host 0 b data section is not read 1 b data section selected for transfer from message ram to output buffer 0 [15:2], [31:18] r reserved returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-192 v1.1, 2011-03 e-ray, v3.12 note: after the transfer of the header sect ion from the message ram to obf shadow has completed, the message buffer status changed flag mbcn (n = 0-31) to mbcn (n = 96-127) of the selected message buffer in the message buffer changed mbsc1 to mbsc4 registers is cleared. afte r the transfer of the data section from the message ram to obf shadow has completed, the new data flag ndn (n = 0-31) to ndn (n = 96-127) of the selected message buffer in the new data ndat1 to ndat4 registers is cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-193 v1.1, 2011-03 e-ray, v3.12 output buffer comma nd request (obcr) the message buffer selected by obcr.obrs is transferred from the message ram to the output buffer as soon as the host has set obcr.req. bit obcr.req can only be set while obcr.obsys is 0 (see also ?data transfer from message ram to output buffer? on page 26-235 ). after setting obcr.re q, obcr.obsys is automatically set, and the transfer of the message buffer selected by obcr.obrs from the message ram to output buffer shadow is started. when the transfer between the message ram and obf shadow has completed, this is signalle d by clearing obcr.obsys. by setting obcr.view while obcr.obsys is 0, obf host and obf shadow are swapped. when output buffer host and output buffer shadow are swapped, also mask bits obcm.rdsh and obcm.rhsh are swapped with bits obcm.rdss and obcm.rhss to keep them attached to the respective output buffer transfer. now the host can read the transferred message buffer from obf host. in parallel the message handler may transfer the next message from the message ram to obf shadow if obcr.view and obcr.req are set at the same time. any write access to an output buffer regi ster while obcr.obsys is set will cause the error flag eir.ioba to be set. in this case the output buffer will not be changed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-194 v1.1, 2011-03 e-ray, v3.12 obcr output buffer command request (0714 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 obrh rrh 1514131211109876543210 ob sys 0req vie w 0obrs rh r rw rw r rwh field bits type description obrs [6:0] rw output buffer request shadow number of source message buffer to be transferred from the message ram to obf shadow. valid values are 00 h to 7f h (0 to 127). if the number of the first message buffer of the receive fifo is written to this register the message handler transfers the message buffer addressed by the get index register (gidx, ?fifo function? on page 26-230 ) to obf shadow. view 8rw view shadow buffer toggles between obf shadow and obf host. only writeable while obcr.obsys = 0. 0 b no action 1 b swap obf shadow and obf host req 9rw request message ram transfer requests transfer of message buffer addressed by obcr.obrs from message ram to obf shadow. only writeable while obcr.obsys = 0. 0 b no request 1 b transfer to obf shadow requested obsys 15 rh output buffer busy shadow set to 1 after setting bit obcr.req. when the transfer between the message ram and obf shadow has completed, obcr.obsys is cleared again. 0 b no transfer in progress 1 b transfer between message ram and obf shadow in progress www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-195 v1.1, 2011-03 e-ray, v3.12 obrh [22:16] rh output buffer request host number of message buffer currently accessible by the host via rdhs1 to rdhs3, mbs, and rddsnn (nn = 01-64). by setting obcr.view obf shadow and obf host are swapped and the transferred message buffer is accessible by the host. valid values are 00 h to 7f h (01 to 27). 0 7, [14:10], [31:23] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-196 v1.1, 2011-03 e-ray, v3.12 26.6 functional description this chapter describes the e-ray implemen tation together with the related flexray? protocol features. more information about the flexray? protocol itself can be found in the flexray? protocol specification v2.1. communication on flexray? networks is based on frames and symbols. the wakeup symbol (wus) and the collision avoidance symbol (cas) are transmitted outside the communication cycle to setup the time schedule. frames and media access test symbols (mts) are transmitted inside the communication cycle. 26.6.1 communication cycle a communication cycle in flexray? co nsists of the following elements: ? static segment ? dynamic segment ? symbol window ? network idle time (nit) static segment, dynamic segment, and symbol window form the network communication time (nct). for each communication channel the slot counter starts at 1 and counts up until the end of the dynamic segment is reached. both channels share the same arbitration grid which means that they use the same synchronized macrotick. figure 26-4 structure of communication cycle 26.6.1.1 static segment the static segment is characterized by the following features: ? time slots of fixed length (optionally protected by bus guardian) ? start of frame transmission at action point of the respective static slot ? payload length same for all frames on both channel static segment dynamic segment symbol window network communication cycle x communication cycle x-1 communication cycle x+1 time base derived trigger t time base derived trigger idle time nit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-197 v1.1, 2011-03 e-ray, v3.12 parameters: number of static slots gtuc07 . nss , static slot length gtuc07 . ssl , payload length static mhdc . sfdl , action point offset gtuc09 . apo . 26.6.1.2 dynamic segment the dynamic segment is characteri zed by the following features: ? all controllers have bus access (no bus guardian protection possible) ? variable payload length and duration of slots, different for both channels ? start of transmission at minislot action point parameters: number of minislots gtuc08 . nms , minislot length gtuc08 . msl minislot action point offset gtuc09 . mapo , start of latest transmit (last minislot) mhdc . slt . 26.6.1.3 symbol window during the symbol window only one media access test symbol (mts) may be transmitted per channel. mts symbols are send in ?n ormal_active? state to test the bus guardian. the symbol window is characterized by the following features: ? send single symbol ? transmission of the mts symbol starts at the symbol windows action point parameters: symbol window action point offset gtuc09 . apo (same as for static slots), network idle time start gtuc04 . nit . 26.6.1.4 network idle time (nit) during network idle time the communication controller has to perform the following tasks: ? calculate clock correcti on terms (offset and rate) ? distribute offset correctio n over multiple macroticks ? perform cluster cycle related tasks parameters: network idle time start gtuc04 . nit , offset correction start gtuc04 . ocs . 26.6.1.5 configuration of network idle time (nit) start and offset correction start the number of macr oticks per cycle (gmacropercycle) is assumed to be m. it is configured by programming gtuc02 . mpc = m. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-198 v1.1, 2011-03 e-ray, v3.12 figure 26-5 configuration of network idle time (nit) start an d offset correction start the static / dynamic segment starts with macrotick 0 and ends with macrotick n: n = static segment length + dynamic segment offset + dynamic segment length - 1macrotick n = gnumberofstaticslots ? gdstaticslot + dynamic segment offset + gnumberofminislots ? gdminislot - 1 macroticks the static segment length is configured by gtuc07 . ssl and gtuc07 . nss . the dynamic segment length is configured by gtuc08 . msl and gtuc08 . nms . the dynamic segment offset is: if gdactionpointoffset gdminislotactionpointoffset: dynamic segment offset = 0 mt else if gdactionpointoffset > gdminislotactionpointoffset: dynamic segment offset = gdactionpointoffset - gdminislotactionpointoffset the network idle time (nit) starts with macrotick k+1 and ends with the last macrotick of cycle m-1. it has to be configured by setting gtuc04 . nit = k. for the e-ray the offset correction start is required to be gtuc04 . ocs gtuc04 . nit + 1 = k+1. the length of sym bol window results from the number of macroticks be tween the end of the static / dynamic segment and the beginning of the nit. it can be calculated by k - n. k+1 m-1 0 k nn+1 gtuc2.mpc = m gtuc4.ocs = nit + 1 gtuc4.nit = k nit symbol window static / dynamic segment www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-199 v1.1, 2011-03 e-ray, v3.12 26.6.2 communication modes the flexray? protocol specification v2.1 defines the time-triggered distributed (tt- d) mode. time-triggered distributed (tt-d) in tt-d mode the following configurations are possible: ? pure static : minimum 2 static slots + symbol window (optional) ? mixed static/dynamic : minimum 2 static slots + dynamic segment + symbol window (optional) a minimum of two coldstart nodes need to be configured for distributed time-triggered operation. two fault-free coldstart nodes are necessary for the cluster startup. each startup frame must be a sync frame, ther efore all coldstart nodes are sync nodes. 26.6.3 clock sy nchronization in tt-d mode a distributed clock synchronization is used. each node individually synchronizes itself to the cluster by observing the timing of received sync frames from other nodes. 26.6.3.1 global time activities in a flexray? node, including communication, are based on the concept of a global time, even though each individual node maintains its own view of it. it is the clock synchronization mechanism that differentiates the flexray? cluster from other node collections with independent clock mechanisms. the global time is a vector of two values; the cycle (cycle counter) and the cycle time (macrotick counter). cluster specific: ? macrotick = basic unit of time measurem ent in a flexray? network, a macrotick consists of an integer number of microticks ? cycle length = duration of a communi cation cycle in units of macroticks 26.6.3.2 local time internally, nodes time their behavior with microtick resolution. microticks are time units derived from the oscillator clock tick of th e specific node. ther efore microticks are controller-specific units. they may have diff erent duration in different controllers. the precision of a node?s local time difference measurements is a microtick. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-200 v1.1, 2011-03 e-ray, v3.12 node specific: ? oscillator clock prescaler microtick ? microtick = basic unit of time measurement in a communication controller, clock correction is done in units of microticks ? cycle counter + macrotick counter = nodes local view of the global time 26.6.3.3 synchronization process clock synchronization is performed by means of sync frames. only preconfigured nodes (sync nodes) are allowed to send sy nc frames. in a two-channel cluster a sync node has to send its sync frame on both channels. for synchronization in flexray? the following constraints have to be considered: ? max. one sync frame per node in one communication cycle ? max. 15 sync frames per cluster in one communication cycle ? every node has to use all available sync frames for clock synchronization ? minimum of two sync nodes required for clock synchronization and startup for clock synchronization the time difference between expected and observed arrival time of sync frames received during the static segment, valid on both channels (two- channel cluster), is measured. the calculation of correction terms is done during network idle time (nit) (offset: ever y cycle, rate: odd cycle) by using a fta / ftm algorithm. for details see flexray? protocol specification v2.1, chapter 8. offset (phase) correction ? only deviation values measured and stored in the current cycle used ? for a two channel node the smaller value will be taken ? calculation during network idle time (nit) of every communication cycle, value may be negative ? offset correction value calculated in even cycles used for error checking only ? checked against limit values (violation: ?normal_active? ?normal_passive? ?halt?) ? correction value is an integer number of microticks ? correction done in odd numbered cycles, distributed ov er the macroticks beginning at offset correction start up to cycle end (end of network idle time (nit)) to shift nodes next start of cycle (macroticks lengthened / shortened) rate (frequency) correction ? pairs of deviation values measured and stored in even / odd cycle pair used ? for a two channel node the average of the differences from the two channels is used ? calculated during network idle time (nit) of odd numbered cycles, value may be negative ? cluster drift damping is performed using global damping value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-201 v1.1, 2011-03 e-ray, v3.12 ? checked against limit values ? correction value is a signed integer number of microticks ? distributed over macroticks comprising the next even / odd cycle pair (macroticks lengthened / shortened) synchronization process clock synchronization is performed by means of sync frames. only preconfigured nodes (sync nodes) are allowed to send sy nc frames. in a two-channel cluster a sync node has to send its sync frame on both channels. for synchronization in flexray? the following constraints have to be considered: ? max. one sync frame per node in one communication cycle ? max. 15 sync frames per cluster in one communication cycle ? every node has to use all available sync frames for clock synchronization ? minimum of two sync nodes required for clock synchronization and startup for clock synchronization the time difference between expected and observed arrival time of sync frames received during the static segment, valid on both channels (two- channel cluster), is measured. the calculation of correction terms is done during network idle time (nit) (offset: ever y cycle, rate: odd cycle) by using a fta / ftm algorithm. for details see flexray? protocol specification v2.1, chapter 8. sync frame transmission sync frame transmission is only possible from buffer 0 and 1. message buffer 1 may be used for sync frame transmission in case that sync frames should have different payloads on the two channels. in this case bit mrc . splm has to be programmed to 1. message buffers used for sync frame transmission have to be configured with the key slot id and can be (re)configured in ?defau lt_config? or ?config? state only. for nodes transmitting sync frames succ1 . txsy must be set to 1. 26.6.3.4 external clock synchronization during normal operation, independent clusters can drift significantly. if synchronous operation across independent clusters is desi red, external synchronization is necessary; even though the nodes within each cluster are synchronized. this can be accomplished with synchronous application of host-deduced rate and offset correction terms to the clusters. ? external offset / rate correction value is a signed integer ? external offset / rate correction value is added to calculated offset / rate correction value ? aggregated offset / rate correction term (e xternal + internal) is not checked against configured limits www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-202 v1.1, 2011-03 e-ray, v3.12 26.6.4 error handling the implemented error handling concept is intended to ensure that in case of a lower layer protocol error in a single node communication between non-affected nodes can be maintained. in some cases, higher layer pr ogram command activity is required for the communication controller to resume normal operation. a change of the error handling state will set bit eir . pemc in the error service request register and may trigger an service request to the host if enabled. the actual error mode is signalled by ccev . errm in the communication controller error vector register. 26.6.4.1 clock correction failed counter when the clock correction failed counter reaches the maximum ?without clock correction passive? limit defined by succ3 . wcp , the poc transits from ?normal_active? to ?nor mal_passive? state. when it reaches the ?maximum without clock correction fatal? limit defined by succ3 . wcf , it transits ?normal_active? or ?norma l_passive? to the ?halt? state. both limits are defined in the suc configuration register 3. table 26-10 error modes of th e poc (degrada tion model) error mode activity active (green) full operation , state: ?normal_active? the communication controller is fully synchronized and supports the cluster wide clock synchronization. the host is informed of any error condition(s) or status change by interrupt (if enabled) or by reading the error and status interrupt flags from registers eir and sir . passive (yellow) reduced operation , state: ?normal_passive?, communication controller self rescue allowed the communication controller stops transmitting frames and symbols, but received frames are still pr ocessed. clock synchronization mechanisms are continued based on received frames. no active contribution to the cluster wide clock synchronization. the host is informed of any error condition(s) or status change by interrupt (if enabled) or by reading the error and status interrupt flags from registers eir and sir . comm_halt (red) operation halted , state: ?halt?, communication controller self rescue not allowed the communication controller stops frame and symbol processing, clock synchronization processing, and the macrotick generation. the host has still access to error and status information by reading the error and status interrupt flags from registers eir and sir . the bus drivers are disabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-203 v1.1, 2011-03 e-ray, v3.12 the clock correction failed counter ccev . ccfc allows the host to monitor the duration of the inability of a node to compute clock correction terms after the communication controller passed protocol startup phase. it will be incremented by one at the end of any odd numbered communication cycle where either the missing offset correction signal sfs . mocs nor the missing rate correction signal sfs . mrcs flag is set. the two flags are located in the sy nc frame status register, while the clock correction failed counter is located in the communication controller error vector register. the clock correction failed counter is reset to zero at the end of an odd communication cycle if neither the missing offset correction signal sfs . mocs nor the missing rate correction signal sfs . mrcs flag is set. the clock correction failed counter stops incrementing when the ?maximum without clock correction fatal? value succ3 . wcf as defined in the suc configuration register 3 is reached (i.e. incrementing the counter at its maximum value will not cause it to ?wraparound? back to zero). the clock correction failed counter is initialized to zero when the communication controller enters ?ready? state or when ?normal_active? state is entered. 26.6.4.2 passive to active counter the passive to active counter controls the transition of the poc from ?normal_passive? to ?normal_active? state. succ1 . pta in the suc configuration register 1 defin es the number of consecutiv e even / odd cycle pairs that must have valid clock correction terms before the communication controller is allowed to transit from ?normal_passive? to ?normal_active? state. if succ1 . pta is reset to zero the communication controller is not allowed to transit from ?normal_passive? to ?n ormal_active? state. 26.6.4.3 halt command in case the host wants to stop flexray? communication of the local node it can bring the communication controller into ?halt? state by asserting the halt command. this can be done by writing succ1 . cmd = 0110 b in the suc configuration register 1. when called in ?normal_active? or ?normal_passive? state th e poc transits to ?halt? state at the end of the current cycle. when called in any other state succ1 . cmd will be reset to 0000 b = ?command_not_a ccepted? and bit eir . cna in the error service request register is set to 1. if enabled an service request to the host is generated. 26.6.4.4 freeze command in case the host detects a severe error condition it can bring the communication controller into ?halt? state by asserting the freeze command. this can be done by writing succ1 . cmd = 0111 b in the suc configuration register 1. the freeze www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-204 v1.1, 2011-03 e-ray, v3.12 command triggers the entry of the ?halt? state immediately regardless of the actual poc state. the poc state from which the transition to halt state took place can be read from ccsv . psl . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-205 v1.1, 2011-03 e-ray, v3.12 26.6.5 communication controller states this chapter introduces the states of the communication controller. 26.6.5.1 communication controller state diagram state transitions are controlled by externals the application reset or rxda/b, by the poc state machine, and by the chi command vector succ1 . cmd located in the suc configuration register 1. figure 26-6 overall state diagram of e-ray communic ation controller the communication controller exits from all states to ?halt? state after application of the freeze command (succ1.cmd = 0111 b ). t1 t3 t4 t5 t8 t9 t6 t7 hw reset power on ready wakeup halt monitor_ config normal_ normal_ startup active passive mode t10 t11 t12 t13 t14 t15 t17 t16 transition triggered by host command transition triggered by internal conditions transition triggered by host command or internal conditions default_ config t2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-206 v1.1, 2011-03 e-ray, v3.12 table 26-11 state transitions of e-ray overall state machine t# condition from to 1 application reset hw reset default_config 2 command config, succ1.cmd = 0001 b default_config config 3 unlock sequence followed by command monitor_mode, succ1.cmd = 1011 b config monitor_mode 4 command config, succ1.cmd = 0001 b monitor_mode config 5 unlock sequence followed by command ready, succ1.cmd = 0010 b config ready 6 command config, succ1.cmd = 0001 b ready config 7 command wakeup, succ1.cmd = 0011 b ready wakeup 8 complete, non-aborted transmission of wakeup pattern or received wup or received frame header or command ready, succ1.cmd = 0010 b wakeup ready 9 command run, succ1.cmd = 0100 b ready startup 10 successful startup startup normal_active 11 clock correction failed counter reached maximum without clock correction passive limit configured by wcp in suc configuration register 3 normal_active normal_passive 12 number of valid correction terms reached the passive to active limit configured by pta in suc configuration register 1 normal_passive normal_active 13 command ready, succ1.cmd = 0010 b startup, normal_active, normal_passive ready www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-207 v1.1, 2011-03 e-ray, v3.12 26.6.5.2 default_config state in ?default_config? state, the communication controller is stopped. all configuration registers are accessible and the pins to the physical layer are in their inactive state. the communication controller enters this state ? when leaving application reset ? when exiting from ?halt? state to leave ?default_config? state the host has to write succ1.cmd = 0001 b in the suc configuration register 1. the communication controller transits to ?config? state. config state in ?config? state, the communication controller is stopped. all configuration registers are accessible and the pins to the physical layer are in their inactive state. this state is used to initialize the communication controller configuration. 14 clock correction failed counter reached maximum without clock correction fatal limit configured by wcf in suc configuration register 3 and bit hcse in the suc configuration register 1 set to 1 or command halt, succ1.cmd = 0110 b normal_active halt 15 clock correction failed counter reached maximum without clock correction fatal limit configured by wcf in suc configuration register 3 and bit hcse in the suc configuration register 1 set to 1 or command halt, succ1.cmd = 0110 b normal_passive halt 16 command freeze, succ1.cmd = 0111 b all states halt 17 command config, succ1.cmd = 0001 b halt default_config table 26-11 state transitions of e-ray overall state machine (cont?d) t# condition from to www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-208 v1.1, 2011-03 e-ray, v3.12 the communication controller enters this state ? when exiting from ?default_config? state ? when exiting from ?monitor_mode? or ?ready? state when the state has been entered via ?halt? and ?default_config? state, the host can analyze status information and configuration. before leaving ?config? state the host has to assure that the configuration is fault-free. to leave ?config? state, the host has to perform the unlock sequence as described on ?lck? on page 26-39 . directly after unlocking the ?config? state the host has to write succ1 . cmd in the suc configuration register 1 to enter the next state. internal counters and the communication controller status flags are reset when the communication controller leaves ?config?. note: the message buffer status registers ( mhds , txrq1 to txrq4 , ndat1 to ndat4 , mbsc1 to mbsc4 ) and status data stored in the message ram and are not affected by the trans ition of the poc from ?config? to ?ready? state. when the communication controller is in ?config? state it is also possible to bring the communication controller into a power savi ng mode by halting the module clocks ( f sclk , f clc_eray ). to do this the host has to assure that all message ram transfers have finished before turn ing off the clocks. 26.6.5.3 monitor_mode after unlocking ?config? state and writing succ1 . cmd = 0011 b the communication controller enters ?monitor_mode?. in this mode the communication controller is able to receive flexray? frames and to det ect wakeup pattern. the temporal integrity of received frames is not c hecked, and ther efore cycle counter filter ing is not supported. it is not possible to distinguish between static and dynamic frames, because limited functions in monitor mode (frf.rss will be ignored, filtering not functional).this mode can be used for debugging purposes in case e.g. that startup of a flexray? network fails. after writing succ1 . cmd = 0001 b the communication controller transits back to ?config? state. in monitor_mode the pick first valid me chanism is disabled. this means that a receive message buffer may only be configured to receive on one channel. received frames are stored into message buffers according to frame id and receive channel. null frames are handled like data frames. after frame reception only status bits mbs . vfra , mbs , mbs . mlst , mbs . rcis , mbs . sfis , mbs . syns , mbs . nfis , mbs . ppis , mbs . ress have valid value. in ?monitor_mode? the communication controller is not able to distinguish between cas and mts symbols. in case one of these symbols is received on one or both of the two channels, the flags sir . mtsa resp. sir . mtsb are set. sir . cas has no function in ?monitor_mode?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-209 v1.1, 2011-03 e-ray, v3.12 26.6.5.4 ready state after unlocking ?config? state and writing succ1 . cmd = 0010 b the communication controller enters ?ready? state. from this state the communication controller can transit to wakeup st ate and perform a cluster wake up or to ?startup? state to perform a coldstart or to integrate into a running communication. the communication controller enters this state ? when exiting from ?config?, ?wakeu p?, ?startup?, ?normal_active?, or ?normal_passive? state by writing succ1 . cmd = 0010 b (ready command). the communication controller exits from this state ? to ?config? state by writing succ1 . cmd = 0001 b (config command) ? to ?wakeup? state by writing succ1 . cmd = 0011 b (wakeup command) ? to ?startup? state by writing succ1 . cmd = 0100 b (run command) internal counters and the communication controller status flags are reset when the communication controller enters ?startup? state. note: status bits mhds , registers txrq1 to txrq4 , and status data stored in the message ram are not affected by the transition of the poc from ?ready? to ?startup? state. 26.6.5.5 wakeup state the description below is intended to help configuring wakeup for the e-ray ip-module. a detailed description of the wakeup procedure together with the respective sdl diagrams can be found in the flexray? protocol specification v2.1, section 7.1. the communication controller enters this state ? when exiting from ?ready? state by writing succ1 . cmd = 0011 b (wakeup command). the communication controller exits from this state to ?ready? state ? after complete non-aborted transmission of wakeup pattern ?after wup reception ? after detecting a wup collision ? after reception of a frame header ? by writing succ1 . cmd = 0010 b (ready command) the cluster wakeup must precede the communication startup in order to ensure that all mechanisms defined for the startup work properly. the minimum requirement for a cluster wakeup is that all bus drivers are su pplied with power. a bu s driver has the ability to wake up the other components of its node when it receives a wakeup pattern on its channel. at least one node in the cluster needs an external wakeup source. the host completely controls the wakeup procedure. it is informed about the state of the cluster by the bus driver and the communication controller and configures bus guardian www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-210 v1.1, 2011-03 e-ray, v3.12 (if available) and communication controller to perform the cluster wakeup. the communication controller provides to the host the ability to transmit a special wakeup pattern on each of its available channel s separately. the communication controller needs to recognize t he wakeup pattern only du ring ?wakeup? state. wakeup may be performed on only one channel at a time. the host has to configure the wakeup channel while the communication controller is in ?config? state by writing bit succ1 . wucs in the suc configuration register 1. the communication controller ensures that ongoing communication on this channel is not disturbed. the communication controller cannot guarantee that all nodes connected to the configured channel awake upon the transmission of the wakeup pattern, since these nodes cannot give feedback until the startup phase. t he wakeup procedure enables single-channel devices in a two-channel system to trigger the wakeup, by only transmitting the wakeup pattern on the single channel to which th ey are connected. any coldstart node that deems a system startup necessary will then wake the remaining channel before initiating communication startup. the wakeup procedure tolerates any number of nodes simultaneously trying to wakeup a single channel and resolves this situation such that only one node transmits the pattern. additionally the wakeup pattern is collision resilient, so even in the presence of a fault causing two nodes to simultaneously transmit a wakeup pattern, the resulting collided signal can still wake the other nodes. after wakeup the communication controller returns to ?ready? state and signals the change of the wakeup status to the host by setting bit sir . wst in the status service request register. the wakeup status vector can be read from the communication controller status vector register ccsv . wsv . if a valid wakeup pattern was received also either flag sir . wupa or flag sir . wupb in the status service request register is set. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-211 v1.1, 2011-03 e-ray, v3.12 figure 26-7 structure of poc state wakeup table 26-12 state transitions wakeup t# condition from to enter host commands change to ?wakeup? state by writing succ1 . cmd = 0011 b (wakeup command) ready wakeup 1 chi command wakeup triggers wakeup fsm to transit to ?wakeu p_listen? state wakeup_ standby wakeup_ listen 2 received wup on wakeup channel selected by flag succ1 . wucs in the suc configuration register 1 or frame header on either available channel wakeup_ listen wakeup_ standby 3 timer event wakeup_ listen wakeup_ send 4 complete, non-aborted transmission of wakeup pattern wakeup_ send wakeup_ standby t enter t2 t6 t3 t5 wakeup wakeup_ send wakeup_ listen wakeup_ detect t4 t exit ready wakeup_ standby t1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-212 v1.1, 2011-03 e-ray, v3.12 the ?wakeup_listen? state is controlled by the wakeup timer and the wakeup noise timer. the two timers are controlled by the parameters listen time-out succ2 . lt and listen time-out noise succ2 . ltn . both values can be configured in the suc configuration register 2. listen time-out enables a fast cluster wakeup in case of a noise free environment, while listen time-out noise enables wakeup under more difficult conditions regarding noise interference. in ?wakeup_send? state the communication controller tr ansmits the wa keup pattern on the configured cha nnel and checks for collisions. afte r return from wakeup the host has to bring the communication controller into ?startup? state by chi command run. in ?wakeup_detect? state the communication controller attempts to identify the reason for the wakeup collision detected in ?wakeup_send? state. the monitoring is bounded by the expiration of listen time-out as configured by succ2 . lt in the suc configuration register 2. either the detection of a wakeup pattern indicating a wakeup attempt by another node or the receptio n of a frame header indication existing communication, causes the direct transition to ?ready? state. otherwise wakeup_detect is left after expiration of lis ten time-out; in this case the reason for wakeup collision is unknown. the host has to be aware of possible failures of the wakeup and act accordingly. it is advisable to delay any potential startup attempt of the node having instigated the wakeup by the minimal time it takes another coldstart node to become awake and to be configured. the flexray? protocol specification v2.1 recommends that two different communication controllers shall awake the two channels. 5 collision detected wakeup_ send wakeup_ detect 6 wakeup timer expired or wup detected on wakeup channel selected by flag succ1 . wucs in the suc configuration register 1 or frame header received on either available channel wakeup_ detect wakeup_ standby exit wakeup completed (after t2 or t4 or t6) or host commands change to ?ready? state by writing succ1 . cmd = 0010 b (ready command). this command also resets the wakeup fsm to ?wakeup_standby? state wakeup ready table 26-12 state transitions wakeup (cont?d) t# condition from to www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-213 v1.1, 2011-03 e-ray, v3.12 host activities the host must coordinate the wakeup of the two channels and must decide whether, or not, to wake a specific channel. the sending of the wakeup pattern is initiated by the host and generated by the communication controller. the wakeup pattern is detected by the remote bds and signalled to their local hosts. wakeup procedure controlled by host (single-channel wakeup): ? configure the communication controller in ?config? state ? select wakeup channel by programming bit succ1 . wucs ? check local bds whether a wup was received ? activate bd of selected wakeup channel ? command communication controller to start wakeup on the configured channel by writing succ1 . cmd = 0011 b ? communication controller enters ?wakeup ? communication controller returns to ?ready? state and signals status of wakeup attempt to host ? wait predefined time to allow the other nodes to wakeup and configure themselves ? coldstart node: wait for wup on the other channel ? in a dual channel cluster wait for wup on the other channel ? reset coldstart inhibit flag ccsv . csi by writing succ1 . cmd = 1001 b (allow_coldstart command)) ? reset coldstart inhibit flag ccsv . csi in the ccsv register by writing succ1 . cmd = 1001 b (allow_coldstart command), coldstart node only ? command communication controller to enter startup by writing succ1 . cmd = 0100 b (run command) wakeup procedure triggered by bd: ? wakeup recognized by bd ? bd triggers power-up of host (if required) ? bd signals wakeup event to host ? host configures its local communication controller ? if necessary host commands wakeup of second channel and waits predefined time to allow the other nodes to wakeup and configure themselves ? host commands communication controller to enter ?startup? state by writing succ1 . cmd = 0100 b (run command) wakeup pattern (wup) the wakeup pattern is composed of at least two wakeup symbols (wus). wakeup symbol and wakeup pattern are configured by the prt configuration registers prtc1 and prtc2 . ? single channel wakeup, wakeup symbol may not be sent on both channels at the same time www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-214 v1.1, 2011-03 e-ray, v3.12 ? wakeup symbol collision resilient for up to two sending nodes (two overlapping wakeup symbols still recognizable) ? wakeup symbol must be configured identical in all nodes of a cluster ? wakeup symbol transmit low time configured by prtc2 . txl ? wakeup symbol idle time used to listen for activity on the bus, configured by prtc2 . txi ? a wakeup pattern composed of at least two tx-wakeup symbols needed for wakeup ? number of repetitions configurable by prtc1 . rwp (2 to 63 repetitions) ? wakeup symbol receive window length configured by prtc1 . rxw ? wakeup symbol receive low time configured by prtc2 . rxl ? wakeup symbol receive idle time configured by prtc2 . rxi figure 26-8 timing of wakeup pattern 26.6.5.6 startup state the description below is intended to help configuring startup for the e-ray ip-module. a detailed description of the startup procedur e together with the respective sdl diagrams can be found in the flexray? protocol specification v2.1, section 7.2. any node entering ?startup? state that has coldstart capability should assure that both channels attached have been awakened before initiating coldstart. it cannot be assumed that all nodes and stars need the same amount of time to become completely awake and to be configured. since at least two nodes are necessary to start up the cluster communication, it is advisable to delay any potential startup attempt of the node having instigated the wakeup by the minimal amount of time it takes another coldstart node to become awake, to be configured and to enter startup. it may require several hundred milliseconds (depending on the hardware used) before all nodes and stars are completely awakened and configured. startup is performed on all channels synchronously. during startup, a node only transmits startup frames. a fault-tolerant, distributed startup strategy is specified for initial synchronization of all nodes. in general, a node may enter ?normal_active? state via (see figure 26-9 ): tx-wakeup symbol rx-wakeup pattern (no collision) rx-wakeup pattern (collision, worst case) txl = 15-60 bit times txi = 45-180 bit times www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-215 v1.1, 2011-03 e-ray, v3.12 ? coldstart path initiating the schedule synchronization (leading coldstart node) ? coldstart path joining other coldstart nodes (following coldstart node) ? integration path integrating into an existing communication schedule (all other nodes) a coldstart attempt begins with the transmission of a collision avoidance symbol (cas). only a coldstart node that had transmitted the cas transmits frames in the first four cycles after the cas, it is then joined firstl y by the other coldstar t nodes and afterwards by all other nodes. a coldstart node has the transmit sync frame in key slot bits succ1 . txst and succ1 . txsy in the suc configuration register 1 set to 1. the message buffer 0 holds the key slot id which defines the slot number where the startup frame is send. in the frame header of the startup frame the startup frame indicator bit is set. in clusters consisting of three or more nodes , at least three nodes shall be configured to be coldstart nodes. in clusters consisting of two nodes, both nodes must be coldstart nodes. at least two fault-free coldstart nodes are necessary for the cluster to startup. each startup frame must also be a sync fr ame; therefore each coldstart node will also be a sync node. the number of coldstart attempts is configured by succ1 . csa in the suc configuration register 1. a non-coldstart node requires at least two startup frames from distinct nodes for integration. it may start integration before the coldstart nodes have finished their startup. it will not finish its startup until at least two coldstart nodes have finished their startup. both non-coldstart nodes and coldstart nodes start passive integration via the integration path as soon as they receive sync frames from which to derive the tdma schedule information. during integration the node has to adapt its own clock to the global clock (rate and offset) and has to make its cycle time consistent with the global schedule observable at the network. afterwards, these settings are checked for consistency with all available network nodes. the node can onl y leave the integration phase and actively participate in communication when these checks are passed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-216 v1.1, 2011-03 e-ray, v3.12 figure 26-9 state diagram time-triggered startup coldstart inhibit mode in coldstart inhibit mode the node is prevented from initializing the tdma communication schedule. if bit ccsv . csi in the communication controller status vector register is set, the node is not allowed to initialize the cluster communication, i.e. entering the coldstart path is prohibited. the node is allowed to in tegrate to a running cluster or to transmit startup frames after another coldstart node started the initialization of the cluster communication. the coldstart inhibit bit ccsv . csi is set whenever the poc enters ?ready? state. the bit has to be cleared under control of the host by chi command allow_coldstart ( succ1 . cmd = 1001 b ) eray_startup ready startup_ prepare abort_ startup integration_ listen coldst art _ listen c oldstart_ collision_ resolution initialize_ schedule coldstart_ co nsi st ency_ check integration_ coldstart_ check coldstart_ gap coldstart_ join normal_ active coldstart_ co nsi st ency_ check startup leading coldstart node following coldstart node non-coldstart node integrating power-on hw reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-217 v1.1, 2011-03 e-ray, v3.12 26.6.5.7 startup time-outs the communication controller supplies two different microtick timers supporting two time-out values, startup time-out and start up noise time-out. the two timers are reset when the communication controller enters the ?coldstart_listen? state. the expiration of either of these timers causes the node to leave the initial sensing phase (?coldstart_listen? state) with the in tention of starting up communication. note: the startup and startup noise timers are identical with the wakeup and wakeup noise timers and use the same configuration values succ2 . lt and succ2 . ltn from the suc configuration register 2. startup time-out the startup time-out limits the listen time used by a node to determine if there is already communication between other nodes or at least one coldstart node actively requesting the integration of others. the startup timer is configured by programming succ2 . lt (pdlistentimeout) in the suc configuration register 2. the startup timer is restarted upon: ? entering the ?coldstart_listen? state ? both channels reaching idle state while in ?coldstart_listen? state the startup timer is stopped: ? if communication channel activity is detect ed on one of the configured channels while the node is in the ?coldstart_listen? state ? when the ?coldstart_listen? state is left once the startup time-out expires, neither an overflow nor a cyclic restart of the timer is performed. the timer status is kept for fu rther processing by the startup state machine. startup noise time-out at the same time the startup timer is started for the first time (transition from ?startup_prepare? state to ?coldstart_listen ? state), the star tup noise timer is started. this additional time-out is used to improve reliability of the startup procedure in the presence of noise. the startup noise timer is configured by programming succ2 . ltn (glistennoise - 1) in the suc configuration register 2 (see ?suc configuration register 2 (succ2)? on page 26-96 ). the startup noise time-out is: pdlistentimeout ? glistennoise = succ2 . lt ? ( succ2 . ltn + 1) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-218 v1.1, 2011-03 e-ray, v3.12 the startup noise timer is restarted upon: ? entering the ?coldstart_listen? state ? reception of correctly decoded headers or cas symbols while the node is in ?coldstart_listen? state the startup noise timer is stopped when the ?coldstart_listen? state is left. once the startup noise time-out expires, neither an overflow nor a cyclic restart of the timer is performed. the status is kept for further processing by the startup state machine. since the startup noise timer won?t be restarted when random channel activity is sensed, this time-out defines the fall-back solution that guarantees that a node will try to start up the communication cluster even in the presence of noise. 26.6.5.8 path of leading coldst art node (initiating coldstart) when a coldstart node enters ?coldstart_listen?, it listens to its attached channels. if no communication is detected, the node enters the ?coldstart_collision_ resolution? state and commences a coldstart attempt. the initial transmission of a cas symbol is succeeded by the first regu lar cycle. this cycle ha s the number zero. from cycle zero on, the node transmits its startup frame. since each coldstart node is allowed to perform a coldstart attempt, it may occur that several nodes simultaneously transmit the cas symbol and enter the coldstart path. this situation is resolved during the first four cycles after cas transmission. as soon as a node that initiates a coldstart attempt receives a cas symbol or a frame header during these four cycles, it re-ent ers the ?coldstart_list en? state. thereby, only one node remains in this path. in cycle four, other coldstart nodes begin to transmit their startup frames. after four cycles in ?coldstart_col lision_resolution? state, the node that initiated the coldstart enters the ?coldstart_consistency_check? state. it collects all startup frames from cycle four and five and performs the clock correction. if the clock correction does not deliver any errors and it has received at least one valid startup frame pair, the node leaves ?coldstart_consistency_check? and enters ?normal_active? state. the number of coldstart attempts that a node is allowed to perform is configured by succ1 . csa in the suc configuration register 1. the number of remaining coldstarts attempts ccsv . rca can be read from communication controller status vector register. the number of remaining attempts is reduced by one for each attempted coldstart. a node may enter the ?coldstart_listen? state only if this value is larger than one and it may enter the ?coldstart_collision_resolution? state only if this value is larger than zero. if the number of coldstart attempts is one, coldstart is inhibited but integrat ion is still possible. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-219 v1.1, 2011-03 e-ray, v3.12 path of following coldstart node (responding to leading coldstart node) when a coldstart node enters the ?coldstart_listen? state, it tries to receive a valid pair of startup frames to derive its schedule and clock correction from the leading coldstart node. as soon as a valid startup frame has been received the ?initialize_schedule? state is entered. if the cl ock synchronization can successfully receive a matching second valid startup frame and can derive a sche dule from this startup frames, the ?integration_coldstart_check? state is entered. in ?integration_coldstart_check? state it is assured that the clock correction can be performed correctly and that the coldstart node from which this node has initialized its schedule is still available. the node collects all sync frames and performs clock correction in the following double-cycl e. if clock correction does not signal any errors and if the node continues to receive sufficient frames from the same node it has integrated on, the ?coldstart_join? state is entered. in ?coldstart_join? state integrating coldstart nodes begin to transmit their own startup frames. thereby the node that initiated the coldstart and the nodes joining it can check if their schedules agree to each other. if for the following three cycles the clock correction does not signal errors and at least one other coldstart node is visible, the node leaves ?coldstart_join? state and enters ?normal_active? state. thereby it leaves ?startup? at least one cycle after the node that initiated the coldstart. path of non-coldstart node when a non-coldstart node enters the integrat ion_listen state, it listens to its attached channels and tries to receive flexray? frames. as soon as a valid startup frame has been received the ?initialize_schedule? state is entered. if the cl ock synchronization can successfully receive a matching second valid startup frame and derive a schedule from this, the integration_consistency_ check state is entered. in ?integration_consistency_check? state it is verified that the clock correction can be performed correctly and that enough coldstart nodes (at least 2) send startup frames that agree to the nodes own schedule. clock correction is activated, and if any errors are signalled, the integration attempt is aborted. during the first even cycle in this state, eit her two valid startup frames or the startup frame of the node that this node has integrated on must be received; otherwise the node aborts the integration attempt. during the first double-cycle in this state, either two valid startup frame pairs or the startup frame pair of the node that this node has integrated on must be received; otherwise the node aborts the integration attempt. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-220 v1.1, 2011-03 e-ray, v3.12 if after the first double-cycle less than two valid startup frames are received within an even cycle, or less than two valid startup frame pairs are received within a double-cycle, the startup attempt is aborted. nodes in this state need to see two valid startup frame pairs for two consecutive double- cycles each to be allowed to leave startup and enter normal_operation. consequently, they leave startup at least one double-cycle after the node that initiated the coldstart and only at the end of a cycle with an odd cycle number. 26.6.5.9 normal_active state as soon as the node that transmitted the first cas symbol (resolving the potential access conflict and entering ?startup? via coldstart path) and one additional node have entered the ?normal_active? state, the startup phase for the cluster has finished. in the ?normal_active? state, all configured messages are scheduled for transmission. this includes all data frames as well as the sync frames. rate and offset measurement is started in all even cycles (even/odd cycl e pairs required). in ?normal_active? state the communication controller supports regular communication functions ? the communication controller performs transmissions and reception on the flexray? bus as configured ? clock synchronization is running ? the host interface is operational the communication controller exits from that state to ? ?halt? state by writing succ1 . cmd = 0110 b (halt command, at the end of the current cycle) ? ?halt? state by writing succ1 . cmd = 0111 b (freeze command, immediately) ? ?halt? state due to change of the error state from ?active? to ?comm_halt? ? ?normal_passive? state due to change of the error state from ?active? to ?passive? ? ?ready? state by writing succ1 . cmd = 0010 b (ready command) 26.6.5.10 normal_passive state ?normal_passive? state is entered from ?normal_active? state when the error state changes from active (green) to passive (yellow). in ?normal_passive? state, t he node is able to receive all frames (node is fully synchronized and performs clock synchro nization). in comparison to the ?normal_active? state the node does not actively participate in communication, i.e. neither symbols nor frames are transmitted. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-221 v1.1, 2011-03 e-ray, v3.12 in ?normal_p assive? state ? the communication controller performs reception on the flexray? bus ? the communication controller does not transmit any frames or symbols on the flexray? bus ? clock synchronization is running ? the host interface is operational the communication controller exits from this state to ? ?halt? state by writing succ1 . cmd = 0110 b (halt command, at the end of the current cycle) ? ?halt? state by writing succ1 . cmd = 0111 b (freeze command, immediately) ? ?halt? state due to chang e of the error state from ?passive? to ?comm_halt? ? ?normal_active? state due to change of the error state from ?passive? to ?active?. the transition takes place when ccev . ptac from the communication controller error vector register equals succ1 . pta - 1. ? ?ready? state by writing succ1 . cmd = 0010 b (ready command) 26.6.5.11 halt state in this state all communication (reception and transmission) is stopped. the communication controller enters this state ? by writing succ1 . cmd = 0110 b (halt command) while the communication controller is in ?normal_ac tive? or ?normal_passive? state ? by writing succ1 . cmd = 0111 b (freeze command) from all states ? when exiting from ?normal_active? state because the clock correction failed counter reached the ?maximum without clock correction fatal? limit ? when exiting from ?normal_passive? state because the clock correction failed counter reached the ?maximum without clock correction fatal? limit the communication controller exits from this state to ?config? state ? by writing succ1 . cmd = 0001 b (default_config command) when the communication controller enters ?halt? state, all configuration and status data is maintained for analyzing purposes. when the host writes succ1 . cmd = 0110 b (halt command) in the suc configuration register 1 to 1, the communication controller sets bit ccsv . hrq in the communication controller status vector register a nd enters ?halt? state after the current communication cycle has finished. when the host writes succ1 . cmd = 0111 b (freeze command) in the suc configuration register to 1, the communication controller enters ?halt? state immediately and sets the ccsv . fsi bit in the communication controller status vector register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-222 v1.1, 2011-03 e-ray, v3.12 the poc state from which the transition to halt state took place can be read from ccsv . psl . 26.6.6 network management the accrued network management (nm) vector is located in the network management register 1 to network management register 3 ( nmvx (x = 1-3) ). the communication controller performs a logical or operation over all network management (nm) vectors out of all received valid network management (nm) frames with the payload preamble indicator (ppi) bit set. only a static frame may be configured to hold network management (nm) information. the communication controller updates the network management (nm) vector at the end of each cycle. the length of the network management (nm) ve ctor can be configured from 0 to 12 byte by nml in the nem configuration regist er. the network management (nm) vector length must be configured identically in all nodes of a cluster. to configure a transmit buffer to send flexray? frames with the ppi bit set, the ppit bit in the header section of the respective transmit buffer has to be set via wrhs1 . ppit . in addition the host has to write the network management (nm) information to the data section of the respective transmit buffer. the evaluation of the network management (nm) vector has to be done by the application running on the host. note: in case a message buffer is configured for transmission / reception of network management frames, the payload length c onfigured in header 2 of that message buffer should be equal or greater than t he length of the nm vector configured by nemc . nml . when the communication controller transits to ?halt? state, the cycle count is not incremented and therefore the nm vect or is not updated. in this case nmv1 to nmv3 holds the valu e from the cycle before. 26.6.7 filtering and masking filtering is done by checking specific fields in a received frame against the corresponding configuration constants of the valid message buffers and the actual slot and cycle counter values (acceptance filter ing), or by compari ng the conf iguration constants of the valid message buffers agai nst the actual slot and cycle counter values (transmit filtering). a message buffer is only updated / transmitted if the required matches occur. filtering is done on the following fields: ? channel id ? frame id ? cycle counter the following filter combinations for acceptance / transmit filtering are allowed: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-223 v1.1, 2011-03 e-ray, v3.12 ? frame id + channel id ? frame id + channel id + cycle counter in order to store a received message in a message buffer all configured filters must match. note: for the fifo the acceptance filter is configured by the fifo rejection filter and the fifo rejection filter mask. a message will be transmitted in the time slot corresponding to the configured frame id on the configured channel(s). if cycle count er filtering is enabled the configured cycle filter value must also match. 26.6.7.1 frame id filtering every transmit and receive buffer contains a frame id stored in the header section. this frame id is used differently for receive and transmit buffers. receive buffers a received message is stored in the first receive buffer where the received frame id matches the configured frame id, provided channel id and cycle counter criteria are also met. transmit buffers for transmit buffers the configured frame id is used to determine the appropriate slot for message transmission. the frame will be transmitted in the time slot corresponding to the configured frame id, provided channel id and cycle counter cr iteria are also met. 26.6.7.2 channel id filtering there is a 2-bit channel filtering field (cha, chb) located in the header section of each message buffer in the message ram. it serves as a filter for receive buffers, and as a control field for transmit buffers (see table 26-13 ). table 26-13 channel filtering configuration cha chb transmit buffer transmit frame receive buffer store valid receive frame 1 1 on both channels (static segment only) received on channel a or b (store first semantically valid frame, static segment only) 1 0 on channel a received on channel a 0 1 on channel b received on channel b 0 0 no transmission ignore frame www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-224 v1.1, 2011-03 e-ray, v3.12 note: if a message buffer is configured for the dynamic segment a nd both bits of the channel filtering field are set to 1, no frames are transmitted resp. received frames are ignored (same function as cha = chb = 0) receive buffers valid received frames are stored if they are received on the channels specified in the channel filtering field. only in static segment a receive buffer may be setup for reception on both channels (cha and chb set). other filtering criteria must also be met. if a valid header segment was stored, the respective mbc flag in the message buffer status changed register is set. if a valid payload segment was stored, the respective ndn (n = 0-31) to ndn (n = 96-127) flag in the new data ndat1 to ndat4 register is set. in both cases, if bit rdhs1 . mbi in the header section of the respective message buffer is set, the rxi flag in the status service request register is set to 1. if enabled an service request is generated. transmit buffers the content of the buffer is transmitted only on the channels specified in the channel filtering field when the frame id filtering and cycle counter fi ltering criteria are also met. only in static segment a transmit buffer may be setup for transmission on both channels (cha and chb set). after transmission has completed, and if bit wrhs1 . mbi in the header section of the respective message buffer is set, the txi flag in the status service request register is set to 1. if enabled an service request is generated. 26.6.7.3 cycle counter filtering cycle counter filtering is bas ed on the notion of a cycle set. for filtering purposes, a match is detected if any one of the elemen ts of the cycle set is matched. the cycle set is defined by the cycle code field in t he header section of each message buffer. if message buffer 0 is configured to hold the startup / sync frame or the single slot frame by bits txst, txsy, an d tsm in the suc configurat ion register 1, cycle counter filtering for message buffer 0 should be disabled. note: sharing of a static time slot via cycle co unter filtering between different nodes of a flexray? network is not allowed. the set of cycle numbers belonging to a cycle set is determined as described in table 26-14 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-225 v1.1, 2011-03 e-ray, v3.12 table 26-15 below gives some examples for valid cycle sets to be used for cycle counter filtering: receive buffers the received message is stored only if the received cycle counter matches an element of the receive buffer?s cycle set. channel id and frame id criteria must also be met. transmit buffers the content of the buffer is transmitted on the configured channels when an element of the cycle set matches the current cycle counte r value and the frame id matches the slot counter value. 26.6.7.4 fifo filtering for fifo filtering there is one rejection filter and one rejection filter mask available. the fifo rejection filter consists of 20 bits for channel (2 bits), frame id (11 bits), and cycle code (7 bits). rejection filter and rejection filter mask can be configured in table 26-14 definition of cycle set cycle code matching cycle counter values 000000x b all cycles 000001c b every second cycle at (cycle count)mod2 = c 00001cc b every fourth cycle at (cycle count)mod4 = cc 0001ccc b every eighth cycle at (cycle count)mod8 = ccc 001cccc b every sixteenth cycle a t (cycle count)mod16 = cccc 01ccccc b every thirty-second cycle at (cycle count)mod32 = ccccc 1cccccc b every sixty-fourth cycle a t (cycle count)mod64 = cccccc table 26-15 examples for valid cycle sets cycle code matching cycle counter values 0000011 b 1-3-5-7- .-63 ? 0000100 b 0-4-8-12- .-60 ? 0001110 b 6-14-22-30- .-62 ? 0011000 b 8-24-40-56 ? 0100011 b 3-35 ? 1001001 b 9 ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-226 v1.1, 2011-03 e-ray, v3.12 defaiult_congif or ?config? state only. the filter configuration in the header sections of message buffers belonging to the fifo is ignored. a valid received frame is stored in the fi fo if channel id, frame id, and cycle counter are not rejected by the configured rejection filter and rejection filter mask, and if there is no matching dedicated receive buffer. 26.6.8 transmit process the transmit process is described in the following sections. 26.6.8.1 static segment for the static segment, if there are several messages pending for transmission, the message with the frame id corresponding to the next sending slot is selected for transmission. the data section of transmit buffers assigned to the static segment can be updated until the end of the preceding time slot. this means that a transfer from the input buffer has to be started by writing to the input buffer command request register latest at this time. 26.6.8.2 dynamic segment in the dynamic segment, if several messages are pending, the message with the highest priority (lowest frame id) is selected next. only frame id?s which are higher than the largest static frame id are allowed for the dynamic segment. in the dynamic segment different slot counter sequences are possible (concurrent sending of different frame id?s on both channels). therefore pending messages are selected according to their frame id and their channel configuration bit. the data section of transmit buffers assigned to the dynamic segment can be updated until the end of the preceding slot. this means that a transfer from the input buffer has to be started by writing to the input buffer command request register latest at this time. the start of latest transmit configured by slt in the mhd configuration register 1 defines the maximum minislot value allowed before inhibiting new frame transmission in the dynamic segment of the current cycle. 26.6.8.3 transmit buffers a portion of the e-ray message buffers can be configured as transmit buffers by programming bit cfg in the header section of the respective message buffer to 1. this can be done via the write header section 1 register. there exist the following possi bilities to assign a transmit buffer to the communication controller channels: ? static segment: channel a or channel b, channel a and channel b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-227 v1.1, 2011-03 e-ray, v3.12 ? dynamic segment: channel a or channel b message buffer 0 is dedicated to hold the startup frame, the sync frame, or the designated single slot frame as configur ed by txst, txsy, and tsm in the suc configuration register 1. in this case it can be reconfigured in ?default_config? or ?config? state only. this ensures that any node transmits at most one startup / sync frame per communication cycle. transmissi on of startup / sync frames from other message buffers is not possible. all other message buffers configured for transmission in static or dynamic segment are reconfigurable during runtime. due to the organization of the data partition in the message ram (reference by data pointer), reconfiguration of the configured payload length and the data pointer in the header section of a message buffer may lead to erroneous configurations. if a message buff er is reconfigured during runtime it may happen that this message buffer is not send out in the respective communication cycle. the communication controller does not have the capability to calculate the header crc. the host is supposed to provide the header crcs for all transmit buffers. if network management is required the host has to set the ppit bit in the header section of the respective message buffer to 1 and write the network management information to the data section of the message buffer (see section 26.6.6 ). the payload length field configures the data payload length in 2-byte words. if the configured payload length of a static transmit buffer is shorter than the payload length configured for the static segment by sfdl in the message handler configuration register 1, the communication controller generates padding byte to ensure that frames have proper physical length. the padding pattern is logical zero. each transmit buffer provides a transmission mode flag txm that allows the host to configure the transmission mode for the transmit buffer in the static segment. if this bit is set, the transmitter operates in the single-shot mode. if this bit is cleared, the transmitter operates in the continuous mode. in dynamic segment the transmitter always works in single-shot mode. if a message buffer is configured in the continuous mode, the communication controller does not reset the transmission request flag txr after successful transmission. in this case a frame is sent out each time the frame id and cycle co unter filter match. the txr flag can be reset by the host by writing the respective message buffer number to the input buffer command request register while bit stxrh in the input buffer command mask register is reset to 0. if two or more transmit buffers are configured with the same frame id and cycle counter filter value, the transmit buffer with the lo west message buffer number will be transmitted in the respective slot. 26.6.8.4 frame transmission to prepare a transmit buffer for transm ission the following steps are required: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-228 v1.1, 2011-03 e-ray, v3.12 ? configure the message buffer as transmit buffer by writing bit cfg = 1 in the write header section 1 register ? write transmit message (header and data section) to the input buffer. ? to transfer a transmit message from i nput buffer to the message ram proceed as described on ?data transfer from input buffer to message ram? on page 26-233 . ? if configured in the input buffer command mask register the transmission request flag for the respective message buffer will be set as soon as the transfer has completed, and the message buffer is ready for transmission. ? check whether the message buffer has been transmitted by checking the txr bits (txr = 0) in the transmission request 1,2 registers (single-shot mode only). in single-shot mode the communication controller resets the txr flag after transmission has been completed. now the host may update the transmit buffer with the next message. the communication controller does not transmit the message before the host has indicated that the update is completed by setting the transmission request flag txr again. the host can check the actual state of the txr flags of all message buffers by reading the transmission request registers. after successful transmission, if bit wrhs1 . mbi in the header section of the respective message buffer is set, the transmit service request flag in the status service r equest register is set (txi = 1). if enabled an service request is generated. 26.6.8.5 null frame transmission if in static segment the host does not set the transmission request flag before transmit time, and if there is no other transmit buffer with matching filter criteria (matching frame id and cycle counter filter), the communicat ion controller transmits a null frame with the null frame indication bit reset to 0 and the payload data reset to zero. in the following cases the communication controller transmits a null frame with the null frame indication bit reset to 0, and the rest of the frame header and the frame length unchanged (payload data is reset to zero): ? all transmit buffers configured for the slot have cycle counter filters that do not match the current cycle ? there are matching frame id?s and cycle c ounter filters, but no ne of these transmit buffers has the transmission request flag txr set null frames are not transmitted in the dynamic segment. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-229 v1.1, 2011-03 e-ray, v3.12 26.6.9 receive process the receive process is described in the following sections. 26.6.9.1 frame reception to prepare or change a message buffer for reception the following steps are required: ? configure the message buffer as receive buffer by writing bit cfg = 0 in the write header section 1 register ? configure the receive buffer by writing the configuration data (header section) to the input buffer ? transfer the configuration from input buffer to the message ram by writing the number of the target message buffer to the input buffer command request register. once these steps are performed, the message buffer functions as an active receive buffer and participates in the internal acceptance filtering process, which takes place every time the communication controller receives a message. the first matching receive buffer is updated from the received message. if the message buffer holds an unprocessed data section (nd = 1) it is ov erwritten with the new message and the mlst bit in the respective message buffer status register is set. if the payload length of a received frame plc is longer than the value programmed by plc in the header section of the respective message buffer, the data field stored in the message buffer is truncated to that length. if no frame, a null frame, or a corrupted frame is received in a slot, the data section of the message buffer configured for this slot is not updated. in this case only the flags in the message buffer status register are updat ed to signal the cause of the problem. in addition the respective mbc flag in the mess age buffer status changed 1,2,3,4 registers is set. when the data section of a receive buffer has been updated from a received frame, the respective new data ndn (n = 0-31) to ndn (n = 96-127) flag in the new data ndat1 to ndat4 registers is set. when the message handler has updated the message buffer status, the respective mbc flag in the message buffer status changed 1,2,3,4 registers is set. if bit rdhs1 . mbi in the header section of the respective message buffer is set, the receive service request flag in the status service request register is set (rxi = 1). if enabled an service request is generated. to read a receive buffer from the message ram via the output buffer proceed as described on ?data transfer from message ram to output buffer? on page 26-235 . note: the nd and mbc flags are automatically cleared by the message handler when the received message has been tran sferred to the output buffer. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-230 v1.1, 2011-03 e-ray, v3.12 26.6.9.2 null frame reception the payload segment of a received null frame is not copied into the matching receive buffer. if a null frame has been received, the header section of the matching message buffer is updated from the rece ived null frame. the null frame indication bit in the header section 3 of the respective message buffer is reset (nfi = 0) and the respective mbc flag in the message buffer status changed 1,2,3,4 registers is set. in case that bit nd and / or mbc were al ready set before this event because the host did not read the last received message, bit ml st in the message buffer status register of the respective message buffer is also set. 26.6.10 fifo function a group of the message buffers can be config ured as a cyclic first-in-first-out (fifo). the group of message buffers belonging to the fifo is contiguous in the register map starting with the message buffer referenced by ffb and ending with the message buffer referenced by lcb in the message ram configuration register. up to 128 message buffers can be assigned to the fifo. 26.6.10.1 description every valid incoming message not matching with any dedicated receive buffer but passing the programmable fifo filter is stor ed into the fifo. in this case frame id, payload length, receive cycle count, and the st atus bits of the addressed fifo message buffer are overwritten with frame id, paylo ad length, receive cycle count, and the status from the received message and can be read by the host for message identification. bit rfne in the status service request register shows that the fifo is not empty, bit rff in the status service request register is set when the last available message buffer belonging to the fifo is written, bit rfo in the error service request register shows that a fifo overrun has been detected. if enabled, service requests are generated. there are two index registers associated with the fifo. the put index register (pidx) is an index to the next available location in the fifo. when a new message has been received it is written into the message buffer addressed by the pidx register. the pidx register is then incremented and addresses the next available message buffer. if the pidx register is incremented past the hig hest numbered message buffer of the fifo, the pidx register is loaded with the number of the first (lowest numbered) message buffer in the fifo chain. the get index register (gidx) is used to address the next message buffer of the fifo to be read. the gidx register is incremented after transfer of the contents of a message buffer belonging to the fifo to the output buffer. the put index register and the get index register are not accessible by the host. the fifo is completely filled when the put index (pidx) reaches the value of the get index (gidx). when the next message is wri tten to the fifo before the oldest message has been read, both put index and get index are incremented and the new message www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-231 v1.1, 2011-03 e-ray, v3.12 overwrites the oldest message in the fifo. this will set fifo overrun flag rfo in the error service request register. figure 26-10 fifo status: em pty, not empty, overrun a fifo non empty status is detected when the put index (pidx) differs from the get index (gidx). in this case flag rfne is set. this indicates that there is at least one received message in the fifo. the fifo empty, fifo not empty, and the fifo overrun states are explained in figure 26-10 for a three message buffer fifo. there is a programmable fifo rejection filt er for the fifo. the fifo rejection filter register (frf) defines a filter pattern for messages to be rejected. the fifo rejection filter consists of channel filt er, frame id filter, and cycle count er filter. if bit rss is set to 1 (default), all messages received in the static segment are rejected by the fifo. if bit rnf is set to 1 (default), received null frames are not stored in the fifo. the fifo rejection filter mask register (frfm) specifies which bits of the frame id filter in the fifo rejection filter register are marked ?don?t care? for rejection filtering. 26.6.10.2 configuration of the fifo for all message buffers belonging to the fifo the data pointer to the first 32-bit word of the data section of the respective message buffer in the message ram has to be configured via the write header section 3 register. all information required for acceptance filtering is taken from the fifo rejection filter and the fifo rejection filter mask and needs not be configured in the header sections of the message buffers belonging to the fifo. when programming the data pointers for the message buffers belonging to the fifo, the payload length of all message buffers should be programmed to the same value. 123 a- - buffers messages fifo empty fifo not empty fifo overrun 123 ab c buffers messages 123 -- - buffers messages pidx (store next) gidx (read oldest) gidx (read oldest) gidx (read oldest) pidx (store next) pidx (store next) ? pidx incremented last ? next received message will be stored into buffer 1 ? if buffer 1 has not been read before message a is lost www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-232 v1.1, 2011-03 e-ray, v3.12 note: it is recommended to program the mb i bits of the message buffers belonging to the fifo to 0 via wrhs1 . mbi to avoid generation of rx interrupts. if the payload length of a received fram e is longer than the value programmed by wrhs2 . plc in the header section of the respective message buffer, the data field stored in a message buffer of th e fifo is truncated to that length. 26.6.10.3 access to the fifo to read from the fifo the host has to tri gger a transfer from the message ram to the output buffer by writing the number of the first message buffer of the fifo (referenced by ffb) to the output buffer command request register. the message handler then transfers the message buffer addressed by the get index register (gidx) to the output buffer. after this transfer the get in dex register (gidx) is incremented. 26.6.11 message handling the message handler controls data transfers between the input / output buffer and the message ram and between the message ram a nd the two transient buffer rams. all accesses to the internal ram?s are 32 bit accesses. access to the message buffers stored in the message ram is done under control of the message handler state machine. this avoids conflicts between accesses of the two protocol controllers and the host to the message ram. frame ids of message buffers assigned to the static segment have to be in the range from 1 to nss as configured in the gtu configuration register 7. frame ids of message buffers assigned to the dynamic segment have to be in the range from nss + 1 to 2047. received messages with no matching dedicated receive buffer (static or dynamic segment) are stored in the receive fifo (if configured) if they pass the fifo rejection filter. 26.6.11.1 host access to message ram the message transfer between input buffer and message ram as well as between message ram and output buffer is triggered by the host by writing the number of the target / source message buffer to be accessed to the input or output buffer command request register. the input / output buffer command mask registers can be used to write / read header and data section of the selected message buffer separately. if bit stxrs in the input buffer command mask register is set ( stxrs = 1), the transmission request flag txr of the selected message buffer is automatically set after the message buffer has been updated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-233 v1.1, 2011-03 e-ray, v3.12 if bit stxrs in the input buffer command mask register is reset ( stxrs = 0), the transmission request flag txr of the select ed message buffer is reset. this can be used to stop transmission from message bu ffers operated in continuous mode. input buffer (ibf) and the output buffer (o bf) are build up as a double buffer structure. one half of this double buffer structure is accessible by the host (ibf host / obf host), while the other half (ibf shadow / obf shadow) is accessed by the message handler for data transfers between ibf / obf and message ram. figure 26-11 host access to message ram data transfer from input buffer to message ram to configure / update a message buffer in the message ram, the host has to write the data to wrdsnn (nn = 01-64) and the header to wrhs1 , wrhs2 , wrhs3 . two sets of wrdsnn (nn = 01-64) are available in parallel and selected by cust1 . ibf1pag and cust1 . ibf2pag . cust1 . ibfs shows which input buffer is currently used as input shadow buffer and which as input host buffer. wrhs1 , wrhs2 , and wrhs2 does only exist once. the specific action is sele cted by configuring the input buffer command mask ibcm . data[31:0] data[31:0] address data[31:0] data[31:0] address- input buffer message handler address output buffer decoder & control control host header partition data partition message ram [shadow] [shadow] address www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-234 v1.1, 2011-03 e-ray, v3.12 when the host writes the number of the target message buffer in the message ram to ibrh in the input buffer command request register ibcr , ibf host and ibf shadow are swapped (see figure 26-12 ). figure 26-12 double buffer structure input buffer in addition the bits in the input buffer command mask and input buffer command request registers are also swapped to keep them attached to the respective ibf section (see figure 26-13 ). figure 26-13 swapping of ibcm and ibcr bit with this write opera tion the ibsys bit in th e input buffer command request register is set to 1. the message handler then starts to transfer the contents of ibf shadow to the message buffer in the message ram selected by ibrs. while the message handler transfers the data from ibf shadow to the target message buffer in the message ram, the host may write the next message to ibf host. after the transfer between ibf shadow and the message ram has completed, the ibsys bit is set back to 0 and the next transfer to the message ram may be started by the host by writing the respective target message buffer number to ibrh in the input buffer command request register. if a write access to ibrh occurs while ibsys is 1, ibsyh is set to 1. after completion of the ongoing data transfer from ibf shadow to the message ram, ibf host and ibf shadow are swapped, i bsyh is reset to 0, ibsys remains set to 1, and the next transfer host message ram e-ray ibf ibf sha dow ibf = input buffer host ibcm ibcr swap swap 1 0 2 17 16 18 1 0 2 4 3 5 20 19 21 17 16 18 31 15 6 22 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-235 v1.1, 2011-03 e-ray, v3.12 to the message ram is started. in addition the message buffer numbers stored under ibrh and ibrs and the command mask flags are also swapped. data transfer from messa ge ram to output buffer to read a message buffer from the message ram, the host has to write to command request register obcr to trigger the data transfer as configured in output buffer command mask obcm register. after the transfer has completed, the host can read the transferred data from rddsnn (nn = 01-64) , rdhs1 , rdhs2 , rdhs2 , and mbs . table 26-16 assignment of input buffer command mask bit pos. access bit function 18 rh stxrs set transmission request shadow 17 rh ldss load data section shadow 16 rh lhss load header section shadow 2rw stxrh set transmission request host 1rw ldsh load data section host 0rw lhsh load header section host table 26-17 assignment of input buffer command request bit pos. access bit function 31 rh ibsys ibf busy shadow, signals ongoing transfer from ibf shadow to message ram 21 ? 16 rh ibrs ibf request shadow, number of message buffer currently / last updated 15 rh ibsyh ibf busy host, transfer request pending for message buffer referenced by ibrh 5-0 rwh ibrh ibf request host, number of message buffer to be updated next www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-236 v1.1, 2011-03 e-ray, v3.12 figure 26-14 double buffer structure output buffer obf host and obf shadow as well as bits obcm . rhss , obcm . rdss , obcm . rhsh , obcm . rdsh and bits obcr . obrs , obcr . obrh are swapped under control of bits obcr . view and obcr . req . writing bit obcr . req to 1 copies bits obcm . rhss , obcm . rdss and bits obcr . obrs to an internal storage (see figure 26-15 ). after setting obcr . req to 1, obcr . obsys is set to 1, and the transfer of the message buffer selected by obcr . obrs from the message ram to obf shadow is started. after the transfer between the message ram and obf shadow has completed, the obcr . obsys bit is set back to 0. bits obcr . req and obcr . view can only be set to 1 while obcr . obsys is 0. figure 26-15 swapping of obcm and obcr bit obf host and obf shadow are swapped by setting bit obcr . view to 1 while bit obcr . obsys is 0 (see figure 26-14 ). in addition bits obcr . obrh and bits obcm . rhsh , obcm . rdsh are swapped with the registers internal storage thus assuring that the message buffer number stored in host message ram e-ray obf obf sha dow obf = output buffer host obcm obcr 1 0 2 4 3 5 20 19 21 17 16 18 1 0 15 17 16 8 9 1 0 2 4 3 5 view request 1 0 view request internal storage internal storage 6 22 6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-237 v1.1, 2011-03 e-ray, v3.12 obcr . obrh and the mask configuration stored in obcm . rhsh , obcm . rdsh matches the transferred data stored in obf host (see figure 26-15 ). now the host can read the transferred message buffer from obf host while the message handler may transfer the next message from the message ram to obf shadow. 26.6.11.2 data transfers between ibf / obf and message ram this document uses the following terms and abbreviations: table 26-18 assignment of output buffer command mask bit pos. access bit function 17 rh rdsh data section available for host access 16 rh rhsh header section available for host access 1 rw rdss read data section shadow 0 rw rhss read header section shadow table 26-19 assignment of output buffer command request bit pos. access bit function 22 ? 16 rh obrh obf request host, number of message buffer available for host access 15 rh obsys obf busy shadow, signals ongoing transfer from message ram to obf shadow 9rwreq request transfer from message ram to obf shadow 8 rwh view view obf shadow, swap obf shadow, and obf host 6 ? 0 rwh obrs obf request shadow, number of message buffer for next request table 26-20 terms and abbreviations term meaning mhd message handler ibf input buffer 1 or 2 ram obf output buffer 1 or 2 ram mbf message buffer ram tbf transient buffer ram channel a (tbf1) or channel b (tbf2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-238 v1.1, 2011-03 e-ray, v3.12 message handler functionality the mhd controls the access to the mbf. it manages data-transfer between mbf and ibf, obf, tbf1, tbf2. the data-path are shown in figure 26-16. figure 26-16 interconnection of rams furthermore a search-algorithm allows to find the next valid message object in the mbf for transmission or reception. each transfer consists of a setup-time, four time steps to transfer the header-section and a payload-length-dependent number of time steps to transfer the data-section. the internal data-busses have a width of 32 bits. t hereby it is possible to transfer two 2-byte words in one time step. if the payload consists of an odd number of 2-byte words the last time step of the data-section contains only 16 bit of valid data. if the payload-length (pl) is e.g. 7, the data-section consists of 4 time steps. the maximum length for the data-section is 64 time steps, the minimum length is zero time steps. ibf ? mbf transfer from ibf to mbf mbf ? obf transfer from mbf to obf mbf ? tbf transfer from mbf to tbf tbf ? mbf transfer from tbf to mbf ss slot status ss ? mbf transfer ss to mbf table 26-20 terms and abbreviations (cont?d) ibf obf tbf1 tbf2 mbf mhd www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-239 v1.1, 2011-03 e-ray, v3.12 figure 26-17 different possible buffer transfers the update of the slot-status consists of a setup-time and one time-step to write the new slot-status. figure 26-18 update of slot status the length of a time step depends on the number of concurrent tasks. the following concurrent tasks are executed under control of the message handler: ? data transfer between ibf or obf and mbf ? data transfer between tbf1 and mbf, search next tx / rx message buffer cha ? data transfer between tbf2 and mbf, search next tx / rx message buffer chb thereby the time step length can vary between one and three f clc_eray periods. under certain conditions it is possible that a transfer is stopped or interrupted for a number of time steps until it is continued. when a ib f ? mbf is started short after a tbf ? mbf or ss ? mbf the transfer from ibf has to wait until the setup-time of the inte rnal transfer has finished (see figure 26-19) mbs hs1 hs3 hs2 hs1 hs2 hs3 mbs hs1-rd mbs-rd hs2-rd hs3-rd start start hs1 hs2 hs3 mbs start idle start hs1 hs2 hs3 mbs ibf ? mbf mbf ? obf mbf ? tbf tbf ? mbf idle idle idle ... dw1/2 dw3/4 dw5/6 dw127 ... dw1/2 dw3/4 dw5/6 dw127 ... dw1/2 dw3/4 dw5/6 dw127 ... dw1/2 dw3/4 dw5/6 dw127 header-section setup-time data-section hs1-rd mbs start mbs-rd ss ? mbf idle header-section setup-time www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-240 v1.1, 2011-03 e-ray, v3.12 figure 26-19 delay start of ibf ? mbf the internal signal ?disable_i2m? is always active when the tbf ? mbf is in state ?hs1- rd?, ?hs2-rd?, ?hs3-rd? or ?mbs-rd? and when the ss ? mbf is in state ?hs1-rd? or ?mbs- rd?. the ibf ? mbf is hold in state ?start? until the internal signal ?disable_i2m? gets inactive. these additional time-steps are independent of any address-counter-values. this means, the ibf ? mbf has to wait even if it writes to another buffer than the internal transfer. multiple requests of transfers between ibf/obf and message ram the time required to transfer the contents of a message buffer between ibf / obf and message ram depends on the number of 4-byte words to be transferred, the number of concurrent tasks to be managed by the message handler, and in special cases the type and address range of the internal transfer. the number of 4-byte words varies from 4 (header section only) to 68 (header + maximum data section) plus a short setup time to start the first transfer, while the number of concurrent task varies from one to three. the 4 header words have to be included in calculation even if only the data section is requested for transfer. the following concurrent tasks are executed under control of the message handler: ? data transfer between ibf or obf and mbf ? data transfer between tbf1 and mbf, search next tx / rx message buffer cha ? data transfer between tbf2 and mbf, search next tx / rx message buffer chb transfers between ibf and mbf respectively mbf and obf can only be handled one after another. in case that e.g. a ibf ? mbf has been started shortly before a dw127 start start start start start start start start idle idle idle idle hs1-rd hs1-rd mbs-rd hs2-rd hs3-rd mbs hs2 hs3 hs2 hs1 hs3 mbs dw1/2 dw3/4 dw5/6 ... ibf=>mbf hs1 hs2 mbs tbf=>mbf start hs1 hs3 mbs disable_i2m ss=>mbf start mbs-rd ibf=>mbf disable_i2m dw127 dw1/2 dw3/4 dw5/6 ... dw127 dw1/2 dw3/4 dw5/6 ... dw127 dw1/2 dw3/4 dw5/6 ... www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-241 v1.1, 2011-03 e-ray, v3.12 mbf ? obf is requested, the mbf ? obf has to wait until the ibf ? mbf has completed. in case that e.g. a second ibf ? mbf is requested, a mbf ? obf is requested and a ibf ? mbf is ongoing, the mbf ? obf has to wait until the first ibf ? ibf has completed. the second ibf=mbf has to wait until the mbf ? obf has completed (see figure 26-20) independent whether mbf ? obf or second ibf ? mbf is requested first. figure 26-20 multiple ibf/obf request worst case for single request when a message with a large payload length is received the tbf ? mbf is started at the begin of the next slot (n+1). if the next slot is a dynamic slot without transmission/reception (minislot), it may happen that the tbf ? mbf has not finished until begin of the next but one slot (n+2). in this case the tbf ? mbf will be service requested (break) to start a transmission in the next but one slot (mbf ? tbf) and/or to update the slot status (ss ? mbf) for the rx-buffer corresponding with next slot (n+1). after this interruption the tbf ? mbf is continued. figure 26-21 address counter scheme of message ram (simplified) for the transfers ibf ? mbf / mbf ? obf, tbf ? mbf and mbf ? tbf separate address-counter are impl emented (see figure 26-21). write to ibcr-register write to obcr-register ibf ? mbf mbf ? obf 1 1 2 3 3 2 acnt_mbf addr_mbf(10?0) acnt_mbf_find_reg acnt_mbf_t2m_reg acnt_mbf_m2t_reg acnt_mbf_io_reg www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-242 v1.1, 2011-03 e-ray, v3.12 figure 26-22 interruption of tbf ? mbf if the address-counter for ibf ? mbf / mbf ? obf (acnt_mbf_io_reg) reaches the address of the interrupted tbf=>mbf (acnt_mbf_t2m_reg) the ibf ? mbf / mbf ? obf has to wait until the tbf ? mbf is continued (see figure 26-22). the relative time is measured in f clc_eray cycles. absolute time depends on the actual f clc_eray cycle period. tbf_to_mbf_break time max = (setup time + mbf_to_tbf time max ) + (setup time + ss_to_mbf) cycles req = (number of concurrent tasks) ( (setup time+ (number of 4-byte words) req ) + tbf_to_mbf_break time) setup time = 2 f clc_eray cycles slot counter nn+1 n+2 tbf ? mbf ibf ? mbf or mbf ? obf break wait mbf ? tbf ss ? mbf www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-243 v1.1, 2011-03 e-ray, v3.12 worst case for one ibf ? mbf or mbf ? obf: worst case for multiple transfers if a second ibf ? mbf and a mbf ? obf (see figure 26-20) is requested directly after the first ibf ? mbf has started following worst case timing could appear: 26.6.11.3 minimum f clc_eray to calculate the minimum f clc_eray the worst case scenario has to be considered. the worst case scenario depends on the following parameters ? maximum payload length ? minimum minislot length ? number of configured message buffers (excluding fifo) ? used channels (single/dual channel) figure 26-23 worst case scenario max. break time: tbf_to_mbf_break time max = (2+68) + (4+1) = 75 max. number of f clc_eray cycles: cycles req = 3 (6 + 68 + 75) = 435 cycles trans = (remaining cycles of transfer running) + (cycles of second requested transfer) + (cycles of third requested transfer) cycles trans = cycles rem + cycles req_2 + cycles req_3 max. number of f clc_eray cycles: cycles trans = 447 + 435 + 447 = 1329 slot counter n (receive) tbf ? mbf find sequence ss ? mbf n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-244 v1.1, 2011-03 e-ray, v3.12 worst case scenario: ? reception of message with a maximum payload length in slot n (n is 7,15,23,31,39,?) ? slot n+1 to n+7 are empty dynamic slots (minislot) and configured as receive buffer ? the find-sequence (usually started in slot 8,16,24,32,40,?) has to scan the maximum number of configured buffers ? the number of concurrent tasks has its maximum value of three the find-sequence is executed each 8 slots (s lot 8,16,24,32,40,?). it has to be finished until the next find-sequence is requested. the length of a tbf ? mbf varies from 4 (header section only) to 68 (header + maximum data section) time step plus a setup time of 6 time steps. a ss ? mbf has a fixed length of 1 time steps plus a setup time of 4 time steps. the find sequence has a maximum length of 128 (maximum number of buffers) time steps plus a setup time of 2 time steps. a minislot has a length of 2 to 63 macrotick (gdminislot). the minimum nominal macrotick period (cdminmtnom) is 1 s. a sequence of 8 minislots has a length of f clc_eray cycles t2m = number of concurrent tasks) (setup time t2m + (number of 4-byte words) t2m ) f clc_eray cycles ss2m = (number of concurrent tasks) 5 f clc_eray cycles find = (number of concurrent tasks) (setup time find + (number of configured buffers)) time 8minislots =8 gdminislot cdminmtnom www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-245 v1.1, 2011-03 e-ray, v3.12 the maximum period t clc_eray = 1/ f clc_eray can be calculated as followed: the minimum f clc_eray frequency for this worst case scenario is 44.8125 mhz. a too low f clc_eray frequency can cause a malfunction of the e-ray. the e-ray can detect several malfunctions and reports this by setting the corresponding flag in the message handler constraints flags ( mhdf ) register. minimum f clc_eray for various maxi mum payload length table 26-21 summarizes the minimum required f clc_eray frequency for various maximum payload length assuming: ? a minimum minislot length of 2 s. ? a maximum of 128 configured message buffers. ? dual channels in use. minimum f clc_eray for various minimu m minislot length table 26-22 summarizes the minimum required f clc_eray frequency for various minimum minislot length assuming: time 8minislots ( f clc_eray period in s) (( f clc_eray cycles t2m ) + 7 ( f clc_eray cycles ss2m ) + ( f clc_eray cycles find )) f clc_eray period in ms minimum time 8minislots = 8 2 1 s = 16 s maximum f clc_eray cycles t2m = 3 (6 + 68) = 222 maximum f clc_eray cycles ss2m = 3 * 5 = 15 maximum f clc_eray cycles find = 3 * (2 + 128) = 390 f clc_eray period in ms table 26-21 minimum f clc_eray for different maximum payload length maximum payload length of 32 bit words 4 8 163264 minimum f clc_eray 32,82 mhz 33,57 mhz 35,07 mhz 38,07 mhz 44,82 mhz time 8mnislots cycles t2m () 7cycles ss2m () cycles find () + + ------------------------------------------------------------------------------------------------------------------ 16 s 222 7 15 390 + + --------------------------------------------- - 22.315?ns = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-246 v1.1, 2011-03 e-ray, v3.12 ? a maximum payload length of 254 bytes / 64 four-byte-words. ? a maximum 128 configured message buffers. ? dual channels in use. minimum f clc_eray for various amount of configured message buffers table 26-23 summarizes the minimum required f clc_eray frequency for various amount of configured message buffers assuming: ? a maximum payload length of 254 bytes / 64 four-byte-words. ? a minimum minislot length of 2 s. ? dual channels in use. minimum f clc_eray for a typical configuration the minimum required f clc_eray frequency for various assuming the following typical e- ray configuration: ? a maximum payload length of 32 bytes / 8 four-byte-words. ? a minimum minislot length of 7 s. ? a maximum 128 configured message buffers. ? dual channels in use the minimum f clc_eray frequency for this typical example would be 10 mhz. table 26-22 minimum f clc_eray for different mini mum minislot length gdminislot at dminmtnom = 1 s 2 s3 s4 s7 s8 s minimum f clc_eray 44,82 mhz 29,88 mhz 22,412 mhz 12,8 mhz 9,96 mhz table 26-23 minimum f clc_eray for different amount of configured message buffers configured maximum amount of message buffers 128 64 32 minimum f clc_eray 44,82 mhz 32,82 mhz 26,82 mhz www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-247 v1.1, 2011-03 e-ray, v3.12 26.6.11.4 flexray? protocol cont roller access to message ram the two transient buffer rams (tbf 1, tbf 2) are used to buffer the data for transfer between the two flexray? protocol controllers and the message ram. each transient buffer ram is build up as a double buffer, able to store two complete flexray? messages. there is always one buffer assigned to the corresponding protocol controller while the other one is accessible by the message handler. if e.g. the message handler writes the next message to be send to transient buffer tx, the flexray? channel protocol controller can access transient buffer rx to store the message it is actually receiving. during transmission of the message stored in transient buffer tx, the message handler transfers the last received message stored in transient buffer rx to the message ram (if it passes acceptance filtering) and updates the respective message buffer. data transfers between the transient buffer rams and the shift registers of the flexray? channel protocol controllers are done in words of 32 bit. this enables the use of a 32 bit shift register independent of the length of the flexray? messages. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-248 v1.1, 2011-03 e-ray, v3.12 figure 26-24 access to transient buffer rams 26.6.12 message ram to avoid conflicts between host access to the messa ge ram and flexray? message reception / transmission, the host cannot directly access the me ssage buffers in the message ram. these accesses are handled via the input and output buffers. the message ram is able to store up to 128 message buffers depending on the configured payload length. the message ram is organized 2048 x 32. to achieve the required flexibility with respect to different numbers of data byte per flexray? frame (0 to 254), the message ram has a structure as shown in figure 26-25 . the data partition is allowed to start at message ram word number: (mrc.lcb + 1) ? 4 address-decoder transient buffer tx transient buffer rx shift register control address data[31:0] data[31:0] txda rxda control address data[31:0] data[31:0] txdb rxdb shift register flexray? prt a flexray? prt b address-decoder transient buffer tx transient buffer rx message handler tbf 1 tbf 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-249 v1.1, 2011-03 e-ray, v3.12 figure 26-25 structu re of message ram header partition stores header segments of flexray? frames: ? supports a maximum of 128 message buffers ? each message buffer has a header of four 32 bit words ? header 3 of each message buffer holds the11 bit pointer to the respective data section in the data partition data partition flexible storage of data sections with different length. some maximum values are: ? 30 message buffers with 254 byte data section each ? or 56 message buffers with 128 byte data section each ? or 128 message buffers with 48 byte data section each restriction: header partition + data partition may not occupy more than 2048 32-bit words. header mb0 header mb1 . . . header mbn data mb0 data mbn . . . data mb1 message ram 32 bit header sectio n data section 2048 words www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-250 v1.1, 2011-03 e-ray, v3.12 26.6.12.1 header partition the header of each message buffer occupies four 32-bit words in the header partition of the message ram. the header of message bu ffer 0 starts with the first word in the message ram. for transmit buffers the header crc has to be calculated by the host. payload length received plr , receive cycle count rcc , received on channel indication rci , startup frame indication bit sfi , sync bit syn , null frame indication bit nfi , payload preamble indication bit ppi , and reserved bit res are only updated from received valid frames (including valid null frames). header word 4 of each configured message buffer holds the respective message buffer status mbs information. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-251 v1.1, 2011-03 e-ray, v3.12 table 26-24 header section of a message buffer in the message ram bit word 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 1 m b i t x m n m e c f g c h b c h a cycle code frame id 2 payload length received payload length configured tx buffer: header crc configured rx buffer: header crc received 3 r e s p p i n f i s y n s f i r c i receive cycle count data pointer 4 r e s s p p i s n f i s s y n s s f i s r c i s cycle count status t f b f t y m l s t e s b e s a t c i b t c i a s v o b s v o a c e o b c e o a s e o b s e o a v f r b v f r a frame configuration filter configuration message buffer control message ram configuration updated from received frame message buffer status unused www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-252 v1.1, 2011-03 e-ray, v3.12 header 1 (word 0) write access via wrhs1 , read access via rdhs1 : ? frame id: slot counter filtering configuration ? cycle code: cycle counter filtering configuration ? cha, chb: channel filtering configuration ? cfg: message buffer configuration: receive / transmit ? ppit: payload preamble indicator transmit ? xmi: transmit mode configurat ion: single-shot / continuous ? mbi: message buffer receive / transmit service request enable header 2 (word 1) write access via wrhs2 , read access via rdhs2 : ? header crc ? transmit buffer: configured by the host (calculated from frame header segment) ? receive buffer: updated from received frame ? payload length configured ? length of data section (2-byte words) as configured by the host ? payload length received ? length of payload segment (2-byte words) stored from received frame header 3 write access via wrhs3 , read access via rdhs3 : ? data pointer ? pointer to the beginning of the corresponding data section in the data partition read access via rdhs3 , valid for receive buffers only, updated from received frames: ? receive cycle count: cycle count from received frame ? rci: received on channel indicator ? sfi: startup frame indicator ? syn: sync frame indicator ? nfi: null frame indicator ? ppi: payload preamble indicator ? res: reserved bit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-253 v1.1, 2011-03 e-ray, v3.12 message buffer status mbs (word 3) read access via mbs, updated by the communication controller at the end of the configured slot. ? vfra: valid frame received on channel a ? vfrb: valid frame received on channel b ? seoa: syntax error observed on channel a ? seob: syntax error observed on channel b ? ceoa: content error observed on channel a ? ceob: content error observed on channel b ? svoa: slot boundary violation observed on channel a ? svob: slot boundary violation observed on channel b ? tcia: transmission conflict indication channel a ? tcib: transmission conflict indication channel b ? esa: empty slot channel a ? esb: empty slot channel b ? mlst: message lost ? fta: frame transmitted on channel a ? fta: frame transmitted on channel b ? cycle count status: actual cycle count when status was updated ? rcis: received on channel indicator status ? sfis: startup frame indicator status ? syns: sync frame indicator status ? nfis: null frame indicator status ? ppis: payload preamb le indicator status ? ress: reserved bit status 26.6.12.2 data partition the data partition of the message ram stores the data sections of the message buffers configured for reception / transmission as defined in the header partition. the number of data bytes for each message buffer can vary from 0 to 254. to optimize the data transfer between the shift registers of the two flexray? protocol controllers and the message ram as well as between the host interface and the message ram, the physical width of the message ram is set to 4 bytes. the data partition starts after the last word of the header partition. when configuring the message buffers in the message ram the programmer has to assure that the data pointers point to addresses within the data partition. table 26-25 below shows an example how the data sections of the configured message buffers can be stored in the data partition of the message ram. the beginning and the end of a message buffer?s data section is determined by the data pointer and the payload length configured in the message buffer?s header section, www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-254 v1.1, 2011-03 e-ray, v3.12 respectively. this enables a flexible usage of the available ram space for storage of message buffers with different data length. if the size of the data section is an odd number of 2-byte words, the remaining 16 bits in the last 32-bit word are unused (see table 26-25 below) 26.6.12.3 ecc check there is an ecc checking mechanism implemented in the e-ray module to assure the integrity of the data stored in the seven ram blocks of the module. the ram blocks have an ecc generator / checker attached as shown in figure 26-26 . when data is written to a ram block, the local ecc generator generates the ecc data. the ecc data is stored together with the respective data word. the ecc data is checked each time a data word is read from any of the ram blocks. if an ecc error is detected, the respecti ve error flag is se t. the ecc error flags mhds . eibf , mhds . eobf , mhds . emr , mhds . etbf1 , mhds . etbf2 , and the faulty message buffer indicators mhds . fmbd , mhds . mfmb , mhds . fmb are located in the message handler status register. these error flags control the error interrupt flag eir . eerr . table 26-25 example for structure of the data section in the message ram bit word 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 876543210 unused unused unused unused unused unused unused unused mb1 data3 mb1 data2 mb1 data1 mb1 data0 mb1 data(n) mb1 data(n-1) mb1 data(n-2) mb1 data(n-3) mb1 data3 mb1 data2 mb1 data1 mb1 data0 mb1 data(k)0 mb1 data(k-1)0 mb1 data(k-2)0 mb1 data(k-3)0 2046 mb80 data3 mb80 data2 mb80 data2 mb80 data0 2047 unused unused mb80 data5 mb80 data4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-255 v1.1, 2011-03 e-ray, v3.12 figure 26-26 ecc generation and check when an ecc error has been detected the follo wing actions w ill be performed: in all cases ? the respective ecc error flag in the message handler status mhds register is set ? the ecc error flag eir . eerr in the error service request register is set, and if enabled, a module service request to the host will be generated. eg ec ec eg eg ec ecc generator ecc checker ec ec message ram transient buffer ram a transient buffer ram b prt a prt b output buffer ram 1,2 eg eg ec eg input buffer ram 1,2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-256 v1.1, 2011-03 e-ray, v3.12 additionally in specific cases 1. ecc error in data transfer from input buffer ram 1,2 ? message ram (transfer of header and data section) a) mhds . eibf bit is set b) mhds . fmbd bit is set to indicate that mhds . fmb has been updated c) mhds . fmb indicates the number of the faulty message buffer d) transmit buffer: transmission request for t he respective message buffer is not set 2. ecc error in data transfer from input buffer ram 1,2 ? message ram (transfer of data section only) a) mhds . emr bit is set b) mhds . fmbd bit is set to indicate that mhds . fmb points to a faulty message buffer c) mhds . fmb indicates the number of the faulty message buffer d) the data section of the respective message buffer is not updated e) transmit buffer: transmission request for t he respective message buffer is not set 3. ecc error during host reading input buffer ram a) ? mhds . eibf bit is set 4. ecc error during scan of header sections in message ram a) mhds . emr bit is set b) mhds . fmbd bit is set to indicate that mhds . fmb points to a faulty message buffer c) mhds . fmb indicates the number of the faulty message buffer d) ignore message buffer (message buffer is skipped) 5. ecc error during data transfer from message ram ? transient buffer ram a, b a) mhds . emr bit is set b) mhds . fmbd bit is set to indicate that mhds . fmb points to a faulty message buffer c) mhds . fmb indicates the number of the faulty message buffer d) frame not transmitted, fram es already in transmission are invalidated by setting the frame crc to zero 6. ecc error during data transfer from transient buffer ram a, b ? protocol controller 1, 2 a) mhds . etbf1 , mhds . etbf2 bit is set 7. ecc error in data transfer from transient buffer ram a, b ? message ram (ecc error when reading header section of respective message buffer from message ram) a) mhds . emr bit is set b) mhds . fmbd bit is set to indicate that mhds . fmb points to a faulty message buffer c) mhds . fmb indicates the number of the faulty message buffer d) the data section of the respective message buffer is not updated www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-257 v1.1, 2011-03 e-ray, v3.12 8. ecc error in data transfer from transient buffer ram a, b ? message ram (ecc error when reading transient buffer ram a, b) a) mhds . etbf1 , mhds . etbf2 bit is set b) mhds . fmbd bit is set to indicate that mhds . fmb points to a faulty message buffer c) mhds . fmb indicates the number of the faulty message buffer 9. ecc error during data transfer from message ram ? output buffer ram a) mhds . emr bit is set b) mhds . fmbd bit is set to indicate that mhds . fmb points to a faulty message buffer c) mhds . fmb indicates the number of the faulty message buffer 10. ecc error during host reading output buffer ram a) ? mhds . eobf bit is set 11. ecc error during data read of transient buffer ram a, b if an ecc error occurs while the mess age handler reads a frame with network management information (ppi = 1) from the transient buffer ram a, b the corresponding network management vector registers nmv1 to nmv3 are not updated from that frame. 26.6.13 host handling of errors an ecc error caused by transient bit flips can be fixed by: 26.6.13.1 self-healing ecc errors located in ? input buffer ram 1,2 ? output buffer ram 1,2 ? data section of message ram ? transient buffer ram a ? transient buffer ram b are overwritten with the next write access to the disturbed bit(s) caused by host access or by flexray communication. 26.6.13.2 clear_rams command when called in default_config or co nfig state poc command clear_rams initializes all module-internal rams to zero. 26.6.13.3 temporary unlocking of header section an ecc error in the header section of a locked message buffer can be fixed by a transfer from the input buffer to the locked buffer header section. for this transfer, the write- www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-258 v1.1, 2011-03 e-ray, v3.12 access to the ibcr (specifying the message buffer number) must be immediately preceded by the unlock sequence normally used to leave config state (see ?lock register (lck)? on page 26-39 ). for that single transfer the respective me ssage buffer header is unlocked, regardless whether it belongs to the fifo or whether its locking is controlled by mrc.sec[1:0], and will be updated with new data. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-259 v1.1, 2011-03 e-ray, v3.12 26.7 module service request in general, service requests provide a close link to the protocol timing as they are triggered almost immediately when an error or status change is detected by the controller, a frame is received or transmi tted, a configured timer service request is activated, or a stop watch event occurred. this enables the host to react very quickly on specific error conditions, status changes, or timer events. on the other hand too many service requests can cause the host to miss deadlines required for the application. therefore the communication controller supports disable / enable controls for each individual service request source separately. an service request may be triggered when ? an error was detected ? a status flag is set ? a timer reaches a preconfigured value ? a message transfer from input buffer to message ram or from message ram to output buffer has completed ? a stop watch event occurred tracking status and generating service requ ests when a status change or an error occurs are two independent tasks. regardless of whether an service request is enabled or not, the corresponding status is tracked and indicated by the communication controller. the host has access to the actual status and error information by reading the error service request register eir and the status service request sir register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-260 v1.1, 2011-03 e-ray, v3.12 table 26-26 module service request flags and service request line enable register bit function sir wst wakeup status cas collision avoidance symbol cycs cycle start service request txi transmit service request rxi receive service request rfne receive fifo not empty rff receive fifo full nmvc network management vector changed ti0 timer service request 0 ti1 timer service request 1 tibc transfer input buffer completed tobc transfer output buffer completed swe stop watch event sucs startup completed successfully mbsi message buffer status interrupt sds start of dynamic segment wupa wakeup pattern channel a mtsa mts received on channel a wupb wakeup pattern channel b mtsb mts received on channel b ile eint0 enable service request line 0 eint1 enable service request line 1 eir pemc protocol error mode changed cna command not valid sfbm sync frames below minimum sfo sync frame overflow ccf clock correction failure ccl chi command locked eerr ecc error rfo receive fifo overrun www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-261 v1.1, 2011-03 e-ray, v3.12 the interrupt lines to the host tint0sr and tint1sr are controlled by the enabled interrupts. in addition each of the two interrupt lines can be enabled / disabled separately by programming bit ile.eint0/int0src.sre and ile.eint1/ int1src.sre. the interrupt lines to the host ndat0sr and ndat1sr are controlled by the enabled new data interrupts ( ndic1 to ndic4 ). in addition each of the two interrupt lines can be enabled / disabled separately by programming bit ndat0src.sre and ndat1src.sre. the interrupt lines to the host mbsc0sr and mbsc1sr are controlled by the enabled new data interrupts ( msic1 to msic4 ). in addition each of the two interrupt lines can be enabled / disabled separately by programming bit mbsc0src.sre and mbsc1src.sre. the two timer service requests generated by service request timer 0 and 1 are available on pins tint0sr and tint1sr. they can be configured via the timer 0 and timer 1 configuration register. in addition each of the two interrupt lines can be enabled / disabled separately by programmi ng bit tint0src.sre and tint1src.sre. a stop watch event may be triggered via input pin stpwn. the status of the data transfer between ibf / obf and the message ram is signalled on signals ibusy and obusy. when a transfer has completed bit sir . tibc or sir . tobc is set. eir efa empty fifo access iiba illegal input buffer access ioba illegal output buffer access mhf message handler constraints flag eda error detected on channel a ltva latest transmit violation channel a taba transmission across boundary channel a edb error detected on channel b ltvb latest transmit violation channel b tabb transmission across boundary channel b table 26-26 module service request flags and service request line enable register bit function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-262 v1.1, 2011-03 e-ray, v3.12 26.8 restrictions the following restrictions have to be considered when programming the e-ray ip- module. a violation of these restrictions may lead to an erroneous behavior of the e-ray ip-module. 26.8.1 message buffers with the same frame id if two or more message buffers are configured with the same frame id, and if they have a matching cycle counter filter value for the sa me slot, then the mess age buffer with the lowest message buffer number is used. sharing of a static time slot via cycle coun ter filtering between different no des of a flexray? network is not allowed. 26.8.2 data transfers between ibf / obf and message ram the time required to transfer the contents of a message buffer between ibf / obf and message ram depends on the setup time to star t the first transfer, the number of 4-byte words to be transferred, and the number of concurrent tasks to be managed by the message handler. the number of 4-byte words varies from 4 (header section only) to 68 (header + maximum data section) while the number of concurrent task varies from one to three. the following concurrent tasks are executed under control of the message handler: ? data transfer between ibf or obf and message ram ? data transfer between tbf1 and message ram, search next tx / rx message buffer cha ? data transfer between tbf2 and message ram, search next tx / rx message buffer chb transfers between ibf and message ram respectively message ram and obf can only be handled one after another. in case that e.g. a transfer between ibf and message ram has been started shortly before a transfer between message ram and obf is requested, the obf transfer has to wait until the ibf transfer has completed. the relative time is measured in f clc_eray cycles. absolute time depends on the actual f clc_eray cycle period. cyclestrans = (remaining cycles of transfer r unning) + (cycles of requested transfer) cyclestrans = cyclesrem + cyclesreq cyclesrem = (number of concurre nt tasks) * (setup time + (number of 4-byte words)rem) cyclesreq = (number of concurrent tasks) * (s etup time + (number of 4-byte words)req) setup time = 2 f clc_eray cycles under worst case conditions a transfer is requested directly after the previous transfer started: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-263 v1.1, 2011-03 e-ray, v3.12 max. number of f clc_eray cycles: cyclestrans = (3 * (2 + 68)) + (3 * (2 + 68)) = 420 worst case timing: timetrans(40mhz) = 420 * 25ns = 10.5 ms 26.9 e-ray module implementation this section describes the e-ray interfaces as implemented in TC1798 with the clock control, port and dma connections, interrupt control, and address decoding. figure 26-27 shows a detailed view of the e-ray interface. figure 26-27 detailed block diagram of the e-ray interface 26.9.1 interconnections of the e-ray module the e-ray module has 2 flexray? communication channels, channel a and channel b. each channel provides a set of signals to drive a bus driver. the e-ray module requires two different clocks, a sa mpling clock of the flexray? bus f sclk . f sclk has to be 8 times the baud rate of the flexray? communication. a second clock f clc_eray is txdb rxdb3 dmax (x= 0,1) address decoder interrupt control eray module (kernel ) rxda1 txda int0src tint0src rxda0 channel a rxda3 rxda2 txena rxdb1 rxdb0 channel b rxdb2 txenb int1src tint1src interrupt select mbsc0src mbsc1src ndat0src ndat1src nd[127:0] mbc[127:0] port 6 control rxda1 txda txena rxdb1 txdb txenb port 0 control rxda0 txda txena rxdb0 txdb txenb external request unit in scu stop watch trigger select stpw pdout0 stpwt0 pdout1 stpwt1 pdout2 stpwt2 pdout3 stpwt3 chx7_regi11 chx6_regi11 chx5_regi11 chx4_regi11 chx3_regi11 chx2_regi11 chx1_regi11 chx0_regi12 chx4_regi13 obusy ibusy chx0_regi11 mt in23 external clock output in scu f mt obusy ibusy clock control f c lc_er ay f sc lk f pll_er ay f fpi www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-264 v1.1, 2011-03 e-ray, v3.12 used for the main protocol controller state machine and the customer interface logic. to enable deactivation of the e-ray module, f clc_eray and f sclk may be disabled (clock gated) by the clc . disr enable e-ray (clock gating) bit.the following items are described in this section: ? e-ray module (kernel) external registers ? port control and connections ? i/o port line assignment ? i/o function selection ? pad driver characteristics selection ? on-chip connections ? scu connections ? dma connections ? module clock generation ? interrupt registers ? e-ray address map 26.9.2 port control and connections this section describes the i/o connections of the e-ray module. 26.9.2.1 input/output function selection table 26-27 shows how bits and bit fields must be programmed for the required i/o functionality of the e-ray i/o lines. this table also shows the values of the peripheral input select registers. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-265 v1.1, 2011-03 e-ray, v3.12 table 26-27 e-ray i/o control selection and setup flexray ? channel port lines input select register input/output control register bits i/o a rxda0/ p0.9 eray_ cust1 . risa =00 b p0_iocr8.pc9 = 0xxx b input rxda1/ p6.12 eray_ cust1 . risa =01 b p6_iocr12.pc12 = 0xxx b input rxda2 eray_ cust1 . risa =10 b input rxda3 eray_ cust1 . risa =11 b input txda/ p0.14 not applicable p0_iocr12.pc14 = 1x01 b output txda/ p6.13 not applicable p6_iocr12.pc13 = 1x10 b output txena / p0.10 not applicable p0_iocr8.pc10 = 1x01 b output txena / p6.10 not applicable p6_iocr8.pc10 = 1x11 b output b rxdb0/ p0.13 eray_ cust1 . risb =00 b p0_iocr12.pc13 = 0xxx b input rxdb1/ p6.14 eray_ cust1 . risb =01 b p6_iocr12.pc14 = 0xxx b input rxdb2 eray_ cust1 . risb =10 b input rxdb3 eray_ cust1 . risb =11 b input txdb/ p0.12 not applicable p0_iocr12.pc12 = 1x01 b output txdb/ p6.15 not applicable p6_iocr12.pc15 = 1x10 b output txenb / p0.11 not applicable p0_iocr8.pc11 = 1x01 b output txenb / p6.11 not applicable p6_iocr8.pc11 = 1x11 b output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-266 v1.1, 2011-03 e-ray, v3.12 26.9.3 on-chip connections this section describes all on-chip interconn ections of the e-ray modules except the connections to i/o ports (see section 26.9.2 ). 26.9.3.1 e-ray connections with dma the e-ray module of the TC1798 has several on-chip interconnections to the dma modules. table 26-28 shows these interconnections. these enable the dma to handle different service request of e-ray module via the dma. table 26-28 dma request assignment for dma sub-block 0 and dma sub-block 1 dma channel eray output signal dma request input line selected by 00 int1src ch00_regi11 chcr00.prsel = 1011 b 00 ibusy ch00_regi12 chcr00.prsel = 1100 b 01 tint0src ch01_regi11 chcr01.prsel = 1011 b 02 ndat1src ch02_regi11 chcr02.prsel = 1011 b 03 mbsc1src ch03_regi11 chcr03.prsel = 1011 b 04 int1src ch04_regi11 chcr04.prsel = 1011 b 04 obusy ch04_regi13 chcr04.prsel = 1101 b 05 tint1src ch05_regi11 chcr05.prsel = 1011 b 06 ndat1src ch06_regi11 chcr06.prsel = 1011 b 07 mbsc1src ch07_regi11 chcr07.prsel = 1011 b 10 int1src ch10_regi11 chcr10.prsel = 1011 b 10 ibusy ch10_regi12 chcr10.prsel = 1100 b 11 tint0src ch11_regi11 chcr11.prsel = 1011 b 12 ndat1src ch12_regi11 chcr12.prsel = 1011 b 13 mbsc1src ch13_regi11 chcr13.prsel = 1011 b 14 int1src ch14_regi11 chcr14.prsel = 1011 b 14 obusy ch14_regi13 chcr14.prsel = 1101 b 15 tint1src ch15_regi11 chcr15.prsel = 1011 b 16 ndat1src ch16_regi11 chcr16.prsel = 1011 b 17 mbsc1src ch17_regi11 chcr17.prsel = 1011 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-267 v1.1, 2011-03 e-ray, v3.12 26.9.3.2 e-ray connections with th e external request unit of scu the e-ray module of the TC1798 has several on-chip interconnections to the external request unit (eru) in the scu to externally trigger stop watch events and to provide a global time e.g. to the on chip timers. table 26-29 and table 26-30 show these interconnections. 26.9.3.3 e-ray connections with the ecc error handling unit of scu the e-ray module of the TC1798 has one on-chip interconnection to the ecc error handling unit in the scu to trigger an ecc error trap. table 26-31 shows this interconnection. 26.9.3.4 e-ray connections with th e external clock output of scu the e-ray module of the TC1798 has one on-chip interconnections to the external clock output unit in the scu to distribute externally as also internally the macro tick as time base for distributed system control e.g. to the gpta ? as global system timer or external devices. table 26-32 shows this interconnection. table 26-29 external stop watch request assignment eray input signal eru reques t output line selected by stpwt0 eru_pdout0 cust1 . stpwts = 00 b stpwt1 eru_pdout1 cust1 . stpwts = 01 b stpwt2 eru_pdout2 cust1 . stpwts = 10 b stpwt3 eru_pdout3 cust1 . stpwts = 11 b table 26-30 global macrotick connection to eru eray output signal eru requ est input line selected by mt eru_in23 eru_eicr1.exis2 = 11 b table 26-31 ecc error signalling to scu eray output signal scu line selected by eerr ecct trapdis.ecct = 0 b table 26-32 global macrotick connection to external clock output eray output signal external clock output selected by mt f mt scu_exctcon.sel0 = 1111 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-268 v1.1, 2011-03 e-ray, v3.12 26.9.4 clock control register the clock control register makes it possible to control (enable/disable) the e-ray module control clock f clc_eray . the clock signal f clc_eray is used by the e-ray as a clock for internal control operations but not for flexray? bus signal sampling. after an application reset, by default, the startup software (ssw) will disable the module by setting clc.disr and thereby requesting the hw to set bit clc.diss. in consequence, the initial value readable by the application is 0x0000 0003 h note: the application sw must make sure that the transceiver enable (txena , txenb ) pins are forced to their inactive state first, before the module clock is switched off. eray_clc eray clock control register (0000 h ) reset value: 0000 0100 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0rmc0 fs oe sb we e dis sp en dis s dis r r rw r rwwrwrwrhrw field bits type description disr 0rw e-ray module disable request bit used for enable/disable control of the e-ray module. note: this bit disables the kernel clocks f clc_eray and the sampling clock f sclk . diss 1rh e-ray module disable status bit bit indicates the current status of the e-ray module. spen 2rw e-ray module suspend enable for ocds used to enable the suspend mode. edis 3rw external request disable used to control the external clock disable request. sbwe 4w e-ray module suspend bit write enable for ocds determines whether spen and fsoe are write-protected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-269 v1.1, 2011-03 e-ray, v3.12 note: after an application reset, the f clc_eray clock is disabled (diss set). therefore, the e-ray modules clock generation is completely disabled. 26.9.5 interrupt registers two different type of interrupt register s are described within this chapter. the interrupt control register enable the selection of the service request used to signal an event. the interrupt control registers ndic1 to ndic4 select the service request node used for new data events.the interrupt control registers msic1 to msic4 select the service request node used for message buffer status changed events. the interrupt service request control registers control the eight service request nodes. fsoe 5rw fast switch off enable used for fast clock switch off in suspend mode. rmc [10:8] rw clock divider in run mode 000 b no clock signal f clc_eray generated (default after reset) 001 b clock f clc_eray = f fpi selected 010 b clock f clc_eray = f fpi /2 selected 011 b clock f clc_eray = f fpi /3 selected 100 b clock f clc_eray = f fpi /4 selected 101 b clock f clc_eray = f fpi /5 selected 110 b clock f clc_eray = f fpi /6 selected 111 b clock f clc_eray = f fpi /7 selected note: this bit field is not affected by an application reset. note: this bit field only controls the kernel clock f clc_eray and not the sampling clock f sclk . 0 [7:6], [31:11] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-270 v1.1, 2011-03 e-ray, v3.12 new data interrupt control 1 (ndic1) this new data interrupt control register controls the interrupt that becomes active (ndat0src or ndat1src) on a nd flag turning active of all configured message buffers 0 to message buffers 31. ndic1 new data interrupt control 1 (03a8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ndip 31 ndip 30 ndip 29 ndip 28 ndip 27 ndip 26 ndip 25 ndip 24 ndip 23 ndip 22 ndip 21 ndip 20 ndip 19 ndip 18 ndip 17 ndip 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 ndip 15 ndip 14 ndip 13 ndip 12 ndip 11 ndip 10 ndip 9 ndip 8 ndip 7 ndip 6 ndip 5 ndip 4 ndip 3 ndip 2 ndip 1 ndip 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description ndipn (n = 0-31) nrw new data interrupt pointer n (n = 0-31) ndipn determines the interrupt (ndat0src or ndat1src) of the service request output that becomes active on a new data flag becoming active. 0 b ndat0src selected for new data service request 1 b ndat1src selected for new data service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-271 v1.1, 2011-03 e-ray, v3.12 new data interrupt control 2 (ndic2) this new data interrupt control register controls the interrupt that becomes active ( ndat0src or ndat1src ) on a nd flag turning active of all configured message buffers 32 to message buffers 63. ndic2 new data interrupt control 2 (03ac h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ndip 63 ndip 62 ndip 61 ndip 60 ndip 59 ndip 58 ndip 57 ndip 56 ndip 55 ndip 54 ndip 53 ndip 52 ndip 51 ndip 50 ndip 49 ndip 48 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 ndip 47 ndip 46 ndip 45 ndip 44 ndip 43 ndip 42 ndip 41 ndip 40 ndip 39 ndip 38 ndip 37 ndip 36 ndip 35 ndip 34 ndip 33 ndip 32 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description ndipn (n = 32-63) n - 32 rw new data interrupt pointer n (n = 32-63) ndipn determines the interrupt (ndat0src or ndat1src) of the service request output that becomes active on a new data flag becoming active. 0 b ndat0src selected for new data service request 1 b ndat1src selected for new data service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-272 v1.1, 2011-03 e-ray, v3.12 new data interrupt control 3 (ndic3) this new data interrupt control register controls the interrupt that becomes active ( ndat0src or ndat1src) on a nd flag turning active of all configured message buffers 64 to message buffers 95. ndic3 new data interrupt control 3 (03b0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ndip 95 ndip 94 ndip 93 ndip 92 ndip 91 ndip 90 ndip 89 ndip 88 ndip 87 ndip 86 ndip 85 ndip 84 ndip 83 ndip 82 ndip 81 ndip 80 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 ndip 79 ndip 78 ndip 77 ndip 76 ndip 75 ndip 74 ndip 73 ndip 72 ndip 71 ndip 70 ndip 69 ndip 68 ndip 67 ndip 66 ndip 65 ndip 64 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description ndipn (n = 64-95) n - 64 rw new data interrupt pointer n (n = 64-95) ndipn determines the interrupt (ndat0src or ndat1src) of the service request output that becomes active on a new data flag becoming active. 0 b ndat0src selected for new data service request 1 b ndat1src selected for new data service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-273 v1.1, 2011-03 e-ray, v3.12 new data interrupt control 4 (ndic4) this new data interrupt control register controls the interrupt that becomes active (ndat0src or ndat1src) on a nd flag turning active of all configured message buffers 96 to message buffers 127. ndic4 new data interrupt control 4 (03b4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ndip 127 ndip 126 ndip 125 ndip 124 ndip 123 ndip 122 ndip 121 ndip 120 ndip 119 ndip 118 ndip 117 ndip 116 ndip 115 ndip 114 ndip 113 ndip 112 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 ndip 111 ndip 110 ndip 109 ndip 108 ndip 107 ndip 106 ndip 105 ndip 104 ndip 103 ndip 102 ndip 101 ndip 100 ndip 99 ndip 98 ndip 97 ndip 96 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description ndipn (n = 96-127) n - 96 rw new data interrupt pointer n (n = 96-127) ndipn determines the interrupt (ndat0src or ndat1src) of the service request output that becomes active on a new data flag becoming active. 0 b ndat0src selected for new data service request 1 b ndat1src selected for new data service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-274 v1.1, 2011-03 e-ray, v3.12 message buffer status change d interrupt control 1 (msic1) this message buffer status change interrupt control register controls the interrupt that becomes active (mbsc0src or mbsc1src) on a mbc flag of all configured message buffer 0 to message buffer 31 turning active. msic1 message buffer status changed interrupt control 1 (03b8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 msip 31 msip 30 msip 29 msip 28 msip 27 msip 26 msip 25 msip 24 msip 23 msip 22 msip 21 msip 20 msip 19 msip 18 msip 17 msip 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 msip 15 msip 14 msip 13 msip 12 msip 11 msip 10 msip 9 msip 8 msip 7 msip 6 msip 5 msip 4 msip 3 msip 2 msip 1 msip 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description msipn (n = 0-31) nrw message buffer status change d interrupt pointer n (n = 0- 31) msipn determines the interrupt (mbsc0src or mbsc1src) of the service request output that becomes active on a message buffer status changed flag becoming active. 0 b mbsc0src selected for me ssage buffer status changed service request 1 b mbsc1src selected for me ssage buffer status changed service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-275 v1.1, 2011-03 e-ray, v3.12 message buffer status change d interrupt control 2 (msic2) this message buffer status change interrupt control register controls the interrupt that becomes active (mbsc0src or mbsc1src) on a mbc flag of all configured message buffer 32 to message buffer 63 turning active. msic2 message buffer status changed interrupt control 2 (03bc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 msip 63 msip 62 msip 61 msip 60 msip 59 msip 58 msip 57 msip 56 msip 55 msip 54 msip 53 msip 52 msip 51 msip 50 msip 49 msip 48 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 msip 47 msip 46 msip 45 msip 44 msip 43 msip 42 msip 41 msip 40 msip 39 msip 38 msip 37 msip 36 msip 35 msip 34 msip 33 msip 32 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description msipn (n = 32-63) n - 32 rh message buffer status chan ged interrupt pointer n (n = 32-63) msipn determines the interrupt (mbsc0src or mbsc1src) of the service request output that becomes active on a message buffer status changed flag becoming active. 0 b mbsc0src selected for message buffer status changed service request 1 b mbsc1src selected for message buffer status changed service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-276 v1.1, 2011-03 e-ray, v3.12 message buffer status change d interrupt control 3 (msic3) this message buffer status change interrupt control register controls the interrupt that becomes active (mbsc0src or mbsc1src) on a mbc flag of all configured message buffer 64 to message buffer 95 turning active. msic3 message buffer status changed interrupt control 3 (03c0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 msip 95 msip 94 msip 93 msip 92 msip 91 msip 90 msip 89 msip 88 msip 87 msip 86 msip 85 msip 84 msip 83 msip 82 msip 81 msip 80 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 msip 79 msip 78 msip 77 msip 76 msip 75 msip 74 msip 73 msip 72 msip 71 msip 70 msip 69 msip 68 msip 67 msip 66 msip 65 msip 64 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description msipn (n = 64-95) n - 64 rw message buffer status chan ged interrupt pointer n (n = 64-95) msipn determines the interrupt (mbsc0src or mbsc1src) of the service request output that becomes active on a message buffer status changed flag becoming active. 0 b mbsc0src selected for message buffer status changed service request 1 b mbsc1src selected for message buffer status changed service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-277 v1.1, 2011-03 e-ray, v3.12 message buffer status change d interrupt control 4 (msic4) this message buffer status change interrupt control register controls the interrupt that becomes active (mbsc0src or mbsc1src) on a mbc flag of all configured message buffer 96 to message buffer 127 turning active. msic4 message buffer status changed interrupt control 4 (03c4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 msip 127 msip 126 msip 125 msip 124 msip 123 msip 122 msip 121 msip 120 msip 119 msip 118 msip 117 msip 116 msip 115 msip 114 msip 113 msip 112 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 msip 111 msip 110 msip 109 msip 108 msip 107 msip 106 msip 105 msip 104 msip 103 msip 102 msip 101 msip 100 msip 99 msip 98 msip 97 msip 96 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description msipn (n = 96-127) n - 96 rw message buffer status changed interrupt pointer n (n = 96-127) msipn determines the interrupt (mbsc0src or mbsc1src) of the service request output that becomes active on a message buffer status changed flag becoming active. 0 b mbsc0src selected for message buffer status changed service request 1 b mbsc1src selected for message buffer status changed service request www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-278 v1.1, 2011-03 e-ray, v3.12 service request control registers each of the service request outputs of the e-ray module kernels is able to generate an interrupt and is controlled by an interrupt service request control register int0src, int1src, tint0src, tint1src, ndat0src, ndat1src, mbsc0src, mbsc1src, obusysrc, and ibusysrc.the service request obusysrc, and ibusysrc is generated, when the output bu ffer or input buffer switches from busy state to the state being accessible by the host. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-279 v1.1, 2011-03 e-ray, v3.12 int0src interrupt 0 service request control register (3ec h ) reset value: 0000 0000 h int1src interrupt 1 service request control register (3e8 h ) reset value: 0000 0000 h tint0src timer interrupt 0 service request control register (3e4 h ) reset value: 0000 0000 h tint1src timer interrupt 1 service request control register (3e0 h ) reset value: 0000 0000 h ndat0src new data 0 service request control register (3dc h ) reset value: 0000 0000 h ndat1src new data 1 service request control register (3d8 h ) reset value: 0000 0000 h mbsc0src message buffer status changed 0 service request control register (3d4 h ) reset value: 0000 0000 h mbsc1src message buffer status changed 1 service request control register (3d0 h ) reset value: 0000 0000 h obusysrc output buffer busy service request control register (3cc h ) reset value: 0000 0000 h ibusysrc input buffer busy service request control register (3c8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 flexray? protocol controller (e-ray) users manual 26-280 v1.1, 2011-03 e-ray, v3.12 note: additional details on service reques t nodes and the service request control registers are described in chapter ?int errupt system? of the TC1798 users manual system units part (volume 1). field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-1 v1.1, 2011-03 mli, v1.11 27 micro link interface (mli) this chapter describes the micro link interface module and the mli protocol. it contains the following sections: ? functional description of the mli (see page 27-2 ) ? module kernel description (see page 27-27 ) ? operation the mli module (see page 27-69 ) ? mli kernel register descriptions (see page 27-77 ) ? device implementation-specific descriptions and details (see page 27-127 ) note: the mli kernel register names described in section 27.3 are referenced in the TC1798 users manual by the module name prefix ?mli0_? for the mli0 interface and ?mli1_? for the mli1 interface. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-2 v1.1, 2011-03 mli, v1.11 27.1 functional description this chapter describes the functionality of the mli interface. ? a general introduction to the interface (see page 27-2 ) ? the mli frame structure for data exchange (see page 27-10 ) 27.1.1 general introduction the introduction comprises: ? an overview about the mli (see page 27-2 ) ? naming conventions (see page 27-4 ) ? a description of the mli communication principles (see page 27-6 ) 27.1.1.1 mli overview the micro link interface (mli) is a fast sy nchronous serial interface to exchange data between microcontrollers or other devices, such as stand-alone peripheral components. figure 27-1 shows how two microcontrollers are typically connected together via their mli interfaces. figure 27-1 typical micro li nk interface connection mca05869 controller 1 cpu peripheral b peripheral a mli system bus controller 2 cpu peripheral d peripheral c mli system bus memory memory www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-3 v1.1, 2011-03 mli, v1.11 features ? synchronous serial communication between an mli transmitter and an mli receiver ? different system clock speeds supported in mli transmitter and mli receiver due to full handshake protocol (4 lines between a transmitter and a receiver) ? fully transparent read/write acce ss supported (= remote programming) ? complete address range of target device available ? specific frame protocol to transfer commands, addresses and data ? error detection by parity bit ? 32-bit, 16-bit, or 8-bit data transfers supported ? programmable baud rates ? mli transmitter baud rate: max. f mli /2 ? mli receiver baud rate: max. f mli ? address range protection scheme to block unauthorized accesses ? multiple receiving devices supported www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-4 v1.1, 2011-03 mli, v1.11 27.1.1.2 naming conventions local and remote controller the terms ?local? and ?remote? controller are assigned to the two partners (microcontrollers or other devices with mli modules) of a serial mli connection. the controller with an mli module initiating a data exchange or a control task is defined as local controller. each data exchange and control task starts with a frame transmission of the local controller. the controller wi th an mli module reacting on received data exchange requests or executing control ta sks is defined as remote controller. the terms ?local? and ?remote? are independent of the direction of the information flow (transmission or reception), except for read frames (always transmitted by the local controller) and answer frames (always transmitted by the remote controller). a triggered command frame is transferred from the local to the remote controller. due to the full duplex operation capability of an mli module (independent transmitter and receiver), each microcontroller with an mli module is able to operate as a local controller (e.g. for data transmission) as well as a remote cont roller (e.g. for data reception) at the same time. transmitting and receiving controller the terms ?transmitting? and ?receiving? controller are referring to the direction of the information flow. these terms are independent from the terms ?local? and ?remote?. for example, the initialization of a bidirectional mli connection between two controllers (or between a controller and a stand-alone device) is always controlled and initiated by one controller (named local), although during this phase, both mli participants can transmit and receive frames. due to the full duplex operation capability of the mli module (independent transmitter and receiver), each microcontroller with an mli module is able to operate as a transmitting controller as well as a receiving controller at the same time. transfer window a transfer window is an address space in the address map of the transmitting controller. transfer windows are typically assigned to a fixed address space (base address and size). the transfer windows are the logical data inputs for the mli transmitter. data write actions via mli are initiated by a writ e access to a transfer window, whereas data read actions are started by a r ead access from a transfer window. each mli module supports up to four independent transfer windows, one for each pipe. in the implementation of a specific device, a transfer window can appear at several locations in the address map. here, each transfer window can be accessed at two different address ranges with two different window sizes (one 64 kbyte and one 8 kbyte area for each transfer window), leading to: ? four small transfer windows stw with 8 kbyte address range each and www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-5 v1.1, 2011-03 mli, v1.11 ? four large transfer windows ltw with 64 kbyte address range each remote window a remote window is an area in the address space of the receiving controller. remote window parameters (base address and size) of the receiving controller are programmable by the transmitting microcon troller by mli transfers, independently for each pipe. each remote window of a receiving controller is related to specific transfer window of the transmitting controller. the remote windows are the logical data outputs of the mli receiver. if enabled, the mli module can automatically execute the requested data transfer to/from the defined address location in the remote window. if the automatic data handling is disabled, the offset and the data are available in the mli receiver registers and have to be handled by software. remote windows can not be accessed by read or write accesses by software of the remote controller (either the data is automatically transferred or it is located in receiver registers). pipe a pipe defines the logical connection between a transfer window in the transmitting controller and the associated remote window in the receiving controller. the mli protocol supports four independent pipes. frame a frame is a contiguous set of bits forming a message sent by an mli transmitter to an mli receiver. a normal frame is a frame used for data exchange between a transmitting and a receiving controller (read request and write data from a local controller to a remote controller, as well as the answer to a read request back to the local controller). base address copy frames are also considered as normal frames. a command frame contains information about the receiver setting or triggers actions in the mli receiver. a triggered command frame is generated under hardware control and can be used to transfer interrupt or service r equests between the mli participants. offset the offset is an address distance relative to the base address of the transfer window in the transmitting controller and the base address of the remote window in the receiving controller. for example, a write access to the 10th byte of the transfer window is transferred to a write to the 10th byte of the remote window. the offset of a write access to a transfer window is also called write offset, whereas a read offset is related to a read access from a transfer window. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-6 v1.1, 2011-03 mli, v1.11 27.1.1.3 mli communi cation principles the communication principle of the mli modules allows data to be transferred between a local and a remote controller without intervention of a cpu in the remote controller. data transfers are always triggered in the local controller by read or write operations to an address location in a transfer window. all control tasks, address and data transmissions that are required for the data transfer/request between local and remote controller can be handled autonomously by the two connected mli modules. figure 27-2 mli communication principles write access to a transfer window a write access to a location within a transfer window of the transmitting (local) controller is detected by the mli transmitter. this detection initiates a transfer of the data that has been written to the transfer window t ogether with the write offset to the mli of the receiving controller. the receiving controller stores the data internally and can also automatically place the data in the remote window of the receiving controller (at the address location defined by the write offset plus the base address). read access from a transfer window a read access from a location of a transfer window in the local controller is detected by the mli transmitter and delivers dummy data. this detection initiates a transfer of the read offset from the local microcontroller to the mli receiver to request data from the remote controller. this data can be automatically read or prepared by a cpu in the remote controller. when the requested data is available in the remote controller, it is mca06286_mod transmitter mli module local controller remote controller receiver address space transfer window write read receiver mli module transmitter complete address space remote window interrupt 1) 2) 1) transmission of write data (and optinally write offset) or read offset 2) transmission of read data www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-7 v1.1, 2011-03 mli, v1.11 introduced into the data stream back to the local controller (answer frame). then, the cpu in the local controller is informed by an mli event that the requested data is now available and can be read. transfer window organization figure 27-3 shows an example of the organization of transfer windows and remote windows with a possible assignment in local and remote controller. each of the four pipes assigns one transfer window to one remote window with its base address and window size. for reasons of simplicity, a pi pe to a remote window is only shown either from a ltw or from a stw, although each transfer window can be accessed at both address locations, its ltw and its stw. figure 27-3 transfer/remote window assignment example during initialization of the pipes, base addresses and sizes of the remote windows are transmitted from the local controller to the remote controller. in the example of figure 27-3 , pipe 1 and pipe 2 cover the full range of their transfer and remote mca06287_mod local controller address map large transfer window 1 small transfer window 0 large transfer window 0 large transfer window 2 large transfer window 3 small transfer window 1 small transfer window 2 small transfer window 3 large transfer windows (ltw) small transfer windows (stw) remote controller address map remote window 2 remote window 0 remote window 1 remote window 3 pipe 0 pipe 2 pipe 1 pipe 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-8 v1.1, 2011-03 mli, v1.11 windows. the ranges of the remote windows of pipe 0 and pipe 3 are sub-ranges of the related transfer windows. the location of a transfer window (base address and size) in the local controller is always fixed in a specific product device. remote windows can be freely moved and located within the address space of the rece iving controller. they are used to overlay address ranges of peripheral modules or internal memories. remote window address generation figure 27-4 shows the generation of the remote window address ranges, with fixed base address part and additional variable address part. the variable address part is determined by the available address area for each remote window (also named buffer size, value of bsx = buffer size for remote window x in dicates how many address bits are variable, defining the available address range). figure 27-4 base address definition of remote windows mli_rwindow_bac base adresses of the four pipes base addr 0 ?.. 00 bs0-1 31 0 pipe 0 buffer area 0 remote window 0 size = 2 bs0 mli receiver base addr 1 ?.. 00 bs1-1 31 0 pipe 1 buffer area 1 remote window 1 size = 2 bs1 base addr 2 ?.. 00 bs2-1 31 0 pipe 2 buffer area 2 remote window 2 size = 2 bs2 base addr 3 ?.. 00 bs3-1 31 0 pipe 3 buffer area 3 remote window 3 size = 2 bs3 mli transmitter www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-9 v1.1, 2011-03 mli, v1.11 figure 27-5 shows the generation of the complete remote window address without address prediction. the variable address part can be transferred as offset by a write or a read frame, or it can be predicted in case of regular address modifications, whereas the fixed part of the address is defined by the upper bits of the base address. in case of address prediction, the variable address part is internally calculated and taken as lower address bits of the target addre ss (the upper address bits are given by the remote window?s base address). figure 27-5 remote window address ge neration without address prediction figure 27-6 remote window address ge neration with ad dress prediction mli_rwindow _offs transfer window pipe x base address x ?.. 00 bsx 31 0 remote window pipe x bsx-1 0 mli transmitter base address x offset bsx 31 0 offset offset mli receiver 1) read or write offset 1) mli_rwindow_pred transfer window pipe x base address x ?.. 00 bsx 31 0 remote window pipe x mli transmitter base address x offset bsx 31 0 mli receiver 1) read or write offset 1) address prediction current offset predicted offset address prediction match www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-10 v1.1, 2011-03 mli, v1.11 27.1.2 mli frame structure a frame is a message sent by an mli transmitter to an mli receiver. depending on the desired behavior, different frame types exist: ? copy base address frame to define location and size of a remote window (see page 27-12 ) ? write offset and data frame to transmit the write offset and the write data (see page 27-13 ) ? optimized write frame to transmit write data without write offset in case of an address prediction match (see page 27-14 ) ? discrete read frame to transmit read request with the read offset (see page 27-15 ) ? optimized read frame to transmit the read request without read offset in case of an address prediction match (see page 27-16 ) ? command frame to transmit a command, e.g. setup information or mli service request generation (see page 27-17 ) ? answer frame to transmit the data pr eviously requested by a read frame (see page 27-18 ) the local/remote structure of an mli connection between two microcontrollers requires a transmitter unit and a receiver unit in both mli modules (local and remote) for communication. figure 27-7 logic frame assignment to local/remote controller mca06292 copy base address frame transmitter receiver mli module local controller write offset and data frame discrete read frame command frame optimized write frame optimized read frame answer frame receiver transmitter mli module remote controller www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-11 v1.1, 2011-03 mli, v1.11 27.1.2.1 genera l frame layout the general layout of a frame is shown in figure 27-8 . it contains the following parts: ? a frame starts with a 4-bit header field t hat contains a 2-bit frame code (fc) and a 2- bit pipe number (pn). ? the data field can contain address, data, or control information. the width of the data field depends on the frame type. ? the frame is terminated by a parity bit (p) with even parity (see page 27-26 ), calculated over header and data field bits. figure 27-8 general frame layout the frame code (fc) determines the frame type of the transmitted frame. the pipe number (pn) indicates the pipe that is related to the frame content (the value of pn is defined as 00 b for pipe 0, 01 b for pipe 1, 10 b for pipe 2, and 11 b for pipe 3). the fc parameter is coded according to table 27-1 . if more than one frame type is defined with the same frame code value (see fc = 01 h , 10 h or 11 h ), the width of the received frame defines the type. the value given by m in the table below represents the number of address bits transferred as offset (defined by the buffer size bsx of the remote window x). table 27-1 frame code definition frame code fc frame type data field width [bits] description see 00 b copy base address frame 32 page 27-12 01 b write offset and data frame 8+m, 16+m, or 32+m page 27-13 discrete read frame 2+m page 27-15 10 b command frame 4 page 27-17 answer frame 8, 16, or 32 page 27-18 11 b optimized write frame 8, 16, or 32 page 27-14 optimized read frame 2 page 27-16 mca06293 fc = frame code pn = pipe number p = parity fc pn p header data field www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-12 v1.1, 2011-03 mli, v1.11 27.1.2.2 copy base address frame with a copy base address frame, the two parameters of a remote window are transferred from the transmitting controller to the receiving controller to initialize or to redirect the remote window. the copy base address frame contains the following parts: ? header: the header starts with frame code fc = 00 b followed by the pipe number pn of the pipe targeted by the transmitted base address bits and the size code. ? remote window address location: the 28 most significant bits of the 32- bit base address bits can be programmed by the transmitting controller (the 4 lsbs are considered as 0). the base address of a remote window has to be aligned to its size, e.g. a window of 1 kbyte has to start at 1kbyte address boundaries. ? remote window size: the size is defined by the 4-bit coded buffer size bs. the maximum size is 64 kbytes. ?parity bit p figure 27-9 copy base address frame more details about the copy base address frame handling of the mli module are described on page 27-28 . table 27-2 bs coding buffer size code bs remote window size (also named buffer size) number m of offset bits 0000 b 2 bytes m = 1 0001 b 4 bytes m = 2 ... ... ... 1110 b 32 kbytes m = 15 1111 b 64 kbytes m = 16 mca06294_mod p base address (28-bit) 0 02 4 bs 32 36 3 1 31 35 0 header pn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-13 v1.1, 2011-03 mli, v1.11 27.1.2.3 write offset and data frame a write offset and data frame is used by th e transmitting controller to send an address offset and data to the receiving controller. th is frame is initiated by a write operation to one of the transfer windows in the transmitting controller. the write offset and data frame contains the following parts: ? header: the header starts with frame code fc = 01 b followed by the pipe number pn of the transfer window that has been the target of the write operation. ? m-bits of write offset: these bits define the write offset. the value of m depends on the size of the remote window, defined by the copy base address frame (m = 1-16). ? write data field: the write data field can be 8-bit, 16-bit, or 32-bit wide, depending on the data width of the write access to the transfer window. ?parity bit p figure 27-10 write offs et and data frame more details about the write offset and data frame handling of the mli module are provided on page 27-30 . mca06295_mod p 8-bit data 0 0 2 12+m 3 1 1 p 16-bit data 0 023 1 1 p 32-bit data 0 023 1 1 4 header header header m-bit offset address 4 m-bit offset address 4 m-bit offset address 20+m 36+m pn pn pn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-14 v1.1, 2011-03 mli, v1.11 27.1.2.4 optimized write frame an optimized write frame is used by the transmitting controller to send 8-bit, 16-bit, or 32-bit wide data to the receiving controller. this frame is initiated by a write operation to one of the transfer windows in the transmitting controller. in contrast to a write offset and data frame, no write offset is transmitted because the offset address for the write data can be predicted and calculated by th e receiving controller. an optimized write frame allows a higher data bandwidth than wr ite offset and data frames, because they are shorter. an optimized frame is only po ssible if the predicted address matches with the actually written one. the optimized write frame contains the following parts: ? header: the header starts with frame code fc = 11 b followed by the pipe number pn of the transfer window that has been the target of the write operation. ? write data field: the write data field can be 8-bit, 16-bit, or 32-bit wide, depending on the data width of the write access to the transfer window. ?parity bit p figure 27-11 optimized write frame more details about the optimized write fram e handling of the mli module are provided on page 27-30 . mca06299_mod p 8-bit data 1 02 4 12 3 1 1 11 p 16-bit data 1 02 4 20 3 1 1 p 32-bit data 1 02 4 36 3 1 1 19 35 header header header pn pn pn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-15 v1.1, 2011-03 mli, v1.11 27.1.2.5 discrete read frame a discrete read frame is used by the local controller to request data to be read from the remote window in the remote controller. if the data is available, the remote controller typically responds to this request by sending an answer frame with the requested read data back to the local controller. the discrete read frame contains the following parts: ? header: the header starts with frame code fc = 01 b followed by the pipe number pn of the transfer window that has been the target of the read operation. ? m-bits of write offset: these bits define the read offset. the value of m depends on the size of the remote window, defined by the copy base address frame (m = 1-16). ? data width dw: the data width dw indicates if the read from the transfer window was a 8-bit, 16- bit, or 32-bit read action. it defines how many bytes have to be delivered to the local controller by the answer frame. ?parity bit p figure 27-12 discrete read frame more details about the discrete read frame handling of the mli module are provided on page 27-34 . table 27-3 data width dw coding data width dw number of data bits to be transferred 00 b 8-bit read access 01 b 16-bit read access 10 b 32-bit read access 11 b reserved for future use mca06296_mod p dw 0 02 6+m 3 1 1 m-bit offset address 4 header pn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-16 v1.1, 2011-03 mli, v1.11 27.1.2.6 optimized read frame an optimized read frame is used by the local controller to request 8-bit, 16-bit, or 32- bit wide data from the remote controller without sending any offset address. the address for the requested data can be predicted and calculated by the mli receiver of the remote controller. the optimized read frame contains the following parts: ? header: the header starts with frame code fc = 11 b followed by the pipe number pn of the transfer window that has been the target of the read operation. ? data width dw: the data width dw indicates if the read from the transfer window was a 8-bit, 16- bit, or 32-bit read action. it defines how many bytes have to be delivered to the local controller by the answer frame. same coding as for the discrete read frame. ?parity bit p figure 27-13 optimized read frame more details about the optimized read frame handling of the mli module are provided on page 27-30 . mca06300_mod 1 02 dw 46 3 15 1 dw = data width header pn p www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-17 v1.1, 2011-03 mli, v1.11 27.1.2.7 command frame the transmitting controller is able to initiate control actions to be executed by the receiving controller by sending a command frame. the command frame contains the following parts: ? header: the header starts with frame code fc = 10 b followed by the pipe number pn. the pipe number defines the type of command to be executed. ? command code cmd: pipe number pn and a 4-bit cmd field are used for command coding. the command coding of some control actions is fixed, but free programmable software commands can also be defined (with pn = 11 b ). the coding of the command bit field is pipe- specific and depends on the transmitted pipe number x. ?parity bit p figure 27-14 command frame more details about the command frame handl ing of the mli module are provided on page 27-41 . table 27-4 pn for command coding pipe number pn command type 00 b activate mli service request or other control signal(s) of the receiving controller. the definition which signal becomes activated is defined by cmd. the usage of these lines depends on the implementation. 01 b define delay for parity error indica tion in the receiving controller. the delay in rclk cycles is defined by the value of cmd. 10 b control of internal functions of the receiving controller. the value of cmd indicates which function is controlled. the coding of cmd and the control mechanisms depend on the implementation. 11 b freely programmable software command. mca06297_mod p 1 02 cmd 48 3 1 7 0 cmd = command code header pn www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-18 v1.1, 2011-03 mli, v1.11 27.1.2.8 answer frame an answer frame is used by the remote contro ller to send 8-bit, 16-bit, or 32-bit wide data to the local controller. the answer frame is the only frame that is transmitted within a logic local/remote controller assignment from the remote controller to the local controller. it is the answer to a discr ete read frame or an optimized read frame that has been sent by the local controller to request data from the remote controller. the answer frame contains the following parts: ? header: the header starts with frame code fc = 10 b followed by the pipe number pn. the value of pn is taken from the read frame that has triggered the answer frame. ? read data field: the read data field can be 8-bit, 16-bit, or 32-bit wide, depending on the data width requested by the read frame that triggered the answer frame. ?parity bit p figure 27-15 answer frame more details about the answer frame handling of the mli module are provided on page 27-39 . mca06298_mod pn p 8-bit data 1 02 12 3 1 0 pn p 16-bit data 1 02 20 3 1 0 pn p 32-bit data 1 02 37 3 1 0 4 4 4 header header header 11 19 36 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-19 v1.1, 2011-03 mli, v1.11 27.1.3 handshake description the description of the transmitter/receiver signal handshaking refers to an mli connection between an mli transmitter and an mli receiver. mli module transmitter i/o signals are indicated with prefix ?t? and mli receiver i/o signals are indicated with the prefix ?r?. the 4-line mli bus between a transmitter and a receiver outside the controllers uses signal names without any prefix. in order to lay emphasis where a signal is generated or sampled, actions taken by the transmitter are described referring to signals with the prefix ?t?, whereas receiver actions are referring to signals with the prefix ?r?. figure 27-16 transmitter/receiver signal definitions the mli connection allows high data rates and, at the same time, supports significant signal propagation delays between the transmitter and the receiver. as shown in figure 27-16 , each output signal passes through the port stage, reaches the physical interface line between the mli modules, enters via an input stage and can be finally evaluated. all these steps introduce an accumulating propagation delay. in standard synchronous serial connections (such as spi) , this delay limits the reachable baud rate to a few mbit/s (closed-loop delay problem). in order to support higher baud rates than a standard spi, the mli protocol is based on a full handshake (ready-valid) to deal with propagation delays in the range of some shift clock cycles and to avoid the closed- loop delay limitations of an spi connection. controller 2 mca06288_mod mli transmitter tclk tready tvalid tdata port control controller 1 mli receiver port control rclk rready rvalid rdata clk ready valid data mli receiver port control mli transmitter port control clk ready valid data rclk rready rvalid rdata tclk tready tvalid tdata f fpi controller 1 f fpi controller 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-20 v1.1, 2011-03 mli, v1.11 in a full handshake, each edge of the handshake signals has a defined meaning and the sequence of edges is clearly specified. as a result, the propagation delays do not directly limit the mli baud rate. therefore, the points in time when a signal is generated, when it is visible on the physical interface line, or when it is evaluated have to be considered independently. this is done by defining 3 different names for a signal, referring to the 3 significant locations: ? the place where it is generated, also in relation to the generation clock edge ? the physical interface line where it can be observed ? the place where it is evaluated, also in relation to the evaluation clock edge if a local controller should be connected to more than one remote controller, the transmitter signals clk and data can be used as broadcast signals (parallel connection to the remote controllers), whereas the handshake signals valid and ready have to be established as independent signal pairs for each device. as a result, a local controller only needs one clk and one data output, but an individual set of ready and valid handshake signals for each remote controller. please note that read frames and answer frames are based on an established connection between a local and a remote controller (because the answer frame is the only frame sent back to the local controller). therefore, switching between several remote controllers can only be done while no read request is pending in the local controller. if no read frames are used by the local controller, frames can be sent out in parallel to all remote controllers if their ready signals are all respected. if a remote controller should be connected to several local controllers, it may have several data and clk inputs in addition to the ready-valid signal sets. please note that an active switching of a remote controller between several local controllers requires that all local controllers have the information which connection is active. in any case, switching between local and remote controllers is not allowed while frame transmission is in progress. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-21 v1.1, 2011-03 mli, v1.11 27.1.3.1 handshake signals the synchronous serial frame transfer from an mli transmitter to an mli receiver is based on the following 4 signals (the mli protocol only defines the signal transitions, but neither the signaling level nor the driver characteristics): ? shift clock clk: this signal is used as serial shift clock th at is generated by the transmitter during the complete frame transfer (tvalid is active) and until the end of ready delay time. signal tclk can also be generated while no frame is transferred. in this case, the receiving controller can use the incoming rclk receiver signal as base for its internal clock generation. the transmitter signals are always referring to the rising edge of tclk, so tready is sampled and the output signals tdata and tvalid are changing with the rising edge of tclk. the mli receiver actions refer to the falling edges of its rclk input. the receiver samples the rvalid and rdata signals and outputs its rready line with the falling edges of rclk. ? shift data data: this signal represents the transmit data tdata transferred from the mli transmitter to the mli receiver input rdata. changes on transmitter side take place with rising edges of tclk, whereas sampling on the receiver side takes place with falling edges of rclk. ? transmitter valid handshake valid: this signal indicates the start and the end of each frame. it is active (1-level) during a frame transmission and passive (0-level) while no frame is transferred. changes of tvalid on transmitter side take place with rising edges of tclk, whereas sampling of rvalid on the receiver side takes place with falling edges of rclk. an activation of tvalid to start a new frame can only take place if tready is 1. ? receiver ready handshake ready: this signal indicates that the receiver is ready for a data transfer. additionally, this line is used to indicate reception errors (parity error indication). changes of rready on receiver side take place with falling edges of rclk, whereas sampling of tready on the transmitter side takes place with rising edges of tclk. 27.1.3.2 error-free handshake a transmission can be started by an mli transmitter when the mli receiver is ready to receive data indicated by rready = 1 by the receiver. when the mli transmitter detects tready = 1 and starts its transmission , tvalid is asserted to 1 level while a frame transfer is in progress. when the mli receiver has detected the 0-to-1 transition of the rvalid signal it will de-assert rready back to 0 (transmission start acknowledged by receiver). at the end of the frame transmission, the mli transmitter also de-asserts signal tvalid back to 0 and checks if the tready signal is at 0 level, www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-22 v1.1, 2011-03 mli, v1.11 too. this check is used as life-sign of the receiver and the mli transmitter can detect whether the receiver is able to react in-time to the transmitter actions (see also page 27-23 ). figure 27-17 mli handshake without error indication 27.1.3.3 ready delay time in order to support significant propagation delays, the handshake signal tready is evaluated with respect to tvalid and tclk in an time interval called ready delay time after the end of the frame (see figure 27-17 ). the length of the ready delay time is programmable, defining the size of the time interval. when a transmission is finished (rvalid becomes 0), the mli receiver checks the received frame for correct reception (parity error). if no parity error has been detected, the mli receiver asserts its rready signal again to 1 to indicate the correct reception with the next falling edge of rclk. the mli transmit ter checks its tr eady input with each rising edge of tclk after tvalid has become 0 and increments a counter. this counter is started from 0 at the end of a frame transmission (tvalid becomes 0) and counts tclk periods (ready delay time counter). if the condition tready = 1 is detected before the programmed ready delay time has elapsed, the mli receiver has indicated a frame reception without parity error to the mli transmitter. in this case, a new frame transmission can be started. the tran sfer handshake signalling without a parity error indication is shown in figure 27-17 . figure 27-18 shows the transfer handshake if a parity error condition has been detected by the mli receiver and indicated to the mli transmitter. in this case, the receiver waits a programmable number of rclk clock cycles before setting rrea dy to 1. if the tready = 1 condition is detected by the transmitter after the ready delay has elapsed, a parity error has been indicated by the mli receiver. in this case, it is assumed that the mli receiver has detected a frame with a parity error and has discarded the frame. the mct06289_mod tvalid tdata tready tclk ready delay time fc p www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-23 v1.1, 2011-03 mli, v1.11 transmitter automatically sends the last frame again after a parity error indication. optionally, this mli event can activate a service request output. figure 27-18 mli handshake with parity error indication 27.1.3.4 non-acknowledge error a transmitter of an mli module is able to detect an inoperable receiver by analyzing the handshake signal tready. after tvalid has been asserted to 1, the transmitter checks the receiver?s acknowledge (tread y becoming 0). a non-acknowledge error condition is detected by the transmitter when at the end of a frame transmission the tready signal is still at high level (tready = 1 when tvalid becomes 0). figure 27-19 shows the non-acknowledge error case. in this case, the transmitter automatically sends the last frame again. optionally, this mli event can activate a service request output. figure 27-19 non-acknowledge error mct06290_mod tvalid tdata tready tclk ready delay time fc p mct06291_mod tvalid tready tclk non-acknowledge error www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-24 v1.1, 2011-03 mli, v1.11 27.1.3.5 signal timing figure 27-20 shows the mli timing requirements. figure 27-20 signal timing t 27 t 25 t 26 t 16 t 17 t 15 t 15 mli_tmg_2.vsd tdatax tvalidx tclkx rdatax rvalidx rclkx treadyx rreadyx t 10 t 13 t 11 t 12 t 14 t 20 t 27 mli transmitter timing mli receiver timing t 23 t 21 t 22 t 24 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-25 v1.1, 2011-03 mli, v1.11 the transmitter output signals tdata and tvalidx might have a certain delay to the transmitter clock output tclk due to on-chip variation of the driver stages and differences in the propagation delays. the transmitter tready input can change at any point in time compared to tclk. in order to ensure stability, it is internally synchronized to f mli of the transmitter before being evaluated with the rising tclk edge when tvalid becomes 0. for the calculation of the signa l propagation time, these 2 clock cycles have to be taken into account. the transmitter input treadyx has to be stable a certain time before tvalid becomes low, referring to the rising edge of tclk when tvalid becomes low. if at this point in time, treadyx is detected at a high level, a non-acknowledge error is signaled. the same timing relation has to be considered at the end of the ready delay time for the parity error detection. the receiver input signals are handled asynchronously based on the rclk signal. the synchronization to the receiver?s system clock f fpi is done i n the receiver logic. the input signals rdata and rvalid have to respect a certain setup and hold time at the falling edge of rclk. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-26 v1.1, 2011-03 mli, v1.11 27.1.4 parity generation for parity generation, the number of transmitted bits with the value of 1 is counted over the header and the complete data field of a frame. for even parity, the parity bit is set if the result of a modulo-2 division of the elaborated number is 1. for error-free mli traffic, even parity generation and checking is defined. more details about the parity handling of the mli module are provided on page 27-44 . 27.1.5 address prediction an address prediction method can be enabled to support communication between mli transmitter and mli receiver without sending address offset information in the frames. this feature reduces the required bandwidth for mli communication. both of the communication partners, mli transmitter and receiver are able to detect regular offset differences of consecutive window accesses to the same window. the address prediction mechanism working independently for each pipe, different prediction values can be handled in parallel for the different pipes. the mli transmitter can compare the offset of each transfer window read or write access with the offset of the previous access to the same transfer window. between the accesses to a specific window, other windows can be accessed without disturbing the prediction. bigger offset differences than 512 bytes are not supported by the address prediction. if the offset differences are identical in at least two accesses to the same transfer window, an address prediction is possible an d optimized write frames or optimized read frames can be sent to the receiving cont roller for this pipe. if the offset difference of a next access to this transfer window does not match the former ones (predicted offset), address prediction is not possible. in this case, a normal frame for writing or reading (write offset and data frame or discrete read frame) is started. the identical address prediction mechanism is built in the receiver. as a result, the receiver can elaborate the original offset value in the transmitter when receiving an optimized frame for any pipe. more details about the address prediction mechanism of the mli module are provided on page 27-47 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-27 v1.1, 2011-03 mli, v1.11 27.2 module kernel description this chapter describes how the mli protocol is implemented in the mli module and how frame handling can be done by software, comprising: ? the frame handling (see page 27-27 ) ? the general mli features (see page 27-44 ) ? the interface signals (see page 27-51 ) ? the general mli service request structure (see page 27-57 ) ? the mli transmitter events (see page 27-59 ) ? the mli receiver events (see page 27-62 ) ? the baud rate generation (see page 27-67 ) 27.2.1 frame handling the frame handling is based on receiver and transmitter registers and the transfer windows. depending on the type of access to the transfer windows, different actions take place inside the mli module. please refer to the following pages for the handling of: ? copy base address frame (see page 27-28 ) ? data frames (see page 27-30 ) ? read frames (see page 27-34 ) ? answer frame (see page 27-39 ) ? command frame (see page 27-41 ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-28 v1.1, 2011-03 mli, v1.11 27.2.1.1 copy base address frame a copy base address frame defines the location and the size of a remote window. figure 27-21 copy base address frame flow transmitting controller the transmission of a copy base address frame is started after a transmitter pipe x base address registers tpxbar has been written, triggering the following actions for pipe x. ? bit field tpxbar.bs (4-bit coded buffer size) is loaded into bit field tpxstatr.bs ? bit field tpxbar.addr (28 most significant base address bits) is loaded into bit field tcbar.addr. mca06303_mod transmitting mli controller receiving mli controller mli transmitter ready tpxbar is written tpxstatr.bs := tpxbar.bs tcbar.addr := tpxbar.addr trstatr.pn := x trstatr.bav := 1 send "copy base address frame" of pipe x rpxbar.addr := base address (28-bit) rpxstatr.bs := buffer size (4-bit) rcr.tf := 00 b risr.nfri := 1 mli receiver ready tready = 1 remote window of pipe x is initialized and ready to read/write data trstatr.bav := 0 tisr.nfsix := 1 normal frame sent x event normal frame received event parity check & acknowledge frame www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-29 v1.1, 2011-03 mli, v1.11 ? status bit field trstatr.pn is updated with the pipe number x (for example x = 2 when tp2bar has been written). ? status flag trstatr.bav (base address valid) becomes set. ? the transmission of a copy base address frame with the two buffered parameters tcbar.addr and tpxstatr.bs is started for pipe x (if the corresponding pipe is idle and tready = 1). ? status flag trstatr.bav (in th e transmitting controller) is cleared after the copy base address frame has been finished and correctly acknowledged by the mli receiver of the re ceiving co ntroller. ? mli event status flag tisr.nfsix (normal frame sent event in pipe x) is set and a service request output is activated if enabled by tier.nfsiex = 1. note: after the transfer of a copy base address frame the optimized mode will be suppressed automatically by hardware for the next two data frames. this ensures a correct offset prediction afterwards. receiving controller when a copy base address frame for pipe x has been received correctly and acknowledged, the following actions are executed in the mli receiver. ? the received 28 most significant address bits are written into the receiver pipe x base address register bit field rpxbar.addr. this bit field determines the base address of the pipe x remote window. ? the received 4-bit coded buffer size is stored in the receiver pipe x status register bit field rpxstatr.bs. this bit field determines the number of variable address bits for the offset (determining the size) of the pipe x remote window. ? the information about the received frame type (= 00 b for copy base address frame) is written into the receiver c ontrol register bit field rcr.tf. ? mli event status flag risr.nfri (normal frame received event) is set and a service request output is activated if enabled by rier.nfrie = 01 b or 10 b . figure 27-22 copy base address frame mca0629 4 x p base address (28-bit) 0 024 bs 32 3 6 tcbar.addr tpxstatr.bs 3 1 31 35 0 header x = pipe number www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-30 v1.1, 2011-03 mli, v1.11 27.2.1.2 write/data frames write frames (also named data frames) transm it the write data and optionally the write offset. figure 27-23 write frame flow mca06305_mod mli transmitter ready transfer window x is written (offset, data, width) tpxaofr.aoff := offset tpxdatar.data:= data tpxstatr.dw := width trstatr.dvx := 1 trstatr.dvx := 0 tisr.nfsix := 1 normal frame sent x event tready = 1 send "write offset and data frame" of pipe x address prediction: calculate tpxstatr.ap and tpxstatr.op tpxstatr.op = 0 ? tcr.no = 1 ? yes yes no no send "optimized write frame" of pipe x mli receiver ready pipe x initialized radrr.addr, rpxbar.addr := rpxbar modified by offset radrr.addr, rpxbar.addr := rpxbar.addr + rpxstatr.ap rdatar.data := data rcr.dw := detected data width rcr.tf := 10 b rier.nfri := 1 parity check & acknowledge frame parity check & acknowledge frame write data to remote window (see separate figure) normal frame received event transmitting mli controller receiving mli controller www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-31 v1.1, 2011-03 mli, v1.11 transmitting controller in the transmitting controller, a write operation to a location within a transfer window delivers the address, the data, and the data size to the transmitter and triggers the following actions in the mli transmitter. ? the 16 least significant address bits of the transfer window write access are stored in tpxaofr.aoff as write offset address. in case of a an access to a small transfer window, also 16 bits are stored, but the higher bits are not taken into account assuming the buffer size is configured correctly (see page 27-105 ). ? the data of the write access to the trans fer window is stored in tpxdatar.data. ? the data width of the write access to the transfer window (8-bit, 16-bit, or 32-bit) is stored in bit field tpxstatr.dw. ? status flag trstatr.dvx (data valid) is set, indicating that the pipe contains valid data for transmission. ? if the address prediction method is dis abled (tcr.no = 1), the transmission of a write offset and data frame is started as soon as the mli transmitter is idle, no higher priority frames are pending, and tready = 1. if the address prediction method is enabled (tcr.no = 0), a write offset and data frame is started only if an address prediction is not possible (indicated by tpxstatr.op = 0). if tpxstatr.op = 1, an address prediction is possible in the mli transmitter (and the mli receiver) and an optimized write frame can be started. the address prediction method used is described on page 27-47 . ? status flag trstatr.dvx is cleared by hardware and mli event status flag tisr.nfsix (normal frame sent event in pi pe x) is set (and a service request output is activated if enabled by tier.nfsiex = 1) after the write frame has been finished and correctly acknowledged by the mli receiver. the number m of offset address bits that are transmitted at a write offset and data frame is determined by the size of the remote window in the receiving controller that has been previously initialized by the tr ansmission of a copy base address frame. parameter m is referring to bit field tpxstatr.bs (and rpxstatr.bs) and can be in the range of 1 to 16 bits. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-32 v1.1, 2011-03 mli, v1.11 figure 27-24 write offs et and data frame figure 27-25 optimized write frame mca06295 x p 8-bit data 0 0 2 12+m tpxdatar.data[7:0] 3 1 1 x p 16-bit data 0 02 tpxdatar.data[15:0] 3 1 1 x p 32-bit data 0 02 tpxdatar.data[31:0] 3 1 1 4 tpxstatr.dw = 00 b tpxstatr.dw = 01 b tpxstatr.dw = 10 b header header header m = tpxstatr.bs+1 x = pipe number m-bit offset address tpxaofr.aoff 4 m-bit offset address tpxaofr.aoff 4 m-bit offset address tpxaofr.aoff 20+m 36+m mca06298 pn p 8-bit data 1 02 12 tdrar.data[7:0] 3 1 0 pn p 16-bit data 1 02 20 tdrar.data[15:0] 3 1 0 pn p 32-bit data 1 02 3 7 tdrar.data[31:0] 3 1 0 4 4 t pxstatr.dw = 00 b t pxstatr.dw = 01 b t pxstatr.dw = 10 b 4 header header header pn = tstatr.apn 11 19 36 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-33 v1.1, 2011-03 mli, v1.11 receiving controller after a write frame has been received correctly and acknowledged, the following actions are automatically executed in the mli receiver: ? in the case of a write offset and data frame: the result of the internal address predicti on is not taken into account. the received offset address is added to the base address of the pipe x remote window and the result is stored in rpxbar.addr. it is also stored in raddr.addr and represents the destination address in the receiving controller where data should be written to. in the case of an optimized write frame: the result of the internal address predicti on is taken into account. the next address in the receiving controller where data should be written to is calculated by adding the detected receiver address prediction value rpxstatr.ap to the actual address stored in rpxbar.addr and the result is stored in rpxbar.addr and in raddr.addr. ? the received data is written into the receiver data register rdatar (right aligned, unused bits are 0). ? the detected data width of the received data is written into bit field rcr.dw. ? the information about the received frame type (= 10 b for a write frame) is written into bit field rcr.tf. ? mli event status flag risr.nfri (normal frame received event) is set and an sr output line is activated if enabled by rier.nfrie = 01 b or 10 b . after these actions related to the reception of a write frame by the receiving controller, the data that has been received from the transmitting controller is ready to be written into the remote window related to the receiving pipe. this write operation can be executed in two ways: ? rcr.mod = 0: automatic data mode is disabled. in this mode, a bus master of the receiving controller, typically a cpu, is informed by a normal frame received event risr.nfri (a service request output is activated if rier.nfrie = 10 b ) to transfer the received write data from the mli receiver to the remote window. therefore, it must read the data from rdatar, together with width rcr.dw and the address stored in radrr and write it to the indicated address location. ? rcr.mod = 1: automatic data mode is enabled. in this mode, the mli module automatically writes the received write data to the remote window. this automatic action is controlled by a move engine block in the mli receiver. it also sets event status flag risr.mei (move engine event when the access is terminated). a service request output is activated if enabled by rier.meie = 1. the write operation to the remote window is executed only if the write address is within an enabled access protection range. if the address range is disabled for the write address, the automatic write action does not take place and event status flag risr.mpei (memory protection error) is set and a service request output is activated www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-34 v1.1, 2011-03 mli, v1.11 if enabled by rier.mpeie = 1. in this case, the receiving controller software can analyze the values in rdatar, together with width rcr.dw and the address stored in radrr. figure 27-26 write frame handling on receiving side note: in automatic data mode, write frames are leading to a write action executed by the mli move engine. during the move engine operation, only one more mli frame can be received (stored in a waiting position to be executed). then the reception of more frames is blocked by non-acknowledge handshake. if the move engine operation is finished, frame exec ution and reception continue normally. if automatic data mode is disabled, no blocking mechanism has been implemented. the receiving controller software has to take care to deal with the received data before it is overwr itten by new incoming frames. 27.2.1.3 read frames read frames transmit read request and optionally the read offset from the local controller to the remote controller. mca06307_wfhrs rcr.mod = 1 ? yes no access protection violation ? no yes memory protection error event write frame received write to remote window is not executed by the move engine write to remote window is executed automatically by the move engine risr.mei := 1 risr.mpei := 1 risr.nfri := 1 normal frame received event move engine event write to remote window is not executed by the move engine www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-35 v1.1, 2011-03 mli, v1.11 figure 27-27 read frame and answer frame flow normal frame received event mca06306_mod local mli controller remote mli controller mli transmitter ready read access to transfer window x (offset, width) tpxaofr.aoff := offset tpxstatr.dw := width trstatr.dvx := 1 trstatr.rpx := 1 rcr.dw := width tstatr.apn := x rcr.tf := 01 b risr.nfri := 1 mli receiver ready pipe x initialized trstatr.dvx := 0 tisr.nsfix := 1 tready = 1 send "discrete read frame" of pipe x send "answer frame" of pipe x trstatr.av := 0 tready = 1 rdatar.data := read data rcr.dw := width rcr.tf := 11 b trstatr.rpx := 0 risr.nfri := 1 address prediction: calculate tpxstatr.ap and tpxstatr.op tpxstatr.op = 0 ? tcr.no = 1 ? yes yes no no parity check & acknowledge frame radrr.addr, rpxbar.addr := rpxbar modified by offset parity check & acknowledge frame radrr.addr, rpxbar.addr := rpxbar.addr + rpxstatr.ap parity check & acknowledge frame send "optimized read frame" of pipe x normal frame received event read data from remote window (see separate figure) normal frame sent event www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-36 v1.1, 2011-03 mli, v1.11 local controller a read operation from a location within a transfer window x of the local controller delivers a dummy value as result of the read action and triggers the transmission of a read frame. the dummy value of the initial read action should be ignored and the software has to wait for the reception of the answer frame to get the desired data. ? the 16 least significant address bits of the transfer window read access are stored in tpxaofr.aoff as read offset address. in case of a an access to a small transfer window, also 16 bits are stored, but th e higher bits are not taken into account assuming the buffer size is configured correctly (see page 27-105 ). ? the data width of the transfer window read access (8-bit, 16-bit, or 32-bit) is stored in bit field tpxstatr.dw. ? status flag trstatr.dvx (data valid) is set. ? status flag trstatr.rpx (read pending) is set. this bit is cleared by hardware when an answer frame has been received correctly. ? if the address prediction method is not enabled (tcr.no = 1), transmission of a discrete read frame is started. if the address prediction method is enabled (tcr.no = 0), a discrete read frame is started only if an address prediction is not possible (indicated by tpxstatr.op = 0). if tpxstatr.op = 1, an address prediction is possible and an optimized read frame is started. ? status flag trstatr.dvx is cleared by hardware and mli event status flag tisr.nfsix (normal frame sent event in pi pe x) is set (and a service request output is activated if enabled by tier.nfsiex = 1) after the read frame has been finished and correctly acknowledged by the mli receiver of the remote controller. the number m of offset address bits that are transmitted at a discrete read frame is determined by the (coded) size of the remote window in the remote controller that has been previously initialized by the trans mission of a copy base address frame. parameter m is stored in bit field tpxstatr.bs (and rpxstatr.bs) and can be in the range of 1 to 16 bits. after a completed transmission of a read frame, the local controller expects the reception of an answer frame. the answer fr ame is introduced with the highest priority into the data flow of the transmitter of the remote controller. figure 27-28 discrete read frame mca06296 x p dw 0 02 6+m tpxstatr.d w 3 1 1 m-bit offset address 4 tpxaofr.aoff header m = tpxstatr.bs+1 x = pipe number dw = data width www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-37 v1.1, 2011-03 mli, v1.11 figure 27-29 optimized read frame remote controller after a read frame has been correctly received and acknowledged, the following actions are executed in the mli receiver of the remote controller: ? in the case of a discrete read frame: the result of the address prediction is not taken into account. the received offset address is added to the base address of the pipe x transfer window (stored in rpxbar.addr). the result of this additi on is stored in radrr.addr and also in rpxbar.addr and represents the destina tion address in the remote controller from where data should be read. in the case of an optimized read frame: the result of the address prediction is taken into account. the next address in the remote controller where data should be read is calculated by adding the detected receiver address prediction value rpxstatr.ap to the actual address stored in rpxbar.addr. the result of this addition is stored in radrr.addr and also in rpxbar.addr and represents the destina tion address in the remote controller from where data should be read. ? the transmitted data width dw is written into bit field rcr.dw. ? the information about the received frame type (= 01 b for a read frame) is written into bit field rcr.tf. ? mli event status flag risr.nfri (normal frame received event) is set and a service request output is activated if enabled by rier.nfrie = 01 b or 10 b . after correct reception of a read frame by the remote controller, the data requested by the local controller can be read by the remote controller and sent back to the local controller in form of an answer frame. this read operation can be executed in two ways: ? rcr.mod = 0: automatic data mode is disabled. in this mode, a bus master of the remote controller, typically a cpu, is informed by a normal frame received event to read the requested read data and transfer it to the mli receiver. therefore, it must read data mca0630 0 x p header 1 02 dw 46 tpxstatr.dw 3 15 1 dw = data width x = pipe numbe r www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-38 v1.1, 2011-03 mli, v1.11 with width rcr.dw from the address stored in radrr and write the data into tdrar.data. ? rcr.mod = 1: automatic data mode is enabled. in this mode, the move engine of the mli automatically reads data from the remote window and sets event status flag risr.mei (move engine access terminated). a service request output is activated if enabled by rier.meie = 1. the read operation from the remote window is executed only if the read address is within an enabled access protection range. if no address range is enabled for the actual read address, the automatic read action is not executed by the move engine, event status flag risr.mpei (memory protection error) is set and a service request output is activated if enabled by rier.mpeie = 1. in the interrupt handler routine, a bus master (e.g. cpu or pcp) must then take care of the remote window read operation and the data transfer to tdrar. ? after tdrar.data has been updated, status flag trstatr.av of the remote controller is set and the transmission of an answer frame is started. figure 27-30 read frame handling on remote side note: in automatic data mode, read frames are leading to a read action executed by the mli move engine. during the move engine operation, only one more mli frame can be received (stored in a waiting position to be executed). then the reception of more frames is blocked by a non-acknowledge handshake. if the move engine operation is finished, fram e execution and reception can continue normally. if automatic data mode is disabled, no blocking mechanism has been mca06307_rfhrs read from remote window is executed by a bus master (e.g. cpu) rcr.mod = 1 ? yes no access protection violation ? no yes risr.mpei := 1 read from remote window is executed by the move engine write to tdrar.data trstatr.av := 1 risr.mei := 1 move engine event memory protection error event read from remote window is executed by a bus master (e.g. cpu) risr.nfri := 1 normal frame received event www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-39 v1.1, 2011-03 mli, v1.11 implemented. the remote controller soft ware has to take care to read the received data. 27.2.1.4 answer frame please note that only one answer frame ca n be handled by the system at a time (no read frame request while any trstatr.rpx is set). make sure that not more than one read frame is pending at a time. if a read frame is not answered by an answer frame during a certain time interval, a time-out criterion should be handled in software. the remote controller has to take care that no answer frame is delivered after the time-out criterion has been detected (e.g. by a soft ware-triggered command frame). do not start a new read frame while waiting for an answer frame if the time-out criterion has not yet been detected and the answer frame has not yet been received. the length of the time-out interval depends on the application and has to be defined accordingly on a case by case base (e.g. the transfer rates between mli modules, bus architecture, etc. have to be considered). in the case a time-out has been detected, the local controller software has to clear the trstatr.rpx bit by writing 1 to scr.cdvx and can start a new read frame. remote controller (receiving the read request) the answer frame is the only frame sent from the remote controller back to the local controller. the transmitter registers of the remote controller are used to generate the answer frame. every time the transmitter data read answer register tdrar is written in the remote controller, the transmission of an answer frame is started and the following actions are triggered. ? status flag trstatr.av is set to tri gger the transmission of an answer frame. the following parameter is transmitted in the data field of the answer frame: ? read data: stored in tdrar.data; data width is determined by trstatr.dw. ? status flag trstatr.av is cleared after the answer frame has been finished and correctly acknowledged by the mli receiver of the local controller. an answer frame should be sent through the pipe that has received a read request but there must be only one mli transfer window read access pending on any side of a mli connection at any time, because the answer mechanism does not contain buffers for multiple answer frames. local controller (transmitting the read request) if an answer frame has been received correctly and acknowledged, the following actions are executed in the mli receiver of the local controller: ? the trstatr.rpx flags are cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-40 v1.1, 2011-03 mli, v1.11 ? the received data is written into the receiver data register rdatar. if 8 data bits are received, they are duplicated to all 4 bytes in rdatar. if 16 data bits are received, they are du plicated to both half-words in rdatar. ? the detected data width of the received data is written into bit field rcr.dw. ? the received pipe number x represents the answer pipe number and is written into bit field tstatr.apn. ? the information about the received frame type (= 11 b for an answer frame) is written into bit field rcr.tf. ? mli event status flag risr.nfri (normal frame received event) is set and a service request output is activated if enabled by rier.nfrie = 01 b or 10 b . ? the content of radrr becomes invalid. ? the data that has been previously requested from the remote controller by a read frame is now available in rdatar and can be read by a bus master (e.g. the cpu) of the local controller. ? if an answer frame is received while the corresponding trstatr.rpx bit is 0, the reception is declared as unintended and a discarded read answer event is generated (see page 27-62 ). figure 27-31 answer frame note: if an answer frame has been correctly received in the local controller, the local controller?s software has to read it. as l ong as at least one byte of this data has not yet been read out, only one more mli frame can be received (stored in a waiting position to be executed). then the reception of more frames is blocked by non-acknowledge handshake. if the re ceived data has been read out, frame execution and reception continue normally. mca06299 x p 8-bit data 1 024 12 tpxdatar.data[7:0] 3 1 1 11 x p 16-bit data 1 024 20 tpxdatar.data[15:0] 3 1 1 x p 32-bit data 1 024 3 6 tpxdatar.data[31:0] 3 1 1 19 35 t pxstatr.dw = 00 b t pxstatr.dw = 01 b t pxstatr.dw = 10 b header header header x = pipe number www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-41 v1.1, 2011-03 mli, v1.11 27.2.1.5 command frame command frames transmit a command (e.g. setup information or service request) from a transmitting controller to a receiving controller. figure 27-32 command frame transaction flow tready = 1 mca06304_mod transmitting mli controller receiving mli controller mli transmitter ready tcmdr.cmdpx is written trstatr.cv := 1 send "command frame" of pipe x (x, code) pipe 0: activate one signal of sr[3:0] risr.ic := 1 mli receiver ready trstatr.cv := 0 tisr.cfsix := 1 command frame sent in pipe x event interrupt command frame event pipe x: risr.cfrix := 1 command frame received event pipe 1: write rcr.dpe pipe 2: set/reset rcr.mod or reset trstatr.rp[3:0] or activate brkout signal pipe 3: write command code into rcr.cmdp3 parity check & frame acknowledge www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-42 v1.1, 2011-03 mli, v1.11 transmitting controller the transmission of a command frame is initiated by writing one of the four pipe x related command code bit fields in register tcmdr.cmdpx, triggering the following actions: ? status flag tpxstatr.cvx (command valid) is set and the command frame transmission is started using x as pipe number pn and the command code stored in tcmdr.cmdpx as parameters. ? trstatr.cvx is cleared after the command frame has been finished and correctly acknowledged by the mli receiver of the remote controller. ? mli event status flag tisr.cfsix (command frame sent event in pipe x) is set and a service request output is activated if enabled by tier.cfsiex = 1. receiving controller depending on the pipe x related command code that is transmitted by a command frame, different actions are triggered in the receiving controller. table 27-5 describes the actions that are transmitted by a command frame and that cause a specific control task in the mli receiver. ? the received pn value is checked and the corresponding control actions are executed according to table 27-5 . ? independent of the received pipe number, event status flag risr.cfrix (command frame received event in pipe x) is set an d a service request output is activated if enabled by rier.cfriex = 1. if a command frame is received for pipe 2 with command code 1111 b , the brkout output signal of the mli module becomes activated if it is enabled by bit rcr.ben = 1. if disabled by rcr.ben = 0, signal brkout will not be activated. the usage of brkout is implementation-specific and can be used, for example, to generate a break condition in the on-chip debug suppor t logic or trigger other functions. table 27-5 command frame encoding pn cmd command description 00 b 0001 b activate service request output sr0 of receiving mli module 0010 b activate service request output sr1 of receiving mli module 0011 b activate service request output sr2 of receiving mli module 0100 b activate service request output sr3 of receiving mli module others no effect, reserved for future use www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-43 v1.1, 2011-03 mli, v1.11 01 b 0000 b set rcr.dpe (delay for parity error indication) in receiving mli to 0000 b 0001 b set rcr.dpe in receiving mli to 0001 b 0010 b set rcr.dpe in receiving mli to 0010 b ... ... 1111 b set rcr.dpe in receiving mli to 1111 b 10 b 0001 b enable automatic data mode in receiving mli (set rcr.mod = 1) 0010 b disable automatic data mode in receiving mli (set rcr.mod = 0) 0100 b clear bit trstatr.rp0 in receiving mli 0101 b clear bit trstatr.rp1 in receiving mli 0110 b clear bit trstatr.rp2 in receiving mli 0111 b clear bit trstatr.rp3 in receiving mli 1111 b generate break output signal brkout in receiving mli (if enabled by rcr.ben = 1) others no effect, reserved for future use 11 b any free programmable software command, written into bit field rcr.cmdp3 of receiving mli table 27-5 command frame encoding (cont?d) pn cmd command description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-44 v1.1, 2011-03 mli, v1.11 27.2.2 general mli features the general mli features comprise the: ? parity generation and checking (see page 27-44 ) ? non-acknowledge error (see page 27-47 ) ? address prediction (see page 27-47 ) ? automatic data transfers (see page 27-48 ) ? access protection (see page 27-49 ) ? triggered command frames (see page 27-49 ) ? transmit priority (see page 27-50 ) ? transmission delay (see page 27-50 ) 27.2.2.1 parity check and parity error indication for parity generation, the number of transmitted bits with the value of 1 is counted over the header and the complete data field of a frame. for even parity, the parity bit is set if the result of a modulo-2 division of the elaborated number is 1. for odd parity, the parity bit is set if the result of a modulo-2 division of the elaborated number is 0. for a parity error-free mli connection, even parity must be selected in the transmitter because the receiver operates only with even parity detection. the capability to select odd parity can be used by the transmitter to force a parity error reply from the receiver during the startup procedure of the mli conn ection. this can be used to measure the propagation delay and to optimize the ready delay time (see page 27-73 ). note: there is no protection against frames where more than one bit is corrupted (e.g. shortened frames). in such a case, an unpredictable behavior of the mli module may occur. transmitting controller the mli transmitter counts the detected parity error conditions and generates a parity error event if a programmable number (max. 16) of parity error conditions has occurred. a parity error condition is indicated to the transmitter by the receiver after the transmission of a frame (see page 27-23 ). the transmitter parity error condition is detected when the tready signal is sampled at low level within a programmable number (tcr.mdp = maximum delay for parity errors) of tclk clock cycles after tvalid has been de-asserted to low. if a transmitter parity error condition is detected, the mli transmitter sets the parity error flag tstatr.pe and also decreases the maxi mum parity error counter tcr.mpe by 1. the maximum parity error counter of the transmitter tcr.mpe determines the number of transmit parity error c onditions that can be still detected until a tr ansmitter parity error event is generated. if a transmitter parity error condition is detected and tcr.mpe is becoming 0 or while it is 0, a transmitter parity error event is generated by setting bit tisr.pei (see figure 27-40 on page 27-60 ) and an srx output line is activated if www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-45 v1.1, 2011-03 mli, v1.11 enabled by tier.peie = 1. after a transmitter parity error event occurred, tcr.mpe can be set again by software to a value greater 0001 b . otherwise, each additional transmitter parity error condition will generate a parity error event. the transmitter parity error flag tstatr.pe is cleared by hardware when a correct frame transmission and tready has been sampled with 1 within the ready delay time. it can be cleared by software by writing a 1 to bit scr.ctpe. if for example, each transmitter parity error condition should generate a transmitter parity error event, tcr.mpe should be set to 0000 b . the software can check for accumulated parity error conditions by reading tcr.mpe or tisr.pei, for the status of the latest received frame, it can check tstatr.pe. figure 27-33 parity error indication for the transmitter receiving controller the receiver always checks the parity bit of a received frame for ev en parity. a receiver parity error condition is detected if the received parity bit does not match with the internally calculated one. if no receiver parity error condition is found after the reception of a frame, rready is immediately set to 1, otherwise rready is kept at 0 until a defined number of rclk cycles (determined by bit field rcr.dpe = delay for parity error) has been elapsed. then, rready is asserted high. if a receiver parity error condition is found, the mli receiver sets the parity error flag rcr.pe and additionally decreases the maximum parity error counter of the receiver rcr.mpe by 1. the maximum parity error counter rcr.mpe determines the number of receiver parity error conditions that can be still detected until a receiver parity error event is generated. if a receiver parity error condition is detected and rcr.mpe is becoming tcr.mdp mct06309_mod tdata tready tready tclk tvalid p with parity error indication without parity error indication www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-46 v1.1, 2011-03 mli, v1.11 0 or while it is already 0, a receiver parity error event is generated by setting bit risr.pei (see figure 27-44 on page 27-63 ) and a service request output is activated if enabled by rier.peie = 1. after a receiver parity error event has occurred, rcr.mpe can set again by software to a value greater 0001 b . if, for example, each receiver parity error condition should generate a receiver parity error event, rcr.mpe can be programmed to 0000 b or 0001 b . the receiver parity error flag rcr.pe is cleared by hardware if a correct frame transmission has occurred. rcr.pe can be cleared by software by writing a 1 to bit scr.crpe. the receiver parity error flag rcr.pe is cleared by hardware after a correct frame reception. it can be cleared by software by writing a 1 to bit scr.crpe. the software can check for accumulated parity error conditions by reading rcr.mpe or risr.pei, for the status of the latest received frame, it can check rcr.pe. the delay for parity error bit field rcr.dpe is a read-only bit field in the receiver that updated by hardware if a command frame for pipe 1 is received. with this frame type, the transmitting controller transfers a value for rcr.dpe to the receiving controller during the setup phase of the mli connection. figure 27-34 parity error indication by the receiver rcr.dpe mct06309_modr rdata rready rready rclk rvalid p with parity error indication without parity error indication www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-47 v1.1, 2011-03 mli, v1.11 27.2.2.2 non-acknowledge error a non-acknowledge error condition is detected by the transmitter when at the end of a frame transmission, the tready signal is still at high level (tready = 1 when tvalid becomes 0). in this case, the error flag tstatr.nae is set and the maximum non- acknowledge error counter tcr.mnae is dec remented by 1. if a non-acknowledge error condition is detected and tcr.mnae is becoming 0 or while it is already 0, a time- out event is generated by setting bit tisr.tei (see figure 27-40 on page 27-60 ) and an mli service request is generated if enabled by tier.teie = 1. the non-acknowledge error flag tstatr.nae is cleared by hardw are when a frame transmission has been acknowledged correctly. it can also be cleared by software when writing a 1 to bit scr.cnae. the non-acknowledge error counter tcr.mnae is automatically set to 11 b when a frame has been acknowledged correctly. it can be read and written by software, allowing a limited number of consecutive non-acknowledge errors to be defined that can be detected until a time-out error event is generated. if, for example, the first occurrence of a non-acknowledge error should lead to a time-out event, bit tcr.mnae has to be written by software with 00 b or 01 b after each correctly received frame. 27.2.2.3 address prediction an address prediction method can be enabled to support communication between mli transmitter and mli receiver without sending address offset information in the frames to optimize the required mli bandwidth. this feature reduces the required bandwidth for mli communication. both communication partners, mli transmitter and the mli receiver are able to detect regular offset differences of consecutive window accesses to the same window. the address prediction mechan ism working independently for each pipe, different prediction values can be handled in parallel for the different pipes. transmitting controller if the address prediction method is enabled (tcr.no = 0), the mli transmitter compares the offset of each transfer window read or write access with the offset of the previous access to the same transfer window (stored in tpxaofr.aoff). the result of this comparison is stored in two?s complement representation in tpxstatr.ap (limited to 9 bits, otherwise prediction is not possible). between the accesses to a specific window, other windows can be accessed without disturbing the prediction. if the offset differences are identical in at least two consecutive accesses to the same transfer window, an address prediction is possible (flag tpxstatr.op becomes set) and optimized frames can be sent to the receiving controller for this pipe. if the offset difference of a next access to the same transfer window does not match the calculated value in tpxstatr.ap, flag tpxstatr.op is cleared and address prediction is not possible. in this case, a normal frame for writing or reading (write offset and data frame or discrete read frame) is started. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-48 v1.1, 2011-03 mli, v1.11 receiving controller the mli receiver operates with an address prediction method equivalent to the mli transmitter. this means that after receiving at least two consecutive write offset and data frames and/or discrete read frames th at include address information, the mli receiver is able to follow the address prediction method used by the mli transmitter. each received offset is compared in the mli receiver with the offset of the previously received frame of the same pipe. the result of this comparison is stored in two?s complement representation in rpxstatr.ap (limited 9 bits). if an optimized frame is received by the mli receiver, it calculates the next address by adding the value stored in rpxstatr.ap to the contents of the receiver address register radrr. in case of a write offset and data frame or a discrete read frame (m offset bits), the receiver address registers radrr and rpxbar are always loaded with an updated address. this address is calculated by r eplacing the lowest m bit positions in rpxbar with the received offset value. in this case, the address delta value stored in rpxstatr.ap is not taken into account. the programmed size of the remote window and the number m of offset bits are given by rpxstatr.bs. the bit positions rpxbar[31:m] are kept constant, wherea s the bit positions rpxbar[m-1:0] are replaced. 27.2.2.4 automatic data mode the mli module supports automatic data transf ers for read or write frames without any cpu load in the receiving controller. this features is based on a move engine block providing the data, the complete address and the data width to an associated bus master on the system bus (see figure 27-1 ). depending on the implementation, this bus master can be capable of executing the request ed data move operations autonomously. the automatic data mode in the receiving controller can be enabled (rcr.mod = 1) or disabled (rcr.mod = 0) by software on receiving side or a command frame sent by the transmitting controller. if the automatic data mode is disabled, the receiving controller software has to execute the requested data transfers. additionally to the global enable/disable of the automatic mode by rcr .mod, it is possible to individually exclude address ra nges from automatic data transfer by an access protection scheme. the definition of the address ranges depend on the product and has been introduced to support the pr otection of critical data or modules. note: if a device contains the mli move e ngine block as the only bus master, automatic mode has to be selected to allow transfers. this could be the case for external peripheral devices without own cpu. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-49 v1.1, 2011-03 mli, v1.11 27.2.2.5 memory access protection the mli receiver provides a memory access protection logic allowing to exclude read and write accesses of the mli move engine to specific parts of the memory map from automatic mode. each address of a data move (read or write) is always checked if it targets an address range that is enabled for read/write access. if a requested data move is targeting an excluded address range, a memory access protection error event is generated and the receiving controller?s software can take care of the service request. the memory access protection logic handles two levels of address range definitions: ? fixed address ranges (for complete modules or memory areas) ? programmable address sub-ranges (to limit accesses to specific parts of bigger memory areas) there is a maximum of 2 x 32 fixed address ranges available that can be individually enabled/disabled by the address range enable bits aer0.aenx and aer1.aenx (x = 0- 31). if bit aery.aenx is set, read/write accesses to the associated address range x are supported in automatic mode. if bit aenx is cleared, read/write accesses to the associated address range x are not automati cally executed, a memory protection error event is generated, and srx output line is activated if enabled by risr.mpei. the mli module supports a definition of up to two times four programmable address sub- ranges (with index n) within fixed addre ss ranges. the parameters for the sub-ranges are stored in the access range registers arr0 and arr1, comprising: ? the size of an address slice defined as sub-range (arry.sizen) ? the location of an address slice defined as sub-range (arry.slicen) note: the definition of the fixed address ran ges and the sub-ranges is product-specific. detailed values are given in the module implementation chapter. 27.2.2.6 triggered command transfers the mli module supports the transmission of command frames triggered by hardware signals (up to 4 trigger inputs tr[3:0]). if a rising edge at a trx input is detected, a corresponding bit trstatr.civx is set. the mli transmitter sends out a command frame with pn = 00 b and cmd = x + 1 if bit civx = 1. this command frame can then trigger the activation of the corresponding srx service request output of the remote controller. a triggered command frame ca n be used monitor service request signals in the local controller and to transfer the requests to the remote controller, without intervention of any cpu. bit civx is automatically cleared after successful transmission of the related command frame or by writing 1 to scr.ccivx. note: the connection of the tr[3:0] input lines is product-specific. detailed information is given in the module implementation chapter (see page 27-137 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-50 v1.1, 2011-03 mli, v1.11 27.2.2.7 transmit priority in the case that several requests for frame transmission are pending at the same time in a mli transmitter, the following priority scheme is applied, starting with the highest priority. for the answer frame, only one frame can be pending at a time in the transmitter. so the user has to take care that an older answer frame is completely handled before requesting a new one. the same applies for the base address copy frame. for the triggered command frames, the software driven command frames and the read or write frames, one frame of eac h type can be pending per pipe at a time. note: the mli has 4 inputs for triggered command frames. they are not necessarily connected in all devices. please refe r to the device specific implementation chapter for details (see page 27-137 ). ? answer frame (only one frame pending allowed at a time) ? triggered command transfer (civ0 before civ1 before civ2 before civ3) ? software driven command frames (cv0 before cv1 before cv2 before cv3) ? read or write frames (dv0 before dv1 before dv2 before dv3) ? base address copy frame (only one frame pending allowed at a time) 27.2.2.8 transmission delay a transmission delay can be introduced in the transmitter between the detection of the rising edge of the rready input signal and the next possible frame start. this delay represents the minimum time between the acknowledge of a former frame by rready and a new frame (if a request is pending). the delay is defined by bit field tcr.tdel in cycles of the transmitter system clock f fpi . the purpose of the transmission delay is to compensate for the time required for data to be transferred from the receiver frequen cy domain into the microcontroller frequency domain. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-51 v1.1, 2011-03 mli, v1.11 27.2.3 interface description the mli transmitter and mli receiver communicate with other mli receivers and mli transmitters via a four-line serial connection each. several i/o lines of these connections are available outside the mli module kernel as a four-line output or input vector with index numbering a, b, c and d. the mli module internal i/o control blocks define which signal of a vector is actually taken into ac count and also allow polarity inversions (to adapt to different physical interconnection means). figure 27-35 general block diagram of the mli module each input/output signal used for mli communication between a transmitter and a receiver can be disabled and inverted in its polarity. please note that all waveform diagrams in the mli chapter refer to non-inverted signals. if polarity inversions are programmed, the waveform diagrams have to be interpreted accordingly. in order to avoid naming mismatches, the signals keep their names, although a polarity inversion might have been programmed. if desired, polarity inversions for the same signal have to be programmed in the transmitter and in the receiver to guaranty signal consistency (there has always to be an even number of inversions between an mli transmitter and receiver). after reset, the following setting is applied, allowing mli communication without modification of register oicr 1) : ? the signal with the index a is selected from each input/output vector. ? tclk generation is enabled and rclk reception is enabled. 1) other services (e.g. an automati c boot sequence or a boot routine) ca n change the oicr setting. differing values are then indicated in the corresponding implem entation chapter. 4 mcb06062_mod port control tready[d:a] tvalid[d:a] rclk[d:a] mli transmitter mli receiver mli module tdata tclk rready[d:a] rvalid[d:a] rdata[d:a] fract. divider i/o control i/o control move engine sr[7:0] f ml i f fpi brkout 4 4 4 4 4 tr[3:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-52 v1.1, 2011-03 mli, v1.11 ? polarity inversion is disabled for all signals (no inversion). ? not selected output signals are at low level. the usage of signal brkout is implementati on-specific and can be used, for example, to generate a break condition in the on-c hip debug support logic or trigger other functions. this signal is activated (as a pulse) by a command frame. the service request outputs sr[7:0] of the mli module can be activated (as a pulse) by transmitter or receiver events (for all srx), as well as by command frames (only for sr[3:0]). the mli module also supports 4 trigger inputs tr[3:0]. a rising edge at input trx sets bit trstatr.civx and requests the transfe r of a triggered command frame in pipe 0, with a cmd = x + 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-53 v1.1, 2011-03 mli, v1.11 27.2.3.1 transmitter i/o line control figure 27-36 shows the mli transmitter i/o control logic. figure 27-36 transmitter input/output control logic 27.2.3.2 receiver i/o line control figure 27-37 shows the mli receiver i/o control logic. 1 0 1 0 1 0 1 0 1 0 1 0 mca06301_mod tvalid tdata tclk tvalidb & tveb tvpb tdata trs treadya treadyb treadyc treadyd trp & tre tready mli transmitter mli transmitter i/o control logic tvalida & tvea tvpa tvalidd & tved tvpd tvalidc & tvec tvpc tdp tclk & tce tcp 2 01 10 11 00 1 0 oicr oicr oicr oicr oicr oicr oicr oicr oicr oicr oicr oicr oicr oicr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-54 v1.1, 2011-03 mli, v1.11 figure 27-37 receiver input/output control logic mca06302_mod rready rdata rclk rreadyb 1 0 rrpb rvs rvalida rvalidb rvalidc rvalidd rvp 1 0 01 10 11 00 & rve rvalid mli receiver mli receiver i/o control logic rreadya 1 0 rrpa rreadyd 1 0 rrpd rreadyc 1 0 rrpc rrs 01 10 11 00 rcs rclka rclkb rclkc rclkd rcp 1 0 01 10 11 00 & rce rds rdataa rdatab rdatac rdatad rdp 1 0 01 10 11 00 2 2 2 2 oicr oicr oicr oicr oicr oicr oicr oicr oicr oicr oicr oicr oicr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-55 v1.1, 2011-03 mli, v1.11 27.2.3.3 connecting several mli modules the mli structure also allows to connect several mli modules together, e.g. two remote controllers (x and y) to one local controller . in this case, the local controller can send data to either one or the other or to both remote controllers in parallel. each remote controller is connected via an own set of ready/valid signals to the local controller, whereas the transmitter data and clk are broadcast signals. the status of the valid lines defines, which remote controller is accessed. only one receiver being available in the local controller, the reception of data can be handled only either from one or the other remote controller. the software has to ensure that only one remote controller sends data back to the local controller, e.g. by using read frames or by enabling/disabling the generation of write frames in the remote controllers. figure 27-38 connecting two remote controllers remote controller x mli_trmulti treadya tdata tvalida tclk rreadya rdataa rvalida rclka mli receiver mli transmitter remote controller y treadya tdata tvalida tclk rreadya rdataa rvalida rclka mli receiver mli transmitter local controller treadya tvalida tvalidb treadyb tclk tdata mli transmitter rreadya rvalida rvalidb rreadyb rclka rdataa mli receiver rclkb rdatab www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-56 v1.1, 2011-03 mli, v1.11 another possibility to connect se veral mli modules is a ring st ructure, with (at least) one dedicated pipe per device. this leads to a structure where the local controller?s transmitter is connected to the receiver of remote controller x, the transmitter of remote controller x to the receiver of remote controller y, and the transmitter of remote controller y to the local controller?s receiver. this structure supports autonomous data generation and transfer in both remote controllers, for example to transfer data generated in a remote controller to the local controller without using read frames. in a ring structure, the read frame handling should be avoided. it is possible for the local controller to access both remote controllers independently. for example, the remote window of pipe x covers the address range of remote controller x, whereas pipe y targets the transfer window y of remote controller x. in remote controller y, the pipe y targets the available address range. if the local controller issues a write frame on pipe x, the remote controller x is addressed. in case of a write frame on pipe y, the remote controller y is targeted, passing through a transfer window of remote controller x. the two remaining pipes could be used for write frames issued by remote controller x (passing through a transfer window of remote controller y) and by remote controller y. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-57 v1.1, 2011-03 mli, v1.11 27.2.4 mli service request generation the mli module?s service request outputs srx are used to indicate module internal mli events to other modules or devices outside the mli module, depending on the device implementation. they can trigger interrupts of a cpu (if available), can be used as dma request lines (if available), or for other tr igger purposes. the mli events being able to trigger interrupts or other service requests , names of some flags and control registers refer to interrupt generation. mli module events are generated by event sources in the transmitter and in the receiver. each event source provides a status flag an d an enable bit with software clear capability. in some cases, several event sources are combined to a common event. an mli event, internally generated by an event source, is stored in a status flag that is located in the interrupt status registers tisr (for transmitter events) or risr (for receiver events). all event flags can be cleared individually by software write actions to bits located in the interrupt enable registers tier (for transmitter events) or rier (for receiver events). these two registers also contain the enable control bits that allow each event source to be enabled/disabled individually for service request activation. each event can be connected to exactly one of the eight serv ice request outputs sr[7:0] by a 3-bit interrupt node pointer. one additional register, the global interrupt set register gintr, allows each service request output to be activated separately without setting the status flags of the event sources (see page 27-58 ). this feature is sometimes helpful for software test purposes or to trigger mli external actions. interrupt registers the mli event sources are controlled by several registers (see table 27-6 and page 27-107 ). the register name prefixes ?t? and ?r ? indicate if a register is assigned to the mli transmitter or to the mli receiver. service request compressor the mli event logic uses a compressing schem e for flexible service request processing. eleven mli events (six transmitter events and four of the five receiver events) are directed via a 3-bit interrupt node pointer to one of the eight service request outputs table 27-6 interrupt registers unit registers with request flags enable bits/ req. flag clear bits node pointer mli transmitter tisr tier tinpr mli receiver risr rier rinpr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-58 v1.1, 2011-03 mli, v1.11 sr[7:0]. each demultiplexer output selected by its node pointer = x (x = 0-7) is connected to one input of the srx or-gate. this wiring scheme also supports the connection of more than one event source to an service request output srx. one receiver event, the interrupt command frame event, has a special characteristic: its node pointer is controlled by the received cmd value directly and only sr[3:0] or-gates are selectable. figure 27-39 shows the service request compressing logic. for reasons of simplicity, not all mli events, connections, and or-gates are explicitly shown. the or-gate inputs are connected to the demultiplexers of th e mli event specific lines. furthermore, a service request output srx can be triggered by software if the corresponding interrupt set bit in register gintr is written with a 1. figure 27-39 service request compressor mca06319_mod node pointer tinpr service request output sr0 001 010 011 000 transmitter event with own node pointer . . . . . . . to sr1 or-gate to sr2 or-gate sr0 or-gate to sr3 or-gate to sr4 or-gate to sr5 or-gate to sr6 or-gate 101 110 111 100 simli0 gintr node pointer rinpr service request output sr7 001 010 011 000 receiver event with own node pointer to sr1 or-gate to sr2 or-gate sr7 or-gate to sr3 or-gate to sr4 or-gate to sr5 or-gate to sr6 or-gate 101 110 111 100 simli7 gintr interrupt command frame event 0001 0010 0011 0000 mli receiver to sr1 or-gate to sr2 or-gate to sr3 or-gate receiver events 3 4 3 1 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-59 v1.1, 2011-03 mli, v1.11 note: the number of srx outputs of an mli module and their connection to other modules depends on the implementation of th e mli module in the specific product. 27.2.5 transmitter events the mli transmitter can generate the following mli events: table 27-7 mli transmitter events events events combined to see parity error parit y/time-out error page 27-60 time-out error normal frame sent in pipe 0 normal frame sent in pipe 0 page 27-60 normal frame sent in pipe 1 normal frame sent in pipe 1 normal frame sent in pipe 2 normal frame sent in pipe 2 normal frame sent in pipe 3 normal frame sent in pipe 3 command frame sent in pipe 0 command frame sent page 27-61 command frame sent in pipe 1 command frame sent in pipe 2 command frame sent in pipe 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-60 v1.1, 2011-03 mli, v1.11 27.2.5.1 parity/tim e-out error event a parity/time-out error event is generat ed when a programmable maximum number of parity errors or a programmable maximum number of non-acknowledge errors have been reached. both events have separate status/control bits but are concatenated to one common error event. figure 27-40 parity/time-o ut error event logic 27.2.5.2 normal frame sent x event a normal frame sent x (x = 0-3) event is generated when a normal frame has been sent and correctly received in pipe x. figure 27-41 normal frame sent x event logic peie tier peir mca06311a_mod teie tier teir 1 software clear parity error event pei tisr set time-out error event tei tisr set software clear pteip 3 tinpr to sr0 to sr7 ?. ?. parity/ time-out error event nfsiex tier nfsirx software clear mca06312_mod x = 0-3 normal frame sent in pipe x event nfsix tisr set nfsipx 3 tinpr to sr0 to sr7 ?. ?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-61 v1.1, 2011-03 mli, v1.11 27.2.5.3 command frame sent events a command frame sent event is generated when the mli transmitter has sent a command frame through pipe x (x = 0-3) that has been correctly received. separate status/control bits are assigned to each pipe. all four pipe related command frame sent events are concatenated to one co mmon command frame sent event. figure 27-42 command frame sent event logic command frame sent in pipe 0 event cfsi0 tisr software clear set cfsi0 control logic command frame sent in pipe 1 event cfsi1 control logic cfsi2 control logic cfsi3 control logic command frame sent in pipe 2 event command frame sent in pipe 1 event cfsie0 tier cfsir0 mca06313a_mod command frame sent event 1 cfsip 3 tinpr to sr0 to sr7 ?. ?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-62 v1.1, 2011-03 mli, v1.11 27.2.6 receiver events the mli receiver can generate the following mli events: 27.2.6.1 discarded read answer event a discarded read answer received event is generated if an answer frame has been received and the read pending flag trstatr.rpx of its correspondent pipe is 0. although named ?discarded?, the received data is available in the receiver data register until it is overwritten by the next incoming data. figure 27-43 discarded read answer event logic table 27-8 mli receiver interrupts events events combined to see discarded read answer discarded read answer page 27-62 memory access protection error memory access protection/ parity error page 27-63 parity error normal frame correctly received normal frame received page 27-64 move engine access terminated interrupt command frame interrupt command frame page 27-65 command frame received on pipe 0 command frame received page 27-66 command frame received on pipe 1 command frame received on pipe 2 command frame received on pipe 3 discarded read answer event draie rier drair drai risr set mca06314a_mod software clear draip 3 rinpr to sr0 to sr7 ?. ?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-63 v1.1, 2011-03 mli, v1.11 27.2.6.2 memory access prot ection/parity error event a memory access protection/parity error event is detected if a non allowed read or write access has been detected or if a programmable maximum number of receiver parity errors is reached. both mli events have separate status/control bits but are concatenated to one common error event. figure 27-44 memory access protection/parity error event logic mca06315a_mod mpeie rier mpeir peie rier peir memory access protection / parity error event software clear mpei risr set pei risr set memory access protection error event parity error event software clear 1 mppeip 3 rinpr to sr0 to sr7 ?. ?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-64 v1.1, 2011-03 mli, v1.11 27.2.6.3 normal frame received/move engine terminated event a normal frame received event is generated if the mli receiver has correctly received a normal frame (a copy base address fr ame, a read or a write frame, an answer frame, but not a command frame) or if the mo ve engine has terminated its read or write access. both event sources have separate status/control bits but are concatenated to one common normal frame received event. figure 27-45 normal frame received event logic nfrie rier nfrir nfri risr set mca06316a_mod rier meir mei risr set 0 normal frame received event 2 software clear software clear normal frame correctly received event move engine access correctly terminated event nfrip 3 rinpr to sr0 to sr7 ?. ?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-65 v1.1, 2011-03 mli, v1.11 27.2.6.4 interrupt co mmand frame event an interrupt command frame event is ge nerated if a command frame is received correctly on pipe 0 with a valid command code for service request output activation (cmd = 0000 b to 0011 b ). the received command code determines which of the service request outputs sr[3:0] should be activated. figure 27-46 interrupt command frame event logic ice rier icer software reset mca06312a_mod interrupt command frame event ic risr set cmd pn = 0 to sr0 to sr3 to sr1 to sr2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-66 v1.1, 2011-03 mli, v1.11 27.2.6.5 command frame received event a command frame received event is generated if the mli receiver has correctly received a command frame through pipe number x (x = 0-3). separate status/control bits are assigned to each pipe. all four pi pe related command frame received in pipe x events are concatenated to one common command frame received event. figure 27-47 command frame received event logic command frame received in pipe 0 event cfri0 risr set cfri0 control logic command frame received in pipe 1 event cfri1 control logic cfri2 control logic cfri3 control logic command frame received in pipe 2 event command frame received in pipe 3 event software clear cfrie0 rier cfrir0 mca06317a_mod command frame received event 31 cfrip 3 rinpr to sr0 to sr7 ?. ?. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-67 v1.1, 2011-03 mli, v1.11 27.2.7 baud rate generation the mli transmitter baud rate is given by f mli /2. the mli shift clock output signal tclk of the transmitter toggles with each clock cycle of f mli in order to obtain a 50% duty cycle (the 50% duty cycle can vary up to one clock cycle of f fpi in fract ional divider mode). the mli receiver automatically adapts to the incoming receive shift clock signal rclk. the received baud rate is determined by the connected transmitter and has no direct relation to f fpi except that it should not exceed f fpi . the frequency f mli is generated by the fractional divider fdiv. figure 27-48 mli baud rate generation normal divider mode in normal divider mode (fdr.dm = 01 b ) the fractional divider behaves like a reload counter (addition of +1) that generates a clock f mli on the transition from 3ff h to 000 h . fdr.result represents the counter value and fdr.step defines the reload value. in order to achieve f mli = f fpi , fdr.step must b e programme d wit h 3ff h . the output frequency in normal divider mode is defined according the following equation: (27.1) fractional divider mode if the fractional divider mode is selected (fdr.dm = 10 b ), the clock f mli is derived from the input clock f fpi by division of a fraction of step/1024 for any value of step from 0 to 1023. in general, the fractional divider mode allows to program the average clock frequency with a higher accuracy than in normal divider mode. in fractional divider mode a clock pulse f mli is generated depending on the result of the addition fdr.result + fdr.step. the frequency f mli corresponds to the overflows over 3ff h . note that in fractional divider mode the clock f mli can have a maximum period jitter of one f fpi clock period. this jitter is not accumulated over several cycles and does not fdiv mca06324_mod f fpi f ml i transmitter receiver mli registers tclk rclk f ml i /2 f mli = f fpi 1 1024 - fdr.step www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-68 v1.1, 2011-03 mli, v1.11 exceed one cycle of f fpi . the frequency in fractional divider mode is defined according the following equation: (27.2) the baud rate of mli transmissions equals f tclk , that is defined by the frequency of clock signal f mli divided by 2 to create the 50% duty cycle of the shift clock signal tclk. the signal tclk toggling with each period of f mli , a jitter due to fractional dividing is propagated to tclk. (27.3) 27.2.8 automatic register overwrite the value of register oicr and bit rcr.rcvrst is overwritten by hardware in the next two clock cycles after a reset (first oicr, followed by rcr). t he value applied during reset is given in the register description. this automatic overwrite allows adapting the module to different application requirements without changing the module itself. for example, during reset the receiver is set to a defined state and can be used afterwards for reception without the need to modify it by a write action (if the bit rcvrst is modified to 0). the values applied after the overwrite can be identical to the indicated reset values. please refer to the implementation chapter for the modified values (see ). f mli = f fpi step 1024 f tclk = f mli 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-69 v1.1, 2011-03 mli, v1.11 27.3 operating the mli data transfer via mli between a local controller and a remote controller is only possible if both are initialized correctly by following sequence of 4 steps. steps 3 and 4 are necessary if the initialization sequence is exclusively controlled by the local controller. if both communication partners are able to run initialization software, steps 1 and 2 can be executed separately by both controllers to initialize both transmitters and both receivers. 1. the transmitter of the local controller has to be initialized by write actions to the transmitter registers. 2. the pipes from the local controller?s tran smitter to the remote controller?s receiver and the remote controller?s receiver have to be initialized. 3. the remote controller?s transmitter has to be initialized by data write actions from the local controller via the remote controller?s receiver to the remote controller?s transmitter registers. 4. the pipes from the remote controller?s transmitter back to the local controller?s receiver and the local controller?s receiver have to be initialized. this is done by frames from the remote controller?s transm itter. these frames are the result of data write actions of the local controller to the remote controller?s transmitter registers. figure 27-49 initialization sequ ence for an mli connection mli_init_sequenc e local controller port mli transmitter mli receiver port port mli receiver mli transmitter port step 1 remote controller step 4 step 2 step 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-70 v1.1, 2011-03 mli, v1.11 to initialize and to operate the mli, the following items should be taken into account: ? connection setup (see page 27-70 ) ? local controller transmitter and pipe setup (see page 27-71 ) ? remote controller receiver setup (see page 27-71 ) ? remote controller transmitter and local controller receiver setup (see page 27-72 ) ? delay adjustment (see page 27-73 ) ? connection to dma mechanism (see page 27-75 ) ? connection of mli to spi (see page 27-75 ) 27.3.1 connection setup for the general setup of an mli connection, several steps have to be respected. ? there is the possibility to change the signal routing to adapt to di fferent appl ications. if another connection than the default one from an input/output vector of the mli signals is desired, register oicr has to be programmed (see also section 27.2.8 ). ? in some devices (mainly stand-alone peripheral devices without cpu, where the mli module is a possible communication channel), the setting ?a? can be modified by hardware to another setting (e.g. to setting ?b?) during the boot phase. in this case, the initial setting ?a? can correspond to an inactive setting (mli not used for communication), whereas the setting ?b? is used for mli communication. ? in the case a memory access protection is implemented in the receiver and automatic handling of data is desired, the user has to enable the corresponding address range in registers aer and arr. after a reset, in most microcontrollers, the access protection is generally disabled to avoid access to safety-critical data. depending on the device, some specific address ranges can already be enabled for automatic access by default. ? in devices with explicit port control (such as microcontrollers), the port pins are generally set to input after a reset. in order to allow mli communication, the mli- related port pins have to be configured to make the mli signals externally available and to adapt the driver setting (refer to port chapter). the mli module should not be enabled for reception (rcr.rcvrst = 1) before programming the desired port setting, because changing the port setting can lead to unintended edges at the module inputs due to setting changes. if the mli module is already enabled for reception, unintended edges are interpreted as communication signals, so the receiver might deliver wrong results. if this has happened unintentionally, the receiver can be reset by rcr.rcvrst=1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-71 v1.1, 2011-03 mli, v1.11 27.3.2 local transmitter and pipe setup the initialization of the transmitter of the local controller is done by writing to the transmitter registers. the remote controller?s mli receiver can then be initialized by the local controller?s transmitter. ? after a hardware reset operation, the ml i transmitter is disabled (tcr.mod = 0). in disabled mode, no frame transmission can take place. after writing tcr.mod = 1, the transmitter is enabled to send frames. ? the desired transmitter baud rate can be adj usted by the fractional divider fdiv. it has to be ensured that the fractional divider is set to a value that is supported by the port structures of the local and the remote controllers (rise/fall times) and the physical layer. for example, if a division by 1,5 is selected, the fractional divider will deliver count pulses for f mli with a sequence of 1-2-1-2-1-2- clock cycles of f fpi . the shortest interval between two count puls es in a sequence (given by the truncated divider factor, so 1 cycle of in this exampl e) has to be handled by the communicating devices. f fpi ? depending on the application requirements, a desired service request output srx can be activated if a transmitter event is detected. ? the maximum delay for parity error detection in the transmitter has to be programmed. there are two possibilities to get the mli communication started. first (easier) possibility is to write tcr.mdp to 14 and to set rcr.dpe to 15. the second possibility could be used to optimize the bandwidth of the mli connection. it is described in section 27.3.5 on page 27-73 . 27.3.3 remote receiver setup the initialization of the remote controller?s receiver is done by frames sent by the local transmitter. therefore, the remote controller?s receiver has to be able to receive frames. ? in order to allow communication, the remote controller?s mli signals have to be connected to the local controller?s transmitter signals (see register oicr and port settings). ? the remote controller?s bit rcr.rcvrst has to be 0 to enable frame reception. ? the buffer area size and the base address of the remote window for pipe x are defined by the data writ ten to registers tpxbar. bit trstatr.bav has to be 0 before each write action to one of these r egisters. with this information, the buffer area sizes (defining the number of address bi ts in data frames or read frames) are known in the transmitter and in the receiver for each pipe. the base addresses for the remote windows have to be selected to cover the target address ranges in the remote controller. it is recommended to use the minimum buffer size required by the application in order to minimize the bandwidth taken by the transfer of the address bits. the base address of a remote window has to be set to a value aligned to its size, e.g. a remote window of 8 kbytes must start at an 8 kbyte address boundary. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-72 v1.1, 2011-03 mli, v1.11 ? in devices with access protection mechanism against unauthorized accesses via mli, the remote controller has to enable the desired address range(s) to support automatic mode. if automatic mode is not desired, the remote controller has to handle the complete data traffic by software. ? a possibility to test t he setup in devices with the capab ility to run own test software is the local loop back (the transmitter is connected locally to the receiver of the same mli module). in devices without this capability, the module loop back can be hardly used (or it is even not implemented, refer the connection table in the implementation chapter). if implemented, for local loop back, the signal connections have to be programmed to setting ?d?, leading to the local receiver being connected directly to the local transmitter (without using a port structure). in this case, the local receiver seems to be the remote receiver. data written to a local transfer window are received and handled by the local receiver. test software in the local controller can check for correct setup, data consistency, mli event handling, and correct address handling in the local controller. ? if automatic data handling is desired (nece ssary for devices without the capability to handle data traffic by its cpu), the automatic data mode has to be enabled by sending a command frame in pipe 2 with cm = 0001 b to set rcr.mod = 1 in the remote controller. 27.3.4 remote tran smitter and local receiver setup the initialization of the remote controller?s transmitter and the local controller?s receiver can be done by data frames sent by the local transmitter. therefore, the remote controller?s receiver has to be able to receive frames (the port structure has to be set up accordingly). ? the remote window of pipe x (x can be freely chosen) has to be set to the mli register address range in the remote cont roller. the initialization by data frames is then done via pipe x. ? the automatic mode has to be enabled in the remote controller (command frame in pipe 2 with cm = 0001 b ). ? the connections between the remote transmitter and the local receiver have to be established (if not already done by the default setting), similar to section 27.3.2 . ? the remote transmitter has to be enabled, similar procedure as for the local transmitter. the data word to be written to the remote controller?s mli registers have to be written to the corresponding address in the local transfer window of pipe x. ? the local receiver can then be configured by writing the appropriate data (similar scenario as for the remote receiver) to the local transfer window of pipe x. ? a possibility to test the complete setup is the remote loop back. in this case another remote window is overlaid directly to a transfer window in the remote controller. writing data to the corresponding transfer window in the local controller leads to a data frame sent to the remote controller. there, the received data is written to the www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-73 v1.1, 2011-03 mli, v1.11 transfer window and a new data frame is sent back to the local controller. the mli move engine in the local controller?s receiver can be used to write the received data to a defined location, e.g. to a memory location. test software in the local controller can check for correct setup, data consistency, mli event handling, and correct address handling in the local and the remote controllers. 27.3.5 delay adjustment the local mli transmitter is measuring the number of tclk clock cycles between tvalid becoming 0 after a transmission and tready becoming 1 again. this time represents the overall loop delay of the mli connection. the loop delay is the time used for signal propagation, input/output driver delay and remote receiver reaction. for example, with slow drivers and a high load ( due to long wires, etc.), the signals take a longer time to propagate from the local transmitter to the remote receiver and back again (ready-valid control handshake). this delay (also visible when tvalid becomes 1 at the beginning of a frame) limits the maximum baud rate of an mli connection, because the answer of the receiver has to be detected by the transmitter with tready = 0 at the end of the frame. the value measured after the end of the frame is indicated in bit field tstatr.rdc. the receiver participates in the control handshake by changing its rready output as a reaction to an incoming rvalid signal. for the transmitter, the tready input delivers the information that a receiver is connected and that it is ready for reception (transfer only starts if tready = 1). if a receiver is not able to handle the data or is not connected, the tready line will not become low after tvalid becomes 1 (non-acknowledge). in addition to this information, the mli protocol offers the possibility to use the control handshake also to indicate that the receiver has detected a parity error in the received frame. if a correct frame has been received, the receiver immediately asserts rready = 1 after the reception of a frame when detecting rvalid = 0. if the receiver has detected a parity error, it waits fo r a programmable number of rclk cycles before setting rready = 1 again. this additional delay is defined by bit field rcr.dpe. the transmitter measuring the delay and comparing it to a programmed value, it can detect that the receiver has signaled a parity error by introducing the additional delay. the compare value for the transmitter is pr ogrammed by bit field tcr.mdp. a measured value of tstatr.rdc above tcr.mdp is interpreted as parity error by the transmitter (for parity error handling refer to page 27-44 ). in the receiver, frames with parity error are ignored for data transfers and don?t lead to internal move actions. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-74 v1.1, 2011-03 mli, v1.11 figure 27-50 loop delay measurement to adjust the generated parity delay in the local transmitter and in the remote receiver, the following steps are necessary: ? send a dummy frame to the receiver for me asuring the loop delay. this frame should not lead to internal data move actions in the receiver, so a parity error can be simulated in the transmitter. the receiver has a fixed even parity scheme, whereas the transmitter can be programmed either for even or for odd parity. programming odd parity before sending a frame will generate a (dummy) frame that will be discarded by the receiver (assuming a correct transfer). for a dummy frame, it is recommended to use a data frame with disabled automatic data mode in the receiver (rcr.mod = 0). ? the receiver delay rcr.dpe being 0 after a module reset, the transmitter can measure the loop delay and the receiver discards the frame (without modification of dpe, there is no difference in time between a frame with or without a parity error having been detected). the value given by tstatr.rdc indicates how many tclk cycles are necessary for a control handshake. this value should be incremented by a value delta (value see below) and written to tcr.mdp. ? the transmitter parity has to be programmed to even parity to be able to generate frames that are not discarded by the receiver. ? programming the receiver delay for parity error (rcr.dpe) to a value bigger than delta will lead to a value of tstatr.rdc bigger than tcr.mdp if the receiver detects a parity error. the value of dpe in the remote receiver is modified by the local transmitter by sending a command frame in pipe 1 with the desired value. the difference between tstatr.rdc and tcr.mdp allows a certain timing tolerance between local transmitter and remote receiver. ? the value of delta depends on the possible variations of the propagation characteristics of the mli connection. if the environment does not significantly change, delta can be 1. for systems with variations, delta could be bigger. the mct06309a_mod rdc tready 012n-1n loop delay tvalid tclk www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-75 v1.1, 2011-03 mli, v1.11 user can check about changing propagation characteristics by reading tstatr.rdc from time to time and to check if it is constant for correct transfers. if it changes, either a bigger delta value ca n be applied, or the delay adjustment can be repeated, adapting to the new circumstances. 27.3.6 connection to dma mechanism the mli module supports the connection to a dma (direct memory access) mechanism. this mechanism allows the tran sfer of blocks of data of pr ogrammable size via an mli connection without cpu intervention. therefore, a dma mechanism can be used in the local controller to write the desired number of data words one after the other to the corresponding mli transfer window. the addr ess ranges of the data blocks and their length has to be handled by the dma module. an mli pipe supporting only one pending write frame request at a time, the dma has to wait until the pipe is capable to handle new data before writing another data word to the transfer window. therefore, the normal frame sent events of the pipes can trigger dma data transfers. depending on the connection of the mli module?s service request outputs srx to the dma trigger inputs, the normal frame sent events have to be enabled for service request activation and directed to the desired srx outputs. it is recommended to use only one type of mli event per srx output to trigger a data transfer by dma. if the dma mechanism needs a start trigger for the first data word transfer, register gintr can be written with the appropriate pattern to activate an srx output. 27.3.7 connection of mli to spi the handshake signals between a transmitter and a receiver are based on a synchronous transfer protocol. in the spi protocol, the shift clock and the data signal are equivalent to clk and data. in case of an 4-wire spi, the slave select signal represents the valid signal (the leading and the trailing delay have to be set up accordingly). contrary to the mli, in the spi protocol, a complete control handshake is not defined, so the ready signal does not exist in spi modules. as a result, the spi communication does not check by hardware for correct data transfer, but has to handle this on an upper software layer. if using an spi module for communication with an mli transmitter or an mli receiver, the ready signal has to be handled by software or the handshake has to be given up. this can be done by connecting the tvalid signal of an mli transmitter to one of its own tready inputs with polarity inversion. like this, the tready input directly following the inverted tvalid signal, the parity error indication and the non- acknowledge error detection are not possible. furthermore, in the mli protocol, the fram es may have a different width, depending on their type and selected buffer size. the di fferent numbers of data bits per frame have also to be handled by the spi module. in order to minimize the number of different frames, it is recommended to restrict the possibility to program different buffer sizes, the use of read frames or command frames. in order to simplify the data handling by an www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-76 v1.1, 2011-03 mli, v1.11 spi module, the parity generation could be skipped for frames received by the spi module and an error detection mechanism on an upper software layer could be implemented. for frames sent by an spi modul e, the parity bit has to be calculated and sent correctly. otherwise, the mli receiver will discard the received frame. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-77 v1.1, 2011-03 mli, v1.11 27.4 mli kernel registers this section describes the kernel registers of the mli module. all registers can be accessed with 8-bit, 16-bit or 32-bit write or read operations. accesses to address locations inside the mli address range not targeting the indicated registers are not allowed. the complete and detailed address map of the of the mli module and its registers is described in table 27-14 on page 27-139 . all registers in the mli address spaces are reset with the application reset. mli kernel register overview figure 27-51 mli kernel registers tpxbar mca06320b_mod tpxaofr tcbar rpxbar radrr fdr tstatr tpxstatr tcmdr trstatr tcr rpxstatr scr tier tisr tinpr rier risr rinpr gintr oicr aerx arrx x = 0-3 (number of pipes) general module registers general status / control registers access protection registers transmitter control/ status registers transmitter address / data registers transmitter interrupt registers receiver control / status registers receiver address / data registers receiver interrupt registers rcr id tpxdatar tdrar rdatar x = 0-1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-78 v1.1, 2011-03 mli, v1.11 table 27-9 registers address space - mli kernel registers module base address end address note mli0 f010 c000 h f010 c0ff h ? mli1 f010 c100 h f010 c1ff h ? table 27-10 registers overview - mli kernel registers register short name register long name offset address 1) description see id module identification register 08 h page 27-82 fdr fractional divider register 0c h page 27-79 tcr transmitter control register 10 h page 27-92 tstatr transmitter status register 14 h page 27-95 tpxstatr transmitter pipe x status register 18 h + (x * 4) page 27-97 tcmdr transmitter command register 28 h page 27-99 trstatr transmitter receiver status register 2c h page 27-101 tpxaofr transmitter pipe x address offset register 30 h + (x * 4) page 27-103 tpxdatar transmitter pi pe x data register 40 h + (x * 4) page 27-104 tdrar transmitter data read answer register 50 h page 27-104 tpxbar transmitter pipe x base address register 54 h + (x * 4) page 27-105 tcbar transmitter copy base address register 64 h page 27-106 rcr receiver control register 68 h page 27-113 rpxbar receiver pipe x base address register 6c h + (x * 4) page 27-117 rpxstatr receiver pipe x status register 7c h + (x * 4) page 27-116 raddr receiver address register 8c h page 27-118 rdatar receiver data register 90 h page 27-119 scr set clear register 94 h page 27-84 tier transmitter interrupt enable register 98 h page 27-107 tisr transmitter interrupt status register 9c h page 27-109 tinpr transmitter interrupt node pointer register 0a0 h page 27-111 rier receiver interrupt enable register a4 h page 27-120 risr receiver interrupt status register a8 h page 27-123 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-79 v1.1, 2011-03 mli, v1.11 27.4.1 general module registers fractional divider register the fractional divider register allows to program the frequency f mli to generate the baud rate of the of the 50% duty cycle transmitter shift clock tclk. rinpr receiver interrupt node pointer register ac h page 27-125 gintr global interrupt set register b0 h page 27-83 oicr output input control register b4 h page 27-86 aer0 access enable register 0 b8 h page 27-90 arr0 access range register 0 bc h page 27-91 aer1 access enable register 1 c0 h page 27-90 arr1 access range register 1 c4 h page 27-91 1) the absolute register addres s is calculated as follows: module base address ( table 27-9 ) + offset address (sho wn in this column) fdr fractional divider register (0c h ) reset value: 03ff 43ff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dis clk en hw sus req sus ack 0result rwh rw rh rh r rh 1514131211109876543210 dm sc sm 0 step rw rw rw r rw table 27-10 registers overview - mli kernel registers (cont?d) register short name register long name offset address 1) description see www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-80 v1.1, 2011-03 mli, v1.11 field bits type description step [9:0] rw step value in normal divider mode step contains the reload value for result. in fractional divider mode this bit field defines the 10- bit value that is added to the result with each input clock cycle. sm 11 rw suspend mode sm selects between granted or immediate suspend mode. this bit is only taken into account in devices supporting suspend mode. 0 b granted suspend mode selected 1 b immediate suspend mode selected sc [13:12] rw suspend control this bit field defines the behavior of the fractional divider in suspend mode (bit susreq and susack set). this bit field is only taken into account in devices supporting suspend mode. 01 b clock generation is stopped and the clock output signals are not generated. result is not changed except when writing bit field dm with 01 b or 10 b . 00 b clock generation continues. 10 b clock generation is stopped and the clock output signals are not generated. result is loaded with 3ff h . 11 b same as sc = 10 b but rst_ext_div is 1 (independently of bit field dm). dm [15:14] rw divider mode this bit fields defines the functionality of the fractional divider block. 00 b fractional divider is switched off; no output clock is generated. rst_ext_div is 1. result is not updated (default after reset). 01 b normal divider mode selected. 10 b fractional divider mode selected. 11 b fractional divider is switched off; no output clock is generated. result is not updated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-81 v1.1, 2011-03 mli, v1.11 result [25:16] rh result value in normal divider mode result acts as reload counter (addition +1). in fractional divider mode this bit field contains the result of the addition result+step. if dm is written with 01 b or 10 b , result is loaded with 3ff h . susack 28 rh suspend mode acknowledge 0 b suspend mode is not acknowledged. 1 b suspend mode is acknowledged. suspend mode is entered when susack and susreq are set. susreq 29 rh suspend mode request 0 b suspend mode is not requested. 1 b suspend mode is requested. suspend mode is entered when susack and susreq are set. enhw 30 rw enable hardware clock control 0 b bit disclk cannot be cleared by hardware by a high level at input signal ecen. 1 b bit disclk is cleared by hardware while input signal ecen is at high level. disclk 31 rwh disable clock 0 b clock generation of f out = f mli is enabled according to the setting of bit field dm. 1 b fractional divider is stopped. signal f out = f mli becomes inactive. no change except when writing bit field dm. in case of a conflict between hardware reset and software set of disclk, th e software set wins. any write or read-modify-write action leads to the described behavior. as a result read-modify-write operations should be avoided. 0 10, [27:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-82 v1.1, 2011-03 mli, v1.11 module identification register the mli module identification register id contains read-only information about the module version. id module identificat ion register (08 h ) reset value: 0025 c0xx h 31 16 15 8 7 0 modnum modtype modrev rrr field bits type description modrev [7:0] r module revision number this bit field defines the module revision number. the value of a module revision starts with 01 h (first revision). modtype [15:8] r module type this bit field defines the module as a 32-bit module: c0 h modnum [31:16] r module number value this bit field defines the module identification number for the mli: 0025 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-83 v1.1, 2011-03 mli, v1.11 27.4.2 general status /control registers global interrup t set register the global interrupt set register gintr is a write only register (always reads 0) that allows each of the service request outputs srx to be activated under software control (see page 27-58 ). gintr global interrupt set register (b0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 si mli7 si mli6 si mli5 si mli4 si mli3 si mli2 si mli1 si mli0 r wwwwwwww field bits type description simlix (x = 0-7) xw set mli service request output line x 0 b no action 1 b service request output srx is activated (pulse). 0 [31:8] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-84 v1.1, 2011-03 mli, v1.11 set clear register the set clear register scr is a write only regi ster that makes it possible to set or clear by software several status flags located in registers tstatr, trstatr and rcr. reading register scr always returns zeros at all bit locations. bits that are not written with a 1 have no effect. scr set clear register (94 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 c civ3 c civ2 c civ1 c civ0 c nae c tpe c rpe c av 0 c bav c mod wwwwwwww w ww 1514131211109876543210 c cv3 c cv2 c cv1 c cv0 c dv3 c dv2 c dv1 c dv0 0 s mod s cv3 s cv2 s cv1 s cv0 wwwwwwww w wwwww field bits type description scv0, scv1, scv2, scv3 0, 1, 2, 3 w set command valid 0 b no effect 1 b bit trstatr.cvx is set. smod 4w set mod flag 0 b no effect 1 b if cmod = 0, rcr is set. if cmod = 1, rcr.mod is cleared. cdv0, cdv1, cdv2, cdv3 8, 9, 10, 11 w clear data valid x flag 0 b no effect 1 b bits trstatr.dvx a nd trstatr.rpx are cleared. ccv0, ccv1, ccv2, ccv3 12, 13, 14, 15 w clear command valid x flag 0 b no effect. 1 b if scvx = 0, bit trstatr.cvx is cleared. if scvx = 1, bit trstatr.cvx is set. cmod 16 w clear mod flag 0 b no effect. 1 b bit rcr.mod is cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-85 v1.1, 2011-03 mli, v1.11 cbav 17 w clear bav flag 0 b no effect. 1 b bit trstatr.bav is cleared. cav 24 w clear av flag 0 b no effect. 1 b bit trstatr.av is cleared. crpe 25 w clear receiver pe flag 0 b no effect. 1 b bit rcr.pe is cleared. ctpe 26 w clear transmitter pe flag 0 b no effect. 1 b bit tstatr.pe is cleared. cnae 27 w clear nae flag 0 b no effect. 1 b bit tstatr.nae is cleared. cciv0, cciv1, cciv2, cciv3 28, 29, 30, 31 w clear command interrupt valid x flag 0 b no effect. 1 b bit tstatr.civx is cleared. 0 [7:5], [23:18] w reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-86 v1.1, 2011-03 mli, v1.11 output input control register the output input control register oicr determines the functionality of the mli transmitter and mli receiver i/o control logic. the bits in this register are automatically overwritten after a reset with a value given in the implementation chapter (see ). furthermore, the connection table of the mli module signals is given there. note: the value of register oi cr should not be modified while a data transfer (reception or transmission) is ongoing (bits in oicr directly control the i/o signal paths). oicr output input control register (b4 h ) reset value: 1000 8000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdp rds rce rcp rcs rvp rvs rrp d rrp c rrp b rrp a rrs rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rve tdp tcp tce tre trp trs tvp d tvp c tvp b tvp a tve d tve c tve b tve a rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description tvea, tveb, tvec, tved 0, 1, 2, 3 rw transmitter valid enable these bits enable the module kernel output signals tvalidx (x = a, b, c, d) to be driven by mli transmitter output signal tvalid. 0 b tvalidx is disabled and remains at passive level (as selected by tvpx). 1 b transmitter output signal tvalidx is enabled and driven by tvalid. tvpa, tvpb, tvpc, tvpd 4, 5, 6, 7 rw transmitter valid polarity these bits determine the polarity of the module kernel transmitter output signals tvalidx (x = a, b, c, d). 0 b non-inverted polarity fo r tvalidx selected: tvalidx is passive when driving a 0. tvalidx is active when driving a 1. 1 b inverted polarity for tvalidx selected: tvalidx is passive when driving a 1. tvalidx is active when driving a 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-87 v1.1, 2011-03 mli, v1.11 trs [9:8] rw transmitter ready selection this bit field determines the module kernel input signal treadyx (x = a, b, c, d) that is used as mli transmitter input signal tready. 00 b treadya is selected. 01 b treadyb is selected. 10 b treadyc is selected. 11 b treadyd is selected. trp 10 rw transmitter ready polarity this bit determines the polarity of treadyx. 0 b non-inverted polarity for treadyx selected: treadyx is passive if 0. treadyx is active if 1. 1 b inverted polarity for treadyx selected: treadyx is passive if 1. tready is active if 0. tre 11 rw transmitter ready enable this bit enables the mli transmitter input signal tready. 0 b tready signal is disabled (always at 0 level). 1 b tready signal is enabled and driven by treadyx according to the settings of trs and trp. tce 12 rw transmitter clock enable this bit enables the module kernel output signal tclk. 0 b tclk is disabled and remains at passive level (as selected by tcp). 1 b tclk is enabled and driven according to the setting of tcp. tcp 13 rw transmitter clock polarity this bit determines the polarity of the module kernel output clock signal tclk. 0 b non-inverted polarity for tclk selected: tclk is driving a 0 when it is passive. 1 b inverted polarity fo r tclk selected: tclk is driving a 1 when it is passive. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-88 v1.1, 2011-03 mli, v1.11 tdp 14 rw transmitter data polarity this bit determines the polarity of the module kernel output clock signal tdata. 0 b tdata is directly driven by mli transmitter output signal tdata (non-inverted). 1 b tdata is directly driven by the inverted mli transmitter output signal tdata. rve 15 rw receiver valid enable this bit enables the mli receiver input signal rvalid. 0 b rvalid signal is disabled (always at 0 level). 1 b rvalid signal is enabled and driven by rvalidx according to the settings of rvs and rvp (default after reset). rrs [17:16] rw receiver ready selector this bit field determines the module kernel output signal rreadyx (x = a, b, c, d) that is driven by the mli receiver output signal rready. the rreadyx output signals that are not selected drives a passive level according to the setting of rrpx. 00 b rreadya is selected. 01 b rreadyb is selected. 10 b rreadyc is selected. 11 b rreadyd is selected. rrpa, rrpb, rrpc, rrpd 18, 19, 20, 21 rw receiver ready polarity these bits determine the polarity of the module kernel receiver output signals rreadyx (x = a, b, c, d). 0 b non-inverted polarity for rreadyx selected: rreadyx is passive if 0. rreadyx is active if 1. 1 b inverted polarity for rreadyx selected: rreadyx is passive if 1. rreadyx is active if 0. rvs [23:22] rw receiver valid selector this bit field determines the module kernel input signal rvalidx (x = a, b, c, d) that is used as mli receiver input signal rvalid. 00 b rvalida is selected. 01 b rvalidb is selected. 10 b rvalidc is selected. 11 b rvalidd is selected. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-89 v1.1, 2011-03 mli, v1.11 rvp 24 rw receiver valid polarity this bit determines the polarity of rvalidx. 0 b non-inverted polarity for rvalidx selected: rvalidx is passive if 0. rvalidx is active if 1. 1 b inverted polarity fo r rvalidx selected: rvalidx is passive if 1. rvalidx is active if 0. rcs [26:25] rw receiver clock selector this bit field determines the module kernel input signal rclkx (x = a, b, c, d) that is used as mli receiver input clock clk. 00 b rclka is selected. 01 b rclkb is selected. 10 b rclkc is selected. 11 b rclkd is selected. rcp 27 rw receiver clock polarity this bit determines the polarity of rclkx. 0 b non-inverted polarity for rclkx selected: rclkx is at 0 level in passive state. 1 b inverted polarity fo r tclk selected: rclkx is at 1 level in passive state. rce 28 rw receiver clock enable this bit enables the mli receiver input clock rclk. 0 b rclk signal is disabled (always at 0 level). 1 b rclk signal is enabled and driven by rclkx according to the settings of rcs and rcp. rds [30:29] rw receiver data selector this bit field determines the module kernel input signal rdatax (x = a, b, c, d) that is used as mli receiver data input line rdata. 00 b rdataa is selected. 01 b rdatab is selected. 10 b rdatac is selected. 11 b rdatad is selected. rdp 31 rw receiver data polarity this bit determines the polarity of rdatax. 0 b non-inverted polarity for rdatax selected: rdatax is passive if 0. rdatax is active if 1. 1 b inverted polarity for rdatax selected: rdatax is passive if 1. rdatax is active if 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-90 v1.1, 2011-03 mli, v1.11 27.4.3 access protection registers access enable register the access enable register aer enables write and read operations in the corresponding address ranges (x = 0 to 31) in addition to the global move engine enable rcr.mod. each address range can be indivi dually enabled or excluded from automatic mode. note: please refer to the implementation chapter for the devic e specific access protection (see page 27-137 ). aer0 access enable register 0 (b8 h ) reset value: 0000 0000 h aer1 access enable register 1 (c0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 aen 31 aen 30 aen 29 aen 28 aen 27 aen 26 aen 25 aen 24 aen 23 aen 22 aen 21 aen 20 aen 19 aen 18 aen 17 aen 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 aen 15 aen 14 aen 13 aen 12 aen 11 aen 10 aen 9 aen 8 aen 7 aen 6 aen 5 aen 4 aen 3 aen 2 aen 1 aen 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description aenx (x = 0-31) xrw address range x enable this bit enables the read and write capability of the mli move engine for address range x (x = 0-31). 0 b automatic mli read and write moves to address range x are disabled. read/write moves to address range x are not executed automatically and an mli service request can be generated. the receiving controller?s software has to take care about the move. 1 b automatic mli read and write moves to address range x are enabled if rcr.mod = 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-91 v1.1, 2011-03 mli, v1.11 access range register the access range register arr determines size and number of the address sub-range n (n = 0-3). arr0 access range register 0 (bc h ) reset value: 0000 0000 h arr1 access range register 1 (c4 h ) reset value: 0000 0000 h 31 29 28 24 23 21 20 16 15 13 12 8 7 5 4 0 size3 slice3 size2 slice2 size1 slice1 size0 slice0 rw rw rw rw rw rw rw rw field bits type description slice0 [4:0] rw address slice 0 slice0 selects a specific sub-range within address sub-range 0. size0 [7:5] rw address size 0 size0 determines the sub-range size within address sub-range 0. slice1 [12:8] rw address slice 1 slice1 selects a specific sub-range within address sub-range 1. size1 [15:13] rw address size 1 size1 determines the sub-range size within address sub-range 1. slice2 [20:16] rw address slice 2 slice2 selects a specific sub-range within address sub-range 2. size2 [23:21] rw address size 2 size2 determines the sub-range size within address sub-range 2. slice3 [28:24] rw address slice 3 slice3 selects a specific sub-range within address sub-range 3. size3 [31:29] rw address size 3 size3 determines the sub-range size within address sub-range 3. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-92 v1.1, 2011-03 mli, v1.11 27.4.4 transmitter cont rol/status registers transmitter control register the transmitter control register tcr include s transmitter related control bits and bit fields that are used for parity/acknowledge, address optimization, tdata idle polarity, retry, and transmitter enable/disable control. tcr transmitter control register (10 h ) reset value: 0000 0110 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0tdel rrw 1514131211109876543210 tp no mdp mnae mpe 0 0 dnt mod rw rw rw rwh rwh r rw rw rw field bits type description mod 0rw mode of operation this bit enables the mli transmitter. 0 b the mli transmitter is disabled. 1 b the mli transmitter is enabled. dnt 1rw data in not transmission this bit determines the level of the transmitter data line tdata when no transmission is in progress. 0 b tdata is at low level if no transmission is running. 1 b tdata is at high level if no transmission is running. 0 2rw reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-93 v1.1, 2011-03 mli, v1.11 mpe [7:4] rwh maximum parity errors this bit field determines the maximum number of transmitter parity error conditions that can be still detected until a transmitter parity error event is generated (see page 27-44 ). with each condition detected, mpe is decremented down to 0. 0000 b a parity error event is generated if a transmitter parity error condition is detected. 0001 b a parity error event is generated if a transmitter parity error condition is detected. 0010 b a parity error event is generated if 2 transmitter parity error conditions are detected. 0011 b a parity error event is generated if 3 transmitter parity error conditions are detected. ? b ? 1110 b a parity error event is generated if 14 transmitter parity error conditions are detected. 1111 b a parity error event is generated if 15 transmitter parity error conditions are detected. mnae [9:8] rwh maximum non acknowledge errors this bit field determines the maximum number of consecutive non-acknowledge error conditions that can be still detected in the transmitter until a time-out event is generated. mnae is decremented down to 0 at each non-acknowledge error condition. when mnae = 0 or becoming 0, a time-out event is generated. mnae is automatically set to 11 b after a successful frame transmission (see page 27-47 ). 00 b a time-out event is generated if a non-ack condition is detected. 01 b a time-out event is generated if a non-ack condition is detected. 10 b a time-out event is generated if 2 consecutive non-ack conditions are detected. 11 b a time-out event is generated if 3 consecutive non-ack conditions are detected. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-94 v1.1, 2011-03 mli, v1.11 mdp [13:10] rw maximum delay for parity error this bit field determines a window for the transmitter in number of tclk clock periods where a tready low- to-high signal transition signal is considered as ?correctly received? condition (see page 27-22 ). 0000 b zero clock periods selected (not useful) 0001 b 1 clock period selected ? b ? 1110 b 14 clock periods selected 1111 b 15 clock periods selected no 14 rw no optimized method this bit field enables/disables the address prediction for read or write frames (see page 27-47 ). 0 b optimized method (address prediction) enabled. 1 b optimized method (address prediction) disabled. tp 15 rw type of parity this bit will determines the ty pe of parity used in frame transmissions. for correct data transfers, tp = 0 has to be programmed. the value tp = 1 can be selected to force parity errors to analyze the propagation delay (see page 27-26 ). 0 b even parity is selected. 1 b odd parity selected. tdel [19:16] rw transmission delay this bit field defines a delay in cycles of f fpi of the transmitter between the reception of the rising edge of rready and the next possible frame start (see page 27-50 ). 0000 b no transmission delay selected 0001 b one f fpi cycle delay selected ... b ... 1110 b fourteen f fpi cycles delay selected 1111 b fifteen f fpi cycles delay selected 0 3, [31:20] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-95 v1.1, 2011-03 mli, v1.11 transmitter status register the transmitter status register tstatr contains transmitter specific status information. tstatr transmitter status register (14 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 nae pe apn rdc rrhrhrhrh field bits type description rdc [4:0] rh ready delay counter this bit field counts tclk periods after the end of a frame transmission. when the tvalid signal goes to low level, rdc is cleared to zero and starts counting up the tclk clock periods until a tready high level is detected (see page 27-22 ). apn [6:5] rh answer pipe number this bit field is written by the mli receiver with the pipe number of a received read frame. apn is used by an answer frame that is transmitted as response to the read frame. 00 b pipe 0 is used in answer frame. 01 b pipe 1 is used in answer frame. 10 b pipe 2 is used in answer frame. 11 b pipe 3 is used in answer frame. pe 7rh parity error flag this bit is set if a transmitter parity error condition is detected by the transmitter after a frame transmission. pe is cleared by hardware when a frame has been transmitted without a parity error (see page 27-44 ). bit pe can be cleared by software via bit scr.ctpe. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-96 v1.1, 2011-03 mli, v1.11 nae 8rh non acknowledge error flag this bit is set when a non-acknowledge error condition is detected by the mli transmitter after a frame transmission (see page 27-47 ). nae is cleared by hardware if a transmitted frame has been acknowledged correctly. bit nae can be cleared by software via bit scr.cnae. 0 [31:9] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-97 v1.1, 2011-03 mli, v1.11 transmitter pipe x status registers the transmitter pipe x status registers tpxstatr contain pipe-specific status information related to address optimization and prediction, data width for transmit data, and remote window size. tpxstatr (x = 0-3) transmitter pipe x status register (18 h +4 h *x) reset value: 0000 0000 h 31 17 16 15 6 5 4 3 0 0 o p ap dw bs rrhrhrhrh field bits type description bs [3:0] rh buffer size this bit field indicates the coded buffer size of the pipe x remote window in the receiving controller. bs further determines how many address offset bits are transmitted in a write offset and data frame or in a discrete read frame. when r egister tpxbar is written for generation of a copy base address frame, bs is updated by the copy base address frame (see page 27-28 ). 0000 b 1-bit offset address of remote window 0001 b 2-bit offset address of remote window 0010 b 3-bit offset address of remote window ... b ... 1110 b 15-bit offset address of remote window 1111 b 16-bit offset address of remote window dw [5:4] rh data width this bit field indicates the data width that has been detected for a read or write access of a bus master to a transfer window of pipe x (see page 27-30 and page 27-34 ). 00 b 8-bit data width detected 01 b 16-bit data width detected 10 b 32-bit data width detected 11 b reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-98 v1.1, 2011-03 mli, v1.11 ap [15:6] rh address prediction factor this bit field indicates the delta value (positive or negative number) of offset address used by the mli transmitter for the next address prediction. ap is a signed 9-bit number (10th bit is the sign bit) that is written with each transmitter address prediction calculation (see page 27-26 and page 27-47 ). op 16 rh use optimized frame when address optimization is enabled with tcr.no = 0, this bit indicates if address prediction is possible in the transmitter. op is written with each transmitter address prediction calculation (see page 27-26 and page 27-47 ). 0 b no address prediction is possible. a write offset and data frame or a discrete read frame are used for transmission. 1 b address prediction is possible. an optimized write frame or an optimized read frame are used for transmission. 0 [31:17] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-99 v1.1, 2011-03 mli, v1.11 transmitter command register the transmitter command register tcmdr contains the command codes that are used during command frame transmission (see page 27-41 ). each time one of the cmdpx bit fields is written, a command frame tr ansmission is triggered. independent of the transferred command code value, a command frame transmitted event can be generated in the transmitter for each pipe and a command frame received event for each pipe in the receiver, respectively. tcmdr transmitter command register (28 h ) reset value: 0000 0000 h 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 0cmdp30cmdp20cmdp10cmdp0 rrwrrwrrwrrw field bits type description cmdp0 [3:0] rw command code for pipe 0 this bit field contains the command code related to pipe 0. the pipe 0 command codes allow an activation (pulse) of one of the service request outputs sr[3:0] in the receiving controller. 0001 b activate sr0 0010 b activate sr1 0011 b activate sr2 0100 b activate sr3 other bit combinations are reserved for future use; no further action in the receiver. cmdp1 [11:8] rw command code for pipe 1 this bit field contains the command code related to pipe 1. the pipe 1 command codes allow to adjust the receiver delay for the parity error condition (see rcr.dpe) in the mli receiver of the receiving controller. 0000 b set rcr.dpe = 0000 b 0001 b set rcr.dpe = 0001 b ... b ... 1110 b set rcr.dpe = 1110 b 1111 b set rcr.dpe = 1111 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-100 v1.1, 2011-03 mli, v1.11 cmdp2 [19:16] rw command code for pipe 2 this bit field contains the command code related to pipe 2. the pipe 2 command codes allow to control the mli receiver in the receiving controller. 0001 b enable automatic data mode (rcr.mod = 1) 0010 b disable automatic data mode (rcr.mod = 0) 0100 b clear bit trstatr.rp0 0101 b clear bit trstatr.rp1 0110 b clear bit trstatr.rp2 0111 b clear bit trstatr.rp3 1111 b activate a pulse at brkout other bit combinations are reserved for future use; no further action in the receiver. cmdp3 [27:24] rw command code for pipe 3 this bit field contains the command code related to pipe 3. the command codes for pipe 3 are free programmable by software. 0 [7:4], [15:12], [23:20], [31:28] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-101 v1.1, 2011-03 mli, v1.11 transmitter-receiver status register the transmitter receiver status register trstatr contains read-only flags that indicate the status of mli operations. trstatr transmitter receiver status register (2c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 pn rp3 rp2 rp1 rp0 dv3 dv2 dv1 dv0 r rh rhrhrhrhrhrhrhrh 1514131211109876543210 0 bav av cv3 cv2 cv1 cv0 civ3 civ2 civ1 civ0 r rhrhrhrhrhrhrhrhrhrh field bits type description civ0, civ1, civ2, civ3 0, 1, 2, 3 rh command interrupt valid bit is set to 1 by the mli transmitter whenever it detects a rising edge at the corresponding trx input line (for triggered command frames in pipe 0). it is cleared by hardware when the command frame has been correctly transmitted. civx can be cleared by software via bit scr.ccivx. cv0, cv1, cv2, cv3 4, 5, 6, 7 rh command valid bit is set by hardware when a tcmdr.cmdpx bit field is written. it is cleared by hardware when the command frame has been correctly tr ansmitted. cvx can be set or cleared by software via bits scr.scvx or scr.ccvx. av 8rh answer valid bit is set by hardware when the tdrar register in the the mli transmitter (in t he remote controller) is written. av is cleared by hardware when the answer frame has been correctly sent. av can be cleared by software via bit scr.cav. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-102 v1.1, 2011-03 mli, v1.11 bav 9rh base address valid bit is set by hardware when the tcbar register in the mli transmitter is written. bav is cleared by hardware when the copy base address frame has been correctly sent. bav can be cleared by software via bit scr.cbav. dv0, dv1, dv2, dv3 16, 17, 18, 19 rh data valid bit is set by hardware when the tpxdatar and/or the tpxaofr registers of the mli transmitter are updated after a read or write access to a transfer window of pipe x. dvx is cleared again by hardware when the read or write frame has been correctly sent. dvx can be cleared by software via bit scr.cdvx. rp0, rp1, rp2, rp3 20, 21, 22, 23 rh read pending bit is set by hardware when the tpxaofr register of the mli transmitter is updated after a read access to a transfer window of pipe x. rpx is cleared by hardware when the mli receiver in the local controller receives an answer frame for pipe x from the remote controller. rpx can be cleared by software via bit scr.cdvx. pn [25:24] rh pipe number this bit field indicates the pipe number x of the base address that has been written into register tpxbar. 00 b tp0bar has been last written. 01 b tp1bar has been last written. 10 b tp2bar has been last written. 11 b tp3bar has been last written. 0 [15:10], [31:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-103 v1.1, 2011-03 mli, v1.11 27.4.5 transmitter pipe x address offset register transmitter pipe x address offset register the transmitter pipe x address offset regist er tpxaofr is a read-only register that stores the offset address that has been used by the last read or write access to a transfer window of pipe x. tpxaofr (x = 0-3) transmitter pipe x address offset register (30 h +4 h *x) reset value: 0000 0000 h 31 16 15 0 0aoff rrh field bits type description aoff [15:0] rh address offset whenever a location within a transfer window is accessed (read or written) aoff is loaded with the lowest 16 address bits of the access. also in the case of a small transfer window access, all aoff bits are loaded, but aoff[15:13] are not taken into account for further actions assuming the buffer size is configured correctly (see page 27-105 ). 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-104 v1.1, 2011-03 mli, v1.11 transmitter pipe x data register the transmitter pipe x data register tpxdatar is a read-only register that stores the data that has been written during the last write access to a transfer window of pipe x. transmitter data read answer register the transmitter data read answer regist er tdrar contains the read data for the transmission of an answer frame. tpxdatar (x = 0-3) transmitter pipe x data register (40 h +4 h *x) reset value: 0000 0000 h 31 0 data rh field bits type description data [31:0] rh data whenever a location within a transfer window is written, the data is loaded in this bit field. tdrar transmitter data read answer register (50 h ) reset value: 0000 0000 h 31 0 data rwh field bits type description data [31:0] rwh data this bit field is loaded with data that is read from the address requested by a read frame. an update of this bit field triggers the start of an answer frame with data used as content of the answer frame. this bit field can be updated either automatically by the move engine (if automatic data mode is enabled) or by the cpu (if automatic data mode is disabled). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-105 v1.1, 2011-03 mli, v1.11 transmitter pipe x base address register the write-only transmitter pipe x base address register tpxbar represents the 28-bit pipe x remote window base address and the remote window size that is transmitted to the receiving controller via a copy base address frame. tpxbar (x = 0-3) transmitter pipe x base address register (54 h +4 h *x) reset value: 0000 0000 h 31 43 0 addr bs ww field bits type description bs [3:0] w buffer size this bit field determines the coded buffer size of the pipe x remote window in the receiving controller. when writing tpxbar, bs is copied into bit field tpxstatr.bs. 0000 b 1-bit offset address of remote window 0001 b 2-bit offset address of remote window 0010 b 3-bit offset address of remote window ... b ... 1101 b 14-bit offset address of remote window 1110 b 15-bit offset address of remote window 1111 b 16-bit offset address of remote window do not use the coding values 1101 b , 1110 b , and 1111 b as buffer size for small transfer windows. addr [31:4] w address this bit field determines the most significant 28 bits of the pipe x remote window base address. when writing tpxbar, addr is copied into bit field tcbar.addr[31:4]. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-106 v1.1, 2011-03 mli, v1.11 transmitter copy base address register the transmitter copy base address register tcbar contains the 28-bit pipe x remote window base address of the latest write access to tpxbar.addr. tcbar transmitter copy base address register (64 h ) reset value: 0000 0000 h 31 43 0 addr 0 rh r field bits type description addr [31:4] rh address this bit field contains the 28 address bits written to tpxbar.addr. this value will be transferred to the receiving controller to define the base address of the remote window for pipe x. 0 [3:0] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-107 v1.1, 2011-03 mli, v1.11 27.4.6 transmitter in terrupt registers transmitter interrupt enable register the transmitter interrupt enable register tier contains the interrupt enable bits and the clear bits for all transmitter events. the bits marked w always read as 0. tier transmitter interrupt enable register (98 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 te ir pe ir cfs ir3 cfs ir2 cfs ir1 cfs ir0 nfs ir3 nfs ir2 nfs ir1 nfs ir0 r wwwwwwwwww 1514131211109876543210 0 te ie pe ie cfs ie3 cfs ie2 cfs ie1 cfs ie0 nfs ie3 nfs ie2 nfs ie1 nfs ie0 r rwrwrwrwrwrwrwrwrwrw field bits type description nfsie0, nfsie1, nfsie2, nfsie3 0, 1, 2, 3 rw normal frame sent in pipe x interrupt enable 0 b normal frame sent in pipe x event is disabled for activation of an srx line. 1 b normal frame sent in pipe x event is enabled for activation of an srx line. cfsie0, cfsie1, cfsie2, cfsie3 4, 5, 6, 7 rw command frame sent in pipe x interrupt enable 0 b command frame sent in pipe x event is disabled for activation of an srx line. 1 b command frame sent in pipe x event is enabled for activation of an srx line. peie 8rw parity error interrupt enable 0 b parity error event is disabled for activation of an srx line. 1 b parity error event is enabled for activation of an srx line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-108 v1.1, 2011-03 mli, v1.11 teie 9rw time-out error interrupt enable 0 b time-out error event is disabled for activation of an srx line. 1 b time-out error event is enabled for activation of an srx line. nfsir0, nfsir1, nfsir2, nfsir3 16, 17, 18, 19 w normal frame sent in pipe x flag clear 0 b no action. 1 b clear tisr.nfsix. cfsir0, cfsir1, cfsir2, cfsir3 20, 21, 22, 23 w command frame sent in pipe x flag clear 0 b no action. 1 b clear tisr.cfsix. peir 24 w parity error flag clear 0 b no action. 1 b clear tisr.peix. teir 25 w time out error flag clear 0 b no action. 1 b clear tisr.teix. 0 [15:10], [31:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-109 v1.1, 2011-03 mli, v1.11 transmitter interrupt register the transmitter interrupt status register tisr contains all mli event (or interrupt) flags of the mli transmitter. these flags can be cleared by software when writing the appropriate bits in the tier register ; they are not cleared by hardware. tisr transmitter interrupt status register (9c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 te i pe i cfs i3 cfs i2 cfs i1 cfs i0 nfs i3 nfs i2 nfs i1 nfs i0 r rhrhrhrhrhrhrhrhrhrh field bits type description nfsi0, nfsi1, nfsi2, nfsi3 0, 1, 2, 3 rh normal frame sent in pipe x flag the service request output that can be activated is defined by tinpr.nfsipx. 0 b a normal frame has not yet been sent. 1 b a write or read frame has been correctly sent and acknowledged for pipe x. cfsi0, cfsi1, cfsi2, cfsi3 4, 5, 6, 7 rh command frame sent in pipe x flag the service request output that can be activated is defined by tinpr.cfsip. 0 b a command frame has not yet been sent. 1 b a command frame has been correctly sent and acknowledged for pipe x. pei 8rh parity error flag the service request output that can be activated is defined by tinpr.pteipx. 0 b a parity error event has not yet been detected. 1 b a parity error event has been detected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-110 v1.1, 2011-03 mli, v1.11 tei 9rh time-out error flag the service request output that can be activated is defined by tinpr.pteipx. 0 b a time-out error event has not yet been detected. 1 b a time-out error event has been detected. 0 [31:10] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-111 v1.1, 2011-03 mli, v1.11 transmitter interrupt node pointer register the transmitter interrupt node pointer register tinpr contains the node pointers for the mli transmitter events. tinpr transmitter interrupt node pointer register (a0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 pteip 0 cfsip rrwrrw 1514131211109876543210 0nfsip30nfsip20nfsip10nfsip0 rrwrrwrrwrrw field bits type description nfsip0 [2:0] rw normal frame sent in pipe 0 interrupt pointer this bit field determines which service request output srx becomes active when a normal frame sent in pipe 0 event occurs (if enabled). 000 b the service request output sr0 is selected. 001 b the service request output sr1 is selected. ? b ? 110 b the service request output sr6 is selected. 111 b the service request output sr7 is selected. nfsip1 [6:4] rw normal frame sent in pipe 1 interrupt pointer this bit field determines which service request output srx becomes active when a normal frame sent in pipe 1 event occurs (if enabled). coding see nfsip0. nfsip2 [10:8] rw normal frame sent in pipe 2 interrupt pointer this bit field determines which service request output srx becomes active when a normal frame sent in pipe 2 event occurs (if enabled). coding see nfsip0. nfsip3 [14:12] rw normal frame sent in pipe 3 interrupt pointer this bit field determines which service request output srx becomes active when a normal frame sent in pipe 3 event occurs (if enabled). coding see nfsip0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-112 v1.1, 2011-03 mli, v1.11 cfsip [18:16] rw command frame sent interrupt pointer this bit field determines which service request output srx becomes active when a command frame sent event occurs (if enabled). coding see nfsip0. pteip [22:20] rw parity or time out interrupt pointer this bit field determines which service request output srx becomes active when a parity/time-out event occurs (if enabled). coding see nfsip0. 0 3, 7, 11, 15, 19, [31:23] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-113 v1.1, 2011-03 mli, v1.11 27.4.7 receiver control/status registers receiver control register the receiver control register rcr contains control and status bits/bit fields that are related to the mli receiver operation. bit rcvrst is automatically overwritten after a reset (see page 27-68 ) with a value given in the implementation chapter (see page 27-130 ). rcr receiver control register (68 h ) reset value: 0100 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 rcv rst 0ben mpe r rw r rw rwh 1514131211109876543210 rpn pe tf dw mod cmdp3 dpe rh rh rh rh rh rh rh field bits type description dpe [3:0] rh delay for parity error dpe determines the number of rclk clock periods that the mli receiver waits before the rready signal is raised again when it has detected a parity error (see page 27-22 ). when a pipe 1 command frame is received by the mli receiver, the command code is stored in this bit field (see page 27-41 ). 0000 b zero rclk clock period delay is selected. 0001 b one rclk clock period delay is selected. 0010 b two rclk clock periods delay is selected. ... b ... 1110 b fourteen rclk clock periods delay is selected. 1111 b fifteen rclk clock periods delay is selected. cmdp3 [7:4] rh command from pipe 3 when a pipe 3 command frame is received by the mli receiver, the command code is stored in this bit field. pipe 3 commands are free for software use. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-114 v1.1, 2011-03 mli, v1.11 mod 8rh mode of operation this bit determines the data transfer operation mode of the mli receiver. bit mod can be set by hardware with the reception of a pipe 2 command frame (see page 27-100 ). it can be set or cleared by software via bits scr.smod or scr.cmod. 0 b automatic data mode is disabled. data read/write operations from/to a remote window must be executed by a bus master (e.g. the cpu). 1 b automatic data mode is enabled. data read/write operations from/to a remote window are executed by the mli?s move engine. dw [10:9] rh data width this bit field is updated by the mli receiver whenever new data is received in the rdatar register. it indicates the relevant data width. 00 b 8-bit relevant data width in rdatar 01 b 16-bit relevant data width in rdatar 10 b 32-bit relevant data width in rdatar 11 b reserved tf [12:11] rh type of frame this bit field determines the frame type that has most recently been received by the mli receiver. it is updated whenever the mli receiver updates rdatar, raddr, or rpxbar. the most recently received frame was a: 00 b copy base address frame 01 b discrete read frame or optimized read frame 10 b write offset and data frame or optimized write frame 11 b answer frame note that the coding of tf is different from the frame coding as defined in table 27-1 on page 27-11 . pe 13 rh parity error pe is set when a parity error is detected in a received frame (see page 27-44 ). pe is cleared by hardware when a frame has been received without parity error. pe can be cleared by software via bit scr.crpe. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-115 v1.1, 2011-03 mli, v1.11 rpn [15:14] rh received pipe number this bit field contains the pipe number that was indicated by the pipe number bit field of the latest received frame. it is updated by any received frame. mpe [19:16] rwh maximum parity errors this bit field indicates the number of receive parity error conditions after which a receiver parity error event will be generated. it is set to a desired value by software and it is decremented down to 0 automatically by the mli each time it detects a receiver parity error condition. if a receiver parity error condition is detected and mpe becomes 0 or is already 0, a receiver parity error event is generated (see page 27-44 ). 0000 b a receiver parity event is generated if a receiver error condition is detected. 0001 b a receiver parity event is generated if a receiver error condition is detected. 0010 b a receiver parity event is generated if 2 receiver error conditions are detected. ? b ? 1110 b a receiver parity event is generated if 14 receiver error conditions are detected. 1111 b a receiver parity event is generated if 15 receiver error conditions are detected. ben 20 rw break out enable when setting ben = 1, the mli receiver generates a pulse on its break output signal brkout when a pipe 2 command frame with command code cmd = 1111 b is received. 0 b break output signal generation is disabled. 1 b break output signal is enabled. rcvrst 24 rw receiver reset this bit forces the receiver to be reset in order to be able to change oicr settings without affecting the receiver registers. 0 b the mli receiver is in operating mode. 1 b the mli receiver is held in reset state and oicr can be modified without unintentional actions in the receiver. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-116 v1.1, 2011-03 mli, v1.11 receiver pipe x status register the receiver pipe x status register rpxsta tr indicates the coded buffer size which represents the remote window size of 2 bytes to 64 kbytes and the address prediction factor that has been calculated for pipe x in the receiving controller. 0 [23:21], [31:25] r reserved read as 0; should be written with 0. rpxstatr (x = 0-3) receiver pipe x status register (7c h +4 h *x) reset value: 0000 0000 h 31 16 15 6 5 4 3 0 0ap0bs rrhrrh field bits type description bs [3:0] rh buffer size this bit field indicates the size of pipe x remote window in the receiving controller. it is updated by hardware when a copy base address frame has been received (see page 27-28 ). 0000 b 1-bit offset address of remote window 0001 b 2-bit offset address of remote window 0010 b 3-bit offset address of remote window ... b ... 1110 b 15-bit offset address of remote window 1111 b 16-bit offset address of remote window ap [15:6] rh address prediction factor ap contains the address prediction factor that has been calculated for pipe x in the receiving controller. it is a signed 9-bit number with the sign in its most significant bit (see page 27-47 ). 0 [5:4], [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-117 v1.1, 2011-03 mli, v1.11 27.4.8 receiver address/data registers receiver pipe x base address register the receiver pipe x base address regist er rpxbar is a read-only register that contains the complete target address in the remote window of pipe x. rpxbar (x = 0-3) receiver pipe x base address register (6c h +4 h *x) reset value: 0000 0000 h 31 0 addr rh field bits type description addr [31:0] rh address addr indicates the complete target address for the pipe x remote window. if a pipe x copy base address frame is received, addr[31:4] becomes loaded with the transmitted 28-bit address and bits [3:0] are cleared. if a write or read frame with m bits of address offset is received, bits addr[31:m] are held constant and bits addr[m-1:0] are replaced by the received offset. if an optimized read or data frame is received, the address prediction mechanism adds the predicted address offset rpxstatr.ap to addr and stores the result in addr. if an answer frame is received, addr is not changed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-118 v1.1, 2011-03 mli, v1.11 receiver address register the receiver address register radrr is a read-only register storing the complete address of the most recently (or currently) targeted remote window. radrr receiver address register (8c h ) reset value: 0000 0000 h 31 0 addr rh field bits type description addr [31:0] rh address addr indicates the complete target address for the most recently (or currently) targeted remote window (pipe x). if a copy base address frame is received, addr is unchanged. if a write or read frame with m bits of address offset is received, bits addr[31:m] replaced by the bits rpxbar.addr[31:m] and bits addr[m-1:0] are replaced by the received offset. if an optimized read or data frame is received, the address prediction mechanism adds the predicted address offset rpxstatr.ap to rpxbar.addr and stores the result in addr. if an answer frame is received, addr becomes invalid. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-119 v1.1, 2011-03 mli, v1.11 receiver data register the receiver data register rdatar is a re ad-only register that stores data received by a write frame or an answer frame. rdatar receiver data register (90 h ) reset value: 0000 0000 h 31 0 data rh field bits type description data [31:0] rh data in the receiving controller, data contains the data received by a write frame or an answer frame. bit field rcr.dw determines the width of the relevant data that is stored in rdatar. rcr.dw = 00 b : rdatar[7:0] are relevant (8-bit) rcr.dw = 01 b : rdatar[15:0] are relevant (16-bit) rcr.dw = 10 b : rdatar[31:0] are relevant (32-bit) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-120 v1.1, 2011-03 mli, v1.11 27.4.9 receiver in terrupt registers receiver interrupt enable register the receiver interrupt enable register rier contains the interrupt enable bits and the clear bits for all receiver events. the bits marked w are always read as 0. rier receiver interrupt enable register (a4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 dra ir mpe ir pe ir ice r cfr ir3 cfr ir2 cfr ir1 cfr ir0 me ir nfr ir r wwwwwwwwww 1514131211109876543210 0 dra ie m peie peie ice cfr ie3 cfr ie2 cfr ie1 cfr ie0 nfr ie r rwrwrwrwrwrwrwrw rw field bits type description nfrie [1:0] rw normal frame received interrupt enable this bit field defines if an srx output is activated if a normal frame is co rrectly received. 00 b the srx activation is disabled. 01 b the selected srx line is activated each time a normal frame is correctly received. 10 b the selected srx line is activated each time a normal frame is correctly received that is not handled automatically by the mli move engine (e.g. an answer frame). 11 b reserved cfrie0, cfrie1, cfrie2, cfrie3 2, 3, 4, 5 rw command received in pipe x interrupt enable this bit determines if an srx output is activated if a command frame for pipe x has been received correctly. 0 b command received in pipe x event is disabled for activation of an srx line. 1 b command received in pipe x event is enabled for activation of an srx line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-121 v1.1, 2011-03 mli, v1.11 ice 6rw interrupt command enable this bit determines if an srx output line is activated if a command frame is received in pipe 0. 0 b command frame received in pipe 0 event is disabled for activation of an srx line. 1 b command frame received in pipe 0 event is enabled for activation of an srx line. peie 7rw parity error interrupt enable this bit determines if an srx output line is activated if receiver a parity error event is detected. 0 b parity error event is disabled for activation of an srx line. 1 b parity error event is enabled for activation of an srx line. mpeie 8rw memory access protection interrupt enable this bit determines if an srx output line is activated if a memory access protection error is detected. 0 b memory access protection error event is disabled for activation of an srx line. 1 b memory access protection error event is enabled for activation of an srx line. draie 9rw discarded read answer interrupt enable this bit determines if an srx output line is activated if a discarded read answer frame condition is detected. 0 b discarded read answer event is disabled for activation of an srx line. 1 b discarded read answer event is enabled for activation of an srx line. nfrir 16 w normal frame received interrupt flag clear 0 b no action. 1 b clear risr.nfri. meir 17 w mli move engine in terrupt flag clear 0 b no action. 1 b clear risr.mei. cfrir0, cfrir1, cfrir2, cfrir3 18, 19, 20, 21 w command frame received in pipe x interrupt flag clear 0 b no action. 1 b clear risr.cfrix. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-122 v1.1, 2011-03 mli, v1.11 icer 22 w interrupt command flag clear 0 b no action. 1 b clear risr.ice. peir 23 w parity error inte rrupt flag clear 0 b no action. 1 b clear risr.pei. mpeir 24 w memory protection erro r interrupt flag clear 0 b no action. 1 b clear risr.mpei. drair 25 w discarded read answer interrupt flag clear 0 b no action. 1 b clear risr.drai. 0 [15:10], [31:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-123 v1.1, 2011-03 mli, v1.11 receiver interrupt status register the receiver interrupt status register risr contains all event (interrupt) flags of the mli receiver. these flags can be cleared by software when writing the appropriate bits in the rier register; they are not cleared by hardware. risr receiver interrupt status register (a8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 drai mpei pei ic cfr i3 cfr i2 cfr i1 cfr i0 me i nfr i r rhrhrhrhrhrhrhrhrhrh field bits type description nfri 0rh normal frame received interrupt flag this flag is set when a write or a read frame has been received. the service request output that is activated is defined by rinpr.nfrip. mei 1rh mli move engine interrupt flag this flag is set when the move engine has finished an operation (read or write, depending on received frame). the service request output that is activated is defined by rinpr.mppeip. cfri0, cfri1, cfri2, cfri3 2, 3, 4, 5 rh command frame received in pipe x interrupt flag this flag is set when a command frame has been received in pipe x. the service request output that is activated is defined by rinpr.cfrip. ic 6rh interrupt command flag this flag is set when a command frame has been received in pipe 0 leading to an activation of one of the service request outputs sr[3:0]. the service request output that is activated is defined by the received command cmd. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-124 v1.1, 2011-03 mli, v1.11 pei 7rh parity error interrupt flag this flag is set when a parity error event has occurred. the service request output that is activated is defined by rinpr.mppeip. mpei 8rh memory protection error interrupt flag this flag is set when a memory protection event has occurred. the service request output that is activated is defined by rinpr.mppeip. drai 9rh discarded read answer interrupt flag this flag is set when the discarded read answer event has occurred. this condition occurs if an answer frame is received while none of the trstatr.rpx bits is set (the answer frame was not expected). the service request output that is activated is defined by rinpr.draip. 0 [31:10] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-125 v1.1, 2011-03 mli, v1.11 receiver interrupt no de pointer register the receiver interrupt node pointer register rinpr contains the node pointers for the mli receiver events. rinpr receiver interrupt no de pointer register (ac h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 draip 0 mppeip 0 cfrip 0 nfrip rrwrrwrrwrrw field bits type description nfrip [2:0] rw normal frame received interrupt pointer this bit field determines which service request output srx becomes active when a normal frame received event occurs. 000 b the service request output sr0 is selected. 001 b the service request output sr1 is selected. ? b ? 110 b the service request output sr6 is selected. 111 b the service request output sr7 is selected. cfrip [6:4] rw command frame received interrupt pointer this bit field determines which service request output srx becomes active when a command frame received event occurs. coding see nfrip. mppeip [10:8] rw memory protection or parity error interrupt pointer this bit field determines which service request output srx becomes active when a memory protection/parity error event occurs. coding see nfrip. draip [14:12] rw discarded read answer interrupt pointer this bit field determines which service request output srx becomes active when a discarded read answer event occurs. coding see nfrip. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-126 v1.1, 2011-03 mli, v1.11 0 3, 7, 11, [31:15] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-127 v1.1, 2011-03 mli, v1.11 27.5 implementation of the mli0/mli1 in TC1798 this section describes the mli0/mli1 module related external functions such as port connections, interrupt and service request control, connections to other on-chip modules, clock control, and the address map. 27.5.1 interfaces of the mli modules each mli module is supplied with separate clock control, address decoding, and interrupt control logic. four (for mli0) and two (for mli1) of the eight module service request outputs are connected to service re quest nodes. four service request outputs of each mli module are connected as dma request to with the dma controller. the data, clock, and control lines of each mli receiver and transmitter are connected to gpio lines. alternate functions of port 1 and port 5 lines are assigned to the mli0 module i/o lines while alternate functions of port 8 lines are assigned to the mli0 module i/o lines. additionally, within one mli module transmitter and receiver signals can be dynamically connected among each other with out using pins; this is useful for test purposes. figure 27-52 and figure 27-53 show how the mli0 and mli1 modules are interconnected to port lines and other on-chip functional blocks. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-128 v1.1, 2011-03 mli, v1.11 figure 27-52 mli0 module implementation and interconnections when programming the mli0_oicr register, the following additional items must be considered: ? unused transmitter/receiver output lines with index ?c? (tvalidc and rreadyc) are not connected. ? unused transmitter/receiver input lines with index ?c? (treadyc, rclkc, rvalidc, and rdatac) are connected to low level. sr[3:0] f ml i 0 address decoder interrupt control clock control to dma sr[7:4] port 1 control p1.5 / tready0a port 5 control treadya tclk treadyd tvalida tvalidd tdata transmitter recei ver rclka rclkd rreadya rreadyd rvalida rvalidd rdataa rdatab treadyb rreadyb rvalidb rdatad tvalidb rclkb mli0 module (kernel) mca05906_mod p1.4 / tclk0 p1.3 / tready0b p1.6 / tvalid0a p1.7 / tdata0 p1.8 / rclk0a p1.9 / rready0a p1.10 / rvalid0a p1.11 / rdata0a p1.13 / rclk0b p1.14 / rvalid0b p1.15 / rdata0b p5.4 / rready0b p5.6 / tvalid0b f dma brkout cerberus a2 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 tr[3:0] v ss www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-129 v1.1, 2011-03 mli, v1.11 figure 27-53 mli1 module implementation and interconnections when programming the mli1_oicr register, the following additional items must be considered: ? lines with index ?b? (not shown in the figure above) ? unused transmitter/receiver output lines tvalidb and rreadyb are not connected. ? unused transmitter/receiver input lines treadyb, rclkb, rvalidb, and rdatab are connected to low level. ? lines with index ?c? (not shown in the figure above) ? unused transmitter/receiver output lines tvalidc and rreadyc are reserved for emulation purposes. ? unused transmitter/receiver input lines treadyc, rclkc, rvalidc, and rdatac are reserved for emulation purposes and should not be selected during normal operation of the TC1798. see also page 27-133 for additional details on i/o line control and function. interrupt control mca05907_mod port 8 control sr[1:0] f ml i 1 address decoder clock control not connected treadya mli1 module (kernel) tclk sr[3:2] treadyd tvalida tvalidd tdata transmitter recei ver rclka rclkd rreadya rreadyd rvalida rvalidd rdataa rdatad to dma sr[7:4] brkout p8.0 / tclk1 p8.1 / tready1a p8.2 / tvalid1a p8.3 / tdata1 p8.4 / rclk1a p8.5 / rready1a p8.6 / rvalid1a p8.7 / rdata1a f dma cerberus a2 a1 a1 a1 a1 a2 a2 a2 tr[3:0] v ss www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-130 v1.1, 2011-03 mli, v1.11 27.5.2 mli module external registers figure 27-54 summarizes the module related exter nal registers that are required for mli0/mli1 programming. details on mli0/mli1 related register settings are shown in the following sections. figure 27-54 mli0/mli1 implementation-specific special function registers 27.5.2.1 automatic register overwrite the following values are applied after reset (see page 27-68 ). ? oicr = 1000 8000 h ; setting ?a? is selected ? rcr.rcvrst = 0: the receiver is enabled for reception. p1_iocr0 mca05908_mod dma_mli0srcx interrupt registers p1_iocr4 p1_iocr8 port registers clock control register dma_mli1srcy x = 3-0 y = 1-0 dma_clc p1_iocr12 p1_pdr p5_iocr4 p5_pdr p8_iocr0 p8_iocr4 p8_pdr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-131 v1.1, 2011-03 mli, v1.11 27.5.3 module clock generation the module clock generation configuration for the two mli modules is shown in figure 27-55 . figure 27-55 clock configuration of the mli modules the dma controller and the two mli modules (mli0 and mli1) are supplied from a common module clock f dma , that has t he frequency of t he system clock f fpi ) and is controlled via the dma_clc clock control register. the mli modules do not have its own clock control registers. its module clocks f mli0 and f mli1 are derived from f dma by two separate fractional divider registers, mli0_fdr and mli1_fdr (description see page 27-79 ). output signal can_int_o15 of the multican module can be used for external clock enable control of the fractional divider. ? f dma this is the module clock used inside the mli kernels for control purposes such as for clocking of control logic and register operations. the clock control register dma_clc makes it possible to enable/disable f dma under certain conditions. dma_clc is described in the dma chapter of this document. ? f mli0 and f mli1 this clock is the module clock used in the mli kernels as base for the shift clock and therefore determines the baud rate of the synchronous serial data transmission. the fractional divider registers mli0_fdr and mli1_fdr control the frequencies of f mli0 and f mli1 . this configuration makes it possible to enable/disable the module clocks f mli0 and f mli1 independently of f dma . dma clock control (dma_clc) mca05909_mod f ml i 0 f dma (= f clc ) mli0 module kernel mli1 module kernel mli0_fdr mli1_fdr f ml i 1 f s fpi ecen multican module ecen www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-132 v1.1, 2011-03 mli, v1.11 combined with the baud rate as derived in the mli module (see equation (27.1) on page 27-67 ) and the mlix_fdr fractional divider setup, the resulting mli baud rate is defined by: (27.4) (27.5) equation (27.4) applies to normal divider mode of the fractional divider (fdr.dm = 01 b ). equation (27.5) applies to fractional divider mode (fdr.dm = 10 b ). after a reset operation, both mli modules are enabled in normal divider mode. according the mlix_fdr register?s reset value of 03ff 43ff h , the selected baud rate is f dma /2. note that the dma controller is also enabled after a reset operation with clock f dma = f fpi . baud rate mlix f dma 2 ---------------- - 1 n -- - f dma 2 ---------------- - n 1024 ------------ - www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-133 v1.1, 2011-03 mli, v1.11 27.5.4 port control and connections mli0 and mli1 clock and data output lines are connected to gpio ports and are, therefore, controlled in the port logics (see also page 27-128 and page 27-129 ). the following port control operations selections must be executed for these i/o lines: ? input/output function selection (iocr registers) ? pad driver characteristics select ion for the outputs (pdr registers) 27.5.4.1 input/output function selection the port input/output control registers contain the bit fields that select the digital output and input driver characteristics such as port direction (input/output) with alternate output selection, pull-up/down devices, and open-drain selections. the i/o lines for the mli modules are controlled by the port 1, port 5 and port 8 input/output control registers. when the mli modules are connected to the gpio port lines, the correct settings of the enable/polarity control bits and bit fields in the output input control registers mli0_iocr and mli1_iocr must also be regarded (transmitter i/o line control see page 27-53 , receiver i/o line control see page 27-54 ). note that after a reset operation the mli0 and mli1 modules (although enabled) have no direct connections to the gpio lines. table 27-11 shows how oicr register bits and bit fields must be programmed for the required gpio functionality of the mli i/o lines. table 27-11 mli0 and mli1 i/o line selection and setup module port lines input/output control register bits i/o mli0 p1.3 / tready0b p1_iocr0.pc3 = 0xxx b mli0_oicr.tre = 1 mli0_oicr.trp = x mli0_oicr.trs = 01 b input p1.4 / tclk0 p1_iocr4.pc4 = 1x01 b mli0_oicr.tce = 1 mli0_oicr.tcp = x output p1.5 / tready0a p1_iocr4.pc5 = 0xxx b mli0_oicr.tre = 1 mli0_oicr.trp = x mli0_oicr.trs = 00 b input p1.6 / tvalid0a p1 _iocr4.pc6 = 1x01 b mli0_oicr.tvea = 1 mli0_oicr.tvpa = x output p1.7 / tdata0 p1_iocr4.pc7 = 1x01 b mli0_oicr.tdp = x output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-134 v1.1, 2011-03 mli, v1.11 mli0 p1.8 / rclk0a p1_iocr8.pc8 = 0xxx b mli0_oicr.rce = 1 mli0_oicr.rcp = x mli0_oicr.rcs = 00 b input p1.9 / rready0a p1_iocr8.pc9 = 1x01 b mli0_oicr.rrs = 00 b mli0_oicr.rrpa = x output p1.10 / rvalid0a p1_iocr8.pc10 = 0xxx b mli0_oicr.rve = 1 mli0_oicr.rvp = x mli0_oicr.rvs = 00 b input p1.11 / rdata0a p1_iocr8.pc11 = 0xxx b mli0_oicr.rdp = x mli0_oicr.rds = 00 b input p1.13 / rclk0b p1_iocr12.pc13 = 0xxx b mli0_oicr.rce = 1 mli0_oicr.rcp = x mli0_oicr.rcs = 01 b input p1.14 / rvalid0b p1_iocr12.pc14 = 0xxx b mli0_oicr.rve = 1 mli0_oicr.rvp = x mli0_oicr.rvs = 01 b input p1.15 / rdata0b p1_iocr12.pc15 = 0xxx b mli0_oicr.rdp = x mli0_oicr.rds = 01 b input p5.4 / rready0b p5_iocr4.pc4 = 1x10 b mli0_oicr.rrs = 01 b mli0_oicr.rrpb = x output p5.6 / tvalid0b p5 _iocr4.pc6 = 1x10 b mli0_oicr.tveb = 1 mli0_oicr.tvpb = x output table 27-11 mli0 and mli1 i/o line selection and setup (cont?d) module port lines input/output control register bits i/o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-135 v1.1, 2011-03 mli, v1.11 mli1 p8.0 / tclk1 p8_iocr0.pc0 = 1x11 b mli1_oicr.tce = 1 mli1_oicr.tcp = x output p8.1 / tready1a p8_iocr0.pc1 = 0xxx b mli1_oicr.tre = 1 mli1_oicr.trp = x mli1_oicr.trs = 00 b input p8.2 / tvalid1a p8 _iocr0.pc2 = 1x11 b mli1_oicr.tvea = 1 mli1_oicr.tvpa = x output p8.3 / tdata1 p8_iocr0.pc3 = 1x11 b mli1_oicr.tdp = x output p8.4 / rclk1a p8_iocr4.pc4 = 0xxx b mli1_oicr.rce = 1 mli1_oicr.rcp = x mli1_oicr.rcs = 00 b input p8.5 / rready1a p8_iocr4.pc5 = 1x11 b mli1_oicr.rrs = 00 b mli1_oicr.rrpa = x output p8.6 / rvalid1a p8_iocr4.pc6 = 0xxx b mli1_oicr.rve = 1 mli1_oicr.rvp = x mli1_oicr.rvs = 00 b input p8.7 / rdata1a p8_iocr4.pc7 = 0xxx b mli1_oicr.rdp = x mli1_oicr.rds = 00 b input table 27-11 mli0 and mli1 i/o line selection and setup (cont?d) module port lines input/output control register bits i/o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-136 v1.1, 2011-03 mli, v1.11 27.5.5 on-chip connections 27.5.5.1 service request output connections each mli module provides eight service req uest outputs sr[7:0] that can be used to generate interrupts or dma requests. in the TC1798, four service request outputs sr[3:0] of the mli0 module and two service request outputs sr[1:0] of the mli1 module are connected to an interrupt node. service request outputs sr[3:2] of the mli1 module are not connected. four service request outpu ts (sr[7:4]) of each mli module are connected to dma request inputs of the TC1798 dma controller. each of the service request outputs used as interrupt requests are controlled by a service request control register. the service request control registers of the mli modules are located inside the dma address area. therefore, all mli0/mli1 service request control registers are named as dma_ml ixsrcy and described in the dma chapter implementation part of the TC1798 users manual. all mli service request output connections are listed in table 27-12 . table 27-12 service request lines and interconnections of mli0/mli1 module service req. output line connected to node or dma request input description mli0 sr0 dma_mli0src0 mli0 service request node 0 (in dma) sr1 dma_mli0src1 mli0 service request node 1 (in dma) sr2 dma_mli0src2 mli0 service request node 2 (in dma) sr3 dma_mli0src3 mli0 service request node 3 (in dma) sr4 ch00_reqi7 dma channel 00 request input 7 ch04_reqi7 dma channel 04 request input 7 sr5 ch01_reqi7 dma channel 01 request input 7 ch05_reqi7 dma channel 05 request input 7 sr6 ch02_reqi7 dma channel 02 request input 7 ch06_reqi7 dma channel 06 request input 7 sr7 ch03_reqi7 dma channel 03 request input 7 ch07_reqi7 dma channel 07 request input 7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-137 v1.1, 2011-03 mli, v1.11 27.5.5.2 break signals the brkout output signals of mli0 and mli1 are connected as break input signals to the multi core break switch (mcbs) that is a part of the cerberus on-chip debug control module. these connections allow mli0/mli1 in itiated break conditions to be generated in the cerberus. 27.5.5.3 trigger input signals the five trigger input signals tr[4:0] are connected to v ss . 27.5.6 access protection the access protection parameters for the mli module in the TC1798 are identical with access protection parameters of the dma controller. details of the access protection parameters are defined in the dma chapte r at ?dma module implementation? - ?access protection assignment?. the table ?dma access protection address ranges? in the dma chapter is also valid for mli register bits aer0.aenrx and aer1.aenrx (x = 0-31). the tables ?... address protection sub-range definition? for pmi, ovram, dmi, and pcp pram in the dma chapter are also valid for mli register bits arr0,1.slicen and arr0,1.sizen (n = 0-3). mli1 sr0 dma_mli1src0 mli1 service request node 0 (in dma) sr1 dma_mli1src1 mli1 service request node 1 (in dma) sr2 ? not connected sr3 ? not connected sr4 ch10_reqi15 dma channel 10 request input 15 ch14_reqi15 dma channel 14 request input 15 sr5 ch11_reqi15 dma channel 11 request input 15 ch15_reqi15 dma channel 15 request input 15 sr6 ch12_reqi15 dma channel 12 request input 15 ch16_reqi15 dma channel 16 request input 15 sr7 ch13_reqi15 dma channel 13 request input 15 ch17_reqi15 dma channel 17 request input 15 table 27-12 service request lines and interconnections of mli0/mli1 (cont?d) module service req. output line connected to node or dma request input description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-138 v1.1, 2011-03 mli, v1.11 27.5.7 mli0/mli1 transfer window address maps in the TC1798, the transfer windows for the mli0 and mli1 modules are located in the address ranges as identified in table 27-13 . table 27-13 mli0/mli1 transfer windows module window type pipe address range mli0 small transfer window (stw) pipe 0 f01e 0000 h to f01e 1fff h pipe 1 f01e 2000 h to f01e 3fff h pipe 2 f01e 4000 h to f01e 5fff h pipe 3 f01e 6000 h to f01e 7fff h large transfer window (ltw) pipe 0 f020 0000 h to f020 ffff h pipe 1 f021 0000 h to f021 ffff h pipe 2 f022 0000 h to f022 ffff h pipe 3 f023 0000 h to f023 ffff h mli1 small transfer window (stw) pipe 0 f01e 8000 h to f01e 9fff h pipe 1 f01e a000 h to f01e bfff h pipe 2 f01e c000 h to f01e dfff h pipe 3 f01e e000 h to f01e ffff h large transfer window (ltw) pipe 0 f024 0000 h to f024 ffff h pipe 1 f025 0000 h to f025 ffff h pipe 2 f026 0000 h to f026 ffff h pipe 3 f027 0000 h to f027 ffff h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-139 v1.1, 2011-03 mli, v1.11 27.5.8 mli0/mli1 address map an absolute register address is given by th e offset address of the register (given in table 27-10 ) plus the module base address (given in table 27-9 ). table 27-14 address map of mli0/mli1 short name description address access mode reset value read write multi link interface 0 (mli0) ? reserved f010 c000 h nbe sv, e ? ? reserved f010 c004 h nbe nbe ? mli0_ id mli0 module identification register f010 c008 h u, sv be 0025 c0xx h mli0_ fdr mli0 fractional divider register f010 c00c h u, sv sv, e 03ff 43ff h mli0_ tcr mli0 transmitter control register f010 c010 h u, sv u, sv 0000 0110 h mli0_ tstatr mli0 transmitter status register f010 c014 h u, sv be 0000 0000 h mli0_ tp0statr mli0 transmitter pipe 0 status register f010 c018 h u, sv be 0000 0000 h mli0_ tp1statr mli0 transmitter pipe 1 status register f010 c01c h u, sv be 0000 0000 h mli0_ tp2statr mli0 transmitter pipe 2 status register f010 c020 h u, sv be 0000 0000 h mli0_ tp3statr mli0 transmitter pipe 3 status register f010 c024 h u, sv be 0000 0000 h mli0_ tcmdr mli0 transmitter command register f010 c028 h u, sv u, sv 0000 0000 h mli0_ trstatr mli0 transmitter registers status register f010 c02c h u, sv be 0000 0000 h mli0_ tp0aofr mli0 transmitter pipe 0 address offset register f010 c030 h u, sv be 0000 0000 h mli0_ tp1aofr mli0 transmitter pipe 1 address offset register f010 c034 h u, sv be 0000 0000 h mli0_ tp2aofr mli0 transmitter pipe 2 address offset register f010 c038 h u, sv be 0000 0000 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-140 v1.1, 2011-03 mli, v1.11 mli0_ tp3aofr mli0 transmitter pipe 3 address offset register f010 c03c h u, sv be 0000 0000 h mli0_ tp0datar mli0 transmitter pipe 0 data register f010 c040 h u, sv be 0000 0000 h mli0_ tp1datar mli0 transmitter pipe 1 data register f010 c044 h u, sv be 0000 0000 h mli0_ tp2datar mli0 transmitter pipe 2 data register f010 c048 h u, sv be 0000 0000 h mli0_ tp3datar mli0 transmitter pipe 3 data register f010 c04c h u, sv be 0000 0000 h mli0_ tdrar mli0 transmitter data read answer register f010 c050 h u, sv u, sv 0000 0000 h mli0_ tp0bar mli0 transmitter pipe 0 base address register f010 c054 h u, sv u, sv 0000 0000 h mli0_ tp1bar mli0 transmitter pipe 1 base address register f010 c058 h u, sv u, sv 0000 0000 h mli0_ tp2bar mli0 transmitter pipe 2 base address register f010 c05c h u, sv u, sv 0000 0000 h mli0_ tp3bar mli0 transmitter pipe 3 base address register f010 c060 h u, sv u, sv 0000 0000 h mli0_ tcbar mli0 transmitter copy base address register f010 c064 h u, sv be 0000 0000 h mli0_ rcr mli0 receiver control register f010 c068 h u, sv u, sv 0100 0000 h mli0_ rp0bar mli0 receiver pipe 0 base address register f010 c06c h u, sv be 0000 0000 h mli0_ rp1bar mli0 receiver pipe 1 base address register f010 c070 h u, sv be 0000 0000 h mli0_ rp2bar mli0 receiver pipe 2 base address register f010 c074 h u, sv be 0000 0000 h mli0_ rp3bar mli0 receiver pipe 3 base address register f010 c078 h u, sv be 0000 0000 h table 27-14 address map of mli0/mli1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-141 v1.1, 2011-03 mli, v1.11 mli0_ rp0statr mli0 receiver pipe 0 status register f010 c07c h u, sv be 0000 0000 h mli0_ rp1statr mli0 receiver pipe 1 status register f010 c080 h u, sv be 0000 0000 h mli0_ rp2statr mli0 receiver pipe 2 status register f010 c084 h u, sv be 0000 0000 h mli0_ rp3statr mli0 receiver pipe 3 status register f010 c088 h u, sv be 0000 0000 h mli0_ radrr mli0 receiver address register f010 c08c h u, sv be 0000 0000 h mli0_ rdatar mli0 receiver data register f010 c090 h u, sv be 0000 0000 h mli0_ scr mli0 set clear register f010 c094 h u, sv u, sv 0000 0000 h mli0_ tier mli0 transmitter interrupt enable register f010 c098 h u, sv u, sv 0000 0000 h mli0_ tisr mli0 transmitter interrupt status register f010 c09c h u, sv be 0000 0000 h mli0_ tinpr mli0 transmitter interrupt node pointer register f010 c0a0 h u, sv u, sv 0000 0000 h mli0_ rier mli0 receiver interrupt enable register f010 c0a4 h u, sv u, sv 0000 0000 h mli0_ risr mli0 receiver interrupt status register f010 c0a8 h u, sv be 0000 0000 h mli0_ rinpr mli0 receiver interrupt node pointer register f010 c0ac h u, sv u, sv 0000 0000 h mli0_ gintr mli0 global interrupt set register f010 c0b0 h u, sv u, sv 0000 0000 h mli0_ oicr mli0 output input control register f010 c0b4 h u, sv u, sv 1000 8000 h mli0_ aer0 mli0 access enable register 0 f010 c0b8 h u, sv sv, e 0000 0000 h table 27-14 address map of mli0/mli1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-142 v1.1, 2011-03 mli, v1.11 mli0_ arr0 mli0 access range register 0 f010 c0bc h u, sv sv, e 0000 0000 h mli0_ aer1 mli0 access enable register 1 f010 c0c0 h u, sv sv, e 0000 0000 h mli0 arr1 mli0 access range register 1 f010 c0c4 h u, sv sv, e 0000 0000 h ? reserved f010 c0c0 h - f010 c0fc h be be ? micro link interface 1 (mli1) ? reserved f010 c100 h nbe sv, e ? ? reserved f010 c104 h nbe nbe ? mli1_ id mli1 module identification register f010 c108 h u, sv be 0025 c0xx h mli1_ fdr mli1 fractional divider register f010 c10c h u, sv sv, e 03ff 43ff h mli1_ tcr mli1 transmitter control register f010 c110 h u, sv u, sv 0000 0110 h mli1_ tstatr mli1 transmitter status register f010 c114 h u, sv be 0000 0000 h mli1_ tp0statr mli1 transmitter pipe 0 status register f010 c118 h u, sv be 0000 0000 h mli1_ tp1statr mli1 transmitter pipe 1 status register f010 c11c h u, sv be 0000 0000 h mli1_ tp2statr mli1 transmitter pipe 2 status register f010 c120 h u, sv be 0000 0000 h mli1_ tp3statr mli1 transmitter pipe 3 status register f010 c124 h u, sv be 0000 0000 h mli1_ tcmdr mli1 transmitter command register f010 c128 h u, sv u, sv 0000 0000 h mli1_ trstatr mli1 transmitter registers status register f010 c12c h u, sv be 0000 0000 h mli1_ tp0aofr mli1 transmitter pipe 0 address offset register f010 c130 h u, sv be 0000 0000 h table 27-14 address map of mli0/mli1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-143 v1.1, 2011-03 mli, v1.11 mli1_ tp1aofr mli1 transmitter pipe 1 address offset register f010 c134 h u, sv be 0000 0000 h mli1_ tp2aofr mli1 transmitter pipe 2 address offset register f010 c138 h u, sv be 0000 0000 h mli1_ tp3aofr mli1 transmitter pipe 3 address offset register f010 c13c h u, sv be 0000 0000 h mli1_ tp0datar mli1 transmitter pipe 0 data register f010 c140 h u, sv be 0000 0000 h mli1_ tp1datar mli1 transmitter pipe 1 data register f010 c144 h u, sv be 0000 0000 h mli1_ tp2datar mli1 transmitter pipe 2 data register f010 c148 h u, sv be 0000 0000 h mli1_ tp3datar mli1 transmitter pipe 3 data register f010 c14c h u, sv be 0000 0000 h mli1_ tdrar mli1 transmitter data read answer register f010 c150 h u, sv u, sv 0000 0000 h mli1_ tp0bar mli1 transmitter pipe 0 base address register f010 c154 h u, sv u, sv 0000 0000 h mli1_ tp1bar mli1 transmitter pipe 1 base address register f010 c158 h u, sv u, sv 0000 0000 h mli1_ tp2bar mli1 transmitter pipe 2 base address register f010 c15c h u, sv u, sv 0000 0000 h mli1_ tp3bar mli1 transmitter pipe 3 base address register f010 c160 h u, sv u, sv 0000 0000 h mli1_ tcbar mli1 transmitter copy base address register f010 c164 h u, sv be 0000 0000 h mli1_ rcr mli1 receiver control register f010 c168 h u, sv u, sv 0100 0000 h mli1_ rp0bar mli1 receiver pipe 0 base address register f010 c16c h u, sv be 0000 0000 h mli1_ rp1bar mli1 receiver pipe 1 base address register f010 c170 h u, sv be 0000 0000 h table 27-14 address map of mli0/mli1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-144 v1.1, 2011-03 mli, v1.11 mli1_ rp2bar mli1 receiver pipe 2 base address register f010 c174 h u, sv be 0000 0000 h mli1_ rp3bar mli1 receiver pipe 3 base address register f010 c178 h u, sv be 0000 0000 h mli1_ rp0statr mli1 receiver pipe 0 status register f010 c17c h u, sv be 0000 0000 h mli1_ rp1statr mli1 receiver pipe 1 status register f010 c180 h u, sv be 0000 0000 h mli1_ rp2statr mli1 receiver pipe 2 status register f010 c184 h u, sv be 0000 0000 h mli1_ rp3statr mli1 receiver pipe 3 status register f010 c188 h u, sv be 0000 0000 h mli1_ radrr mli1 receiver address register f010 c18c h u, sv be 0000 0000 h mli1_ rdatar mli1 receiver data register f010 c190 h u, sv be 0000 0000 h mli1_ scr mli1 set clear register f010 c194 h u, sv u, sv 0000 0000 h mli1_ tier mli1 transmitter interrupt enable register f010 c198 h u, sv sv 0000 0000 h mli1_ tisr mli1 transmitter interrupt status register f010 c19c h u, sv be 0000 0000 h mli1_ tinpr mli1 transmitter interrupt node pointer register f010 c1a0 h u, sv u, sv 0000 0000 h mli1_ rier mli1 receiver interrupt enable register f010 c1a4 h u, sv u, sv 0000 0000 h mli1_ risr mli1 receiver interrupt status register f010 c1a8 h u, sv be 0000 0000 h mli1_ rinpr mli1 receiver interrupt node pointer register f010 c1ac h u, sv u, sv 0000 0000 h mli1_ gintr mli1 global interrupt set register f010 c1b0 h u, sv u, sv 0000 0000 h table 27-14 address map of mli0/mli1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-145 v1.1, 2011-03 mli, v1.11 mli1_ oicr mli1 output input control register f010 c1b4 h u, sv u, sv 1000 8000 h mli1_ aer0 mli1 access enable register 0 f010 c1b8 h u, sv sv, e 0000 0000 h mli1_ arr0 mli1 access range register 0 f010 c1bc h u, sv sv, e 0000 0000 h mli1_ aer1 mli1 access enable register 1 f010 c1c0 h u, sv sv, e 0000 0000 h mli1_ arr1 mli1 access range register 1 f010 c1c4 h u, sv sv, e 0000 0000 h ? reserved f010 c1c0 h - f010 c1cc h be be ? table 27-14 address map of mli0/mli1 (cont?d) short name description address access mode reset value read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 micro link interface (mli) users manual 27-146 v1.1, 2011-03 mli, v1.11 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-1 v1.1, 2011-03 gpta ? v5, v1.0 28 general purpose timer array (gpta ? v5) this chapter describes the general pur pose timer array of the TC1798. the gpta 1) consists of the following units: gpta0 and gp ta1 with identical functionality; ltca2 with reduced gpta0 functionality. this chapter contains the following sections: ? a summary on the structure and basic functionalities (see page 28-4 ) ? functional description of the gpta ? v5 kernel, applicable for gpta0 and gpta1 (see page 28-8 ) ? register descriptions of all gpta ? v5 kernel specific registers, applicable for gpta0 and gpta1 (see page 28-160 ) ? functional description of the ltca2 kernel (see page 28-234 ) ? register descriptions of all ltca2 kernel specific registers (see page 28-250 ) ? TC1798 implementation-specific details and registers of the gpta ? v5 module, including port connections and control, interrupt control, address decoding, and clock control (see page 28-274 ). note: the gpta ? v5 kernel register names described in section 28.4 , section 28.6 , and section 28.7.2 will be referenced in the TC1798 users manual by the unit name prefix ?gpta0_? for the gpta0 uni t, by ?gpta1_? for the gpta1 unit, and by ?ltca2_? for the ltca2 unit. 28.1 what is new? the major updates from gptav4 to gptav5 are: ? the flexibility to generate on-chip trigger and gating signals have been increased. the gptav5 provides 16 such signals. each of the signals may be mapped to any output signal of a local or global timer cell. therefore it is not limited as before to a single group of global or local timer cells (25% of the gtc or ltc). limitation now is, that no more than 4 different on-chip trigger and gating signals may be mapped to one group of ltc or gtc. details concer ning this new on-chip trigger and gating signal multiplexer are described in section 28.3.4.3 (see page 28-108 ). this new features is not fully upwards compatible to the gptav4. additional output multiplexer registers have to be configured to achieve the same functionality (see ?multiplexer register array programming? on page 28-121 ). some very minor issue may occur due to a minor reduction of on-chip signal and trigger signals compared to gptav4, but on the other hand the increased flexibility should nearly always compensated this. the following list summarizes the principle of mapping former gptav4 signals to the new gptav5 signals: ? gptav4 signal gpta0_out0 is replaced by gptav5 signal gpta0_trig01 ? gptav4 signal gpta0_out1 is replaced by gptav5 signal gpta0_trig11 1) tricore ? , c166 ? , infineon ? , infineon technologies ? , and gpta ? are trademarks of infineon technologies ag. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-2 v1.1, 2011-03 gpta ? v5, v1.0 ? gptav4 signal gpta0_out2 is replaced by gptav5 signal gpta0_trig00 ? gptav4 signal gpta0_out3 is replaced by gptav5 signal gpta0_trig10 ? gptav4 signal gpta0_out8 is replaced by gptav5 signal gpta0_trig03 ? gptav4 signal gpta0_out9 is replaced by gptav5 signal gpta0_trig13 ? gptav4 signal gpta0_out10 is repl aced by gptav5 signal gpta0_trig02 ? gptav4 signal gpta0_out11 is repl aced by gptav5 signal gpta0_trig12 ? gptav4 signal gpta0_out16 is repl aced by gptav5 signal gpta0_trig05 ? gptav4 signal gpta0_out18 is repl aced by gptav5 signal gpta0_trig15 ? gptav4 signal gpta0_out19 is repl aced by gptav5 signal gpta0_trig04 ? gptav4 signal gpta0_out24 is repl aced by gptav5 signal gpta0_trig07 ? gptav4 signal gpta0_out26 is repl aced by gptav5 signal gpta0_trig17 ? gptav4 signal gpta0_out27 is repl aced by gptav5 signal gpta0_trig06 ? gptav4 signal gpta0_out28 is repl aced by gptav5 signal gpta0_trig07 ? gptav4 signal gpta0_out4 is no longer available in gptav5. this signal was routed to the eru (tc1766 only) to cover 75% of the gtc and ltc cells as input to input channel 1. but signal gpta 0_trig12 may be routed to all (100%) gtc and ltc cells due to the on-chip trigger and gating multiplexer and therefore fulfills this requirement already. ? gptav4 signal gpta0_out7 is no longer available in gptav5. this signal was routed to the eru (tc1766 only) to cover 75% of the gtc and ltc cells as input to input channel 2. but signal gpta 0_trig14 may be routed to all (100%) gtc and ltc cells due to the on-chip trigger and gating multiplexer and therefore fulfills this requirement already. ? to be consistent to tc1797, the double c onnected input group of iog3 is renamed to iog6 and the output group og1-7 are renamed to og0-og6 and the og0 is renamed to iog7. ? gptav4 signal gpta0_out17 is no longer available in gptav5. this signal was routed to the eru to cover 50% of the gtc and ltc cells as input to input channel 2. but signal gpta0_trig14 may be rout ed to all (100%) gtc and ltc cells due to the on-chip trigger and gating multiple xer and therefore fulfills this requirement already. ? gptav4 signal gpta0_out22 is no longer available in gptav5. this signal was routed to the eru (tc1766 only) to cover 75% of the gtc and ltc cells as input to input channel 3. but signal gpta 0_trig16 may be routed to all (100%) gtc and ltc cells due to the on-chip trigger and gating multiplexer and therefore fulfills this requirement already. ? gptav4 signal gpta0_out25 is no longer available in gptav5. this signal was routed to the eru to cover 50% of the gtc and ltc cells as input to input channel 3. but signal gpta0_trig16 may be rout ed to all (100%) gtc and ltc cells due to the on-chip trigger and gating multiple xer and therefore fulfills this requirement already. ? gptav4 signal gpta0_out5 is no long er required (time trigger can) but gptav5 signal gpta0_trig05 is reserved for it. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-3 v1.1, 2011-03 gpta ? v5, v1.0 ? to improve effective usage of the local timer cells, a new cell bypassing, so called global bypass, is introduced. this bypassing enables more flexible cell allocation and also reduces the number of ltc required for coherent update. details on the two different local timer cell bypass mechanism may be found in the section ?data output line control? on page 28-73 . two different application examples using the global and local bypass may be found in section 28.3.3.5 (see page 28-85 ). this new features is upwards compatible to the gptav4. ? due to the new bypassing mechanism, a new coherent update mechanism has been introduced, the local coherent update described within section 28.3.3.5 (see page 28-85 ). this new local coherent update or double action principle, is very useful to update single local timer cells or a couple of local timer cells within a group sequentially (not simultaneously) without signal distortion (no other signal output beside the previously configured and the new configured). the new update principle allows to update a local timer cell within a group of local timer cells independent of other local timer cells and therefore also not synchronous/coherent to other local timer cells. this new mechanism upgrades the older mechanism of global coherent update. this older principle of global coherent is very useful to update a number of local timer cells simultaneously. this new features is upwards compatible to the gptav4. ? the gpta0/gpta1, and ltca2 outs are additionally assigned to new ports. eight new outputs on port 0, eight new outputs on port 1, one new output on port 2, two new outputs on port 3, fourteen new outputs on port 5, four new outputs on port 14, sixteen new outputs on port 13, and twelve new outputs on port 14. ? to enable a family concept between tc1797 and tc1767, the gpta to msc interconnection assignment of msc0 and msc1 has been changed. details can be found in section 28.7.4.2 (see page 28-287 ). ? to fix a design bug for tc1797 and tc1767, the input line in1 of the gpta1 now switches the common input of gpta0/gpta1/ltca2 units for connecting to the output of a 4-to-1 multiplexer. this multiplexer is controlled by bit field scu_syscon.gptais and a llows the gpta0/gpta1/ ltca2 input in1 to be connected to one out of four port input lines. ? gpta1 provided the clock base for ltca2 within the gptav4 version. this disables a family concept of products only having a gpta0 and an ltca2 (e.g. tc1767). therefore gpta0 is now used as clock source for the ltca2 and gpta1 is used as clock source for ltca3. ? the common in0 of gpta0/gpta1/ltca2 is multiplexed within the scu to connect either to a port pin or the extclk0 (see page 28-296 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-4 v1.1, 2011-03 gpta ? v5, v1.0 28.2 gpta ? v5 overview the TC1798 contains the two general purpose timer arrays (gpta0 and gpta1) with identical functionality, plus the additional local timer cell array (ltca2). figure 28-1 shows a global view of the gpta ? v5 units. the gpta ? v5 provides a set of timer, compare, and capture functionalities that can be flexibly combined to form signal measur ement and signal generation cells. they are optimized for tasks typical of engine, gearbox , and electrical motor control applications, but can also be used to generate simple and complex signal waveforms required for other industrial applications. figure 28-1 general block diagram of the gpta ? v5 units in the TC1798 signal generation cells mcb05910_tc 1798 gt1 gt0 fpc5 fpc4 fpc3 fpc2 fpc1 fpc0 pdl1 pdl0 dcm2 dcm1 dcm0 digital pll dcm3 gtc02 gtc01 gtc00 gtc31 global timer cell array gtc03 gtc30 clock bus gpta0 clock generation cells signal generation cells gt1 gt0 fpc5 fpc4 fpc3 fpc2 fpc1 fpc0 pdl1 pdl0 dcm2 dcm1 dcm0 digital pll dcm3 gtc02 gtc01 gtc00 gtc31 global timer cell array gtc03 gtc30 clock bus gpta1 clock generation cells clock conn . clock distribution cells f gpta f gpta ltc02 ltc01 ltc00 ltc63 local timer cell array ltc03 ltc62 ltc02 ltc01 ltc00 ltc63 local timer cell array ltc03 ltc62 i/o line sharing block i/o line sharing block interrupt sharing block interrupt sharing block clock distribution cells ltc02 ltc01 ltc00 ltc63 local timer cell array ltc03 ltc62 ltca2 i/o line sharing block interrupt sharing block www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-5 v1.1, 2011-03 gpta ? v5, v1.0 28.2.1 functionality of gpta0 and gpta1 the general purpose timer arrays (gpta0 and gpta1) each provides a set of hardware cells required for high-speed digital signal processing: ? filter and prescaler cells (fpc) support input noise filtering and prescaler operation. ? phase discrimination logic cells (pdl) decode the direction information output by a rotation tracking system. ? duty cycle measurement cells (dcm) provide pulse-width measurement capabilities. ? a digital phase locked loop cell (pll) generates a programmable number of gpta ? v5 unit ticks during an input signal?s period. ? global timer cells (gt) driven by various clock sources are implemented to operate as a time base for the associated global timer cells. ? global timer cells (gtc) can be programmed to capture the contents of a global timer on an external or inter nal event. a gtc may also be used to control an external port pin depending on the result of an internal compare operation. gtcs can be logically concatenated to provide a common external port pin with a complex signal waveform. ? local timer cells (ltc) operating in timer, capture, or compare mode may also be logically tied together to drive a common external port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mode ? can be clocked or triggered by various external or internal events. ? on-chip trigger and gating signals (otgs) can be configured to provide trigger or gating signals to integrated peripherals (gpta0 only). input lines can be shared by an ltc and a gtc to trigger their programmed operation simultaneously. the following list summarizes the specific features of the gpta ? v5 cells. clock generation cells ? filter and prescaler cell (fpc) ? six independent cells ? three basic operating modes: prescaler, delayed debounce filter, immediate debounce filter ? selectable input sources: port lines, gpta ? v5 unit clock, fpc output of preceding fpc cell ? selectable input clocks: gpta ? v5 unit clock, prescaled gpta ? v5 unit clock, dcm clock, compensated or uncompensated pll clock. ? f gpta /2 maximum input signal frequency in filter modes ? phase discriminator logic (pdl) ? two independent cells ? two operating modes (2- and 3- sensor signals) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-6 v1.1, 2011-03 gpta ? v5, v1.0 ? f gpta /4 maximum input signal frequency in 2-sensor mode, f gpta /6 maximum input signal frequency in 3-sensor mode ? duty cycle measurement (dcm) ? four independent cells ? 0 - 100% margin and time-out handling ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? digital phase locked loop (pll) ?one cell ? arbitrary multiplication factor between 1 and 65535 ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? clock distribution cells (cdc) ?one unit ? provides nine clock output signals: f gpta , divided f gpta clocks, fpc1/fpc4 outputs, dcm clock, ltc prescaler clock signal generation cells ? global timers (gt) ? two independent cells ? two operating modes (free-running timer and reload timer) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? global timer cell (gtc) ? 32 cells related to the global timers ? two operating modes (capture, compare and capture after compare) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? local timer cell (ltc) ? 64 independent cells ? three basic operating modes (timer, capture and compare) for 63 cells ? special compare modes for one cell ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency interrupt sharing block ? 318 interrupt sources, generating up to 108 service requests www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-7 v1.1, 2011-03 gpta ? v5, v1.0 on-chip trigger block ? 16 on-chip trigger signals i/o sharing block ? interconnecting inputs and outputs from inte rnal clocks, fpc, gt c, ltc, ports, and msc interface 28.2.2 functionality of ltca2 the local timer cell array (ltca2) provide a set of hardware cells required for high- speed digital signal processing: ? local timer cells (ltc) operating in timer, capture, or compare mode may also be logically tied together to drive a common external port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mode ? can be clocked or triggered by various external or internal events. the following list summarizes the specific features of the ltca cells. signal generation cells ? local timer cell (ltc) ? 64 independent cells ? three basic operating modes (timer, capture and compare) for 63 cells ? special compare modes for one cell ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency i/o sharing block ? interconnecting input s and outputs from internal clocks, lt c, ports, and msc interface www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-8 v1.1, 2011-03 gpta ? v5, v1.0 28.3 gpta0/gpta1 kernel description the functionality of the general purpose timer arrays gpta0/gpta1 kernel is described in this section. clock control, address decoding, and service (interrupt) request control are managed outside the gpta0/gpta1 unit kernel. figure 28-2 shows a global unit diagram of the gpta ? v5 unit kernel. figure 28-2 block diagram of gpta ? v5 kernel each gpta0/1 kernel has 56 input signals, 112 output signals, and four input signals, that can be connected to port pins or other on-chip logic modules (see ?gpta?v5 module implementation? on page 28-274 for the TC1798 specific interconnections). further, several clock input and output signals are provided. interrupt control mcb05911_tc!/)/ clock control address decoder f gpta sr[37 :00 ] gpta module kernel clock generation cells filter & prescaler cells phase discriminator logic duty cycle measurement cells digital phase locked loop i/o line sh aring blo ck signal generation cells global timers global timer cells local timer cells f clc gt0run gt1run in[55:00] out[111 :00 ] interrupt sharing block clock bus clk[7:0] int[3:0] external pll clock inputs internal pll clock outputs clock distribution cells 2 2 on-chip trigger block trig[15:00] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-9 v1.1, 2011-03 gpta ? v5, v1.0 28.3.1 gtpa units each of the general purpose timer arrays gpta0 and gpta1 ( figure 28-2 ) is split into clock generation cells (cgc) and a signal generation cells (sgc): ?the clock generation cells (see page 28-10 ) allow a preprocessing of the input signals using filter, timer, capture, compare and enhanced digital pll cells: ?the filter and prescaler cells (fpc) provide input noise filtering (immediate debounce and delayed debounce) and may also work as prescalers for the gpta ? v5 module clock and external signals. ?the phase discrimination logic (pdl) may take the outputs of the fpcs to decode phase encoded signals from a position and rotation direction sensor system. ?the duty cycle measurement cells (dcm) provide signal measurement capabilities (timer plus capture register, single and double capture on rising and falling edges or both) as well as missing pulse detection/reconstruction functions. ?the digital phase locked loop (digital pll) generates a clock with higher clock resolution (harmonic) out of the sign al measured by dcm cells. any arbitrary multiplication factor between 1 and 65535 is supported and may be changed each pll clock period. ?the clock distribution cells (cdc) provide all ltcs and gts with a variety of different clock signals. it is equipped with gpta ? v5 module clock prescalers and multiplexers supporting alternate clock sources. the original signals and all outputs of the preprocessing cells are distributed to the global timers and ltcs via the clock bus. ?the signal generation cells (see page 28-38 ) provide a set of timers, capture and compare cells: ? the two 24-bit global timers (gt) can be individually configured as free-running counters or as reload counters star ting at a programmable value from 0 h to ffffff h . each gt is equipped with a scalable greater-or-equal comparator; the number of bits to be compared is selectable. ?the global timer cell registers (gtc) are 24-bit wide. gtcs may be used as comparators (modifying the logical state of a related output port pin), or as capture cells, storing the current gt0 or gt1 valu e on rising, falling or both signal edges detected on a related input port pin. several adjacent gtcs may be connected to logical cells operating on the same pin, allowing complex functions to be implemented. ?the local timer cell registers (ltc) are 16-bit wide. 63 ltcs can be configured to operate in one of four different modes: free-running or resetable counter, capture or compare cell. adjacent cells can be combined to operate on the same pin, thus generating complex waveforms. one ltc (ltc63) can be used for special compare modes. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-10 v1.1, 2011-03 gpta ? v5, v1.0 28.3.2 clock generation cells as described in detail in the following sections, the clock generation cells (cgc) provides the following signal pre-processing cells: ? filter and prescaler cell (fpc) ? phase discrimination logic (pdl) ? duty cycle measurement cell (dcm) ? digital phase locked loop cell (pll) ? clock distribution cells (cdc) the filter and prescaler cells (fpc) provide input noise filtering using a debounce filter. fpcs are also able to operate as a prescaler for the gpta ? v5 module clock and external signals. each fpc can select among different data and clock input signals. the phase discrimination logic (pdl) is able to decode fpc debounce filtered and phase encoded signals coming from a position and rotation direction sensor system. in the pdl, phase encoding can be bypassed. the duty cycle measurement cells (dcm) provide signal measurement capabilities (timer plus capture register, single and double capture on rising and falling edges or both) as well as missing pulse detection/reconstruction functions. the digital phase locked loop (pll) is intended to generate a higher resolution clock out of the values measured by dcm cells. an y arbitrary multiplication factor between 1 and 65535 is supported and may be changed from input clock period to input clock period. the clock distribution cells (cdc) provide all local and global timer cells with a variety of different clock signals. it is equipped with gpta ? v5 module clock prescalers and multiplexers supporting alternate clock sources. figure 28-3 shows how the cells of the cgc are interconnected. the external interface signals of the cgc are: ?gpta ? v5 module clock f gpta ?gpta ? v5 module input signals (connected to the fpcs) ? clock bus outputs (generated by the cdc) ? pdl bus outputs ? external pll clock inputs (fed into cdc) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-11 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-3 interconnections in the clock generation cells mca05912 sot0 f gpta fpc0 signal inp. clock g pta i nputs sol0 sot1 fpc1 signal inp. clock sol1 sot2 fpc2 signal inp. clock sol2 sot3 fpc3 signal inp. clock sol3 sot4 fpc4 signal inp. clock sol4 sot5 fpc5 signal inp. clock sol5 m u x control logic m u x dcm0 dcm1 pdl0 f0 b0 m u x control logic m u x dcm2 dcm3 pdl1 f0 b0 pll cdu g pta i nputs g pta i nputs g pta i nputs g pta i nputs g pta i nputs clock bus 8 ext. pll clock inputs clk1 / clk2 / clk3 pdl0 pdl1 pdl2 pdl3 pdl bus int. pl l clock outpu ts 4 3 4 3 4 3 4 3 4 3 4 3 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-12 v1.1, 2011-03 gpta ? v5, v1.0 28.3.2.1 filter and prescaler cell (fpc) each gpta ? v5 contains six filter and prescaler cells, fpc0 to fpc5. as shown in figure 28-4 , each fpc is equipped with an signal input multiplexer, a clock multiplexer, an edge detection circuitry, a 16-bit timer, a 16-bit compare register, a 16-bit comparator, and a fpc control circuitry (see also page 28-126 for the fpc functional algorithm description). the edge detection circuitry detects respective edges for the prescaler modes and detects glitches in all other modes. figure 28-4 filter and prescaler cell architecture fpc registers the following registers are assigned to the filter and prescaler cells fpck (k = 0-5): ? fpcstat = filter and prescale r cell status register (see page 28-167 ) ? fpcctrk = filter and prescaler cell control register k (see page 28-168 ) ? fpctimk = filter and prescaler cell timer register k (see page 28-170 ) mca05913_mod ips fpcctrk sink0 sink4 = f gpta sink5 = solk-1 clk cink1 cink3 cink2 edge detect sink1 sink2 sink3 pin select clock select fe re fpc control logic cmp f gpta fpcctrk compare value tim fpctimk timer sotk solk 2 mod regk fpcstat fegk fpcstat cink0 = f gpta rtg fpcctrk fpc sin cin 3 16 16 3 sin www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-13 v1.1, 2011-03 gpta ? v5, v1.0 fpc operating modes each filter and prescaler cell can be individually configured to operate in one of the following operating modes: ? delayed debounce filter mode on both edges ? immediate debounce filter mode on both edges ? rising edge: immediate debounce filter mode, falling edge: no filtering ? rising edge: no filtering, falling edge: immediate debounce filter mode ? rising edge: delayed debounce filter mode, falling edge: immediate debounce filter mode ? rising edge: immediate debounce filter mode, falling edge: delayed debounce filter mode ? prescaler mode (triggered by edge detection circuitry on rising edge) ? prescaler mode (triggered by edge detection circuitry on falling edge) the operation mode is selected by bit field fpcctrk.mod ( page 28-168 ). fpc input signals bit field fpcctrk.ips (see page 28-168 ) selects one of the following inputs for fpck: ? signal input 0 (sink0) ? signal input 1(sink1) ? signal input 2 (sink2) ? signal input 3 (sink3) ?gpta ? v5 module clock f gpta (sink4) ? preceding fpc level output signal solk-1 (sin05 is connected to sol5) when the preceding fpc level output signal is selected as input, two or more fpcs may be concatenated; for example, to combine a delayed debounce filter and an immediate debounce filter. the maximum fpc input signal frequency must be less than or equal to the sampling rate ( f gpta /2). the assignment of gpta ? v5 i/o line and fpc signal inputs sink is defined in ?fpc input line selection? on page 28-102 . fpc filter clocks bit field fpcctrk.clk (see page 28-169 ) selects one of four filter clocks for fpck: ? clock input line 0 (cink0) = gpta ? v5 module clock f gpta ? clock input line 1 (cin k1) = local pll clock, ? clock input line 2 (cink2) = (prescaled) gpta ? v5 module clock f gpta or pll clock from other unit or dcm 3 clock ? clock input line 3 (cink3) = dcm 2 clock or pll clock of other unit or uncompensated pll clock or uncompensated pll clock of other unit when using a pll clock for the fpc, no software is needed to adapt the fpc filter to changing speed for angle-based input signals. the standard pll clock can be either the www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-14 v1.1, 2011-03 gpta ? v5, v1.0 compensated or uncompensated pll clock or can be the pll clock of the other gpta ? v5 units. the uncompensated pll clock is useful in applications in which bursts (due to acceleration) might disturb the filter function. with a prescaled gpta ? v5 module clock, very long time filter time periods can be achieved. note: all filter operation are always synchronously to f gpta . therefore the further signal analysis (e.g. glitch detection) is not processed on the rising edge of the selected filter clock cin, but on the next rising edge of f gpta following the rising edge of selected cin (gated clock principle). therefore cin clock rates above f gpta will lead to non deterministic behavior. output signal splitting two output lines are provided by each fpc cell as follows: ? an trigger output signal sotk, reporting a falling or rising signal edge on the fpc input by a single f gpta clock pulse, ? a level output signal solk, indicating the direction of the detected signal transition. this signal-splitting scheme (pair of trigger and level output) provides subsequent pdl and dcm cells with the information about an input signal transition in the same f gpta clock cycle. this feature avoids cascading a one clock delay per edge detection circuitry implemented at the input of each subsequent cell. figure 28-5 shows the fpc output signal splitting scheme. figure 28-5 fpc output splitting into trigger and level information mct05914 f gpta fpc level output solk fpc trigger output sotk fpc input sink www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-15 v1.1, 2011-03 gpta ? v5, v1.0 delayed debounce filter mode in delayed debounce filter mode, the signal input sin is filtered from all signal transitions and glitches with a width smaller than the selected clock period length multiplied by the compare register value. the input signal sin (sampled with f gpta ) is analyzed at the selected filter clock rate of cin. if the state of the input sample differs from the current output signal value, the 16-bit timer is incremented by one. when the timer register fpctimk is not in its idle state (0000 h ) and the state of the input sample matches the current output signal value, the 16-bit timer is decremented by one (see figure 28-6 ); if bit fpcctrk.rtg is set, the timer will be set to idle state again (see figure 28-7 ). a rising or falling edge, occurring on the signal input line sin when the timer is greater than zero but less than the compare value, sets the corresponding glitch flag fpcstat.reg (on rising edge glitch) or fpcstat.feg (on falling edge glitch). when the timer matches the 16-bit compare value stored in fpcctrk.cmp (timer threshold), the level output signal line solk is inverted, a gpta ? v5 module clock pulse is generated at the trigger output signal sotk, and the timer is reset to 0000 h . the rising/falling edge glitch flags must be reset by software. the filter is by-passed if the compare value fpcctrk.cmp is programmed to zero (0000 h ). in this case, the input signal is directly copied to the output signal. figure 28-6 fpc delayed debounce filter algorithm with timer decrement must be cleared by software mct05915 total signal delay timer threshold s ignal input s in t imer value f pcctrk.tim l evel output s olk f pcstat.fegk f pcstat.regk t rigger output s otk www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-16 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-7 fpc delayed debounce filter algorithm with timer reset the total signal delay from input to output depends on the programmed compare register value, the number of high-frequency pulses (g litches) during the filter operating time, and the timer behavior in case of a glitch (decrement or reset). the fpc delayed debounce filter mode is selected by: ? fpcctrk.mod = 000 b mct05916 total signal delay timer threshold must be cleared by software s ignal input s in t imer value f pcctrk.tim l evel output s olk f pcstat.fegk f pcstat.regk t rigger output s otk www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-17 v1.1, 2011-03 gpta ? v5, v1.0 immediate debounce filter mode in immediate debounce filter mode, the inpu t signal is filtered from signal transitions and glitches arriving a programmable time after an input signal edge detection (see figure 28-8 ). the input signal sin is sampled with f gpta and the input signal sin edge detection is also performed with f gpta . the further analysis (e.g. filter timer increment, glitch detection) is done at the selected filt er clock rate of cin. as long as the timer is reset, the fpc control circuitry copies the sampled input value directly to the level output signal line solk. when a rising or falling edge occurs on the signal input line sin and the 16-bit compare value fpcctrk.cmp is not zero, the timer is enabled to be incremented by the selected clock and the copy mechanism is disabled. when the timer value fpctimk.tim matches the compare value fpcctrk.cmp, the timer is reset and the copy mechanism is enabled again. a rising or falling edge, occurring on sin while the timer is greater than zero but less than the compare value, sets the corresponding glitch flag fpcstat.reg (on rising edge glitch) or fpcstat.feg (on falling edge glitch). the rising/falling edge glitch flags must be reset by software. the filter is by-passed if the compare value fpcctrk.cmp is programmed to zero (0000 h ). in this case, the input signal is directly copied to the output signal without any disable periods. figure 28-8 fpc immediate debounce filter algorithm on both edges must be cleared by software mct05917 edge inhibition timer threshold s ignal input s in t imer value f pcctrk.tim l evel output s olk f pcstat.fegk f pcstat.regk t rigger output s otk www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-18 v1.1, 2011-03 gpta ? v5, v1.0 note: during the last clock cycle of edge inhibition time (where timer value is equal to the compare value) an input signal glitch will be filtered but the corresponding glitch status flag in r egister fpcstat is not set. the immediate debounce filter can be enabled only for one edge, either rising or falling. in this case, the signal output follows the signal input value immediately after the timer threshold of the filtered edge is reached, without re-starting the timer (see figure 28-9 ). figure 28-9 fpc immediate debounce filter algorithm on rising edge only the fpc immediate debounce filter modes are selected by: ? fpcctrk.mod = 001 b : immediate debounce filter mode on both edges ? fpcctrk.mod = 010 b : immediate debounce filter mode on rising edge only, no filtering on falling edge. ? fpcctrk.mod = 011 b : immediate debounce filter mode on falling edge only, no filtering on rising edge. mct05918 edge inhibition timer threshold must be cleared by software s ignal input s in t imer value f pcctrk.tim l evel output s olk f pcstat.fegk f pcstat.regk t rigger output s otk www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-19 v1.1, 2011-03 gpta ? v5, v1.0 mixed filter modes in the mixed filter modes, one edge of a signal is filtered in the delayed debounce mode, and the other edge is filtered in the immediate debounce mode. the debounce mode is switched when the timer threshold is reached. note that both filter modes use the same timer threshold in this case (see figure 28-10 , demonstrating delayed debounce mode with timer decrement on rising edge and immediate debounce of on falling edge). figure 28-10 fpc mixed filter algorithm the fpc mixed filter mo des are selected by: ? fpcctrk.mod = 100 b : delayed debounce filter mode on rising edge immediate debounce filter mode on falling edge ? fpcctrk.mod = 101 b : immediate debounce filter mode on rising edge delayed debounce filter mode on falling edge mct05919 timer threshold total signal delay edge inhibition must be cleared by software s ignal input s ink t imer value f pcctrk.tim l evel output s olk f pcstat.fegk f pcstat.regk www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-20 v1.1, 2011-03 gpta ? v5, v1.0 prescaler mode in prescaler mode, the input signal is sampled and analyzed with f gpta . the fpc control circuitry counts each rising (or falling) edge of the input signal. when the timer value matches the compare value: ? one gpta ? v5 module clock pulse is generated at the trigger output signal sotk and level output signal solk ? the timer fpctimk.tim is reset to 0000 h figure 28-11 shows a divide-by-6 operation using the fpc in prescaler mode with trigger on rising edge selected. figure 28-11 fpc prescaler mode for a divide-by-n operation, the compare value fpcctrk.cmp must be set to n - 1. the fpc prescaler modes are selected by: ? fpcctrk.mod = 110 b : prescaler mode triggered by edge detection circuitry on rising edge ? fpcctrk.mod = 111 b : prescaler mode triggered by edge detection circuitry on falling edge fpcctrk.cmp = 000 5 h mct05920 s ignal input s ink t imer value f pcctrk.tim l evel/trigger o utputs s olk/sotk 0000 h 0001 h 0002 h 0005 h 0000 h 0001 h 0002 h 0004 h 0003 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-21 v1.1, 2011-03 gpta ? v5, v1.0 28.3.2.2 phase discrimination logic (pdl) the gpta ? v5 provides two phase discriminatio n logic cells (pdl0, pdl1) driven by two signal lines coming from an fpc cell (for description, see page 28-14 ): ? an event input signal ? a level input signal both phase discrimination logic cells are c ontrolled by the phase discrimination logic control register pdlctr (see page 28-171 ). each pdl is equipped with an edge detection circuitry, a phase detection circuitry, a pdl control circuitry, and an output multiplexer. six output lines are provided by each pdl cell: ? a forward output signal (f0, f1) is driven by one f gpta clock pulse if an input signal edge is recognized as forward rotation. t hese signals can be connected to any local timer cell via the pdl bus. ? a backward output signal (b0, b1) is driven by one f gpta clock pulse if an input signal edge is recognized as backward rotation. this signal can be connected to any local timer cell via the pdl bus. ? two pairs of output signals, carrying the bypassed input level and event information from the driving fpc cells or the angular velocity and error information provided by the pdl function. these output lines are directly connected to the adjacent duty cycle measurement cells, dcm0/dcm1(for pdl0) and dcm2/dcm3 (for pdl1). the pdl processes the output signal of a 2- sensor or 3-sensor positioning system. with bit pdlctr.tsex = 1, a 3-sensor system ex ecution is selected providing the dcm1 and/or dcm3 cell with information concerning erroneous states in the signal input. when pdlctr.tsex = 0, a 2-sensor syst em is selected and dcm1 and/or dcm3 are supplied with the input event and level information from the driving fpc2 and/or fpc5. the rotation direction, monitored by the co nnected sensors, is automatically derived from the sequence in which the input signals change. each edge detected on an input signal line generates a pulse on the f0, f1 forward output lines or on the b0, b1 backward output lines. input jitter, which might occur if a sensor rests near to one of its switching points, is compensated. if bit pdlctr.muxx = 1, the trigger output signal to dcm0/dcm2 (angular velocity information) is driven by a boolean ?or? operation of the corresponding forward trigger and backward trigger signal while the level output signal at dcm0/dcm2 is at fixed high level. in this case, every pulse at f0/b0 and f1/b1 generates a rising edge at the dcm0/dcm trigger signal. if bit pdlctr.muxx = 0, the associated dcm0/dcm2 signals are directly connected with the input event and level signals from the driving fpc0/fpc3. to calculate the sensor?s current position, the associated ltcs should be clocked with the pdl forward and backward output pulses. a software operation, subtracting the backward counter contents from the forwar d counter contents, provides the absolute www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-22 v1.1, 2011-03 gpta ? v5, v1.0 position. dynamic information (speed, acceleration, deceleration) may be obtained by analyzing the angular velocity signal periods with the associated dcm cell. the maximum input frequency is f gpta /4 for a 2-sensor positioning system and f gpta /6 for a 3-sensor positioning system. to ensur e that a transition of any input signal is correctly recognized, its level should be held high or low for at least two f gpta cycles before it changes (three f gpta cycles for a 3-sensor positioning system). figure 28-12 block diagram of phase discrimination logic cells mcb05921 2 f pc0 phase discrimation logic pdl0 f0 b0 dcm 0 2 2 2 f pc1 f pc2 dcm 1 2 pdl0 pdl1 pdl2 pdl3 pdl bus tse0 mux0 err0 pdlctr set 2 f pc3 phase discrimation logic pdl1 f1 b1 dcm 2 2 2 2 f pc4 f pc5 dcm 3 2 tse1 mux1 err1 set pdlctr mux mux mux mux 1 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-23 v1.1, 2011-03 gpta ? v5, v1.0 positioning system with two sensors the 2-sensor mode is enabled when bit pdlctr.tsex is reset. the sensors are mounted at a 90 angle to each other (see figure 28-13 ). the third sensor input of the pdl cell is internally disabled and dcm1/dcm 3 cell inputs are driven by fed-through fpc2/fpc5 output lines. this configuration can measure an absolute position with a resolution of 90 . no error conditions can be detected. figure 28-13 interface signals of a pdl in a 2-sensor positioning system figure 28-14 illustrates how the output signals of a 2-sensor system superimposed with noise are processed by the pdl cell. jitter pulses are completely compensated if they do not occur on both signal lines simultaneously. ! means not re means rising edge fe means falling edge forward res1*!s2 + s1*res2 + fes1*s2 + !s1*fes2 backward res1*s2 + !s1*res2 + fes1*!s2 + s1*fes2 position forward_counter - backward_counter mct05922 s1 s2 forward backward s2 forward_counter backward_counter forward s1 s2 backward s1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-24 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-14 compensation of input jitter positioning system with three sensors the 3-sensor mode is enabled when bit pd lctr.tsex is set to 1. the sensors are mounted at an 120 angle to each other (see figure 28-15 ). this configuration can measure an absolute position with a resolution of 60 . input signal combinations that are not allowed in a properly-working positioning system (all inputs low or all inputs high) cause the following to occur: ? an error signal is generated, driving the duty cycle measurement cells dcm1 and/or dcm3, ? the error flag pdlctr.errx is set, ? no forward or backward pulses are generated. when the error disappears, the error signal will be cleared. the error flag pdlctr.errx must be reset by software. ! means not re means rising edge fe means falling edge forward res1*!s2*s3 + fes3*s1*!s2 + res2*s1*!s3 + fes1*s2*!s3 + res3*!s1*s2 + fes2*!s1*s3 backward res1*s2*!s3 + fes3*!s1*s2 + res2*!s1*s3 + fes1*!s2*s3 + res3*s1*!s2 + fes2*s1*!s3 error the input signal states s1*s2*s3 and !s1*!s2*!s3 are not allowed position forward_counter - backward_counter mct05923 s 1 s 2 f orward b ackward jitter jitter www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-25 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-15 interface signals of a pdl in a 3-sensor positioning system jitter pulses are completely compensated as illustrated in figure 28-14 . mct05924 12345612 s 1 s 2 s 3 f orward b ackward 16543216 s1 s2 s3 forward backward s2 s 3 s 1 forward_counter backward_counter 1 3 2 4 5 6 1 2 3 4 5 6 00 01 11 10 00 01 11 10 0 1 s3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-26 v1.1, 2011-03 gpta ? v5, v1.0 28.3.2.3 duty cycle me asurement cell (dcm) the gpta ? v5 contains four dcm cells (dcm0 to dcm3). the input signal to be analyzed is delivered as a 2-line signal input (see figure 28-5 for the event/level input signal splitting scheme). it is build by: ? an event input, and ? a signal level input. each dcm cell has four outputs: ? an event output line, ? an interrupt output that can become active at a signal input rising edge, ? an interrupt output that can become active at a signal input falling edge, ? an interrupt output that can become active at a compare event. each dcm cell is equipped with a 24-bit timer, a 24-bit capture register, a 24-bit capture/compare register, a 24-bit com parator and a dcm control circuitry ( figure 28-16 ). the following registers are assigned to the dcm cells: ? dcmctrk = duty cycle measurement control register k (see page 28-173 ) ? dcmtimk = duty cycle measurement timer register k (see page 28-175 ) ? dcmcavk = duty cycle measurement capture register k (see page 28-175 ) ? dcmcovk = duty cycle measurement capture/compare register k (also referred as ?capcom?, see page 28-176 ) ? srsc0 = service request state clear register 0 (see page 28-223 ) ? srss0 = service request state set register 0 (see page 28-225 ) figure 28-16 block diagram of a duty cycle measurement cell mca05925 24 ce rising edge service reque st tim (timer) dcmtimk cav (capture) dcmcavk cov (capt./comp) dcmcovk = 2 s ignal i nput dcm control unit falling edge service reque st compare service reque st event output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-27 v1.1, 2011-03 gpta ? v5, v1.0 the dcm cell inputs are connected to the pdl outputs. depending on the configuration of the associated pdl cell, the dcm cells can also be driven by a fpc directly (as shown in figure 28-12 ): ? dcm0 is driven by fpc0 or pdl0 angular velocity signal, ? dcm1 is driven by fpc2 or pdl0 error signal, ? dcm2 is driven by fpc3 or pdl1 angular velocity signal, ? dcm3 is driven by fpc5 or pdl1 error signal. when the driving fpcs and pdl cells are programmed in feed-through mode, an external port pin signal as selected by the fpc input multiplexer can be directly processed by a dcm cell. the duty cycle of the dcm cell signal input can be determined by measuring its period length and the width of its low or high state. for this purpose, several operations can be started on an signal input edge: ? reset timer the local timer can be reset on rising, falling, or both edges of the signal input line as selected via control bits dcmctrk.rze (for rising edge) and dcmctrk.fze (for falling edge). after a reset timer event, the timer is continuously incremented by the gpta ? v5 module clock f gpta until the next reset condition occurs. if no reset timer event is enabled, the timer operates in free-running timer mode, repeatedly counting from its lower limit (000000 h ) to its upper limit (ffffff h ). ? capture the current timer value is stored in the capture register dcmcav on the rising edge (dcmctr.rca = 1) or falling edge (dcmctrk.rca = 0) of the signal input line. the current timer value is stored in the capture/compare register dcmcov on the opposite signal edge as selected by dcmctrk.rca and if enabled by bit dcmctrk.oca = 1. with dcmctrk.oca = 0 the capture/compare register dcmcov is not affected. ? edge service request and interrupt request on a rising input signal edge of the dcmk cell (k = 0-3) the service request flag srs0.dcm0kr is set. additionally, a serv ice request signal is triggered if bit dcmctrk.rre = 1. a falling input signal edge sets the service request flag srs0.dcm0kf. an interrupt request generation on this edge is triggered if bit dcmctrk.fre = 1. both edges of the signal input line initiate an interrupt request when both bits, dcmctrk.fre and dcmctrk .rre, are set. the interrupt on signal input edges is disabled if both bits are cleared. ? hardware generated output pulse a single f gpta clock pulse is generated on the dcm output line if enabled by control register bit dcmctrk.rck (rising edge at signal line) and/or dcmctrk.fck (falling edge at signal line) and an appropriate edge is detected at the input. the 0% or 100% duty cycle exception (no edge or only one edge detected) can be handled by a limit checking option. the expected input signal?s maximum period length (measured in f gpta clock ticks) can be loaded into the capture/compare www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-28 v1.1, 2011-03 gpta ? v5, v1.0 register dcmcov that is continuously compared with the timer value. when the timer is incremented up to the limit stored in c apture/compare register, the service request flag srs0.dcm0xc is set. if the compare serv ice request is enabled (control register bit dcmctrk.cre = 1), an interrupt request is generated. ? software generate d output pulse if the software intends to compensate an input pulse backlog, bit dcmctrk.qck should be set to 1. this immediately triggers a single clock pulse generation on the dcm output signal line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-29 v1.1, 2011-03 gpta ? v5, v1.0 dcm interrupt control each dcm cell is able to generate three service request output signals. the service request outputs of a dcmk cell are controlled as shown in figure 28-17 . when a service request condition occurs, the corresponding service request flag is always set. the service request output is activated only if it is enabled by the corresponding enable bit. further details on service request and interrupt handling are provided in section ?interrupt sharing block (is)? on page 28-123 . figure 28-17 dcmk service request generation mca05926_mod rre dcmctrk dcm0kr dcm0kr dcm0kr srss0 (read) srsr0 (read) set srss0 (write) srsc0 (write) set reset fre dcmctrk dcm0kf dcm0kf dcm0kf srss0 (read) srsr0 (read) set srss0 (write) srsc0 (write) set reset cre dcmctrk dcm0kc dcm0kc dcm0kc srss0 (read) srsr0 (read) set srss0 (write) srsc0 (write) set reset rising edge detection of input signal falling edge detection of input signal compare event occurred dcmkrsr dcmkfsr dcmkcsr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-30 v1.1, 2011-03 gpta ? v5, v1.0 28.3.2.4 digital phase locked loop cell (pll) the gpta ? v5 provides a digital phase locked loop cell (pll) with a frequency multiplier function. an input signal edge is used as a trigger to generate a programmable number of gpta ? v5 module clocks f gpta on the output signal line. the four signal output lines of the dcm cells can be used as p ll trigger input. the pll control circuitry distributes the desired number of gpta ? v5 clocks in regular time intervals over the input signal period length. the pll can automatically follow an acceleration or deceleration of the input signal. alternatively, an external software routine may handle the input signal?s period length variation. the pll includes a 4-channel input multiplexer, a 16-bit timer, a 16-bit step register, a 24-bit reload register, a 24-bit adder, a 24-bit multiplexer, a 25-bit delta register extended by one sign bit and a pll control circuitry (see figure 28-18 ). the following registers are assigned to the phase locked loop cell: ? pllctr = phase locked loop control register (see page 28-177 ) ? pllmti = phase locked loop microtick register (see page 28-178 ) ? pllcnt = phase locked loop counter register (see page 28-179 ) ? pllstp = phase locked loop step register (see page 28-179 ) ? pllrev = phase locked loop reload register (see page 28-180 ) ? plldtr = phase locked loop delta register (see page 28-181 ) ? srsc0 = service request state clear register 0 (see page 28-223 ) ? srss0 = service request state set register 0 (see page 28-225 ) three output signals are available on the pll cell: ? pll signal output line ? uncompensated pll signal output line ? service request line the desired input signal is selected by programming bit field pllctr.mux. the number of output pulses to be generated within one input signal period must be stored in the microtick register pllmti and (coded in 2-co mplement data format) in the step register pllstp. the pllrev reload register must be programmed with a reload value. this reload value is calculated by subtracting the number of output pulses to be generated within one input signal period from the input signal?s period length (measured in number of f gpta clocks). an automatic compensation of an inpu t signal acceleration or deceleration is enabled by setting bit pllctr.aen to 1 (automatic end mode). after disabling the automatic end mode, the pll continuously generates output pulses without synchronization to an input signal edge. when the counter for the number of remaining output signal pulses pllcnt decrements to zero, the pll service request flag is set. additionally, a service request signal pllsr will be generated if the control register bit pllctr.ren is set. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-31 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-18 block diagram of digital pll cell pll interrupt control the pll cell is able to generate a service request output signal pllsr. this signal is controlled as shown in figure 28-19 . when the service request condition pllcnt = 0 occurs, the service request flag is always set. the service request output pllsr is activated only if it is enabled by the enable bit pllctr.ren. additional information about service request and interrupt handling are given in section ?interrupt sharing block (is)? on page 28-123 . figure 28-19 pll service request generation mcb05927 input mux 16 mti (microtick value) pllmti cnt (microtick counter) pllcnt rev (reload value) pllrev stp (step value) pllstp 2-complement mux dtr (delta value) plldtr sign bit add unit pll signal uncompensated pll signal service request pll control logic ren pllctr mux & load 2 24 16 24 d cm0 d cm1 d cm2 d cm3 mca0592 8 ren pllctr pll pll pll srss0 (read) srsr0 (read) set plls r p llcnt = 0 set reset srss0 (write) srsc0 (write) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-32 v1.1, 2011-03 gpta ? v5, v1.0 steady input signal example in the following example, the input signal?s period length is 13 f gpta clock periods, which should be subdivided into three equally spaced sections. the reload value to be stored in pllrev.rev register is calculated to 0a h (10 = 13 - 3). pllmti.mti is loaded with 03 h (number of output pulses) and its 2-complement representation (fffd h ) is written into pllstp.stp. after a reset, a state machine driven by the gpta ? v5 module clock, updates the delta register plldtr with the reload value. afte rwards, the pllstp register?s contents are continuously added to the delta register value ( figure 28-20 ). in fact, the difference between both values is computed and stored in the plldtr register again, because the pllstp register has been loaded with a negative value (2-complement data format). when the plldtr register has been decremented to a negative value, the reload register contents are added to de lta register?s current contents. a rising edge detected on the selected input signal triggers the counter register pllcnt to load the number of requested output pul ses from pllmti. when a negative content of the plldtr register is detected, the microtick counter is decremented by one. in automatic mode (aen = 1), the output pulse generation is stopped when the microtick counter reaches zero. the period length of a single output pulse varies between four and five f gpta clocks; the maximum period length variation of output pulses is restricted to one f gpta clock. the total period length of all three output pulses, generated by one pll loop corresponds to the input signal period width (5 + 4 + 4 = 13 f gpta clocks). figure 28-20 digital pll steady state simulation mct05929_mod pll input signal -1 -3 -2 -1 -3 -2 -1 2 1 0 3 2 1 3 0 4 5 6 3 4 5 6 6 77 8 8 9 9 ticks pll output signal plldtr content 9 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-33 v1.1, 2011-03 gpta ? v5, v1.0 this type of pll implementation presents a valuable advantage compared to classic pll implementation. indeed, the generated microticks are equally distributed. the division reminder is distributed to several cl ocks instead of adding th is reminder to the last pulse clock of the period. figure 28-21 illustrates this advantage. considering a period of 15 clock pulses to be divided by a factor of 4, it gives a result of 3 with a reminder equal to 3. the reload value is calculated to 0b h (11 = 15 - 4). the number of output pulses is equal to 4 and its 2-complement representation (fffc h ) is written into the step register. figure 28-21 advantage of the gpta ? v5 pll input signal acceleration and deceleration the consequence of an input signal accele ration or deceleration can be compensated either automatically or by an external software routine. it detects an input signal?s period length variation by comparing the current period length (measured in the associated dcm cell) with the expected period length used as calculation base for the pllrev register contents. ? compensation of input signal deceleration ? compensation by pll automatic end mode if automatic end mode is enabled (pllctr.aen = 1), the pll stops at the calculated end of the current input signal period. due to the deceleration, the rising edge of the following input signal period is delayed, starting the next pll operation later than expected. a gap occurs between the last output pulse of the current input signal period and the first pulse of the following one (see figure 28-22 ). ? compensation by software after disabling the automatic end mode (pllctr.aen = 0), the pll generates output pulses without synchronization to an input signal edge. in case of a deceleration, more output pulses than calculated are generated during one input signal period. several algorithms can be implemented to compensate the surplus of generated output pulses: the length of the current input signal period has been underestimated by a certain mct05930_mod pll output of a conventional pll pll output of the gpta pll pll input signal 33 3 6 3 4 4 4 f gpta www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-34 v1.1, 2011-03 gpta ? v5, v1.0 number of f gpta clock periods. this deficit could be added to the calculated length of the next input signal period. the pll can continue to operate with the old input signal period length estimation, but the number of output pulses to be generated during the next input clock period may be decreased by the surplus of output pulses initiated during the last signal period. figure 28-22 compensation of input signal deceleration ? compensation of input signal acceleration ? compensation by pll automatic end mode the next rising edge of the input signal arrives while the counter has not been decremented to zero. the pll performs all remaining output signal pulses at full speed ( f gpta ), when control register bit aen is set to 1. afterwards, counter and delta register are reloaded with their calculated values and the pll operates at normal speed (see figure 28-23 ). ? compensation by software after disabling the automatic end mode, the pll generates fewer output pulses than calculated during one input signal period. several algorithm can be mct05931_mod compensated signal output aen = 0 0123456789abcdef012345 microtick counter aen = 0 time time compensated signal_output aen = 1 microtick counter aen = 1 decelerated input signal steady state input signal 0123456789abcdef 01 uncompensated signal output aen = x 0123456789abcdef012345 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-35 v1.1, 2011-03 gpta ? v5, v1.0 implemented to compensate for the lack of generated output pulses: the length of the current input signal period has been overestimated by a certain number of f gpta clock periods. this deficit should be subtracted from the calculated length of the next input signal period. the pll can continue to operate with the old input signal period length estimation, but the number of output pulses to be generated during the next input clock period may be increased by the lack of output pulses initiated during the last signal period. figure 28-23 compensation of input signal acceleration additionally to the normal output signal , the pll provides an uncompensated output signal. this signal has no gaps or acceleration bursts. however, the number of microticks during one signa l period may be incorrect. 28.3.2.5 clock distribution cell (cdc) the clock distribution cells (cdc) provides al l local and global timer cells with a clock bus containing eight different clock output signals clk[7:0] and a special ltc prescaler clock ltcpre. these nine clock signals are generated out of eleven clock input signals coming from different clock sources (see figure 28-24 ). the prescalers divide the gpta ? v5 module clock f gpta by a programmable 2 n factor. factor n is defined by bit fields dfa02, dfa04, dfa06 and dfa07 of control register mct05932_mod signal output aen = 0 0123456789abcdef012345 0123456789abcd ef 0 1 microtick counter aen = 0 time time signal_output aen, pen = 1 microtick counter aen, pen = 1 accelerated input signal steady state input signal www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-36 v1.1, 2011-03 gpta ? v5, v1.0 ckbctr. a bit field value of 15 disables the related prescaler and selects alternate sources for clock bus lines 2, 4, 6 and 7. for clock bus line clk2, a bit field value of 14 selects an alternate source. for clock bus line clk3, the 2-bit wide bit field dfa03 of control register ckbctr selects one of the four available clocks. the ltc prescaler clock ltcpre is generated by dividing the f gpta module clock by a factor defined by the 3-bit wide bit field dfaltc of control register ckbctr. note that the ltcpre clock is not a part of the clock bus but a clock signal that is distributed directly from the cdc to each ltc except ltc63. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-37 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-24 block diagram of clock distribution cells mcb05933 14 0-13 15 0-14 dfa02 ckbctr 15 clk0 dfa04 ckbctr 15 0-14 dfa06 ckbctr 15 0-14 dfa07 ckbctr 1 0 dfa03 ckbctr 2 3 ext. pllclk pllclk f gpta pllclk uncomp. ext. pllclk uncomp. fpc1 sot1 fpc4 sot4 dcm0 dcm1 dcm3 dcm2 pll cloc k bus clk1 clk2 clk3 clk4 clk5 clk6 clk7 0-7 dfaltc ckbctr ltcpre 2 dfa02 2 dfa04 2 dfa06 2 dfa07 2 dfaltc 4 2 14 4 15 15 15 8 4 4 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-38 v1.1, 2011-03 gpta ? v5, v1.0 28.3.3 signal generation cells as described in detail in the following sections, the signal generation cells contains the following types of cells: ? global timer (gt) ? global timer cell (gtc) ? local timer cell (ltc) 28.3.3.1 global timers (gt) the gpta ? v5 provides two global 24-bit timers (gt) that are connected to the clock bus with its eight clock lines. each gt is locally equipped with a clock source multiplexer, a 24-bit up-counter, a 24-bit reload register, and a 24-bit greater/equal comparator (see figure 28-25 ). note: index variable k (= 0, 1) determines the number of the global timer. figure 28-25 block diagram of global timer (gt) the following registers are assigned to the global timers gtk (k = 0, 1): ? gtctrk = global timer control register k (see page 28-182 ) ? gtrevk = global timer reload value register k (see page 28-184 ) ? gttimk = global timer register k (see page 28-183 ) ? srsc0 = service request state clear register 0 (see page 28-223 ) ? srss0 = service request state set register 0 (see page 28-225 ) mcb05934 mux gtctrk cloc k bus . . . clock select tim (24-bit timer) gttimk rev (24-bit reload) gtrevk tevk ren gtctrk & gpta data bus mux (16:1) sco gtctrk tgek reload 3 4 s qtk g tvk clk0 clk1 clk6 clk7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-39 v1.1, 2011-03 gpta ? v5, v1.0 each of the two gt cells provides the following input/output signals: ? eight clock inputs, connected to the clock bus from the clock distribution cells (cdc) ? global timer value bus gtvk (outputs), carrying the 24-bit gtk counter value ? tevk output, indicating a gt counter update ? tgek output, indicating the result of a compare operation ? sqtk service request output, triggered at a timer overflow. the global timer output signals gtvk, tevk, an d tgek are available as input signals at each gtc (see also page 28-56 ). global timer k can be initialized with a start value, that is written by software into the gttimk register. the 24-bit global timer value gttimk.tim is incremented by each rising edge of clock input signal tevk that is selected from the 8-bit clock bus via bit field gtctrk.mux. on a global timer overflow (transition of ffffff h to 000000 h ), the following events occur: ? the 24-bit reload value gtrevk.rev is copied into gttimk.tim ? bit srsc0.gt0k is set ? the service request output sqtk is activated (if enabled by bit gtctrk.ren) a free-running timer is configured by programming gtrevk.rev with 000000 h . the ?timer event? (tevk) output is activat ed if the gtk value changes because of a clock edge, a timer reload operation, or a software write access to gtctrk. the tevk output is connected to all gtcs. tevk is used in the gtcs to trigger a compare operation, re-checking the equality of their compare register contents and the updated global timer value. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-40 v1.1, 2011-03 gpta ? v5, v1.0 gt interrupt control each of the gts is able to generate a service request output signal sqtk. this signal is controlled as shown in figure 28-26 . on a gtk timer overflow, the service request flag gt0k is always set. the service request output sqtk is activated only if it is enabled by the enable bit gtctrk.ren. additional in formation about service request and interrupt handling is given in section ?interrupt sharing block (is)? on page 28-123 . figure 28-26 gtk service request generation synchronization of global timers both global timers, gt0 and gt1, can be enabled and disabled individually. each gt has its own run signal gtkrun that is generated outside the gpta ? v5 kernel (see also page 28-8 ). signal gtkrun is generated in a gpta ? v5 clock control circuitry. this external control capability allows the run signals gtkrun to be controlled in a way that all global timers of one ore more gpta ? v5 units can be enabled/disabled synchronously. the two global timers will run synchronously only if all of the following conditions are true: ? timers use the same input signal ? timers are started (and stopped, if required) synchronously ? timers use identical start and reload values ? timers are not written while they are running mca0593 5 ren gtctrk gt0k gt0k gt0k srss0 (read) srsr0 (read) set sqt k srss0 (write) srsc0 (write) t imer overflow set reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-41 v1.1, 2011-03 gpta ? v5, v1.0 scalable signed greater or equal compare this section (up to page 28-54 ) explains the classical timer update problem , and the solutions supported by the gpta ? v5. the two global timers embedded into the gpta ? v5 include a 24-bit greater/equal comparator. this comparator cell perform s compare operations between the gt timer contents and the data value found on the gpta ? v5-internal data bus (coming from a gtc compare register update). the goal of this comparator is to be able to perform an action immediately if the compare cell is updated with a new threshold but the timer has already passed this value. figure 28-27 gives an example on this greater/equal concept. assumption: a timer is running and a new threshold (value t) is set. the different points px represent different ca ses of present time. when at p1 or p2, the moment represented by t lies in the future and no action is yet required. when at p3 or p4, the moment represented by t lies in t he past, and an action is required immediately. so, the problem is to determine if the threshold t has been passed or not. considering an infinite counter , the situation is simple. the evaluation consists in determining if point p is before or after t. considering a reloaded counter , as the timer rolls over at its maximum value, the situation is more complex. figure 28-27 greater/equal concept the observation window determines the space in time where writing the value t to the comparator will lead to correct observation (meaning, there is an event if ?after?; there is no event if ?before?). considering an observation window, an event (threshold t) is mct05936 tim e r eloaded counter t p3 p4 p2 p1 i nfinite counter www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-42 v1.1, 2011-03 gpta ? v5, v1.0 programmed and then the window is split into two windows, the ?after? window and the ?before? window ( figure 28-28 ). if the timer lies in the ?after? window at the time of programming the threshold, the event is performed immediately. if it lies in the ?before? window, the event will happen later when the timer reache s the threshold t. the ?before? window refers to a ?prediction range?, and the ?after? window refers to the ?history buffer?. from a practical point of view, once the value t is determined, it is necessary to calculate the observation window (position and width). before updating the value t, the application must assure that the observation window was entered but has not yet been left. the width of the observation window cannot exceed the timer period. to support reloaded counters where the overflow can occur within the observation window, a signed comparison is performed. figure 28-28 before and after windows mct05937 t observation window before after www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-43 v1.1, 2011-03 gpta ? v5, v1.0 comparison between unsigned and signed compare to be able to support different timer periods and to support correct observation even beyond timer overflow, the gpta ? v5 embeds the scalable and signed greater/equal comparator. using a signed comparison allows one overflow of the timer to occur within the observation window. this is illustrated in figure 28-29 . using a signed compare in order to take into account the timer overflow, the comparator window is introduced. the comparator window is centered to the point t and its width can be selected by the user. figure 28-29 unsigned versus signed compare when the timer range is a multiple of 2 and because the comparator is scalable, the observation window and the comparator window are identical. see figure 28-30 . mct05938 u nsigned c ompare t ba t ba t ba s igned c ompare t ba t ba t ba t : threshold b : before a: after ideal case where the timer period is a power of 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-44 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-30 observation and comparator windows (timer is a power of 2) the scalable and signed greater/equal comparator scheme leads to a limitation that must be considered when programming the gpta ? v5 module. if the timer range is not a power of 2, the comparator window (always a power of 2) will no longer match the timer period. this will impact the observation window as described in the following paragraph. observation window for reloaded timers (period is not a power of 2) in that case, the comparator window must exceed the timer period. the user must find the comparator window (by selecting the scale factor k) which fits best the timer period. the following equation must apply: 2 k < period 2 2 k (28.1) figure 28-31 and figure 28-32 show that one part of the comparator window must be discarded in order to avoid inconsistency, resulting in the observation window. mct05939 before after t comparator window (= 2 2 k ) observation window (= period) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-45 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-31 observation window when threshold t is high figure 28-32 observation window when threshold t is low mct05940 observation: (performed by g/e compare) before after t before comparator window (= 2 2 k ) observation window (= period) should be after! !! core observation window mct05941 o bservation: ( performed by g /e compare) before comparator window observation window should be before!!! core observation window after after t www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-46 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-33 the core observation window a comparison of the previous figures shows that the position of the observation window with respect to t is dependent on the value of t itself. that means the user, before updating the comparator with t, needs to calculate the observation window as a function of t. to avoid this calculation, a core observation window can be defined that is independent of t. it will always be centered on t, whatever its value. however, one particularity exists when using the core observation window: the size of the core observation window varies depending on two static values: the timer period and the comparator window?s sizes. in particular, the core observation window reduces as the value of the timer period is just after a power of 2. this is shown in figure 28-34 . for any timer period (whatever the range) a nd any threshold position, a symmetrical core observation window of a statically defined size can be determined. figure 28-34 core observation window sizes versus period sizes mct05942 core observation windo w t before after comparator window = 2 2 k period is not a power of 2 m m p eriod = m - m + 1 mct05943 1 2 4 8 16 32 period observation window core observation window width of core observation window = 2 x (period - 2 k ) condition: 2 k < period 2 2 k www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-47 v1.1, 2011-03 gpta ? v5, v1.0 implementation the hardware implementation of the scalable and signed/unsigned greater/equal compare is illustrated in figure 28-35 . the function consists of subtracting the threshold t from the gt timer value. the result is in 2s complement format. the result?s sign bit and the 15 most significant bits are at available for observation. one of those bits is selected according to the mode of operation (unsigned or signed) and the period length (bit field gtctrk.sco). this bit drives the tge (timer greater equal) flag. unsigned compare: select sign bit (sco = 0f h ) signed compare: select one of the 15 most significant result bits (sco = 00 h to 0e h ) note: how to choose one of the 15 bits is explained later. figure 28-35 comparator implemented by a subtraction circuitry the interpretation of the selected result bit is provided in the following simple example: for a 4-bit timer, the subtraction of the threshold t from the timer value, leads to a 4-bit signed result, as illustrated in figure 28-36 . this example is selected for simplicity although 4-bit periods are not covered by the implementation. when using unsigned compare, the sign bit s is selected. if it equals 0, the result is positive, indicating that the timer is greater or equal the threshold, and hence after . if it equals 1, the result is negative, and the observation indicates before . when using signed compare, the result bit r 3 can be selected and interpreted, provided that the timer period is at least 9. here, the range of the result can be split into four sub- mca05944 multiplexer subtract difference sign bit result result [23-9] sc o + - g t value internal bus (new threshold) tge flag www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-48 v1.1, 2011-03 gpta ? v5, v1.0 ranges. because the result is in 2s complement format, a value of 0 for r 3 is interpreted as after , and a value of 1 is interpreted as before . a comparison of figure 28-36 and figure 28-37 shows why this proceeding leads to correct interpretation within the observation window. figure 28-37 shows the case of a period equal a multiple of 2. figure 28-36 result and observation for a 4-bit timer mca04616 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 s 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 r 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 result in 2s complement after s = 0 before s = 1 after r 3 = 0 before r 3 = 1 after r 3 = 0 before r 3 = 1 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 result in decimal observation unsigned compare observation signed compar e using r 3 r 1 r 2 r 3 mca05945 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-49 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-37 result and observation (period = 16) figure 28-38 shows the case of a period of 12 which is not a power of 2. here again, the table in figure 28-36 applies. figure 28-38 result and observation (period = 12) mct05946 0 15 evaluation of s evaluation of r 3 s = 1 s = 0 r 3 = 1 r 3 = 0 t evaluation of: result = timer - t n 3 n 2 n 1 n 0 t 3 t 2 t 1 t 0 - r 3 r 2 r 1 r 0 s timer value threshold value result value with sign bit s example for 4-bit timer (n = 4): unsigned compare: the bit evaluated is s signed compare (on bit 3): the bit evaluated is r 3 mct05947 4 1 5 evaluation of r 3 r 3 = 1 r 3 = 0 t evaluation of: result = timer - t n 3 n 2 n 1 n 0 t 3 t 2 t 1 t 0 - r 3 r 2 r 1 r 0 s timer value threshold value result value with sign bit s r 3 = 1 comparator observation window window core observation window www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-50 v1.1, 2011-03 gpta ? v5, v1.0 the previous examples show that the result bit to select for observation (r 3 ) corresponds to the comparator window?s size (k = 3). considering the case in which the period is not a multiple of 2, choose a comparator window whose width is between 1 and 2 times the timer period: 2 k < period 2 2 k (28.2) in no case may the comparator window be equal to or greater than twice the period. k represents the result bit to select. how to proceed ? unsigned greater/equal compare: sco bit field = 0f h (15 d ) thereby, the sign bit of the result is selected to drive tge flag. this setting is valid for all possible periods. the observation window always matches the period. ? signed greater/equal compare: depending on the period, the appropriate k is selected, so that: period = m - m + 1 (= max - min + 1) (28.3) 2 k < period 2 2 k (28.4) sco bit field = 0 to 0e h (0 to 14 d ) thereby, the result bit r k is selected to drive tge flag. this setting is possible for periods greater than 512. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-51 v1.1, 2011-03 gpta ? v5, v1.0 the width of the core observation window is defined by: 2 (period - 2 k ) (28.5) as a consequence, the width of the ?before? window within the core observation window is (period - 2 k ) and the width of the ?after? window within the core observation window is (period - 2 k ), including the value t. additional informati on: illustration on the general case the previous section illustrated the greater/equal compare for the particular case of a 4-bit timer. the purpose of this section is to describe the implementation from a general point of view, that is, for a timer period equal to m - m + 1. in the following figures, the x axis indicates the timer value (elapsing time) and the y axis indicates the threshold value t. the 45 line starting at (m, m) represents the position in time of t. the graphic shows the observation performed by the hardware for all cases of t (m t m). table 28-1 period range depending on selected k 2 k < period 2 2 k k sco bit field (decimal) 0 < period 512 not covered by implementation 512 < period 1024 9 0 1024 < period 2048 10 1 2048 < period 4096 11 2 4096 < period 8192 12 3 8192 < period 16384 13 4 16384 < period 32768 14 5 32768 < period 65536 15 6 65536 < period 131072 16 7 131072 < period 262144 17 8 262144 < period 524288 18 9 524288 < period 1048576 19 10 1048576 < period 2097152 20 11 2097152 < period 4194304 21 12 4194304 < period 8388608 22 13 8388608 < period 16777216 23 14 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-52 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-39 illustrates the unsigned co mpare. a particular case is shown in which, for a higher value of t, the observation indicates ?before? at the beginning of the period, and until the timer reaches the value t. thereaft er, the observation switches to ?after? and remains there until the timer exits the period. figure 28-39 graphical representation of unsigned compare figure 28-40 illustrates the signed compare where the period equals a multiple of 2 (that means m - m + 1 = 2 2 k ). in this case, for a higher value of t, the observation indicates ?after? at the beginning of the period (not yet inside the observation window). when entering the observation window, ?before? is indicated until the timer reaches the value t. thereafter, the observation switches to ?after? and remains there until the timer exits the observation window. this graphic can be related to table 28-37 where the comparator window equals the period, and the observation window is always centered on the threshold t. after before mct0594 8 after before tim er m m m threshold m v alue of t t (point in time) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-53 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-40 graphical representatio n of signed compare (period = 2 2 k ) the figure 28-41 illustrates the signed compare where the period may also be unequal a multiple of 2. the graphical representation of this general case is analogous to the one described in figure 28-31 . if the period is not a multiple of 2, the graphical representation of the signed compare shows a discontinuity in the ?before? and ?after? ranges. indeed, the widths of the ?before? and ?after? windows are not constant, as they depend on the value t. as a consequence, the observation window is not centered on t. the result is that the position of the observation window would have to be re-evaluated for each value t (i.e. determining the widths of the ?after? and the ?before? window). for this calculation, the principal characteristic is shown in table 28-41 (2 2 k - period = comparator window - period). mct0594 9 before after time r m m m threshold m v alue of t after before observation window www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-54 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-41 graphical represent ation of signed compare (2 k < period 2 2 k ) figure 28-42 shows how the observation window is positioned with respect to t. it also shows the core observation window that is always centered on t and which has a constant width. figure 28-42 core observation window in the graphic before mct05950 after before before time r m m m threshold m v alue of t t (point in time) 2 2 k - period = comparator window - period after after before before mct05951 time r m m m threshold m point t1 observation window core observation window point t2 after after v alue of t1 v alue of t2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-55 v1.1, 2011-03 gpta ? v5, v1.0 28.3.3.2 global timer cell (gtc) the gpta ? v5 provides 32 global timer cells (gtc00 to gtc31) used for capture/compare operations. registers the following registers are assigned to a gtck (k = 00-31): ? gtcctrk = global timer cell control register k (see page 28-187 ) ? gtcxrk = global timer cell x register k (see page 28-191 ) ? srsc1 = service request state clear register 1 (see page 28-226 ) ? srss1 = service request state set register 1 (see page 28-227 ) features ? 24-bit based timer cells related to two global timers gt0 and gt1. ? capture mode on rising, falling or both edges with following actions: ? service request generation ? output signal transition generation (set, reset, toggle the output signal) ? compare mode on equal compare, or greater than, or equal to compare with following actions: ? service request generation ? output signal transition generation (set, reset, toggle the output signal) ? capture (after compare match) the value of the selected global timer or the opposite global timer ? one shot mode allows the selected (capture or compare) mode to be stopped after the first event. ? flexible mechanism to link pin actions and allow complex combination of cells. (a cell has the ability to propagate actions ov er adjacent cells with higher number, in order to perform complex waveforms such as pwms). architecture the architecture of a gtc is shown in figure 28-43 . each gtc has a multiplexer that allows selection of the gt0 or gt1 global timer value bus as data source, a 24-bit capture/compare register gtcxrk, and a 24-bit equal comparator. the 32 global timer cells (gtc00 to gtc31) have the following inputs: ? two global timer value buses, gtv0 and gtv1, coming from the two global timers and carrying the gt0 and gt1 timer values ? two inputs, tev0 and tev1, reporting gt0 and gt1 timer value updates ? two inputs, tge0 and tge1, reporting the result of the gt0 and gt1 compare operations ? a trigger input (gtckin) that is connected via the gtc input multiplexer to one of the following signal sources: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-56 v1.1, 2011-03 gpta ? v5, v1.0 ? external port lines ? local timer cell outputs ? filter and prescaler cell outputs ? internal input signals intx ? two action mode inputs (m0i, m1i) coming from the adjacent gtc with lower order number (m1i and m0i of gtc00 are 0) each gtc provides the following outputs: ? one data output (gtckout) that can be connected to: ? external port lines ? inputs of an msc module ? outputs and/or inputs of local timer cell inputs ? two action mode outputs (m0o, m1o) going to the adjacent gtc with higher order number ? one service request line (sqsk) triggered by a capture/compare event. figure 28-43 architecture of global timer cells mca0595 2 gtck control logic m1o gtckin x (24-bit value) gtv1 = gtcxrk mux mux mux m0o m1i m0i gtckou t sqsk gtv0 tge0 tev0 tev1 tge1 from gt0 from gt1 connected to m1o/m0o of previous gtck-1 connected to m1i/m0i of next gtck+1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-57 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-44 shows how the gtcs are arranged and connected to the adjacent gtcs and with the global timers gt0 and gt1. figure 28-44 gtc interconnections note: cascading of gtcs is limited. TC1798 specific details are given on page 28-306 . mca0595 3 from gtc29 global timer cell gtc00 m1i m0i m1o m0o gtc00in gtc00ou t sqs00 gtv1 bus / tge1 / tev1 gtv0 bus / tge0 / tev0 global timer gt0 global timer cell gtc01 m1i m0i m1o m0o gtc01in gtc01ou t sqs01 global timer cell gtc30 m1i m0i m1o m0o gtc30in gtc30ou t sqs30 global timer cell gtc31 m1i m0i gtc31in gtc31ou t sqs31 to gtc02 global timer gt1 sqt1 sqt0 clock bus . . . . . . . . . . . . . . . . 00 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-58 v1.1, 2011-03 gpta ? v5, v1.0 capture mode the capture function of a gtck cell is pe rformed on a rising edge (gtcctrk.red = 1), a falling edge (gtcctrk.fed = 1) or both edges of the selected gtckin input signal. on the requested event, the gtc: ? copies the 24-bit value of the selected global timer into the 24-bit capture/compare register gtcxrk.x, ? sets the gtck service request flag in register srss1/srsc1, ? activates the service request output sqsk if control register bit gtcctrk.ren = 1, ? performs an gtckout output signal line manipulation (set, reset, toggle, unchanged) as defined by bit field gtcctrk.ocm, ? transfers an action request, generated by an internal event or received on the m1i, m0i input lines, to the m1o, m0o output lines. compare mode in the compare code of a gtck cell, several functions can be performed when the value of the selected global timer matches and/or exceeds the value stored in register gtcxr. with gtcctrk.ges = 0 an ?equal compare? match is selected while gtcctrk.ges = 1 selects a ?greater equal compare? match. on the requested event, the gtc: ? sets the gtck service request flag in register srss1/srsc1, ? activates service request output sqsk if control register bit gtcctrk.ren = 1, ? performs an gtckout output signal line manipulation (set, reset, toggle, unchanged) as defined by bit field gtcctrk.ocm, ? transfers an action request, generated by an internal event or received on the m1i, m0i input lines, to the m1o, m0o output lines. if a greater or equal compare is selected , the condition is evaluated only when the compare value is written to the gtcxrk regi ster. the user should then assure that the gtc is already enabled so that the evaluation can take place. capture after compare mode when bit gtcctrk.cac = 1 and a compare ev ent has occurred, register gtcxr is loaded with: ? the global timer value as selected by bit field gtcctrk.mod (gtcctrk.cat = 0), ? the alternate global timer value (gtcctrk .cat = 1). if a greater or equal compare match has been detected, the gtck should be set into one shot mode in order to prevent double capturing. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-59 v1.1, 2011-03 gpta ? v5, v1.0 one shot mode in one shot mode (gtcctrk.osm = 1), a self -disable of gtck is executed after each gtc event (gtcctrk.cen = 0). the current state of a gtck can be evaluated by reading the control register flag bit gtcctrk.cen. note: the contents of the gtck capture/co mpare register gtcxrk are write-protected for capture_after_compare in single shot mode. write protec tion is activated when the compare value is reached and released after a read access of register gtcxrk occurred. data output line control the data output gtckout can be controlled by the gtck itself and by adjacent gtcs with a lower order number. for this pur pose, two communication signals between gtcs are available connecting all gtcs via their m1i/m0i inputs and their m1o/ m0o outputs respectively (see figure 28-45 ). figure 28-45 gtc output operation and action transfer ((event and cen) or oia) and (ocm != x00 b ) mca0595 4 0 ff gtckou t 1 & & m1o event ocm0 m0i m1i f gpta oia byp ocm1 ocm2 eoa reset m0o & cen out note: all bits/flags shown in this figure are located in register gtcctrk. 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-60 v1.1, 2011-03 gpta ? v5, v1.0 when bit gtcctrk.ocm2 is reset, the data ou tput gtckout is only controlled by the local gtck. a set, reset, toggle, or hold operation can be performed as selected by bits gtcctrk.ocm1 and gtcctrk.ocm0 ( table 28-2 ). when bit gtcctrk.ocm2 is set, the data out put gtckout is affected either by the local gtcctrk.ocm1 and gtcctrk.ocm0 bits or by the m1i/m0i input lines, which are connected to the adjacent gtck-1 global timer output lines m1o/m0o. an enabled gtck event superimposes an ac tion request generated simultaneously by the m1i/m0i inputs. when the bypass bit gtcctrk.byp is cleared , the m1o/m0o output lines logically or together the local gtck events and, if enabled by bit gtcctrk.ocm2, the action requests received via the m1i/m0i input lines. when bit gtcctrk.byp is set to 1, a local gtck event will not modify the m1o/m0o output lines. the gtckout output line can be connected to output ports, on-chip peripheral inputs, and/or ltc inputs via the i/o line sharing block (see page 28-98 ). gtckout can be updated directly by software (setting bit gtcctrk.oia = 1) or upon a timer, capture or compare event within the local gtck or a pr eceding gtc. the current state of the data output line can be evaluated by re ading status flag gtcctrk.out. table 28-2 selection of gtc output oper ations and action transfer modes bit field ocm[2:0] local capture or compare event m1o/m0o byp = 0 m1o/m0o byp = 1 state of local data output line 0 0 0 not occurred occurred 0 0 0 0 0 0 0 0 not modified not modified 0 0 1 not occurred occurred 0 0 0 1 0 0 0 0 not modified inverted 0 1 0 not occurred occurred 0 1 0 0 0 0 0 0 not modified 0 0 1 1 not occurred occurred 0 1 0 1 0 0 0 0 not modified 1 1 0 0 not occurred occurred m1i m1i m0i m0i m1i m1i m0i m0i modified according m1i/m0i modified according m1i/m0i 1 0 1 not occurred occurred m1i 0 m0i 1 m1i m1i m0i m0i modified according m1i/m0i inverted 1 1 0 not occurred occurred m1i 1 m0i 0 m1i m1i m0i m0i modified according m1i/m0i 0 1 1 1 not occurred occurred m1i 1 m0i 1 m1i m1i m0i m0i modified according m1i/m0i 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-61 v1.1, 2011-03 gpta ? v5, v1.0 cell enabling after reset all gtcs are disabled. a gtc may be enabled by resetting gtctrk. eoa (enable-of-action) to 0 in capture mode or compare mode using a standard write assembler operation 1) . because bit eoa is hardware protected, intrinsic read-modify- write assembler operations 2) only enable the gtc if bit eoa is modified from 1 to 0. cell deactivation by programming a gtc to capture mode with no edge selected (gtcctrk.fed = gtcctrk.red = 0), an enabled cell becomes inactive and performs no action, but continues passing action commands via the communication link from m1i/m0i to m1o/m0o. cell enabling on event a gtc can be enabled by an event in a gtc with lower index number. for this purpose, the local event function of an gtc mu st be temporary disabled by setting gtcctrk.eoa (enable-of-action) to 1. because bit eoa is hardware protected, intrinsic read-modify-wr ite assembler operations 2) only disable the gtc if bit eoa is modified from 0 to 1. both operations will clear gtcctrk.cen and now a local event cannot affect the gtc. when a preceding gtc generates and communicates an event (or oia) via its communication link m1o/m0o, at least one of the m1i/ m0i input lines changes its state to 1. this condition clea rs bit gtcctrk.eoa of the disabled gtc via the or gate as shown in figure 28-45 . now gtcctrk.cen is set and the cell is enabled for local events. it is also possible to enable the following gtc via the communication link for local events. for this purpose, the gtcctrk.eoa bit of the following gtc must be set, too. if bit gtcctrk.ocm2 of the preceding gtc is 1, the enable action will take place at the same time as in the preceding gtc. otherwise, the gtc will be enabled later on a capture/compare event in the preceding gtc, provided ocm0 or ocm1 of this gtc is different from 0. in this way, several gtcs can be enabled at the same time or one after the other. normally, the cells will be used in one shot mode, and an interrupt will be generated after the last event to evaluate the data and to prepare the next enable sequence. a disabled gtc (gtcctrk.cen = 0) behaves as an inactive cell. 1) standard tricore ? write operations: st.a, st.b, st.d, st.da, st.dd, st.hst.q, st.w standard pcp write operations: st.f, st.if,bcopy, copy 2) intrinsic tricore ? read-modify-write operations: ldmst, st.t, swap intrinsic pcp read-modify-write operations: set.f, xch.f, clr.f www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-62 v1.1, 2011-03 gpta ? v5, v1.0 logical operating cells the inter-cell communication architecture allows implementation of a complex waveform generation to be distributed over several gtcs, controlling a common port pin. for example, one gtc may be configured in capture mode triggered by a rising edge detected on the associated input pin line. the related interrupt service routine can increment the captured timer value by a delay offset and store the result in the gtcxr register of the adjacent gtc configured in compare mode. upon a compare event in the second gtc, the output port line of a third gtc can be set via m1o, m0o interface lines. when the gtcxr register of the third cell is loaded with another compare value by the interrupt service routine related to the second gtc, the output port line may be reset by the next compare event within gtc3. this logical operating cell provides an output signal with programmable pulse width and configurable delay with minimal software overhead. gtc service request the service request output sqsk of a global timer cell gtck is controlled as shown in figure 28-46 . when the gtck service request condition becomes active, the service request flag always becomes set. the service request output sqsk is only activated if it is enabled by the enable bit gtcctrk.ren . additional information about service request and interrupt handling is given on page 28-123 . figure 28-46 gtck service request generation mca05955 ren gtcctrk gtck gtck gtck srss1 (read) srsr1 (read) set sqs k srss1 (write) srsc1 (write) g tck service request b ecomes active set reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-63 v1.1, 2011-03 gpta ? v5, v1.0 gtc application examples the global timers together with gtcs can typically be used for input signal timing analysis of very complex input signals as well as for generation of complex output signals. figure 28-47 shows a configuration with global timer 0 and four gtcs, which is used in the following two examples: ? example 1: complex input signal capturing and analyzing ? example 2: complex periodical output signal generation figure 28-47 complex input/output signal capturing/generation with gts and gtcs complex input signal capturing and analyzing in this application example, one input signal from a gtc input multiplexer group becomes analyzed from a timing reference po int for three consecutive signal transitions. this common input signal (e.g. a port line) is selected by a gtc input multiplexer group (gimg) common for gtc01, gtc02, and gtc03 (see also page 28-111 ). the gtcs are configured in the following way: ? gt0 operates as free-running up-counting 24-bit timer with reload to gtrev0.rev on overflow. it is clocked by one clock signal from the clock bus. ? gtc00 operates in compare mode with timer gt0. the compare match event is reported on the m0o/m1o output lines to the gtc01. ? gtc01 operates in capture mode at rising edge with enable-on-action set (eoa set) and one shot mode enabled (osm set). mca0595 6 gtc00 m1i m0i m1o m0o global timer gt0 clock b us 00 gtv0 gtc01in gtc02in gtc03in gimg xy tge0 tev0 gtc01 m1i m0i m1o m0o gtc02 m1i m0i m1o m0o gtc03 m1i m0i m1o m0o gtc03out www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-64 v1.1, 2011-03 gpta ? v5, v1.0 ? gtc02 operates in capture mode at falling edge with enable-on-action set (eoa set) and one shot mode enabled (osm set). ? gtc03 operates in capture mode at rising edge with enable-on-action set (eoa set) and one shot mode enabled (osm set). with the compare event of gtc00 (time stamp), gtc01 becomes active and waits for the next rising edge at its data input gtc01in. while gtc01 is active, gtc02 and gtc03 are inactive. when gtc01 detects a rising edge at its data input, it captures the current gt0 value into its gtcxr01 register, enables gtc02, and becomes disabled afterwards because it was operating in one shot mode. when gtc02 detects a falling edge at its data input, it captures the current gt0 value into its gtcxr02 register, enables gtc03, and becomes disabled afterwards because it was operating in one shot mode. when gtc03 detects a rising edge at its data input, it captures the current gt0 value into its gtcxr03 register and becomes disabled afterwards because it was operating in one shot mode. optionally, the capture event at gtc03 may generate a service request to indicate that the three capture events have occurred and the captured values can be checked by software. note that all of th ese capture events are executed by the gpta ? v5 hardware without any software interactions and with a resolution of the gt0 clock rate. figure 28-48 complex input signal analysis/capturing with gtcs don?t care don?t care mcd0595 7 data input gtcxin (x = 01,02,03) gt0 timer value timer value g tcxr03.x g tcxr02.x g tcxr01.x time stamp tim e g tcxr00.x gtc01 active gtc02 active gtc03 active www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-65 v1.1, 2011-03 gpta ? v5, v1.0 complex periodic output signal generation this application example uses the gt /gtc configuration as shown in figure 28-47 . the generated output signal is available at gtc03out. the gtc input signals of the gt/gtc configuration are not used in this example. ? gt0 operates as free-running up-counting 24-bit timer with reload to gtrev0.rev on overflow. it is clocked by a clock signal from the clock bus. its reload period determines the period of the generated pwm output signal. ? gtc00 operates in compare mode with timer gt0 with enable-on-action set (eoa set) and one shot mode enabled (osm set). furthermore, the output gtc03out becomes set on a local event (ocm = x11 b ). ? gtc01 operates in compare mode with timer gt0 with enable-on-action set (eoa set) and one shot mode enabled (osm set). furthermore, the output gtc03out becomes reset on a local event (ocm = 110 b ). ? gtc02 operates in compare mode with timer gt0 with enable-on-action set (eoa set) and one shot mode enabled (osm set). furthermore, the output gtc03out becomes set on a local event (ocm = 111 b ). ? gtc03 operates in compare mode with timer gt0 with enable-on-action set (eoa set) and one shot mode enabled (osm set). furthermore, the output gtc03out becomes reset on a local event (ocm = 110 b ). figure 28-49 complex output signal generation with gtcs at the start of the time period (reload of gt0), gtc00 becomes active and waits for the compare event. at this event, it sets the output signal gtc03out, enables gtc01 for mcd05958 gt0 timer value timer value start of time period tim e ffffff h gtc00 active gtc01 active gtc02 active gtc03 active d ata output g tc03out g tcxr03.x g tcxr02.x g tcxr01.x g tcxr00.x g trev0.rev www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-66 v1.1, 2011-03 gpta ? v5, v1.0 compare operation, and becomes disabled af terwards because it was operating in one shot mode. when the gtc01 compare event occurs, the output signal gtc03out is reset, gtc02 becomes enabled, and gtc0 1becomes disabled because it was operating in one shot mode. when the gtc 02 compare event occurs, the output signal gtc03out is set, gtc03 becomes enabled, and gtc02 becomes disabled because it was operating in one shot mode. when the gtc03 compare event occurs, the output signal gtc03out is reset, and gtc02 bec omes disabled because it was operating in one shot mode. the capture event at gtc03 should generate a service request to indicate that the three compare events have occurred and that gtc0 1 can be enabled again (setting eoa and osm). note that all of the compare events are executed by the gpta ? v5 hardware without any software interactions and with a resolution of the gt0 clock rate. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-67 v1.1, 2011-03 gpta ? v5, v1.0 28.3.3.3 local timer ce ll (ltc00 to ltc62) ltc00 to ltc62 are functionally identical. the functionality of ltc63 is different to ltc00 to ltc62 and therefore described separately at page 28-79 . registers the following registers are assigned to a local timer cell ltck (k = 00-62): ? ltcctrk = local timer cell control register k (see page 28-192 ) ? ltcxrk = local timer cell x register k (see page 28-205 ) ? srsc2 = service request state clear register 2 (see page 28-228 ) ? srsc3 = service request state clear register 3 (see page 28-230 ) ? srss2 = service request state set register 2 (see page 28-229 ) ? srss3 = service request state set register 3 (see page 28-231 ) features ? 16-bit based timer cells providing capture, compare, and timer functions. ? capture mode on rising, falling or both edges with following actions: ? service request generation ? output signal transition generation (set, reset, toggle the output signal). ? compare mode on equal compare of the corresponding (reset-)timer ltc with following actions: ? service request generation ? output signal transition generation (set, reset, toggle the output signal). ? timer mode incremented on hardware signal with following actions: ? event generation at overflow ? service request generation ? output signal transition generation (set, reset, toggle the output signal). ? reset timer mode allows the selected ltc to be reset by an adjacent cell. coherent update capability of adjacent ltcs for pwm management is provided. ? one shot mode allows the selected (capture, co mpare, timer or reset timer) mode to be stopped after the first event. ? flexible mechanism to link pin actions and allow complex combination of cells. (a cell has the ability to propagate actions ov er adjacent cells with higher number, in order to perform complex waveforms such as multi channel pwms). architecture the architecture of an ltc is shown in figure 28-50 . each ltc has a 16-bit capture/compare register and a 16-bit equal to comparator. the first 63 local timer cells (ltc00 to ltc62) have the following inputs: ? a local input data bus (yi) carrying the local timer value of the adjacent ltc with lower order number (yi of ltc00 is always 0000 h ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-68 v1.1, 2011-03 gpta ? v5, v1.0 ? a ti input reporting the occurrence of a local timer value update of the adjacent ltc with lower order number (ti of ltc00 is 0) ? a si input used by the ltc in compare mode as enable line (si of ltc00 is 0) ? four action mode inputs (m3i, m2i, m1i, m0i) coming from the adjacent ltc cell with lower order number (m3i, m2i, m1i, and m0i of ltc00 are 0) ? an ei input reporting an event coming fr om the adjacent ltc with higher order number ? a trigger/clock/enable input ltckin hooked to one of the following signals sources: ? external port lines ? gtc00 to gtc31 outputs ? clock bus signals ? pdl0 or pdl1 outputs ? internal gpta ? v5 kernel input signals intx (x = 0-3) figure 28-50 architecture of local timer cells each ltc provides the following input / output signals: ? one data output line (ltckout) that can be connected to: ? external port lines ? inputs of an msc module ? outputs and/or inputs of global timer cell inputs ? one ltc prescaler clock i nput (ltcpre) for timer mode ? one service request line (sqt) triggered by a capture/compare event ? a local output data bus (yo) carrying the local timer value to the adjacent ltc with higher order number or the value on yi mca05959_mod ltck control logic ltcpre ltcxrk ltckout sqtk from/to previous ltck-1 mux eo ti m0i m1i si ei to m0o m1o so yo yi to/from next ltck+1 = x (16-bit capcom) ltckin m2i m3i m2o m3o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-69 v1.1, 2011-03 gpta ? v5, v1.0 ? a to output reporting the occurrence of a local timer value update to the adjacent ltc with higher order number ? an so output used by the adjacent lt c with higher order number as enable signal for a compare function ? an eo output reporting the occurrence of a local event to the adjacent ltc with lower order number ? four mode lines (m3o, m2o, m1o, m0o) going to the adjacent ltc with higher order number. figure 28-51 shows the arrangement of the ltcs and the connections with adjacent ltcs. ltc63 is a local timer cell that differ s from all other ltcs (ltc00 to ltc62). ltc63 is described in detail on page 28-79 . figure 28-51 interconnections between the ltcs note: cascading of ltcs is limited. TC1798 specific details are given on page 28-306 . from ltc60 local timer cell ltc00 m3i m2i ltc00in ltc00out sqt00 to ltc02 . . . . . . . . . . . . . . . . ti eo si m3o m2o ti ei so 0000 h yi yo local timer cell ltc01 m3i m2i ti eo si m3o m2o to ei so yi yo local timer cell ltc61 m3i m2i ti eo si m3o m2o to ei so yi yo mca05960_mod local timer cell ltc62 m1i m0i ti eo si m1o m0o to ei so yi yo local timer cell ltc63 ti eo yi ltcpre ltc01in ltc01out sqt01 ltc61in ltc61out sqt61 ltc62in ltc62out sqt62 ltc63in ltc63out sqt63 0 00 0 m1i m0i m1o m0o m1i m0i m1o m0o m1i m0i m1o m0o m1i m0i m1o m0o 00 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-70 v1.1, 2011-03 gpta ? v5, v1.0 operating mode selection the operating mode of an ltc ? free-running timer, reset timer, capture, or compare mode ? is defined by bit field ltcctrk.mod. free-running timer mode the content of the local timer cell register ltcxrk is initialized by a software write operation. ltcxrk is incremented by the selected ltckin input signal. level or edge sensitive mode can be selected for ltckin (see page 28-72 ). in level sensitive mode prescaler clock from the cdc (ltcpre) can be used to reduce the timer frequency. every change of the local timer cell regist er ltcxrk (increment, reset, or write access) is indicated by output signal to = 1 . when the timer reaches its overflow value (ffff h ), ? the ltck service request flag is set, ? the service request output sqtk is activa ted if control register bit ltcctrk.ren = 1, ? the ltck output line ltckout can be altered (set, reset, toggle, unchanged), ? the ltckout output line can be altered (set, reset, toggle, unchanged), depending on bit field ltcctrk.ocm, ? an action request, generated by an ltck internal event or received on the m1i/m0i input lines, is transferred via the m1o/m0o output lines to the ltc with higher order number (ltck+1). the event output line eo is also activated (set to high) by a software reset when writing ffff h to register ltcxrk. reset timer mode an ltc that is configured in reset timer mode provides the same functionality as in free-running timer mode, but is extended by two additional features: ? the local timer cell register ltcxrk can be reset to ffff h via the ei line, which can be activated by an event that occurred in the adjacent ltc with higher order number. ? if bit ltcctrk.cud is set to 1, the ei line reset event also toggles the logic state of the so output line before it clears register bit ltcctrk .cud automatically. by accessing register bit ltcctrk.slo, the st ate of the timer?s output line so can be read or explicitly written. capture mode in capture mode, the ltckin input signal is used for capture function. level or edge sensitive modes can be selected (see page 28-72 ). on a capture event, the ltck: ? copies the state of the local input data bus (yi) to the ltcxrk register (ltc00 always copies 0000 h ), ? sets the ltck service request flag, www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-71 v1.1, 2011-03 gpta ? v5, v1.0 ? activates the service request line sq tk, if ltcctrk.ren is set to 1, ? changes the ltckout output line state (set, reset, toggle, unchanged), depending on bit field ltcctrk.ocm and the m1i/ m0i input line state, ? generates and/or passes an action request via the m1o/m0o output lines to the ltc with higher order number (ltck+1), ? sets the event output eo to high level for one f gpta clock cycle. compare mode the compare mode can be enabled on a low, high, or both levels of the select input line si (ltcctrk.sol = 1, ltcctrk.soh = 1). the current state of si is indicated by bit field ltcctrk.sll and can be read. when the value of the local input data bus (yi) matches the ltcxrk contents, ? the ltck service request flag is set, ? the service request line sqtk is activated if ltcctrk.ren is set to 1, ? the ltckout output line state is changed (set, reset, toggle, unchanged), depending on bit field ltcctrk.ocm, ? an action request is generated and/or passed via the m1o/m0o output lines to the ltc with higher order number (ltck+1), ? the event output eo is set to high level for one f gpta clock cycle. note: to enable the compare function in all cases (on every timer or compare register update caused by a software write access, a reset event or a compare match), bits ltcctrk.sol and ltcctrk.soh must be set to 1. an inactive cell (ltcctrk.sol = ltcctrk.soh = 0, or si does not match the programmed value) will transfer the state of the event input line ei to the event output line eo. one shot operation when bit ltcctrk.osm is set to 1, a self-dis able is executed after each ltc event. the current state of ltck can be checked by reading the control register flag bit ltcctrk.cen. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-72 v1.1, 2011-03 gpta ? v5, v1.0 data input line control the data input line ltckin can operate in two modes (selected by bit ltcctrk.ilm): ? level sensitive or ? edge sensitive. in edge sensitive mode, the active edges are selected by bits ltcctrk.fed and ltcctrk.red. for the level sensitive mode, the active level of the input signal can be selected by bit fed/ail of register ltcctrk. depending on which source is selected for the input line by the input multiplexer, different clocking modes of the ltc cell are possible ( table 28-3 ). table 28-3 ltc data input line operation (in timer mode) input source level sensitive input line ltcctrk.ilm = 1 edge sensitive input line ltcctrk.ilm = 0 external signal (port line) the external signal operates as gating signal for the cell. the active input level can be selected with control register bit ail. additionally, the ltc prescaler mode can be enabled with ltcctrk.pen to reduce the timer frequency. the programmed function of the ltc is performed with the gpta ? v5 module clock frequency, or with the programmed prescaler clock ltcpre (see page 28-37 ). the programmed function of the ltc cell is performed on selected edge(s). internal clock bus line or pdl output or int input the programmed function is performed with the internal clock or pdl/int signal. note that all internal clock bus lines and pdl signals are active high pulses. the ltc prescaler mode and the input signal inversion must not be used. the programmed function of the ltc cell is performed on selected edge(s). in case of full speed gpta ? v5 module clock selection as input clock, the level sensitive mode must be selected. the edge sensitive mode will not produce an event in this special case. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-73 v1.1, 2011-03 gpta ? v5, v1.0 note: if capture mode and level sensitiv e input is selected for an ltck (bit ltcctrk.ilm = 1), a capture event occurs on every ltc timer clock event if the corresponding ltc input signal is a high level. data output line control the data output ltckout can be controlled by the ltck itself and by adjacent ltcs with a lower order number. for this purpo se, two communication signals between ltcs are available that make it possible to connect all ltcs via their m1i/m0i inputs and their m1o/ m0o outputs respectively ( figure 28-52 ). figure 28-52 ltc output operation and action transfer gtc output the gtc output signal operates as gating signal for the cell. the active input level can be selected with bit ltcctrk.ail. additionally, the ltc prescaler clock ltcpre can be enabled with bit ltcctrk.pen to reduce the timer frequency. the programmed function of the ltc cell is performed on selected edge(s). table 28-3 ltc data input line operation (in timer mode) (cont?d) input source level sensitive input line ltcctrk.ilm = 1 edge sensitive input line ltcctrk.ilm = 0 ((event and cen) or oia) and (ocm != x00 b ) mca05961_mod 0 ff ltckout 1 & & event ocm0 m0i m1i f gp ta oia byp ocm1 ocm2 eoa reset & cen out 1 note: all bits/flags shown in this figure are located in register ltcctrk. m3i gbyp m2i m0o m1o m3o m2o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-74 v1.1, 2011-03 gpta ? v5, v1.0 when bit ltcctrk.ocm2 is reset, the data out put ltckout is controlled only by the local ltck. a set, reset, toggle, or hold operation can be performed as selected by bits ltcctrk.ocm1 and ltcctrk.ocm0 (see table 28-4 ). when bit ltcctrk.ocm2 is set, the data output ltckout is affected either by the local ltcctrk.ocm1 and ltcctrk.ocm 0 bits or by the m1i/m0i input lines, which are connected to the adjacent ltck-1 global timer output lines m1o/m0o. an enabled ltck event superimposes an action reques t generated simultaneously by the m1i/m0i inputs. figure 28-53 direct, local bypass, and global bypass action request routing when the bypass bit ltcctrk.byp is cleared, the m1o/m0o output lines logically or together the local ltck events and, if enabled by bit ltcctrk.ocm2, the action requests received via the m1i/m0i input lines. when the bypass bit ltcctrk.gbyp is clea red, the action re quests received via m1i/m0i input lines, if enabled by bit ltcctrk.ocm2, are forwarded to the subsequent ltck+1 via the m3o/ m2o output lines. if ltcctrk.g byp is set to 1, the action requests received via m3i/m2i input lines ar e forwarded to the subsequent ltck+1 via the m3o/m2o output lines. therefore the m3i/m2i may be used to pass the action requests of a reseted timer cross a group of ltc generating a complex signal or providing coherent update. the two bypass bit ltcctr k.byp and ltcctrk.g byp enable three di fferent types of action request routing, a direct routing, a local bypass routing and a global bypass ltcx+2 action request x+2 action request x action_routing ltcx a.) direct ltcx b.) local bypass action request x action request x-1 action request x action request x-1 ltcx c.) global bypass action request x action request x-1 ltcx+1 action request x+1 action request x action request x+1 action request x-1 action request x-1 m1i/m0i m3i/m2i m1o/m0o m3o/m2o m1i/m0i byp=0 gbyp=1(or 0) m1i/m0i m3i/m2i m1o/m0o m3o/m2o m1o/m0o byp=1 gbyp=0 byp=0 gbyp=0 m3i/m2i m3o/m2o byp=0 gbyp=1 byp=1 gbyp=1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-75 v1.1, 2011-03 gpta ? v5, v1.0 routing. these three different types of action request routing is sketched in figure 28-53 . the direct routing uses only the action request lines m1i/m0i. all action request run done the same path. the m3i/m2i are forwarded unchanged to m3o/m2o (next cells). the local bypass copies all action request coming into a cell (m1i/m0i) to the outputs of the cell (m1o/m0o and m3o/m2o. the following cells do not see any action request generated within this locally bypassed cell. the global bypass routing copies all action request coming into a group of sequential cells (m1i/m0i) to the outputs of this gro up of sequential cells (m1o/m0o and m3o/m2o. the following cells do not see any action request generated within this group of cells. typically for edge aligned signals, the one action request for the edge is globally or locally bypassed, an all non edge aligned action request then locally generated within the group or local bypassed cell. within a group complex signals may be generated or two cells used for local coherent update (double action principle). table 28-4 selection of ltc output oper ations and action transfer modes bit field ocm [2:0] local event m1o/m0o state of local data output line byp = 0 byp = 1 gbyp =0 gbyp=1 gbyp = 0 gbyp = 1 0 0 0 no yes 0 0 0 0 0 0 0 0 0 0 0 0 m3i m3i m2i m2i not modified not modified 0 0 1 no yes 0 0 0 1 0 0 0 1 0 0 0 0 m3i m3i m2i m2i not modified inverted 0 1 0 no yes 0 1 0 0 0 1 0 0 0 0 0 0 m3i m3i m2i m2i not modified 0 0 1 1 no yes 0 1 0 1 0 1 0 1 0 0 0 0 m3i m3i m2i m2i not modified 1 1 0 0 no yes m1i m1i m0i m0i m1i m1i m0i m0i m1i m1i m0i m0i m3i m3i m2i m2i modified according m1i/m0i modified according m1i/m0i 1 0 1 no yes m1i 0 m0i 1 m1i 0 m0i 1 m1i m1i m0i m0i m3i m3i m2i m2i modified according m1i/m0i inverted 1 1 0 no yes m1i 1 m0i 0 m1i 1 m0i 0 m1i m1i m0i m0i m3i m3i m2i m2i modified according m1i/m0i 0 1 1 1 no yes m1i 1 m0i 1 m1i 1 m0i 1 m1i m1i m0i m0i m3i m3i m2i m2i modified according m1i/m0i 1 m3o/m2 o = 1) m3o/m2 o = m3i/m2i m3o/m2o = 1) m3o/m2o = m3i/m2i www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-76 v1.1, 2011-03 gpta ? v5, v1.0 the ltckout output line can be connected to output ports, on-chip peripheral inputs (otgs) and/or ltc inputs via the i/o line sharing block (see page 28-98 ). ltckout can be updated directly by software (setting bit ltcctrk.oia = 1) or upon a timer, capture, or compare event within the local ltck or a preceding ltc. the current state of the data output line can be evaluated by reading status flag ltcctrk.out. global bypass may also be used to move a group of local timer cells (consecutive local timer cells using the same local timer) into the previous group of local timer to e.g. hit a specific output pin. the previo us local timer group will therefore have some local timer before and some after the to be moved local timer group. because the local time bus yi and yo is driven by every ltc configured as timer regardless of the chosen bypass mechanism, special care ha s to be taken. an example is sketched in figure 28-54 . three local timer for an edge aligned pwm, using the same time base as the local timer cell group1 but different offsets (not edge aligned), is inserted into another group of local timer cells implementing an independent other signal. figure 28-54 global bypass action reques t routing for flexible cell allocation 1) if ocm2 = 0: m3o/m2o = 0/0 if ocm2 = 1: m3o/m2o = m1i/m0i ltcx+3 ltcx+2 ltcx+1 flexible_cell_alocation ltcx action request x action request x-1 m1i/m0i m3i/m2i m1o/m0o m3o/m2o byp=0 gbyp=0 byp=0 gbyp=1 action request +3 action request x+1 action request x-1 action request x+2 byp=1 gbyp=1 byp=0 gbyp=1 local timer cell group 2, e.g. pwm compare (period) compare (duty cycle) local timer cell group 1 local timer cell group 1 (continued) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-77 v1.1, 2011-03 gpta ? v5, v1.0 cell enabling after reset all ltcs are disabled. an ltc may be enabled by resetting ltcctrk. eoa (enable-of-action) to 0 in capture mode or compare mode using a standard write assembler operation 1) . because bit eoa is hardware protected, intrinsic read-modify- write assembler operations 2) only enable the ltc in capture mode or compare mode if bit eoa is modified from 1 to 0. if switching to timer mode, the ltc cell is enabled. in timer mode every write operation to bit 0?7 of ltcctrk will enable the ltc. cell deactivation by programming an ltc to capture mode with no edge selected (ltcctrk.ilm = ltcctrk.fed = ltcctrk.red = 0), an enabled cell becomes inactive and performs no action, but continues passing action commands via the communication link from m1i/m0i to m1o/m0o. output eo is inactive. alternatively, the ltc can be deactivated by setting it into compare mode with no active select line level (ltcctrk.sol = ltcct rk.soh = 0) but the communication link remains active. in this mode configurat ion, ei will be passed to eo. cell enabling on event an ltc can be enabled in capture mode or compare mode by an event in an ltc with lower index number. for this purpose, the local event function of an ltc must be temporary disabled by setting ltcctrk.eoa (e nable-of-action) to 1. because bit eoa is hardware protected, intrinsic read-modify-write assembler operations 2) only disables the ltc if bit eoa is modified from 0 to 1. both operations will clear ltcctrk.cen and now a local event cannot affect the lt c. when a preceding ltc generates and communicates an event (or oia) via the communication link m1o/m0o, at least one of the m1i/m0i input lines changes its state to 1. this condition clears bit ltcctrk.eoa of the disabled ltc via the or gate as shown in figure 28-52 . now ltcctrk.cen is set and the ltc is enabled for local events. it is also possible to enable the following ltc via the communication link for local events. for this purpose, the bit ltcctrk.eoa of this cell must be set, too. if bit ltcctrk.ocm2 of the preceding cell is 1, the enable action will take place at the same time as in the preceding cell. otherwise, the ltc will be enabled later on a capture/compare event in the prec eding ltc, provided ltcctrk.ocm0 or ltcctrk.ocm1 of this cell is different from 0. in this way, several ltcs can be enabled at the same time or one after the other. normally, the ltcs will be used in one shot mode, and a service request will be 1) standard tricore ? write operations: st.a, st.b, st.d, st.da, st.dd, st.hst.q, st.w standard pcp write operations: st.f, st.if,bcopy, copy 2) intrinsic tricore ? read-modify-write operations: ldmst, st.t, swap intrinsic pcp read-modify-write operations: set.f, xch.f, clr.f www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-78 v1.1, 2011-03 gpta ? v5, v1.0 generated after the last event to evaluate the data and to prepare the next enable sequence. a disabled ltc (ltcctrk.cen = 0) behaves as an inactive capture ltc. logical operating cells the inter-cell communication architecture al lows concatenation of several ltcs to a logical cell. a logical cell contains any number of ltcs communicating via m1 and m0 lines and ends at an ltc disabled for action i nput or transfer (such as an ltc configured as timer, reset timer or ltc initiated with ltcctrk.ocm2 = 0). therefore, the ltc with the lowest order num ber should be configured in reset timer mode, thus providing all other ltcs of the logical cell with a time base (yo) and a compare enable signal (so). another ltc of the same logical cell can be initiated in compare mode to reset the ltc via its event output line eo, when a programmed threshold value is reached (register ltcxr) and the current state of its select line input si matches the condition selected by the ltcctrk bits soh/sol. additional ltcs of the same logical cell can operate in capture mode triggered by a rising edge, falling edge, or both edges of a gpta ? v5 input line or a clock line of the clock bus. on the generated event, these ltcs capture the current contents of the timer cell, can generate a service request, can perform a manipulation of a gpta ? v5 output line (set, reset or toggle), and can also reset the ltc via the event output line eo. ltc service request the service request output sqtk of a local timer cell ltck is controlled as shown in figure 28-55 . when the ltck service request condition becomes active, the service request flag becomes always set. the service request output sqtk is only activated if it is enabled by the enable bit ltcctrk.ren. additional information about service request and interrupt handling is given on page 28-123 . figure 28-55 ltck service request generation mca05962 ren ltcctrk ltck ltck ltck srssn (read) srsrn (read) set sqtk srssn (write) srscn (write) set reset l tck service request b ecomes active n ote: s ervice request flags of ltc00 to ltc31 are located in srss2/srsc2 registers (n = 2 ). s ervice request flags of ltc32 to ltc62 are located in srss3/srsc3 registers (n = 3 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-79 v1.1, 2011-03 gpta ? v5, v1.0 28.3.3.4 local timer cell ltc63 the functionality of ltc63 is different to ltc00 to ltc62 and therefore described below. registers the following registers are assigned to local timer cell ltc63: ? ltcctr63 = local timer cell control register 63 (see page 28-204 ) ? ltcxr63 = local timer cell x register 63 (see page 28-206 ) ? srsc3 = service request state clear register 3 (see page 28-230 ) ? srss3 = service request state set register 3 (see page 28-231 ) features the gpta ? v5 local timer cell array has one special cell, ltc63, which provides the following special features: ? compare mode on greater equal compare of the last timer, 16-bit based with following actions: ? service request generation ? output signal transition generation (set, reset, toggle the output signal). ? bit reversal mode: ? timer can be selected to enable a special pwm mode, called pulse count modulation (pcm) ? compare value switching can be triggered by a hardware signal. this function can generate a service request. one shot mode makes it possible to stop the function after the first event. architecture ltc63 is locally equipped with a 16-bit com pare register, a 16-bit shadow register and a 16-bit greater comparator ( figure 28-56 ). the ltc63 has the following inputs: ? a local input data bus (yi) carrying the local timer value of the adjacent ltc with lower order number ? a ti input reporting the occurrence of a local timer value update of the adjacent ltc with lower order number ? a trigger/enable input ltckin for com pare value switching hooked to one of the following signals sources: ? external port lines ? gtc00 to gtc31 outputs ? clock bus signals ? pdl0 or pdl1 outputs ? internal gpta ? v5 kernel input signals intx (x = 0-3) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-80 v1.1, 2011-03 gpta ? v5, v1.0 the ltc63 provides the following output signals: ? one data output line (ltckout) that can be connected to: ? external port lines ? inputs of an msc module ? outputs and/or inputs of global timer cell inputs ? one service request line (sqt) triggered by a compare or copy event ? an eo output reporting the occurrence of a local event to the adjacent ltc with lower order number figure 28-56 architecture of local timer cell 63 compare the compare function is always enabled. as long as the 16-bit compare value ltcxr63.x is greater than the timer value pr ovided at yi, the comparator output signal is 1. the timer value at yi comes from the ltc62 either in original or in reversed order (bit0 <-> bit15, bit1 <-> bit14, etc.). the greater comparator output is connected directly to the output line ltc63out. the 16-bit compare value ltcxr63.x is never greater than the ltc timer value (ffff h ) coming from yi and which is used on ltc timer reset. without special measures, a duty cycle of 100% cannot be achieved. ther e is always one ltc timer clock missing. therefore, additional logic generates a permanent high signal whenever the 16-bit compare value ltcxr63.x is ffff h . mca05963 ltc63 control logic ltc63in x (16-bit compare) ltcxr63 ltc63ou t sqt63 from/to ltc62 eo ti yi > ltcxr63 mux bit reversal logic xs (16-bit shadow) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-81 v1.1, 2011-03 gpta ? v5, v1.0 when the comparator output si gnal changes from 1 to 0, ? the service request flag ltc63 is set, ? an interrupt request will be activated if enabled by bit field ltcctr63.ren, ? the event output line eo is set to high level for one f gpta clock cycle. as well as the16-bit compare register ltcxr63.x, the ltc63 also contains a 16-bit shadow register ltcxr63.xs. both 16-bit registers are combined in the 32-bit register ltcxr. on an ltc input signal selected via the ltc input multiplexer, the contents of the shadow register are copi ed to the compare register. standard pwm mode the ltc63 can be used for standard pwm duty cycle generation with enhanced update features. for this purpose, a pair of ltcs with lower index is configured as reset timer/period compare register. the user must set the period compare register to the desired period - 2 and ltc63 to the desir ed duty cycle. with ltcctr63.brm = 0 (bit reversal mode), timer bit reversal is disabled. ltc63 is used for standard pwm mode but with enhanced update features due to the ?greater? comparator. the compare register ltcxr63.x can be written on-the-fly. if the duty cycle is changed at an arbitrary time, the actual duty cycle for the current pe riod will reflect the old duty cycle, the new one, or a mixture of both. a duty cycle of 100% will be gen erated if the compare register is set to ffff h . pulse count modula tion mode (pcm) with a period of 1 00 clocks and a duty cycle of 64%, standard pwm will produce an output signal that is on for 64 clock cycl es and off for the remaining 36 clock cycles. in contrast, pulse count modulation will generate 64 on pulses and 36 off pulses distributed over the whole period as even ly as possible. pcm offers higher output frequency than standard pwm. this allows faster settling time e.g. when building a d/a converter in conjunction with an external low- pass filter. only for very short or very long duty cycles does the method sh ow no advantage or just little advantage compared to standard pwm. as with standard pwm, a pair of ltcs with lower index is configured as reset timer/period compare register and ltc63 is used as duty cycle compare register. but now, bit brm (bit reversal mode) in the ltcctr63 register is set to 1 which enables the timer bit reversal to activate pcm. the algorithm will also work if fewer than 16 timer bits are effectively used, even if the period is not a power of two. in any case, t he user must write the duty cycle in unsigned 16-bit fractional format to the compare register. figure 28-57 shows an pcm example for an effective period of 6 clocks. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-82 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-57 pulse count modulation example 1 table 28-5 shows the rounding behavior for a period of 100 clocks. the output is off for the remaining cycles of the period. the worst case error is approximately +2/-1 on pulses. a subtraction performed via software may be used to reduce the worst case error. if the duty cycle is changed at an arbitrary time, the actual duty cycle for the entire current period will reflect the old duty cycle, the new one, or a mixture of both. table 28-5 implicit pcm rounding desired duty cycle expected on pulses actual on pulses 0.000 = 0000 0 0 0.100 = 199a h 10 11 0.500 = 8000 h 50 50 0.800 = cccd h 80 82 0.900 = e666 h 90 90 0.999 = ffbe h 100 99 1.000 = ffff h 100 100 mct05964 0000 h 0000 h t imer value n ormal/ r eversed 0001 h 8000 h 0002 h 4000 h 0003 h c000 h 0004 h 2000 h ffff h ffff h d esired d uty cycle 0 .25 = 4000 h 0 .00 = 0000 h 0 .50 = 8000 h 0 .75 = c000 h 1 .00 = ffff h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-83 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-58 shows another pcm example that demonstrates the difference between a standard pwm signal and the derived pcm signal. during one pwm period (128 clock cycles), the standard pwm sign al is on for 8 clock cycles and off for the remaining 120 clock cycles (duty cycle of 6.25%). the pcm signal operates with a pcm duty cycle of 1/8 = 0.125 resulting in 8 on pulses of 1 clock cycle width within 1 pwm period. figure 28-58 pulse count modulation example 2 compare value switching in both pulse modulation modes, it is possible to change the duty cycle either by software or on an ltc input signal. ltc63 contains tw o registers, the compare register and a shadow register. for software access, the compare register ltcxr63.x (= 16-bit low part of ltcxr63) is written directly. for compare value switching triggered by hardware, the shadow register ltcxr63.xs (= 16-bit high part of ltcx r63) is pre-loaded with the desired dut y cycle. on an ltc input signal selected via the ltc input multiplexer, ? the shadow register content ltcxr63. xs is copied to the compare register ltcxr63.x, ? the ltc63 service request flag is set, ? an interrupt request will be activat ed if enabled by bit field ltcctr63.ren. the data input line ltc63in can operate in two modes (selected by bit ltcctr63.ilm): ? level sensitive mode or ? edge sensitive mode in edge sensitive mode, the active edges are selected by bits ltcctr63.fed and ltcctr63.red. in level sensitive mode, the data input line ltckin is sensitive on a high level. various clocking modes of the ltc63 copy function are possible, depending on the source selected for the input line by the input multiplexer (see table 28-6 ). pcm: 8 pulses with 1 clock cycle width pwm: 1 pulse with 8 clock cycle width 8 clock cycles mct0596 5 pwm period = 128 clock cycles s tandard p wm signal p cm signal 1 clock cycles www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-84 v1.1, 2011-03 gpta ? v5, v1.0 when bit ltcctr63.osm is set to 1, a self-disable is executed after each copy event (pwm is not affected). the current state of the ltc copy enable may be evaluated by reading the control register flag bit ltcctr63.cen. the output can be switched immediately to 0 or 1 in any pulse modulation mode by writing 0000 h or ffff h to the duty cycle comp are register ltcxr63.x. table 28-6 ltc63 data input line operation input source level sensitive input line edge sensitive input line external signal (port line) the external signal operates as gating signal for the cell. if the input is high the copy function of the ltc cell is performed with each rising edge of the gpta ? v5 module clock f gpta . the copy function of the ltc cell is performed on selected edge(s). internal clock bus line or pdl output or int input the copy function is performed with the internal clock or pdl/int signal. the copy function of the ltc cell is performed on selected edge(s). in case of full speed gpta ? v5 module clock selection, the level sensitive mode must be selected. the edge sensitive mode will not produce an event in this special case. gtc output the gtc output signal operates as gating signal for the cell. if the input is high the copy function of the ltc cell is performed with each rising edge of the gpta ? v5 module clock f gpta . the copy function of the ltc cell is performed on selected edge(s). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-85 v1.1, 2011-03 gpta ? v5, v1.0 ltc63 service request the service request sqt63 can be generated by one of the following events: ? comparator output changes from 1 to 0 (this makes sense mainly for standard pwm), ? copy event. bit combinations 01 b and 10 b of bit field ltcctr63.ren selects one of the two service request sources and enables it. output sqt63 becomes active in these two cases. with the other two bit combinations of bit field ltcctr63.ren (00 b , 11 b ), the sqt63 output will not be activated. the ltc63 service request flag srss3.ltc63 will be set on a service request independently of ltcctr63.ren. additional information on service request and interrupt handling is provided on page 28-123 . figure 28-59 ltc63 service request generation 28.3.3.5 coherent update this section describes the two different me chanism to update signal features (e.g. period, duty cycle) if using local timer cells. both mechanism grant a coherent update only if a single update within a group of local timer cells using a common local timer is performed within a timer period. so coherent update can only be granted if between coherent updating routine exit and coherent upda ting routine entry a time period of more then a period is maintained. if updating more frequently, software has to take care of coherency. global coherent update the first mechanism, the so called global coherent update, is very useful to update a number of local timer cells simultaneously. furthermore this is the only way to grant a coherent update of a local timer cell used as the period cell for a reseted timer. this global coherent update uses a common signal line (si/so) within a group of local timer cells (all local timer cells following an ltc configured as timer). a pair of local timer cells are configured so one cell being active on a high level of this si/so mca05966 ren ltcctr63 set ltc63 ltc63 reset ltc63 srss3 (read) srsr3 (read) set sqt6 3 srss3 (write) srsc3 (write) 2 0 0 c opy event occured c ompare event occured www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-86 v1.1, 2011-03 gpta ? v5, v1.0 (ltcctrk.soh = 1, ltcctrk.sol = 0) signal and the other cell being active on a low level of this si/so (ltcctrk.soh = 0, ltcctrk.sol = 1) signal. this pair of local timer cells are configured to generate both action request for a single output signal (e.g. pin). if the global si/so is in a low state, all local timer cells to be active on a high level of si/so can be configured (programmed with new values) without distortion of the output signal, because of being inactive. by setting the ltcctrk.cud bit within the local timer cell used as local timer, the si/so bit will be toggled at the start of the next timer period, so all pair of local timer cells simultaneously switch from active to passive (ltcctrk.soh = 0, ltcctrk.sol = 1) or passive to active state. now the local timer cells being inactive (ltcctrk.soh = 0, ltcctrk.sol = 1) may be configured (programmed) for the next update. no local timer cell may be configured (programmed) while respective timer bit ltcctrk.cud =1, else wise a coherent update is no longer granted. either the ltcctrk.cud has to be reset to 0 by software or a update of the local timer registers have to be delayed to the next start of the period (ltcctrk.cud is reset by hardware to 0). the following example shows a pwm using global coherent update. fully programmable pwm signal generation with 5 ltcs (global coherent update) as shown in figure 28-59 , a logical cell of five ltcs can be used to generate a pwm signal with a programmable duty cycle, per iod length, and fully global coherent update of the period and duty cycle. in this example, ltc00 up to ltc04 are used to generate a pwm signal at the output of ltc04. to reduc e complexity of this example, only a single duty cycle pair is described in the following text . more duty cycle cells may follow using the same reseted timer and pair of period cells. so if re quiring a second duty cycle ltc pair, the first pair would be located to lt c2 and ltc6, the next pair on ltc 3 and ltc7 and the period cells would be assigned to ltc1 and ltc4. ltc00 is configured in reset timer mode thus providing all subsequent cells with a time base. ltc00 is clocked by a clock signal at the ltc00in which has been selected by the ltc input multiplexer. ltc00 counts afte r reseted by ltc01 or ltc02 from ffff h , 0000 h , 0001 h ? ltcxr01.x or ltcxr01.x. th e period of the generated pwm is therefore ltcxr01.x +2 or ltcxr02.x + 2. ltc01 and ltc02 are configured in compare mo de. they are enabled if its si inputs are at low level and responsible for the ltc04out signal generation in phase 1. with the programmed values from table 28-7 , the ltc04out signal of phase 1 has a period of 1000 d (= 3e8 h ) clocks of the ltc00in clock si gnal and a duty cycle of 20% (= 200 d or c8 h ). ltc01 is configured in such a way (ltcctr01.ocm = 011 b ) that its output ltc01out is set to 1 whenever the ltc00 timer value ltcxr00.x is equal to the ltc01 compare value ltcxr01.x. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-87 v1.1, 2011-03 gpta ? v5, v1.0 ltc02 is configured in such a way (ltcctr02.ocm = 110 b ) that its output ltc02out is reset whenever the ltc00 timer value ltcxr00.x is equal to the ltc02 compare value ltcxr02.x or it copies the action from the previous ltc01. figure 28-60 pwm signal generation with ltcs (global coherent update) figure 28-61 internal signal states of th e pwm signal generation with 5 ltcs local timer cell ltc00 m1i m0i ti eo si m1o ti ei so yi yo local timer cell ltc01 m1i m0i ltc00in ti eo si m1o to ei so yi yo mca05967 ltc04ou t r eset t imer p eriod c ompare local timer cell ltc02 m1i m0i ti eo si m1o to ei so yi yo d uty cycle c ompare local timer cell ltc03 m1i m0i ti eo si m1o to ei so yi yo p eriod c ompare local timer cell ltc04 m1i m0i ti eo si m1o to ei so yi yo d uty cycle c ompare m0o m0o m0o m0o m0o mct0596 8 s o of ltc00 c ud flag d ata output line l tc04out ltc01 period threshold ltc00 timer value phase 1 phase 2 ltc03 period threshold ltc02 duty cycle threshold ltc04 duty cycle threshold tim e set by software ffffff h 0000c7 h 0003e7 h 0005dc h 0007d0 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-88 v1.1, 2011-03 gpta ? v5, v1.0 ltc03 and ltc04 are configured in compare mo de. they are enabled if its si inputs are at high level and are responsible for t he ltc04out signal generation in phase 2. with the programmed values from table 28-7 , the ltc04out signal of phase 2 has a period of 2000 d (= 7d0 h ) clocks of the ltc00in clock si gnal and a duty cycle of 75% (= 1500 d or 5dc h ). ltc00 to ltc04 for the pwm example mu st be configured as defined in table 28-7 . note: special care has to be taken not to reprogrammed the group of local timer cells (ltc) capcom register before the previous global or local coherent update has been completed (end of current local timer period). therefore maximum only one global coherent update within a timer period is possible! no local coherent updates may be activated while a global co herent update modifying the period has not been completed. note: if several sequential coherent updates within a group of local timer cells (ltc) is required, instead of using the global coherent update featur e, the local coherent update mechanism (double action principle) is preferable. mixing both principle, so updating the period using the cohere nt update and updating one or more duty cycle using local coherent update (double action principle) may result under specific condition in distorted signals ( new duty cycle, old period or old duty cycle and new period). therefore within a peri od either a global coherent update or multiple local coherent updates may be scheduled. note: to generate an output signal having 0% duty cycle (continuously low), the duty compare of the active cells must be set to ffff h . the timer sets the data output line by generating a respective signal on mo0 and mo1, but this signal is overruled by the dominating duty compare cell resetting the same data output line and therefore not passing t he mi0 and mi1 signal from the timer to the data output line. this result in a data output line remaining continuously low. note: to generate an output signal having 100% duty cycle (continuously high), the duty cycle threshold must be set above the perio d threshold value. therefore no reset event for the data line is generated and pe riodically the timer generates a set event. this result in a data output line remaining continuously high. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-89 v1.1, 2011-03 gpta ? v5, v1.0 table 28-7 programming values for pwm signal generation with 5 ltcs register value function ltc00 configuration setup gpta0_ltcxr00 0000 0000 h ltc00 data register value = 0 gpta0_ltcctr00 0001 0413 h mod = 11 b : reset timer mode selected osm = 0: ltc00 continuously enabled ilm =0, red=1, fed=0: input ltc00in operates in edge sensitive mode with rising edge; one clock bus signal is selected via the ltc input multiplexer slo = 0: state of select line output so is 0 cen = 0: enable ltc00 for local events ocm = 000 b : hold ltc00out state ltc01 configuration setup gpta0_ltcxr01 0000 03e7 h load compare value = 3e7 h = 999 d gpta0_ltcctr01 0001 5c11 h mod = 01 b : compare mode with ltc00 selected osm = 0: ltc01 continuously enabled soh = 0, sol = 1: compare enabled by low level at si byp = 0: local bypass in ltc01 is disabled gbyp = 1: global bypass in ltc01 is disabled eoa = 0: ltc02 enabled for local events ocm = 011 b : set ltc01out by a local event only oia = 1: output action defined by ocm must be performed immediately ltc02 configuration setup gpta0_ltcxr02 0000 00c7 h load compare value = c7 h = 199 d gpta0_ltcctr02 0001 3411 h mod = 01 b : compare mode with ltc00 selected osm = 0: ltc02 continuously enabled soh = 0, sol = 1: compare enabled by low level at si byp = 0: local bypass in ltc02 is disabled gbyp = 1: global bypass in ltc02 is disabled eoa = 0: ltc02 enabled for local events ocm = 110 b : reset ltc02out by a local event or copy the previous cell action oia = 0: no immediate output action required www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-90 v1.1, 2011-03 gpta ? v5, v1.0 ltc03 configuration setup gpta0_ltcxr03 0000 07cf h load compare value = 7cf h = 1999 d gpta0_ltcctr03 0001 7c21 h mod = 01 b : compare mode with ltc00 selected osm = 0: ltc03 continuously enabled soh = 1, sol = 0: compare enabled by high level at si byp = 0: local bypass in ltc03 is disabled gbyp = 1: global bypass in ltc03 is disabled eoa = 0: ltc03 enabled for local events ocm = 111 b : set ltc04out by a local event or copy the previous cell action oia = 1: output action defined by ocm must be performed immediately ltc04 configuration setup gpta0_ltcxr04 0000 05db h load compare value = 5db h = 1499 d gpta0_ltcctr04 0001 3421 h mod = 01 b : compare mode with ltc00 selected osm = 0: ltc04 continuously enabled soh = 1, sol = 0: compare enabled by high level at si byp = 0: local bypass in ltc04 is disabled gbyp = 1: global bypass in ltc04 is disabled eoa = 0: ltc04 enabled for local events ocm = 110 b : reset ltc04out by a local event or copy the previous cell action oia = 0: no immediate output action required table 28-7 programming values for pwm signal generation with 5 ltcs (cont?d) register value function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-91 v1.1, 2011-03 gpta ? v5, v1.0 local coherent update the second mechanism, the so called local coherent update or double action principle, is very useful to update single local timer cells without signal distortion (no other signal output beside the previously configured a nd the new configured). this coherent update may not be used for local timer cells generating toggle action requests (ltcctrk.ocm = ocm = x01 b ). the local coherent update is useful to configure (programme) several local timer cells within a group of local timer cells (all using the same local timer cell as time base) sequentially (not simultaneously), e.g. within different routines of the application software. the only restriction to grant non distorted output signals by hardware is to update (configure or programme) every single pair of local timer cells no often than once within a timer period (time measured from previous routine exit and current routine entry), else wi se software has to take care of coherency (non distorted signals). a pair of local ti mer cells are configured one cell being active (ltcctrk.soh = 1, ltcctrk.sol = 1) and the other being inactive (ltcctrk.soh = 0, ltcctrk.sol = 0, ltcctrk.cen = 0). this pair of local timer cells are configured to generate both action requests for a single output signal (e.g. pin). a local timer cell being inactive may be configured (programmed with a new value) without distortion of the output signal, because of being inactive. by activating the newly configured local timer cell (ltcctrk.soh = 1, ltcctrk.sol = 1, ltcctrk.osm = 0), now two local timer cells generate the same type of action request. the one being earlier within the period will now drive the output signal (either the newly configured or the previously conf igured one). now the local timer cell being active before configuration is coherently deactivated (ltcctrk.osm = 1) on its next action. so one period later this cell will be inactive (ltcctrk.cen = 0) and may be used for the next local coherent update. local and coherent update may be used simultaneously within a group of local timer cells. the following example shows a pwm using local coherent update. to reduce complexity of this example, only a single duty cycle pair is described in the following text . more duty cycle cells may follow using the same reseted timer and pair of period cells. so if re quiring a second duty cycle ltc pair, the first pair would remain on ltc2 and ltc3 and the next pair on ltc 4and ltc5 using ltc05 as output. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-92 v1.1, 2011-03 gpta ? v5, v1.0 programmable pwm signal generation with 4 ltcs (local coherent update) as shown in figure 28-62 , a logical cell of four ltcs can be used to generate a pwm signal with a programmable duty cycle and loca l coherent update of this duty cycle. in this example, ltc00 up to ltc03 are used to generate a pwm signal at the output of ltc03. figure 28-62 pwm signal generation with ltcs (local coherent update) ltc00 is configured in reset timer mode thus providing all subsequent cells with a time base. ltc00 is clocked by a clock signal at the ltc00in which has been selected by the ltc input multiplexer. ltc00 counts afte r reseted by ltc01 or ltc02 from ffff h , 0000 h , 0001 h ? ltcxr01.x or ltcxr01.x. th e period of the generated pwm is therefore ltcxr01.x +2 or ltcxr02.x + 2. ltc01 is configured in compare mode. it is always active and responsible for the ltc03out signal generation in phase 1. with the programmed value from table 28-8 , the ltc03out signal of phase 1 has a period of 1000 d (= 3e8 h ) clocks of the ltc00in clock signal and a duty cycle of 20% (= 200 d or c8 h ). ltc01 is configured in such a way (ltcctr01.ocm = 011 b ) that its output ltc01out is set to 1 whenever the ltc00 timer value ltcxr00.x is equal to the ltc01 compare value ltcxr01.x. ltc02 and ltc03 are configured in compare mode. they are responsible for the ltc03out signal generation in phase 2. with the programmed values from table 28-8 , the ltc03out signal of phase 2 has a duty cycle of 77% (= 770 d or 302 h ). local timer cell ltc00 m1i m0i ti eo si m1o ti ei so yi yo local timer cell ltc01 m1i m0i ltc00in ti eo si m1o to ei so yi yo mca05967_ii ltc03out reset timer period compare local timer cell ltc02 m1i m0i ti eo si m1o to ei so yi yo duty cycle compare local timer cell ltc03 m1i m0i ti eo si m1o to ei so yi yo duty cycle compare m0o m0o m0o m0o m3i m2i m3o m3i m2i m3o m3i m2i m3o m3i m2i m3o m2o m2o m2o m2o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-93 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-63 internal signal states of th e pwm signal generation with 4 ltcs ltc00 to ltc03 for the pwm example mu st be configured as defined in table 28-8 . note: special care has to be taken not to reprogram ltcxr02.x or ltcxr03.x before the previous local coherent update has been completed (ltcxr02.cen = 0 or ltcxr03.cen = 0). therefore maximu m one coherent update within a timer period is possible (measured from previous routine exit to current routine entry)! note: if simultaneous coherent updates of several local timer cells within a group of local timer cells (ltc) is required, inst ead of using the local coherent update (double action principle), the global coherent update mechanism must be used. note: if coherent updating the period of a timer in reset timer mode is required, the global coherent update mechanism must be used. note: global bypass may be used to route e.g. period action request (edge aligned pwm) around the pair of locally coherent updated local timer cells to following local timer cells. but special care has to be taken, because the timer bus is not routed over a ltc configured as timer. note: this scheme activates for one period two cells in parallel. therefore, if enabled, also two interrupts for this one signal are generated, one for the old (previous) edge, one for the new (updated) edge. mct05968_ii osm bit of ltc02 data output line ltc03out ltc01 period threshold ltc00 timer value ltc02 duty cycle threshold ltc03 duty cycle threshold time set by software ffffff h 0000c7 h 0003e7 h 000301 h cen bit of ltc02 reset by hardware (osm) cen bit of ltc03 set by software action request at ltct03out set 0 set 0 set 0 set 0 set 1 set 1 set 1 set 1 set 1 set 0 set 0 phase 2 phase 3 phase 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-94 v1.1, 2011-03 gpta ? v5, v1.0 note: to generate an output signal having 0% duty cycle (continuously low), the duty compare of the active cells must be set to ffff h . the timer sets the data output line by generating a respective signal on mo0 and mo1, but this signal is overruled by the dominating duty compare cell resetting the same data output line and therefore not passing t he mi0 and mi1 signal from the timer to the data output line. this result in a data output line remaining continuously low. note: to generate an output signal having 100% duty cycle (continuously high), the duty cycle threshold must be set above the perio d threshold value. therefore no reset event for the data line is generated and pe riodically the timer generates a set event. this result in a data output line remaining continuously high. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-95 v1.1, 2011-03 gpta ? v5, v1.0 table 28-8 programming values for pwm signal generation with 4 ltcs register value function ltc00 configuration setup gpta0_ltcxr00 0000 0000 h ltc00 data register value = 0 gpta0_ltcctr00 0000 0413 h mod = 11 b : reset timer mode selected osm = 0: ltc00 continuously enabled ilm =0, red=1, fed=0: input ltc00in operates in edge sensitive mode with rising edge; one clock bus signal is selected via the ltc input multiplexer slo = 0: state of select line output so is 0 cen = 0: enable ltc00 for local events ocm = 000 b : hold ltc00out state ltc01 configuration setup gpta0_ltcxr01 0000 03e7 h load compare value = 3e7 h = 999 d gpta0_ltcctr01 0000 5c11 h mod = 01 b : compare mode with ltc00 selected osm = 0: ltc01 continuously enabled soh = 1, sol = 1: enabled by both level at si byp = 0: bypass in ltc02 is disabled gbyp = 0: global bypass in ltc02 is disabled eoa = 0: ltc02 enabled for local events ocm = 011 b : set ltc01out by a local event only oia = 1: output action defined by ocm must be performed immediately www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-96 v1.1, 2011-03 gpta ? v5, v1.0 ltc02 configuration setup gpta0_ltcxr02 0000 00c7 h load compare value = c7 h = 199 d gpta0_ltcctr02 0000 3431 h mod = 01 b : compare mode with ltc00 selected osm = 0: ltc02 continuously enabled soh = 1, sol = 1: compare enabled by low and high level at si byp = 0: local bypass in ltc02 is disabled gbyp = 0: begin of global bypass in ltc02 eoa = 0: ltc02 enabled for local events ocm = 110 b : reset ltc02out by a local event or copy the previous cell action oia = 0: no immediate output action required ltc03 configuration setup gpta0_ltcxr03 0000 0301 h load compare value = 301 h = 769 d gpta0_ltcctr03 0001 3401 h mod = 01 b : compare mode with ltc00 selected osm = 0: ltc03 continuously enabled soh = 0, sol = 0: compare disabled by low and high level at si byp = 1: local bypass in ltc03 is disabled gbyp = 1: end of global bypass in ltc03 eoa = 0: ltc04 enabled for local events ocm = 110 b : reset ltc03out by a local event or copy the previous cell action oia = 0: no immediate output action required table 28-8 programming values for pwm signal generation with 4 ltcs (cont?d) register value function www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-97 v1.1, 2011-03 gpta ? v5, v1.0 the following code exemplifies the scheme to update the duty cycle of the pwm signal generation with 4 ltcs read ltcctr02 if ( ltcctr02.sol=1 and ltcctr02.soh=1 and ltcctr02.cen=1 and ltcctr02.osm=0) then write new_value into ltcxr03 of ltc03 set ltcctr03.osm=0 and ltcct r03.sol=ltcctr03.soh=1 for ltc03 (do not use load/modify/store, swap, or clear_bit assembler instructions) set ltcctr02.osm=1 of ltc02 (use load/modify/store, swap, or clear_bit asse mbler instructions) read ltcxr02 read ltcxr00 if ltcxr00>read_ltcxr02 then clear ltcctr02.sol=ltcctr02.soh=0 of ltc02 end if else write new_value into ltcxr02 of ltc02 set ltcctr02.osm=0 and ltcct r02.sol=ltcctr02.soh=1 for ltc02 (do not use load/modify/store, swap, or clear_bit assembler instructions) set ltcctr03.osm=1 of ltc03 (use load/modify/store, swap, or clear_bit asse mbler instructions) read ltcxr03 read ltcxr00 if ltcxr00>read_ltcxr03 then clear ltcctr03.sol=ltcctr03.soh=0 of ltc03 end if end if www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-98 v1.1, 2011-03 gpta ? v5, v1.0 28.3.4 input/output line sharing block (iols) the i/o line sharing block allows the 56 inputs and 112 outputs of the gpta ? v5 units to be routed with high flexibility between i/o lines, output lines, clock inputs, other on- chip peripherals and other gpta ? v5 cells. the gpta ? v5 module provides a total of 56 input lines and 112 output lines, assigned to seven i/o groups iog[6:0], two on-chip trigger and gating signal groups otg[1: 0], and seven output groups og[6:0]. figure 28-64 input/output line sharing block overview mca05969_mod int[3:0] output multiplexer out [55:00] gtc input multiplexer pdl[3:0] int[3:0] clk[7:0] ltc input multiplexer in [55:00] out [111:56] gpta module kernel og0 output groups og1 og2 og3 56 32 32 64 56 8 8 24 4 64 56 56 56 8 iog3 iog2 iog1 iog0 iog6 iog5 iog4 i/o groups ltcg3 ltcg2 ltcg1 ltcg0 ltc groups ltcg7 ltcg6 ltcg5 ltcg4 fpc[5:0] int[1:0] gtcg3 gtcg2 gtcg1 gtcg0 gtc groups otg1 otg0 trigger groups 16 og4 og5 og6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-99 v1.1, 2011-03 gpta ? v5, v1.0 the i/o line sharing block does the following selections: ? fpc input line selection ? gtc and ltc output multiplexer selection ? on-chip trigger and gating signal selection ? gtc input multiplexer selection ? ltc input multiplexer selection for choosing these selection, the input and output lines of the related cells are integrated into groups with eight parts each. sev en i/o groups, two on-chip and gating signal groups, seven output groups, four gtc groups , eight ltc groups, one clock group, one fpc/int group, and one pdl/int group are defined. figure 28-65 groups definitions for i/o line sharing block mca05970 ltc24in ltc25in ltc26in ltc27in ltc28in ltc29in ltc30in ltc31in example for an ltc group: ltcg3 ltc24 ltc25 ltc26 ltc27 ltc28 ltc29 ltc30 ltc31 ltc24out ltc25out ltc26out ltc27out ltc28out ltc29out ltc30out ltc31out gtc08in gtc09in gtc10in gtc11in gtc12in gtc13in gtc14in gtc15in gtc08 gtc09 gtc10 gtc11 gtc12 gtc13 gtc14 gtc15 gtc08out gtc09out gtc10out gtc11out gtc12out gtc13out gtc14out gtc15out pin io40 pin io41 pin io42 pin io43 pin io44 pin io45 pin io46 pin io47 out40 out41 out42 out43 out44 out45 out46 out47 in40 in41 in42 in43 in44 in45 in46 in47 pin o16 pin o17 pin o18 pin o19 pin o20 pin o21 pin o22 pin o23 out16 out17 out18 out19 out20 out21 out22 out23 clock bus of clock distribution logic clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 fpc0 fpc1 fpc2 fpc3 fpc4 fpc5 sol0 sol1 sol2 sol3 sol4 sol5 int0 int1 clock group fpc/int group pdl bus of pdl0/ pdl1 pdl 0 pdl 1 pdl 2 pdl 3 int 0 int 1 int 2 int 3 pdl/int group example for an gtc group: gtcg1 example for an i/o group: iog5 example for an output group: og2 int0 int1 int2 int3 int0 int1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-100 v1.1, 2011-03 gpta ? v5, v1.0 an ltc group combines eight ltc cells with its input and output lines. this results in eight ltc groups, ltcg0 to ltcg7. a gtc group combines eight gtc cells with its input and output lines. this results in four gtc groups, gtcg0 to gtcg3. an i/o group combines eight gpta ? v5 i/o lines connected to bi-directional device pins with its input and output lines. this results in seven i/o groups, iog0 to iog6, supporting 56 i/o lines. an output group combines eight gpta ? v5 output lines connected to device pins as an output. this results in seven output groups, og0 to og6, supporting 56 output lines. the clock group is a group that combines the eight clock bus output signals clk[7:0] generated by the clock distribution cells. the fpc/int group is a group that combines the six level output signals sol[5:0] of the fpcs with two external input lines int[1:0] of the gpta ? v5 unit. the pdl/int group is a group that combines the four pdl output lines of the pdl bus with four external input lines int[3:0] of the gpta ? v5 unit. an on-chip trigger and gating signal group combines eight gpta ? v5 output lines connected to on-chip peripherals. this results in two on-chip trigger and gating signal groups, otg0 to og1, supporting 16 on-chip trigger and gating lines. table 28-9 group to i/o line/cell assignment group/unit cell/line input output ltc groups ltcg0 ltc[07:00] ltc[07:00]in ltc[07:00]out ltcg1 ltc[15:08] ltc[15:08]in ltc[15:08]out ltcg2 ltc[23:16] ltc[23:16]in ltc[23:16]out ltcg3 ltc[31:24] ltc[31:24]in ltc[31:24]out ltcg4 ltc[39:32] ltc[39:32]in ltc[39:32]out ltcg5 ltc[47:40] ltc[47:40]in ltc[47:40]out ltcg6 ltc[55:48] ltc[55:48]in ltc[55:48]out ltcg7 ltc[63:56] ltc[63:56]in ltc[63:56]out gtc groups gtcg0 gtc[07:00] gtc[07:00]in gtc[07:00]out gtcg1 gtc[15:08] gtc[15:08]in gtc[15:08]out gtcg2 gtc[23:16] gtc[23:16]in gtc[23:16]out gtcg3 gtc[31:24] gtc[31:24]in gtc[31:24]out www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-101 v1.1, 2011-03 gpta ? v5, v1.0 i/o groups iog0 ? in[07:00] out[07:00] iog1 ? in[15:08] out[15:08] iog2 ? in[23:16] out[23:16] iog3 ? in[31:24] out[31:24] iog4 ? in[39:32] out[39:32] iog5 ? in[47:40] out[47:40] iog6 ? in[55:48] out[55:48] output groups og0 ? ? out[63:56] og1 ? ? out[71:64] og2 ? ? out[79:72] og3 ? ? out[87:80] og4 ? ? out[95:88] og5 ? ? out[103:96] og6 ? ? out[111:104] on-chip trigger and gating signals groups otg0 ? ? otgs[07:00] otg1 ? ? otgs[15:08] clock group ? ? ? clk[7:0] fpc/int groups fpc[5:0] ? ? sol[5:0] external input [1:0] ? ? int[1:0] pdl/int groups pdl[1:0] pdl bus ? ? pdl[3:0] external input [3:0] ? ? int[3:0] table 28-9 group to i/o line/cell assignment (cont?d) group/unit cell/line input output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-102 v1.1, 2011-03 gpta ? v5, v1.0 28.3.4.1 fpc input line selection as shown on page 28-12 , each fpc cell can be connected to one out of four input lines sink[3:0], to the gpta ? v5 module clock f gpta , or to the output of the preceding fpc. in total, 24 input lines out of the 56 input line s in[55:00] from the i/ o groups are connected (not programmable) with the fpck inputs. th e fpck input line selection is controlled by the fpcctrk.ips bit fields. table 28-10 shows the fpc input line connections. table 28-10 fpc input line assignments fpc control register bit field ips selected input signal fpcctr0 000 b in0 001 b in12 010 b in24 011 b in36 fpcctr1 000 b in2 001 b in14 010 b in26 011 b in38 fpcctr2 000 b in4 001 b in16 010 b in28 011 b in40 fpcctr3 000 b in6 001 b in18 010 b in30 011 b in42 fpcctr4 000 b in8 001 b in20 010 b in32 011 b in44 fpcctr5 000 b in10 001 b in22 010 b in34 011 b in46 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-103 v1.1, 2011-03 gpta ? v5, v1.0 28.3.4.2 gtc and ltc output multiplexer selection the output multiplexer shown in figure 28-64 and figure 28-66 below connects the 32 gtc output lines and the 64 ltc output lines with the i/o groups (7 8 = 56 output lines) and the output groups (7 8 = 56 output lines). in case of low pin count packages, not all i/o groups may be routed to a pin. figure 28-66 output multiplexer the output multiplexer contains output multiplexer groups (omgs) that connect the global timer cells or local timer cells with the input lines of the i/o groups and output groups. gtcs and ltcs are grouped into f our gtc groups (gtcg[3:0]) and eight ltc groups (ltcg[7:0]) with 8 cells each. in the same way, i/o groups and output groups are grouped into 14 groups (seven i/o gr oups and seven output groups) with 8 lines each. ltc groups gtc groups i/o groups output groups mca05971 iog0 iog1 iog2 iog3 iog4 iog5 iog6 8 gtcg0 gtc[07:00] gtcg1 gtc[15:08] gtcg2 gtc[23:16] gtcg3 gtc[31:24] ltcg0 ltc[07:00] ltcg1 ltc[15:08] ltcg2 ltc[23:16] ltcg3 ltc[31:24] ltcg5 ltc[47:40] ltcg6 ltc[55:48] ltcg7 ltc[63:56] omg 00 omg 02 omg 03 omg 04 omg 05 omg 06 omg 10 omg 11 omg 12 omg 13 omg 14 omg 15 omg 16 omg 24 omg 25 omg 26 omg 20 omg 21 omg 22 omg 23 ltcg4 ltc[39:32] omg 01 og0 og1 og2 og3 og4 og5 og6 omg 08 omg 0c omg 18 omg 28 omg 07 omg 17 omg 19 omg 29 omg 09 omg 0a omg 1a omg 2a omg 0b omg 1b omg 2b omg 1c omg 2c omg 0d omg 1d omg 2d output multiplexer 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 omg 27 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-104 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-67 shows the logical structure of an omg. figure 28-67 output multiplexer group (omg) structure rules for connections to output multiplexer group omg: ? within a gtc or ltc group, the output of the cell with the lowest index number is connected to omg input line in0. the remaining cells of a cell group are connected to omg input lines in1 to in7 with ascending cell index numbers. example: for omg13 (see figure 28-66 ), the cells ltc24 up to ltc31 are wired to the omg13 input lines in0 to line in7. ? omg output line out0 is always connected to the input of an i/o or output group with the lowest index. the remaining output lines out1 to out7 are connected to the i/o or output lines with ascending index. example: for omg13 (see figure 28-66 ), the outputs out0 to out7 are wired (via omg03) to input lines 0 to 7 of i/o group 3 (iog3). ? one input of an i/o or output group can be connected to the output of only one timer cell. this is guaranteed by the omg control register layout. otherwise, short circuits and unpredictable behavior would occur. on the other hand, it is permissible for the output of a gtc or ltc to be connected to more than one input of an i/o or output group. the output multiplexer group configuration is based on the following principles: ? each omg is referenced with two index variables: n and g (omgng) ? index n is a group number. global ti mer cell groups gtcg[3:0] have the group number 0, local timer cell groups ltcg[3:0] have the group number 1, and local timer cell groups ltcg[7:4] have the group number 2. mca05972 from other omgs in0 in1 in2 in3 in4 in5 in6 in7 o utputs of a l tc group or g tc group to other omgs out0 out1 out2 out3 out4 out5 out6 out7 to i/o or output groups more than one switch might be closed per ro w, only one switch can be closed per column www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-105 v1.1, 2011-03 gpta ? v5, v1.0 ? index g indicates the number of an i/o or output group g (g = 0-13 d ) to which the outputs of the output multiplexer group omgng are connected. i/o groups iog0 to iog6 are assigned to index variable g = 0 to 6 and output groups og0 to og6 are assigned to index variable g = 7 to 13. the output multiplexer logic as seen for programming is shown in figure 28-68 . with this logic, always three gtc or ltc group signals are combined to one output line that leads to the input of an i/o or output group. for example, when looking at figure 28-66 , each of the eight output multiplexer output lines to i/o group iog5 is connected via three omgn5 (n = 0, 1, 2) with the eight outputs of one gtc group (gtcg1) and two ltc groups (ltcg1 and ltcg5). figure 28-68 output multiplexe r group (programmer?s view) the 1. level multiplexer is built up by three 8:1 multiplexers that are controlled in parallel by bit field omln. bit field omgn controls the 2. level multiplexer and connects one of the 1. level multiplexer outputs to output n. the output of the 2. level multiplexer is connected only to the input of an i/o group or output group if bit mractl.maen is set (multiplexer array enabled) and no reserved bit combination of omgn is selected. if one of these conditions is not true, the corresponding omg output will be held at a low level. two output gpta ? v5, omcrl and omcrh (see also page 28-121 ), are assigned to each of the i/o or output groups. therefore, a total of 28 registers control the connections within the output multiplexer of the gpta ? v5 module. the omcrl registers control the omg output lines 0 to 3. the omcrh registers control the omg output lines 4 to 7. table 28-11 lists all output multiplexer control registers with its control functions. please note that the output multiplexer control registers are mca05973 mux 8 gtc group (omg0g) mux mux ltc group (omg1g) ltc group (omg2g) mux 010 001 000 2. level mux omln omgn 1. level mux omcrlg omcrhg (g = 0-13) to input of i/o group g or output group (g- 7) mux 0 1 maen mractl & not a reserved omgn bit combination 0 8 8 3 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-106 v1.1, 2011-03 gpta ? v5, v1.0 not directly accessible but must be written or read using a fifo array structure as described on page 28-121 . table 28-11 output multiplexer control register assignments i/o group or output group controlled by multiplexer control register selectable groups via omgng iog0 in[03:00]/out[03:00] om crl0 gtcg0, ltcg0, ltcg4 in[07:04]/out[07:04] omcrh0 iog1 in[11:08]/out[11:08] om crl1 gtcg1, ltcg1, ltcg5 in[15:12]/out[15:12] omcrh1 iog2 in[19:16]/out[19:16] om crl2 gtcg2, ltcg2, ltcg6 in[23:20]/out[23:20] omcrh2 iog3 in[27:24]/out[27:24] om crl3 gtcg3, ltcg3, ltcg7 in[31:28]/out[31:28] omcrh3 iog4 in[35:32]/out[35:32] om crl4 gtcg0, ltcg0, ltcg4 in[39:36]/out[39:36] omcrh4 iog5 in[43:40]/out[43:40] om crl5 gtcg1, ltcg1, ltcg5 in[47:44]/out[47:44] omcrh5 iog6 in[51:48]/out[51:48] om crl6 gtcg2, ltcg2, ltcg6 in[55:52]/out[55:52] omcrh6 og0 out[59:56] omcrl7 gtcg3, ltcg3, ltcg7 out[63:60] omcrh7 og1 out[67:64] omcrl8 gtcg0, ltcg0, ltcg4 out[71:68] omcrh8 og2 out[75:72] omcrl9 gtcg1, ltcg1, ltcg5 out[79:76] omcrh9 og3 out[83:80] omcrl10 gtcg2, ltcg2, ltcg6 out[87:84] omcrh10 og4 out[91:88] omcrl11 gtcg3, ltcg3, ltcg7 out[95:92] omcrh11 og5 out[99:96] omcrl12 gtcg0, ltcg0, ltcg4 out[103:100] omcrh12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-107 v1.1, 2011-03 gpta ? v5, v1.0 og6 out[107:104] omcrl13 gt cg1, ltcg1, ltcg5 out[111:108] omcrh13 table 28-11 output multiplexer control register assignments (cont?d) i/o group or output group controlled by multiplexer control register selectable groups via omgng www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-108 v1.1, 2011-03 gpta ? v5, v1.0 28.3.4.3 on-chip trigger and gati ng output multiplexer selection the on-chip trigger and gating signal (otgs) multiplexer shown in figure 28-64 and figure 28-69 below connects the 32 gtc output lines and the 64 ltc output lines with the on-chip trigger and gating signal groups (2 8 = 16 output lines). in case of low pin count packages, not all i/o groups may be routed to a pin. figure 28-69 on-chip trigger and gating signal multiplexer ltc groups gtc groups i/o groups otmg3 iog0 iog1 iog2 iog3 8 gtcg0 gtc[07:00] gtcg1 gtc[15:08] gtcg2 gtc[23:16] gtcg3 gtc[31:24] ltcg0 ltc[07:00] ltcg1 ltc[15:08] ltcg2 ltc[23:16] ltcg3 ltc[31:24] ltcg5 ltc[47:40] ltcg6 ltc[55:48] ltcg7 ltc[63:56] omg 00 omg 02 omg 03 omg 10 omg 11 omg 12 omg 20 omg 22 ltcg4 ltc[39:32] omg 01 output multiplexer 8 8 8 8 8 8 8 8 8 8 8 omg 13 omg 21 omg 23 8 8 8 8 2 1 3 2 2 2 2 8 8 8 8 on-chip trigger and gating multiplexer trig0g trig1g otmg0 otmg1 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-109 v1.1, 2011-03 gpta ? v5, v1.0 the on-chip trigger and gating signal multiplexer contains output multiplexer groups (omgs) that connect the outputs of the i/o groups with the on-chip trigger signals. these on-chip trigger signals are gr ouped into two on-chip trigger groups (otmg[1:0]) with 8 cells each. figure 28-67 shows the logical structure of an otmg. figure 28-70 on-chip trigger and gating multiplexer group (otmg) structure rules for connections to output multiplexer group otmg: ? only one input of an on-chip trigger and gating signal group can be connected to a on-chip trigger and gating signal (trig). this is guaranteed by the otmg control register layout. otherwise, short circuits and unpredictable behavior would occur. on the other hand, it is permissible for the output of a i/o group to be connected to more than one on-chip trigger and gating signal (trig). the on-chip trigger and gating multiplexer group configuration is based on the following principles: ? each otmg is referenced with a single index variables: g (otmgg) ? index g indicates the number of an on-chip trigger and gating signal multiplexer group g (g = 0-1 d ) to which the outputs of the on-chip trigger and gating signal multiplexer group otmgg are connected. trig00 to trig07 are assigned to otmg0 and trig10 to trig17 are assigned to otmg1. the on-chip trigger and gating signal multiplexer logic as seen for programming is shown in figure 28-71 . otmg from other otmgs in0 in1 in2 in3 in4 in5 in6 in7 outputs of i/o groups to other otmgs trig0 trig1 trig2 trig3 trig4 trig5 trig6 trig7 to on-chip trigger groups more than one switch might be closed per row only one switch can be closed per column www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-110 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-71 on-chip trigger and gating multiplexer group (programmer?s view) the multiplexer is built up by three 8:1 multiplexer that is controlled by bit field otmn. bit field the output of the multiplexer is connected only to the on-chip trigger and gating signal trign if bit mractl.maen is set (multiplexer array enabled). if this condition is not true, the corresponding otmg output will be held at a low level. sixteen on-chip trigger and gating signals are assigned to the gpta0. therefore, a total of 2 registers control the connections within the on-chip gating and trigger signal multiplexer of the gpta0 unit. further sixteen on-chip trigger and gating si gnals are assigned to the gpta1. therefore, a total of 2 registers control the connections within the on-chip gating and trigger signal multiplexer of the gpta1 unit. the otmcr0 register control the otmg output lines trig00 to trig07. the otmcr1 register control the otmg output lines trig10 to trig17. table 28-12 lists all on-chip trigger and gating signal multiplexer control registers with its control functions. please note that the on-chip trigger and gating signal multiplexer control registers are not directly accessible but must be written or read using a fifo array structure as described on page 28-121 . otmg1 mux 8 io groups (omg0g, g = [3:0]) otmn otmcrg (g = 0-1) trigg[7:0] (g = 0-1) mux 0 1 maen mractl 0 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-111 v1.1, 2011-03 gpta ? v5, v1.0 28.3.4.4 gtc input multiplexer selection the gtc input multiplexer as shown in figure 28-64 and figure 28-72 connects the 56 (= 7 8) input lines of the i/o groups, the 64 ltc output lines of the eight ltc groups, the six fpc output lines, and two internal input lines int[1:0] with the 32 (= 4 8) ltc input lines, organized into eight ltc groups. table 28-12 on-chip trigger/gating multiplexer control register assignments i/o group signal otmg input signal controlled by multiplexer control register trigger/gating signal (x=0-7) selectable groups via omgng iog0 out00 in00 otmcr0 trig0x gtcg0, ltcg0, ltcg4 iog0 out02 in01 otmcr0 trig0x gtcg0, ltcg0, ltcg4 iog1 out08 in02 otmcr0 trig0x gtcg1, ltcg1, ltcg5 iog1 out10 in03 otmcr0 trig0x gtcg1, ltcg1, ltcg5 iog2 out16 in04 otmcr0 trig0x gtcg2, ltcg2, ltcg6 iog2 out19 in05 otmcr0 trig0x gtcg2, ltcg2, ltcg6 iog3 out24 in06 otmcr0 trig0x gtcg3, ltcg3, ltcg7 iog3 out27 in07 otmcr0 trig0x gtcg3, ltcg3, ltcg7 iog0 out01 in10 otmcr1 trig1x gtcg0, ltcg0, ltcg4 iog0 out03 in11 otmcr1 trig1x gtcg0, ltcg0, ltcg4 iog1 out09 in12 otmcr1 trig1x gtcg1, ltcg1, ltcg5 iog1 out11 in13 otmcr1 trig1x gtcg1, ltcg1, ltcg5 iog2 out18 in14 otmcr1 trig1x gtcg2, ltcg2, ltcg6 iog3 out25 in15 otmcr1 trig1x gtcg3, ltcg3, ltcg7 iog3 out26 in16 otmcr1 trig1x gtcg3, ltcg3, ltcg7 iog3 out28 in17 otmcr1 trig1x gtcg3, ltcg3, ltcg7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-112 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-72 gtc input multiplexer the gtc input multiplexer contains gtc input multiplexer groups (gimgs) that connect the i/o groups or local timer cells with the input lines of the gtc input lines, organized into four gtc groups with 8 cells each. gtc input multiplexer group are grouped into seven iogs (iog[6:0]) with eight lines each and eight ltc groups (ltcg[7:0]) with 8 cells each. one special fpc/int group with eight outputs is established that combines the six fpc outputs and two internal input lines int[1:0] as a group of gimgs inputs. ltc input multiplexer ltc groups i/o groups mca05974 gtc groups 8 iog0 iog1 iog2 iog3 ltcg0 ltc[07:00] ltcg1 ltc[15:08] ltcg2 ltc[23:16] ltcg3 ltc[31:24] ltcg5 ltc[47:40] ltcg6 ltc[55:48] ltcg7 ltc[63:56] gimg 00 gimg 02 gimg 03 gimg 10 gimg 11 gimg 12 gimg 20 gimg 21 gimg 22 gimg 23 ltcg4 ltc[39:32] gimg 01 gtcg0 gtc[07:00] gtcg1 gtc[15:08] gtcg2 gtc[23:16] gtcg3 gtc[31:24] 8 iog4 fpc[5:0] int[1:0] gimg 30 gimg 31 gimg 32 gimg 40 gimg 41 gimg 42 gimg 43 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 iog5 iog6 gimg 33 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-113 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-73 shows the logical structure of a gimg. figure 28-73 gtc input multiplexer group (gimg) structure rules for connections to gtc input multiplexer group gimg: ? within a i/o group or ltc group, the line or the output of the cell with the lowest index number is connected to gimg input line in0. the remaining lines, cells or lines of a group are connected to gimg input lines in1 to in7 with ascending index numbers. at the fpc/int group, fpc[5:0] is connected to in[5:0] and int[1:0] is connected to in[7:6]. example: for gimg23 (see figure 28-72 ), the cells ltc24 up to ltc31 are wired to the gimg23 input lines in0 to line in7. ? multiplexer output out0 is always connected to the input of a gtc group with the lowest index. the remaining output lines out1 to out7 are connected to the gtc inputs with ascending index. example: for gimg23 (see figure 28-72 ), the outputs out0 to out7 are wired to the inputs of gtc16 to gtc23. ? a gtc input can be connected either to an i/o group output, or to an ltc output, or to an fpc/int output. this is guaranteed by the gimg control register layout. otherwise, short circuits and unpredictable behavior would occur. in contrast, it is permissible for an i/o group output, or an ltc output, or an fpc/int output to be connected to more than one gtc input. the gtc input multiplexer group configuratio n is based on the following principles: ? each gimg is referenced with two index variables: n and g (gimgng) ? index n is a group number. i/o groups iog[3:0] have group number 0, i/o groups iog[6:4] have group number 1, local time r cell groups ltcg[3:0] have group mca05975 from other gimgs in0 in1 in2 in3 in4 in5 in6 in7 o utputs of an i /o group or l tc group or f pc/int group to other gimgs out0 out1 out2 out3 out4 out5 out6 out7 to gtc groups more than one switch might be closed per ro w, only one switch can be closed per column www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-114 v1.1, 2011-03 gpta ? v5, v1.0 number 2, local timer cell groups ltcg[7:4] have group number 3, and the fpc/int group has group number 4. ? index g indicates the number of the gtc group g (g = 0-3) to which the outputs of the input multiplexer group gimgng are connected. the gtc input multiplexer logic as seen for programming is shown in figure 28-74 . with this logic, five group signals (from an i/ o group, ltc group, or fpc/int group) are always combined to one output line that leads to the input of a gtc of gtc group g. for example, when looking at figure 28-73 , each of the eight gtc input multiplexer output lines to gtc group gtcg2 is connected via five omgn2 (n = 0-4) with the eight outputs of two i/o group (iog2 and iog6), two ltc groups (ltcg2 and ltcg6), and the fpc/int group. figure 28-74 gtc input multiplexer group (programmer?s view) the 1. level multiplexer is built up by five 8:1 multiplexers that are controlled in parallel by bit field gimln. bit field gimgn controls the 2. level multiplexer and connects one of the 1. level multiplexer outputs to one of the gimgng outputs. the output of the 2. level multiplexer is only connected to the input of an gtc if bit gimenn (enable multiplexer connection) is set, and bit mractl.aen is set (multiplexer array enabled), and no registers mca05976 mux 8 mux mux 010 001 000 2. level mux gimln gimgn 1. level mux gimcrlg gimcrhg (g = 0-4) mux mux mux 011 100 to input n of gtc group g & gimenn 0 mux 0 1 maenn mractl not a reserved gimgn bit combination 8 8 8 8 3 3 i/o group (gimg0g) i/o group (gimg1g) ltc group (gimg2g) ltc group (gimg3g) fpc/int group (gimg4g) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-115 v1.1, 2011-03 gpta ? v5, v1.0 reserved bit combination of gimgn is selected. if one of these conditions is not true, the corresponding gimg output will be held at a low level. if one of these bit is not set, the corresponding gtc input will be held at a low level. two gtc input multiplexer control registers, gimcrl and gimcrh (see also page 28-215 ), are assigned to each of the gtc groups. therefore, a total of eight registers control the connections within the gtc input multiplexer of the gpta ? v5 module. the gimcrl registers control the gimg output lines 0 to 3 and the gimcrh registers control the gimg output lines 4 to 7. table 28-13 lists all of the gtc input multiplexer control registers with its control functions. please note that all gtc input multiplexer control registers are not directly accessible but must be written or read using a fifo array structure as described on page 28-121 . table 28-13 gtc input multiplexer control register assignments gtc group and gtcs controlled by multiplexer control register selectable groups via gimgng gtcg0 gtc[03:00] gimcrl0 iog0, io g4, ltcg0, ltcg4, fpc/int gtc[07:04] gimcrh0 gtcg1 gtc[11:08] gimcrl1 iog1, io g5, ltcg1, ltcg5, fpc/int gtc[15:12] gimcrh1 gtcg2 gtc[19:16] gimcrl2 iog2, io g6, ltcg2, ltcg6, fpc/int gtc[23:20] gimcrh2 gtcg3 gtc[27:24] gimcrl3 iog3, ltcg3, ltcg7, fpc/int gtc[31:28] gimcrh3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-116 v1.1, 2011-03 gpta ? v5, v1.0 28.3.4.5 ltc input multiplexer selection the ltc input multiplexer as shown in figure 28-64 and figure 28-75 connects the 56 (= 7 8) input lines of the i/o groups, the 32 (= 4 8) gtc output lines of the gtc groups, the eight clock bus lines, or the four pd l output lines with four internal input lines int[3:0] with the 64 (= 8 8) ltc input lines, organized into eight ltc groups. figure 28-75 ltc input multiplexer i/o groups gtc groups mca05977 ltc groups 8 iog0 iog1 iog2 iog3 limg 00 limg 02 limg 03 limg 10 limg 11 limg 12 limg 20 limg 21 limg 22 limg 01 8 iog6 iog5 iog4 pdl[3:0] int[3:0] ltcg0 ltc[07:00] ltcg1 ltc[15:08] ltcg2 ltc[23:16] ltcg3 ltc[31:24] ltcg5 ltc[47:40] ltcg6 ltc[55:48] ltcg7 ltc[63:56] ltcg4 ltc[39:32] limg 04 limg 06 limg 07 limg 05 limg 14 limg 15 limg 16 gtcg0 gtc[07:00] gtcg1 gtc[15:08] gtcg2 gtc[23:16] gtcg3 gtc[31:24] clk[7:0] limg 40 limg 41 limg 42 limg 43 limg 30 limg 31 limg 32 limg 33 limg 44 limg 45 limg 46 limg 47 ltc input multiplexer 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 limg 23 limg 34 limg 35 limg 36 limg 37 limg 24 limg 25 limg 26 limg 27 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-117 v1.1, 2011-03 gpta ? v5, v1.0 the ltc input multiplexer contains ltc input multiplexer groups (limgs) that connect the i/o groups or global timer cells with t he input lines of the ltcs, organized into eight ltc groups with 8 cells each. iogs and gtcs are grouped into seven iogs (iog[6:0]) with eight lines each and four gtc groups (gtcg[3:0]) with 8 cells each. two special groups are available: a clock group with eight lines representing the clock bus lines clk[7:0] of the clock distribution cells and a pdl/int group with eight outputs that combines the four pdl outputs and four internal input lines int[3:0] as a group of limgs inputs. note: gpta0 generates the clock bus lines clk[7:0] and the four pdl outputs. figure 28-76 shows the logical structure of a limg. figure 28-76 ltc input multiplexer group (limg) structure rules for connections to ltc input multiplexer group limg: ? within a i/o group or gtc group, the line or the output of the cell with the lowest index number is connected to limg input line in0. the remaining lines, cells or lines of a group are connected to limg input lines in1 to in7 with ascending index numbers. at the clock group, clk0 is connected to in0 and the remaining clock lines are connected to limg input lines in1 to in7 with ascending index numbers. at the pdl/int group, pdl[3:0] (see page 28-22 ) is connected to in[3:0] and int[3:0] is connected to in[7:4]. example: for limg23 (see figure 28-75 ), the cells gtc24 up to gtc31 are wired to the limg23 input lines in0 to line in7. ? multiplexer output out0 is always connec ted to the input of an ltc group with the lowest index. the remaining output lines out1 to out7 are connected to the ltc inputs with ascending index. mca05978 from other limgs in0 in1 in2 in3 in4 in5 in6 in7 o utputs of an i /o group or g tc group or c lk group p dl/int group to other limgs out0 out1 out2 out3 out4 out5 out6 out7 to ltc groups more than one switch might be closed per ro w, only one switch can be closed per column www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-118 v1.1, 2011-03 gpta ? v5, v1.0 example: for limg23 (see figure 28-75 ), the outputs out0 to out7 are wired to the inputs of ltc24 to gtc31. ? an ltc input can be connected either to an i/o group output, or to an gtc output, or to a clock bus output, or to an pdl/int output. this is guaranteed by the limg control register layout. otherwise, short circuits and unpredictable behavior would occur. in contrast, it is permitted that an i/o group output, or an gtc output, or an pdl/int output is connected to more than one ltc input. the ltc input multiplexer group configuration is based on the following principles: ? each limg is referenced with two index variables: n and g (limgng) ? index n is a group number. i/o groups iog[3:0] have group number 0, i/o groups iog[6:4] have group number 1, global ti mer cell groups gtcg[3:0] have group number 2, clock bus lines clk[7:0] have group number 3, and the pdl/int group has group number 4. ? index g indicates the number of the ltc group g (g = 0-7) to which the outputs of the input multiplexer group limgng are connected. the ltc input multiplexer logic as seen for programming is shown in figure 28-77 . with this logic, five group signals (from an i/o group, gtc group, clock group, or pdl/int group) are always combined to one output line that leads to the input of an ltc of ltc group g. for example, when looking at figure 28-75 , each of the eight ltc input multiplexer output lines to ltc group ltcg2 is connected via five limgn2 (n = 0-4) with the eight outputs of two i/o group (iog2 and iog6), one gtc group (gtcg2), the clock group, and the pdl/int group. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-119 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-77 ltc input multiple xer group (programmer?s view) the 1. level multiplexer is built up by five 8:1 multiplexers that are controlled in parallel by bit field limln. bit field limgn controls the 2. level multiplexer and connects one of the 1. level multiplexer outputs to one of the limgng outputs. the output of the 2. level multiplexer is connected only to the input of an ltc if bit limenn is set (enable multiplexer connection), and bit mractl.aen is set (multiplexer array enabled), and no reserved bit combination of limgn is selected. if one of these conditions is not true, the corresponding ltc input will be held at a low level. two ltc input multiplexer control registers, limcrl and limcrh (see also page 28-219 ), are assigned to each of the ltc groups. therefore, in total sixteen registers control the connections within the ltc input multiplexer of the gpta ? v5 module. the limcrl registers control the limg out put lines 0 to 3 and the gimcrh registers control the limg output lines 4 to 7. table 28-14 lists all ltc input multiplexer control registers with its control functions. please note that all ltc input multiplexer control registers are not directly accessible but must be written or read using a fifo array structure as described on page 28-121 . mca05979 mux 8 i/o group (limg0g) mux mux i/o group (limg1g) gtc group (limg2g) 2. level mux 1. level mux 3 mux clock group (limg3g) mux pdl/int group (limg4g) mux limcrlg limcrhg (g = 0-7) to input n of ltc group g limenn 0 mux 0 1 maen mractl registers limgn limln & not a reserved limgn bit combination 3 8 8 8 8 010 001 000 011 100 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-120 v1.1, 2011-03 gpta ? v5, v1.0 table 28-14 ltc input multiplexer control register assignments ltc group and ltcs controlled by register selectable groups via limgng ltcg0 ltc[03:00] limcrl0 iog0, iog4, gtcg0, clock, pdl/int ltc[07:04] limcrh0 ltcg1 ltc[11:08] limcrl1 iog1, iog5, gtcg1, clock, pdl/int ltc[15:12] limcrh1 ltcg2 ltc[19:16] limcrl2 iog2, iog6, gtcg2, clock, pdl/int ltc[23:20] limcrh2 ltcg3 ltc[27:24] limcrl3 iog3, gtcg3, clock, pdl/int ltc[31:28] limcrh3 ltcg4 ltc[35:32] limcrl4 iog0, iog4, gtcg0, clock, pdl/int ltc[39:36] limcrh4 ltcg5 ltc[43:40] limcrl5 iog1, iog5, gtcg1, clock, pdl/int ltc[47:44] limcrh5 ltcg6 ltc[51:48] limcrl6 iog2, iog6, gtcg2, clock, pdl/int ltc[55:52] limcrh6 ltcg7 ltc[59:56] limcrl7 iog3, gtcg3, clock, pdl/int ltc[63:60] limcrh7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-121 v1.1, 2011-03 gpta ? v5, v1.0 28.3.4.6 multiplexer regi ster array programming a total of 54 control registers are required to program the configuration of the output multiplexer, the on-chip trigger and gating multiplexer, and the two input multiplexers of the input/output line sharing block. these iols control registers are combined into a multiplexer register array fifo that can only be read or written sequentially. therefore, the control registers values cannot be accessed directly but must be accessed in a specific sequential order. three registers are available for controlling the multiplexer register array: ? multiplexer register array control register mractl ? multiplexer register array data in register mradin ? multiplexer register array data out register mradout figure 28-78 shows the structure of the multiplexer array fifo with the arrangement of the multiplexer control registers. for programming of the multiplexer array fifo, the following steps must be executed: 1. disable interconnections of the multiplexer array by writing mractl.maen = 0 (default after reset). the multiplexer array is disabled, all cell input lines are driven with 0, and device pins assigned to gpta ? v5 i/o lines or output lines are disconnected. 2. reset the write cycle counter to 0 by writing mractl.wcres = 1. 3. write sequentially the multiplexer control register contents one after the other (54 values) into mradin, starting with the register values for otmcr1, otmcr0, ? up to gimcrh0, gimcrl0 (see figure 28-78 ). after the first mradin write operation, the contents for otmcr1 is at fifo position 1. with each following mradin write operation, it becomes shifted one fifo position upwards. after the 54. mradin write operation, the otmcr1 value is at its final position. the contents of fifo position 54 can be read via register mradout. with each mradin write operation the write cycle counter mractl.fif ofillcnt is incremented by 1. after all fifo entries have been written, the fi fo is locked, bit mr actl.fifofull is set, and further mradin write operations are discarded until bit mractl.wcres is written again with a 0. 4. enable the multiplexer array by writing mractl.maen = 1. this establishes and enables all programmed interconnections. to check the fifo contents, the fifo can be written a second time. at this check mradin is written before mradout is read. th is will return the fi fo contents of the first write sequence in the order of otmcr1, otmcr0, ?, gimcrh0, gimcrl0. before disabling the mult iplexer array fifo, gpta ? v5 output pins that are already enabled as gpta ? v5 output should be switched to gpio function to avoid output spikes. after enabling the multiplexer array fifo again, the gpta ? v5 output can be switched again back to gpta ? v5 output function. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-122 v1.1, 2011-03 gpta ? v5, v1.0 shifting the write data th rough the fifo requires a few clock cycles. when new data becomes written before the fifo is ready to accept them, wait states will be inserted into the write access. if the omcrlg register bit field omgn of t he multiplexer array is programmed with an invalid (reserved) value, the related outputs will be forced to 0. when the array is disabled (mractl.maen = 0), all cell inputs and outputs are disconnected from the gpio lines and are driven with 0. figure 28-78 gpta ? v5 multiplexer array control register fifo structure multiplexer register array fifo mca05980_mod otmcr0 31 otmcr1 omcrl0 omcrh0 mradout 0 limcrl7 limcrh7 limcrl0 limcrh0 output multiplexer control registers ltc input multiplexer control registers gimcrl3 gimcrh3 gimcrl0 gimcrh0 gtc input multiplexer control registers 31 mradin 0 31 mractl 0 51 52 25 26 23 24 9 10 7 8 1 2 omcrl13 omcrh13 trigger/gating multiplexer control registers 53 54 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-123 v1.1, 2011-03 gpta ? v5, v1.0 28.3.5 interrupt sh aring block (is) the gpta ? v5 provides 111 service request source s. these service request sources are generated by different cell types, as shown in table 28-15 . to reduce hardware and software overhead, at maximum five request sources are combined together in service request groups. a service request group has up to five service request inputs and one service reques t output sry which is typically connected outside the gpta ? v5 kernel with a standard interrupt node y and controlled by its srcy register. figure 28-79 service request groups the bits in the service request state r egisters (srssx and srscx) are service request status flags that are set by hardware (type ?h?) when the related event occurs. each gpta ? v5 service request source has its own service request flag. this flag is normally set by hardware but can be set and reset by software. each service request status flag can be read twice, at the same bit location in the srscx register and in the srssx register, and cleared or set by software when writing to the corresponding request bit in srscx or srssx. when writing to srscx or srssx, several request flags table 28-15 gpta ? v5 number of service request sources cell type number of cells number of service request sources/cell total number of request sources dcm 4 3 12 pll 1 1 1 gt 2 1 2 gtc 32 1 32 ltc 64 1 64 sum: 111 mca05981 a t maximum f ive request sources from d cm, pll, gt, gtc, ltc service request node y (srcy register) service request group y sry 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-124 v1.1, 2011-03 gpta ? v5, v1.0 can be cleared at once by one write operatio n. request flags of bit positions that are written with 0 are not changed. this feature allows fast, simple clearing or setting of request flags without affecting other bits in the same service request state register. note that service request flag is always set independently of whether it is enabled or disabled by the related cell; but the service request line to the corresponding service request group becomes only active if the corresponding service request is enabled by the related cell. finally, each service request group y must be enabled by the enable flag that is located in src register y. table 28-16 lists all of the service requests groups with its request sources. note that service requests of gtcs with an odd index number k can be individually redirected via register srnr to a service request group that is assigned mainly to four ltcs. table 28-16 gpta ? v5 service request groups service request group number y request source 1 request source 2 request source 3 request source 4 request source 5 00 dcm0 rising dcm0 falling dcm0 comp. ? ? 01 dcm1 rising dcm1 falling dcm1 comp. ? ? 02 dcm2 rising dcm2 falling dcm2 comp. ? ? 03 dcm3 rising dcm3 falling dcm3 comp. ? ? 04 pll ? ? ? ? 05 gt0 gt1 ? ? ? 06 gtc00 gtc01 1) ??? 07 gtc02 gtc03 1) ??? 08 gtc04 gtc05 1) ??? 09 gtc06 gtc07 1) ??? 10 gtc08 gtc09 1) ??? 11 gtc10 gtc11 1) ??? 12 gtc12 gtc13 1) ??? 13 gtc14 gtc15 1) ??? 14 gtc16 gtc17 1) ??? 15 gtc18 gtc19 1) ??? 16 gtc20 gtc21 1) ??? 17 gtc22 gtc23 1) ??? 18 gtc24 gtc25 1) ??? 19 gtc26 gtc27 1) ??? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-125 v1.1, 2011-03 gpta ? v5, v1.0 20 gtc28 gtc29 1) ??? 21 gtc30 gtc31 1) ??? 22 ltc00 ltc01 ltc02 ltc03 gtc01 2) 23 ltc04 ltc05 ltc06 ltc07 gtc03 2) 24 ltc08 ltc09 ltc10 ltc11 gtc05 2) 25 ltc12 ltc13 ltc14 ltc15 gtc07 2) 26 ltc16 ltc17 ltc18 ltc19 gtc09 2) 27 ltc20 ltc21 ltc22 ltc23 gtc11 2) 28 ltc24 ltc25 ltc26 ltc27 gtc13 2) 29 ltc28 ltc29 ltc30 ltc31 gtc15 2) 30 ltc32 ltc33 ltc34 ltc35 gtc17 2) 31 ltc36 ltc37 ltc38 ltc39 gtc19 2) 32 ltc40 ltc41 ltc42 ltc43 gtc21 2) 33 ltc44 ltc45 ltc46 ltc47 gtc23 2) 34 ltc48 ltc49 ltc50 ltc51 gtc25 2) 35 ltc52 ltc53 ltc54 ltc55 gtc27 2) 36 ltc56 ltc57 ltc58 ltc59 gtc29 2) 37 ltc60 ltc61 ltc62 ltc63 gtc31 2) 1) redirection bit srnr.gtckr = 0 (k = 01, 03, 05, ? 27, 29, 31). 2) redirection bit srnr.gtckr = 1 (k = 01, 03, 05, ? 27, 29, 31). table 28-16 gpta ? v5 service request groups (cont?d) service request group number y request source 1 request source 2 request source 3 request source 4 request source 5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-126 v1.1, 2011-03 gpta ? v5, v1.0 28.3.6 pseudo code description of gpta ? v5 kernel functionality this section describes the functional algorithms of the gpta ? v5 cells in a pseudo code language. 28.3.6.1 fpc algorithm fpck_control_logic() ?to be performed every gpta ? v5 clock? switch (fpck.mode) case prescaler_rising: if (fpck.rising_edge) then prescaler() endif break case prescaler_falling: if (fpck.falling_edge) then prescaler() endif break case delayed_filter_both: delayed_filter() break case immediate_filter_both: case immediate_filter_rising: case immediat e_filter_falling: immediate_filter() break case mixed_fil ter_rising_delayed: if (fpck.signal_filtered == 0) then delayed_filter() else immediate_filter() endif break case mixed_filte r_rising_immediate: if (fpck.signal_filtered == 0) then immediate_filter() else delayed_filter() endif break endswitch www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-127 v1.1, 2011-03 gpta ? v5, v1.0 delayed_filter() if (fpck.filter_clock[n]) then if (fpck.timer >= fpck.compare_value) then if (fpck.compare_value == 0) then //by-pass if (fpck.signal_output.level != fpck.signal_input[m]) then generate pulse on fpck.signal_output.transition fpck.signal_output.level = fpck.signal_input[m] fpck.signal_filtered = fpck.signal_output.level endif else //delay time is over generate pulse on fpck.signal_output.transition fpck.signal_output.level = !fpck.signal_output.level fpck.signal_filtered = fpck.signal_output.level endif fpck.timer = 0 else if (fpck.timer != 0) then //delay time is running if (fpck.rising_edge is detected) then //edge detection done at clock input fpck.rising_edge_glitch = 1 else if (fpck.falling_edge is detected) then //edge detection done at clock input fpck.falling_edge_glitch = 1 endif endif endif if (fpck.signal_output.level != fpck.signal_input[m]) then //expected level fpck.timer ++ else //unexpected level if (fpck.timer != 0) then if (fpck.reset_timer) then fpck.timer = 0 else fpck.timer -- endif endif endif endif endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-128 v1.1, 2011-03 gpta ? v5, v1.0 prescaler() immediate_filter() if (fpck.timer >= fpck.compare_value) then generate pulse on fpck.signal_output.transition generate pulse on fpck.signal_output.level fpck.timer = 0 else fpck.timer ++ endif if (fpck.filter_clock[n]) then if (fpck.timer == 0) then if (fpck.signal_output.level != fpck.signal_input[m]) ) then //change detected generate pulse on fpck.signal_output.transition fpck.signal_output.level = fpck.signal_input[m] if ( (fpck.compare_value == 0) or ((fpck.mode == immediate_filter_rising) and !fpck.signal_input[m]) or ((fpck.mode == immediate_filter_falling) and fpck.signal_input[m]) ) then //by-pass fpck.signal_filtered = fpck.signal_output.level else //start delay time fpck.timer ++ endif endif else if (fpck.timer >= fpck.compare_value) then //delay time is over fpck.timer = 0 fpck.signal_filtered = fpck.signal_output.level else //delay time is running fpck.timer ++ if (fpck.rising_edge) then fpck.rising_edge_glitch = 1 else if (fpck.falling_edge) then fpck.falling_edge_glitch = 1 endif endif endif endif endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-129 v1.1, 2011-03 gpta ? v5, v1.0 variables input, local, output variables of the cell (i, l, o) name k = [0 to 5] for fpc m = [0 to 5] for signal n = [0 to 3] for clock short name (*)fpc used (ilo) comment fpck.signal_input[m] *sinm i signal input selected by fpck.input_source fpck.filter_clock[n] *cinn i filter clock selected by fpck.clock_source fpck.rising_edge *re l signal coming from the edge detect fpck.falling_edge *fe l signal coming from the edge detect fpck.signal_filtered *sf l filtered output signal (after delay time), initialized to 0 at reset fpck.signal_output.transition fpck.signal_output.level *sotk *solk o transition/level of the output signal, initialized to 0 at reset www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-130 v1.1, 2011-03 gpta ? v5, v1.0 global variables name k = [0 to 5] for fpc short name (*)fpc size (bits) function fpck.mode *modk 3 selects one of these modes: delayed_filter_both immediate_filter_both immediate_filter_rising immediate_fi lter_falling mixed_filter_rising_delayed mixed_filter_ri sing_immediate prescaler_rising prescaler_falling fpck.input_source *ipsk 3 selects input signal fpck.clock_source *clkk 2 selects fpc clock fpck.rising_edge_glitch *regk 1 bit is set when rising edge glitch occurs during filtering fpck.falling_edge_glitch *fegk 1 bit is set when falling edge glitch occurs during filtering fpck.timer *timk 16 timer value fpck.reset_timer *rtgk 1 reset timer on glitch in delayed filter mode fpck.compare_value *cmpk 16 compare value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-131 v1.1, 2011-03 gpta ? v5, v1.0 28.3.6.2 pdl-algorithm pdlx_control_logic() ?to be performed every gpta ? v5 clock? if (x == 0) then s1.level = fpc0.signal_output.level s1.transition = fpc0.signal_output.transition s2.level = fpc1.signal_output.level s2.transition = fpc1.signal_output.transition s3.level = fpc2.signal_output.level s3.transition = fpc2.signal_output.transition else //x = 1 s1.level = fpc3.signal_output.level s1.transition = fpc3.signal_output.transition s2.level = fpc4.signal_output.level s2.transition = fpc4.signal_output.transition s3.level = fpc5.signal_output.level s3.transition = fpc5.signal_output.transition endif if (pdlx.three_sensors_enable) then three_sensors() else two_sensors() endif if (pdlx.mux) then pdlx.signal_output1.level = 1 if (pdlx.signal_forward or pdlx.signal_backward) then pdlx.signal_output1.transition = 1 else pdlx.signal_output1.transition = 0 endif else pdlx.signal_output1.transition = s1.transition pdlx.signal_output1.level = s1.level endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-132 v1.1, 2011-03 gpta ? v5, v1.0 two_sensors() if ( ( s1.level and !s2.level and s1.transition) or ( s1.level and s2.level and s2.transition) or (!s1.level and s2.level and s1.transition) or (!s1.level and !s2.level and s2.transition) ) then generate pulse on pdlx.signal_forward else if ( ( s1.level and s2.level and s1.transition) or (!s1.level and s2.level and s2.transition) or (!s1.level and !s2.level and s1.transition) or ( s1.level and !s2.level and s2.transition) ) then generate pulse on pdlx.signal_backward endif endif pdlx.signal_output2.level = s3.level pdlx.signal_output2.transition = s3.transition www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-133 v1.1, 2011-03 gpta ? v5, v1.0 three_sensors() if ( ( s1.level and !s2.level and s3.level and s1.transition) or ( s1.level and !s2.level and !s3.level and s3.transition) or ( s1.level and s2.level and !s3.level and s2.transition) or (!s1.level and s2.level and !s3.level and s1.transition) or (!s1.level and s2.level and s3.level and s3.transition) or (!s1.level and !s2.level and s3.level and s2.transition) ) then generate pulse on pdlx.signal_forward else if ( ( s1.level and s2.level and !s3.level and s1.transition) or (!s1.level and s2.level and !s3.level and s3.transition) or (!s1.level and s2.level and s3.level and s2.transition) or (!s1.level and !s2.level and s3.level and s1.transition) or ( s1.level and !s2.level and s3.level and s3.transition) or ( s1.level and !s2.level and !s3.level and s2.transition) ) then generate pulse on pdlx.signal_backward endif endif if ( (s1.level == s2.level) and (s1.level == s3.level) ) then //error if (!pdlx.signal_output2.level) then //rising edge generate pulse on pdlx.signal_output2.transition endif pdlx.signal_output2.level = 1 pdlx.error = 1 else //no error if (pdlx.signal_output2.level) then //falling edge generate pulse on pdlx.signal_output2.transition endif pdlx.signal_output2.level = 0 endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-134 v1.1, 2011-03 gpta ? v5, v1.0 variables input, local, output variables of the cell (i, l, o) global variables name x = [0,1] for pdl k = [0 to 5] for fpc short name (*)pdl used (ilo) comment fpck.signal_output.transition fpck.signal_output.level sotk solk i transition/level of signals coming from fpc s1.transition, s1.level s2.transition, s2.level s3.transition, s3.level s1t, s1l s2t, s2l s3t, s3l l transition/level of local fpc signals pdlx.signal_output1.transition pdlx.signal_output1.level sit0, sil0 sit2, sil2 o transition/level of output 1 signal going to dcm0/dcm2 pdlx.signal_output2.transition pdlx.signal_output2.level sit1, sil1 sit3, sil3 o transition/level of output 2 signal going to dcm1/dcm3 pdlx.signal_forward *f0 *f1 o forward signals to be counted by ltc pdlx.signal_backward *b0 *b1 o backward signals to be counted by ltc name x = [0,1] for pdl short name (*)pdl size (bits) function pdlx.mux *muxx 1 selects pdl speed signal (instead of fpc feed-through signal) for output 1 pdlx.three_sensors_enable *tsex 1 selects 3-sensor option and pdl error signal (instead of fpc feed-through signal) for output 2 pdlx.error *errx 1 allows the so ftware to read pdl error www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-135 v1.1, 2011-03 gpta ? v5, v1.0 28.3.6.3 dcm-algorithm dcmk_control_logic() ?to be performed every gpta ? v5 clock? compare() add_clock() compare() add_clock() check_input() if (dcmk.timer == dcmk.capcom_value) then trig(dcmk.service_request_compare) endif if (dcmk.clock_request) then generate dcmk.signal_output dcmk.clock_request = 0 endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-136 v1.1, 2011-03 gpta ? v5, v1.0 check_input() if (dcmk.signal_input.transition) then if (dcmk.signal_input.level) then //rising edge trig(dcmk.service_request_rising) if (dcmk.capture_on_rising_edge) then dcmk.capture_value = dcmk.timer else if (dcmk.capcom_opposite) then dcmk.capcom_value = dcmk.timer endif endif if (dcmk.clear_on_rising_edge) then dcmk.timer = 0 else dcmk.timer ++ endif if (dcmk.clock_on_rising_edge) then generate pulse on dcmk.signal_output endif else //falling edge trig(dcmk.service_request_falling) if (!dcmk.capture_on_rising_edge) then dcmk.capture_value = dcmk.timer else if (dcmk.capcom_opposite) then dcmk.capcom_value = dcmk.timer endif endif if (dcmk.clear_on_falling_edge) then dcmk.timer = 0 else dcmk.timer ++ endif if (dcmk.cl ock_on_falling_edge) then generate pulse on dcmk.signal_output endif endif else dcmk.timer ++ endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-137 v1.1, 2011-03 gpta ? v5, v1.0 variables input, local, output variables of the cell (i, l, o) global variables name k = [0 to 3] for dcm short name used (ilo) comment dcmk.signal_input.transition dcmk.signal_input.level *sitk *silk i input of the cell dcmk.signal_output *sok o output of the cell dcmk.service_request_rising *rtqk o s ervice request on rising edge dcmk.service_request_falling *ftqk o service request on falling edge dcmk.service_request_compare *ctqk o s ervice request on compare event name k = [0 to 3] for dcm short name (*)dcm size (bits) function dcmk.capture_on_rising_edge *rcak 1 capture into capture_value on rising edge dcmk.capcom_opposite *ocak 1 capture into capcom_value on opposite edge defined by rcak dcmk.clear_on_rising_edge *rzek 1 clear timer on rising edge dcmk.clear_on_fa lling_edge *fzek 1 clear ti mer on falling edge dcmk.clock_on_rising_edge *rckk 1 generate a single clock pulse on rising edge dcmk.clock_on_falling_edge *fckk 1 generate a single clock pulse on falling edge dcmk.clock_request *qckk 1 generate a single clock pulse immediately dcmk.request_enable_rising *rrek 1 enable request on rising edge dcmk.request_enable_falling *frek 1 enable request on falling edge dcmk.request_enable_compare *crek 1 request enable on compare dcmk.timer *timk 24 timer value dcmk.capture_value *cavk 24 capture value dcmk.capcom_value *covk 24 capture/compare value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-138 v1.1, 2011-03 gpta ? v5, v1.0 28.3.6.4 pll-algorithm pll_control_logic() ?to be performed every gpta ? v5 clock? if ( (pll.automatic_end) and (pll.event) ) then //allow compensation pll.perform_end = 1 endif if ( (pll.counter_mtick == 0) and ((pll.perform_end) or (!pll.automatic_end)) ) then //compensation finished or no automatic compensation pll.counter_mtick = pll.number_mtick pll.perfom_end = 0 endif if ( (pll.counter_mtick != 0) and ((pll.perf orm_end) or (bit 24 of pll.delta)) ) then //output pulse is necessary generate pulse on pll.signal_output pll.counter_mtick -- if (pll.counter_mtick == 0) then trig(pll.service_request_trigger) endif endif if (bit 24 of pll.delta) then //delta is < 0 pll.delta = pll.delta + pll.reload_value generate pulse on pll.signal_uncomp else //delta is >= 0 pll.delta = pll.delta + (0xffff0000 or (pll.step)) endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-139 v1.1, 2011-03 gpta ? v5, v1.0 variables input, local, output variables of the cell (i, l, o) global variables name k = [0 to 3] for dcm short name (*)pll used (ilo) comment dcmk.signal_output sok i input of the cell from dcm pll.event *eve l input selected by the multiplexer pll.signal_output *so o output of the cell pll.signal_uncomp *su o uncompensated output of the cell pll.service_request_trigger *sqt o service request when counter reaches zero name short name (*)pll size (bits) function pll.mux *mux 2 selects the signal input for pll pll.automatic_end *aen 1 performs the acceleration/ deceleration correction pll.perform_end *pen 1 makes it possible to decrement the counter at full speed pll.request_enable *ren 1 allows a request when microtick counter reaches zero pll.number_mtick *mti 16 number of microticks per input signal period pll.counter_mtick *cnt 16 microtick counter pll.step *stp 16 step value, to be added to positive/zero delta register pll.reload_value *rev 24 reload value, to be added to negative delta register pll.delta *dtr 25 delta register www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-140 v1.1, 2011-03 gpta ? v5, v1.0 28.3.6.5 gt-algorithm gtm_control_logic() ?to be performed every gpta ? v5 clock? variables input, local, output variables of the cell (i, l, o) global variables if (gtm.run) then if (event on gtm.clock_in[p ] selected by gtm.clock_mux) then gtm.timer ++ if (overflow of gtm.timer) then gtm.timer = gtm.reload_value trig(gtm.service_request_trigger) endif endif endif name m = [0, 1] for gt p = [0 to 7] for clock bus short name (*)gt used (ilo) comment gtm.clock_in[p] *cinmp i input coming from clock bus gtm.timer_greater_equal_comp tgem o timer is greater or equal gtm.timer_event tevm o signal for timer change gtm.service_request_trigger *sqtm o service request line name m = [0, 1] for gt short name (*)gt size (bits) function gtm.run *runm 1 enables timer gtm.scale_compare *scom 4 selects compare flag gtm.clock_mux *muxm 3 selects clock from clock bus gtm.request_enable *renm 1 allows a request when timer overflows gtm.timer *timm 24 timer value gtm.reload_value *revm 24 reload value when timer overflows www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-141 v1.1, 2011-03 gpta ? v5, v1.0 28.3.6.6 gtc-algorithm gtck_control_logic() ?to be performed every gpta ? v5 clock? capture(m) if (gtck.cell_enable) then switch (gtck.mode) case capture_t0: capture(0) break case capture_t1: capture(1) break case compare_t0: compare(0) break case compare_t1: compare(1) endswitch if ( (gtck.one_shot_mode) and (gtck.event) ) then gtck.cell_enable = 0 endif endif manage_mux() if (gtck.signal_input) then trig(gtck.service_request_trigger) gtck.x = gtm.timer gtck.event = 1 else gtck.event = 0 endif ck.event = 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-142 v1.1, 2011-03 gpta ? v5, v1.0 compare(m) set_data_out(mode) if ( ((gtck.x == gtm.timer) and ((gtck.x_ write_access) or (gtm.timer_event))) or ((gtck.greater_equal_select) and (gtck.x_write_access) and (gtm.timer_greater_equal_comp)) ) then if (gtck.capture_after_compare) then if (gtck.capture_alternate_timer) then gtck.x = gt(!m).timer else gtck.x = gtm.timer endif endif trig(gtck.service_request_trigger) gtck.event = 1 else gtck.event = 0 endif switch (mode) case 00b: //no change break case 01b: //toggle gtck.data_out = !gtck.data_out break case 10b: //clear gtck.data_out = 0 break case 11b: //set gtck.data_out = 1 break endswitch gtck.output_state = gtck.data_out www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-143 v1.1, 2011-03 gpta ? v5, v1.0 manage_mux() if ((gtck.event or gtck.oia) and gtck.o cm != x00) then //local event set_data_out(gtck.output_control_mode.[1:0]) if (!gtck.bypass) then //no bypass gtck.output_mode_out = gtck.output_control_mode.[1:0] else if (gtck.output_control_mode.2) then //bypass, input link enabled gtck.output_ mode_out = gtck.output_mode_in else //bypass, input link disabled gtck.output_mode_out = 00b endif endif else //no local event if (gtck.output_control_mode.2) then //input link enabled set_data_out(gtck.output_mode_in) gtck.output_mo de_out = gtck.output_mode_in else //input link disabled set_data_out(00b) gtck.output_mode_out = 00b endif endif if ( (gtck.enable_of_action) and ((gtck.output_mode_in.1) or (gtck.output_mode_in.0)) ) then gtck.cell_enable = 1 gtck.enable_of_action = 0 endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-144 v1.1, 2011-03 gpta ? v5, v1.0 variables input, local, output variables of the cell (i, l, o) name k = [0 to 31] for gtc m = [0, 1] for gt short name (*)gtc used (ilo) comment gtm.timer_greater_equal_comp tgem i timer is greater or equal gtm.timer_event tevm i signal for timer change gtm.timer *timm i timer value gtck.data_in *dink i data input from input multiplexer gtck.output_mode_in *m1ik *m0ik i link signals from preceding cell gtck.x_write_access *xwa l i ndicates that gtck.x was modified gtck.event *eve l local event gtck.signal_input *ins l qualified input signal gtck.service_request_trigger *sqsk o service request line gtck.data_out *douk o data output for output multiplexer gtck.output_mode_out *m1ok *m0ok o link signals to following cell www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-145 v1.1, 2011-03 gpta ? v5, v1.0 global variables name k = [0 to 31] for gtc short name (*)gtc size (bits) comment gtck.mode *modk 2 operation mode: capture_t0, capture_t1, compare_t0, compare_t1 gtck.one_shot_mode *osmk 1 one shot mode gtck.request_enable *renk 1 allows a request on event gtck.input_rising_edge_select (capture mode) gtck.greater_equal_select (compare mode) *redk *gesk 1 1 selects rising edge of input pin selects >= compare mode gtck.input_falling_edge_select (capture mode) gtck.capture_after_compare (compare mode) *fedk *cack 1 1 selects falling edge of input pin selects capture after compare gtck.capture_alternate_timer (compare mode) *catk 1 capture alternate global timer after compare gtck.bypass *bypk 1 local ev ents bypassed for output link gtck.enable_of_action *eoak 1 enables cell on action communicated via link gtck.cell_enable *cenk 1 cell enable state gtck.output_control_mode *ocmk 3 output control mode gtck.output_immediate_action *oiak 1 forces immediate action gtck.output_state *outk 1 read value of data_out gtck.x *xk 24 capture/compare value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-146 v1.1, 2011-03 gpta ? v5, v1.0 28.3.6.7 ltc-algorithm for cells 0 to 62 ltck_control_logic() ?to be performed every gpta ? v5 clock? if (ltck.cell_enable) then switch (ltck.mode) case timer_free_run: ltck.reset_timer_bit = 0 timer() break case timer_reset: if (ltck.event_in) then ltck.reset_timer_bit = 1 endif timer() break; case capture: capture() break case compare: compare() break endswitch if ((ltck.one_shot_mode) and (ltck.event)) then ltck.cell_enable = 0 endif endif manage_mux() www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-147 v1.1, 2011-03 gpta ? v5, v1.0 timer() if ( (ltck.x == 0xffff) and (ltck.x_write_access) ) then //above condition is also true for timer overflow or software reset trig(ltck.service_request_trigger) ltck.event = 1 else ltck.event = 0 endif if (ltck.signal_input) then if (ltck.reset_timer_bit) then //timer must be reset ltck.reset_timer_bit = 0 ltck.x = 0xffff if (ltck.coherent_update_enable) then ltck.select_line_value = !ltck.select_line_value ltck.coherent_update_enable = 0 endif else //timer runs normally ltck.x ++ endif endif ltck.event_out = ltck.event www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-148 v1.1, 2011-03 gpta ? v5, v1.0 capture() compare() if (ltck.signal_input) then trig(ltck.service_request_trigger) ltck.x = ltck.y_in ltck.event = 1 else ltck.event = 0 endif ltck.event_out = ltck.event if ( ((ltck.select_in) and (ltck.select_on_high_level)) or ((!ltck.select_in) and (ltck.select_on_low_level)) ) then //cell is active if ( (ltck.x == ltck.y_in) and ((ltck.x_write_access) or (l tck.timer_event_in)) ) then //event trig(ltck.service_request_trigger) ltck.event = 1 else ltck.event = 0 endif ltck.event_out = ltck.event else //cell is inactive ltck.event_out = ltck.event_in endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-149 v1.1, 2011-03 gpta ? v5, v1.0 manage_mux() if ( (ltck.mode == timer_free_run) or (ltck.mode == timer_reset) ) then ltck.y_out = ltck.x if (the timer has been modified) then //increment, reset, software overwrite ltck.timer_event_out = 1 else ltck.timer_event_out = 0 endif ltck.select_out = ltck.select_line_value else //capture mode or compare mode ltck.y_out = ltck.y_in ltck.timer_event_out = ltck.timer_event_in ltck.select_line_value = ltck.select_in ltck.select_out = ltck.select_in endif if (ltck.event) then //local event set_data_out(ltck.output_control_mode.[1:0]) if (!ltck.bypass) then //no bypass ltck.output_mode_out = ltck.output_control_mode.[1:0] endif else //no local event if (ltck.output_control_mode.2) //input link enabled set_data_out(ltck.output_mode_in) if (!ltck.bypass) then //no bypass ltck.output_mode_out = ltck.output_mode_in endif else //input link disabled set_data_out(00 b ) if (!ltck.bypass) then //no bypass ltck.output_mode_out = 00 b endif endif endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-150 v1.1, 2011-03 gpta ? v5, v1.0 manage_mux() - continued if (ltck.globalbypass) then //global bypass ltck.output_mode_alternate_out = ltck.output_mode_alternate_in if (ltck.bypass) then // bypass ltck.output_mode_out = ltck.output_mode_alternate_in endif else if (ltck.output_control_mode.2) then //bypass, input link enabled ltck.output_mode_alter nate_out = ltck.output_mode_in if (ltck.bypass) then // bypass ltck.output_mode_out = ltck.output_mode_in endif else //bypass, input link disabled ltck.output_mode_alternate_out = 00 b if (ltck.bypass) then // bypass ltck.output_mode_out = 00 b endif endif endif if ( (ltck.enable_of_action) and ((ltck.output_mode_in.1) or (ltck.output_mode_in.0)) ) then //enable condition ltck.cell_enable = 1 ltck.enable_of_action = 0 endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-151 v1.1, 2011-03 gpta ? v5, v1.0 set_data_out(mode) switch (mode) case 00b: //no change break case 01b: //toggle ltck.data_out = !ltck.data_out break case 10b: //clear ltck.data_out = 0 break case 11b: //set ltck.data_out = 1 break endswitch ltck.output_state = ltck.data_out www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-152 v1.1, 2011-03 gpta ? v5, v1.0 variables input, local, output variables of the cell (i, l, o) name short name (*)ltc used (ilo) comment ltck.data_in *dinkp i data input from input multiplexer ltck.y_in *yik i timer comi ng from preceding cell ltck.output_mode_in *m1ik *m0ik i link signals coming from preceding cell ltck.output_mode_alternate_in *m3ik *m2ik i alternative link signals coming from preceding cell ltck.timer_event_in *tik i sign al for timer change from preceding cell ltck.event_in *eik i signal for event from following cell ltck.select_in *si i select signal from preceding cell ltck.x_write_access *xwa l indicates that ltck.x was modified ltck.select_line_value *slv l internal value for select line reset value: 0 ltck.signal_input *ins l qualified input signal for timer mode and capture mode ltck.reset_timer_bit *rtm l flip-flop to reset timer on next clock ltck.event *eve l local event ltck.data_out *douk o data output for output multiplexer ltck.service_request_trigger * sqtk o service request line ltck.y_out *yok o timer going to following cell ltck.output_mode_out *m1ok *m0ok o link signals to following cell ltck.output_mode_alternate_out *m3ok *m2ok o link signals to following cell ltck.timer_event_out *tok o event output to following cell ltck.select_out *so o select output to following cell ltck.event_out *eok o event output to preceding cell www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-153 v1.1, 2011-03 gpta ? v5, v1.0 global variables name k = [0 to 62] for ltc short name (*)ltc size (bits) comment ltck.mode *modk 2 operation mode: timer, timer_reset, capture, compare ltck.one_shot_mode *osmk 1 one shot mode ltck.request_enable *renk 1 allows a request on event ltck.input_rising_edge_select (timer mode, capture mode) ltck.select_on_low_level (compare mode) *redk *solk 1 1 selects rising edge of input pin enables compare on low level of select line ltck.input_falling_edge_select (timer mode, capture mode) ltck.select_on_high_level (compare mode) *fedk *sohk 1 1 selects falling edge of input pin enables compare on high level of select line ltck.bypass (capture mode, compare mode) *bypk 1 local events bypassed for output link ltck.globalbypass *gbypk 1 alternative output links forwarded to alternative output link ltck.enable_of_action (capture mode, compare mode) *eoak 1 enables cell on action communicated via link ltck.input_line_mode *ilmk 1 selects edge input line mode ltck.coherent_update_enable (timer mode) ltck.select_line_level (capture mode, compare mode) *cudk *sllk 1 1 selects coherent update select line level ltck.cell_enable *cenk 1 cell enable state ltck.output_control_mode *ocmk 3 output control mode ltck.output_immediate_action *o iak 1 forces immediate action ltck.output_state *outk 1 read value of data_out ltck.x *xk 16 timer/capture/compare value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-154 v1.1, 2011-03 gpta ? v5, v1.0 28.3.6.8 ltc algorithm for cell 63 ltc63_control_logic() ?to be performed every gpta ? v5 clock? copy() copy() compare() if (ltc63.cell_enable) then if (ltc63.signal_input) then ltc63.x = ltc63.x_shadow trig(ltc63.service_request_trigger) if (ltc63.one_shot_mode) then ltc63.cell_enable = 0 endif endif endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-155 v1.1, 2011-03 gpta ? v5, v1.0 compare() if ( (ltc63.x_write_access) or (ltc63.timer_event_in) ) then if (ltc63.bit_rev_mode) then ltc63.y_comp = ltc63.y_rev else ltc63.y_comp = ltc63.y_in endif if ( (ltc63.x > ltc63.y_comp) or (ltc63.x == ffffh) ) then //output must be 1 ltc63.data_out = 1 ltc63.event_out = 0 else //output must be 0 if (ltc63.data_out == 1) then //falling edge on output trig(ltc63.service_request_trigger) ltc63.event_out = 1 else ltc63.event_out = 0 endif ltc63.data_out = 0 endif ltc63.output_state = ltc63.data_out endif www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-156 v1.1, 2011-03 gpta ? v5, v1.0 variables input, local, output variables of the cell (i, l, o) name short name (*)ltc used (ilo) comment ltc63.data_in *din63 i data input from input multiplexer ltc63.y_in *yi63 i timer coming from preceding cell ltc63.timer_event_in *ti63 i signal for timer change from preceding cell ltc63.y_rev *yr l timer coming from preceding cell, bit reversed ltc63.y_comp *yc l timer actually used for compare ltc63.x_write_access *xwa l indicates that ltc63.x was modified ltc63.signal_input *ins l qualified input signal ltc63.data_out *dou63 o data output for output multiplexer ltc63.service_request_trigger *sqt63 o service request line ltc63.event_out *eo63 o event output to preceding cell www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-157 v1.1, 2011-03 gpta ? v5, v1.0 global variables name short name (*)ltc size (bits) comment ltc63.bit_rev_mode *brm63 1 bit reverse mode ltc63.one_shot_mode *osm63 1 one shot mode for copy ltc63.request_enable *ren63 2 allows a request on compare or copy ltc63.input_rising_edge_select *red63 1 selects rising edge of input pin ltc63.input_falling_edge _select *fed63 1 selects fa lling edge of input pin ltc63.input_line_mode *ilm63 1 selects edge input line mode ltc63.cell_enable *cen63 1 cell enable state for copy ltc63.output_state *out63 1 read value of data_out ltc63.x *x63 16 compare value ltc63.x_shadow *xs63 16 shadow compare value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-158 v1.1, 2011-03 gpta ? v5, v1.0 28.3.7 programming of a gpta ? v5 unit a hierarchical top-down design approach may be used to implement a complex signal processing circuitry as follows: ? partitioning the complex signal processi ng circuitry into simple function cells. ? implementing each simple function cell by configuring the ltc and/or gtc cells which can be tied together for realizing a common signal operation. ? implementing necessary signal pre-processing tasks by configuring the fpc, pdl, dcm and pll cells accordingly. ? defining and configuring all input/output port pins required as clock source, trigger input or signal output. table 28-17 summarizes all of the software ta sks to be implemen ted for ge tting a gpta ? v5 unit into operation. table 28-17 software tasks controlling a gpta ? v5 unit gpta ? v5 shell initialization gpta ? v5 module clock enable fractional divider setting unit enable configuration of interrupt handling gpta ? v5 kernel initialization fpc: pdl: selection of operating mode (prescaler, filter or feed-through) selection of operating mode (phase discriminator or feed-through) input channel selection 2- or 3-sensor mode selection clock selection pll: configuration of prescaler factor or debounce mode selection of input channel dcm: estimation of input signal period width selection of reset event for timer configuration of output signal frequency selection of trigger source for capture event handling of input signal period length variation selection of trigger source for capture compare register update interrupt request enable on end of output pulse generation interrupt request enable on input edge or compare event www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-159 v1.1, 2011-03 gpta ? v5, v1.0 clock bus setup selection and configuration of 8 clock sources for gt, gtc and ltc cells gt: gtc: selection of timer clock source selection of operating mode (capture or compare) and time base (gt0 or gt1) configuration of timer width (reload value, tge flag) configuration of trigger events for capture mode or selection of a relational operator for compare mode interrupt request enable on timer overflow interrupt request enable on capture or compare event start global timer(s) configuration of data output triggered by a gtc event ltc: iols: selection of operating mode (timer, capture or compare) configuration of the multiplexer array to link gtc and ltc data outputs/inputs to external port pins or other cells by writing the multiplexer register array fifo configuration of the on-chip trigger and gating signal multiple xer array to link gtc and ltc data outputs to on-chip modules by writing the multiplexer register array fifo selection of trigger source for timer, capture or compare mode configuration of port output source configuration of trigger event for timer, capture or compare mode interrupt request enable on timer, capture or compare event configuration of data output triggered by an ltc event port initialization definition of electrical port characteristic configuration of port pin direction (input or output) table 28-17 software tasks controlling a gpta ? v5 unit (cont?d) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-160 v1.1, 2011-03 gpta ? v5, v1.0 28.4 gpta0/1 kernel registers this section describes the kernel registers of the gpta0 and gpta1 unit. gpta0/1 kernel register overview figure 28-80 gpta0 and gpta1 kernel registers in the TC1798, the registers of the gpta ? v5 units are located in the following address ranges. table 28-18 registers address space module base address end address note gpta0 f000 1800 h f000 1fff h - gpta1 f000 2000 h f000 27ff h - ltca2 f000 2800 h f000 2fff h - 1) k = 0-5 2) k = 0-3 3) k = 0-2 4) k = 00-31 5) k = 00-63 6) n = 0-3 7) g = 0-13 8) g = 0-7 9) g = 0-3 mca0598 2 fpctimk control registers interrupt & iols registers data registers dcmtimk dcmcavk srscn dcmcovk pllmti pllstp pllcnt pllrev plldtr gttimk gtrevk gtcxrk ltcxrk srssn fpcstat fpcctrk pdlctr dcmctrk pllctr ckbctr gtctrk gtcctrk ltcctrk srnr mractl mradin mradout 1) 2) 2) 2) 2) 1) 6) 3) 3) 4) 4) 5) 5) 6) 3) multiplexer array fifo registers omrclg omrchg limcrlg limcrhg gimcrlg gimcrhg 7) 7) 9) 9) 8) 8) note: the multiplexer array fifo registers are not directly accessibl e! www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-161 v1.1, 2011-03 gpta ? v5, v1.0 table 28-19 registers overview - gp ta0 and gpta1 kernel registers register short name register long name offset addr. 1) access mode reset class description see read write gpta0_ clc 2) gpta clock control register 0000 h u, sv sv, e 3 page 28-300 gpta0_ dbgctr 2) gpta debug clock control register 0004 h u, sv u, sv 3 page 28-305 id gpta identification register 0008 h u, sv nbe 3 page 28-166 gpta0_ fdr 2) gpta fractional divider register 000c h u, sv sv, e 3 page 28-301 srsc0 service request state clear register 0 010 h u, sv u, sv 3 page 28-223 srss0 service request state set register 0 014 h u, sv u, sv 3 page 28-225 srsc1 service request state clear register 1 018 h u, sv u, sv 3 page 28-226 srss1 service request state set register 1 01c h u, sv u, sv 3 page 28-227 srsc2 service request state clear register 2 020 h u, sv u, sv 3 page 28-228 srss2 service request state set register 2 024 h u, sv u, sv 3 page 28-229 srsc3 service request state clear register 3 028 h u, sv u, sv 3 page 28-230 srss3 service request state set register 3 02c h u, sv u, sv 3 page 28-231 srnr service request node redirection register 030 h u, sv u, sv 3 page 28-232 mractl multiplexer register array control register 0038 h u, sv u, sv 3 page 28-207 mradin multiplexer register array data in register 003c h u, sv, 32 u, sv, 32 3 page 28-208 mradout multiplexer register array data out register 0040 h u, sv, 32 u, sv, 32 3 page 28-209 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-162 v1.1, 2011-03 gpta ? v5, v1.0 fpcstat filter and prescaler cell status register 0044 h u, sv u, sv 3 page 28-167 fpcctrk filter and prescaler cell control register k (k = 0-5) 0048 h +k 8 u, sv u, sv 3 page 28-168 fpctimk filter and prescaler cell timer register k (k = 0- 5) 004c h +k 8 u, sv u, sv 3 page 28-170 pdlctr phase discrimination logic control register 0078 h u, sv u, sv 3 page 28-171 dcmctrk duty cycle measurement control register k (k = 0-3) 0080 h +k 16 u, sv u, sv 3 page 28-173 dcmtimk duty cycle measurement timer register k (k = 0-3) 0084 h +k 16 u, sv u, sv 3 page 28-175 dcmcavk duty cycle measurement capture register k (k = 0-3) 0088 h + k 16 u, sv u, sv 3 page 28-175 dcmcovk duty cycle measurement capture/compare register k (k = 0-3) 008c h +k 16 u, sv u, sv 3 page 28-176 pllctr phase locked loop control register 00c0 h u, sv u, sv 3 page 28-177 pllmti phase locked loop micro tick register 00c4 h u, sv u, sv 3 page 28-178 pllcnt phase locked loop counter register 00c8 h u, sv u, sv 3 page 28-179 pllstp phase locked loop step register 00cc h u, sv u, sv 3 page 28-179 pllrev phase locked loop reload register 00d0 h u, sv u, sv 3 page 28-180 table 28-19 registers overview - gp ta0 and gpta1 kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-163 v1.1, 2011-03 gpta ? v5, v1.0 plldtr phase locked loop delta register 00d4 h u, sv u, sv 3 page 28-181 ckbctr clock bus control register 00d8 h u, sv u, sv 3 page 28-185 gtctrk global timer control register k (k = 0, 1) 00e0 h + k 16 u, sv u, sv 3 page 28-182 gtrevk global timer reload value register k (k = 0, 1) 00e4 h +k 16 u, sv u, sv 3 page 28-184 gttimk global timer register k (k = 0, 1) 00e8 h + k 16 u, sv u, sv 3 page 28-183 gtcctrk global timer cell control register k (k = 00-31) 0100 h +k 8 u, sv u, sv 3 page 28-187 page 28-189 gtcxrk global timer cell x register k (k = 00-31) 0104 h +k 8 u, sv u, sv 3 page 28-191 ltcctrk local timer cell control register k (k = 00-62) 0200 h +k 8 u, sv u, sv 3 page 28-192 page 28-198 page 28-201 ltcxrk local timer cell x register k (k = 00-62) 0204 h +k 8 u, sv u, sv 3 page 28-205 ltcctr63 local timer cell control register 63 03f8 h u, sv u, sv 3 page 28-204 ltcxr63 local timer cell x register 63 03fc h u, sv u, sv 3 page 28-206 gpta0_ edctr 2) gpta clock enable/disable control register 0400 h u, sv u, sv 3 page 28-303 table 28-19 registers overview - gp ta0 and gpta1 kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-164 v1.1, 2011-03 gpta ? v5, v1.0 bit protection bits with bit protection (this is valid, for example, for all bits in the service request state registers) are not changed during a read-mod ify-write instruction, for example when otmcrg on-chip trigger and gating signal multiplexer control register of group g (g = 0-1) not directly address -able; see page 28 -121 n.a. n.a. 3 page 28-214 omcrlg output multiplexer control register for lower half of group g (g = 0-13) n.a. n.a. 3 page 28-210 omcrhg output multiplexer control register for upper half of group g (g = 0-13) n.a. n.a. 3 page 28-212 gimcrlg input multiplexer control register for lower half of gtc group g (g = 0-3) n.a. n.a. 3 page 28-215 gimcrhg input multiplexer control register for lower half of gtc group g (g = 0-3) n.a. n.a. 3 page 28-217 limcrlg input multiplexer control register for upper half of ltc group g (g = 0-7) not directly address -able; see page 28 -121 n.a. n.a. 3 page 28-219 limcrlg input multiplexer control register for upper half of ltc group g (g = 0-7) n.a. n.a. 3 page 28-221 1) the absolute register addres s is calculated as follows: unit base address + offset a ddress (shown in this column) 2) only implemented in gpta0 kernel. table 28-19 registers overview - gp ta0 and gpta1 kernel registers (cont?d) register short name register long name offset addr. 1) access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-165 v1.1, 2011-03 gpta ? v5, v1.0 hardware sets a request state bit between the read and the write of the read-modify-write sequence. for bit protected bits it is guaranteed that a hardware setting operation always has priority. thus, no hardware triggered events are lost. bits with bit protection are marked in the corresponding bit descriptions. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-166 v1.1, 2011-03 gpta ? v5, v1.0 28.4.1 gpta ? v5 identification register the gpta ? v5 identification register id contains read-only information about the module version. gpta0_id gpta0 identification register (08 h ) reset value: 0029 c0xx h gpta1_id gpta1 identification register (08 h ) reset value: 0029 c0xx h ltca2_id ltca2 identificati on register (08 h ) reset value: 002a c0xx h 31 16 15 8 7 0 mod_number mod_type mod_rev rrr field bits type description mod_rev [7:0] r module revision number mod_rev defines the module revision number. the value of a module revi sion starts with 01 h (first revision). gptav5 will start with module revision 05 h . mod_type [15:8] r module number value this bit field defines the module as a 32 bit module: c0 h mod_num [31:16] r module number value this bit field defines the identification number for the gpta: 0029 h and ltca: 002a h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-167 v1.1, 2011-03 gpta ? v5, v1.0 28.4.2 fpc registers gpta0_fpcstat gpta0 filter and prescaler cell status register (044 h ) reset value: 0000 0000 h gpta1_fpcstat gpta1 filter and prescaler cell status register (044 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 feg 5 feg 4 feg 3 feg 2 feg 1 feg 0 0 reg 5 reg 4 reg 3 reg 2 reg 1 reg 0 r rwh rwh rwh rwh rwh rwh r rwh rwh rwh rwh rwh rwh field bits type description regk (k = 0-5) krwh rising edge glitch flag for fpck 0 b no rising edge of glitch detected during filtering 1 b rising edge of glitch detected during filtering bits regk are bit protected (see section 28.4.2 ). fegk (k = 0-5) k+8 rwh falling edge glitch flag for fpck 0 b no falling edge of glitch detected during filtering 1 b falling edge of glitch detected during filtering bits fegk are bit protected (see section 28.4.2 ). 0 [7:6], [31:14] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-168 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_fpcctrk (k = 0-5) gpta0 filter and prescaler cell control register k (048 h +k*8 h ) reset value: 0000 0000 h gpta1_fpcctrk (k = 0-5) gpta1 filter and prescaler cell control register k (048 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0rtgclkipsmod rrwrwrwrw 1514131211109876543210 cmp rw field bits type description cmp [15:0] rw threshold value of filter and prescaler cell k cmp is the 16-bit threshold value that is compared with the 16-bit timer value fpctimk.tim. mod [18:16] rw operation mode selection for fpck 000 b delayed debounce filter mode on both edges 001 b immediate debounce filter mode on both edges 010 b rising edge: immediate debounce filter mode, falling edge: no filtering 011 b rising edge: no filtering, falling edge: immediate debounce filter mode 100 b rising edge: delayed debounce filter mode, falling edge: immediate debounce filter mode 101 b rising edge: immediate debounce filter mode, falling edge: delayed debounce filter mode 110 b prescaler mode (triggered on rising edge) 111 b prescaler mode (triggered on falling edge) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-169 v1.1, 2011-03 gpta ? v5, v1.0 ips [21:19] rw input line selection for fpck ips determines the signal input used for edge detection. 000 b signal input sink0 selected 001 b signal input sink1 selected 010 b signal input sink2 selected 011 b signal input sink3 selected 100 b signal input sink4 = gpta ? v5 module clock f gpta selected 101 b signal input sink5 = preceding fpc output solk-1 selected; sin05 is connected to sol5 11x b reserved clk [23:22] rw clock selection for fpck clk selects the clock signal used for edge detection. 00 b ciock input line 0 selected (gpta ? v5 module clock f gpta ) 01 b clock bus line 1 select ed (local pll clock) 10 b clock bus line 2 selected (prescaled) gpta ? v5 module clock f gpta or pll clock from other unit or dcm 3 clock 11 b clock bus line 3 selected dcm 2 clock or pll clock of other unit or uncompensated pll clock or uncompensated pll clock of other unit rtg 24 rw reset timer for fpck on glitch 0 b timer for fpck is decremented on glitch 1 b timer for fpck is cleared on glitch this bit is effective in delayed debounce filter mode only. 0 [31:25] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-170 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_fpctimk (k = 0-5) gpta0 filter and prescaler cell timer register k (048 h +k*8 h +4 h ) reset value: 0000 0000 h gpta1_fpctimk (k = 0-5) gpta1 filter and prescaler cell timer register k (048 h +k*8 h +4 h ) reset value: 0000 0000 h 31 16 15 0 0tim rrwh field bits type description tim [15:0] rwh timer value of filter and prescaler cell k 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-171 v1.1, 2011-03 gpta ? v5, v1.0 28.4.3 phase discriminator registers gpta0_pdlctr gpta0 phase discrimination logic control register (078 h ) reset value: 0000 0000 h gpta1_pdlctr gpta1 phase discrimination logic control register (078 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 err 1 tse 1 mux 1 0 err 0 tse 0 mux 0 r rwh rw rw r rwh rw rw field bits type description mux0 0rw output signal source selection for pdl0 0 b dcm0 cell input is driven by fed-through fpc0 output lines 1 b dcm0 cell input is provided with pdl0 ?forward? and ?backward? pulses tse0 1rw 3-sensor mode enable for pdl0 0 b pdl0 operates in ?2-sensor mode? and dcm1 cell input is driven by fed-through fpc2 output lines 1 b pdl0 operates in ?3-sensor mode? and dcm1 cell input is provided with pdl0 error information err0 2rwh error flag for pdl0 0 b no error has occurred 1 b error detected in ?3-sensor mode?: all pdl0 input signals are simultaneously provided with high or low level bit err0 is bit protected (see page 28-167 ). mux1 4rw output signal source selection for pdl1 0 b dcm2 cell input is driven by fed-through fpc3 output lines 1 b dcm2 cell input is provided with pdl1 ?forward? and ?backward? pulses www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-172 v1.1, 2011-03 gpta ? v5, v1.0 tse1 5rw 3-sensor mode enable for pdl1 0 b pdl1 operates in ?2-sensor mode? and dcm3 cell input is driven by fed-through fpc5 output lines 1 b pdl1 operates in ?3-sensor mode? and dcm3 cell input is provided with pdl1 error information err1 6rwh error flag for pdl1 0 b no error has occurred 1 b error detected in ?3-sensor mode?: all pdl1 input signals are simultaneously provided with high or low level bit err1 is bit protected (see page 28-167 ). 0 3, [31:7] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-173 v1.1, 2011-03 gpta ? v5, v1.0 28.4.4 duty cycle measurement registers gpta0_dcmctrk (k = 0-3) gpta0 duty cycle measurement control register k (080 h +k*10 h ) reset value: 0000 0000 h gpta1_dcmctrk (k = 0-3) gpta1 duty cycle measurement control register k (080 h +k*10 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 cre fre rre qck fck rck fze rze oca rca r rw rw rw w rw rw rw rw rw rw field bits type description rca 0rw trigger source selection for capture event 0 b timer contents are copied to dcmcavk capture register on a falling input signal edge 1 b timer contents are copied to capture register on a rising input signal edge oca 1rw trigger source for capture/compare register update 0 b capture/compare register dcmcovk is not affected. 1 b timer contents are copied to dcmcovk capture/compare register on the opposite edge selected by rcak. rze 2rw timer reset on rising edge 0 b timer is not affected 1 b timer is reset on a rising input signal edge fze 3rw timer reset on falling edge 0 b timer is not affected 1 b timer is reset on a falling input signal edge rck 4rw output pulse on rising edge 0 b dcm output line is not affected 1 b dcm output line is provided with a single clock pulse generated on a rising input signal edge www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-174 v1.1, 2011-03 gpta ? v5, v1.0 fck 5rw output pulse on falling edge 0 b dcm output line is not affected 1 b dcm output line is provided with a single clock pulse generated on a falling input signal edge qck 6w additional output pulse generation 0 b dcm output line is not affected 1 b dcm output line is immediately provided with a single clock pulse qck is always read as 0. rre 7rw interrupt request on rising edge 0 b interrupt request is not affected 1 b interrupt request is set on rising input signal edge fre 8rw interrupt request on falling edge 0 b interrupt request is not affected 1 b interrupt request is set on falling input signal edge cre 9rw interrupt request on compare event 0 b interrupt request is not affected 1 b interrupt request is set when the timer matches capture/compare register dcmcovk 0 [31:10] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-175 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_dcmtimk (k = 0-3) gpta0 duty cycle measurement timer register k (080 h +k*10 h +4 h ) reset value: 0000 0000 h gpta1_dcmtimk (k = 0-3) gpta1 duty cycle measurement timer register k (080 h +k*10 h +4 h ) reset value: 0000 0000 h 31 24 23 0 0tim rrwh field bits type description tim [23:0] rwh timer value of dcmk 0 [31:24] r reserved read as 0; should be written with 0. gpta0_dcmcavk (k = 0-3) gpta0 duty cycle measurement capture register k (088 h +k*10 h ) reset value: 0000 0000 h gpta1_dcmcavk (k = 0-3) gpta1 duty cycle measurement capture register k (088 h +k*10 h ) reset value: 0000 0000 h 31 24 23 0 0 cav rrwh field bits type description cav [23:0] rwh capture value of dcmk 0 [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-176 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_dcmcovk (k = 0-3) gpta0 duty cycle measurement capture/compare register k (08c h +k*10 h ) reset value: 0000 0000 h gpta1_dcmcovk (k = 0-3) gpta1 duty cycle measurement capture/compare register k (08c h +k*10 h ) reset value: 0000 0000 h 31 24 23 0 0cov rrwh field bits type description cov [23:0] rwh capture/compare register value of dcmk 0 [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-177 v1.1, 2011-03 gpta ? v5, v1.0 28.4.5 digital phase locked loop registers gpta0_pllctr gpta0 phase locked loop control register (0c0 h ) reset value: 0000 0000 h gpta1_pllctr gpta1 phase locked loop control register (0c0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ren pen aen mux r rw rwh rw rw field bits type description mux [1:0] rw trigger input channel selection 00 b dcm0 output is selected as pll input 01 b dcm1 output is selected as pll input 10 b dcm2 output is selected as pll input 11 b dcm3 output is selected as pll input aen 2rw automatic end mode enable with the automatic end mode compensation of input signal?s period length variation (acceleration, deceleration) is requested 0 b automatic end mode is disabled 1 b automatic end mode is enabled pen 3rwh unexpected period end behavior 0 b counter decrements with constant frequency 1 b counter is allowed to decrement with f gpta frequency in case of an input signal period length? reduction programming pen to 1 immediately changes the microtick counter to decrement with f gpta frequency. this bit is protected during read-modify-write operations (hardware will win). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-178 v1.1, 2011-03 gpta ? v5, v1.0 ren 4rw interrupt service request enable 0 b interrupt request is disabled 1 b an interrupt request is set when the number of remaining output pulses to be generated reaches zero 0 [31:5] r reserved read as 0; should be written with 0. gpta0_pllmti gpta0 phase locked loop microtick register (0c4 h ) reset value: 0000 0000 h gpta1_pllmti gpta1 phase locked loop microtick register (0c4 h ) reset value: 0000 0000 h 31 16 15 0 0mti rrw field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-179 v1.1, 2011-03 gpta ? v5, v1.0 field bits type description mti [15:0] rw microtick value number of output pulses to be generated within one input signal period. 0 [31:16] r reserved read as 0; should be written with 0. gpta0_pllstp gpta0 phase locked loop step register (0cc h ) reset value: 0000 0000 h gpta1_pllstp gpta1 phase locked loop step register (0cc h ) reset value: 0000 0000 h 31 16 15 0 0stp rrw field bits type description stp [15:0] rw step value number of output pulses to be generated within one input signal period (2-complement data format). 0 [31:16] r reserved read as 0; should be written with 0. gpta0_pllcnt gpta0 phase locked loop counter register (0c8 h ) reset value: 0000 0000 h gpta1_pllcnt gpta1 phase locked loop counter register (0c8 h ) reset value: 0000 0000 h 31 16 15 0 0 cnt rrwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-180 v1.1, 2011-03 gpta ? v5, v1.0 field bits type description cnt [15:0] rwh pulse counter counter for the number of remaining output pulses to be generated. 0 [31:16] r reserved read as 0; should be written with 0. gpta0_pllrev gpta0 phase locked loop reload register (0d0 h ) reset value: 0000 0000 h gpta1_pllrev gpta1 phase locked loop reload register (0d0 h ) reset value: 0000 0000 h 31 24 23 0 0rev rrw field bits type description rev [23:0] rw reload value reload value calculated by a subtraction of the number of output pulses to be generated within one input signal period from the input signal?s period length (measured in number of gpta ? v5 module clocks). 0 [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-181 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_plldtr gpta0 phase locked loop delta register (0d4 h ) reset value: 0000 0000 h gpta1_plldtr gpta1 phase locked loop delta register (0d4 h ) reset value: 0000 0000 h 31 25 24 0 0dtr rrwh field bits type description dtr [24:0] rwh delta register value internal register used to store intermediate results for output pulse generation. do not write to this register while pll is running! 0 [31:25] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-182 v1.1, 2011-03 gpta ? v5, v1.0 28.4.6 global timer registers gpta0_gtctrk (k = 0-1) gpta0 global timer control register k (0e0 h +k*10 h ) reset value: 0000 0000 h gpta1_gtctrk (k = 0-1) gpta1 global timer control register k (0e0 h +k*10 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0renmuxsco rrwrwrw field bits type description sco [3:0] rw tge flag source selection this bit field determines the bit of the operation result ?gtk timer value - data bus value? which is used as tge flag. 0000 b 10 th bit is used as tge flag. 0001 b 11 th bit is used as tge flag. ? b ? 1110 b 24 th bit is used as tge flag. 1111 b 25 th bit is used as tge flag. mux [6:4] rw timer clock selection one of eight available clock bus lines is selected as the timer gtk clock. 000 b clock bus line clk0 selected 001 b clock bus line clk1 selected 010 b clock bus line clk2 selected 011 b clock bus line clk3 selected 100 b clock bus line clk4 selected 101 b clock bus line clk5 selected 110 b clock bus line clk6 selected 111 b clock bus line clk7 selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-183 v1.1, 2011-03 gpta ? v5, v1.0 ren 7rw interrupt request enable 0 b the interrupt request is disabled 1 b an interrupt request is generated when timer gtk overflows 0 [31:8] r reserved read as 0; should be written with 0. gpta0_gttimk (k = 0-1) gpta0 global timer register k (0e8 h +k*10 h ) reset value: 0000 0000 h gpta1_gttimk (k = 0-1) gpta1 global timer register k (0e8 h +k*10 h ) reset value: 0000 0000 h 31 24 23 0 0tim rrwh field bits type description tim [23:0] rwh timer value of global timer k 0 [31:24] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-184 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_gtrevk (k = 0-1) gpta0 global timer reload value register k (0e4 h +k*10 h ) reset value: 0000 0000 h gpta1_gtrevk (k = 0-1) gpta1 global timer reload value register k (0e4 h +k*10 h ) reset value: 0000 0000 h 31 24 23 0 0rev rrwh field bits type description rev [23:0] rw reload value of global timer k reload value for timer gtk after an overflow 0 [31:24] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-185 v1.1, 2011-03 gpta ? v5, v1.0 28.4.7 clock bus register gpta0_ckbctr gpta0 clock bus control register (0d8 h ) reset value: 0000 ffff h gpta1_ckbctr gpta1 clock bus control register (0d8 h ) reset value: 0000 ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 dfaltc dfa03 rrwrw 1514131211109876543210 dfa07 dfa06 dfa04 dfa02 rw rw rw rw field bits type description dfa02 [3:0] rw clock line 2 driving source selection 0 d clk2 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa02 1 d clk2 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa02 ... 13 d clk2 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa02 14 d clk2 is driven by pll clock of other gpta ? v5 unit 15 d clk2 is driven by dcm3 output dfa04 [7:4] rw clock line 4 driving source selection 0 d clk4 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa04 1 d clk4 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa04 ... 14 d clk4 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa04 15 d clk4 is driven by dcm1 output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-186 v1.1, 2011-03 gpta ? v5, v1.0 dfa06 [11:8] rw clock line 6 driving source selection 0 d clk6 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa06 1 d clk6 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa06 ... 14 d clk6 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa06 15 d clk6 is driven by fpc1 output dfa07 [15:12] rw clock line 7 driving source selection 0 d clk7 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa07 1 d clk7 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa07 ... 14 d clk7 is provided with the gpta ? v5 module clock f gpta divided by 2 dfa07 15 d clk7 is driven by fpc4 output dfa03 [17:16] rw clock line 3 driving source selection 0 d clk3 is driven by dcm2 output 1 d clk3 is driven by pll clock of other gpta ? v5 unit 2 d clk3 is driven by uncompensated pll clock 3 d clk3 is driven by uncompensated pll clock of other gpta ? v5 unit dfaltc [20:18] rw dividing factor for ltc prescaler clock selection 0 d the ltcpre clock is provided with the gpta ? v5 module clock f gpta divided by 2 dfaltc . 1 d the ltcpre clock is provided with the gpta ? v5 module clock f gpta divided by 2 dfaltc . ... 7 d the ltcpre clock is provided with the gpta ? v5 module clock f gpta divided by 2 dfaltc . 0 [31:21] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-187 v1.1, 2011-03 gpta ? v5, v1.0 28.4.8 global timer cell registers gpta0_gtcctrk (k = 00-31) gpta0 global timer cell control register k [capture mode] (100 h +k*8 h ) reset value: 0000 0000 h gpta1_gtcctrk (k = 00-31) gpta1 global timer cell control register k [capture mode] (100 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 out oia ocm cen 0 eoa byp ne fed red ren osm mod rh rw rw rh r rwh rw rw rw rw rw rw rw field bits type description mod [1:0] rw mode control bits 00 b gtck operates in capture mode hooked to gt0. 01 b gtck operates in capture mode hooked to gt1. 10 b gtck operates in compare mode hooked to gt0. 11 b gtck operates in compare mode hooked to gt1. osm 2rw one shot mode enable 0 b gtck is continuously enabled. 1 b gtck is enabled for one event only. ren 3rw interrupt request enable 0 b service request is disabled. 1 b service request line sqsk is activated when a capture or compare event has occurred. red 4rw input rising edge select 0 b capture event is not triggered by a rising edge. 1 b capture event is triggered by a rising edge on the gtckin input line. fed 5rw input falling edge select 0 b capture event is not triggered by a falling edge. 1 b capture event is triggered by a falling edge on the gtckin input line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-188 v1.1, 2011-03 gpta ? v5, v1.0 ne 6rw not effective reserved byp 7rw bypass 0 b m0o/m1o lines are affected either by m0i/m1i lines or by ocm0/ocm1 bits. 1 b m0o/m1o lines are affected only by m0i/m1i lines. note: ocm2 must be set in any case to enable reaction on m0i/m1i changes. eoa 8rwh enable on action 0 b gtck is enabled for local events. 1 b gtck is disabled for local events. on an event on the communication link via m0i/m1i lines, eoa will be cleared and local events will be enabled. eoa is bit protected (see section 28.4.2 ). eoa is cleared if mode is switched to timer mode. cen 10 rh cell enable 0 b gtck is currently disabled for local events. 1 b gtck is currently enabled for local events. ocm [13:11] rw output control mode select 000 b current state of gtckout output line is hold 001 b current state of gtckout output line is toggled by an internal gtck event otherwise hold 010 b gtckout output line is forced to 0 by an internal gtck event otherwise hold 011 b gtckout output line is forced to 1 by an internal gtck event otherwise hold 1xx b gtckout output line state is affected by an internal gtck event and/or by an operation occurred in an adjacent gtcn (n = less or equal k) and reported by the m1i, m0i interface lines. oia 14 rw output immediate action 0 b no immediate action required. 1 b action defined by ocm must be performed immediately. reading bit oia always returns 0. out 15 rh output state 0 b gtckout output line is 0. 1 b gtckout output line is 1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-189 v1.1, 2011-03 gpta ? v5, v1.0 0 9, [31:16] r reserved read as 0; should be written with 0. gpta0_gtcctrk (k = 00-31) gpta0 global timer cell control register k [compare mode] (100 h +k*8 h ) reset value: 0000 0000 h gpta1_gtcctrk (k = 00-31) gpta1 global timer cell control register k [compare mode] (100 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 out oia ocm cen 0 eoa byp cat cac ges ren osm mod rh rw rw rh r rwh rw rw rw rw rw rw rw field bits type description mod [1:0] rw mode control bits 00 b gtck operates in capture mode hooked to gt0. 01 b gtck operates in capture mode hooked to gt1. 10 b gtck operates in compare mode hooked to gt0. 11 b gtck operates in compare mode hooked to gt1. osm 2rw one shot mode enable 0 b gtck is continuously enabled. 1 b gtck is enabled for one event only. ren 3rw interrupt request enable 0 b service request is disabled. 1 b service request line sqsk is activated when a capture or compare event has occurred. ges 4rw greater equal select 0 b an ?equal? compare is selected. 1 b a ?greater equal? compare is required. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-190 v1.1, 2011-03 gpta ? v5, v1.0 cac 5rw capture after compare select 0 b capture after compare is disabled. 1 b after a compare event, the contents of the associated global timer as selected by mod or (depending on control bit cat) the contents of the alternate global timer are copied to the capture/compare register gtcxrk. cat 6rw capture alternate timer 0 b the global timer as selected by mod is captured, if enabled by control bit cac = 1. 1 b the alternate global timer is captured. byp 7rw bypass 0 b m1o/m0o lines are affected either by m1i/m0i lines or by ocm1/ocm0 bits. 1 b m0o/m1o lines are affected only by m0i/m1i lines. note: ocm2 must be set in any case to enable reaction on m0i/m1i changes. eoa 8rwh enable on action 0 b gtck is enabled for local events. 1 b gtck is disabled for local events. on an event on the communication link via m0i/m1i lines, eoa will be cleared and local events will be enabled. eoa is bit protected (see section 28.4.2 ). eoa is cleared if mode is switched to timer mode. cen 10 rh cell enable 0 b gtck is currently disabled for local events. 1 b gtck is currently enabled for local events. ocm [13:11] rw output control mode select 000 b current state of gtckout output line is hold 001 b current state of gtckout output line is toggled by an internal gtck event otherwise hold 010 b gtckout output line is forced to 0 by an internal gtck event otherwise hold 011 b gtckout output line is forced to 1 by an internal gtck event otherwise hold 1xx b gtckout output line state is affected by an internal gtck event and/or by an operation occurred in an adjacent gtcn (n = less or equal k) and reported by the m1i, m0i interface lines. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-191 v1.1, 2011-03 gpta ? v5, v1.0 note: gtcxrk is write-protected when contro l bits cac and osm are set to 1 (?capture after compare? in single shot mode). writ e protection is activated, when the value of the selected gt timer matches and/o r exceeds the capture/compare register contents. write protection is released af ter a software access to register gtcxrk. oia 14 rw output immediate action 0 b no immediate action required. 1 b action defined by ocm must be performed immediately. reading bit oia always returns 0. out 15 rh output state 0 b gtckout output line is 0. 1 b gtckout output line is 1. 0 9, [31:16] r reserved read as 0; should be written with 0. gpta0_gtcxrk (k = 00-31) gpta0 global timer cell x register k (104 h +k*8 h ) reset value: 0000 0000 h gpta1_gtcxrk (k = 00-31) gpta1 global timer cell x register k (104 h +k*8 h ) reset value: 0000 0000 h 31 24 23 0 0x rrwh field bits type description x [23:0] rwh capture/compare register contents of gtck 0 [31:24] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-192 v1.1, 2011-03 gpta ? v5, v1.0 28.4.9 local timer cell registers gpta0_ltcctrk (k = 00-62) gpta0 local timer cell control register k [timer mode ilm=0] (200 h +k*8 h ) reset value: 0000 0000 h gpta1_ltcctrk (k = 00-62) gpta1 local timer cell control register k [timer mode ilm=0] (200 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 g byp rrw 1514131211109876543210 out oia ocm cen cud ilm cud clr slo fed red ren osm mod rh rw rw rh rwh rw w rwh rw rw rw rw rw field bits type description mod [1:0] rw mode control bits 00 b ltck operates in capture mode. 01 b ltck operates in compare mode. 10 b ltck operates in free-running timer mode. 11 b ltck operates in reset timer mode. osm 2rw one shot mode enable 0 b ltck is continuously enabled. 1 b ltck is enabled for one event only. ren 3rw request enable 0 b service request is disabled. 1 b service request sqsk is activated when a - capture event has occurred - compare event has occurred - timer overflow has happened depending on the operation mode selected by bit field mod. red 4rw input rising edge select 0 b timer is not updated by a rising edge. 1 b timer is updated by a rising edge on the ltckin input line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-193 v1.1, 2011-03 gpta ? v5, v1.0 fed 5rw input falling edge select 0 b timer is not updated by a falling edge. 1 b timer is updated by a falling edge on the ltckin input line. slo 6rwh select line output 0 b state of select line output so is 0. 1 b state of select line output so is 1. slo is bit protected (see page 28-167 ). cudclr 7w coherent update disable 0 b no effect. 1 b coherent update disabled (bit cud is cleared). if bits cud and cudclr are both written with 1, bit cud will be set. cudclr is always read as 0. ilm 8rw input line mode 0 b input line is operating in edge sensitive mode. 1 b input line is operating in level sensitive mode. in case of full speed gpta ? v5 module clock selection as input clock, level sensitive mode must be selected. in this case the edge sensitive mode will not produce any event. cud 9rwh coherent update enable 0 b select output so is not toggled on timer reset overflow. 1 b select output so is toggled on next timer reset overflow. when cud is set by software, it remains set until the next timer reset overflow (ltck reset event) occurs and is cleared by hardware afterwards. cud can be reset by software by writing bit cudclr with 1 and cud with 0. cud is automatically cleared after ltck reset event and when mode is switched to another mode than reset timer mode. this bit can only be set in reset timer mode. if bits cud and cudclr are both written with 1, bit cud will be set. cudclr is always read as 0. cen 10 rh cell enable 0 b ltck is currently disabled for local events. 1 b ltck is currently enabled for local events. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-194 v1.1, 2011-03 gpta ? v5, v1.0 ocm [13:11] rw output control mode select 000 b current state of ltckout output line is hold 001 b current state of ltckout output line is toggled by an internal ltck event otherwise hold 010 b ltckout output line is forced to 0 by an internal ltck event otherwise hold 011 b ltckout output line is forced to 1 by an internal ltck event otherwise hold 1xx b ltckout output line state is affected by an internal ltck event and/or by an operation occurred in an adjacent ltck cell (reported by m1i/m0i interface lines). oia 14 rw output immediate action 0 b no immediate action required. 1 b action defined by bit field ocm must be performed immediately. oia is always read as 0. out 15 rh output state 0 b ltckout output line is 0. 1 b ltckout output line is 1. gbyp 16 rw global bypass 0 b m3o/m2o lines are affected by m1i/m0i lines. 1 b m3o/m2o lines are affected by m3i/m2i lines. 0 [31:17] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-195 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_ltcctrk (k = 00-62) gpta0 local timer cell control register k [timer mode ilm=1] (200 h +k*8 h ) reset value: 0000 0000 h gpta1_ltcctrk (k = 00-62) gpta1 local timer cell control register k [timer mode ilm=1] (200 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 g byp rrw 1514131211109876543210 out oia ocm cen cud ilm cud clr slo ail pen ren osm mod rh rw rw rh rwh rw w rwh rw rw rw rw rw field bits type description mod [1:0] rw mode control bits 00 b ltck operates in capture mode. 01 b ltck operates in compare mode. 10 b ltck operates in free-running timer mode. 11 b ltck operates in reset timer mode. osm 2rw one shot mode enable 0 b ltck is continuously enabled. 1 b ltck is enabled for one event only. ren 3rw request enable 0 b service request is disabled. 1 b service request sqsk is activated when a - capture event has occurred - compare event has occurred - timer overflow has happened depending on the operation mode selected by bit field mod. pen 4rw ltc prescaler enable 0 b ltc prescaler mode is disabled. 1 b ltc prescaler mode with ltc prescaler clock ltcpre is enabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-196 v1.1, 2011-03 gpta ? v5, v1.0 ail 5rw active input level select 0 b input signal is active high. 1 b input signal is active low. slo 6rwh select line output 0 b state of select line output so is 0. 1 b state of select line output so is 1. slo is bit protected (see page 28-167 ). cudclr 7w coherent update disable 0 b no effect. 1 b coherent update disabled (bit cud is cleared). if bits cud and cudclr are both written with 1, bit cud will be set. cudclr is always read as 0. ilm 8rw input line mode 0 b input line is operating in edge sensitive mode. 1 b input line is operating in level sensitive mode. in case of full speed gpta ? v5 module clock selection as input clock, level sensitive mode must be selected. in this case the edge sensitive mode will not produce any event. cud 9rwh coherent update enable 0 b select output so is not toggled on timer reset overflow. 1 b select output so is toggled on next timer reset overflow. when cud is set by software, it remains set until the next timer reset overflow (ltck reset event) occurs and is cleared by hardware afterwards. cud can be reset by software by writing bit cudclr with 1 and cud with 0. cud is automatically cleared after ltck reset event and when mode is switched to another mode than reset timer mode. this bit can only be set in reset timer mode. if bits cud and cudclr are both written with 1, bit cud will be set. cudclr is always read as 0. cen 10 rh cell enable 0 b ltck is currently disabled for local events. 1 b ltck is currently enabled for local events. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-197 v1.1, 2011-03 gpta ? v5, v1.0 ocm [13:11] rw output control mode select 000 b current state of ltckout output line is hold 001 b current state of ltckout output line is toggled by an internal ltck event otherwise hold 010 b ltckout output line is forced to 0 by an internal ltck event otherwise hold 011 b ltckout output line is forced to 1 by an internal ltck event otherwise hold 1xx b ltckout output line state is affected by an internal ltck event and/or by an operation occurred in an adjacent ltck cell (reported by m1i/m0i interface lines). oia 14 rw output immediate action 0 b no immediate action required. 1 b action defined by bit field ocm must be performed immediately. oia is always read as 0. out 15 rh output state 0 b ltckout output line is 0. 1 b ltckout output line is 1. gbyp 16 rw global bypass 0 b m3o/m2o lines are affected by m1i/m0i lines. 1 b m3o/m2o lines are affected by m3i/m2i lines. 0 [31:17] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-198 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_ltcctrk (k = 00-62) gpta0 local timer cell control register k [capture mode] (200 h +k*8 h ) reset value: 0000 0000 h gpta1_ltcctrk (k = 00-62) gpta1 local timer cell control register k [capture mode] (200 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 g byp rrw 1514131211109876543210 out oia ocm cen sll ilm eoa byp fed red ren osm mod rh rw rw rh rh rw rwh rw rw rw rw rw rw field bits type description mod [1:0] rw mode control bits 00 b ltck operates in capture mode. 01 b ltck operates in compare mode. 10 b ltck operates in free-running timer mode. 11 b ltck operates in reset timer mode. osm 2rw one shot mode enable 0 b ltck is continuously enabled. 1 b ltck is enabled for one event only. ren 3rw request enable 0 b service request is disabled. 1 b service request sqsk is activated when a - capture event has occurred - compare event has occurred - timer overflow has happened depending on the operation mode selected by bit field mod. red 4rw input rising edge select 0 b capture event is not triggered by a rising edge. 1 b capture event is triggered by a rising edge on the ltckin input line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-199 v1.1, 2011-03 gpta ? v5, v1.0 fed 5rw input falling edge select 0 b capture event is not triggered by a falling edge. 1 b capture event is triggered by a falling edge on the ltckin input line. byp 6rw local bypass 0 b m1o/m0o lines are affected either by m1i/m0i lines or by ocm1/ocm0 bits. 1 b m1o/m0o lines are affected only by m1i/m0i (gbyp = 0) or m2i/m2i (gbyp = 1) lines. this bit is cleared if mode is switched to timer mode. ocm2 must be set in any case to enable reaction on m1i/m0i change. eoa 7rwh enable on action 0 b ltck is enabled for local events. 1 b ltck is disabled for local events. on an event on the communication link via m0i/m1i lines, eoa will be cleared and local events will be enabled. eoa is bit protected (see section 28.4.2 ). eoa is cleared if mode is switched to timer mode. ilm 8rw input line mode 0 b input line is operating in edge sensitive mode. 1 b input line is operating in level sensitive mode. in case of full speed gpta ? v5 module clock selection as input clock, level sensitive mode must be selected. in this case the edge sensitive mode will not produce any event. sll 9rh capture & compare mode: select line level 0 b current state of select input si is 0. 1 b current state of select input si is 1. cen 10 rh cell enable 0 b ltck is currently disabled for local events. 1 b ltck is currently enabled for local events. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-200 v1.1, 2011-03 gpta ? v5, v1.0 ocm [13:11] rw output control mode select 000 b current state of ltckout output line is hold 001 b current state of ltckout output line is toggled by an internal ltck event otherwise hold 010 b ltckout output line is forced to 0 by an internal ltck event otherwise hold 011 b ltckout output line is forced to 1 by an internal ltck event otherwise hold 1xx b ltckout output line state is affected by an internal ltck event and/or by an operation occurred in an adjacent ltck cell (reported by m1i/m0i interface lines). oia 14 rw output immediate action 0 b no immediate action required. 1 b action defined by bit field ocm must be performed immediately. oia is always read as 0. out 15 rh output state 0 b ltckout output line is 0. 1 b ltckout output line is 1. gbyp 16 rw global bypass 0 b m3o/m2o lines are affected by m1i/m0i lines. 1 b m3o/m2o lines are affected by m3i/m2i lines. 0 [31:17] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-201 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_ltcctrk (k = 00-62) gpta0 local timer cell control register k [compare mode] (200 h +k*8 h ) reset value: 0000 0000 h gpta1_ltcctrk (k = 00-62) gpta1 local timer cell control register k [compare mode] (200 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 g byp rrw 1514131211109876543210 out oia ocm cen sll ilm eoa byp soh sol ren osm mod rh rw rw rh rh rw rwh rw rw rw rw rw rw field bits type description mod [1:0] rw mode control bits 00 b ltck operates in capture mode. 01 b ltck operates in compare mode. 10 b ltck operates in free-running timer mode. 11 b ltck operates in reset timer mode. osm 2rw one shot mode enable 0 b ltck is continuously enabled. 1 b ltck is enabled for one event only. ren 3rw request enable 0 b service request is disabled. 1 b service request sqsk is activated when a - capture event has occurred - compare event has occurred - timer overflow has happened depending on the operation mode selected by bit field mod. sol 4rw compare mode: select output low 0 b compare is deactivated or on high level. 1 b compare operation is enabled by a low level on select input si 1) . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-202 v1.1, 2011-03 gpta ? v5, v1.0 soh 5rw compare mode: select output high 0 b compare is deactivated or on high level. 1 b compare operation is enabled by a high level on select input si 1) . byp 6rw bypass 0 b m1o/m0o lines are affected either by m1i/m0i lines or by ocm1/ocm0 bits. 1 b m1o/m0o lines are affected only by m1i/m0i lines. this bit is cleared if mode is switched to timer mode. ocm2 must be set in any case to enable reaction on m1i/m0i change. eoa 7rwh enable on action 0 b ltck is enabled for local events. 1 b ltck is disabled for local events. on an event on the communication link via m0i/m1i lines, eoa will be cleared and local events will be enabled. eoa is bit protected (see section 28.4.2 ). eoa is cleared if mode is switched to timer mode. ilm 8rw input line mode 0 b input line is operating in edge sensitive mode. 1 b input line is operating in level sensitive mode. in case of full speed gpta ? v5 module clock selection as input clock, level sensitive mode must be selected. in this case the edge sensitive mode will not produce any event. sll 9rh select line level 0 b current state of select input si is 0. 1 b current state of select input si is 1. cen 10 rh cell enable 0 b ltck is currently disabled for local events. 1 b ltck is currently enabled for local events. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-203 v1.1, 2011-03 gpta ? v5, v1.0 ocm [13:11] rw output control mode select 000 b current state of ltckout output line is hold 001 b current state of ltckout output line is toggled by an internal ltck event otherwise hold 010 b ltckout output line is forced to 0 by an internal ltck event otherwise hold 011 b ltckout output line is forced to 1 by an internal ltck event otherwise hold 1xx b ltckout output line state is affected by an internal ltck event and/or by an operation occurred in an adjacent ltck cell (reported by m1i/m0i interface lines). oia 14 rw output immediate action 0 b no immediate action required. 1 b action defined by bit field ocm must be performed immediately. oia is always read as 0. out 15 rh output state 0 b ltckout output line is 0. 1 b ltckout output line is 1. gbyp 16 rw global bypass 0 b m3o/m2o lines are affected by m1i/m0i lines. 1 b m3o/m2o lines are affected by m3i/m2i lines. 0 [31:17] r reserved read as 0; should be written with 0. 1) to enable compare mode in all cases, sol and soh bits must be set to 1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-204 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_ltcctr63 gpta0 local timer cell control register 63(3f8 h ) reset value: 0000 0000 h gpta1_ltcctr63 gpta1 local timer cell control register 63(3f8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 out 0 cen 0 ilm 0 fed red ren osm brm rh r rhrrw r rwrwrwrwrw field bits type description brm 0rw bit reversal mode control 0 b compare uses normal sequence of local input data bus (yi) bits. 1 b compare uses reversed sequence of local input data bus (yi) bits. osm 1rw one shot mode enable for shadow register copy 0 b shadow register copy is continuously enabled. 1 b shadow register copy is enabled for one event only. ren [3:2] rw request enable 00 b service request sqt63 is disabled. 01 b service request sqt63 is generated when a compare event has occurred. 10 b service request sqt63 is generated when a shadow register copy event has occurred. 11 b reserved. red 4rw rising edge select fo r shadow register copy 0 b shadow register copy is not triggered by a rising edge on the ltc63in input line. 1 b shadow register copy is triggered by a rising edge on the ltc63in input line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-205 v1.1, 2011-03 gpta ? v5, v1.0 fed 5rw falling edge select for shadow register copy 0 b shadow register copy is not triggered by a falling edge on the ltc63in input line. 1 b shadow register copy is triggered by a falling edge on the ltc63in input line. ilm 8rw shadow register copy input line mode 0 b ltc63in is operating in edge sensitive mode. 1 b ltc63in is operating in level sensitive mode. cen 10 rh enable for shadow register copy 0 b shadow register copy is currently disabled. 1 b shadow register copy is currently enabled. out 15 rh output state 0 b ltc63out output line is 0. 1 b ltc63out output line is 1. 0 [7:6], 9, [14:11], [31:16] r reserved read as 0; should be written with 0. gpta0_ltcxrk (k = 00-62) gpta0 local timer cell x register k(204 h +k*8 h ) reset value: 0000 0000 h gpta1_ltcxrk (k = 00-62) gpta1 local timer cell x register k(204 h +k*8 h ) reset value: 0000 0000 h 31 16 15 0 0x rrwh field bits type description x [15:0] rwh local timer data register value 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-206 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_ltcxr63 gpta0 local timer cell x register 63(3fc h ) reset value: 0000 0000 h gpta1_ltcxr63 gpta1 local timer cell x register 63(3fc h ) reset value: 0000 0000 h 31 16 15 0 xs x rw rwh field bits type description x [15:0] rwh compare register value software write operations has priority above a simultaneous hardware update. xs [31:16] rw shadow register value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-207 v1.1, 2011-03 gpta ? v5, v1.0 28.4.10 multiplexer control registers these registers are not directly accessible and can be written and read only via the multiplexer register array fifo (see page 28-121 ). i/o sharing block registers the three registers mractl, mradin, and mradout are used to write data to and read data from the gtca multiplexer register array fifo. the multiplexer register array fifo controls the operation of the input/output line sharing block (see ?input/output line sharing block (iols)? on page 28-235 ). the multiplexer register array control register controls the operation of the multiplexer register array fifo. gpta0_mractl gpta0 multiplexer register array control register (038 h ) reset value: 0000 0000 h gpta1_mractl gpta1 multiplexer register array control register (038 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fifofillcnt 0 fifo ful l wcr es ma en rr r rwrw field bits type description maen 0rw multiplexer array enable bit field maen enables/disables the programming and the interconnections of the multiplexer array. 0 b multiplexer array is disabled; all cell inputs are driven with 0, gpta ? v5 i/o lines (pins) are disconnected and fifo writing is enabled. 1 b multiplexer array is enabled; all cell and i/o line interconnections are established as previously programmed and fifo writing is disabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-208 v1.1, 2011-03 gpta ? v5, v1.0 the multiplexer register array data in register is used to write data to the multiplexer register array fifo. the multiplexer register array data out register is used to read data from the multiplexer register array fifo. wcres 1w write count reset writing wcres with 1 while the array is disabled (maen = 0), resets the write cycle counter to zero and the fifo written sequentially (initialized). wcres is always read as 0. fifofull 2r fifo full status 0 b fifo not completely written (write access to mradin allowed). 1 b fifo completely written (w rite access to mradin ignored). must be re-enabled via wcres before array can be re-initialized. fifofillcnt [13:8] r fifo fill count this bit field shows the current contents of the write cycle counter. 0 [7:3], [31:14] r reserved read as 0; should be written with 0. gpta0_mradin gpta0 multiplexer register array data in register (03c h ) reset value: 0000 0000 h gpta1_mradin gpta1 multiplexer register array data in register (03c h ) reset value: 0000 0000 h 31 0 datain w field bits type description datain [31:0] w fifo write data this register contains the fifo write data as defined for the output multiplexer control registers and the input multiplexer control registers. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-209 v1.1, 2011-03 gpta ? v5, v1.0 note: for correct operation, the mradin and mradin registers must be always read or written 32-bit wide. 8-bit and 16-bit accesses are ignored without any bus error! gpta0_mradout gpta0 multiplexer register array data out register (040 h ) reset value: 0000 0000 h gpta1_mradout gpta1 multiplexer register array data out register (040 h ) reset value: 0000 0000 h 31 0 dataout rh field bits type description dataout [31:0] rh fifo read data this register contains the fifo read data as assigned for the output multiplexer control registers and the input multiplexer control registers. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-210 v1.1, 2011-03 gpta ? v5, v1.0 output multiplexer control registers two registers, omcrl and omcrh, are assigned to each i/o group iog[6:0] and each output group og[6:0]. omcrl[6:0]/omcrh[6:0] are assigned to iog[6:0] and omcrl[13:7]/omcrh[13:7] are assigned to og[6:0]. omcrl controls the connections of group pins 0 to 3. omcrh controls the connections of group pins 4 to 7. gpta0_omcrlg (g = 0-13) gpta0 output multiplexer control register for lower half of group g reset value: 0000 0000 h gpta1_omcrlg (g = 0-13) gpta1 output multiplexer control register for lower half of group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0omg30oml30omg20oml2 rrwrrwrrwrrw 1514131211109876543210 0omg10oml10omg00oml0 rrwrrwrrwrrw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-211 v1.1, 2011-03 gpta ? v5, v1.0 field bits type description oml0, oml1, oml2, oml3 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a omg that can be selected by bit field omgn for omg output n. 000 b omg input in0 selected 001 b omg input in1 selected 010 b omg input in2 selected 011 b omg input in3 selected 100 b omg input in4 selected 101 b omg input in5 selected 110 b omg input in6 selected 111 b omg input in7 selected omg0, omg1, omg2, omg3 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the omgng which is connected to input n of i/o group g or output group g-7. x00 b omg0g selected x01 b omg1g selected x10 b omg2g selected all other combinations are reserved. if a reserved combination of omgn value is selected, the corresponding omg output is forced to 0 level. for comp atibility reasons, omgn[2] = 0 should be used (as value for x) for omgn bit field programming. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-212 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_omcrhg (g = 0-13) output multiplexer control register for upper half of pin group g reset value: 0000 0000 h gpta1_omcrhg (g = 0-13) output multiplexer control register for upper half of pin group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0omg70oml70omg60oml6 rrwrrwrrwrrw 1514131211109876543210 0omg50oml50omg40oml4 rrwrrwrrwrrw field bits type description oml4, oml5, oml6, oml7 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a omg that can be selected by bit field omgn for omg output n. 000 b omg input in0 selected 001 b omg input in1 selected 010 b omg input in2 selected 011 b omg input in3 selected 100 b omg input in4 selected 101 b omg input in5 selected 110 b omg input in6 selected 111 b omg input in7 selected omg4, omg5, omg6, omg7 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the omgng which is connected to input n of i/o group g or output group g-7. x00 b omg0g selected x01 b omg1g selected x10 b omg2g selected all other combinations are reserved. if a reserved combination of omgn value is selected, the corresponding omg output is forced to 0 level. for comp atibility reasons, omgn[2] = 0 should be used (as value for x) for omgn bit field programming. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-213 v1.1, 2011-03 gpta ? v5, v1.0 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-214 v1.1, 2011-03 gpta ? v5, v1.0 on-chip trigger and gating signal multiplexer control registers otmcr controls the connections of i/o outpu t group signals to the trigger and gating signals triggn gpta0_otmcrg (g = 0-1) gpta0 on-chip trigger and gating multiplexer control register of group g reset value: 0000 0000 h gpta1_otmcrg (g = 0-1) gpta1 on-chip trigger and gating multiplexer control register of group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0otm70otm60otm50otm4 rrwrrwrrwrrw 1514131211109876543210 0otm30otm20otm10otm0 rrwrrwrrwrrw field bits type description otmn, (n=0...7) [4 x (n + 4):4 x n] rw multiplexer line selection this bit field selects the input line of a omg that can be selected by bit field omgn for omg output n. 000 b otmg input in0 selected 001 b otmg input in1 selected 010 b otmg input in2 selected 011 b otmg input in3 selected 100 b otmg input in4 selected 101 b otmg input in5 selected 110 b otmg input in6 selected 111 b otmg input in7 selected 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-215 v1.1, 2011-03 gpta ? v5, v1.0 gtc input multiplexer control registers two registers, gimcrl and gimcrh, ar e assigned to each gtcg[3:0]. gimcrl controls the connections of cells 0 to 3 in a gtc group. gimcrh controls the connections of cells 4 to 7 in a gtc group. note: these registers are not directly acce ssible and can be written and read only via the multiplexer regist er array fifo (see section 28.3.4.6 ). gpta0_gimcrlg (g = 0-3) gpta0 input multiplexer control register for lower half of gtc group g reset value: 0000 0000 h gpta1_gimcrlg (g = 0-3) gpta1 input multiplexer control register for lower half of gtc group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gim en3 gimg3 0 giml3 gim en2 gimg2 0 giml2 rrwrrwrrwrrw 1514131211109876543210 gim en1 gimg1 0 giml1 gim en0 gimg0 0 giml0 rw rw r rw rw rw r rw field bits type description giml0, giml1, giml2, giml3 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a gimg that can be selected by bit field gimgn for gimg output n. 000 b gimg input in0 selected 001 b gimg input in1 selected 010 b gimg input in2 selected 011 b gimg input in3 selected 100 b gimg input in4 selected 101 b gimg input in5 selected 110 b gimg input in6 selected 111 b gimg input in7 selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-216 v1.1, 2011-03 gpta ? v5, v1.0 gimg0, gimg1, gimg2, gimg3 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the gimgng which is connected to input n of gtc group g. 000 b gimg0g selected 001 b gimg1g selected (reserved for g = 3) 010 b gimg2g selected 011 b gimg3g selected 100 b gimg4g selected all other combinations are reserved. gimen0, gimen1, gimen2, gimen3 7, 15, 23, 31 rw enable multiplexer connection 0 b input n is not connected to any line. 1 b input n is connected to the line defined by gimln and gimgn. 0 3, 11, 19, 27 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-217 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_gimcrhg (g = 0-3) gpta0 input multiplexer control register for upper half of gtc group g reset value: 0000 0000 h gpta1_gimcrhg (g = 0-3) gpta1 input multiplexer control register for upper half of gtc group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gim en7 gimg7 0 giml7 gim en6 gimg6 0 giml6 rrwrrwrrwrrw 1514131211109876543210 gim en5 gimg5 0 giml5 gim en4 gimg4 0 giml4 rrwrrwrrwrrw field bits type description giml4, giml5, giml6, giml7 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a gimg that can be selected by bit field gimgn for gimg output n. 000 b gimg input in0 selected 001 b gimg input in1 selected 010 b gimg input in2 selected 011 b gimg input in3 selected 100 b gimg input in4 selected 101 b gimg input in5 selected 110 b gimg input in6 selected 111 b gimg input in7 selected gimg4, gimg5, gimg6, gimg7 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the gimgng which is connected to input n of gtc group g. 000 b gimg0g selected 001 b gimg1g selected (reserved for g = 3) 010 b gimg2g selected 011 b gimg3g selected 100 b gimg4g selected all other combinations are reserved. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-218 v1.1, 2011-03 gpta ? v5, v1.0 gimen4, gimen5, gimen6, gimen7 7, 15, 23, 31 rw enable multiplexer connection 0 b input n is not connected to any line. 1 b input n is connected to the line defined by gimln and gimgn. 0 3, 11, 19, 27 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-219 v1.1, 2011-03 gpta ? v5, v1.0 ltc input multiplexer control registers two registers, limcrl and limcrh, are assigned to each ltc group. limcrl controls the connections of ltc group cells with index 0 to 3. limcrh controls the connections of ltc group cells with index 4 to 7. note: these registers are not directly acce ssible and can be written and read only via the multiplexer regist er array fifo (see section 28.3.4.6 ). gpta0_limcrlg (g = 0-7) gpta0 input multiplexer control register for lower half of ltc group g reset value: 0000 0000 h gpta1_limcrlg (g = 0-7) gpta1 input multiplexer control register for lower half of ltc group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lim en3 limg3 0 liml3 lim en2 limg2 0 liml2 rrwrrwrrwrrw 1514131211109876543210 lim en1 limg1 0 liml1 lim en0 limg0 0 liml0 rrwrrwrrwrrw field bits type description liml0, liml1, liml2, liml3 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a limg that can be selected by bit field limgn for limg output n. 000 b limg input in0 selected 001 b limg input in1 selected 010 b limg input in2 selected 011 b limg input in3 selected 100 b limg input in4 selected 101 b limg input in5 selected 110 b limg input in6 selected 111 b limg input in7 selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-220 v1.1, 2011-03 gpta ? v5, v1.0 limg0, limg1, limg2, limg3 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the limgng which is connected to input n of ltc group g. 000 b limg0g selected 001 b limg1g selected (reserved for g = 3) 010 b limg2g selected 011 b limg3g selected 100 b limg4g selected all other combinations are reserved. limen0, limen1, limen2, limen3 7, 15, 23, 31 rw enable multiplexer connection 0 b input n is not connected to any line. 1 b input n is connected to the line defined by limln and limgn. 0 3, 11, 19, 27 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-221 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_limcrhg (g = 0-7) gpta0 input multiplexer control register for upper half of ltc group g reset value: 0000 0000 h gpta1_limcrhg (g = 0-7) gpta1 input multiplexer control register for upper half of ltc group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lim en7 limg7 0 liml7 lim en6 limg6 0 liml6 rrwrrwrrwrrw 1514131211109876543210 lim en5 limg5 0 liml5 lim en4 limg4 0 liml4 rrwrrwrrwrrw field bits type description liml4, liml5, liml6, liml7 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a limg that can be selected by bit field limgn for limg output n. 000 b limg input in0 selected 001 b limg input in1 selected 010 b limg input in2 selected 011 b limg input in3 selected 100 b limg input in4 selected 101 b limg input in5 selected 110 b limg input in6 selected 111 b limg input in7 selected limg4, limg5, limg6, limg7 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the limgng which is connected to input n of ltc group g. 000 b limg0g selected 001 b limg1g selected (reserved for g = 3) 010 b limg2g selected 011 b limg3g selected 100 b limg4g selected all other combinations are reserved. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-222 v1.1, 2011-03 gpta ? v5, v1.0 limen4, limen5, limen6, limen7 7, 15, 23, 31 rw enable multiplexer connection 0 b input n is not connected to any line. 1 b input n is connected to the line defined by limln and limgn. 0 3, 11, 19, 27 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-223 v1.1, 2011-03 gpta ? v5, v1.0 28.4.11 service request registers the bits in the service request state register s are service request status flags that are set by hardware (type ?h?) when the related event occurs, regardless if a respective interrupt request is enabled. each service request status flag can be read twice (in srscx register and in srssx register, x = 0-3) and cleared or set by software when writing to the specific request bit in srsc x or srssx. if enabled, a interrupt request is generated regardless of the content of the srssx or srscx registers. the service request status flags can be rese t (cleared) by software when writing a 1 to the corresponding bit location in the srscx registers. writing a 0 has no effect. the service request status flags can be se t by software when writing a 1 to the corresponding bit location in the srssx registers. writing a 0 has no effect. gpta0_srsc0 gpta0 service request state clear register 0 (010 h ) reset value: 0000 0000 h gpta1_srsc0 gpta1 service request state clear register 0 (010 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 gt 01 gt 00 pll dcm 03c dcm 03f dcm 03r dcm 02c dcm 02f dcm 02r dcm 01c dcm 01f dcm 01r dcm 00c dcm 00f dcm 00r r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description dcm00r, dcm01r, dcm02r, dcm03r 0, 3, 6, 9 rwh 1) dcmk 2) rising edge event service request state 0 b no service is requested. 1 b service is requested due to a rising edge detected on the dcmk input signal line. dcm00f, dcm01f, dcm02f, dcm03f 1, 4, 7, 10 rwh 1) dcmk 2) falling edge event service request state 0 b no service is requested. 1 b service is requested due to a falling edge detected on the dcmk input signal line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-224 v1.1, 2011-03 gpta ? v5, v1.0 dcm00c, dcm01c, dcm02c, dcm03c 2, 5, 8, 11 rwh 1) dcmk 2) compare event service request state 0 b no service is requested. 1 b service is requested due to a compare event occurred in dcmk cell (k = 0-3). pll 12 rwh 1) counter service requ est state for pll 0 b no service is requested. 1 b service is requested because the counter for the number remaining output pulses decremented to 0. gt00 13 rwh 1) gt0 timer service request state 0 b no service is requested. 1 b service is requested due to a gt0 timer overflow. gt01 14 rwh 1) gt1 timer service request state 0 b no service is requested. 1 b service is requested due to a gt1 timer overflow. 0 [31:15] r reserved read as 0; should be written with 0. 1) writing an one to a set bit clears the bit. all other write operations have no effect. 2) k = 0-3; k = 0 refers to dcm00r, dcm00f, or dcm00c; k = 1 refers to dcm01r, dcm01f, or dcm01c; k = 2 refers to dcm02r, dcm02f, or dcm02c; k = 3 refers to dcm03r, dcm03f, or dcm03c. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-225 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_srss0 gpta0 service request state set register 0 (014 h ) reset value: 0000 0000 h gpta1_srss0 gpta1 service request state set register 0 (014 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 gt 01 gt 00 pll dcm 03c dcm 03f dcm 03r dcm 02c dcm 02f dcm 02r dcm 01c dcm 01f dcm 01r dcm 00c dcm 00f dcm 00r r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description dcm00r, dcm01r, dcm02r, dcm03r 0, 3, 6, 9 rwh 1) dcmk 2) rising edge event service request state 0 b no service is requested. 1 b service is requested due to a rising edge detected on dcmk input signal line. dcm00f, dcm01f, dcm02f, dcm03f 1, 4, 7, 10 rwh 1) dcmk 2) falling edge event service request state 0 b no service is requested. 1 b service is requested due to a falling edge detected on dcmk input signal line. dcm00c, dcm01c, dcm02c, dcm03c 2, 5, 8, 11 rwh 1) dcmk 2) compare event service request state 0 b no service is requested. 1 b service is requested due to a compare event occurred in dcmk cell. pll 12 rwh 1) counter service requ est state for pll 0 b no service is requested 1 b service is requested because the counter for the number remaining output pulses decremented to 0. gt00 13 rwh 1) gt0 timer service request state 0 b no service is requested. 1 b service is requested due to a gt0 timer overflow. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-226 v1.1, 2011-03 gpta ? v5, v1.0 gt01 14 rwh 1) gt1 timer service request state 0 b no service is requested. 1 b service is requested due to a gt1 timer overflow. 0 [31:15] r reserved read as 0; should be written with 0. 1) writing a one to a cleared bit sets the bit. all other write operations have no effect. 2) k = 0-3; k = 0 refers to dcm00r, dcm00f, or dcm00c; k = 1 refers to dcm01r, dcm01f, or dcm01c; k = 2 refers to dcm02r, dcm02f, or dcm02c; k = 3 refers to dcm03r, dcm03f, or dcm03c. gpta0_srsc1 gpta0 service request state clear register 1 (018 h ) reset value: 0000 0000 h gpta1_srsc1 gpta1 service request state clear register 1 (018 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gtc 31 gtc 30 gtc 29 gtc 28 gtc 27 gtc 26 gtc 25 gtc 24 gtc 23 gtc 22 gtc 21 gtc 20 gtc 19 gtc 18 gtc 17 gtc 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 1514131211109876543210 gtc 15 gtc 14 gtc 13 gtc 12 gtc 11 gtc 10 gtc 09 gtc 08 gtc 07 gtc 06 gtc 05 gtc 04 gtc 03 gtc 02 gtc 01 gtc 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description gtck (k = 00-31) krwh 1) 1) writing an one to a set bit clears the bit. all other write operations have no effect. gtck capture/compare service request state 0 b no service is requested. 1 b service is requested due to a capture or compare event occurred in gtck. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-227 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_srss1 gpta0 service request state set register 1 (01c h ) reset value: 0000 0000 h gpta1_srss1 gpta1 service request state set register 1 (01c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gtc 31 gtc 30 gtc 29 gtc 28 gtc 27 gtc 26 gtc 25 gtc 24 gtc 23 gtc 22 gtc 21 gtc 20 gtc 19 gtc 18 gtc 17 gtc 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 1514131211109876543210 gtc 15 gtc 14 gtc 13 gtc 12 gtc 11 gtc 10 gtc 09 gtc 08 gtc 07 gtc 06 gtc 05 gtc 04 gtc 03 gtc 02 gtc 01 gtc 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description gtck (k = 00-31) krwh 1) 1) writing a one to a cleared bit sets the bit. all other write operations have no effect. gtck capture/compare service request state 0 b no service is requested. 1 b service is requested due to a capture or compare event occurred in gtck. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-228 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_srsc2 gpta0 service request state clear register 2 (020 h ) reset value: 0000 0000 h gpta1_srsc2 gpta1 service request state clear register 2 (020 h ) reset value: 0000 0000 h ltca2_srsc2 ltca2 service request state clear register 2 (020 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ltc 31 ltc 30 ltc 29 ltc 28 ltc 27 ltc 26 ltc 25 ltc 24 ltc 23 ltc 22 ltc 21 ltc 20 ltc 19 ltc 18 ltc 17 ltc 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 1514131211109876543210 ltc 15 ltc 14 ltc 13 ltc 12 ltc 11 ltc 10 ltc 09 ltc 08 ltc 07 ltc 06 ltc 05 ltc 04 ltc 03 ltc 02 ltc 01 ltc 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description ltck (k = 00-31) krwh 1) 1) writing an one to a set bit clears the bit. all other write operations have no effect. ltck timer/capture/compare service request state 0 b no service is requested. 1 b service is requested due to a timer overflow, capture, or compare event that occurred in ltck. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-229 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_srss2 gpta0 service request state set register 2 (024 h ) reset value: 0000 0000 h gpta1_srss2 gpta1 service request state set register 2 (024 h ) reset value: 0000 0000 h ltca2_srss2 ltca2 service request state set register 2 (024 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ltc 31 ltc 30 ltc 29 ltc 28 ltc 27 ltc 26 ltc 25 ltc 24 ltc 23 ltc 22 ltc 21 ltc 20 ltc 19 ltc 18 ltc 17 ltc 16 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 1514131211109876543210 ltc 15 ltc 14 ltc 13 ltc 12 ltc 11 ltc 10 ltc 09 ltc 08 ltc 07 ltc 06 ltc 05 ltc 04 ltc 03 ltc 02 ltc 01 ltc 00 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description ltck (k = 00-31) krwh 1) 1) writing a one to a cleared bit sets the bit. all other write operations have no effect. ltck timer/capture/compare service request state 0 b no service is requested. 1 b service is requested due to a timer overflow, capture, or compare event that occurred in ltck. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-230 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_srsc3 gpta0 service request state clear register 3 (028 h ) reset value: 0000 0000 h gpta1_srsc3 gpta1 service request state clear register 3 (028 h ) reset value: 0000 0000 h ltca2_srsc3 ltca2 service request state clear register 3 (028 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ltc 63 ltc 62 ltc 61 ltc 60 ltc 59 ltc 58 ltc 57 ltc 56 ltc 55 ltc 54 ltc 53 ltc 52 ltc 51 ltc 50 ltc 49 ltc 48 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 1514131211109876543210 ltc 47 ltc 46 ltc 45 ltc 44 ltc 43 ltc 42 ltc 41 ltc 40 ltc 39 ltc 38 ltc 37 ltc 36 ltc 35 ltc 34 ltc 33 ltc 32 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description ltck (k = 32-63) k-32 rwh 1) 1) writing an one to a set bit clears the bit. all other write operations have no effect. ltck timer/capture/compare service request state 0 b no service is requested. 1 b service is requested due to a timer overflow, capture, or compare event that occurred in ltck. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-231 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_srss3 gpta0 service request state set register 3 (02c h ) reset value: 0000 0000 h gpta1_srss3 gpta1 service request state set register 3 (02c h ) reset value: 0000 0000 h ltca2_srss3 ltca2 service request state set register 3 (02c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ltc 63 ltc 62 ltc 61 ltc 60 ltc 59 ltc 58 ltc 57 ltc 56 ltc 55 ltc 54 ltc 53 ltc 52 ltc 51 ltc 50 ltc 49 ltc 48 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh 1514131211109876543210 ltc 47 ltc 46 ltc 45 ltc 44 ltc 43 ltc 42 ltc 41 ltc 40 ltc 39 ltc 38 ltc 37 ltc 36 ltc 35 ltc 34 ltc 33 ltc 32 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description ltck (k = 32-63) k-32 rwh 1) 1) writing a one to a cleared bit sets the bit. all other write operations have no effect. ltck timer/capture/compare service request state 0 b no service is requested. 1 b service is requested due to a timer overflow, capture, or compare event that occurred in ltck. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-232 v1.1, 2011-03 gpta ? v5, v1.0 node redirection register the service request node redirection register allows that gtc service requests of gtcs with an odd index number k can be individually redirected via register srnr to a service request group that is assigned mainly to four ltcs. more details are provided on page 28-124 . gpta0_srnr gpta0 service request node redirection register (030 h ) reset value: 0000 0000 h gpta1_srnr gpta1 service request node redirection register (030 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 gtc 31r gtc 29r gtc 27r gtc 25r gtc 23r gtc 21r gtc 19r gtc 17r gtc 15r gtc 13r gtc 11r gtc 09r gtc 07r gtc 05r gtc 03r gtc 01r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description gtc01r, gtc03r, gtc05r, gtc07r, gtc09r, gtc11r, gtc13r, gtc15r, gtc17r, gtc19r, gtc21r, gtc23r, gtc25r, gtc27r, gtc29r, gtc31r 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 rw global timer cell k redirection 0 b no redirection of gtc service requests. 1 b redirection of gtc service request to ltc service request groups (see page 28-124 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-233 v1.1, 2011-03 gpta ? v5, v1.0 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-234 v1.1, 2011-03 gpta ? v5, v1.0 28.5 ltca kernel description the local timer cell array (ltca2) is a unit that contains signal generation cells with 64 local timer cells. these ltcs have ident ical functionality as the ltcs which are available in the signal generation cells of the gpta ? v5 module. the local timer cells (ltc00 to ltc62) can be configured to operate in different modes: capture mode, compare mode, free-running timer mode, reset timer mode, and one shot mode. adjacent cells may be combined to operate on the same pin, thus generating complex waveforms. one ltc (ltc63) can be used for special compare modes. figure 28-81 block diagram of ltca unit kernel the ltca unit kernel contains signal gener ation cells that contains all local timer cells including an i/o line sharing block that controls the ltc connections to the i/o lines and output lines. i/o lines are supposed to be connected to i/o port lines while the output lines are typically connected to a msc in terface that is especially able to control external power devices via a serial connection. the ltcs can be further connected to input signals of an external clock bus and input lines coming e.g. from other on-chip peripheral modules. the clock control cells generates two modules clocks that are required for ltca operation. an address decoder generates the select signals for the ltc registers. service requests, coming from the ltcs, are able to generate interrupts via the interrupt sharing block. the interrupts are handled by the external interrupt logic. mcb05983 clock control address decoder f lt c a2 ltca module kernel i/o line shar ing block signal generation cells local timer cells ltc[63:00 ] f clc interrupt control sr [15 :00 ] int[3:0] interrupt sharing block in[31:00] out[111 :80 ] out[31:00] clk[7:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-235 v1.1, 2011-03 gpta ? v5, v1.0 28.5.1 local timer cell (ltc00 to ltc63) ltc00 to ltc62 are fully identical with the local timer cells in the gpta0 and gpta1 units. its functionalities are described in gpta ? v5 section ?local timer cell (ltc00 to ltc62)? on page 28-67 and ltc63 functionalities are described in gpta ? v5 section ?local timer cell ltc63? on page 28-79 . 28.5.2 input/output line sharing block (iols) the i/o line sharing block allows the inputs and outputs of the ltca unit to be routed with high flexibility between i/o lines, output lines, clock inputs, and other on-chip peripherals. the ltca unit provides a total of 32 input lines and 64 output lines, that are connected to four i/o groups iog[3:0] and four output groups og[6:3]. figure 28-82 input/output line sharing block overview the ltca i/o line sharing block makes the following two selections: ? ltc output multiplexer selection ? ltc input multiplexer selection to choose these selection, the input and output lines of the related cells are integrated into groups with eight parts, each. there ar e i/o groups, output groups, ltc groups, and a pdl/int group. mca05984_ltca64.vsd output multiplexer 32 ltc input multiplexer ltca module kernel output groups og3 iog2 iog1 iog0 i/o groups ltcg2 ltcg1 ltcg0 ltc groups 32 8 4 4 32 32 32 32 out [31:00] in [31 :00 ] out [111:80 ] clk[7:0] pdl[3:0] int[3:0] iog3 ltcg4 ltcg3 ltcg5 ltcg6 ltcg7 og4 og5 og6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-236 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-83 groups definitions for i/o line sharing block an ltc group combines eight ltc cells with its input and output lines. this results in eight ltc groups, ltcg0 to ltcg7. an i/o group combines eight ltca i/o lines connected to bi-directional device pins with its input and output lines. this results in four i/o groups, iog0 to iog3, supporting 32 i/o lines. an output group combines four ltca output lines connected to device pins as an output. this results in four output groups, og3 to og6, supporting 32 output lines. the pdl/int group is a logical group that combines the ltca unit inputs pdl[3:0] together with the inputs int[3:0]. the clock group is a logical group that combines the eight ltca unit clock inputs clk[7:0]. mca05985_tc1767 pdl0 pdl1 pdl2 pdl3 int0 int1 int2 int3 pdl/int group int2 int3 int0 int1 pdl2 pdl3 pdl0 pdl1 clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 clock group clk6 clk7 clk4 clk5 clk2 clk3 clk0 clk1 ltc24in ltc25in ltc26in ltc27in ltc28in ltc29in ltc30in ltc31in example for an ltc group: ltcg3 ltc24 ltc25 ltc26 ltc27 ltc28 ltc29 ltc30 ltc31 ltc24out ltc25out ltc26out ltc27out ltc28out ltc29out ltc30out ltc31out pin io08 pin io09 pin io10 pin io11 pin io12 pin io13 pin io14 pin io15 out08 out09 out10 out11 out12 out13 out14 out15 in08 in09 in10 in11 in12 in13 in14 in15 example for an i/o group: iog1 pin o80 pin o81 pin o82 pin o83 pin o84 pin o85 pin o86 pin o87 out80 out81 out82 out83 out84 out85 out86 out87 example for an output group: og3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-237 v1.1, 2011-03 gpta ? v5, v1.0 28.5.2.1 output multiplexer the output multiplexer shown in figure 28-84 and figure 28-86 connects the 64 ltc output lines with the i/o groups (4 8 = 32 output lines) and the output groups (4 8 = 32 output lines). table 28-20 group to i/o line/cell assignment group/unit cell/line input output ltc groups ltcg0 ltc[07:00] ltc[07:00]in ltc[07:00]out ltcg1 ltc[15:08] ltc[15:08]in ltc[15:08]out ltcg2 ltc[23:16] ltc[23:16]in ltc[23:16]out ltcg3 ltc[31:24] ltc[31:24]in ltc[31:24]out ltcg4 ltc[39:32] ltc[39:32]in ltc[39:32]out ltcg5 ltc[47:40] ltc[47:40]in ltc[47:40]out ltcg6 ltc[55:48] ltc[55:48]in ltc[55:48]out ltcg7 ltc[63:56] ltc[63:56]in ltc[63:56]out i/o groups iog0 ? in[07:00] out[07:00] iog1 ? in[15:08] out[15:08] iog2 ? in[23:16] out[23:16] iog3 ? in[31:24] out[31:24] output groups og3 ? ? out[87:80] og4 ? ? out[95:88] og5 ? ? out[103:96] og6 ? ? out[111:104] clock group ? ? clk[7:0] clk[7:0] pdl/int groups pdl[1:0] pdl bus ? pdl[3:0] pdl[3:0] external input [3:0] ? int[3:0] int[3:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-238 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-84 output multiplexer of ltca the output multiplexer contains output multiplexer groups (omgs) that connect the local timer cells with the input lines of the i/o groups and output groups. the ltcs are grouped into eight ltc groups (ltcg[7:0]) with 8 cells each. in the same way, i/o groups and output groups are grouped into 8 groups (four i/o groups and four output groups) with 8 lines each. output mu ltip lexer lt c g rou ps mca05986 i/o groups iog0 iog1 iog2 iog3 ltcg0 ltc[07:00] ltcg1 ltc[15:08] ltcg2 ltc[23:16] ltcg3 ltc[31:24] ltcg5 ltc[47:40] ltcg6 ltc[55:48] ltcg7 ltc[63:56] omg 10 omg 11 omg 12 omg 13 omg 20 omg 21 omg 22 ltcg4 ltc[39:32] output groups og3 og4 og5 og6 omg 1a omg 2a omg 1b omg 2b omg 1c omg 1d omg 2d 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 omg 23 omg 2c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-239 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-85 shows the logical structure of an omg. figure 28-85 output multiple xer group (omg) structure rules for connections to output multiplexer group omg: ? omg output line out0 is always connected to the input of an i/o or output group with the lowest index. the remaining output lines out1 to out7 are connected to the i/o or output lines with ascending index. example: for omg13 (see figure 28-84 ), the outputs out0 to out7 are wired to input lines 0 to 7 of i/o group 3 (iog3). ? one input of an i/o or output group can be connected only to the output of one timer cell. this is guaranteed by the omg control register layout. otherwise, short circuits and unpredictable behavior would occur. on the other hand, it is permitted that for the output of an ltc cell to be connected to more than one input of an i/o or output group. the output multiplexer group configuration is based on the following principles: ? each omg is referenced with two index variables: n and g (omgng) ? index n is a group number. local time r cell groups ltcg[3:0] have the group number 1, and local timer cell groups ltcg[7:4] have the group number 2. ? index g indicates the number of an i/o or output group g (g = 3-7 d ) to which the outputs of the output multiplexer group omgng are connected. i/o groups og0 to og3 are assigned to index variable g = 0 to 3 and output groups og3 to og6 are assigned to index variable g = 10 to 13. index g = 4, 5, 6, 7, 8, 9 are not available. the output multiplexer logic as seen for programming is shown in figure 28-86 . with this logic, one ltc group signal is always combined to one output line that leads to the mca05987 from other omgs in0 in1 in2 in3 in4 in5 in6 in7 o utputs of a l tc group to other omgs out0 out1 out2 out3 out4 out5 out6 out7 to i/o or output groups more than one switch might be closed per row , only one switch can be closed per column www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-240 v1.1, 2011-03 gpta ? v5, v1.0 input of an i/o or output group. for example, when looking at figure 28-84 , each of the eight output multiplexer output lines to i/o group iog0 is connected via two omgs (omg10 and omg20) with the eight outputs of two ltc groups (ltcg0 and ltcg4). figure 28-86 omg multiplexer (programmer?s view) the 1. level multiplexer is built up by two 8:1 multiplexers that are controlled in parallel by bit field omln. bit field omgn controls the 2. level multiplexer and connects one of the 1. level multiplexer outputs to the 2. level inputs.the output of the 2. level multiplexer is connected only to the input of an i/o group or output group if bit mractl.maen (multiplexer array enabled) is set. if mractl.maen = 0, the corresponding omg output will be held at a low level. two output multiplexer control registers, omcrl and omcrh (see also page 28-210 ), are assigned to each of the i/o or output groups. therefore, in total 16 registers control the connections within the output multiplexer of the ltca unit. the omcrl registers control the omg output lines 0 to 3 and the omcrh registers control the omg output lines 4 to 7. table 28-21 lists all output multiplexer control registers with its control functions. please note that all output multiplexer control registers are not directly accessible but must be written or read using the fifo array structure as described on page 28-210 . mca05973_mod mux 8 mux ltc group (omg1g) ltc group (omg2g) mux 001 000 2 . level mux omln omgn 1. level mux omcrlg omcrhg (g = 0-13 ) to input of i/o group g or output group (g-7 ) mux 0 1 maen mractl & not a reserved omgn bit combination 0 8 3 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-241 v1.1, 2011-03 gpta ? v5, v1.0 table 28-21 output multiplexer control register assignments i/o group or output group controlled by multiplexer control register selectable groups via omgng iog0 in[03:00]/out[03:00] omcrl0 ltcg0 / ltcg4 in[07:04]/out[07:04] omcrh0 iog1 in[11:08]/out[11:08] omcrl1 ltcg1 / ltcg5 in[15:12]/out[15:12] omcrh1 iog2 in[19:16]/out[19:16] omcrl2 ltcg2 / ltcg6 in[23:20]/out[23:20] omcrh2 iog3 in[27:24]/out[27:24] omcrl3 ltcg3 / ltcg7 in[31:28]/out[31:28] omcrh3 og0 out[59:56] 1) 1) out[55:32] is not available. omcrl07 ltcg3 / ltcg7 out[63:60] omcrh07 og1 out[67:64] omcrl08 ltcg0 / ltcg4 out[71:68] omcrh08 og2 out[75:72] omcrl09 ltcg1 / ltcg5 out[79:76] omcrh09 og3 out[83:80] omcrl10 ltcg2 / ltcg6 out[87:84] omcrh10 og4 out[91:88] omcrl11 ltcg3 / ltcg7 out[95:92] omcrh11 og5 out[99:96] omcrl12 ltcg0 / ltcg4 out[103:100] omcrh12 og6 out[107:104] omcrl13 ltcg1 / ltcg5 out[111:108] omcrh13 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-242 v1.1, 2011-03 gpta ? v5, v1.0 28.5.2.2 ltc input multiplexing scheme the ltc input multiplexer as shown in figure 28-87 and figure 28-89 connects the 32 (= 4 8) input lines of the i/o groups, the eight clock bus input lines, or the four pdl input lines pdl[3:0] and the four internal input lines int[3:0] with the 64 (= 8 8) ltc inputs, organized in eight ltc groups. figure 28-87 ltc input multiplexer of ltca i/o groups mca05989_ltca 64 ltc groups 8 iog0 iog1 iog2 iog3 limg 00 limg 02 limg 03 limg 01 pdl[3:0] int[3:0] ltcg0 ltc[07:00 ] ltcg1 ltc[15:08] ltcg2 ltc[23 :16] ltcg3 ltc[31:24 ] clk[7:0] limg 40 limg 41 limg 42 limg 30 limg 31 limg 32 limg 33 8 8 8 8 8 8 8 8 8 limg 43 ltc input mu ltip lexer limg 04 limg 06 limg 07 limg 05 ltcg4 ltc[07:00 ] ltcg5 ltc[15:08] ltcg6 ltc[23 :16] ltcg7 ltc[31:24 ] limg 44 limg 45 limg 46 limg 34 limg 35 limg 36 limg 37 8 8 8 8 limg 47 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-243 v1.1, 2011-03 gpta ? v5, v1.0 the ltc input multiplexer contains ltc input multiplexer groups (limgs) that connect the i/o groups or the clock, pdl, or int inpu ts to the input lines of the ltcs, organized in eight ltc groups with 8 cells each. iogs are grouped into four iogs (iog[3:0]) with eight lines each. two special groups are available, a clock group with eight lines representing the clock bus inputs clk[7:0] and a pdl/int group with eight outputs that combines the four pdl inputs and the four inputs int[3:0] as a group of limgs inputs. figure 28-88 shows the logical structure of a limg. figure 28-88 ltc input multiplexer group (limg) structure rules for connections to ltc input multiplexer group limg: ? within a i/o group, the line or the output of the cell with the lowest index number is connected to limg input line in0. the remaining lines, cells or lines of a group are connected to limg input lines in1 to in7 with ascending index numbers. at the clock group, clk0 is connected to in0 and the remaining clock lines are connected to limg input lines in1 to in7 with ascending index numbers. at the pdl/int group, pdl[3:0] (see page 28-22 ) are connected to in[3:0] and int[3:0] are connected to in[7:4]. example: for limg04 (see figure 28-87 ), the i/o lines of iog0 (in00 up to in07) are wired to its input lines in0 to line in7. ? multiplexer output out0 of a limg is always connected to the input of an ltc group with the lowest index. the remaining output lines out1 to out7 are connected to the ltc inputs with ascending index. example: for limg04 (see figure 28-87 ), the outputs out0 to out7 are wired to the inputs of ltc32 to ltc39. ? an ltc input can be connected either to an i/o group output, or to a clock bus output, or to an pdl/int output. this is guaranteed by the limg control register layout. mca05990 from other limgs in0 in1 in2 in3 in4 in5 in6 in7 o utputs of an i /o group or c lk group or p dl/int group to other limgs out0 out1 out2 out3 out4 out5 out6 out7 to ltc groups more than one switch might be closed per ro w, only one switch can be closed per column www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-244 v1.1, 2011-03 gpta ? v5, v1.0 otherwise, short circuits and unpredictable behavior would occur. in contrast, it is permitted that an i/o group output, or to a clock bus output, or a pdl/int output is connected to more than one ltc input. the ltc input multiplexer group configuration is based on the following principles: ? each limg is referenced with two index variables: n and g (limgng) ? index n is a group number. i/o groups iog[3:0] have group number 0, i/o group iog4 is not implemented, clock bus lines clk[7:0] have group number 3, and the pdl/int group has group number 4. ? index g indicates the number of the ltc group g (g = 0-7) to which the outputs of the input multiplexer group limgng are connected. the ltc input multiplexer logic as seen for programming is shown in figure 28-89 . with this logic, three group signals (from i/o groups, clock group, or pdl/int group) are always combined to one output line that leads to an ltc input of ltc group g. for example, when looking at figure 28-87 , each of the eight ltc input multiplexer output lines to ltc group ltcg2 is connected vi a three limgn2 (n = 0, 3, 4) to the eight outputs of i/o group iog2, the clock group, and the pdl/int group. figure 28-89 ltc input multip lexer (programmer?s view) the 1. level multiplexer is built up by four three 8:1 multiplexers that are controlled in parallel by bit field limln. the output of the multiplexer is connected only to the input of an ltc if bit limenn is set (enable multiplexer connection), and bit mractl.aen is set (multiplexer array enabled), and no reserved bit combination is selected. if one of these conditions is not true, the corresponding ltc input will be held at a low level. mca05991_ltc32.vsd mux i/o group (limg0g) mux 001 000 2. level mux limln limgn 1 . level mux limcrlg limcrhg ( g = 0- 3) to input n of ltc group g mux 011 100 clock group (limg3g) fpc/int group (limg4g) mux limenn 0 mux 0 1 maen mractl registers & not a reserved limgn bit combination 8 3 3 8 8 reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-245 v1.1, 2011-03 gpta ? v5, v1.0 two ltc input multiplexer control registers, limcrl (see also page 28-271 and page 28-272 ), are assigned to each of the ltc groups. therefore, in total sixteen registers control the connections within the ltc input multiplexer of the ltca unit. the limcrl registers control the limg output lines 0 to 3 and the limcrh registers control the limg output lines 4 to 7. table 28-22 lists all ltc input multiplexer control registers with its control functions. please note that all ltc input multiplexer control registers are not directly accessible but must be written or read using a fifo array structure as described on page 28-121 . 28.5.2.3 multiplexer regi ster array programming a total of 38 control registers are required to program the configuration of the output multiplexer and the ltc input multiplexer of the input/output line sharing block. these iols control registers are combined into a multiplexer register array fifo that can only be read or written sequentially. therefor e, the control registers values cannot be accessed directly but must be accessed in a specific sequential order. three registers are available for controlling the multiplexer register array: ? multiplexer register array control register mractl table 28-22 ltc input multiplexer control register assignments ltc group and ltcs controlled by register selectable groups via limgng ltcg0 ltc[03:00] limcrl0 iog0, clock, pdl/int ltc[07:04] limcrh0 ltcg1 ltc[11:08] limcrl1 iog1, clock, pdl/int ltc[15:12] limcrh1 ltcg2 ltc[19:16] limcrl2 iog2, clock, pdl/int ltc[23:20] limcrh2 ltcg3 ltc[27:24] limcrl3 iog3, clock, pdl/int ltc[31:28] limcrh3 ltcg4 ltc[35:32] limcrl4 iog0, clock, pdl/int ltc[39:36] limcrh4 ltcg5 ltc[43:40] limcrl5 iog1, clock, pdl/int ltc[47:44] limcrh5 ltcg6 ltc[51:48] limcrl6 iog2, clock, pdl/int ltc[55:52] limcrh6 ltcg7 ltc[59:56] limcrl7 iog3, clock, pdl/int ltc[63:60] limcrh7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-246 v1.1, 2011-03 gpta ? v5, v1.0 ? multiplexer register array data out register mradout ? multiplexer register array data in register mradin figure 28-90 shows the structure of the multiplexer array fifo with the arrangement of the multiplexer control registers. for programming of the multiplexer array fifo, the following steps must be executed: 1. disable interconnections of the multiplexer array by writing mractl.maen = 0 (default after reset). the multiplexer array is disabled, all cell input lines are driven with 0, and device pins assigned to ltca i/o lines or output lines are disconnected. 2. reset the write cycle counter to 0 by writing mractl.wcres = 1. 3. write sequentially the multiplexer control register contents one after the other (38 values) into mradin, starting with the register values for omcrh10, omcrl10, ? up to limcrh0, limcrl0 (see figure 28-90 ). after the first mradin write operation, the contents for omcrh10 is at fifo position 1. with each following mradin write operation, it becomes shifted one fifo position upwards. after the 38. mradin write operation, the omcrh10 value is at its final position. the contents of fifo position 38 can be read via register mradout. with each mradin write operation the write cycle counter mractl.fif ofillcnt is incremented by 1. after all fifo entries have been written, the fi fo is locked, bit mr actl.fifofull is set, and further mradin write operations are discarded until bit mractl.wcres is written again with a 0. 4. enable the multiplexer array by writing mractl.maen = 1. this establishes and enables all programmed interconnections. to check the fifo contents, the fifo can be written a second time. at this check mradin is written before mradout is read. th is will return the fi fo contents of the first write sequence in the order of omcrh10, omcrl10, ?, limcrl0. before disabling the multiplexer array fifo, ltca output pins that are already enabled as ltca output should be switched to gpio function to avoid output spikes. after enabling the multiplexer array fifo again, the ltca output can be switched again back to ltca output function. shifting the write data th rough the fifo requires a few clock cycles. when new data becomes written before the fifo is ready to accept them, wait states will be inserted into the write access. if the omcrlg register bit field omgn of t he multiplexer array is programmed with an invalid (reserved) value, the related outputs will be forced to 0. when the array is disabled (mractl.maen = 0), all cell inputs and outputs are disconnected from the gpio lines and are driven with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-247 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-90 ltca multiplexer array control register fifo structure multiplexer register array fifo mca05992_ltca64.vsd omcrl13 31 32 31 omcrh13 omcrl00 17 18 omcrh00 mradout 0 output multiplexer control registers limcrl7 15 16 limcrh7 limcrl0 1 2 limcrh0 ltc input multiplexer control registers mradin mractl 31 0 31 0 omcrl10 25 26 omcrh10 omcrl03 23 24 omcrh03 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-248 v1.1, 2011-03 gpta ? v5, v1.0 28.5.3 interrupt sh aring block (is) the ltca provides 16 service request s ources. these service request sources are generated by the ltcs. to reduce hardware and software overhead, four request sources are combined together in service request groups. a service request group y (y = 00-15) has four service request inputs and one service reques t output sry which is typically connected outside the ltca kernel to a standard interrupt node y and controlled by its srcy register. figure 28-91 service request groups the bits in the service request state registers (srssx and srscx, x = 3, 2) are service request status flags that are set by hardware (type ?h?) when the related event occurs. each ltca service request source has its own service request flag. this flag is normally set by hardware but can be set and reset by software. each service request status flag can be read twice, at the same bit location in srscx register and in srssx register, and cleared or set by software when writing to the corresponding request bit in srscx or srssx. when writing to srscx or srssx, several flags can be cleared at once by one write operation. flags written with 0 are not influenced. this feature allows fast, simple clearing or setting of request flags without affecting other bits in the same register. note that the service request flag is always set by the service request event even if the corresponding service request is disabled in the interrupt node. table 28-24 lists the interrupt requests used by ltca. table 28-23 ltca number of service request sources cell type number of cells number of service request sources/cell total number of request sources ltc 64 1 16 mca05993 a t maximum f our request s ources f rom ltcs service request node y (srcy register) service request group y sry 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-249 v1.1, 2011-03 gpta ? v5, v1.0 table 28-24 ltca service request groups service request group number source 1 source 2 source 3 source 4 00 ltc00 ltc01 ltc02 ltc03 01 ltc04 ltc05 ltc06 ltc07 02 ltc08 ltc09 ltc10 ltc11 03 ltc12 ltc13 ltc14 ltc15 04 ltc16 ltc17 ltc18 ltc19 05 ltc20 ltc21 ltc22 ltc23 06 ltc24 ltc25 ltc26 ltc27 07 ltc28 ltc29 ltc30 ltc31 08 ltc32 ltc33 ltc34 ltc35 09 ltc36 ltc37 ltc38 ltc39 10 ltc40 ltc41 ltc42 ltc43 11 ltc44 ltc45 ltc46 ltc47 12 ltc48 ltc49 ltc50 ltc51 13 ltc52 ltc53 ltc54 ltc55 14 ltc56 ltc57 ltc58 ltc59 15 ltc60 ltc61 ltc62 ltc63 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-250 v1.1, 2011-03 gpta ? v5, v1.0 28.6 ltca kernel registers this section describes the ltca kernel registers. some of the kernel registers (srscn, srssn, ltcctrk, and ltcxrk) are already described as gpta ? v5 kernel register at the pages as referenced in column ?description see? of table 28-25 . the multiplexer array fifo registers are ltca specific and therefore defined on the next pages. figure 28-92 ltca2 kernel registers table 28-25 ltca2 kernel registers register short name register long name offset addr. access mode reset class description see read write id ltca identification register 0008 h u, sv nbe 1 page 28-166 srsc2 service request state clear register 2 0020 h u, sv sv, e 3 page 28-228 srss2 service request state set register 2 0024 h u, sv sv, e 3 page 28-229 srsc3 service request state clear register 3 0028 h u, sv sv, e 3 page 28-230 srss3 service request state set register 3 002c h u, sv sv, e 3 page 28-231 mractl multiplexer register array control register 0038 h u, sv u, sv 3 page 28-264 mradin multiplexer register array data in register 003c h u, sv, 32 u, sv, 32 3 page 28-266 control registers interrupt & iols registers data registers ltcxrk ltcctrk 1) k = 00-63 2 ) g = 0-3 , 10 -13 3 ) g = 0-4 1) 1) mca05994_ltca 64.vsd srsc3 srss3 mractl mradin mradout multiplexer array fifo registers omrclg omrchg limcrlg limcrhg 2) 2) 3) 3) note: the multiplexer array fifo registers are not directly accessible ! srsc2 srss2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-251 v1.1, 2011-03 gpta ? v5, v1.0 28.6.1 bit protection bits with bit protection (this is valid, for example, for all bits in the service request state registers) are not changed during a read-modify-write instruction, that is when hardware sets a request state bit between the read and the write of the read-modify-write sequence. for bit protected bits it is guaranteed that a hardware setting operation always has priority. thus, no hardware triggered events are lost. mradout multiplexer register array data out register 0040 h u, sv, 32 u, sv, 32 3 page 28-266 ltcctrk local timer cell control register k (k = 00-62) 0200 h +k 8 u, sv u, sv 3 page 28-252 page 28-255 page 28-258 ltcxrk local timer cell x register k (k = 00-62) 0204 h +k 8 u, sv u, sv 3 page 28-263 ltcctr63 local timer cell control register 63 0200 h +63 8 u, sv u, sv 3 page 28-261 ltcxr63 local timer cell x register 63 0204 h +63 8 u, sv u, sv 3 page 28-263 omcrlg output multiplexer control register for lower half of group g (g = 0-3, 10-13) not directly address- able see page 28 -245 n.a. n.a. 3 page 28-268 omcrhg output multiplexer control register for upper half of group g (g = 0-3, 10-13) n.a. n.a. 3 page 28-269 limcrlg input multiplexer control register for lower half of ltc group g (g = 0-7) not directly address- able see page 28 -245 n.a. n.a. 3 page 28-271 limcrhg input multiplexer control register for upper half of ltc group g (g = 0-7) n.a. n.a. 3 page 28-272 table 28-25 ltca2 kernel registers (cont?d) register short name register long name offset addr. access mode reset class description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-252 v1.1, 2011-03 gpta ? v5, v1.0 28.6.2 service request registers see ?gpta0_srsc2? on page 28-228 . 28.6.3 local timer cell registers ltca2_ltcctrk (k = 00-62) local timer cell control register k [timer mode] (200 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 g byp rrw 1514131211109876543210 out oia ocm cen cud ilm cud clr slo fed or ail red or pen ren osm mod rh rw rw rh rwh rw w rwh rw rw rw rw rw field bits type description mod [1:0] rw mode control bits 00 b ltck operates in capture mode 01 b ltck operates in compare mode 10 b ltck operates in free-running timer mode 11 b ltck operates in reset timer mode osm 2rw one shot mode enable 0 b ltck is continuously enabled 1 b ltck is enabled for one event only ren 3rw request enable 0 b service request is disabled. 1 b service request sqsk is activated when a - capture event has occurred - compare event has occurred - timer overflow has happened depending on the operation mode selected by bit field mod. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-253 v1.1, 2011-03 gpta ? v5, v1.0 red 4rw ilm = 0: input rising edge select 0 b timer is not updated by a rising edge 1 b timer is updated by a rising edge on the ltckin input line pen 4rw ilm = 1: ltc prescaler enable 0 b ltc prescaler mode is disabled 1 b ltc prescaler mode with ltc prescaler clock ltcpre is enabled fed 5rw ilm = 0: input falling edge select 0 b timer is not updated by a falling edge 1 b timer is updated by a falling edge on the ltckin input line ail 5rw ilm = 1: active input level select 0 b input signal is active high 1 b input signal is active low slo 6rwh select line output 0 b state of select line output so is 0 1 b state of select line output so is 1 slo is bit protected (see page 28-167 ). cudclr 7w coherent update disable 0 b no effect 1 b coherent update disabled (bit cud is cleared) if bits cud and cudclr are both written with 1, bit cud will be set. cudclr is always read as 0. ilm 8rw input line mode 0 b input line is operating in edge sensitive mode. 1 b input line is operating in level sensitive mode. in case of full speed gpta ? v5 module clock selection as input clock, level sensitive mode must be selected. in this case the edge sensitive mode will not produce any event. cud 9rwh coherent update enable 0 b select output so is not toggled on timer reset overflow 1 b select output so is toggled on next timer reset overflow when cud is set by software (writing cud and cudclr both with 1), it remains set until the next timer reset overflow (ltck reset event) occurs and is cleared by hardware afterwards. cud can be reset by software by writing bit cudclr with 1 and cud with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-254 v1.1, 2011-03 gpta ? v5, v1.0 cen 10 rh cell enable 0 b ltck is currently disabled for local events 1 b ltck is currently enabled for local events ocm [13:11] rw output control mode select 000 b current state of ltckout output line is hold 001 b current state of ltckout output line is toggled by an internal ltck event otherwise hold 010 b ltckout output line is forced to 0 by an internal ltck event otherwise hold 011 b ltckout output line is forced to 1 by an internal ltck event otherwise hold 1xx b ltckout output line state is affected by an internal ltck event and/or by an operation occurred in an adjacent ltck cell (reported by m1i/m0i interface lines) oia 14 rw output immediate action 0 b no immediate action required 1 b action defined by bit field ocm must be performed immediately oia is always read as 0. out 15 rh output state 0 b ltckout output line is 0 1 b ltckout output line is 1 gbyp 16 rw global bypass 0 b m3o/m2o lines are affected by m1i/m0i lines 1 b m3o/m2o lines are affected by m3i/m2i lines 0 [31:17] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-255 v1.1, 2011-03 gpta ? v5, v1.0 ltca2_ltcctrk (k = 00-62) local timer cell control register k [capture mode] (200 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 g byp rrw 1514131211109876543210 out oia ocm cen sll ilm eoa byp fed red ren osm mod rh rw rw rh rh rw rwh rw rw rw rw rw rw field bits type description mod [1:0] rw mode control bits 00 b ltck operates in capture mode. 01 b ltck operates in compare mode. 10 b ltck operates in free-running timer mode. 11 b ltck operates in reset timer mode. osm 2rw one shot mode enable 0 b ltck is continuously enabled. 1 b ltck is enabled for one event only. ren 3rw request enable 0 b service request is disabled. 1 b service request sqsk is activated when a - capture event has occurred - compare event has occurred - timer overflow has happened depending on the operation mode selected by bit field mod. red 4rw input rising edge select 0 b capture event is not triggered by a rising edge. 1 b capture event is triggered by a rising edge on the ltckin input line. fed 5rw input falling edge select 0 b capture event is not triggered by a falling edge. 1 b capture event is triggered by a falling edge on the ltckin input line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-256 v1.1, 2011-03 gpta ? v5, v1.0 byp 6rw local bypass 0 b m1o/m0o lines are affected eith er by m1i/m0i lines or by ocm1/ocm0 bits. 1 b m1o/m0o lines are affected only by m1i/m0i (gbyp = 0) or m2i/m2i (gbyp = 1) lines. this bit is cleared if mode is switched to timer mode. ocm2 must be set in any case to enable reaction on m1i/m0i change. eoa 7rwh enable on action 0 b ltck is enabled for local events. 1 b ltck is disabled for local events. on an event on the communication link via m0i/m1i lines, eoa will be cleared and local events will be enabled. eoa is bit protected (see section 28.4.2 ). eoa is cleared if mode is switched to timer mode. ilm 8rw input line mode 0 b input line is operating in edge sensitive mode. 1 b input line is operating in level sensitive mode. in case of full speed gpta ? v5 module clock selection as input clock, level sensitive mode must be selected. in this case the edge sensitive mode will not produce any event. sll 9rh capture & compare mode: select line level 0 b current state of select input si is 0. 1 b current state of select input si is 1. cen 10 rh cell enable 0 b ltck is currently disabled for local events. 1 b ltck is currently enabled for local events. ocm [13:11] rw output control mode select 000 b current state of ltckout output line is hold 001 b current state of ltckout output line is toggled by an internal ltck event otherwise hold 010 b ltckout output line is forced to 0 by an internal ltck event otherwise hold 011 b ltckout output line is forced to 1 by an internal ltck event otherwise hold 1xx b ltckout output line state is affected by an internal ltck event and/or by an operation occurred in an adjacent ltck cell (reported by m1i/m0i interface lines). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-257 v1.1, 2011-03 gpta ? v5, v1.0 oia 14 rw output immediate action 0 b no immediate action required. 1 b action defined by bit field ocm must be performed immediately. oia is always read as 0. out 15 rh output state 0 b ltckout output line is 0. 1 b ltckout output line is 1. gbyp 16 rw global bypass 0 b m3o/m2o lines are affected by m1i/m0i lines. 1 b m3o/m2o lines are affected by m3i/m2i lines. 0 [31:17] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-258 v1.1, 2011-03 gpta ? v5, v1.0 ltca2_ltcctrk (k = 00-62) local timer cell control register k [compare mode] (200 h +k*8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 g byp rrw 1514131211109876543210 out oia ocm cen sll ilm eoa byp soh sol ren osm mod rh rw rw rh rh rw rwh rw rw rw rw rw rw field bits type description mod [1:0] rw mode control bits 00 b ltck operates in capture mode. 01 b ltck operates in compare mode. 10 b ltck operates in free-running timer mode. 11 b ltck operates in reset timer mode. osm 2rw one shot mode enable 0 b ltck is continuously enabled. 1 b ltck is enabled for one event only. ren 3rw request enable 0 b service request is disabled. 1 b service request sqsk is activated when a - capture event has occurred - compare event has occurred - timer overflow has happened depending on the operation mode selected by bit field mod. sol 4rw compare mode: select output low 0 b compare is deactivated or on high level. 1 b compare operation is enabled by a low level on select input si 1) . soh 5rw compare mode: select output high 0 b compare is deactivated or on high level. 1 b compare operation is enabled by a high level on select input si 1) . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-259 v1.1, 2011-03 gpta ? v5, v1.0 byp 6rw bypass 0 b m1o/m0o lines are affected eith er by m1i/m0i lines or by ocm1/ocm0 bits. 1 b m1o/m0o lines are affected only by m1i/m0i lines. this bit is cleared if mode is switched to timer mode. ocm2 must be set in any case to enable reaction on m1i/m0i change. eoa 7rwh enable on action 0 b ltck is enabled for local events. 1 b ltck is disabled for local events. on an event on the communication link via m0i/m1i lines, eoa will be cleared and local events will be enabled. eoa is bit protected (see section 28.4.2 ). eoa is cleared if mode is switched to timer mode. ilm 8rw input line mode 0 b input line is operating in edge sensitive mode. 1 b input line is operating in level sensitive mode. in case of full speed gpta ? v5 module clock selection as input clock, level sensitive mode must be selected. in this case the edge sensitive mode will not produce any event. sll 9rh select line level 0 b current state of select input si is 0. 1 b current state of select input si is 1. cen 10 rh cell enable 0 b ltck is currently disabled for local events. 1 b ltck is currently enabled for local events. ocm [13:11] rw output control mode select 000 b current state of ltckout output line is hold 001 b current state of ltckout output line is toggled by an internal ltck event otherwise hold 010 b ltckout output line is forced to 0 by an internal ltck event otherwise hold 011 b ltckout output line is forced to 1 by an internal ltck event otherwise hold 1xx b ltckout output line state is affected by an internal ltck event and/or by an operation occurred in an adjacent ltck cell (reported by m1i/m0i interface lines). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-260 v1.1, 2011-03 gpta ? v5, v1.0 oia 14 rw output immediate action 0 b no immediate action required. 1 b action defined by bit field ocm must be performed immediately. oia is always read as 0. out 15 rh output state 0 b ltckout output line is 0. 1 b ltckout output line is 1. gbyp 16 rw global bypass 0 b m3o/m2o lines are affected by m1i/m0i lines. 1 b m3o/m2o lines are affected by m3i/m2i lines. 0 [31:17] r reserved read as 0; should be written with 0. 1) to enable compare mode in all cases, sol and soh bits must be set to 1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-261 v1.1, 2011-03 gpta ? v5, v1.0 ltca2_ltcctr63 local timer cell control register 63 (3f8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 out 0 cen 0 ilm 0 fed red ren osm brm rh r rhrrw r rwrwrwrwrw field bits type description brm 0rw bit reversal mode control 0 b compare uses normal sequence of local input data bus (yi) bits. 1 b compare uses reversed sequence of local input data bus (yi) bits. osm 1rw one shot mode enable for shadow register copy 0 b shadow register copy is continuously enabled. 1 b shadow register copy is enabled for one event only. ren [3:2] rw request enable 00 b service request sqt63 is disabled. 01 b service request sqt63 is generated when a compare event has occurred. 10 b service request sqt63 is generated when a shadow register copy event has occurred. 11 b reserved. red 4rw rising edge select fo r shadow register copy 0 b shadow register copy is not triggered by a rising edge on the ltc63in input line. 1 b shadow register copy is triggered by a rising edge on the ltc63in input line. fed 5rw falling edge select for shadow register copy 0 b shadow register copy is not triggered by a falling edge on the ltc63in input line. 1 b shadow register copy is triggered by a falling edge on the ltc63in input line. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-262 v1.1, 2011-03 gpta ? v5, v1.0 ilm 8rw shadow register copy input line mode 0 b ltc63in is operating in edge sensitive mode. 1 b ltc63in is operating in level sensitive mode. cen 10 rh enable for shadow register copy 0 b shadow register copy is currently disabled. 1 b shadow register copy is currently enabled. out 15 rh output state 0 b ltc63out output line is 0. 1 b ltc63out output line is 1. 0 [7:6], 9, [14:11], [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-263 v1.1, 2011-03 gpta ? v5, v1.0 28.6.4 i/o sharing block registers the three registers mractl, mradin, and mradout are used to write data to and read data from the ltca multiplexer register array fifo. the multiplexer register array fifo controls the operation of the input/output line sharing block (see ?input/output line sharing block (iols)? on page 28-98 ). ltca2_ltcxrk (k = 00-62) local timer cell x register k (204 h +k*8 h ) reset value: 0000 0000 h 31 16 15 0 0x rrwh field bits type description x [15:0] rwh local timer data register value 0 [31:16] r reserved read as 0; should be written with 0. ltca2_ltcxr63 local timer cell x register 63 (3fc h ) reset value: 0000 0000 h 31 16 15 0 xs x rw rwh field bits type description x [15:0] rwh compare register value software write operations has priority above a simultaneous hardware update. xs [31:16] rw shadow register value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-264 v1.1, 2011-03 gpta ? v5, v1.0 the multiplexer register array control register controls the operation of the multiplexer register array fifo. ltca2_mractl multiplexer register array control register (038 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fifofillcnt 0 fifo ful l wcr es ma en rr r rwrw field bits type description maen 0rw multiplexer array enable bit field maen enables/disables the programming and the interconnections of the multiplexer array. 0 b multiplexer array is disabled; all cell inputs are driven with 0, ltca i/o lines (pins) are disconnected and fifo writing is enabled. 1 b multiplexer array is enabled; all cell and i/o line interconnections are established as previously programmed and fifo writing is disabled. wcres 1w write count reset writing wcres with 1 while the array is disabled (maen = 0), resets the write cycle counter to zero and the fifo written sequentially (initialized). wcres is always read as 0. fifofull 2r fifo full status 0 b fifo not completely written (write access to mradin allowed). 1 b fifo completely written (w rite access to mradin ignored). must be re-enabled via wcres before array can be re-initialized. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-265 v1.1, 2011-03 gpta ? v5, v1.0 fifofillcnt [13:8] r fifo fill count this bit field shows the current contents of the write cycle counter. 0 [7:3], [31:14] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-266 v1.1, 2011-03 gpta ? v5, v1.0 the multiplexer register array data in register is used to write data to the multiplexer register array fifo. the multiplexer register array data out register is used to read data from the multiplexer register array fifo. note: for correct operation, the mradin and mradin registers must be always read or written 32-bit wide. 8-bit and 16-bit accesses are ignored without any bus error! ltca2_mradin multiplexer register ar ray data in register (03c h ) reset value: 0000 0000 h 31 0 datain w field bits type description datain [31:0] w fifo write data this register contains the fifo write data as defined for the ltc output multiplexer control registers and the ltc input multiplexer control registers. ltca2_mradout multiplexer register ar ray data out register (040 h ) reset value: 0000 0000 h 31 0 dataout rh field bits type description dataout [31:0] rh fifo read data this register contains the fifo read data as assigned for the ltc output multiplexer control registers and the ltc input multiplexer control registers. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-267 v1.1, 2011-03 gpta ? v5, v1.0 28.6.5 multiplexer control registers these registers are not directly accessible and can be written and read only via the multiplexer register array fifo (see page 28-121 ). 28.6.5.1 output multiple xer control registers two registers, omcrl and omcrh, are assigned to each i/o group iog[3:0] and each output group og[3:0]. omcrl[3:0]/omcrh[3:0] are assigned to iog[3:0] and omcrl[13:10]/omcrh[13:10] are assigned to og[6:3]. omcrl controls the connections of group pins 0 to 3. omcrh controls the connections of group pins 4 to 7. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-268 v1.1, 2011-03 gpta ? v5, v1.0 ltca2_omcrlg (g = 0-3, 10-13) output multiplexer control register for lower half of pin group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0omg30oml30omg20oml2 rrwrrwrrwrrw 1514131211109876543210 0omg10oml10omg00oml0 rrwrrwrrwrrw field bits type description oml0, oml1, oml2, oml3 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a omg that can be selected by bit field omgn for omg output n. 000 b omg input in0 selected 001 b omg input in1 selected 010 b omg input in2 selected 011 b omg input in3 selected 100 b omg input in4 selected 101 b omg input in5 selected 110 b omg input in6 selected 111 b omg input in7 selected omg0, omg1, omg2, omg3 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the omgng which is connected to input n of i/o group g or output group g-7. x00 b omg2g selected x01 b omg1g selected all other combinations are reserved. if a reserved combination of omgn value is selected, the corresponding omg output is forced to 0 level. for compatibility reasons, the value 001 b (for xx1 b ) should be used for omgn bit field programming. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-269 v1.1, 2011-03 gpta ? v5, v1.0 ltca2_omcrhg (g = 0-3, 10-13) output multiplexer control register for upper half of pin group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0omg70oml70omg60oml6 rrwrrwrrwrrw 1514131211109876543210 0omg50oml50omg40oml4 rrwrrwrrwrrw field bits type description oml4, oml5, oml6, oml7 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a omg that can be selected by bit field omgn for omg output n. 000 b omg input in0 selected 001 b omg input in1 selected 010 b omg input in2 selected 011 b omg input in3 selected 100 b omg input in4 selected 101 b omg input in5 selected 110 b omg input in6 selected 111 b omg input in7 selected omg4, omg5, omg6, omg7 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the omgng which is connected to input n of i/o group g or output group g-7. x00 b omg2g selected x01 b omg1g selected all other combinations are reserved and if selected, the corresponding omg output is forced to 0 level. for compatibility reas ons, the value 001 b (for xx1 b ) should be used for omgn bit field programming. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-270 v1.1, 2011-03 gpta ? v5, v1.0 28.6.5.2 ltc input multiplexer control registers two registers, limcrl and limcrh, are assigned to each ltc group. limcrl controls the connections of ltc group cells with index 0 to 3. limcrh controls the connections of ltc group cells with index 4 to 7. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-271 v1.1, 2011-03 gpta ? v5, v1.0 ltca2_limcrlg (g = 0-7) input multiplexer control register for lower half of ltc group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lim en3 limg3 0 liml3 lim en2 limg2 0 liml2 rrwrrwrrwrrw 1514131211109876543210 lim en1 limg1 0 liml1 lim en0 limg0 0 liml0 rrwrrwrrwrrw field bits type description liml0, liml1, liml2, liml3 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a limg that can be selected by bit field limgn for limg output n. 000 b limg input in0 selected 001 b limg input in1 selected 010 b limg input in2 selected 011 b limg input in3 selected 100 b limg input in4 selected 101 b limg input in5 selected 110 b limg input in6 selected 111 b limg input in7 selected limg0, limg1, limg2, limg3 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the limgng which is connected to input n of ltc group g. 000 b limg0g selected 011 b limg3g selected 100 b limg4g selected all other combinations are reserved. if a reserved combination of limgn is selected, or if limenn = 0, the corresponding limg output is forced to 0 level. limen0, limen1, limen2, limen3 7, 15, 23, 31 rw enable multiplexer connection 0 b input n is not connected to any line. 1 b input n is connected to the line defined by limln and limgn. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-272 v1.1, 2011-03 gpta ? v5, v1.0 0 3, 11, 19, 27 r reserved read as 0; should be written with 0. ltca2_limcrhg (g = 0-7) input multiplexer control register for upper half of ltc group g reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lim en7 limg7 0 liml7 lim en6 limg6 0 liml6 rrwrrwrrwrrw 1514131211109876543210 lim en5 limg5 0 liml5 lim en4 limg4 0 liml4 rrwrrwrrwrrw field bits type description liml4, liml5, liml6, liml7 [2:0], [10:8], [18:16], [26:24] rw multiplexer line selection this bit field selects the input line of a limg that can be selected by bit field limgn for limg output n. 000 b limg input in0 selected 001 b limg input in1 selected 010 b limg input in2 selected 011 b limg input in3 selected 100 b limg input in4 selected 101 b limg input in5 selected 110 b limg input in6 selected 111 b limg input in7 selected limg4, limg5, limg6, limg7 [6:4], [14:12], [22:20], [30:28] rw multiplexer group selection this bit field determines the limgng which is connected to input n of ltc group g. 000 b limg0g selected 011 b limg3g selected 100 b limg4g selected all other combinations are reserved. if a reserved combination of limgn is selected, or if limenn = 0, the corresponding limg output is forced to 0 level. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-273 v1.1, 2011-03 gpta ? v5, v1.0 limen4, limen5, limen6, limen7 7, 15, 23, 31 rw enable multiplexer connection 0 b input n is not connected to any line. 1 b input n is connected to the line defined by limln and limgn. 0 3, 11, 19, 27 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-274 v1.1, 2011-03 gpta ? v5, v1.0 28.7 gpta ? v5 module implementation this section describes the gpta ? v5 interfaces as implemented in TC1798 with the clock control, port and micro second channel co nnections, interrupt control, and address decoding. 28.7.1 interconnections of gpta0/gpta1/ltca2 units the following items are described in this section: ?gpta ? v5 module (kernel) external registers ? port control and connections ? i/o port line assignment ? i/o function selection ? pad driver characteristics selection ? emergency control of gpta ? v5 outputs ? on-chip connections ? clock bus connections ? msc controller connections ? fadc connections ? multican, scu, and dma connections ? scu connections (adc, dma) ? module clock generation ? interrupt registers ?gpta ? v5 address map figure 28-93 shows the TC1798 specific implementation details and interconnections of the units gpta0/gpta1/ltca2.the units ar e supplied by clock control and address decoding logic. additional connections are described in the following sections. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-275 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-93 block diagram of gpta ? v5 implementation interrupt control clock control address decoder f gpta 1 f clc p0 .0 p0 .7 p3 .0 p3 .15 p4 .0 p4 .15 in[55:0] out[55:0] sr [37:00] in[55:0] out [111 :56] 56 in[31:0] out[31:0] out [111 :80] sr [37:00] sr [15:00] gt1xrun f gpta 0 gt0xrun f ltca2 out[111 :56] int[3:0] int[3:0] int[3:0] int[3:1] out[55:0] 2 8 clk[7:0] pll clocks 2 2 2 56 32 8 16 16 mcb05995_TC1798_ltca 64.vsd msc0 fadc multican adc0 adc1 dma adc2 9 7 16 9 3 4 msc1 16 16 16 8 8 56 32 32 32 54 32 asc 1 asc 0 in[1] 4 pdl [3 :0] ltc pre scu p1 .8 p1 .15 8 p2 .8 p2 .15 8 p5 .0 p5 .15 p8 .0 p8 .7 p9 .0 p9 .7 16 8 8 p13 .0 p13.15 16 p14 .0 p14.15 16 scu in[0] trig[15:0] trig[15:0] 56 56 32 gpta1 ltca2 port control io groups iog[6:0] output groups og[6:0] gpta0 scu (ext. request unit ) msc mux control output groups og[6:0] eray ecen www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-276 v1.1, 2011-03 gpta ? v5, v1.0 28.7.2 gpta ? v5 module external registers figure 28-94 summarizes the gpta ? v5 module related external registers that are required for gpta0/gpta1/ltca2 programming. these registers are referenced and (some of it) described in detail in the following sub-sections. figure 28-94 gpta ? v5 implementation-specific special function registers 28.7.3 port control and connections this section describes the i/o connections of the gpta0 unit. 28.7.3.1 i/o port line assignment in the TC1798, the seven i/o groups and seven output groups of gpta0 and gpta1 with their input lines in[55:0] and output lines out[111:0] are assigned to seven 8-bit port groups as shown in figure 28-95 . within an 8-bit i/o group, the in/out line with lowest index number is assigned to the port line with the lowest index number. the remaining lines are assigned linearly with in creasing index numbers. for example, p3.15 is assigned to in13/out13. in the TC1798, th e four i/o groups and seven output groups of ltca2 with their input lines in[31:0] and output lines out[56:0] are assigned to five 1) k = 0 , 4 2) k = 8 , 12 3) k = 0 , 4, 8, 12 4) k = 00 - 37 5) k = 00 - 15 register_TC1798 gpta0_clc clock control registers gpta0_fdr gpta0_edctr gpta0_dbgctr p0 _iocrk port control registers p1 _iocrk p2 _iocrk p3 _iocrk p4 _iocrk p0 _p dr p1 _p dr p2 _p dr p3 _p dr p4 _p dr p5 _e sr p8 _e sr p9 _e sr p13_esr p14_esr msc multiplexer control registers gpta0_srck interrupt registers gpta1_srck ltca2 _srck 1) 2) 2) 3) 3) 4) 4) 5) gpta0_mmxctr00 gpta0_mmxctr01 gpta0_mmxctr10 gpta0_mmxctr11 gpta0_id module identification registers p5 _iocrk 3) p8 _iocrk 1) p9 _iocrk 1) p13_iocrk 3) p14_iocrk 3) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-277 v1.1, 2011-03 gpta ? v5, v1.0 8-bit port groups therefore, the ltca does not have iog4, iog5, and iog6 and therefore it has no connection to port 8 or port 9 pins and only output connections to port 4, pins 15 down to 8. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-278 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-95 i/o port line assignment port control 8 og0 og0 og3 [63:56] [63:56] iog0 [7:0] [7:0] [7:0] [7:0] in[31:0](to ltca2) p0.[7:0] p2.[15:8] 8 out[55:0] (from gpta0) out[55:0] (from gpta1) in[55:0](to gpta0) [7:0] out[111:56] (from gpta1) out[111:80] (from ltca2) out[31:0] (from ltca2) out[111:56] (from gpta0) [87:80] 8 og1 og1 og4 [71:64] [71:64] p1.[15:8] [95:88] p3.[7:0] 8 [7:0] iog1 [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] p3.[15:8] 8 iog2 [23:16] [23:16] [23:16] [23:16] [23:16] [23:16] p4.[7:0] 8 iog3 [31:24] [31:24] [31:24] [31:24] [31:24] [31:24] p4.[15:8] 8 iog4 iog4 iog0 iog4 iog4 [39:32] [39:32] [7:0] [39:32] [39:32] 8 og2 og2 og5 [79:72] [79:72] p5.[7:0] [103:96] 8 og3 og3 [87:80] [87:80] p5.[15:8] p8.[7:0] 8 iog5 [47:40] [47:40] [47:40] [47:40] p9.[7:0] 8 iog6 [55:48] [55:48] [55:48] [55:48] 8 og4 og4 og3 [95:88] [95:88] p13.[7:0] [87:80] 8 og5 og5 og4 [103:96] [103:96] p13.[15:8] [95:88] 8 og5 og5 og5 [103:96] [103:96] p14.[7:0] [103:96] 8 og6 og6 og6 [111:104] [111:104] p14.[15:8] [111:104] in[55:0](to gpta1) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-279 v1.1, 2011-03 gpta ? v5, v1.0 the interconnections between the gpta0 unit and the port i/o lines are controlled in the port logics. the following port control operations selections must be executed: ? input/output function selection (iocr registers) ? pad driver characteristics sele ction for outputs (pdr registers) 28.7.3.2 input/output function selection table 28-26 shows the gpta0/gpta1/ltca2 i/o lines mapping to the ports. note that gpta0/gpta1/ltca2 input p2.8/in0 (see page 28-296 ) and gpta0/gpta1/ltca2 input p2.9/in1 (see page 28-296 ) has special connections. table 28-26 iocr assignment for gpta ? v5 port lines pg-lfbga 516 ports for gpta ? v5 gpta0 i/o lines gpta1 i/o lines ltca2 i/o lines input output input output input output p0.[3:0] out[59:56] out[59:56] out[83:80] p0.[7:4] out[63:60] out[63:60] p1.[11:8] out[67:64] 3) out[67:64] 3) out[91:88] 1) p1.[15:12] out[71:68] out[71:68] out[95:92] 2) p2.[11:8] in[3:0] 3) out[3:0] in[3:0] 4) out[3:0] in[3:0] 3) out[3:0] p2.[15:12] in[7:4] out[7:4] in[7:4] out[7:4] in[7:4] out[7:4] p3.[3:0] in[11:8] out[11:8] in[11:8] out[11:8] in[11:8] out[11:8] p3.[7:4] in[15:12] out[15:12] in[15:12] out[15:12] in[15:12] out[15:12] p3.[11:8] in[19:16] out[19:16] in[19:16] out[19:16] in[19:16] out[19:16] p3.[15:12] in[23:20] out[23:20] in[23:20] out[23:20] in[23:20] out[23:20] p4.[3:0] in[27:24] out[27:24] in[27:24] out[27:24] in[27:24] p4.[7:4] in[31:28] out[31:28] in[31:28] out[31:28] in[31:28] p4.[11:8] in[35:32] out[35:32] in[35:32] out[35:32] out[3:0] p4.[15:12] in[39:36] out[39:36] in[39:36] out[39:36] out[7:4] p5.[3:0] out[75:72] out[75:72] p5.[7:4] out[79:76] 5) out[79:76] 6) out[103:100 ] 7) p5.[11:8] out[83:80] p5.[15:12] out[87:84] out[87:84] p8.[3:0] in[43:40] out[43:40] 8) in[43:40] out[42] p8.[7:4] in[47:44] out[47:44] in[47:44] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-280 v1.1, 2011-03 gpta ? v5, v1.0 p9.[3:0] in[51:48] in[51:48] out[51:48] p9.[7:4] in[55:52] out[55:52] 9) in[55:52] out[53:52] p13.[3:0] out[91:88] out[91:88] out[83:80] p13.[7:4] out[95:92] out[95:92] out[87:84] p13.[11:8] out[99:96] out[99:96] out[91:88] p13.[15:12] out[103:100 ] out[103:100 ] out[95:92] p14.[3:0] out[99:96] out[99:96] p14.[7:4] out[103:100 ] out[103:100 ] p14.[11:8] out[107:104 ] p14.[15:12] out[111:108 ] 10) out[111:108 ] out[111:108 ] 1) out[89] is not available as output on a pin. 2) out[92] is not available as output on a pin. 3) there is a special connection provid ed for gpta0/gpta1 input line in0 (see page 28-296 ) and in1 (see page 28-296 ). 4) there is a special connection provid ed for gpta0/gpta1 input line in0 (see page 28-296 ) and in1 (see page 28-296 ). 5) out[78] is not available as output on a pin. 6) out[65], out[76], and out[78] are only as output of gpta0 available on a pin. 7) out[100], out[102] and out[103] are not connected to this port. 8) out[42] is not available as output on a pin. 9) out[52] and out[53] are not available as output on a pin. 10) out[108] and out[109] are not available as output on a pin. table 28-27 iocr assignment for gpta ? v5 port lines pg-lfbga 416 ports for gpta ? v5 gpta0 i/o lines gpta1 i/o lines ltca2 i/o lines input output input output input output p0.[3:0] out[59:56] out[59:56] out[83:80] p0.[7:4] out[63:60] out[63:60] table 28-26 iocr assignment for gpta ? v5 port lines (cont?d) pg-lfbga 516 ports for gpta ? v5 gpta0 i/o lines gpta1 i/o lines ltca2 i/o lines input output input output input output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-281 v1.1, 2011-03 gpta ? v5, v1.0 p1.[11:8] out[67:64] out[67:64] 1) out[91:88] 2) p1.[15:12] out[71:68] out[71:68] out[95:92] 3) p2.[11:8] in[3:0] 4) out[3:0] in[3:0] 5) out[3:0] in[3:0] 3) out[3:0] p2.[15:12] in[7:4] out[7:4] in[7:4] out[7:4] in[7:4] out[7:4] p3.[3:0] in[11:8] out[11:8] in[11:8] out[11:8] in[11:8] out[11:8] p3.[7:4] in[15:12] out[15:12] in[15:12] out[15:12] in[15:12] out[15:12] p3.[11:8] in[19:16] out[19:16] in[19:16] out[19:16] in[19:16] out[19:16] p3.[15:12] in[23:20] out[23:20] in[23:20] out[23:20] in[23:20] out[23:20] p4.[3:0] in[27:24] out[27:24] in[27:24] out[27:24] in[27:24] p4.[7:4] in[31:28] out[31:28] in[31:28] out[31:28] in[31:28] p4.[11:8] in[35:32] out[35:32] in[35:32] out[35:32] out[3:0] p4.[15:12] in[39:36] out[39:36] in[39:36] out[39:36] out[7:4] p5.[3:0] out[75:72] out[75:72] p5.[7:4] out[79:76] 6) out[79:76] 7) out[103:100 ] 8) p5.[11:8] out[83:80] p5.[15:12] out[87:84] out[87:84] p8.[3:0] in[43:40] out[43:40] 9) in[43:40] out[43:40] 10) p8.[7:4] in[47:44] out[47:44] in[47:44] out[45] p9.[3:0] in[51:48] in[51:48] out[51:48] p9.[7:4] in[55:52] out[55:52] 11) in[55:52] out[55:52] 12) p13.[3:0] out[91:88] out[91:88] out[83:80] p13.[7:4] out[95:92] out[95:92] out[87:84] p13.[11:8] out[99:96] out[99:96] out[91:88] p13.[15:12] out[103:100 ] out[103:100 ] out[95:92] p14.[3:0] out[99:96] out[99:96] table 28-27 iocr assignment for gpta ? v5 port lines (cont?d) pg-lfbga 416 ports for gpta ? v5 gpta0 i/o lines gpta1 i/o lines ltca2 i/o lines input output input output input output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-282 v1.1, 2011-03 gpta ? v5, v1.0 p14.[7:4] out[103:100 ] out[103:100 ] p14.[11:8] out[105] out[107:104 ] p14.[15:12] out[111:108 ] 13) out[111:108 ] out[111:108 ] 1) out[65] is not available on a pin. 2) out[89] is not available as output on a pin. 3) out[92] is not available as output on a pin. 4) there is a special connection provid ed for gpta0/gpta1 input line in0 (see page 28-296 ) and in1 (see page 28-296 ). 5) there is a special connection provid ed for gpta0/gpta1 input line in0 (see page 28-296 ) and in1 (see page 28-296 ). 6) out[78] is not available as output on a pin. 7) out[76], and out[78] are only as output of gpta0 available on a pin. 8) out[100], out[102] and out[103] are not connected to this port. 9) out[42] is not available as output on a pin. 10) out[40] and out[41] are not available on a pin. 11) out[52] and out[53] are not available as output on a pin. 12) out[54] and out[55] are not available on a pin. 13) out[108] and out[109] are not available as output on a pin. table 28-28 iocr assignment for gpta ? v5 port lines pg-lfbga 292 ports for gpta ? v5 gpta0 i/o lines gpta1 i/o lines ltca2 i/o lines input output input output input output p0.[3:0] out[59:56] out[59:56] out[83:80] p0.[7:4] out[63:60] out[63:60] p1.9 out[65] p1.12 out[68] out[68] p2.8 in[0] 1) out[0] in[0] 2) out[0] in[0] out[0] p2.10 in[2] out[2] in[2] out[2] in[2] out[2] p2.12 in[4] out[4] in[4] out[4] in[4] out[4] table 28-27 iocr assignment for gpta ? v5 port lines (cont?d) pg-lfbga 416 ports for gpta ? v5 gpta0 i/o lines gpta1 i/o lines ltca2 i/o lines input output input output input output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-283 v1.1, 2011-03 gpta ? v5, v1.0 p2.10 in[6] out[6] in[6] out[6] in[6] out[6] p3.0 in[8] out[8] in[8] out[8] in[8] out[8] p3.2 in[10] out[10] in[10] out[10] in[10] out[10] p3.4 in[12] out[12] in[12] out[12] in[12] out[12] p3.6 in[14] out[14] in[14] out[14] in[14] out[14] p3.8 in[16] out[16] in[16] out[16] in[16] out[16] p3.10 in[18] out[18] in[18] out[18] in[18] out[18] p3.12 in[20] out[20] in[20] out[20] in[20] out[20] p3.14 in[22] out[22] in[22] out[22] in[22] out[22] p4.[3:0] in[27:24] out[27:24] in[27:24] out[27:24] in[27:24] p4.[7:4] in[31:28] out[31:28] in[31:28] out[31:28] in[31:28] p4.[10:8] in[34:32] out[34:32] in[34:32] out[34:32] out[2:0] p4.12 in[36] out[36] in[36] out[36] out[4] p4.14 in[38] out[38] in[38] out[38] out[6] p5.[3:0] out[75:72] out[75:72] p5.[7:4] out[79:76] 3) out[79:76] 4) out[103:100 ] 5) p5.[11:8] out[83:80] p8.[3:0] in[43:40] out[43:40] 6) in[43:40] out[42] p8.[7:4] in[47:44] out[47:44] in[47:44] p9.[3:0] in[51:48] in[51:48] out[51:48] p9.[7:4] in[55:52] out[55:52] 7) in[55:52] out[53:52] p13.0 out[91:88] out[91:88] out[83:80] p13.[7:4] out[95:92] out[95:92] out[87:84] p13.[11:8] out[99:96] out[99:96] out[91:88] p13.[15:12] out[103:100 ] out[103:100 ] out[95:92] p14.0 out[96] out[96] p14.2 out[98] out[98] table 28-28 iocr assignment for gpta ? v5 port lines (cont?d) pg-lfbga 292 ports for gpta ? v5 gpta0 i/o lines gpta1 i/o lines ltca2 i/o lines input output input output input output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-284 v1.1, 2011-03 gpta ? v5, v1.0 a port line that is programmed as input can be used by the gpta0 or other units simultaneously as input. port lines selected as gpta0/gpta1/ltca2 output are forced to a 0 level if the related multiplexer array in the i/o line sharing block is disabled or if a reserved combination of an omgn value is selected. therefore, no glitches and spikes can occur during the programming of the related multiplexer array. 28.7.3.3 emergency control of gpta ? v5 output ports lines port lines connected to gpta0/gpta1/ltca2 unit output pins can be selectively switched into an emergency mode. in this mode, gpta0/gpta1/ltca2 unit output pins react immediately to an active input signal p10.1 (hwcfg1) and drive a logic level that has been programmed in the port output regi ster. as a result, in emergency mode a gpta0/gpta1/ltca2 unit output pin drives a predefined value instead of the corresponding logic level that is provided on the related gpta0/gpta1/ltca2 unit output line. all gpta ? v5 pins at port 0, port 1, port 2, port 3, port 4, port 8, port 9, port 13, and port 14 are connected to one common emergency stop signal that is generated in the system control unit of the TC1798. more details about the generation of this emergency stop signal are described in the ?system control unit? chapter of the TC1798 system units users manual. the emergency stop signal always controls 8-bit groups of port lines. the enable function is controlled for each pin by bits eny (y = number of port line) which are located in the px_esr (x = port number) registers. when the emergency stop signal generated in the scu becomes active and bit px_esr.eny set, output line px.y is set to the value p14.4 out[100] out[100] p14.6 out[102] out[102] p14.8 out[104] 1) there is a special connection provided for gpta0/gpta1 input line in0 (see page 28-296 ). 2) there is a special connection provided for gpta0/gpta1 input line in0 (see page 28-296 ). 3) out[78] is not available as output on a pin. 4) out[65], out[76], and out[78] are only as output of gpta0 available on a pin. 5) out[100], out[102] and out[103] are not connected to this port. 6) out[42] is not available as output on a pin. 7) out[52] and out[53] are not available as output on a pin. table 28-28 iocr assignment for gpta ? v5 port lines (cont?d) pg-lfbga 292 ports for gpta ? v5 gpta0 i/o lines gpta1 i/o lines ltca2 i/o lines input output input output input output www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-285 v1.1, 2011-03 gpta ? v5, v1.0 of register px_out.py (emergency enabled). output px.y is not affected by the emergency stop signal when bit px_out.py is reset (emergency disabled). when the emergency stop signal is released, pi n x.y is switched back to the previously selected gpta ? v5 output function without reprogramming the related port registers. table 28-29 emergency control for gpta ? v5 port output lines port esr register esr enable bits gpta ? v5 output lines ltca output lines port 0 p0_esr en[7:0] out[63:56] out[87:80] port 1 p1_esr en[15:8] out[71:64] out[95:88] port 2 p2_esr en[15:8] out[7:0] out[7:0] port 3 p3_esr en[15:0] out[23:8] out[23:8] port 4 p4_esr en[15:0] out[39:24] out[31:24], out[7:0] port 5 p5_esr en[15:0] out[87:72] out[111:96] port 8 p8_esr en[7:0] out[47:40] port 9 p9_esr en[7:0] out[55:48] port 13 p13_esr en[15:0] out[103:88] out[95:80] port 14 p14_esr en[15:0] out[111:96] out[111:96] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-286 v1.1, 2011-03 gpta ? v5, v1.0 28.7.4 on-chip connections this section describes all on-chip interconnections of the gpta0/gpta1/ltca2 units except the connections to i/o ports (see section 28.7.3 ). 28.7.4.1 clock bus connections the clock bus signals generated in the gpta0 and gpta1 clock distribution cells and pll clocks are interconnected between th e gpta0/gpta1/ltca2 units as shown in figure 28-96 . the gpta0 clock bus drives global timers (g ts), global timer cells (gtcs), and local timer cells (ltcs) of the gpta0 unit and the ltcs of the ltca2 unit. the gpta1 clock bus drives its gts, gtcs, and ltcs. each gpta0 and gpta1 clock distribution cells has two pairs for pll clock inputs, an input pair for the local pll clocks and an in put pair for unit-external pll clocks. the gpta0 and gpta1 units are capable to use the pll clocks from each other. figure 28-96 clock bus connections of gpta0/gpta1/ltca2 mca05998_ltca2 pll clock distribution unit ltcs gtcs gts pll clock distribution unit ltcs gtcs gts gpta0 gpta1 clock bus clock bus 9 9 ltca2 ltcs pdl 4 pdl 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-287 v1.1, 2011-03 gpta ? v5, v1.0 28.7.4.2 msc controller connections the msc interfaces (msc0 and msc1) provide a serial communication link typically used to connect power switches or other peripheral devices. each output multiplexers of gpta0/gpta1 generate 7 8 = 56 output lines out[111:56] grouped into seven output groups. each output multiplexers of ltca2 generate 4 8 = 32 output lines out[111:80] grouped into four output groups. all these output lines are wired to 32 msc0 inputs. up to 32 msc0 and 24 msc1 output extension lines (bits) can be connected to the gpta ? v5. figure 28-97 shows the interconnections among the msc0/1 modules and the gpta ? v5 units. the source for each line of the altinl/altinh msc input buses can be selected via a multiplexer connected either to gpta0 output outx(x = 56-111), gpta1 ou tput outx(x = 56-111), ltca2 output outx(x = 80-111). figure 28-97 gpta ? v5-to-msc multiplexer og3 of gpta0 msc0 og3 of gpta1 og3 of ltca2 altinl[7:0] mux altinl[15:8] mu x altinh[7:0] mux altinh[15:8] mux altinl[7:0] mux altinl[15:8] mux altinh[7:0] mu x msc1 mmxctr10 out[87:80] out[87:80] out[87:80] og4 of gpta0 og4 of gpta1 og4 of ltca2 out[95:88] out[95:88] out[95:88] og5 of gpta0 og5 of gpta1 og5 of ltca2 out[103:96] out[103:96] out[103:96] og6 of gpta0 og6 of gpta1 og6 of ltca2 out[111:104] out[111:104] out[111:104] og0 of gpta0 og0 of gpta1 og3 of ltca2 out[63:56] out[63:56] out[87:80] og1 of gpta0 og1 of gpta1 og4 of ltca2 out[71:64] out[71:64] out[95:88] og2 of gpta0 og2 of gpta1 og5 of ltca2 out[79:72] out[79:72] out[103:96] mmxctr01 mmxctr11 mmxctr00 altinl[7:0] altinl[15:8] altinh[7:0] altinl[7:0] altinl[15:8] altinh[7:0] altinh[15:8] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-288 v1.1, 2011-03 gpta ? v5, v1.0 the multiplexer selection is controlled by four multiplexer control registers that are logically assigned to the gpta0 unit address range (but described in this section). note: note that eight altinh inputs (altinh[15:8]) of the msc1 module are not connected. table 28-30 and table 28-31 shows the gpta ? v5-to-msc interconnection assignment. note: table 28-30 and table 28-31 also shows the assignment of the gpta0/gpta1/ltca2 unit?s seven ogx out put group lines ogx.y to the output signals out[111:56]. table 28-30 gpta0/gpta1/ltca2 to msc0 interconnection assignment msc0 input line assigned gpta0/ gpta1 output line assigned ltca2 output line msc0 input line assigned gpta0/gp ta1 output line assigned ltca2 output line altinl.0 out56 / og0.0 out80 / og3.0 altinh.0 out72 / og2.0 out96 / og5.0 altinl.1 out57 / og0.1 out81 / og3.1 altinh.1 out73 / og2.1 out97 / og5.1 altinl.2 out58 / og0.2 out82 / og3.2 altinh.2 out74 / og2.2 out98 / og5.2 altinl.3 out59 / og0.3 out83 / og3.3 altinh.3 out75 / og2.3 out99 / og5.3 altinl.4 out60 / og0.4 out84 / og3.4 altinh.4 out76 / og2.4 out100 / og5.4 altinl.5 out61 / og0.5 out85 / og3.5 altinh.5 out77 / og2.5 out101 / og5.5 altinl.6 out62 / og0.6 out86 / og3.6 altinh.6 out78 / og2.6 out102 / og5.6 altinl.7 out63 / og0.7 out87 / og3.7 altinh.7 out79 / og2.7 out103 / og5.7 altinl.8 out64 / og1.0 out88 / og4.0 altinh.8 out80 / og3.0 out104 / og6.0 altinl.9 out65 / og1.1 out89 / og4.1 altinh.9 out81 / og3.1 out105 / og6.1 altinl.10 out66 / og1.2 out90 / og4.2 altinh.10 out82 / og3.2 out106 / og6.2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-289 v1.1, 2011-03 gpta ? v5, v1.0 altinl.11 out67 / og1.3 out91 / og4.3 altinh.11 out83 / og3.3 out107 / og6.3 altinl.12 out68 / og1.4 out92 / og4.4 altinh.12 out84 / og3.4 out108 / og6.4 altinl.13 out69 / og1.5 out93 / og4.5 altinh.13 out85 / og3.5 out109 / og6.5 altinl.14 out70 / og1.6 out94 / og5.0 altinh.14 out86 / og3.6 out110 / og6.6 altinl.15 out71 / og1.7 out95 / og5.1 altinh.15 out87 / og3.7 out111 / og6.7 table 28-31 gpta0/gpta1/ltca2 to msc1 interconnection assignment msc1 input line assigned gpta0/ gpta1/ltca2 output line msc1 input line assigned gpta0/ gpta1/ltca2 output line altinl.0 out88 / og4.0 altinh.0 out104 / og6.0 altinl.1 out89 / og4.1 altinh.1 out105 / og6.1 altinl.2 out90 / og4.2 altinh.2 out106 / og6.2 altinl.3 out91 / og4.3 altinh.3 out107 / og6.3 altinl.4 out92 / og4.4 altinh.4 out108 / og6.4 altinl.5 out93 / og4.5 altinh.5 out109 / og6.5 altinl.6 out94 / og4.6 altinh.6 out110 / og6.6 altinl.7 out95 / og4.7 altinh.7 out111 / og6.7 altinl.8 out96 / og5.0 altinh.8 altinl.9 out97 / og5.1 altinh.9 altinl.10 out98 / og5.2 altinh.10 altinl.11 out99 / og5.3 altinh.11 altinl.12 out100 / og5.4 altinh.12 altinl.13 out101 / og5.5 altinh.13 table 28-30 gpta0/gpta1/ltca2 to msc0 interconnection assignment (cont?d) msc0 input line assigned gpta0/ gpta1 output line assigned ltca2 output line msc0 input line assigned gpta0/gp ta1 output line assigned ltca2 output line www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-290 v1.1, 2011-03 gpta ? v5, v1.0 gpta ? v5-to-msc multiplexer control registers the following registers are required for gpta ? v5-to-msc multiplexer control: ? gpta0_mmxctr00 controls the interconnections of gpta ? v5 units to the msc0 altinh[15:8] and msc1 altinl[7:0] inputs. ? gpta0_mmxctr01 controls the interconnections of gpta ? v5 units to the msc0 altinh[15:0] inputs. msc1 altinl[15:8] inputs and msc1 altinh[7:0] inputs. ? gpta0_mmxctr10 controls the interconnections of gpta ? v5 units to the msc0 altinl[15:0] inputs. ? gpta0_mmxctr11 controls the interconnections of gpta ? v5 units to the msc0 altinh[7:0] inputs. for each of the altinl/altinh inputs of the msc, the 2-bit bit fields in these registers determine which unit output is selected. altinl.14 out102 / og5.6 altinh.14 altinl.15 out103 / og5.7 altinh.15 table 28-31 gpta0/gpta1/ltca2 to msc1 interconnection assignment (cont?d) msc1 input line assigned gpta0/ gpta1/ltca2 output line msc1 input line assigned gpta0/ gpta1/ltca2 output line www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-291 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_mmxctr00 gpta-to-msc multiplexer control register 00 (700 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 mux 15 mux 14 mux 13 mux 12 mux 11 mux 10 mux 9 mux 8 mux 7 mux 6 mux 5 mux 4 mux 3 mux 2 mux 1 mux 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description muxn (n = 0-7) [2*n+1:2*n] rw multiplexer control for msc0 inputs altinh.(n+8) 00 b gpta0 output out[80+n] selected and connected to msc0 altinh.(n+8) 01 b gpta1 output out[80+n] selected and connected to msc0 altinh.(n+8) 10 b ltca2 output out[80+n] selected and connected to msc0 altinh.(n+8) 11 b reserved muxn (n = 8-15) [2*n+1:2*n] rw multiplexer control for msc1 inputs altinl(n-8) 00 b gpta0 output out[80+n] selected and connected to altinl.(n-8) 01 b gpta1 output out[80+n] selected and connected to msc1 altinl.(n-8) 10 b ltca2 output out[80+n] selected and connected to msc1 altinl.(n-8) 11 b reserved gpta0_mmxctr01 gpta-to-msc multiplexer control register 01 (704 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 mux 15 mux 14 mux 13 mux 12 mux 11 mux 10 mux 9 mux 8 mux 7 mux 6 mux 5 mux 4 mux 3 mux 2 mux 1 mux 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-292 v1.1, 2011-03 gpta ? v5, v1.0 field bits type description muxn (n = 0-7) [2*n+1:2*n] rw multiplexer control for msc1 inputs altinl.(n+8) 00 b gpta0 output out[96+n] selected and connected to msc1 altinl.(n+8) 01 b gpta1 output out[96+n] selected and connected to msc1 altinl.(n+8) 10 b ltca2 output out[96+n] selected and connected to msc1 altinl.(n+8) 11 b reserved muxn (n = 8-15) [2*n+1:2*n] rw multiplexer control for msc1 inputs altinh.(n-8) 00 b gpta0 output out[96+n] selected and connected to msc1 altinh.(n-8) 01 b gpta1 output out[96+n] selected and connected to msc1 altinh.(n-8) 10 b ltca2 output out[96+n] selected and connected to msc1 altinh.(n-8) 11 b reserved gpta0_mmxctr10 gpta-to-msc multiplexer control register 10 (708 h ) reset value: 0000 0000 h 313029282726252423222120191817161514131211109876543210 mux 15 mux 14 mux 13 mux 12 mux 11 mux 10 mux 9 mux 8 mux 7 mux 6 mux 5 mux 4 mux 3 mux 2 mux 1 mux 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description muxn (n = 0-15) [2*n+1:2*n] rw multiplexer control for msc0 inputs altinl.n 00 b gpta0 output out[56+n] selected and connected to msc0 altinl.n 01 b gpta1 output out[56+n] selected and connected to msc0 altinl.n 10 b ltca2 output out[80+n] selected and connected to msc0 altinl.n 11 b reserved www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-293 v1.1, 2011-03 gpta ? v5, v1.0 gpta0_mmxctr11 gpta-to-msc multiplexer control register 11 (70c h ) reset value: 0000 0000 h 31 161514131211109876543210 0 mux 7 mux 6 mux 5 mux 4 mux 3 mux 2 mux 1 mux 0 r rwrwrwrwrwrwrwrw field bits type description muxn (n = 0-7) [2*n+1:2*n] rw multiplexer control for msc0 inputs altinh.n 00 b gpta0 output out[72+n] selected and connected to msc0 altinh.n 01 b gpta1 output out[72+n] selected and connected to msc0 altinh.n 10 b ltca2 output out[96+n] selected and connected to msc0 altinh.n 11 b reserved 0 [31:15] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-294 v1.1, 2011-03 gpta ? v5, v1.0 28.7.4.3 connections to scu, multican, fadc, dma, ports the gpta0/gpta1/ltca2 units of the TC1798 gpta ? v5 module have several on-chip interconnections with the scu, multican, fadc, dma modules. figure 28-98 shows these interconnections. figure 28-98 connections of gpta ? v5 with on-chip modules gpta0 external request unit (scu) gpta1 interrupt node multican sr15 clock generation fadc trig01 trig03 trig05 trig07 int1 int2 int3 int1 int2 int3 int0 int0 trig15 trig17 trig00 trig02 trig04 trig06 trig11 trig13 in02 in12 in22 in32 gsg gsh tse tsf tsg tsh gse gsf dma trig0k (k=7-0) ch0kreqi09 trig1k (k=7-0) ch0kreqi10 trig0k (k=7-0) ch1kreqi09 trig1k (k=7-0) ch1kreqi10 adc2 trig10 reqgtk_0 (k=4-0) trig12 reqgtk_1 (k=4-0) trig14 reqgtk_2 (k=4-0) trig05 trig16 trig00 reqtr1_0 reqtrk_2 (k=3-1) reqtr3_0 reqtr4_0 reqtr0_0 trig15 adc0 reqgtk_0 (k=4-0) reqgtk_1 (k=4-0) reqgtk_2 (k=4-0) reqtrk_2 (k=3-1) reqtr0_0 trig03 trig11 reqtr1_0 reqtr3_0 reqtr4_0 trig07 iout0 interrupt node iout1 iout2 iout3 ltca2 int1 int2 int3 int0 reqtr2_0 reqgtk_0 (k=4-0) reqgtk_1 (k=4-0) reqgtk_2 (k=4-0) reqtrk_2 (k=3-1) reqtr0_0 reqtr3_0 trig01 trig13 reqtr4_0 trig14 reqtr1_0 adc1 trig06 reqtr2_0 trig04 reqtr2_0 in1 in1 gptais p2.9 / in1 p5.0 / asc0:rxd0a p6.8 / asc0:rxd0b p6.10 / asc1:rxd1b m u x scu_syscon gptainsel p2.8 extclk0 m u x scu_extcon in0 in0 in1 in0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-295 v1.1, 2011-03 gpta ? v5, v1.0 system control unit the scu contains the external request unit (eru), which is especially responsible for controlling requests coming from the msc modules, port pins, or from the gpta0/gpta1/ltca2 unit and passing these request to ad converters, dma controller, eray communication controller or interrupt nodes. multican connections the multican controller has the following connections to the gpta0/gpta1/ltca2 unit: ? multican service request output sr15 is connected to the int0 input of gpta0/gpta1/ltca2. ? gpta0 output line out5 is connected to t he external time trigger input ectt3 of the multican module. dma controller as shown in figure 28-98 , eight gpta0 on-chip trigger and gating output lines are connected as trigger input signals to the dma request inputs. furthermore the external request unit generates four dma request output signals (iout[3:0]) that can be activated via port pins, the msc clock outputs, or the four gpta ? v5 output lines. three of these four dma request output signals are conn ected to the gpta0/gpta1/ltca2 internal inputs int[3:1]. these connections allow, for example, gtc or ltc events in the gpta ? v5 units to be triggered by a request coming from a port pin or from the msc clock. adc connections as shown in figure 28-98 , for each adc nine gpta0 on-chip trigger and gating output lines are connected as trigger input signals or gating input signals to the channel trigger logic of the adc. thus dedicated gpta0 out puts can generate trigger events or act as gating signals for adc channels. furthermore the external request unit generates two adc conversion trigger signals (iout[3:2] ) and two adc conversion gating signals (pdout[3:2]) that can be activated each via port pins, the msc clock outputs, or two gpta ? v5 output lines. fadc connections as shown in figure 28-98 , eight gpta0 on-chip trigger and gating output lines are connected as trigger input signals or gating input signals to the channel trigger logic of the fadc. thus dedicated gpta0 outputs can generate trigger events or act as gating signals for fadc channels. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-296 v1.1, 2011-03 gpta ? v5, v1.0 port connections of input in0 the common input line in0 of the gpta0/gpta1/ltca2 unit is connected to the output of a 2-to-1 multiplexer. this mult iplexer is controlled by bit field scu_extcon.gptainsel and allows the common gpta0/gpta1/ltca2 input in0 to be connected to one out of two input lines. this feature especially allows the number of clock of the pll (to determine clock stability) to be measured by gts (global timers) or fpc0 (filter and prescaler cell) of the gpta0/gpta1. port connections of input in1 the common input line in1 of the gpta0/gpta1/ltca2 unit is connected to the output of a 4-to-1 multiplexe r. this multiplexer is controlle d by bit field scu_syscon.gptais and allows the common gpta0/gpta1/ltca2 input in1 to be connected to one out of four port input lines. this feature especially allows the baud rates of an asc0 or asc1 receiver input signal to be measured by timers of the gpta0/gpta1/ltca2. 28.7.5 module clock generation as shown in figure 28-99 , the clock signals for the gpta0/gpta1/ltca2 units are generated and controlled by one clock generation circuitry. this clock generation circuitry is responsible for the enable/disable control, the clock frequency adjustment, and the debug clock control. the circuitry includes the following registers: ? clock control register gpta0_clc (see page 28-300 ), responsible for the generation of the control clock f clc that is used by each of the units. ? fractional divider register gpta0_fdr (see page 28-301 ), responsible for the frequency control of the module timer clock f gpta . table 28-32 gpta0 input line in0 connections scu_extcon. gptainsel gpta0/gpta 1/ltca2 input in0 connected to 00 b p2.9 / in0 (default after reset) 01 b scu: extclk0 table 28-33 gpta0 input line in1 connections scu_syscon. gptais gpta0/gpta1/ ltca2 input in1 connected to 00 b p2.9 / in1 (default after reset) 01 b p5.0 / asc0: rxd0a 10 b p6.8 asc0: rxd0b 11 b p6.10 / asc1: rxd1b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-297 v1.1, 2011-03 gpta ? v5, v1.0 ? clock enable/disable control register gpta0_edctr (see page 28-303 ), responsible for the enable/disable control of the different units as clocks f gpta0 , /f gpta1 / f ltca2 , and for the run control for the global timers in gpta0 and gpta1. ? debug clock control re gister gpta0_dbgctr (see page 28-305 ), responsible for the module timer clock control in debug mode. figure 28-99 gpta ? v5 clock generation for the units note: registers gpta0_clc, gpta0_ fdr, gpta0_edctr and gpta0_dbgctr are located in the address space of gpta0. mca06001 clock control register gpta0_clc f clc fractional divider register gpta0_fdr clock generation unit for gpta modules clock enable /disable control register gpta0_edctr f gpta f gpta0 f gpta1 f ltca2 gpta0 kernel f fpi gpta1 kernel ltca 2 kernel gt00run gt01run gt10run gt11run (used for control tasks and register accesses ) debug clock control register gpta0_dbgctr multican module sr15 ecen int0 int0 int0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-298 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-100details on module clock generation the gpta ? v5 module control clock f clc is used inside the gpta ? v5 module kernels for control purposes such as clocking of control logic and register operations. the frequency of f clc is identical to the clock frequency f fpi . the clock control registers gpta0_clc make it possible to enable/disable f clc under certain conditions. the separate gpta ? v5 unit clocks f gpta0 , f gpta1 , f ltca2 are used inside the gpta ? v5 units as input clocks for the timers. all unit clocks have the same frequency as f gpta (as selected through register gpta0_fdr) and can be enabled/disabled separately each through register gpta0_ecdtr. note: if f gpta0 , f gpta1 , f ltca2 are disabled by the enable bits in register gpta0_ecdtr, f clc keeps running. in this case, that means that register accesses to the gpta ? v5 units are possible. the frequency of f gpta is defined by: (28.6) (28.7) note: the upper formula applies to normal divider mode of the fractional divider (gpta0_fdr.dm = 01 b ). the lower formula applies to fractional divider mode (gpta0_fdr.dm = 10 b ). the debug clock control register additionally makes it possible to control the timer clocks f gpta0 , f gpta1 , f ltca2 for debug purposes on basis of a clock counter. mca05603 f fpi clock control register (module clock ) sleep mode request suspend request fast shut-off request f clc fractional divider register & control module clock generation (clc clock ) spnd reset external divider moddisreq disable req. disable ack. spndack f mod f clc kernel disable request kernel disable acknowledge f gpta f fpi 1 n -- - with n = 1024 - fdr.step or = f gpta f fpi n 1024 ------------ - with n = 0-1023 = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-299 v1.1, 2011-03 gpta ? v5, v1.0 if the debug clock feature is enabled (gpta0_dbgctr.dbgcen = 1) and bit gpta0_dbgctr.dbgcst is set, the timer clocks f gpta0 , f gpta1 , f ltca2 will be activated in parallel for as many clock cycles as have been programmed into bit field gpta0_dbgctr.clkcnt. when the debug cl ock feature becomes enabled, bit field clkcnt counts down and stops counting at 0000 h . bit dbgcst is again reset by hardware after the programmed number of clock pulses has been issued. this feature makes it possible to single step the gpta ? v5 units with a programmable timer clock granularity. note: the gpta ? v5 module is disabled after reset. in general, after reset, the gpta ? v5 module control clock f clc must be switched on (writing to register gpta0_clc) before the frequency of the gpta ? v5 module timer clock f gpta is defined (writing to register gpta0_fdr). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-300 v1.1, 2011-03 gpta ? v5, v1.0 28.7.5.1 clock control registers the clock control register makes it possible to control (enable/disable) the gpta ? v5 module control clock f clc . the clock signal f clc is used by the gpta0/gpta1/ltca2 as a clock for internal control operations but not for timer purposes. note: after a hardware reset operation, the f clc clock is disabled (diss set). therefore, the gpta ? v5 module clock generation is completely disabled. note: in disabled state, no registers of gpta ? v5 module can be read or written except the gpta_clc register. gpta0_clc gpta clock control register (000 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we e dis sp en dis s dis r r rwwrwrw r rw field bits type description disr 0rw gpta ? v5 module disable request bit used for enable/disable control of the gpta ? v5 module. diss 1r gpta ? v5 module disable status bit bit indicates the current status of the gpta ? v5 module. spen 2rw gpta ? v5 module suspend enable for ocds used to enable the suspend mode. edis 3rw external request disable used to control the external clock disable request. sbwe 4w gpta ? v5 module suspend bit write enable for ocds determines whethe r spen and fsoe are write-protected. fsoe 5rw fast switch off enable used for fast clock switch off in suspend mode. 0 [31:6] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-301 v1.1, 2011-03 gpta ? v5, v1.0 28.7.5.2 fractional divider register the fractional divider makes it possible to generate a gpta ? v5 module clock from an input clock using a programmable divider. the fractional divider divides the input clock f clc either by the factor 1/n or by a fraction of n/1024 for any value of n from 0 to 1023, and outputs the clock signal, f gpta . the fractional divider is controlled by the fdr register. the fractional divider r egister controls the clock frequency of the gpta ? v5 module timer clock f gpta . the clock frequency of f gpta0 , f gpta1 , f ltca2 is identical to the one of f gpta . gpta0_fdr gpta fractional divider register (00c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dis clk en hw sus req sus ack 0result rwh rw rh rh r rh 1514131211109876543210 dm sc sm fdis step rw rw rw rw rw field bits type description step [9:0] rw step value reload or addition value for result. fdis 10 rw freeze disable this bit controls the freeze function for this module. 0 b module operates on corrected clock, with reduced modulation jitter 1 b module operates on uncorrected clock with full modulation jitter sm 11 rw suspend mode sm selects between granted or immediate suspend mode. sc [13:12] rw suspend control this bit field determines the behavior of the fractional divider in suspend mode. dm [15:14] rw divider mode this bit field selects normal divider mode, fractional divider mode, and off-state. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-302 v1.1, 2011-03 gpta ? v5, v1.0 result [25:16] rh result value bit field for the addition result. susack 28 rh suspend mode acknowledge indicates state of spndack signal. susreq 29 rh suspend mode request indicates state of spnd signal. enhw 30 rw enable hardware clock control controls operation of ecen input and disclk bit. disclk 31 rwh disable clock hardware controlled disable for f out signal. 0 [27:26] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-303 v1.1, 2011-03 gpta ? v5, v1.0 the clock enable/disable control register controls two functions: clock enable/disable control for each global timer in the gpta0/gpta1 units and enable/disable control for the gpta ? v5 unit clocks, separa tely for each clock f gpta0 , f gpta1 , f ltca2 . gpta0_edctr gpta clock enable/disable control register (400 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 l2 en g1 en g0 en 0 gt 11 run gt 10 run gt 01 run gt 00 run r rw rw rw r rw rw rw rw field bits type description gt00run 0rw gpta0 global timer 0 run control 0 b gpta0 global timer 0 clock is stopped. 1 b gpta0 global timer 0 clock is started/running. gt01run 1rw gpta0 global timer 1 run control 0 b gpta0 global timer 1 clock is stopped. 1 b gpta0 global timer 1 clock is started/running. gt10run 2rw gpta1 global timer 0 run control 0 b gpta1 global timer 0 clock is stopped. 1 b gpta1 global timer 0 clock is started/running. gt11run 3rw gpta1 global timer 1 run control 0 b gpta1 global timer 1 clock is stopped. 1 b gpta1 global timer 1 clock is started/running. g0en 8rw gpta0 timer clock enable 0 b gpta0 timer clock f gpta0 is disabled. 1 b gpta0 timer clock f gpta0 is enabled. g1en 9rw gpta1 timer clock enable 0 b gpta1 timer clock f gpta1 is disabled. 1 b gpta1 timer clock f gpta1 is enabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-304 v1.1, 2011-03 gpta ? v5, v1.0 l2en 10 rw ltca2 timer clock enable 0 b ltca2 timer clock f ltca2 is disabled. 1 b ltca2 timer clock f ltca2 is enabled. 0 [7:4], [31:11] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-305 v1.1, 2011-03 gpta ? v5, v1.0 the debug clock control register makes it possible to control the gpta ? v5 unit clocks f gpta0 , f gpta1 , f ltca2 for debug purposes on the basis of a clock counter. gpta0_dbgctr gpta debug clock control register (004 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dbg cen 0 rw r 1514131211109876543210 clkcnt rwh field bits type description clkcnt [15:0] rwh debug clock count this bit field determines the number of clock pulses to be issued when the debug clock feature is enabled (dbgcen = 1). clkcnt counts down to 0000 h and stops when the debug clock feature is enabled. dbgcen 31 rw debug clock enable 0 b the debug clock feature is disabled. the gpta ? v5 unit clocks are always enabled. 1 b the debug clock feature is enabled. if a non-zero value is written to bit field clkcnt the related number of clock pulses is issued at f gpta0 , f gpta1 , f ltca2 . 0 [30:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-306 v1.1, 2011-03 gpta ? v5, v1.0 28.7.6 limits of cascading gtcs and ltcs as shown on page 28-57 and page 28-69 , a maximum of 32 gtcs and a maximum of 64 ltcs can be cascaded. in the TC1798, however cascading of gtcs and ltcs is limited under cert ain conditions. if the ltcs are running with the maximum gpta ? v5 unit clock of f gpta = f fpi =90mhz, a maximum of 16 gtcs and 16 ltcs c an be connected together. if the gpta ? v5 unit clock f gpta is reduced, the number of ltcs that can be cascaded increases accordingly. only the integer part of the divider ratio as selected by the gpta0_fdr fractional divider register determines the maximum nu mber of cascaded gtcs and ltcs. table 28-34 limits of cascading gtcs and ltcs f fpi selected clock divider ratio 1) 1) selected by the gpta0_fdr fractional divider register. max. number of cascaded gtcs/ltcs 90 mhz 1 <= f fpi / f gpta < 2 16 gtcs, 16 ltcs 2 <= f fpi / f gpta < 3 no limits for gtcs, 32 ltcs 3 <= f fpi / f gpta < 4 no limits for gtcs, 48 ltcs 4 <= f fpi / f gpta no limits for gtcs and ltcs 45 mhz 1 <= f fpi / f gpta < 2 no limits for gtcs, 32 ltcs 2 <= f fpi / f gpta no limits for gtcs and ltcs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-307 v1.1, 2011-03 gpta ? v5, v1.0 28.7.7 interrupt registers each of the service request outputs of the gpta0/gpta1/ltca2 units is able to generate an interrupt and is controlled by an interrupt service request control register gpta_srck. therefore, the following interrupt service request control registers are available: ? gpta0: gpta0_src[37:00] ? gpta1: gpta1_src[37:00] ? ltca2: ltca2_src[15:00] gpta0_srck (k = 00-37) gpta0 interrupt service request control register k (7fc h -k*4 h ) reset value: 0000 0000 h gpta1_srck (k = 00-37) gpta1 interrupt service request control register k (7fc h -k*4 h ) reset value: 0000 0000 h ltca2_srck (k = 00-15) ltca2 interrupt service request control register k (7fc h -k*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-308 v1.1, 2011-03 gpta ? v5, v1.0 note: additional details on service reques t nodes and the service request control registers are described in the interrupt chapter of the TC1798 users manual system units part (volume 1). 28.7.8 gpta register address map the gpta0 and gpta1 register map shown in figure 28-101 . the ltca2 register map shown in figure 28-102 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-309 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-101gpta0/gpta1 register map mca06002_mod +010 h 000 h k = 00-63 +038 h +044 h +0e0 h +100 h +200 h +404 h +7ff h k = 00-31 k = 0, 1 fpcstat fpcctrk fpctimk k = 0 - 5 pdlctr dcmctrk dcmtimk dcmcavk dcmcovk k = 0-3 pllctr pllmti pllcnt pllstp pllrev plldtr ckbctr 1) these registers are only available in gpta0. +700 h +768 h +400 h general module control input/output line sharing unit interrupt control global timer reserved clock generation unit local timer cells interrupt service request control registers global timer cells reserved gpta-to-msc multiplexer control general module control mradout mradin mractl gtctrk gtrevk gttimk gtcxrk gtcctrk ltcxrk ltcctrk srck edctr dbgctr fdr clc srnrn srssn srscn fpc registers pdl register dcm registers pll registers cdu register gpta_mmxctr00 gpta_mmxctr01 gpta_mmxctr10 gpta_mmxctr11 k = 00-37 1) 1) 1) n = 0-3 id 1) 1) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-310 v1.1, 2011-03 gpta ? v5, v1.0 figure 28-102ltca2 register map reserved reserved mca06003_ltc32 +020 h k = 00-63 +038 h +044 h +200 h +7ff h +7c0 h mradout mradin mractl ltcxrk ltcctrk srck srss2/3 srsc2/3 k = 00-15 +3ff h local timer cells interrupt service request control registers input /output line sharing unit interrupt control 000 h general module control reserved reserved id www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-311 v1.1, 2011-03 gpta ? v5, v1.0 28.8 revision history this chapter gives a summary of recent changes within this specification. table 28-35 revision history version number changes to previous version rev_1.11 modified the tables ?pdr assignment for gpta?v5 port lines? in tc7197, tc1767, and tc1736 specifications. included the pad classes in pdr assignment table. included pdx description for a1 and f pad class. table on on-chip trigger/gating multiplexer control register assignments modified. for ltca2 the numbering of the output groups was done consistently as og3-og6. further more the output multiplexer of ltca2 has been made consistently to be 0-3/4 and 7/10-13. out[65], out[76] and out[78] are marked as signals not available as output for gpta1. rev_1.12 - add to what?s new section: to be consistent to tc1797, the double connected input group of iog3 is renamed to iog6 and the output group og1-7 are renamed to og0-og6 and the og0 is renamed to iog7. - section ?functionality of ltca2; remove plural for ltcas and double centence: the local timer cell array (ltca2) provide a set of hardware cells required for high-speed digital signal processing - add term input to ltc signal overview - add ilm indication to ltcctrk register and split register view to different modes - change for registers srsc0, srsc1, srsc2 and srsc3 in footnote 1) zero to one - add ltca2 outputs for port 5 to iocr assigment table for tc1797 - add footnote 1) and 2) to iocr assigment table for tc1797 - changed bit description for bit fileds ocm in order to allow bit extraction rev_1.13 - split registers gtcctrk for timer mode into ilm = 0 and ilm = 1 views - remove some redundant sentense at the beginning of the implementation part - improve tables ?iocr assignment for gpta port lines? to cover the different packages - remove table for pcx coding as redundant to port chapter - remove table for pdr assignmemt for gpta port lines as redundant to port chapter rev_1.14 - improve bit field description for gtcctrk and ltcctrk register bit fields ocm www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 general purpose timer array (gpta ? v5) users manual 28-312 v1.1, 2011-03 gpta ? v5, v1.0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-1 v1.1, 2011-03 ccu6, v1.0 29 capture/compare unit 6 (ccu6) the ccu6 is a high-resolution 16-bit capture and compare unit with application specific modes, mainly for ac drive control. special operating modes support the control of brushless dc-motors using hall sensors or back-emf detection. furthermore, block commutation and control mechanisms fo r multi-phase machines are supported. it also supports inputs to start several timers synchronously, an important feature in devices with several ccu6 modules. this chapter is structured as follows: ? introduction (see section 29.1 ) including register overview (see section 29.1.3 ) ? operating t12 (see section 29.2 ) including t12-related registers (see section 29.2.8 ) and capture/compare control registers (see section 29.2.9 ) ? operating t13 (see section 29.3 ) including t13-related registers (see section 29.3.6 ) ? synchronous start feature (see section 29.4 ) ? trap handling (see section 29.5 ) ? multi-channel mode (see section 29.6 ) ? hall sensor mode (see section 29.7 ) ? modulation control registers (see section 29.8 ) ? interrupt handling (see section 29.9 ) including interrupt registers (see section 29.9.2 ) ? general module operation (see section 29.10 ) including general registers (see section 29.10.4 ) ? module implementation (see section 29.11 ) 29.1 introduction the ccu6 unit is made up of a timer t12 block with three capture/compare channels and a timer t13 block with one compare channel. the t12 channels can independently generate pwm signals or accept capture triggers, or they can jointly generate control signal patterns to drive ac-motors or inverters. a rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible generation of interr upt request signals provide means for efficient software-control. note: the capture/compare m odule itself is named ccu6 (capture/compare unit 6). a capture/compare channel inside this module is named cc6x. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-2 v1.1, 2011-03 ccu6, v1.0 29.1.1 feature set overview this section gives an overview over the diffe rent building blocks and their main features. timer 12 block features ? three capture/compare channels, each cha nnel can be used either as capture or as compare channel ? generation of a three-phase pwm supported (six outputs, individual signals for high- side and low-side switches) ? 16-bit resolution, maximum count frequency = peripheral clock ? dead-time control for each channel to avoid short-circuits in the power stage ? concurrent update of t12 registers ? center-aligned and edge-aligned pwm can be generated ? single-shot mode supported ? start can be controlled by external events ? capability of counting external events ? many interrupt request sources ? hysteresis-like control mode timer 13 block features ? one independent compare channel with one output ? 16-bit resolution, maximum count frequency = peripheral clock ? concurrent update of t13 registers ? can be synchronized to t12 ? interrupt generation at period-match and compare-match ? single-shot mode supported ? start can be controlled by external events ? capability of counting external events additional specific functions ? block commutation for brushl ess dc-drives implemented ? position detection via hall-sensor pattern ? noise filter supported for position input signals ? automatic rotational speed measurement and commutation control for block commutation ? integrated error handling ? fast emergency stop without cpu load via external signal (ctrap ) ? control modes for multi-channel ac-drives ? output levels can be selected and adapted to the power stage www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-3 v1.1, 2011-03 ccu6, v1.0 29.1.2 block diagram the timer t12 can operate in capture and/or compare mode for its three channels. the modes can also be combined (e.g. a channel operates in compare mode, whereas another channel operates in capture mode ). the timer t13 can operate in compare mode only. the multi-channel control unit generates output patterns which can be modulated by t12 and/or t13. the modulati on sources can be selected and combined for the signal modulation. figure 29-1 ccu6 block diagram ccu6 module kernel input / output control port control compare compare 22 compare ou tpu t select 3 ha ll inpu t ou tpu t select 1 trap in put 3+3 capture t13 cc63 start 2 1 compare multi- channel control trap control dead- time control cc60 cc61 compare 1 1 1 t12 cc62 cc60 cout60 t1 3h r [h :a ] t1 2h r [h :a ] ccp os0[d:a] ccp os1[d:a] ccp os2[d:a] ctrap[d:a] clock control interrupt control f cc6 sr[3:0] cc60in[d:a] cc61 cout61 cc61in[d:a] cc62 cout62 cc62in[d:a] cout63 ccu6_ block_ diag address decoder www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-4 v1.1, 2011-03 ccu6, v1.0 29.1.3 ccu6 kernel registers for the generation of the overall register table, the prefix ?ccu6x_? has to be added to the register names in this table to identify the registers of different ccu6 modules that are implemented. in this naming conv ention, x indicates the module number. table 29-1 shows all registers required for programming of a ccu6 module. it summarizes the ccu6 kernel registers and defines their offset addresses. ccu6 kernel register overview figure 29-2 ccu6 registers note: in the case of a write access to addresses inside the address range (that is covered by the same chip select signal), but that are not the addresses explicitly mentioned for the module, the write access is not taken into account for the module. the same principle is valid for read accesses. in case of a read access to another address, the module does not react. t12 related registers cap/com control registers t12 cmpstat cmpmodif interrupt status / control registers t12pr t12dtc cc60r cc60sr cc61r cc61sr cc62r cc62sr t13 t13pr cc63r mcmout mcmouts pslr trpctr modctr tctr4 tctr2 tctr0 ien inp isr iss is cc63sr mcmctr t12msel general registers kscsr li ccu6_regs mcfg kscfg imon modulation control registers id identification register pisel0 pisel2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-5 v1.1, 2011-03 ccu6, v1.0 note: the exact register address is given by the relative address of the register (given in table 29-1 ) plus the kernel base address (given in table 29-14 ) of the kernel. table 29-1 ccu6 module registers register short name register long name offset addr. access mode reset value reset page read write general registers id module identification register 08 h u, sv u, sv 0000 54xx h class 3 29-11 8 pisel0 port input select register 0 10 h u, sv u, sv 0000 0000 h class 3 29-11 9 pisel2 port input select register 2 14 h u, sv u, sv 0000 0000 h class 3 29-12 1 kscfg kernel state configuration register 18 h u, sv u,sv 0000 0000 h class3/ class 1, see section 2 9.10.4.3 29-12 4 kscsr kernel state control sensitivity register 1c h u, sv u,sv 0000 0000 h class 3 29-12 7 mcfg module configuration register 04 h u, sv u,sv 0000 007 h class 3 29-12 8 imon input monitoring register 98 h u, sv u, sv 0000 0000 h class 3 29-13 0 li lost indicator register 9c h u, sv u, sv 0000 0000 h class 3 29-13 3 srcx x=0 - 3 service request control registers fc h - x * 4 h u, sv u, sv 0000 0000 h class 3 29-11 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-6 v1.1, 2011-03 ccu6, v1.0 timer t12 related registers t12 timer 12 counter register 20 h u, sv u, sv 0000 0000 h class 3 29-35 t12pr timer 12 period register 24 h u, sv u, sv 0000 0000 h class 3 29-36 t12dtc dead-time control register for timer t12 28 h u, sv u, sv 0000 0000 h class 3 29-39 cc60r capture/com pare register channel cc60 30 h u, sv u,sv 0000 0000 h class 3 29-37 cc61r capture/com pare register channel cc61 34 h u, sv u,sv 0000 0000 h class 3 29-37 cc62r capture/com pare register channel cc62 38 h u, sv u,sv 0000 0000 h class 3 29-37 cc60sr capture/com pare shadow register channel cc60 40 h u, sv u, sv 0000 0000 h class 3 29-38 cc61sr capture/com pare shadow register channel cc61 44 h u, sv u, sv 0000 0000 h class 3 29-38 table 29-1 ccu6 module registers (cont?d) register short name register long name offset addr. access mode reset value reset page read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-7 v1.1, 2011-03 ccu6, v1.0 cc62sr capture/com pare shadow register channel cc62 48 h u, sv u, sv 0000 0000 h class 3 29-38 capture/compare control registers cmpstat compare state register 60 h u, sv u, sv 0000 0000 h class 3 29-41 cmpmodif compare state modification register 64 h u, sv u, sv 0000 0000 h class 3 29-44 t12msel t12 capture/com pare mode select register 68 h u, sv u, sv 0000 0000 h class 3 29-45 tctr0 timer control register 0 70 h u, sv u, sv 0000 0000 h class 3 29-46 tctr2 timer control register 2 74 h u, sv u, sv 0000 0000 h class 3 29-50 tctr4 timer control register 4 78 h u, sv u, sv 0000 0000 h class 3 29-53 timer t13 related registers t13 timer 13 counter register 50 h u, sv u, sv 0000 0000 h class 3 29-68 t13pr timer 13 period register 54 h u, sv u, sv 0000 0000 h class 3 29-69 table 29-1 ccu6 module registers (cont?d) register short name register long name offset addr. access mode reset value reset page read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-8 v1.1, 2011-03 ccu6, v1.0 cc63r compare register for timer 13 58 h u, sv u,sv 0000 0000 h class 3 29-70 cc63sr compare shadow register for timer 13 5c h u, sv u, sv 0000 0000 h class 3 29-71 modulation control registers modctr modulation control register 80 h u, sv u, sv 0000 0000 h class 3 29-85 trpctr trap control register 84 h u, sv u, sv 0000 0000 h class 3 29-87 pslr passive state level register 88 h u, sv u, sv 0000 0000 h class 3 29-90 mcmouts multi- channel mode output shadow register 8c h u, sv u, sv 0000 0000 h class 3 29-94 mcmout multi- channel mode output register 90 h u, sv u,sv 0000 0000 h class 3 29-95 mcmctr multi- channel mode control register 94 h u, sv u, sv 0000 0000 h class 3 29-91 interrupt status and node registers table 29-1 ccu6 module registers (cont?d) register short name register long name offset addr. access mode reset value reset page read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-9 v1.1, 2011-03 ccu6, v1.0 is interrupt status register a0 h u, sv u,sv 0000 0000 h class 3 29-10 0 iss interrupt status set register a4 h u, sv u, sv 0000 0000 h class 3 29-10 3 isr interrupt status reset register a8 h u, sv u, sv 0000 0000 h class 3 29-10 5 inp interrupt node pointer register ac h u, sv u, sv 0000 3940 h class 3 29-11 0 ien interrupt node pointer register b0 h u, sv u, sv 0000 0000 h class 3 29-10 7 table 29-1 ccu6 module registers (cont?d) register short name register long name offset addr. access mode reset value reset page read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-10 v1.1, 2011-03 ccu6, v1.0 29.2 operating timer t12 the timer t12 block is the main unit to generate the 3-phase pwm signals. a 16-bit counter is connected to 3 channel registers via comparators, that generate a signal when the counter contents match one of the channel register contents. a variety of control functions facilitate the adaptation of the t12 structure to different application needs. besides the 3-phase pwm generation, the t12 block offers options for individual compare and capture functions, as well as dead-time control and hysteresis-like compare mode. this section provides information about: ? t12 overview (see section 29.2.1 ) ? counting scheme (see section 29.2.2 ) ? compare modes (see section 29.2.3 ) ? compare mode output path (see section 29.2.4 ) ? capture modes (see section 29.2.5 ) ? shadow transfer (see section 29.2.6 ) ? t12 operating mode selection (see section 29.2.7 ) ? t12 register description (see section 29.2.8 figure 29-3 overview diagram of the timer t12 block ccu6_mca05507 timer t12 logic capture/compare channel cc61 capture/compare channel cc60 capture/compare channel cc62 cc61st cc60st cc62st state bits to dead-time control and output modulation input and control/status logic t12hr cc6xin ccposx www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-11 v1.1, 2011-03 ccu6, v1.0 29.2.1 t12 overview figure 29-4 shows a detailed block diagram of timer t12. the functions of the timer t12 block are controlled by bits in registers tctr0 , tctr2 , and pisel0 . timer t12 receives its input clock ( f t12 ) from the module clock f cc6 via a programmable prescaler and an optional 1/256 divider or fr om an input signal t12hr. these options are controlled via bit fields t12clk and t12pre (see table 29-2 ). t12 can count up or down, depending on the selected operation mode. a direction flag, cdir, indicates the current counting direction. figure 29-4 timer t12 logic and period comparators via a comparator, the t12 counter register t12 is connected to a period register t12pr . this register determines the maximum count value for t12. in edge-aligned mode, t12 is cleared to 0000 h after it has reached the period value defined by t12pr. in center-aligned mode, the count direction of t12 is set from ?up? to ccu6_mca0 5508 comp. = ? period register period shadow register t12_pm counter register t12 f cc6 write to t12pr read from t12pr t12_om t12_zm = 0000 h = 0001 h t12_st 256 n clock selection edge detection t12hr t12pre t12clk iscnt12 t12std t12str ctm t12rr t12rs t12r cdir t12res t12ssc t12 control & status ste12 edge detection t12rsel t12cnt f t12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-12 v1.1, 2011-03 ccu6, v1.0 ?down? after it has reached the period value (please note that in this mode, t12 exceeds the period value by one before counting down). in both cases, signal t12_pm (t12 period match) is generated. the period regi ster receives a new period value from its shadow period register. a read access to t12pr delivers the current period value at the comparator, whereas a write access targets the shadow period register to prepare another period value. the transfer of a new period value from the shadow period register into the period register (see section 29.2.6 ) is controlled via the ?t12 shadow transfer? control signal, t12_st. the generation of this signal depends on the operating mode and on the shadow transfer enable bit ste12. providing a shadow register for the period value as well as for other values related to the generation of the pwm signal allows a concurrent update by software for all relevant parameters. two further signals indicate whether the counter contents are equal to 0000 h (t12_zm = zero match) or 0001 h (t12_om = one match). these si gnals control the counting and switching behavior of t12. the basic operating mode of t12, either edge-aligned mode ( figure 29-5 ) or center- aligned mode ( figure 29-6 ), is selected via bit ctm. a single-shot control bit, t12ssc, enables an automatic stop of the timer when the current counting period is finished (see figure 29-7 and figure 29-8 ). the start or stop of t12 is controlled by the run bit t12r that can be modified by bits in register tctr4 . the run bit can be set/cleared by software via the associated set/clear bits t12rs or t12rr, it can be set by a selectable edge of the input signal t12hr ( tctr2 .t12rsel), or it is cleared by hardware according to preselected conditions. the timer t12 run bit t12r must not be set while the applied t12 period value is zero. timer t12 can be cleared via control bit t12r es. setting this write-only bit does only clear the timer contents, but has no further effects, for example, it does not stop the timer. the generation of the t12 shadow transfer control signal, t12_st, is enabled via bit ste12. this bit can be set or reset by softwa re indirectly through it s associated set/clear control bits t12str and t12std. while timer t12 is running, write accesses to the count register t12 are not taken into account. if t12 is stopped and the dead-tim e counters are 0, write actions to register t12 are immediately taken into account. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-13 v1.1, 2011-03 ccu6, v1.0 29.2.2 t12 counting scheme this section describes the clocking and counting capabilities of t12. 29.2.2.1 clock selection in timer mode ( pisel2 .iscnt12 = 00 b ), the input clock f t12 of timer t12 is derived from the internal module clock f cc6 through a programmable prescaler and an optional 1/256 divider. the resulting prescaler factors are listed in table 29-2 . the prescaler of t12 is cleared while t12 is not running ( tctr0 .t12r = 0) to ensure reproducible timings and delays. in counter mode , timer t12 counts one step: ? if a 1 is written to tctr4 .t12cnt and pisel2 .iscnt12 = 01 b ? if a rising edge of input signal t12hr is detected and pisel2 .iscnt12 = 10 b ? if a falling edge of input signal t12hr is detected and pisel2 .iscnt12 = 11 b table 29-2 timer t12 input frequency options t12clk resulting input clock f t12 prescaler off (t12pre = 0) resulting input clock f t12 prescaler on (t12pre = 1) 000 b f cc6 f cc6 / 256 001 b f cc6 / 2 f cc6 / 512 010 b f cc6 / 4 f cc6 / 1024 011 b f cc6 / 8 f cc6 / 2048 100 b f cc6 / 16 f cc6 / 4096 101 b f cc6 / 32 f cc6 / 8192 110 b f cc6 / 64 f cc6 / 16384 111 b f cc6 / 128 f cc6 / 32768 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-14 v1.1, 2011-03 ccu6, v1.0 29.2.2.2 edge-aligned / center-aligned mode in edge-aligned mode (ctm = 0), timer t12 is always counting upwards (cdir = 0). when reaching the value given by the period register (period-match t12_pm), the value of t12 is cleared with the next counting step (saw tooth shape). figure 29-5 t12 operation in edge-aligned mode as a result, in edge-aligned mode, the timer period is given by: t12 per = TC1798 capture/compare unit 6 (ccu6) users manual 29-15 v1.1, 2011-03 ccu6, v1.0 figure 29-6 t12 operation in center-aligned mode note: bit cdir changes with the next timer clock event after the one-match or the period-match. therefore, the timer continues counting in the previous direction for one cycle before actually c hanging its direction (see figure 29-6 ). ccu6_mct 05510 f t12 cc6x shadow transfer t12 count period match zero match value n value n+1 cdir down up shadow transfer value n+1 value n+2 up down period match TC1798 capture/compare unit 6 (ccu6) users manual 29-16 v1.1, 2011-03 ccu6, v1.0 29.2.2.3 single-shot mode in single-shot mode, the timer run bit t12r is cleared by hardware. if bit t12ssc = 1, the timer t12 will stop when the current timer period is finished. in edge-aligned mode, t12r is cleared when the timer becomes zero after having reached the period value (see figure 29-7 ). figure 29-7 single-shot operation in edge-aligned mode in center-aligned mode, the period is finished when the timer has counted down to zero (one clock cycle after the one- match while counting down, see figure 29-8 ). figure 29-8 single-shot operation in center-aligned mode 0 ccu6_mct05511 compare value period value f t12 cc6xst t12ssc t12 count t12r ccu6_mct05512 0 compare value period value cc6xst t12ssc t12 count t12r 1 f t12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-17 v1.1, 2011-03 ccu6, v1.0 29.2.3 t12 compare mode associated with timer t12 are three indi vidual capture/compare channels, that can perform compare or capture operations with r egard to the contents of the t12 counter. the capture functions are explained in section 29.2.5 . 29.2.3.1 compare channels in compare mode (see figure 29-9 ), the three individual compare channels cc60 cc61, and cc62 can generate a three-phase pwm pattern. figure 29-9 t12 channel comparators each compare channel is connected to the t12 counter register via its individual equal- to comparator, generating a match signal when the contents of the counter matches the contents of the associated compare register . each channel consists of the comparator and a double register structure - the actu al compare register cc6xr, feeding the comparator, and an associated shadow register cc6xsr, that is preloaded by software and transferred into the compare register when signal t12 shadow transfer, t12_st, gets active. providing a shadow register for the compare value as well as for other values related to the generation of the pwm signal facilitates a concurrent update by software for all relevant parameters of a three-phase pwm. ccu6_mca0 5513 comp. = ? compare register cc61r compare shadow register cc61sr comp. = ? compare register cc62r compare shadow register cc62sr comp. = ? compare register cc60r compare shadow register cc60sr compare match cm_61 compare match cm_62 compare match cm_60 t12_st counter register t12 f t12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-18 v1.1, 2011-03 ccu6, v1.0 29.2.3.2 channel state bits associated with each (compare) channel is a state bit, cmpstat .cc6xst, holding the status of the compare (or capture) operation (see figure 29-10 ). in compare mode, the state bits are modified according to a set of switching rules, depending on the current status of timer t12. figure 29-10 compare state bits for compare mode the inputs to the switching rule logic for the cc6xst bits are the timer direction (cdir), the timer run bit (t12r), the timer t12 zero-match signal (t12_zm), and the actual individual compare-match signals cm_6x as well as the mode control bits, t12msel .msel6x. ccu6_mcb 05514 switching rule logic state bit cc60st cm_60 to interrupt control cc60_r cc60_f to dead_time counter 0 t12_zm mcc60s/r msel60 t12r switching rule logic state bit cc61st to interrupt control cc61_r cc61_f to dead_time counter 1 mcc61s/r msel61 switching rule logic state bit cc62st to interrupt control cc62_r cc62_f to dead_time counter 2 mcc62s/r msel62 cdir ccpos0 compare channel cc60 cm_61 compare channel cc61 cm_62 compare channel cc62 t12 counter ccpos1 ccpos2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-19 v1.1, 2011-03 ccu6, v1.0 in addition, each state bit can be set or clear ed by software via the appropriate set and reset bits in register cmpmodif , mcc6xs and mcc6xr. the input signals ccposx are used in hysteresis-like compare mode , whereas in normal compare mode, these inputs are ignored. note: in hall sensor, single shot or capture modes, additional/different rules are taken into account (see related sections). a compare interrupt event cc6x_r is signaled when a compare match is detected while counting upwards, whereas the compare interrupt event cc6x_f is signaled when a compare match is detected while counting down. the actual setting of a state bit has no influence on the interrupt generation in compare mode. a modification of a state bit cc6xst by the switching rule logic due to a compare action is only possible while timer t12 is running (t 12r = 1). if this is the case, the following switching rules apply for setting and clearing the state bits in compare mode (illustrated in figure 29-11 and figure 29-12 ): a state bit cc6xst is set to 1: ? with the next t12 clock ( f t12 ) after a compare-match when t12 is counting up (i.e., when the counter is incremented above the compare value); ? with the next t12 clock ( f t12 ) after a zero-match and a parallel compare-match when t12 is counting up. a state bit cc6xst is cleared to 0: ? with the next t12 clock ( f t12 ) after a compare-match when t12 is counting down (i.e., when the counter is decremented below the compare value in center-aligned mode); ? with the next t12 clock ( f t12 ) after a zero-match and no parallel compare-match when t12 is counting up. figure 29-11 compare operation, edge-aligned mode figure 29-13 illustrates some more examples for compare waveforms. it is important to note that in these examples, it is assumed that some of the compare values are changed ccu6_mct05515 f t12 zero compare value cc6xst period value t12 count www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-20 v1.1, 2011-03 ccu6, v1.0 while the timer is running. this change is performed via a software preload of the shadow register, cc6xsr. the value is transferred to the actual compare register cc6xr with the t12 shadow transfer signal, t12_st, that is assumed to be enabled. figure 29-12 compare operation, center-aligned mode ccu6_mct 05516 f t12 zero compare value cc6xst period value compare-match compare-match t12 count www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-21 v1.1, 2011-03 ccu6, v1.0 figure 29-13 compare waveform examples example b) illustrates the transition to a duty cycle of 100%. first, a compare value of 0001 h is used, then changed to 0000 h . please note that a low pulse with the length of one t12 clock is still produced in the cycle where t he new value 0000 h is in effect; this pulse originates from the previous value 0001 h . in the following timer cycles, the state bit cc6xst remains at 1, producing a 100% duty cycle signal. in this case, the compare rule ?zero-match and compare-match? is in effect. example f) shows the transition to a duty cycle of 0%. the new compare value is set to TC1798 capture/compare unit 6 (ccu6) users manual 29-22 v1.1, 2011-03 ccu6, v1.0 figure 29-14 three-channel compare waveforms ccu6_mct05518 period value up down down up down zero cc60r cc61r cc62r cc62st cc61st cc60st shadow transfer cdir t12 count www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-23 v1.1, 2011-03 ccu6, v1.0 29.2.3.3 hysteresis-like control mode the hysteresis-like control mode ( t12msel .msel6x = 1001 b ) offers the possibility to switch off the pwm output if the input ccposx becomes 0 by clearing the state bit cc6xst. this can be used as a simple motor control feature by using a comparator indicating, e.g., overcurrent. while ccposx = 0, the pwm outputs of the corresponding channel are driving their passive levels, because the setting of bit cc6xst is only possible while ccposx = 1. as long as input ccposx is 0, the corres ponding state bit is held 0. when ccposx is at high level, the outputs can be in active state and are determined by bit cc6xst (see figure 29-10 for the state bit logic and figure 29-15 for the output paths). the ccposx inputs are evaluated with f cc6 . this mode can be used to introduce a timing-related behavior to a hysteresis controller. a standard hysteresis controller detects if a value exceeds a limit and switches its output according to the compare result. depending on the operating conditions, the switching frequency and the duty cycle are no t fixed, but change permanently. if (outer) time-related control loops based on a hysteresis controller in an inner loop should be implemented, the outer loops show a better behavior if they are synchronized to the inner loops. therefore, the hysteresis -like mode can be used, that combines timer- related switching with a hysteresis controller behavior. for example, in this mode, an output can be switched on according to a fixed time base, but it is switched off as soon as a falling edge is detected at input ccposx. this mode can also be used for standard pwm with overcurrent protection. as long as there is no low level signal at pin ccposx, the output signals are generated in the normal manner as described in the previous sections. only if input ccposx shows a low level, e.g. due to the detection of overcu rrent, the outputs are shut off to avoid harmful stress to the system. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-24 v1.1, 2011-03 ccu6, v1.0 29.2.4 compare mode output path figure 29-15 gives an overview on the signal path from a channel state bit to its output pin in its simplest form. as illustrated, a user has a variety of controls to determine the desired output signal switching behavior in relation to the current state of the state bit, cc6xst. please refer to section 29.2.4.3 for details on the output modulation. figure 29-15 compare mode simp lified output path diagram the output path is based on signals that are defined as active or passive. the terms active and passive are not related to output levels, but to internal actions. this mainly applies for the modulation, where t12 and t13 signals are combined with the multi- channel signals and the trap function. the output level selection allows the user to define the output level at the output pin for the passive state (inverted level for the active state). it is recommended to configure this block in a way that an external power switch is switched off while the ccu6 delivers an output signal in the passive state. 29.2.4.1 dead-t ime generation the generation of (complementary) signals for the high-side and the low-side switches of one power inverter phase is based on the same compare channel. for example, if the high-side switch should be active while the t12 counter value is above the compare value (state bit = 1), then the low-side switch should be active while the counter value is below the compare value (state bit = 0). in most cases, the switching behavior of the connected power switches is not symmetrical concerning the switch-on and swit ch-off times. a general problem arises if the time for switch-on is smaller than the time for switch-off of the power device. in this case, a short-circuit can occur in the inverter bridge leg, which may damage the complete system. in order to solve this problem by hw , this capture/compare unit ccu6_mca05519 level select level select cc6x cout6x cout6x_o cc6x_o dead-time counters t12 state selection cc6xst cc6xst cc6xps cout6xps t12 output modulation psly psly+1 output level selection cc61st dead-time generation t12 state bits cc60st cc62st www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-25 v1.1, 2011-03 ccu6, v1.0 contains a programmable dead-time generation block, that delays the passive to active edge of the switching signals by a programmable time (the active to passive edge is not delayed). the dead-time generation block, illustrated in figure 29-16 , is built in a similar way for all three channels of t12. it is controlled by bits in register t12dtc . any change of a cc6xst state bit activates the corresponding dead-time counter, that is clocked with the same input clock as t12 ( f t12 ). the length of the dead-time can be programmed by bit field dtm. this value is identical for all three channels. writing tctr4 .dtres = 1 sets all dead-times to passive. figure 29-16 dead-time generation block diagram each of the three dead-time counters has its individual dead-time enable bit, dtex. an enabled dead-time counter generates a dead- time delaying the passive-to-active edge of the channel output signal. the change in a state bit cc6xst is not taken into account while the dead-time generation of this channel is currently in progress (active). this avoids an unintentional additional dead-time if a state bit cc6xst changes too early. a disabled dead-time counter is always consi dered as passive and does not delay any edge of cc6xst. based on the state bits cc6xst, the dead-time generation block outputs a direct signal cc6xst and an inverted signal cc6xst for each compare channel, each masked with the effect of the related dead-time counters (waveforms illustrated in figure 29-17 ). dead-time value dtm dead-time counter 1 dead-time counter 0 f t12 ccu6_mcb05520 dead-time counter 2 dte1 dte2 dtres dte0 cc60st cc61st cc62st dead-time 0 active / passive dead-time 1 active / passive dead-time 2 active / passive cc60st cc60st cc61st cc61st cc62st cc62st www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-26 v1.1, 2011-03 ccu6, v1.0 figure 29-17 dead-time generation waveforms 29.2.4.2 state selection to support a wide range of power switches and drivers, the state selection offers the flexibility to define wh en an output can be active and can be modulated, especially useful for complementary or multi-phase pwm signals. the state selection is based on the signals cc6xst and cc6xst delivered by the dead- time generator (see figure 29-15 ). both signals are never active at the same time, but can be passive at the same time. this happens during the dead-time of each compare channel after a change of the corresponding state bit cc6xst. the user can select independently for eac h output signal cc6xo and cout6xo if it should be active before or after the comp are value has been reached (see register cmpstat ). with this selection, the active (conducting) phases of complementary power switches in a power inverter bridge leg can be positioned with respect to the compare value (e.g. signal cc6xo can be active before, whereas cout6xo can be active after the compare value is reached). like this, the output modulation, the trap logic and the output level selection can be programmed independently for each output signal, although two output signals are referring to the same compare channel. ccu6_mct05521 cc6xst with dead- time cc6xst with dead- time state bit cc6xst compare value t12 counter value dead- time active active passive passive active active passive passive active passive www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-27 v1.1, 2011-03 ccu6, v1.0 29.2.4.3 output modulati on and level selection the last block of the data path is the output modulation block. here, all the modulation sources and the trap functionality are combined and control the actual level of the output pins (controlled by the modulation enable bits t1xmodeny and mcmen in register modctr ). the following signal sources can be combined here for each t12 output signal (see figure 29-18 for compare channel cc60): ?a t12 related compare signal cc6x_o (for outputs cc6 x) or cout6x_o (for outputs cout6x) delivered by the t12 block (state selection with dead-time) with an individual enable bit t12modeny per output signal (y = 0, 2, 4 for outputs cc6x and y = 1, 3, 5 for outputs cout6x) ?the t13 related compare signal cc63_o delivered by the t13 state selection with an individual enable bit t13modeny per output signal (y = 0, 2, 4 for outputs cc6x and y = 1, 3, 5 for outputs cout6x) ?a multi-channel output signal mcmpy (y = 0, 2, 4 for outputs cc6x and y = 1, 3, 5 for outputs cout6x) with a common enable bit mcmen ?the trap state trps with an individual enable bit trpeny per output signal (y = 0, 2, 4 for outputs cc6x and y = 1, 3, 5 for outputs cout6x) if one of the modulation input signals cc6x_o/cout6x_o, cc63_o, or mcmpy of an output modulation block is enabled and is at passive state, the modulated is also in passive state, regardless of the state of the other signals that are enabled. only if all enabled signals are in active state the modulated output shows an active state. if no modulation input is enabled, the output is in passive state. if the trap state is active (trps = 1), then the outputs that are enabled for the trap signal (by trpeny = 1) are set to the passive state. the output of each of the modulation control blocks is connected to a level select block that is configured by register pslr . it offers the option to determine the actual output level of a pin, depending on the state of the output line (decoupling of active/passive state and output polarity) as specified by the passive state select bit psly. if the modulated output signal is in the passive state, the level specified directly by psly is output. if it is in the active state, the inverted level of psly is output. this allows the user to adapt the polarity of an active output signal to the connected circuitry. the psly bits have shadow registers to allow for updates without undesired pulses on the output lines. the bits related to cc6x and cout6x (x = 0, 1, 2) are updated with the t12 shadow transfer signal (t12_st). a read action returns the actually used values, whereas a write action targets the shadow bits. providing a shadow register for the psl value as well as for other values related to the generation of the pwm signal facilitates a concurrent update by software for all relevant parameters. figure 29-18 shows the output modulation structure for compare channel cc60 (output signals cc60 and cout60). a similar structure is implemented for the other two compare channels cc61 and cc62. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-28 v1.1, 2011-03 ccu6, v1.0 figure 29-18 output modulation for compare channel cc60 ccu6_mca 05543 cc60 output modulation cc60 cc60_o t12moden0 trpen0 psl0 active passive t13 block t12 block + dead-time multi-channel mode cc63_o t13moden0 trps trap handling block level selection cout60 output modulation cout60 cout60_o t12moden1 trpen1 psl1 active passive t13moden1 level selection mcmen mcmp0 mcmp1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-29 v1.1, 2011-03 ccu6, v1.0 29.2.5 t12 capture modes each of the three channels of the t12 block can also be used to capture t12 time information in response to an external signal cc6xin. in capture mode, the interrupt event cc6x_r is detected when a rising edge is detected at the input cc6xin, whereas the interrupt event cc6x_f is detected when a falling edge is detected. there are a number of different modes for capture operation. in all modes, both of the registers of a channel are used. the selection of the capture modes is done via the t12msel .msel6x bit fields and can be selected individually for each of the channels. figure 29-19 illustrates capture mode 1 . when a rising edge (0-to-1 transition) is detected at the corresponding input signal cc6xin, the current contents of timer t12 are captured into register cc6xr. when a fa lling edge (1-to-0 transition) is detected at the input signal cc6xin, the contents of ti mer t12 are captured into register cc6xsr. figure 29-19 capture mo de 1 block diagram table 29-3 capture modes overview msel6x mode signal active edge cc6nsr stored in t12 stored in 0100 b 1 cc6xin rising ? cc6xr cc6xin falling ? cc6xsr 0101 b 2 cc6xin rising cc6xr cc6xsr 0110 b 3 cc6xin falling cc6xr cc6xsr 0111 b 4 cc6xin any cc6xr cc6xsr ccu6_mcb05522 f t12 edge detect capture mode selection state bit cc6xst cc6xin to interrupt logic set rising falling shadow register cc6xsr register cc6xr counter register t12 msel6x cc6x_r cc6x_f f cc6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-30 v1.1, 2011-03 ccu6, v1.0 capture modes 2, 3 and 4 are shown in figure 29-20 . they differ only in the active edge causing the capture operation. in each of the three modes, when the selected edge is detected at the corresponding input signal cc6xin, the current contents of the shadow register cc6xsr are transferred into re gister cc6xr, and the current timer t12 contents are captured in register cc6xsr (s imultaneous transfer). the active edge is a rising edge of cc6xin for capture mode 2, a falling edge for mode 3, and both, a rising or a falling edge for capture mode 4, as shown in table 29-3 . these capture modes are very useful in cases where there is little time between two consecutive edges of the input signal. figure 29-20 capture modes 2, 3 and 4 block diagram ccu6_mcb 05523 f t12 edge detect capture mode selection state bit cc6xst cc6xin to interrupt logic set shadow register cc6xsr register cc6xr counter register t12 msel6x cc6x_r cc6x_f f cc6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-31 v1.1, 2011-03 ccu6, v1.0 five further capture modes are called multi-input capture modes , as they use two different external inputs, signal cc6xin and signal ccposx. figure 29-21 multi-input capture modes block diagram in each of these modes, the current t12 contents are captured in register cc6xr in response to a selected event at signal cc6xin, and in register cc6xsr in response to a selected event at signal ccposx. the possible events can be opposite input transitions, or the same transitions, or an y transition at the two inputs. the different options are detailed in table 29-4 . in each of the various capture modes, the channel state bit, cc6xst, is set to 1 when the selected capture trigger event at signal cc6xin or ccposx has occurred. the state bit is not cleared by hardware, but can be cleared by software. in addition, appropriate signal lines to the in terrupt logic are activated, that can generate an interrupt request to the cpu. regardless of the selected active edge, all edges detected at signal cc6xin can lead to the activation of the appropriate interrupt request line (see also section 29.9 ). ccu6_mcb 05524 f t12 edge detect capture mode selection state bit cc6xst cc6xin to interrupt logic set shadow register cc6xsr register cc6xr counter register t12 set capture mode selection edge detect ccposx msel6x msel6x f cc6 cc6x_r cc6x_f www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-32 v1.1, 2011-03 ccu6, v1.0 table 29-4 multi-input capture modes overview msel6x mode signal active edge t12 stored in 1010 b 5 cc6xin rising cc6xr ccposx falling cc6xsr 1011 b 6 cc6xin falling cc6xr ccposx rising cc6xsr 1100 b 7 cc6xin rising cc6xr ccposx rising cc6xsr 1101 b 8 cc6xin falling cc6xr ccposx falling cc6xsr 1110 b 9 cc6xin any cc6xr ccposx any cc6xsr 1111 b ? reserved (no capture or compare action) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-33 v1.1, 2011-03 ccu6, v1.0 29.2.6 t12 shadow register transfer a special shadow transfer signal (t12_st) c an be generated to facilitate updating the period and compare values of the compare channels cc60, cc61, and cc62 synchronously to the operation of t12. providing a shadow register for values defining one pwm period facilitates a concurrent update by software for all relevant parameters. the next pwm period can run with a new set of parameters. the generation of this signal is requested by software via bit tctr0 .ste12 (set by writing 1 to the write-only bit tctr4 .t12str, cleared by writin g 1 to the write-only bit tctr4 .t12std). figure 29-22 shows the shadow register structure and the shadow transfer signals, as well as on the read/write accessibility of the various registers. figure 29-22 t12 shadow register overview ccu6_mca05546 compare register cc6xr compare shadow register cc6xsr >1 _ other modes (hall, capture, etc.) period register t12pr period shadow register t12pr cout6xps cout6xps shadow (t12) psly (t12) psly shadow cc6xps cc6xps shadow t12_st write read read read read write write write read write read www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-34 v1.1, 2011-03 ccu6, v1.0 a t12 shadow register transfer takes place (t12_st active): ? while timer t12 is not running (t12r = 0), or ? ste12 = 1 and a period-match is detected while counting up, or ? ste12 = 1 and a one-match is detected while counting down when signal t12_st is active, a shadow regist er transfer is triggered with the next cycle of the t12 clock. bit ste12 is automatically cleared with the shadow register transfer. 29.2.7 timer t12 operating mode selection the operating mode for the t12 channels are defined by the bit fields t12msel .msel6x. the clocking and counting scheme of the timers are controlled by the timer control registers tctr0 and tctr2 . specific actions are triggered by write operations to register tctr4 . table 29-5 t12 capture/compare modes overview msel6x selected operating mode 0000 b , 1111 b capture/compare modes switched off 0001 b , 0010 b , 0011 b compare mode, see section 29.2.3 same behavior for all three codings 01xx b double-register capture modes, see section 29.2.5 1000 b hall sensor mode, see section 29.7 in order to properly enable this mode, all three msel6x fields have to be programmed to hall sensor mode. 1001 b hysteresis-like compare mode, see section 29.2.3.3 1010 b 1011 b , 1100 b , 1101 b 1110 b multi-input capture modes, see section 29.2.5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-35 v1.1, 2011-03 ccu6, v1.0 29.2.8 t12 rela ted registers 29.2.8.1 t12 counter register register t12 represents the counting value of timer t12. it can only be written while the timer t12 is stopped. write actions while t 12 is running are not taken into account. register t12 can always be read by sw. in edge-aligned mode, t12 only counts up, whereas in center-aligned mode, t12 can count up and down. note: while timer t12 is stopped, the internal clock divider is reset in order to ensure reproducible timings and delays. t12 timer t12 counter register (20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t12cv rwh field bits type description t12cv [15:0] rwh timer 12 counter value this register represents the 16-bit counter value of timer12. 0 [31:16] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-36 v1.1, 2011-03 ccu6, v1.0 29.2.8.2 period register register t12pr contains the period value fo r timer t12. the period value is compared to the actual counter value of t12 and the resulting counter actions depend on the defined counting rules. this register has a shadow register and the shadow transfer is controlled by bit ste12. a read action by sw delivers the value that is currently used for the compare action, whereas the write action targets a shadow register. the shadow register structure allows a concurrent update of all t12-related values. t12pr timer 12 period register (24 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t12pv rwh field bits type description t12pv [15:0] rwh t12 period value the value t12pv defines the counter value for t12 leading to a period-match. when reaching this value, the timert12 is set to zero (edge-aligned mode) or changes its count direction to down counting (center-aligned mode). 0 [31:16] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-37 v1.1, 2011-03 ccu6, v1.0 29.2.8.3 capture/compare registers in compare mode, the registers cc6xr (x = 0 - 2) are the actual compare registers for t12. the values stored in cc6xr are compar ed (all three channels in parallel) to the counter value of t12. in capture mode, the current value of the t12 counter register is captured by registers cc6xr if the co rresponding capture event is detected. cc6xr (x = 0-2) capture/compare register for channel cc6x (30 h + 4*x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 ccv rh field bits type description ccv [15:0] rh capture/compare value in compare mode, the bit fields ccv contain the values, that are compared to the t12 counter value. in capture mode, the captured value of t12 can be read from these registers. 0 [31:16] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-38 v1.1, 2011-03 ccu6, v1.0 29.2.8.4 capture/compare shadow registers the registers cc6xr can only be read by sw, the modification of the value is done by a shadow register transfer from register cc6xsr. the corresponding shadow registers cc6xsr can be read and written by sw. in capture mode, the value of the t12 counter register can also be captured by registers cc6xsr if the selected capture event is detected (depending on the selected capture mode). note: the shadow registers can also be written by sw in capture mode. in this case, the hw capture event wins over the sw writ e if both happen in the same cycle (the sw write is discarded). cc6xsr (x=0-2) capture/compare shadow reg. for channel cc6x (40 h +4*x) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 ccs rwh field bits type description ccs [15:0] rwh shadow register for channel x capture/compare value in compare mode, the bit fields contents of ccs are transferred to the bit fields ccv for the corresponding channel during a shadow transfer. in capture mode, the captured value of t12 can be read from these registers. 0 [31:16] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-39 v1.1, 2011-03 ccu6, v1.0 29.2.8.5 dead-time control register register t12dtc controls the dead-time generation for the timer t12 compare channels. each channel can be independently enabled/disabled for dead-time generation. if enabled, the transition from passive state to active state is delayed by the value defined by bit field dtm. the dead time counters are clocked with the same frequency as t12. this structure allows symmetrical dead-time generation in center-aligned and in edge- aligned pwm mode. a duty cycle of 50% leads to cc6x, cout6x swit ched on for: 0.5 * period - dead time. note: the dead-time counters are not reset by bit t12res, but by bit dtres. t12dtc dead-time control register for timer12 (28 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 dtr 2 dtr 1 dtr 0 0 dte 2 dte 1 dte 0 dtm r rh rh rh r rw rw rw rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-40 v1.1, 2011-03 ccu6, v1.0 field bits type description dtm [7:0] rw dead-time bit field dtm determines the programmable delay between switching from the passive state to the active state of the selected outputs. the switching from the active state to the passive state is not delayed. dte2, dte1, dte0 10, 9, 8 rw dead time enable bits bits dte0..dte2 enable and disable the dead time generation for each compare channel (0, 1, 2) of timer t12. 0 b dead-time counter x is disabled. the corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 1 b dead-time counter x is enabled. the corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field dtm. dtr2, dtr1, dtr0 14, 13, 12 rh dead time run indication bits bits dtr0..dtr2 indicate the status of the dead time generation for each compare channel (0, 1, 2) of timer t12. 0 b dead-time counter x is currently in the passive state. 1 b dead-time counter x is currently in the active state. 0 11, [31:15] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-41 v1.1, 2011-03 ccu6, v1.0 29.2.9 capture/compare control registers 29.2.9.1 channel state bits the compare state register cmpstat contai ns status bits monitoring the current capture and compare state and control bits defining the active/passive state of the compare channels. cmpstat compare state register (60 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t13 im c out 63ps c out 62ps cc 62ps c out 61ps cc 61ps c out 60ps cc 60ps 0 cc 63st cc pos 62 cc pos 61 cc pos 60 cc 62st cc 61st cc 60st rwhrwhrwhrwhrwhrwhrwhrwhr rhrhrhrhrhrhrh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-42 v1.1, 2011-03 ccu6, v1.0 field bits type description cc60st, cc61st, cc62st, cc63st 1) 0, 1, 2, 6 rh capture/compare state bits bits cc6xst monitor the state of the capture/compare channels. bits cc6xst (x = 0, 1, 2) are related to t12, bit cc63st is related to t13. 0 b in compare mode, the timer count is less than the compare value. in capture mode, the selected edge has not yet been detected since the bit has been cleared by sw the last time. 1 b in compare mode, the counter value is greater than or equal to the compare value. in capture mode, the selected edge has been detected. ccpos60, ccpos61, ccpos62 3, 4, 5 rh sampled hall pattern bits bits ccpos6x (x = 0, 1, 2) are indicating the value of the input hall pattern that has been compared to the current and expected value. the value is sampled when the event hcrdy (hall compare ready) occurs. 0 b the input ccposx has been sampled as 0. 1 b the input ccposx has been sampled as 1. cc60ps, cc61ps, cc62ps, cout60ps, cout61ps, cout62ps, cout63ps 2) 8, 10, 12, 9, 11, 13, 14 rwh passive state select for compare outputs bits cc6xps, cout6xps se lect the state of the corresponding compare channel , that is considered to be the passive state. during the passive state, the passive level (defined in register pslr) is driven by the output pin. bits cc6xps, cout6xps (x = 0, 1, 2) are related to t12, bit cc63ps is related to t13. 0 b the corresponding compare signal is in passive state while cc6xst is 0. 1 b the corresponding compare signal is in passive state while cc6xst is 1. in capture mode, these bits are not used. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-43 v1.1, 2011-03 ccu6, v1.0 t13im 3) 15 rwh t13 inverted modulation bit t13im inverts the t13 signal for the modulation of the cc6x and cout6x (x = 0, 1, 2) signals. 0 b t13 output cc63_o is equal to cc63st. 1 b t13 output cc63_o is equal to cc63st . 0 7, [31:16] r reserved; returns 0 if read; should be written with 0. 1) these bits are set and cleared according to the t12, t13 switching rules 2) these bits have shadow bits and are updated in paralle l to the capture/compare registers of t12, t13 respectively. a read action targets t he actually used values, whereas a wr ite action targets the shadow bits. 3) this bit has a shadow bit and is updated in parallel to the compare and period registers of t13. a read action targets the actually used values, whereas a write action targets the shadow bit. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-44 v1.1, 2011-03 ccu6, v1.0 the compare status modification register cmpmodif provides software-control (independent set and clear conditions) for the channel state bits cc6xst. this feature enables the user to individually change the st atus of the output lines by software, for example when the corresponding compare timer is stopped. cmpmodif compare state modification register (64 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 mcc 63r 0 mcc 62r mcc 61r mcc 60r 0 mcc 63s 0 mcc 62s mcc 61s mcc 60s rw r wwwrw r www field bits type description mcc60s, mcc61s, mcc62s, mcc63s, mcc60r, mcc61r, mcc62r, mcc63r 0, 1, 2, 7, 8, 9, 10, 14 w capture/compare status modification bits these bits are used to bits to set (mcc6xs) or to clear (mcc6xr) the corresponding bits cc6xst by sw. this feature allows the user to individually change the status of the output lines by sw, e.g. when the corresponding compare timer is stopped. this allows a bit manipulation of cc6xst-bits by a single data write action. the following functionality of a write access to bits concerning the same capture/compare state bit is provided: [mcc6xr, mcc6xs] = 00 b bit cc6xst is not changed. 01 b bit cc6xst is set. 10 b bit cc6xst is cleared. 11 b reserved 0 [5:3], 7, [13:11] , [31:15] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-45 v1.1, 2011-03 ccu6, v1.0 29.2.9.2 t12 mode control register register t12msel contains control bits to select the capture/compare functionality of the three channels of timer t12. t12msel t12 mode select register (68 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 d byp hsync msel62 msel61 msel60 rw rw rw rw rw field bits type description msel60, msel61, msel62 [3:0], [7:4], [11:8] rw capture/compare mode selection these bit fields select the operating mode of the three t12 capture/compare channels. each channel (x = 0, 1, 2) can be programmed individually for one of these modes (except for hall sensor mode). coding see table 29-5 . hsync [14:12] rw hall synchronization bit field hsync defines the source for the sampling of the hall input pattern and the comparison to the current and the expected hall pattern bit fields. coding see table 29-11 . dbyp 15 rw delay bypass dbyp controls whether the source signal for the sampling of the hall input pattern (selected by hsync) is delayed by the dead-time counter 0. 0 b the bypass is not active. dead-time counter 0 is generating a delay after the source signal becomes active. 1 b the bypass is active. dead-time counter 0 is not used for a delay. 0 [31:16] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-46 v1.1, 2011-03 ccu6, v1.0 29.2.9.3 timer control registers register tctr0 controls the basic fu nctionality of both timers, t12 and t13. note: a write action to the bit fields t12clk or t12pre is only taken into account while the timer t12 is not running (t12r=0). a write action to the bit fields t13clk or t13pre is only taken into account while the timer t13 is not running (t13r=0). tctr0 timer control register 0 (70 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ste 13 t13r t13 pre t13clk ctm cdir ste 12 t12r t12 pre t12clk r rhrhrw rw rwrhrhrhrw rw field bits type description t12clk [2:0] rw timer t12 input clock select selects the input clock for timer t12 that is derived from the peripheral clock according to the equation f t12 = f cc6 / 2 TC1798 capture/compare unit 6 (ccu6) users manual 29-47 v1.1, 2011-03 ccu6, v1.0 t12r 4rh timer t12 run bit 1) t12r starts and stops timer t12. it is set/cleared by sw by setting bits t12rr or t12r s or it is cleared by hw according to the function defined by bit field t12ssc. 0 b timer t12 is stopped. 1 b timer t12 is running. ste12 5rh timer t12 shadow transfer enable bit ste12 enables or disables the shadow transfer of the t12 period value, the compare values and passive state select bits and levels from their shadow registers to the actual registers if a t12 shadow transfer event is detected. bit ste12 is cleared by hardware after the shadow transfer. a t12 shadow transfer event is a period-match while counting up or a one-match while counting down. 0 b the shadow register transfer is disabled. 1 b the shadow register transfer is enabled. cdir 6rh count direction of timer t12 this bit is set/cleared according to the counting rules of t12. 0 b t12 counts up. 1 b t12 counts down. ctm 7rw t12 operating mode 0 b edge-aligned mode: t12 always counts up and continues counting from zero after reaching the period value. 1 b center-aligned mode: t12 counts down after detecting a period-match and counts up after detecting a one-match. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-48 v1.1, 2011-03 ccu6, v1.0 t13clk [10:8] rw timer t13 input clock select selects the input clock for timer t13 that is derived from the peripheral clock according to the equation f t13 = f cc6 / 2 TC1798 capture/compare unit 6 (ccu6) users manual 29-49 v1.1, 2011-03 ccu6, v1.0 2) a concurrent set/cleared action on t13r (from t13ssc , t13tec, t13rr or t13rs) will have no effect. the bit t12r will remain unchanged. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-50 v1.1, 2011-03 ccu6, v1.0 register tctr2 controls the single-shot and the synchronization functionality of both timers t12 and t13. both timers can run in single-shot mode. in this mode they stop their counting sequence automatically after one counting period with a count value of zero. the single-shot mode and the synchronization feature of t13 to t12 allow the generation of events with a programmable delay after well-defined pwm actions of t12. tctr2 timer control register 2 (74 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 t13 rsel t12 rsel 0 t13 ted t13 tec t13 ssc t12 ssc r rw rw r rw rw rw rw field bits type description t12ssc 0rw timer t12 single shot control this bit controls the single shot-mode of t12. 0 b the single-shot mode is disabled, no hw action on t12r. 1 b the single shot mode is enabled, the bit t12r is cleared by hw if - t12 reaches its period value in edge-aligned mode - t12 reaches the value 1 while down counting in center-aligned mode. in parallel to the clear action of bit t12r, the bits cc6xst (x=0, 1, 2) are cleared. t13ssc 1rw timer t13 single shot control this bit controls the single shot-mode of t13. 0 b no hw action on t13r 1 b the single-shot mode is enabled, the bit t13r is cleared by hw if t13 reaches its period value. in parallel to the clear action of bit t13r, the bit cc63st is cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-51 v1.1, 2011-03 ccu6, v1.0 t13tec [4:2] rw t13 trigger event control bit field t13tec selects the trigger event to start t13 (automatic set of t13r for synchronization to t12 compare signals) according to following combinations: 000 b no action 001 b set t13r on a t12 compare event on channel 0 010 b set t13r on a t12 compare event on channel 1 011 b set t13r on a t12 compare event on channel 2 100 b set t13r on any t12 compare event (ch. 0, 1, 2) 101 b set t13r upon a period-match of t12 110 b set t13r upon a zero-match of t12 (while counting up) 111 b set t13r on any edge of inputs ccposx t13ted [6:5] rw timer t13 trigger event direction 1) bit field t13ted delivers additional information to control the automatic set of bit t13r in the case that the trigger action defined by t13tec is detected. 00 b reserved, no action 01 b while t12 is counting up 10 b while t12 is counting down 11 b independent on the count direction of t12 t12rsel [9:8] rw timer t12 external run selection bit field t12rsel defines the event of signal t12hr that can set the run bit t12r by hw. 00 b the external setting of t12r is disabled. 01 b bit t12r is set if a rising edge of signal t12hr is detected. 10 b bit t12r is set if a fallin g edge of si gnal t12hr is detected. 11 b bit t12r is set if an edge of signal t12hr is detected. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-52 v1.1, 2011-03 ccu6, v1.0 t13rsel [11:10] rw timer t13 external run selection bit field t13rsel defines the event of signal t13hr that can set the run bit t13r by hw. 00 b the external setting of t13r is disabled. 01 b bit t13r is set if a rising edge of signal t13hr is detected. 10 b bit t13r is set if a fallin g edge of si gnal t13hr is detected. 11 b bit t13r is set if an edge of signal t13hr is detected. 0 7, [31:12] r reserved; returns 0 if read; should be written with 0; 1) example: if the timer t13 is intended to start at any compare event on t12 (t13tec=100) the trigger event direction can be programmed to - counting up >> a t12 channel 0, 1, 2 compare match triggers t13r only while t12 is counting up - counting down >> a t12 channel 0, 1, 2 compare matc h triggers t13r only while t12 is counting down - independent from bit cdir >> each t12 channel 0, 1, 2 compare match triggers t13r the timer count direction is taken from the value of bi t cdir. as a result, if t12 is running in edge-aligned mode (counting up only), t13 can only be started automatically if bit field t13ted=01 or 11. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-53 v1.1, 2011-03 ccu6, v1.0 register tctr4 provides software-control (independent set and clear conditions) for the run bits t12r and t13r. furthermore, the timers can be reset (while running) and bits ste12 and ste13 can be controlled by software. reading these bits always returns 0. tctr4 timer control register 4 (78 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t13 std t13 str t13 cnt 0 t13 res t13 rs t13 rr t12 std t12 str t12 cnt 0 dt res t12 res t12 rs t12 rr www r wwwwww r wwww field bits type description t12rr 0w timer t12 run reset setting this bit clears the t12r bit. 0 b t12r is not influenced. 1 b t12r is cleared, t12 stops counting. t12rs 1w timer t12 run set setting this bit sets the t12r bit. 0 b t12r is not influenced. 1 b t12r is set, t12 starts counting. t12res 2w timer t12 reset 0 b no effect on t12. 1 b the t12 counter register is cleared to zero. the switching of the output signals is according to the switching rules. setting of t12res has no impact on bit t12r. dtres 3w dead-time counter reset 0 b no effect on the dead-time counters. 1 b the three dead-time counter channels are cleared to zero. t12cnt 5w timer t12 count event 0 b no action 1 b if enabled (pisel2), timer t12 counts one step. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-54 v1.1, 2011-03 ccu6, v1.0 note: a simultaneous write of a 1 to bits that set and clear the same bit will trigger no action. the corresponding bit will remain unchanged. t12str 6w timer t12 shadow transfer request 0 b no action 1 b ste12 is set, enabling the shadow transfer. t12std 7w timer t12 shadow transfer disable 0 b no action 1 b ste12 is cleared without triggering the shadow transfer. t13rr 8w timer t13 run reset setting this bit clears the t13r bit. 0 b t13r is not influenced. 1 b t13r is cleared, t13 stops counting. t13rs 9w timer t13 run set setting this bit sets the t13r bit. 0 b t13r is not influenced. 1 b t13r is set, t13 starts counting. t13res 10 w timer t13 reset 0 b no effect on t13. 1 b the t13 counter register is cleared to zero. the switching of the output signals is according to the switching rules. setting of t13res has no impact on bit t13r. t13cnt 13 w timer t13 count event 0 b no action 1 b if enabled (pisel2), timer t13 counts one step. t13str 14 w timer t13 shadow transfer request 0 b no action 1 b ste13 is set, enabling the shadow transfer. t13std 15 w timer t13 shadow transfer disable 0 b no action 1 b ste13 is cleared without triggering the shadow transfer. 0 4, [12:11] , [31:16] r reserved; returns 0 if read; should be written with 0; field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-55 v1.1, 2011-03 ccu6, v1.0 29.3 operating timer t13 timer t13 is implemented similarly to timer t12, but only with one channel in compare mode. a 16-bit up-counter is connected to a channel register via a comparator, that generates a signal when the counter contents ma tch the contents of the channel register. a variety of control functions facilitate the adaptation of the t13 structure to different application needs. in addition, t13 can be st arted synchronously to timer t12 events. this section provides information about: ? t13 overview (see section 29.3.1 ) ? counting scheme (see section 29.3.2 ) ? compare mode (see section 29.3.3 ) ? compare output path (see section 29.3.4 ) ? shadow register transfer (see section 29.3.5 ) ? t13 counter register description (see section 29.3.6 ) figure 29-23 overview diagram of the timer t13 block 29.3.1 t13 overview figure 29-24 shows a detailed block diagram of timer t13. the functions of the timer t12 block are controlled by bits in registers tctr0 , tctr2 , and pisel2 . timer t13 receives its input clock, f t13 , from the module clock f cc6 via a programmable prescaler and an optional 1/256 divider or from an input signal t13hr. t13 can only count up (similar to the edge-aligned mode of t12). via a comparator, the timer t13 counter register t13 is connected to the period register t13pr . this register determines the maxi mum count value for t13. when t13 reaches the period value, signal t13_pm (t13 period match) is generated and t13 is cleared to 0000 h with the next t13 clock edge. the period register receives a new period value from its shadow period register, t13ps, that is loaded via software. the transfer of a new period value from the shadow register into t13pr is controlled via the ?t13 shadow transfer? control signal, t13_st. the generation of this signal depends on the associated control bit ste13. providing a shadow register for the period value as ccu6_mca 05526 t13hr capture/compare channel cc63 cc63st timer t13 logic state bit to output modulation input and control/status logic synchronization to t12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-56 v1.1, 2011-03 ccu6, v1.0 well as for other values related to the generation of the pwm signal facilitates a concurrent update by software for all relevant parameters (refer to table 29.3.5 ). another signal indicates whether the counter contents are equal to 0000 h (t13_zm). a single-shot control bit, t13ssc, enables an automatic stop of the timer when the current counting period is finished (see figure 29-26 ). figure 29-24 t13 counter logic and period comparators the start or stop of t13 is controlled by the run bit, t13r. this control bit can be set by software via the associat ed set/clear bits t13rs or t13rr in register tctr4 , or it is cleared by hardware according to presel ected conditions (single-shot mode). the timer t13 run bit t13r must not be set while the applied t13 period value is zero. bit t13r can be set automatically if an event of t12 is detected to synchronize t13 timings to t12 events, e.g. to generate a programmable delay via t13 after an edge of a t12 compare channel before triggering an ad conversion (t13 can trigger adc ccu6_mca 05527 comp. = ? period register period shadow register t13_pm counter register t13 write to t13pr read from t13pr t13_zm = 0000 h t13_st f t13 edge detection t13hr t13pre t13clk iscnt13 t13std t13str t13rr t13rs t13r t13res t13ssc t13 control & status ste13 edge detection t13rsel t13cnt sync. to t12 f cc6 256 n clock selection www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-57 v1.1, 2011-03 ccu6, v1.0 conversions). timer t13 can be cleared to 0000 h via control bit t13res. setting this write-only bit only clears the timer contents, but has no further effects, e.g., it does not stop the timer. the generation of the t13 shadow transfer control signal, t13_st, is enabled via bit ste13. this bit can be set or cleared by software indirectly through its associated set/reset control bits t13str and t13std. two bit fields, t13tec and t13ted, control the synchronization of t13 to timer t12 events. t13tec selects the trigger event, while t13ted determines for which t12 count direction the trigger should be active. while timer t13 is running, write accesses to the count register t13 are not taken into account. if t13 is stopped, write actions to register t13 are immediately taken into account. note: the t13 period register and its associated shadow register are located at the same physical address. a write access to this address targets the shadow register, while a read access reads from the actual period register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-58 v1.1, 2011-03 ccu6, v1.0 29.3.2 t13 counting scheme this section describes the clocking and the counting capabilities of t13. 29.3.2.1 clock selection in timer mode ( pisel2 . iscnt13 = 00 b ), the input clock f t13 of timer t13 is derived from the internal module clock f cc6 through a programmable prescaler and an optional 1/256 divider. the resulting prescaler factors are listed in table 29-6 . the prescaler of t13 is cleared while t13 is not running ( tctr0 .t13r = 0) to ensure reproducible timings and delays. in counter mode , timer t13 counts one step: ? if a 1 is written to tctr4 .t13cnt and pisel2 .iscnt13 = 01 b ? if a rising edge of input signal t13hr is detected and pisel2 .iscnt13 = 10 b ? if a falling edge of input signal t13hr is detected and pisel2 .iscnt13 = 11 b table 29-6 timer t13 input clock options t13clk resulting input clock f t13 prescaler off (t13pre = 0) resulting input clock f t13 prescaler on (t13pre = 1) 000 b f cc6 f cc6 / 256 001 b f cc6 / 2 f cc6 / 512 010 b f cc6 / 4 f cc6 / 1024 011 b f cc6 / 8 f cc6 / 2048 100 b f cc6 / 16 f cc6 / 4096 101 b f cc6 / 32 f cc6 / 8192 110 b f cc6 / 64 f cc6 / 16384 111 b f cc6 / 128 f cc6 / 32768 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-59 v1.1, 2011-03 ccu6, v1.0 29.3.2.2 t13 counting the period of the timer is determined by the value in the period register t13pr according to the following formula: t13 per = TC1798 capture/compare unit 6 (ccu6) users manual 29-60 v1.1, 2011-03 ccu6, v1.0 29.3.2.3 single-shot mode in single-shot mode, the timer run bit t13r is cleared by hardware. if bit t13ssc = 1, the timer t13 will stop when the current timer period is finished. figure 29-26 single-shot operation of timer t13 0 ccu6_mct05529 compare value period value f t13 cc63st t13ssc t13 count t13r www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-61 v1.1, 2011-03 ccu6, v1.0 29.3.2.4 synchron ization to t12 timer t13 can be synchronized to a t12 ev ent. bit fields t13tec and t13ted select the event that is used to start timer t13. the selected event sets bit t13r via hw, and t13 starts counting. combined with the singl e-shot mode, this feature can be used to generate a programmable delay after a t12 event. figure 29-27 shows an example for the synchronization of t13 to a t12 event. here, the selected event is a compare-match (compare value = 2) while counting up. the clocks of t12 and t13 can be different (other prescaler factor); the figure shows an example in which t13 is clocked with half the frequency of t12. figure 29-27 synchronization of t13 to t12 compare match bit field t13tec selects the trigger event to start t13 (automatic set of t13r for synchronization to t12 compare signals) according to the combinations shown in table 29-7 . bit field t13ted additionally specifie s for which count direction of t12 the selected trigger event should be regarded (see table 29-8 ). zero compare value compare-match period value ccu6_mct05530 f t12 t13r t13 count f t13 t12 count www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-62 v1.1, 2011-03 ccu6, v1.0 table 29-7 t12 trigger event selection t13tec selected event 000 b none 001 b t12 compare event on channel 0 (cm_cc60) 010 b t12 compare event on channel 1 (cm_cc61) 011 b t12 compare event on channel 2 (cm_cc62) 100 b t12 compare event on any channel (0, 1, 2) 101 b t12 period-match (t12_pm) 110 b t12 zero-match while counting up (t12_zm and cdir = 0) 111 b any hall state change table 29-8 t12 trigger event additional specifier t13ted selected event specifier 00 b reserved, no action 01 b selected event is active while t12 is counting up (cdir = 0) 10 b selected event is active while t12 is counting down (cdir = 1) 11 b selected event is active independently of the count direction of t12 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-63 v1.1, 2011-03 ccu6, v1.0 29.3.3 t13 compare mode associated with timer t13 is one compare channel, that can perform compare operations with regard to t he contents of the t13 counter. figure 29-23 gives an overview on the t13 cha nnel in compare mode. the channel is connected to the t13 counter register via an equal-to comparator, generating a compare match signal when the contents of the counter matches the contents of the compare register. the channel consists of the comparator an d a double register structure - the actual compare register, cc63r , feeding the comparator, and an associated shadow register, cc63sr , that is preloaded by software and transferred into the compare register when signal t13 shadow transfer, t13_st, gets ac tive. providing a shadow register for the compare value as well as for other values related to the generation of the pwm signal facilitates a concurrent update by software for all relevant parameters. associated with the channel is a state bit, cmpstat .cc63st, holding the status of the compare operation. figure 29-28 gives an overview on the logic for the state bit. figure 29-28 t13 state bit block diagram a compare interrupt event cm_63 is signaled when a compare match is detected. the actual setting of a state bit has no influence on the interrupt generation. the inputs to the switching rule logic for the cc63st bit are the timer run bit (t13r), the timer zero-match signal (t13_zm), and the ac tual individual compare-match signal cm_63. in addition, the state bit can be set or cleared by software via bits mcc63s and ccu6_mcb05532 switching rule logic state bit cc63st cm_63 to interrupt control to state selection and output modulation t13_zm mcc63s/r t13r comp. = ? compare register cc63r compare shadow register cc63sr t13_st counter register t13 f t13 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-64 v1.1, 2011-03 ccu6, v1.0 mcc63r in register cmpmodif . a modification of the state bit cc63st by hardware is only possible while timer t13 is running (t13r = 1). if this is the case, the following switching rules apply for setting and resetting the state bit in compare mode: state bit cc63st is set to 1 ? with the next t13 clock ( f t13 ) after a compare-match (t13 is always counting up) (i.e., when the counter is incremented above the compare value); ? with the next t13 clock ( f t13 ) after a zero-match and a parallel compare-match. state bit cc63st is cleared to 0 ? with the next t13 clock ( f t13 ) after a zero-match and no parallel compare-match. figure 29-29 t13 compare operation ccu6_mct05533 f t13 zero compare value cc63st compare-match compare-match period value t13 count www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-65 v1.1, 2011-03 ccu6, v1.0 29.3.4 compare mode output path figure 29-30 gives an overview on the signal path from the channel state bit cc63st to its output pin cout63. as illustrated , a user can determine the desired output behavior in relation to the current state of cc63st. please refer to section 29.2.4.3 for detailed information on the output modulation for t12 signals. figure 29-30 channel 63 output path the output line cout63_o can generate a t13 pwm at the output pin cout63. the signal cc63_o can be used to modulate the t12-related output signals with a t13 pwm. in order to decouple cout63 from the inter nal modulation, the compare state leading to an active signal can be selected independently by bits t13im and cout63ps. the last block of the data path is the output modulation block. here, the modulation source t13 and the trap functionality are co mbined and control the actual level of the output pin cout63 (see figure 29-31 ): ?the t13 related compare signal cout63_o delivered by the t13 state selection with the enable bit modctr .ect13o ?the trap state trps with an individual enable bit trpctr .trpen13 if the modulation input signal cout63_o is enabled (ect13o = 1) and is at passive state, the modulated is also in passive state. if the modulation input is not enabled, the output is in passive state. if the trap state is active (trps = 1), then the output enabled for the trap signal (by trpen13 = 1) is set to the passive state. the output of the modulation control block is connected to a level select block. it offers the option to determine the actual output level of a pin, depending on the state of the output line (decoupling of active/passive state and output polarity) as specified by the passive state select bit pslr .psl63. if the modulated output signal is in the passive ccu6_mca 05534 level select cout63 cout63_o cc63_o t13 state selection cc63st cc63st t13im cout63ps t12 output modulation psl63 output level selection t13 state bit cc63st ect13o t13 output modulation output modulation www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-66 v1.1, 2011-03 ccu6, v1.0 state, the level specified directly by psl63 is output. if it is in the active state, the inverted level of psl63 is output. this allows the user to adapt the polarity of an active output signal to the connected circuitry. the psl63 bit has a shadow register to allo w for updates with the t13 shadow transfer signal (t13_st) without undesired pulses on t he output lines. a read action returns the actually used value, whereas a write acti on targets the shadow bit. providing a shadow register for the psl value as well as for other values related to the generation of the pwm signal facilitates a concurrent update by software for all relevant parameters. figure 29-31 t13 ou tput modulation 29.3.5 t13 shadow register transfer a special shadow transfer signal (t13_st) c an be generated to facilitate updating the period and compare values of the compare channel cc63 synchronously to the operation of t13. providing a shadow regi ster for values defining one pwm period facilitates a concurrent update by software for all relevant parameters. the next pwm period can run with a new set of parameters. the generation of this signal is requested by software via bit tctr0 .ste13 (set by writing 1 to the write-only bit tctr4 .t13str, cleared by writing 1 to the write-only bit tctr4 .t13std). when signal t13_st is active, a shadow regist er transfer is triggered with the next cycle of the t13 clock. bit ste13 is automatically cleared with the shadow register transfer. a t13 shadow register transfer takes place (t13_st active): ? while timer t13 is not running (t13r = 0), or ? ste13 = 1 and a period-match is detected while t13r = 1 ccu6_mca05545 cout63 output modulation cout63 trpen13 psl63 active passive t13 block cout63_o ect13o trps trap handling block level selection www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-67 v1.1, 2011-03 ccu6, v1.0 figure 29-32 t13 shadow register overview ccu6_mca05547 compare register cc63r compare shadow register cc63sr period register t13pr period shadow register t13pr t13im t13im shadow psl63 psl63 shadow cc63ps cc63ps shadow t13_st write read read read read write write write read write read www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-68 v1.1, 2011-03 ccu6, v1.0 29.3.6 t13 rela ted registers 29.3.6.1 t13 counter register the generation of the patterns for a single channel pulse width modulation (pwm) is based on timer t13. the registers related to timer t13 can be concurrently updated (with well-defined conditions) in order to ensure consistency of the pwm signal. t13 can be synchronized to severa l timer t12 events. timer t13 only supports compare mode on its compare channel cc63. register t13 represents the counting value of timer t13. it can only be written while the timer t13 is stopped. write actions while t 13 is running are not taken into account. register t13 can always be read by sw. timer t13 only supports edge-aligned mode (counting up). note: while timer t13 is stopped, the internal clock divider is reset in order to ensure reproducible timings and delays. t13 timer t13 counter register (50 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t13cv rwh field bits type description t13cv [15:0] rwh timer 13 counter value this register represents the 16-bit counter value of timer13. 0 [31:16] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-69 v1.1, 2011-03 ccu6, v1.0 29.3.6.2 period register register t13pr contains the period value fo r timer t13. the period value is compared to the actual counter value of t13 and the resulting counter actions depend on the defined counting rules. this register has a shadow register and the shadow transfer is controlled by bit ste13. a read action by sw delivers the value currently used for the compare action, whereas the write action tar gets a shadow register. the shadow register structure allows a concurrent update of all t13-related values. t13pr timer 13 period register (54 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t13pv rwh field bits type description t13pv [15:0] rwh t13 period value the value t13pv defines the counter value for t13 leading to a period-match. when reaching this value, the timer t13 is set to zero. 0 [31:16] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-70 v1.1, 2011-03 ccu6, v1.0 29.3.6.3 compare register registers cc63r is the actual compare register for t13. the values stored in cc63r is compared to the counter value of t13. the state bit cc63st is located in register cmpstat . cc63r compare register for t13 (58 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 ccv rh field bits type description ccv [15:0] rh channel cc63 compare value the bit field ccv contains the value, that is compared to the t13 counter value. 0 [31:16] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-71 v1.1, 2011-03 ccu6, v1.0 29.3.6.4 compare shadow register the register cc63r can only be read by sw, the modification of the value is done by a shadow register transfer from register cc63sr. the corresponding shadow register cc63sr can be read and written by sw. cc63sr compare shadow register for t13 (5c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 ccs rw field bits type description ccs [15:0] rw shadow register for channel cc63 compare value the bit field contents of ccs is transferred to the bit field ccv during a shadow transfer. 0 [31:16] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-72 v1.1, 2011-03 ccu6, v1.0 29.4 synchronous start feature the t12 and t13 timers can be started synchronously through the t12hr and t13hr inputs of all ccu6x kernels. figure 29-33 synchronization concept edge selection by t12rsel t12r set edge selection by t13rsel t13r set ccu60 t13hr t12hr edge selection by t12rsel t12r set edge selection by t13rsel t13r set ccu61 t13 h r t12 h r ccu6_sync_start synchronous start www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-73 v1.1, 2011-03 ccu6, v1.0 29.5 trap handling the trap functionality permits the pwm outputs to react on the state of the input signal ctrap . this functionality can be used to switch off the power devices if the trap input becomes active (e.g. to perform an emergency stop). the trap handling and the effect on the output modulation are controlled by the bits in the trap control register trpctr . the trap flags trpf and trps are located in register is and can be set/cleared by sw by writing to registers iss and isr . figure 29-34 gives an overview on the trap function. the trap flag trpf monitors the trap input and initiates the entry into the trap state. the trap state bit trps determines the effect on the outputs and controls the exit of the trap state. when a trap condition is detected (ctrap = 0) and the input is enabled (trppen = 1), both, the trap flag trpf and the trap state bit trps, are set to 1 (trap state active). the output of the trap state bit trps leads to the output modulation blocks (for t12 and for t13) and can there deactivate the outputs (set them to the passive state). individual enable control bits for each of the six t12-related outputs and the t13-related output facilitate a flexible adaptation to the application needs. there are a number of different ways to exit the trap state. this offers sw the option to select the best operation for the application. exiting the trap state can be done either immediately when the trap condition is removed (ctrap = 1 or trppen = 0), or under software control, or synchronously to the pwm generated by either timer t12 or timer t13. figure 29-34 trap logic block diagram ccu6_mcb05541 _32bit trap entry / exit control to t12, t13 output modulation ctrap trppen trpm2 trpf rtrpf strpf trap exit synchro- nization trpm0/1 trps t12 _z m t13 _z m www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-74 v1.1, 2011-03 ccu6, v1.0 clearing of trpf is controlled by the mode control bit trpm2. if trpm2 = 0, trpf is automatically cleared by hw when ctrap returns to the inactive level (ctrap =1) or if the trap input is disabled (trppen = 0). when trpm2 = 1, trpf must be reset by sw after ctrap has become inactive. clearing of trps is controlled by the mode control bits trpm1 and trpm0 (located in the trap control register trpctr). a reset of trps terminates the trap state and returns to normal operation. there are three options selected by trpm1 and trpm0. one is that the trap state is left immedi ately when the trap flag trpf is cleared, without any synchronization to timers t12 or t13. the other two options facilitate the synchronization of the termination of the trap state to the count periods of either timer t12 or timer t13. figure 29-35 gives an overview on the associated operation. figure 29-35 trap state synchronization (with trpm2 = 0) ccu6_mct 05542 t12 count t13 count trpf trps trps trps ctrap active sync. to t12 sync. to t13 no sync. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-75 v1.1, 2011-03 ccu6, v1.0 29.6 multi-channel mode the multi-channel mode offers the possibility to modulate all six t12-related output signals with one instruction. the bits in bit field mcmout .mcmp are used to specify the outputs that may become active. if multi-channel mode is enabled (bit modctr .mcmen = 1), only those outputs may become active, that have a 1 at the corresponding bit position in bit field mcmp. this bit field has its own shadow bit field mcmouts .mcmps, that can be written by software. the transfer of the new value in mcmps to the bit field mcmp can be triggered by, and synchronized to, t12 or t13 events. th is structure permits th e software to write the new value, that is then taken into account by the hardware at a well-defined moment and synchronized to a pwm signal. this avoids unintended pulses due to unsynchronized modulation sources. figure 29-36 multi-channel mode block diagram figure 29-36 shows the functional blocks for the mu lti-channel operati on, controlled by bit fields in register mcmctr . the event that triggers the update of bit field mcmp is chosen by swsel. in order to synchronize the update of mcmp to a pwm generated by t12 or t13, bit field swsyn allows the selection of the synchronization event leading to the transfer from mcmps to mcmp. due to this structure, an update takes place with a new pwm period. a reminder flag r is set when the selected switching event occurs ccu6_mcb 05535+ switching synchro- nization shadow register mcmouts.mcmps shadow transfer mcm_st register mcmout.mcmp t12 output modulation outputs cc6x/cout6x t12_zm t13_zm t12_pm cm_61 t12_om t13_pm cm_che swsel cdir swsyn strmcm switching event detection r set clear str set to interrupt control clear idle t12/t13 shadow transfer control t13_st t12_st ste12u ste12d ste13u www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-76 v1.1, 2011-03 ccu6, v1.0 (the event is not necessarily synchronous to the modulating pwm), and is cleared when the transfer takes place. this flag can be monitored by software to check for the status of this logic block. if the shadow transfer from mcmps to mcmp takes place, bit is .str becomes set and an interrupt can be generated. in addition to the multi-channel shadow transfer event mcm_st, the shadow transfers for t12 (t12_st) and t13 (t13_st) can be generated to allow concurrent updates of applied duty cycles for t12 and/or t13 modulation and multi-channel patterns. if it is explicitly desired, the update takes place immediately with the occurrence of the selected event when the direct synchronization mode is selected. the update can also be requested by software by writing to bit field mcmps with the shadow transfer request bit strmcm = 1. the option to trigger an update by sw is possible for all settings of swsel. by using the direct mode and bit strmcm = 1, the update takes place completely under software control. table 29-9 multi-channel mode switching event selection swsel selected event (see register mcmctr ) 000 b no automatic event detection 001 b correct hall event (cm_che) detected at input signals ccposx without additional delay 010 b t13 period-match (t13_pm) 011 b t12 one-match while counting down (t12_om and cdir = 1) 100 b t12 compare channel 1 event while counting up (cm_61 and cdir = 0) to support the phase delay function by cc61 for block commutation mode. 101 b t12 period-match while counting up (t12_pm and cdir = 0) 110 b , 111 b reserved, no action table 29-10 multi-channel mode switching synchronization swsyn synchronization event (see register mcmctr ) 00 b direct mode: the trigger event directly causes the shadow transfer 01 b t13 zero-match (t13_zm), the mcm shadow transfer is synchronized to a t13 pwm 10 b t12 zero-match (t12_zm), the mcm shadow transfer is synchronized to a t12 pwm 11 b reserved, no action www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-77 v1.1, 2011-03 ccu6, v1.0 29.7 hall sensor mode for brushless dc-motors in block commutation mode, the multi-channel mode has been introduced to provide efficient means for switching pattern generation. these patterns need to be output in relation to the angular position of the motor. for this, usually hall sensors or back-emf sensing are used to determine the angular rotor position. the ccu6 provides three inputs, ccpos0, ccpos1, and ccpos2, that can be used as inputs for the hall sensors or the back-emf detection signals. there is a strong correlation between the motor position and the output modulation pattern. when a certain position of the motor has been reached, indicated by the sampled hall sensor inputs (the hall pattern), the next, pre-determined multi-channel modulation pattern has to be output. because of different machine types, the modulation pattern for driving the motor can vary. therefore, it is wishful to have a wide flexibility in defining the correlation between the hall pattern and the corresponding modulation pattern. furthermore, a hardware mechanism significantly reduces the cpu for block- commutation. the ccu6 offers the flexibility by having a r egister containing the currently assumed hall pattern (curh), the next expected hall patte rn (exph) and the corresponding output pattern (mcmp). a new modulation pattern is output when the sampled hall inputs match the expected ones (exph). to detect the next rotation phase (segment for block commutation), the ccu6 monitors the hall inputs for changes. when the next expected hall pattern is detected, the next corresponding modulation pattern is output. to increase for noise immunity (to a certain extend), the ccu6 offers the possibility to introduce a sampling delay for the hall inputs. some changes of the hall inputs are not leading to the expected hall pattern, because they are only short spikes due to noise. the hall pattern compare logic compares t he hall inputs to the next expected pattern and also to the currently assumed pattern to filter out spikes. for the hall and modulation output patterns, a double-register structure is implemented. while register mcmout holds the actually used values, its shadow register mcmouts can be loaded by software from a pre-defin ed table, holding the appropriate hall and modulation patterns for the given motor control. a transfer from the shadow register into register mcmout can take place when a correct hall pattern change is detected. software can then load the next values into register mcmouts. it is also possible by software to force a transfer from mcmouts into mcmout. note: the hall input signals ccposx and the curh and exph bit fields are arranged in the following order: ccpos0 corresponds to curh.0 (lsb) and exph.0 (lsb) ccpos1 corresponds to curh.1 and exph.1 ccpos2 corresponds to curh.2 (msb) and exph.2 (msb) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-78 v1.1, 2011-03 ccu6, v1.0 29.7.1 hall pattern evaluation the hall sensor inputs ccposx can be permanently monitored via an edge detection block (with the module clock f cc6 ). in order to suppress spikes on the hall inputs due to noise in rugged inverter environment, two opt ional noise filtering methods are supported by the hall logic (both methods can be combined). ? noise filtering with delay: for this function, the mode control bit fi elds msel6x for all t12 compare channels must be programmed to 1000 b and dbyp = 0. the selected event triggers dead- time counter 0 to generate a programmabl e delay (defined by bit field dtm). when the delay has elapsed, the evaluation signal hcrdy becomes activated. output modulation with t12 pwm signals is not possible in this mode. ? noise filtering by synchronization to pwm: the hall inputs are not permanently monitored by the edge detection block, but samples are taken only at defined points in time during a pwm period. this can be used to sample the hall inputs when the switching noise (due to pwm) does not disturb the hall input signals. if neither the delay function of dead-time counter 0 is not used for the hall pattern evaluation nor the hall mode for brushless dc-drive control is enabled, the timer t12 block is available for pwm generation and output modulation. figure 29-37 hall pa ttern evaluation if the evaluation signal hcrdy (hall compare ready, see figure 29-38 ) becomes activated, the hall inputs are sampled and the hall compare logic starts the evaluation of the hall inputs. ccu6_mcb 05553 edge detect hall compare logic hcrdy ccpos 0..2 cm_61 t12_om t12_pm t13_pm cm_63 dead-time counter 0 hall inputs delay bypass dbyp hsync event selection cdir hall pattern evaluation f cc6 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-79 v1.1, 2011-03 ccu6, v1.0 figure 29-37 illustrates the events for hall pattern evaluation and the noise filter logic, table 29-11 summarizes the selectable trigger input signals. table 29-11 hall sensor mode trigger event selection hsync selected event (see register t12msel ) 000 b any edge at any of the inputs ccposx, independent from any pwm signal (permanent check). 001 b a t13 compare-match (cm_63). 010 b a t13 period-match (t13_pm). 011 b hall sampling triggered by hw sources is switched off. 100 b a t12 period-match while counting up (t12_pm and cdir = 0). 101 b a t12 one-match while counting down (t12_om and cdir = 1). 110 b a t12 compare-match of compare channel cc61 while counting up (cm_61 and cdir = 0). 111 b a t12 compare-match of compare channel cc61 while counting down (cm_61 and cdir = 1). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-80 v1.1, 2011-03 ccu6, v1.0 29.7.2 hall pattern compare logic figure 29-38 gives an overview on the double-register structure and the pattern compare logic. software writes the nex t modulation pattern (mcmps) and the corresponding current (curhs ) and expected (exphs) hall patterns into the shadow register mcmouts. register mcmout holds the actually used values curh and exph. the modulation pattern mcmp is provid ed to the t12 output modulation block. the current (curh) and expected (exph) hall patterns are compared to the sampled hall sensor inputs (v isible in register cmpstat ). sampling of the inputs and the evaluation of the comparator outputs is trig gered by the evaluation signal hcrdy (hall compare ready), that is detailed in the next section. figure 29-38 hall pattern compare logic ? if the sampled hall pattern matches the value programmed in curh, the detected transition was a spike (no hall event) and no further actions are necessary. ? if the sampled hall pattern matches t he value programmed in exph, the detected transition was the expected event (correct hall event cm_che) and the mcmp value has to change. ? if the sampled hall pattern matches nei ther curh nor exph, the transition was due to a major error (wrong hall event cm_cwe) and can lead to an emergency shut down (idle). ccu6_mca05536 cm_che cm_whe mcmps exph curh hcrdy ccpos0..2 curhs exphs hp_st mcm_st sw write sw write sw write mcmp hall inputs hall pattern evaluation multi-channel mode logic pattern compare sample hall compare logic clear t12 output modulation idle www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-81 v1.1, 2011-03 ccu6, v1.0 at every correct hall event (cm_che), the next hall patterns are transferred from the shadow register mcmouts in to mcmout (hall pattern shadow transfer hp_st), and a new hall pattern with its corresponding output pattern can be loaded (e.g. from a predefined table in memory) by software into mcmouts. for the modulation patterns, signal mcm_st is used to trigger the transfer. loading this shadow register can also be done by writing mcmouts.strhp = 1 (for exph and curh) or mcmouts.strmcmp = 1 (for mcmp). 29.7.3 hall mode flags depending on the hall pattern compare operation, a number of flags are set in order to indicate the status of the module and to trigger further actions and interrupt requests. flag is .che (correct hall event) is set by signal cm_che when the sampled hall pattern matches the expected one (exph). this flag can also be set by sw by setting bit iss .sche = 1. if enabled by bit ien .enche = 1, the set signal for che can also generate an interrupt request to the cpu. bit field inp .inpche defines which service request output becomes activated in case of an interrupt request.to clear flag che, sw needs to write isr .rche = 1. flag is.whe indicates a wrong hall event. its handling for flag setting and resetting as well as interrupt request generation are similar to the mechanism for flag che. the implementation of flag str is done in the same way as for che and whe. this flag is set by hw by the shadow transfer signal mcm_st (see also figure 29-36 ). please note that for flags che, whe, and str, the interrupt request generation is triggered by the set signal for the flag. that means, a request can be generated even if the flag is already set. there is no need to clear the flag in order to enable further interrupt requests. the implementation for the idle flag is different. it is set by hw through signal cm_whe if enabled by bit enidle. software can also set the flag via bit sidle. as long as bit idle is set, the modulation pattern field mcmp is cleared to force the outputs to the passive state. flag idle must be cleared by software by writing ridle = 1 in order to return to normal operation. to fully restart from idle mode, the transfer requests for the bit fields in register mcmouts to re gister mcmout have to be initiated by software via bits strmcm and strhp in register mcmouts. in this way, the release from idle mode is under software control, but can be performed synchronously to the pwm signal. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-82 v1.1, 2011-03 ccu6, v1.0 figure 29-39 hall mode flags ccu6_mca05540 set cm_che che clear set rche sche enche set cm_whe whe clear rwhe swhe sidle idle ridle clear mcmp clear hall compare logic enidle enwhe >1 _ >1 _ >1 _ inperr inpche to sr0 to sr1 to sr2 to sr3 to sr0 to sr1 to sr2 to sr3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-83 v1.1, 2011-03 ccu6, v1.0 29.7.4 hall mode for brushless dc-motor control the ccu6 provides a mode for the timer t12 block especially targeted for convenient control of block commutation patterns for brushless dc-motors. this mode is selected by setting all t12msel .msel6x bit fields of the three t12 channels to 1000 b . in this mode, illustrated in figure 29-40 , channel cc60 is placed in capture mode to measure the time elapsed between the last two correct hall events, channel cc61 in compare mode to provide a programmable phase delay between the hall event and the application of a new pwm output pattern, and channel cc62 also in compare mode as first time-out criterion. a second time-out criterion can be built by the t12 period match event. figure 29-40 t12 block in hall sensor mode the signal cm_che from the hall compare l ogic is used to transfer the new compare values from the shadow registers cc6xsr into the actual compare registers cc6xr, performs the shadow transfer for the t12 period register, to capture the current t12 contents into register cc60r, and to clear t12. note: in this mode, the shadow transfer signal t12_st is not generated. not all shadow bits, such as the psly bits, will be transferre d to their main registers. to program the main registers, sw needs to writ e to these registers while timer t12 is stopped. in this case, a sw wr ite actualizes both registers. ccu6_mca0 5538 comp. = ? compare register cc61r compare shadow register cc61sr comp. = ? compare register cc62r compare shadow register cc62sr counter register t12 f t12 cm_che clear cm_61 cm_62 capture register cc60r hall compare logic www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-84 v1.1, 2011-03 ccu6, v1.0 figure 29-41 brushless dc-motor control example (all msel6x = 1000 b ) after the detection of an expected hall pattern (cm_che active), the t12 count value is captured into channel cc60 (representing the actual rotor speed by measuring the elapsed time between the last two correct hall events), and t12 is reset. when the timer reaches the compare value in channel cc61, the next multi-channel state is switched by triggering the shadow transfer of bit field mcmp (if enabled in bit field swen ). this trigger event can be combined with the synchronization of the next multi-channel state to the pwm source (to avoid spikes on the output lines, see section 29.6 ). this compare function of channel cc61 can be used as a phase delay from the position sensor input signals to the switching of the output signals, that is necessary if a sensorless back-emf technique or hall sensors are used. the compare value in channel cc62 can be used as a time-out trigger (interrupt), indicating that the actual motor speed is far below the desired destination value. an abnormal load change can be detected with this feature and pwm generation can be disabled. ccu6_mct05539 cout6y cc62 comp. cc6x mcmp exph curh = 011 = 001 = 110 = 010 = 100 = 001 = 101 = 010 = 011 = 110 ccpos210001 ccpos100111 ccpos0 1 1 1 00 0000 h cc61 comp. t12 count hall event captures and resets t12 cc62 compare for time-out cc61 compare for phase delay phase delay www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-85 v1.1, 2011-03 ccu6, v1.0 29.8 modulation control registers 29.8.1 modulation control this register contains bits enabling the modulation of the corresponding output signal by pwm pattern generated by the timers t12 and t13. furthermore, the multi-channel mode can be enabled as additional modulation source for the output signals. modctr modulation control register (80 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 ect 13o 0 t13moden mcm en 0 t12moden rw r rw rw r rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-86 v1.1, 2011-03 ccu6, v1.0 field bits type description t12moden [5:0] rw t12 modulation enable these bits enable the modulation of the corresponding output signal by a pwm pattern generated by timer t12. t12moden0 = modctr.0 for output cc60 t12moden1 = modctr.1 for output cout60 t12moden2 = modctr.2 for output cc61 t12moden3 = modctr.3 for output cout61 t12moden4 = modctr.4 for output cc62 t12moden5 = modctr.5 for output cout62 0 b the modulation of the corresponding output signal by a t12 pwm pattern is disabled. 1 b the modulation of the corresponding output signal by a t12 pwm pattern is enabled. mcmen 7rw multi-channel mode enable 0 b the modulation of the corresponding output signal by a multi-channel pattern according to bit field mcmout is disabled. 1 b the modulation of the corresponding output signal by a multi-channel pattern according to bit field mcmout is enabled. t13moden [13:8] rw t13 modulation enable these bits enable the modulation of the corresponding output signal by the pwm pattern cc63_o generated by timer t13. t13moden0 = modctr.8 for output cc60 t13moden1 = modctr.9 for output cout60 t13moden2 = modctr.10 for output cc61 t13moden3 = modctr.11 for output cout61 t13moden4 = modctr.12 for output cc62 t13moden5 = modctr.13 for output cout62 0 b the modulation of the corresponding output signal by a t13 pwm pattern is disabled. 1 b the modulation of the corresponding output signal by a t13 pwm pattern is enabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-87 v1.1, 2011-03 ccu6, v1.0 29.8.2 trap control register the register trpctr controls the trap functionality. it contains independent enable bits for each output signal and control bits to select the behavior in case of a trap condition. the trap condition is a low level on the ctrap input pin, that is monitored (inverted level) by bit is.trpf. while trpf=1 (trap input active), the trap state bit is.trps is set to 1. ect13o 15 rw enable compare timer t13 output 0 b the output cout63 is in the passive state. 1 b the output cout63 is enabled for the pwm signal generated by t13. 0 6, 14, [31:16] r reserved; returns 0 if read; should be written with 0. trpctr trap control register (84 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 trp pen trp en 13 trpen 0 trp m2 trp m1 trp m0 rw rw rw r rw rw rw field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-88 v1.1, 2011-03 ccu6, v1.0 field bits type description trpm1, trpm0 1, 0 rw trap mode control bits 1, 0 these two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has become inactive again. a synchronization to the timer driving the pwm pattern avoids unintended pulses when leaving the trap state. the combination [trpm1, trpm0] leads to: 00 b the trap state is left (return to normal operation) after trpf has become 0 again when a zero- match of t12 (while counting up) is detected (synchronization to t12). 01 b the trap state is left (return to normal operation) after trpf has become 0 again when a zero- match of t13 is detected (synchronization to t13). 10 b reserved 11 b the trap state is left (return to normal operation) immediately after trpf has become 0 again without any synchronization to t12 or t13. trpm2 2rw trap mode control bit 2 this bit defines how the trap flag trpf can be cleared after the trap input condition (ctrap = 0 and trppen = 1) is no longer va lid (either by ctrap =1 or by trppen = 0). 0 b automatic mode: bit trpf is cleared by hw if the trap input condition is no longer valid. 1 b manual mode: bit trpf stays 0 after the trap input condition is no longer valid. it has to be cleared by sw by writing isr.rtrpf = 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-89 v1.1, 2011-03 ccu6, v1.0 trpen [13:8] rw trap enable control setting a bit enables the trap functionality for the following corresponding output signals: trpen0 = trpctr.8 for output cc60 trpen1 = trpctr.9 for output cout60 trpen2 = trpctr.10 for output cc61 trpen3 = trpctr.11 for output cout61 trpen4 = trpctr.12 for output cc62 trpen5 = trpctr.13 for output cout62 0 b the trap functionality of the corresponding output signal is disabled. the output state is independent from bit is.trps. 1 b the trap functionality of the corresponding output signal is enabled. the output state is set to the passive while is.trps=1. trpen13 14 rw trap enable control for timer t13 0 b the trap functionality for output cout63 is disabled. the output state is independent from bit is.trps. 1 b the trap functionality for output cout63 is enabled. the output state is set to the passive while is.trps=1. trppen 15 rw trap pin enable this bit enables the input (pin) function for the trap generation. an interrupt can only be generated if a falling edge is detected at pin ctrap while trppen = 1. 0 b the ccu6 trap functionality based on the input ctrap is disabled. a ccu6 trap can only be generated by sw by setting bit trpf. 1 b the ccu6 trap functionality based on the input ctrap is enabled. a ccu6 trap can be generated by sw by setting bit trpf or by ctrap =0. 0 [7:3], [31:16] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-90 v1.1, 2011-03 ccu6, v1.0 29.8.3 passive state level register register pslr defines the passive state level of the pwm outputs of the module. the passive state level is the value that is driven during the passive state of the output. during the active state, the corresponding output pin drives the active state level, that is the inverted passive state level. the passive state level permits to adapt the driven output levels to the driver polarity (inverted, not inverted) of the connected power stage. the bits in this register have shadow bit fiel ds to permit a concurrent update of all pwm- related parameters (bit field psl is updated with t12_st, whereas psl63 is updated with t13_st). the actually used values can be read (attribute ?rh?), whereas the shadow bits can only be written (attribute ?w?). pslr passive state level register (88 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 psl 63 0psl r rwh r rwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-91 v1.1, 2011-03 ccu6, v1.0 29.8.4 multi-channel mode registers register mcmctr contains control bits for the multi-channel functionality. field bits type description psl [5:0] rwh compare outputs passive state level these bits define the passive level driven by the module outputs during the passive state. psl0 = pslr.0 for output cc60 psl1 = pslr.1 for output cout60 psl2 = pslr.2 for output cc61 psl3 = pslr.3 for output cout61 psl4 = pslr.4 for output cc62 psl5 = pslr.5 for output cout62 0 b the passive level is 0. 1 b the passive level is 1. psl63 7rwh passive state level of output cout63 this bit defines the passive level driven by the module output cout63 during the passive state. 0 b the passive level is 0. 1 b the passive level is 1. 0 6, [31:8] r reserved; returns 0 if read; should be written with 0. mcmctr multi-channel mode control register (94 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ste 13u ste 12d ste 12u 0 swsyn 0 swsel r rwrwrw r rw r rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-92 v1.1, 2011-03 ccu6, v1.0 field bits type description swsel [2:0] rw switching selection bit field swsel selects one of the following trigger request sources (next mult i-channel event) for the shadow transfer mcm_st fr om mcmps to mcmp. the trigger request is stored in the reminder flag r until the shadow transfer is done and flag r is cleared automatically with the shadow transfer. the shadow transfer takes place synchronously with an event selected in bit field swsyn. 000 b no trigger request will be generated 001 b correct hall pattern detected (cm_che) 010 b t13 period-match detected (while counting up) 011 b t12 one-match (while counting down) 100 b t12 channel 1 compare-match detected (phase delay function) 101 b t12 period match detected (while counting up) 110 b reserved, no trigger request will be generated 111 b reserved, no trigger request will be generated swsyn [5:4] rw switching synchronization bit field swsyn defines the synchronization mechanism of the shadow transfer event mcm_st if it has been requested before (flag r set by an event selected by swsel) and if mcmen = 1. this feature permits the synchronization of the outputs to the pwm source, that is used for modulation (t12 or t13). 00 b direct; the trigger event immediately leads to the shadow transfer 01 b a t13 zero-match triggers the shadow transfer 10 b a t12 zero-match (while counting up) triggers the shadow transfer 11 b reserved; no action ste12u 8rw shadow transfer enable for t12 upcounting this bit enables the shadow transfer t12_st if flag mcmout.r is set or becomes set while a t12 period match is detected while counting up. 0 b no action 1 b the t12_st shadow transfer mechanism is enabled if mcmen = 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-93 v1.1, 2011-03 ccu6, v1.0 ste12d 9rw shadow transfer enable for t12 downcounting this bit enables the shadow transfer t12_st if flag mcmout.r is set or becomes set while a t12 one match is detected while counting down. 0 b no action 1 b the t12_st shadow transfer mechanism is enabled if mcmen = 1. ste13u 10 rw shadow transfer enable for t13 upcounting this bit enables the shadow transfer t13_st if flag mcmout.r is set or becomes set while a t13 period match is detected. 0 b no action 1 b the t13_st shadow transfer mechanism is enabled if mcmen = 1. 0 3, [7:6], [31:11] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-94 v1.1, 2011-03 ccu6, v1.0 register mcmouts contains bits used as pa ttern input for the multi-channel mode and the hall mode. this register is a shadow register (that can be read and written) for register mcmout, indicating the currently active signals. mcmouts multi-channel mode output shadow register (8c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 str hp 0 curhs exphs str mcm 0mcmps wr rw rw wr rw field bits type description mcmps [5:0] rw multi-channel pwm pattern shadow bit field mcmps is the shadow bit field for bit field mcmp. the multi-channel shadow transfer is triggered by mcm_st according to the transfer conditions defined by register mcmctr. strmcm 7w shadow transfer request for mcmps writing strmcm = 1 leads to an immediate activation of mcm_st to update bit field mcmp by the value of mcmps. when read, this bit always delivers 0. 0 b no action. 1 b bit field mcmp is updated. exphs [10:8] rw expected hall pattern shadow bit field exphs is the shadow bit field for bit field exph. the shadow transfer takes place when a correct hall event is detected (cm_che). curhs [13:11] rw current hall pattern shadow bit field curhs is the shadow bit field for bit field curh. the shadow transfer takes place when a correct hall event is detected (cm_che). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-95 v1.1, 2011-03 ccu6, v1.0 strhp 15 w shadow transfer request for the hall pattern writing strhp = 1 leads to an immediate activation of hp_st to update bit fields exph and curh by exphs and curhs. when read, this bit always delivers 0. 0 b no action. 1 b bit fields exph and curh are updated. 0 6, 14 [31:16] r reserved; returns 0 if read; should be written with 0. mcmout multi-channel mode output register (90 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 curh exph 0 r mcmp r rh rh r rh rh field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-96 v1.1, 2011-03 ccu6, v1.0 field bits type description mcmp [5:0] rh multi-channel pwm pattern bit field mcmp defines the output pattern for the multi- channel mode. if this mode is enabled by modctr.mcmen = 1, the output state of all t12 related pwm outputs can be modified. this bit field is 0 while is.idle = 1. mcmp0 = mcmout.0 for output cc60 mcmp1 = mcmout.1 for output cout60 mcmp2 = mcmout.2 for output cc61 mcmp3 = mcmout.3 for output cout61 mcmp4 = mcmout.4 for output cc62 mcmp5 = mcmout.5 for output cout62 0 b the output is set to the passive state. a pwm generated by t12 or t13 are not taken into account. 1 b the output can be in the active state, depending on the enabled pwm modulation signals generated by t12, t13 and the trap state. r 6rh reminder flag this flag indicates that the shadow transfer from mcmps to mcmp has been requested by the selected trigger source. it is clea red when the shadow transfer takes place or while mcmen=0. 0 b a shadow transfer mcm_st is not requested. 1 b a shadow transfer mcm_st is requested, but has not yet been executed, because the selected synchronization condition has not yet occurred. exph [10:8] rh expected hall pattern bit field exph is updated by a shadow transfer hp_st from bit field exphs. if hcrdy = 1, exph is compared to the sampled ccposx inputs in order to detect the occurrence of the next desired (=expected) hall pattern or a wrong pattern. if the sampled hall pattern at the hall input pins is equal to bit field exph, a correct hall event has been detected (cm_che). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-97 v1.1, 2011-03 ccu6, v1.0 curh [13:11] rh current hall pattern bit field curh is updated by a shadow transfer hp_st from bit field curhs. if hcrdy = 1, curh is compared to the sampled ccposx inputs in order to detect a spike. if the sampled hall pattern at the hall input pins is equal to bit field curh, no hall event has been detected. if the sampled hall input pattern is neither equal to curh nor equal to exph, the hall event was not the desired one and may be due to a fatal error (e.g. blocked rotor, etc.). in this case, a wrong hall event has been detected (cm_whe). 0 7, [31:14] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-98 v1.1, 2011-03 ccu6, v1.0 29.9 interrupt handling this section describes the interrupt handling of the ccu6 module. 29.9.1 interrupt structure the hw interrupt event or the sw setting of the corresponding interrupt set bit (in register iss) sets the event indication flags (in register is) and can trigger the interrupt generation. the interrupt pulse is generated independently from the interrupt status flag in register is (it is not necessary to clear the related status bit to be able to generate another interrupt). the interrupt flag can be cleared by sw by writing to the corresponding bit in register isr. if enabled by the related interrupt enable bit in register ien, an interrupt pulse can be generated on one of the four service request outputs (sr0 to sr3) of the module. if more than one interrupt source is connected to the same interrupt node pointer (in register inp), the requests are logically or-combi ned to one common service request output (see figure 29-42 ). figure 29-42 general interrupt structure the available interrupt events in the ccu6 are shown in figure 29-43 . ccu6_mca05549 hw interrupt event interrupt status sw requests set clear interrupt >1 _ set interrupt to sr0 to sr1 to sr2 to sr3 interrupt enable interrupt node pointer clear www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-99 v1.1, 2011-03 ccu6, v1.0 figure 29-43 interrupt sources and events ccu6_mca05548 _b interrupt control logic node pointer register inp sr0 interrupt reset register isr interrupt enable register ien interrupt status register is t12 counter t12_ pm t12_ om t12 capture compare channels cc6x cc6x_r cc6x_f t13 counter t13_ pm t13 compare channel cc63 cm_63 trap handling trpf trps hall compare logic cm_che cm_whe multi-channel mode logic str cdir interrupt set register iss sr1 sr2 sr3 service request control register 0 ccu6x_src0 service request control register 1 ccu6x_src1 service request control register 2 ccu6x_src2 service request control register 3 ccu6x_src3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-100 v1.1, 2011-03 ccu6, v1.0 29.9.2 interrupt registers 29.9.2.1 interrupt status register register is contains the individual interrupt request bits. this register can only be read, write actions have no impact on the contents of this register. the sw can set or clear the bits individually by writing to the registers iss (to set the bits) or to register isr (to clear the bits). the interrupt generation is independent from the value of the bits in register is, e.g. the interrupt will be generated (if en abled) even if the corresponding bit is already set. the trigger for an interrupt generation is the detection of a set condition (by hw or sw) for the corresponding bit in register is. in compare mode (and hall mode), the timer-related interrupts are only generated while the timer is running (t1xr=1). in capture mode, the capture interrupts are also generated while the timer t12 is stopped. note: not all bits in register is can generat e an interrupt. other status bits have been added, that have a similar structure for their set and clear actions. it is recommended that sw checks the interrupt bits bit-wisely (i nstead of common or over the bits). is interrupt status register (a0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 str idle whe che trp s trp f t13 pm t13 cm t12 pm t12 om icc 62f icc 62r icc 61f icc 61r icc 60f icc 60r rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-101 v1.1, 2011-03 ccu6, v1.0 field bits type description icc60r, icc61r, icc62r 0, 2, 4 rh capture, compare-match rising edge flag this bit indicates that event cc6x_r has been detected. this event occurs in compare mode when a compare- match is detected while t12 is counting up (cm_6x and cdir = 0) and in capture mode when a rising edge is detected at the related input cc6xin. 0 b the event has not yet been detected. 1 b the event has been detected. icc60f, icc61f, icc62f 1, 3, 5 rh capture, compare-match falling edge flag this bit indicates that event cc6x_f has been detected. this event occurs in compare mode when a compare- match is detected while t12 is counting down (cm_6x and cdir = 1) and in capture mode when a falling edge is detected at the related input cc6xin. 0 b the event has not yet been detected. 1 b the event has been detected. t12om 6rh timer t12 one-match flag this bit indicates that a timer t12 one-match while counting down (t12_om and cdir = 1) has been detected. 0 b the event has not yet been detected. 1 b the event has been detected. t12pm 7rh timer t12 period-match flag this bit indicates that a timer t12 period-match while counting up (t12_pm and cdir = 0) has been detected. 0 b the event has not yet been detected. 1 b the event has been detected. t13cm 8rh timer t13 compare-match flag this bit indicates that a timer t13 compare-match (cm_63) has been detected. 0 b the event has not yet been detected. 1 b the event has been detected. t13pm 9rh timer t13 period-match flag this bit indicates that a timer t13 period-match (t13_pm) has been detected. 0 b the event has not yet been detected. 1 b the event has been detected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-102 v1.1, 2011-03 ccu6, v1.0 trpf 10 rh trap flag this bit indicates if a trap condition (input ctrap =0 or by sw) is / has been detected. if trpm2= 0, it becomes cleared automatically if ctrap =1 or trppen=0, whereas if trpm2 = 1, it has to be cleared by writing rtrpf = 1. 0 b the trap condition has not been detected. 1 b the trap condition is / has been detected. trps 11 rh trap state 1) this bit indicates the actual trap state. it is set if trpf = 1 and becomes cleared according to the mode selected in register trpctr. 0 b the trap state is not active. 1 b the trap state is active. che 12 rh correct hall event this bit indicates that a co rrect hall ev ent (cm_che) has been detected. 0 b the event has not yet been detected. 1 b the event has been detected. whe 13 rh wrong hall event this bit indicates that a wrong hall event (cm_whe) has been detected. 0 b the event has not yet been detected. 1 b the event has been detected. idle 14 rh idle state if enabled by enidle = 1, this bit is set together with bit whe and it has to be cleared by sw. 0 b no action. 1 b bit field mcmp is cleared, the selected outputs are set to passive state. str 15 rh multi-channel mode shadow transfer request this bit indicates that a shadow transfer from mcmps to mcmp (mcm_st) has taken place. 0 b the event has not yet been detected. 1 b the event has been detected. 0 [31:16] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-103 v1.1, 2011-03 ccu6, v1.0 29.9.2.2 interrupt st atus set register register iss contains individual interrupt request set bits to generate a ccu6 interrupt request by software. writing a 1 sets the bit(s) in register is at the corresponding bit position(s) and can generate an interr upt event (if available and enabled). all bit positions read as 0. 1) during the trap state, the selected outputs are set to the passive state. the logic level driven during the passive state is defined by the corresponding bit in register pslr. bits trps=1 and trpf=0 can occur if the trap condition is no longer active but the sele cted synchronization ha s not yet taken place. iss interrupt status set register (a4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 s str s idle s whe s che s whc s trp f s t13 pm s t13 cm s t12 pm s t12 om s cc 62f s cc 62r s cc 61f s cc 61r s cc 60f s cc 60r w wwwwwwwwwwwwwwww field bits type description scc60r, scc61r, scc62r 0, 2, 4 w set capture, compare-match rising edge flag 0 b no action 1 b bit cc6xr will be set. scc60f, scc61f, scc62f 1, 3, 5 w set capture, compare-match falling edge flag 0 b no action 1 b bit cc6xf will be set. st12om 6w set timer t12 one-match flag 0 b no action 1 b bit t12om will be set. st12pm 7w set timer t12 period-match flag 0 b no action 1 b bit t12pm will be set. st13cm 8w set timer t13 compare-match flag 0 b no action 1 b bit t13cm will be set. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-104 v1.1, 2011-03 ccu6, v1.0 st13pm 9w set timer t13 period-match flag 0 b no action 1 b bit t13pm will be set. strpf 10 w set trap flag 0 b no action 1 b bits trpf and trps will be set. swhc 11 w software hall compare 0 b no action 1 b the hall compare action is triggered. sche 12 w set correct hall event flag 0 b no action 1 b bit che will be set. swhe 13 w set wrong hall event flag 0 b no action 1 b bit whe will be set. sidle 14 w set idle flag 0 b no action 1 b bit idle will be set. sstr 15 w set str flag 0 b no action 1 b bit str will be set. 0 [31:16] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-105 v1.1, 2011-03 ccu6, v1.0 29.9.2.3 status reset register register isr contains bits to individually clear the interrupt event flags by software. writing a 1 clears the bit(s) in register is at the corresponding bit position(s). all bit positions read as 0. isr interrupt status reset register (a8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 r str r idle r whe r che 0 r trp f r t13 pm r t13 cm r t12 pm r t12 om r cc 62f r cc 62r r cc 61f r cc 61r r cc 60f r cc 60r w wwww r wwwwwwwwwww field bits type description rcc60r, rcc61r, rcc62r 0, 2, 4 w reset capture, compare-match rising edge flag 0 b no action 1 b bit cc6xr will be cleared. rcc60f, rcc61f, rcc62f 1, 3, 5 w reset capture, compare-match falling edge flag 0 b no action 1 b bit cc6xf will be cleared. rt12om 6w reset timer t12 one-match flag 0 b no action 1 b bit t12om will be cleared. rt12pm 7w reset timer t12 period-match flag 0 b no action 1 b bit t12pm is will be cleared. rt13cm 8w reset timer t13 compare-match flag 0 b no action 1 b bit t13cm will be cleared. rt13pm 9w reset timer t13 period-match flag 0 b no action 1 b bit t13pm will be cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-106 v1.1, 2011-03 ccu6, v1.0 rtrpf 10 w reset trap flag 0 b no action 1 b bit trpf will be cleared (not taken into account while input ctrap =0 and trppen=1. rche 12 w reset correct hall event flag 0 b no action 1 b bit che will be cleared. rwhe 13 w reset wrong hall event flag 1 b no action 0 b bit whe will be cleared. ridle 14 w reset idle flag 0 b no action 1 b bit idle will be cleared. rstr 15 w reset str flag 0 b no action 1 b bit str will be cleared. 0 11, [31:16] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-107 v1.1, 2011-03 ccu6, v1.0 29.9.2.4 interrupt enable register register ien contains the interrupt enable bits and a control bit to enable the automatic idle function in the case of a wrong hall pattern. ien interrupt enable register (b0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 en str en idle en whe en che 0 en trp f en t13 pm en t13 cm en t12 pm en t12 om en cc 62f en cc 62r en cc 61f en cc 61r en cc 60f en cc 60r rwrwrwrw r rwrwrwrwrwrwrwrwrwrwrw field bits type description encc60r, encc61r, encc62r 0, 2, 4 rw capture, compare-match rising edge interrupt enable for channel cc6x 0 b no interrupt will be generated if the set condition for bit cc6xr in register is occurs. 1 b an interrupt will be generated if the set condition for bit cc6xr in register is occurs. the service request output that will be activated is selected by bit field inpcc6x. encc60f, encc61f, encc62f 1, 3, 5 rw capture, compare-match falling edge interrupt enable for channel cc6x 0 b no interrupt will be generated if the set condition for bit cc6xf in register is occurs. 1 b an interrupt will be generated if the set condition for bit cc6xf in register is occurs. the service request output that will be activated is selected by bit field inpcc6x. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-108 v1.1, 2011-03 ccu6, v1.0 ent12om 6rw enable interrupt for t12 one-match 0 b no interrupt will be generated if the set condition for bit t12om in register is occurs. 1 b an interrupt will be generated if the set condition for bit t12om in register is occurs. the service request output that will be activated is selected by bit field inpt12. ent12pm 7rw enable interrupt fo r t12 period-match 0 b no interrupt will be generated if the set condition for bit t12pm in register is occurs. 1 b an interrupt will be generated if the set condition for bit t12pm in register is occurs. the service request output that will be activated is selected by bit field inpt12. ent13cm 8rw enable interrupt fo r t13 compare-match 0 b no interrupt will be generated if the set condition for bit t13cm in register is occurs. 1 b an interrupt will be generated if the set condition for bit t13cm in register is occurs. the service request output that will be activated is selected by bit field inpt13. ent13pm 9rw enable interrupt fo r t13 period-match 0 b no interrupt will be generated if the set condition for bit t13pm in register is occurs. 1 b an interrupt will be generated if the set condition for bit t13pm in register is occurs. the service request output that will be activated is selected by bit field inpt13. entrpf 10 rw enable interrupt for trap flag 0 b no interrupt will be generated if the set condition for bit trpf in register is occurs. 1 b an interrupt will be generated if the set condition for bit trpf in register is occurs. the service request output that will be activated is selected by bit field inperr. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-109 v1.1, 2011-03 ccu6, v1.0 29.9.2.5 interrupt n ode pointer register register inp contains the interrupt node pointers allowing a flexible interrupt handling. these bit fields define which service request output will be activated if the corresponding interrupt event occurs and the interrupt generation for this event is enabled. enche 12 rw enable interrupt for correct hall event 0 b no interrupt will be generated if the set condition for bit che in register is occurs. 1 b an interrupt will be generated if the set condition for bit che in register is occurs. the service request output that will be activated is selected by bit field inpche. enwhe 13 rw enable interrupt for wrong hall event 0 b no interrupt will be generated if the set condition for bit whe in register is occurs. 1 b an interrupt will be generated if the set condition for bit whe in register is occurs. the service request output that will be activated is selected by bit field inperr. enidle 14 rw enable idle this bit enables the automatic entering of the idle state (bit idle will be set) after a wrong hall event has been detected (bit whe is set). during the idle state, the bit field mcmp is automatically cleared. 0 b the bit idle is not automatically set when a wrong hall event is detected. 1 b the bit idle is automatically set when a wrong hall event is detected. enstr 15 rw enable multi-channel mode shadow transfer interrupt 0 b no interrupt will be generated if the set condition for bit str in register is occurs. 1 b an interrupt will be generated if the set condition for bit str in register is occurs. the service request output that will be activated is selected by bit field inpche. 0 11, [31:16] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-110 v1.1, 2011-03 ccu6, v1.0 inp interrupt node poin ter register (ac h ) reset value: 0000 3940 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 inp t13 inp t12 inp err inp che inp cc62 inp cc61 inp cc60 r rwrwrwrwrwrwrw field bits type description inpcc60, inpcc61, inpcc62 [1:0], [3:2], [5:4] rw interrupt node pointer fo r channel cc6x interrupts this bit field defines the service request output activated due to a set condition for bit cc6xr (if enabled by bit encc6xr) or for bit cc6xf (if enabled by bit encc6xf). 00 b service request output sr0 is selected. 01 b service request output sr1 is selected. 10 b service request output sr2 is selected. 11 b service request output sr3 is selected. inpche [7:6] rw interrupt node pointe r for the che interrupt this bit field defines the service request output activated due to a set condition for bit che (if enabled by bit enche) of for bit str (if enabled by bit enstr). coding see inpcc6x. inperr [9:8] rw interrupt node pointe r for error interrupts this bit field defines the service request output activated due to a set condition for bit trpf (if enabled by bit entrpf) or for bit whe (i f enabled by bit enwhe). coding see inpcc6x. inpt12 [11:10] rw interrupt node pointer for timer12 interrupts this bit field defines the service request output activated due to a set condition for bit t12om (if enabled by bit ent12om) or for bit t12pm (if enabled by bit ent12pm). coding see inpcc6x. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-111 v1.1, 2011-03 ccu6, v1.0 inpt13 [13:12] rw interrupt node pointer for timer13 interrupt this bit field defines the service request output activated due to a set condition for bit t13cm (if enabled by bit ent13cm) or for bit t13pm (if enabled by bit ent13pm). coding see inpcc6x. 0 [31:14] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-112 v1.1, 2011-03 ccu6, v1.0 29.9.3 service request control registers each cc6x kernel has four service request outputs which are connected to four service request nodes (srn). each srn contains a service request control register. ccu60_srcx (x = 0-3) ccu60 service request control register (fc h -x*4) reset value: 0000 0000 h ccu61_srcx (x = 0-3) ccu61 service request control register (fc h -x*4) reset value: 0000 0000 h ccu62_srcx (x = 0-3) ccu62 service request control register (fc h -x*4) reset value: 0000 0000 h ccu63_srcx (x = 0-3) ccu63 service request control register (fc h -x*4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-113 v1.1, 2011-03 ccu6, v1.0 29.10 general module operation this section provides information about the: ? configuration of the behavior of the different device operating modes (see mode control description in section 29.10.1 ) ? input selection (see section 29.10.2 ) ? general register description (see section 29.10.4 ) 29.10.1 mode control the mode control conc ept for system control tasks, such as power saving, or suspend request for debugging, allows to program the module behavior under different device operating conditions. the behavior of a ccu6 kernel can be programmed for each of the device operating modes, that are requested by the global state control part of the scu. therefore, a ccu6 module provides a kernel state configuration register kscfg defining the behavior in the following device operating modes: ? normal operation: this operating mode is the default operating mode when neither a suspend request nor a clock-off request are pending. the module clock is not switched off and the ccu6 registers can be read or written. the kernel behavior is defined by kscfg.nomcfg. ? suspend mode: this operating mode is requested when a suspend request (issued by a debugger through ocds) is pending in the device. the module clock is not switched off and the ccu6 registers can be read or writte n. the kernel behavior is defined by kscfg.sumcfg. ? clock-off mode: this operating mode is requested for powe r saving purposes. the module clock is switched off automatically when all kernels of the ccu6 module reached their specified state in a stop mode. in this case, ccu6 registers can not be accessed. the kernel behavior is defined by kscfg.comcf g. the clock-off mode is requested by a sleep request of the fpi bus. the kernel distinguishes four different blo cks (t12, t13, hall logic, and trap logic). these blocks can be individually enabled for the request of stop mode 0 and stop mode 1 by the sensitivity bits kscsr .sbx. if the request sensitivity is disabled, the block continues normal operation. if the request sensitivity is enabled, the block operates as specified for the selected stop mode. the complete ccu6 acknowledge is give n to the gsc when a ll four blocks have reached their defined end condition. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-114 v1.1, 2011-03 ccu6, v1.0 the behavior of the ccu6 kernel can be programmed for each of the device operating modes (normal operation and suspend mode). therefore, it supports four kernel modes, as shown in table 29-13 . table 29-12 ccu6 fu nctional blocks block function sensitivity bit 0 timer t12: a functional enable is delivered until the specified stop condition is reached. then, t12 stops counting and the cc6xin input stages are frozen. kscsr.sb0 1 timer t13: a functional enable is delivered until the specified stop condition is reached. then, t13 stops counting. kscsr.sb1 2 hall logic: the hall logic is stopped immediately and the ccposx input stages are frozen. kscsr.sb2 3 trap logic: the trap logic is stopped immediately and the ctrap input stage is frozen. kscsr.sb3 table 29-13 ccu6 kernel behavior kernel mode kernel behavior code run mode 0 kernel operation as specified, no impact on ccu6 operation (same behavior for run mode 0 and run mode 1) 00 b run mode 1 01 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-115 v1.1, 2011-03 ccu6, v1.0 generally, bit field kscfg.nomcfg should be configured for run mode 0 as default setting for standard operation. if a ccu6 kernel should not react to a suspend request (and to continue operation as in normal mode), bit field kscfg.sumcfg has to be configured with the same value as kscfg.n omcfg. if a ccu6 kernel should show a different behavior and stop operation when a specific stop condition is reached, the code for stop mode 0 or stop mode 1 has to be written to kscfg.sumcfg. a similar mechanism applies for the clock-off mode with the possibility to program the desired behavior by bi t field kscfg.comcfg. note: the stop mode selection strongly depends on the application needs and it is very unlikely that different stop modes are required in parallel in the same application. as a result, only one stop mode type (either 0 or 1) should be used in the bit fields in register kscfg. do not mix stop mode 0 and stop mode 1 and avoid transitions from stop mode 0 to stop mode 1 (or vice versa) for the ccu6 module. if the module clock is disabled by kscfg.moden = 0 or in clock-off mode when the stop condition is reached (in stop mode 0 or 1), the module can not be accessed by read or write operations (except register kscfg and kscsr that can always be accessed). as a consequence, it can not be configured. please note that bit kscfg.moden should only be set by sw while all configuration fields are configured for run mode 0. stop mode 0 the sensitivity bits are taken into account for: t12 block : timer t12 continues normal operation (if running) until they reach the end of the pwm period and then it stops (same stop condition as in single shot mode). when the timer stops, the cc6xin inputs are frozen. t13 block : timer t13 continues normal operation (if running) until they reach the end of the pwm period and then it stops (same stop condition as in single shot mode). hall logic block : the ccposx input values are frozen. trap logic block : the ctrap input value is frozen. 10 b stop mode 1 the output lines enabled for the trap condition are set to their passive values (similar to a trap state). the sensitivity bits are taken into account for: t12 block : timer t12 stops immediately and cc6xin inputs are frozen. t13 block : timer t13 stops. hall logic block : the ccposx input values are frozen. trap logic block : the ctrap input value is frozen. 11 b table 29-13 ccu6 kernel behavior (cont?d) kernel mode kernel behavior code www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-116 v1.1, 2011-03 ccu6, v1.0 29.10.2 input selection each ccu6 input signal can be selected from a vector of four or eight possible inputs by programming the port input select registers pisel0 and pisel2 . this permits to adapt the pin functionality of the device to the application requirements. the output pins for the module output signals are chosen in the ports. naming convention: the input vector cc60in[d:a] for input signal cc60in is composed of the signals cc60ina to cc60ind. note: all functional inputs of the ccu6 are synchronized to f cc6 before they affect the module internal logic. the resulting delay of 2/f cc6 and for asynchronous signals an additional uncertainty of 1/f cc6 have to be taken into account for precise timing calculation. an edge of an input signal c an only be correctly detected if the high phase and the low phase of the input signal are both longer than 1/f cc6 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-117 v1.1, 2011-03 ccu6, v1.0 29.10.3 input monitoring a selected event which occurs at each ccu6 input signal can be monitored through imon .x. every input signal can be included for the detection of a lost bit event ( imon .lbe) if enabled through its individual lost indicator enable bits ( li .yen). the lost bit event occurs if a selected event occurs again with the previous event captured (imon.x remains set) and its lost indicator is enabled for at least one of the monitored input signals. the lost bit event can be enabled ( li .lbeen) for an interrupt to be generated at one of the srx line, selected through li .inplbe. the lbe output signal of the kernel can be connected to a capture input to indicate when does the lost bit event happens. see section 29.12 . the lost bit event can be used as a kind of interrupt or event watchdog to monitor if an action related to an event has been process ed before a second event of the same type occurs. like this, if a certain event is treated by an interrupt that should be monitored, the related indication flag has to be cleared by sw. if the sw has not yet cleared the flag and the event occurs again, the event is considered as being lost and another interrupt can be generate d to inform the system ab out the loss. this can be also used to indicate that input events occur too often and the main task has not enough time to treat them. figure 29-44 lost event logic ccposx input event , x = 0-2 ccposxi imon ccposxi control logic cc6xini control logic ctrapi control logic t12i control logic ccposxen li ccu 6 lost event logic lost bit event or inplbe 2 li to sr0 to sr3 ?. ?. cc6xin input event , x = 0-2 ctrap input event t12hr input event lbeen li t13i control logic t13hr input event lbe output signal and set www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-118 v1.1, 2011-03 ccu6, v1.0 29.10.4 general registers 29.10.4.1 id register reset value of the first version of id register in tc1387 is 0000 5408 h . the ccu6 module identification register id contains read-only information about the module identification number and its revision. id module identificat ion register (08 h ) reset value: 0000 54xx h 31 16 15 8 7 0 0 modnum modrev rrr field bits type description modrev [7:0] r module revision number mod_rev defines the module revision number. the value of a module revision starts with 01 h (first revision), 02 h , 03 h , ... up to ff h . modnum [15:8] r module number value this bit field defines the module identification number for the ccu6: 54 h 0 [31:16] r reserved read as 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-119 v1.1, 2011-03 ccu6, v1.0 29.10.4.2 port input select registers registers pisel0 and pisel2 contain bit fields selecting the actual input signal for the module inputs. pisel0 port input select register 0 (10 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 ist12hr ispos2 ispos1 ispos0 istrp iscc62 iscc61 iscc60 rw rw rw rw rw rw rw rw field bits type description iscc60 [1:0] rw input select for cc60 this bit field defines the input signal used as cc60 capture input. 00 b the signal cc60ina is selected. 01 b the signal cc60inb is selected. 10 b the signal cc60inc is selected. 11 b the signal cc60ind is selected. iscc61 [3:2] rw input select for cc61 this bit field defines the input signal used as cc61 capture input. 00 b the signal cc61ina is selected. 01 b the signal cc61inb is selected. 10 b the signal cc61inc is selected. 11 b the signal cc61ind is selected. iscc62 [5:4] rw input select for cc62 this bit field defines the input signal used as cc62 capture input. 00 b the signal cc62ina is selected. 01 b the signal cc62inb is selected. 10 b the signal cc62inc is selected. 11 b the signal cc62ind is selected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-120 v1.1, 2011-03 ccu6, v1.0 istrp [7:6] rw input select for ctrap this bit field defines the input signal used as ctrap input. 00 b the signal ctrapa is selected. 01 b the signal ctrapb is selected. 10 b the signal ctrapc is selected. 11 b the signal ctrapd is selected. ispos0 [9:8] rw input select for ccpos0 this bit field defines the input signal used as ccpos0 input. 00 b the signal ccpos0a is selected. 01 b the signal ccpos0b is selected. 10 b the signal ccpos0c is selected. 11 b the signal ccpos0d is selected. ispos1 [11:10] rw input select for ccpos1 this bit field defines the input signal used as ccpos1 input. 00 b the signal ccpos1a is selected. 01 b the signal ccpos1b is selected. 10 b the signal ccpos1c is selected. 11 b the signal ccpos1d is selected. ispos2 [13:12] rw input select for ccpos2 this bit field defines the input signal used as ccpos2 input. 00 b the signal ccpos2a is selected. 01 b the signal ccpos2b is selected. 10 b the signal ccpos2c is selected. 11 b the signal ccpos2d is selected. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-121 v1.1, 2011-03 ccu6, v1.0 ist12hr [15:14] rw input select for t12hr this bit field defines the input signal used as t12hr input. 00 b either signal t12hra (if t12ext = 0) or t12hre (if t12ext = 1) is selected. 01 b either signal t12hrb (if t12ext = 0) or t12hrf (if t12ext = 1) is selected. 10 b either signal t12hrc (if t12ext = 0) or t12hrg (if t12ext = 1) is selected. 11 b either signal t12hrd (if t12ext = 0) or t12hrh (if t12ext = 1) is selected. 0 [31:16] r reserved returns 0 if read, should be written with 0. pisel2 port input select register 2 (14 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 t13 ext t12 ext iscnt13 iscnt12 ist13hr r rwrwrwrwrw field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-122 v1.1, 2011-03 ccu6, v1.0 field bits type description ist13hr [1:0] rw input select for t13hr this bit field defines the input signal used as t13hr input. 00 b either signal t13hra (if t13ext = 0) or t13hre (if t13ext = 1) is selected. 01 b either signal t13hrb (if t13ext = 0) or t13hrf (if t13ext = 1) is selected. 10 b either signal t13hrc (if t13ext = 0) or t13hrg (if t13ext = 1) is selected. 11 b either signal t13hrd (if t13ext = 0) or t13hrh (if t13ext = 1) is selected. iscnt12 [3:2] rw input select for t12 counting input this bit field defines the input event leading to a counting action of t12. 00 b the t12 prescaler generates the counting events. bit tctr4.t12cnt is not taken into account. 01 b bit tctr4.t12cnt written with 1 is a counting event. the t12 prescaler is not taken into account. 10 b the timer t12 is counting each rising edge detected in the selected t12hr signal. 11 b the timer t12 is counting each falling edge detected in the selected t12hr signal. iscnt13 [5:4] rw input select for t13 counting input this bit field defines the input event leading to a counting action of t13. 00 b the t13 prescaler generates the counting events. bit tctr4.t13cnt is not taken into account. 01 b bit tctr4.t13cnt written with 1 is a counting event. the t13 prescaler is not taken into account. 10 b the timer t13 is counting each rising edge detected in the selected t13hr signal. 11 b the timer t13 is counting each falling edge detected in the selected t13hr signal. t12ext 6rw extension for t12hr inputs this bit extends the 2-bit field ist12hr. 0 b one of the signals t12hr[d:a] is selected. 1 b one of the signals t12hr[h:e] is selected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-123 v1.1, 2011-03 ccu6, v1.0 t13ext 7rw extension for t13hr inputs this bit extends the 2-bit field ist13hr. 0 b one of the signals t13hr[d:a] is selected. 1 b one of the signals t13hr[h:e] is selected. 0 [31:8] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-124 v1.1, 2011-03 ccu6, v1.0 29.10.4.3 kernel state configuration register the kernel state configuration register kscfg allows the selection of the desired kernel modes for the different device operating modes. bit fields kscfg.nomcfg and kscfg.comcfg are reset by an application (class 3) reset. bit field kscfg.sumcfg is reset by a debug (class 1) reset. note: the coding of the bit fields no mcfg, sumcfg and co mcfg are described in table 29-13 . kscfg kernel state configuration register (18 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 bp com 0comcfg bp sum 0 sumcfg bp nom 0nomcfg sus req ack bp mod en mod en w r rw w r rw w r rw rh rh w rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-125 v1.1, 2011-03 ccu6, v1.0 field bits type description moden 0rw module enable this bit enables the module kernel clock and the module functionality. 0 b the module is switched off immediately (without respecting a stop condition). it does not react on mode control actions and the module clock is switched off. the module does not react on read accesses and ignores write accesses (except to kscfg). 1 b the module is switched on and can operate. after writing 1 to moden, it is recommended to read register kscfg to avoid pipeline effects in the control block before accessing other ccu6 registers. bpmoden 1w bit protection for moden this bit enables the write access to the bit moden. it always reads 0. 0 b moden is not changed. 1 b moden is updated with the written value. ack 2rh module acknowledge this bit monitors the state of the ccu6 module?s acknowledge on incoming requests. 0 b the acknowledge is not activated, because at least one of the module kernels is in a transition phase. 1 b the acknowledge is activated, because all module kernels have reached the requested state. susreq 3rh suspend request this bit monitors the state of the ccu6 module?s suspend request input, requested through ocds. the value is only valid when there is no sleep request. in the event that there is a sleep request, the value is ignored and comcfg is considered as the kernel mode. 0 b a suspend mode is not requested and bit field nomcfg defines the ccu6 kernel mode. 1 b a suspend mode is requested and bit field sumcfg defines the ccu6 kernel mode. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-126 v1.1, 2011-03 ccu6, v1.0 note: the bit protection bits bpxxx allow partly modification of the c onfiguration bits with a single write operation (without the need of a read-modify-write mechanism handled by the cpu). nomcfg [5:4] rw normal operation mode configuration this bit field defines the kernel mode applied in normal operation mode. 00 b run mode 0 is selected. 01 b run mode 1 is selected. 10 b stop mode 0 is selected. 11 b stop mode 1 is selected. bpnom 7w bit protection for nomcfg this bit enables the write access to the bit field nomcfg. it always reads 0. 0 b nomcfg is not changed. 1 b nomcfg is updated with the written value. sumcfg [9:8] rw suspend mode configuration this bit field defines the kernel mode applied in suspend mode. coding like nomcfg. bpsum 11 w bit protection for sumcfg this bit enables the write access to the bit field sumcfg. it always reads 0. 0 b sumcfg is not changed. 1 b sumcfg is updated with the written value. comcfg [13:12] rw clock off mode configuration this bit field defines the kernel mode applied in clock-off mode. coding like nomcfg. bpcom 15 w bit protection for comcfg this bit enables the write access to the bit field comcfg. it always reads 0. 0 b comcfg is not changed. 1 b comcfg is updated with the written value. 0 6, 10, 14, [31:16] r reserved returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-127 v1.1, 2011-03 ccu6, v1.0 29.10.4.4 kernel state sensitivity control register the kernel state control sensitivity register bits define which internal block is effected by stop modes 0 and 1. kscsr kernel state control sensitivity register (1c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 sb3 sb2 sb1 sb0 r rwrwrwrw field bits type description sb0, sb1, sb2, sb3 0, 1, 2, 3 rw sensitivity block x this bit defines if block x of the ccu6 kernel is sensitive to stop mode 0 or stop mode 1. the functional definition of the blocks is given in table 29-12 . 0 b block x is not sensitive to stop mode 0 or stop mode 1 and behaves like in run mode 0. it continues normal operation without respecting the defined stop condition. 1 b block x is sensitive to stop mode 0 or stop mode 1. it is respecting the defined stop condition. 0 [31:4] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-128 v1.1, 2011-03 ccu6, v1.0 29.10.4.5 module conf iguration register the module configuration register contains bits describing the functionality that is available in the ccu6 module. mcfg module configuration register (04 h ) reset value: 0000 0007 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0mcmt13t12 rrrrr field bits type description t12 0r t12 available this bit indicates if the t12 block is available. 0 b the t12 block is not available. a write access to t12pr is ignored. 1 b the t12 block is available. a write access to t12pr is executed. t13 1r t13 available this bit indicates if the t13 block is available. 0 b the t13 block is not available. a write access to t13pr is ignored. 1 b the t13 block is available. a write access to t13pr is executed. mcm 2r multi-channel mode available this bit indicates if the multi-channel mode functionality is available. 0 b the multi-channel mode functionality is not available. a write access to mcmouts is ignored. 1 b the multi-channel mode functionality is available. a write access to mcmouts is executed. 0 [31:3] r reserved; read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-129 v1.1, 2011-03 ccu6, v1.0 note: the mcfg register can be modified only if the signal which comes from the watchdog timer mechanism allows. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-130 v1.1, 2011-03 ccu6, v1.0 29.10.4.6 input m onitoring register the input monitoring register monitors the occurence of a selected event for the input signals. if a hardware event triggers the setting of bit imon.x and the same bit is written with 1 via software at the same time, then the corresponding bit is cleared (software overrules hardware). the lost bit event is indicated if an event is detected again at one or more input signals with its lost indicator enabled. note: the register is only applicable in capture modes if the edges are selected through t12msel.msel6x. imon input monitoring register (98 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 t13 hri t12 hri ctr api cc 62ini cc 61ini cc 60ini cc pos 2i cc pos 1i cc pos 0i lbe r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-131 v1.1, 2011-03 ccu6, v1.0 field bits type description lbe 0rwh lost bit event this bit determines if a lost bit event has occured. a lost bit event occurs when a selected event occurs again with the previous event captured (imon.x remains set ) and its lost indicator is enabled, for at least one of the monitored input signals. the bit can be cleared by writing a 1 to the same bit position, while writing a 0 has no effect. 0 b the lost bit event has not occured. 1 b the lost bit event has occured. ccposxi (x = 0 -2) x + 1 rwh event indication for input signal ccposx the bit determines if the selected event has occured via an edge detection. the bit can be cleared by writing a 1 to the same bit position, while writing a 0 has no effect. 0 b a selected event has not occured. 1 b edge detection indicates a selected event has occured. note: the dedicated edge is indicated for a selected event if hysteretic-like control or capture modes are initialised in t12msel.msel6x. if these modes are not selected, then all edges will be indicated as an event for the inputs. cc6xini (x = 0 -2) x + 4 rwh event indication for input signal cc6xin the bit determines if the selected event has occured via an edge detection. the bit can be cleared by writing a 1 to the same bit position, while writing a 0 has no effect. 0 b a selected event has not occured. 1 b edge detection indicates a selected event has occured. ctrapi 7rwh event indication fo r input signal ctrap the bit determines if the selected event has occured via an edge detection. the bit can be cleared by writing a 1 to the same bit position, while writing a 0 has no effect. 0 b an event has not occured. 1 b edge detection indicates an event has occured. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-132 v1.1, 2011-03 ccu6, v1.0 t12hri 8rwh event indication for input signal t12hr the bit determines if the selected event has occured via an edge detection. the bit can be cleared by writing a 1 to the same bit position, while writing a 0 has no effect. 0 b an event has not occured. 1 b edge detection indicates an event has occured. t13hri 9rwh event indication for input signal t13hr the bit determines if the selected event has occured via an edge detection. the bit can be cleared by writing a 1 to the same bit position, while writing a 0 has no effect. 0 b an event has not occured. 1 b edge detection indicates an event has occured. 0 [31:10] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-133 v1.1, 2011-03 ccu6, v1.0 29.10.4.7 lost indicator register the lost indicator register has the lost indicator enable bits for its detected event at the input signals. the lost bit event can then be enabled as an output signal through one of the service request lines. li lost indicator register (9c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 inplbe lbe en 0 t13 hre n t12 hre n ctr ape n cc 62in en cc 61in en cc 60in en cc pos 2en cc pos 1en cc pos 0en 0 rw rw r rwrwrwrwrwrwrwrwrw r field bits type description ccposxe n (x = 0 -2) x + 1 rw lost indicator enable for input signal ccposx this bit determines if the monitored event at the input signal is enabled for the detection of a lost bit event. 0 b input signal is disabled for a lost bit event detection. 1 b input signal is enabled for a lost bit event detection. cc6xinen (x = 0 -2) x + 4 rw lost indicator enable for input signal cc6xin this bit determines if the monitored event at the input signal is enabled for the detection of a lost bit event. 0 b input signal is disabled for a lost bit event detection. 1 b input signal is enabled for a lost bit event detection. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-134 v1.1, 2011-03 ccu6, v1.0 ctrapen 7rw lost indicator enable for inputsignal ctrap this bit determines if the monitored event at the input signal is enabled for the detection of a lost bit event. 0 b input signal is disabled for a lost bit event detection. 1 b input signal is enabled for a lost bit event detection. t12hren 8rw lost indicator enable for input signal t12hr this bit determines if the monitored event at the input signal is enabled for the detection of a lost bit event. 0 b input signal is disabled for a lost bit event detection. 1 b input signal is enabled for a lost bit event detection. t13hren 9rw lost indicator enable for input signal t13hr this bit determines if the monitored event at the input signal is enabled for the detection of a lost bit event. 0 b input signal is disabled for a lost bit event detection. 1 b input signal is enabled for a lost bit event detection. lbeen 13 rw interrupt enable fo r lost bit event this bit determines if a srx line is activated if lost bit event is detected. 0 b lost bit event is disabled for the activation of a srx line. 1 b lost bit event is enabled for the activation of a srx line. inplbe [15:14] rw interrupt node pointe r for lost bit event this bit field defines which service request output line is selected to output an lost event alert for an enabled lost bit event. 00 b service request output sr0 is selected. 01 b service request output sr1 is selected. 10 b service request output sr2 is selected. 11 b service request output sr3 is selected. 0 0, [12:10], [31:16] r reserved; returns 0 if read; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-135 v1.1, 2011-03 ccu6, v1.0 29.11 implementation this chapter describes the implementation of the ccu6 modules in the TC1798 device. ? address map (see section 29.11.1 ) ? module output select (see section 29.11.2 ) ? synchronous start (see section 29.11.3 ) ? digital connections (see section 29.12 ) 29.11.1 address map there are four ccu6 kernels in the TC1798, namely ccu60 to ccu63. the ccu6061 module consists of ccu60 and ccu61 kernels , while ccu6263 module consists of ccu62 and ccu63 kernels. table 29-14 registers address space module base address end address note ccu60 f000 3000 h f000 30ff h ccu6061 : consists of ccu60 and ccu61 kernels ccu61 f000 3100 h f000 31ff h ccu6061 : consists of ccu60 and ccu61 kernels ccu62 f000 3200 h f000 32ff h ccu6263 : consists of ccu62 and ccu63 kernels ccu63 f000 3300 h f000 33ff h ccu6263 : consists of ccu62 and ccu63 kernels table 29-15 registers overview - ccu6 module registers register short name register long name offset addr. access mode reset value page read write ccu6061 and ccu6263 module registers (onl y available in the address range of ccu60 and ccu62, respectively) ccu60_mo sel ccu60 module output select register 0c h u, sv u, sv 0000 0000 h 29-136 ccu62_mo sel ccu62 module output select register 0c h u, sv u, sv 0000 0000 h 29-138 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-136 v1.1, 2011-03 ccu6, v1.0 29.11.1.1 module registers module output select register mosel contains bit fields to select the output signal from the ccu6061 or ccu6263 for the trigger signals to the adcx modules. ccu60_mosel ccu60 module output select register(0c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 trig2sel trig1sel trig0sel rrwrwrw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-137 v1.1, 2011-03 ccu6, v1.0 field bits type description trig0sel [2:0] rw output trigger select for ccu6061 trig0 this bit field defines the output signal from the module pair used as the trigger signal to adcx inputs. 000 b the signal ccu60_cout63 is selected. 001 b the signal ccu61_cout63 is selected. 010 b the signal ccu60_cc60 is selected. 011 b the signal ccu61_cc60 is selected. 100 b the signal ccu60_sr1 is selected. 101 b the signal ccu61_sr1 is selected. 110 b the signal ccu60_sr3 is selected. 111 b the signal ccu61_sr3 is selected. trig1sel [5:3] rw output trigger select for ccu6061 trig1 this bit field defines the output signal from the module pair used as the trigger signal to adcx inputs. 000 b the signal ccu60_cout63 is selected. 001 b the signal ccu61_cout63 is selected. 010 b the signal ccu60_cc61 is selected. 011 b the signal ccu61_cc61 is selected. 100 b the signal ccu60_sr1 is selected. 101 b the signal ccu61_sr1 is selected. 110 b the signal ccu60_sr3 is selected. 111 b the signal ccu61_sr3 is selected. trig2sel [8:6] rw output trigger select for ccu6061 trig2 this bit field defines the output signal from the module pair used as the trigger signal to adcx inputs. 000 b the signal ccu60_cout63 is selected. 001 b the signal ccu61_cout63 is selected. 010 b the signal ccu60_cc62 is selected. 011 b the signal ccu61_cc62 is selected. 100 b the signal ccu60_sr1 is selected. 101 b the signal ccu61_sr1 is selected. 110 b the signal ccu60_sr3 is selected. 111 b the signal ccu61_sr3 is selected. 0 [31:9] r reserved returns 0 if read, should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-138 v1.1, 2011-03 ccu6, v1.0 ccu62_mosel ccu62 module output select register(0c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 trig2sel trig1sel trig0sel rrwrwrw field bits type description trig0sel [2:0] rw output trigger select for ccu6263 trig0 this bit field defines the output signal from the module pair used as the trigger signal to adcx inputs. 000 b the signal ccu62_cout63 is selected. 001 b the signal ccu63_cout63 is selected. 010 b the signal ccu62_cc60 is selected. 011 b the signal ccu63_cc60 is selected. 100 b the signal ccu62_sr1 is selected. 101 b the signal ccu63_sr1 is selected. 110 b the signal ccu62_sr3 is selected. 111 b the signal ccu63_sr3 is selected. trig1sel [5:3] rw output trigger select for ccu6263 trig1 this bit field defines the output signal from the module pair used as the trigger signal to adcx inputs. 000 b the signal ccu62_cout63 is selected. 001 b the signal ccu63_cout63 is selected. 010 b the signal ccu62_cc61 is selected. 011 b the signal ccu63_cc61 is selected. 100 b the signal ccu62_sr1 is selected. 101 b the signal ccu63_sr1 is selected. 110 b the signal ccu62_sr3 is selected. 111 b the signal ccu63_sr3 is selected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-139 v1.1, 2011-03 ccu6, v1.0 trig2sel [8:6] rw output trigger select for ccu6263 trig2 this bit field defines the output signal from the module pair used as the trigger signal to adcx inputs. 000 b the signal ccu62_cout63 is selected. 001 b the signal ccu63_cout63 is selected. 010 b the signal ccu62_cc62 is selected. 011 b the signal ccu63_cc62 is selected. 100 b the signal ccu62_sr1 is selected. 101 b the signal ccu63_sr1 is selected. 110 b the signal ccu62_sr3 is selected. 111 b the signal ccu63_sr3 is selected. 0 [31:9] r reserved returns 0 if read, should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-140 v1.1, 2011-03 ccu6, v1.0 29.11.2 module output select for ccu6061 module, there are 3 trigger signals which are selectable from the output signals from ccu60 and ccu61 kernels. similarly, ccu6263 module allows up to 3 output trigger signals from ccu62 and ccu63 kernels. figure 29-45 output select trigger trig1sel 3 000 ccu 60_cout63 ccu61_cout 63 ccu60_cc 60 ccu61_cc 60 ccu 60_sr1 ccu61_sr1 ccu60_sr3 ccu61_sr3 001 010 011 100 101 110 111 trig0sel 3 000 001 010 011 100 101 110 111 trig2sel 3 000 001 010 011 100 101 110 111 trig0 reqtr0_5 reqgt0_7 trig1 trig2 reqtr1_5 reqtr2_5 reqgt1_7 reqgt2_7 reqtr3_5 reqtr4_5 reqgt3_7 reqgt4_7 adc0 adc1 trig1sel 000 ccu 62_cout63 ccu 63_cout63 ccu62_cc61 ccu63_cc61 ccu 62_sr1 ccu 63_sr1 ccu 62_sr3 ccu 63_sr3 001 010 011 100 101 110 111 trig0sel 000 001 010 011 100 101 110 111 trig2sel 000 001 010 011 100 101 110 111 trig0 trig1 trig2 reqgt0_7 reqtr0_5 reqgt1_7 reqgt2_7 reqtr1_5 reqtr2_5 reqtr3_5 reqtr4_5 reqgt3_7 reqgt4_7 ccu60_cc 61 ccu61_cc 61 ccu 60_cc62 ccu 61_cc62 ccu6061 module ccu 62_cc60 ccu 63_cc60 ccu62_cc62 ccu63_cc62 ccu6263 module 3 3 3 ccu 6_output_sel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-141 v1.1, 2011-03 ccu6, v1.0 29.11.3 synchronous start synchronous start of the capture/compar e timers are supported by control bits syscon.cctrig0 and syscon.cctrig1 in the scu module. bit syscon.cctrig0 is connected to the t12hr and t13hr for ccu60 and ccu61 kernels while bit syscon.cctrig1 is connected to the t12hr and t13hr for ccu62 and ccu63 kernels. figure 29-46 synchronization concept in TC1798 edge selection by t12rsel t12r set edge selection by t13rsel t13r set ccu60 t13hr t12hr edge selection by t12rsel t12r set edge selection by t13rsel t13r set ccu61 t13 h r t12 h r edge selection by t12rsel t12r set edge selection by t13rsel t13r set ccu62 t13hr t12hr edge selection by t12rsel t12r set edge selection by t13rsel t13r set ccu63 t13 h r t12 h r ccu6_sync_start_impl scu syscon.cctrig0 syscon.cctrig1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-142 v1.1, 2011-03 ccu6, v1.0 29.12 digital connections the following tables show the digital connections of the ccu6x modules with other modules or pins in the TC1798 device. each input signal can be selected among 4 or 8 possible input lines, e.g. the input vector for input signal cc60in is composed of cc60in[d:a], whereas the input vectors for t12hr and t13hr are composed of t12hr[h:a] and t13hr[h:a]. the following sections refer to the interface signals. note: all functional inputs of the ccu6 are synchronized to f cc6 before they can affect the module internal logic. the resulting delay of 2/f cc6 and an uncertainty of 1/f cc6 have to be taken into account for precise timing calculation. an edge of an input signal can only be co rrectly detected if both, the high phase and the low phase of the input signal are each longer than 1/f cc6 . 29.12.1 connectio ns of ccu60 this table describes the module interconnections of ccu60. table 29-16 ccu60 digita l connections in TC1798 signal from/to module i/o to ccu60 can be used to/as cc60ina see port chapter i input signals for capture event on channel cc60 cc60inb see port chapter i cc60inc see port chapter i cc60ind 0 i cc61ina see port chapter i input signals for capture event on channel cc61 cc61inb see port chapter i cc61inc see port chapter i cc61ind 0 i www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-143 v1.1, 2011-03 ccu6, v1.0 cc62ina see port chapter i input signals for capture event on channel cc62 cc62inb see port chapter i cc62inc 0 i cc62ind 0 i ctrapa see port chapter i input signals for ctrap ctrapb see port chapter i ctrapc ccu60_ctrapa and ccu60_ctrapb i ctrapd scu_eru_pdout 0 i ccpos0a see port chapter i input signals for ccpos0 edge detection off ccpos0b ccu61_sr2 i ccpos0c 0 i ccpos0d 0 i ccpos1a see port chapter i input signals for ccpos1 edge detection off ccpos1b adc_sr2 i ccpos1c 0 i ccpos1d 0 i table 29-16 ccu60 digita l connections in TC1798 (cont?d) signal from/to module i/o to ccu60 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-144 v1.1, 2011-03 ccu6, v1.0 ccpos2a see port chapter i input signals for ccpos2 edge detection off ccpos2b 0 i ccpos2c 0 i ccpos2d 0 i t12hra cctrig0 i input signals for t12hr t12hrb see port chapter i t12hrc see port chapter i t12hrd gpta_trig00 i t12hre see port chapter i t12hrf gpt12_0_t6ofl i t12hrg ccu61_sr2 i t12hrh 0 i t13hra cctrig0 i input signals for t13hr t13hrb see port chapter i t13hrc see port chapter i t13hrd gpta_trig00 i t13hre see port chapter i t13hrf gpt12_0_t6ofl i t13hrg ccu61_sr2 i t13hrh ccu60_sr1 i table 29-16 ccu60 digita l connections in TC1798 (cont?d) signal from/to module i/o to ccu60 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-145 v1.1, 2011-03 ccu6, v1.0 cc60 see port chapter o compare outputs of channel cc60 cout60 see port chapter o cc61 see port chapter o compare outputs of channel cc61 cout61 see port chapter o cc62 see port chapter o compare outputs of channel cc62 cout62 see port chapter o cout63 see port chapter o compare output of channel cc63 lbe ccu63_cc60ind o lost bit event output t12_zm ? o t12 zero match t13_pm ? o t13 period match mcm_st ? o mcm shadow transfer sr0 dma chm1_reqi13, m = 0, 1 odma triggers sr1 ccu60_t13hrh, eru_ogu01 o t13 count trigger, output gating unit trigger adc0_reqtrx_5, adc1_reqgtx_7,x =0,1,2,3,4 adc0 and adc1 trigger capability, pls see ccu60_mosel for the respective trigger select to the request trigger/gating inputs of the adc0/1. sr2 ccu61_ccpos0b, ccu61_t12hrg, ccu61_t13hrg o ccu61 triggers sr3 adc0_reqtrx_5, adc1_reqgtx_7, x=0,1,2,3,4 o adc0 and adc1 trigger capability, pls see ccu60_mosel for the respective trigger select to the request trigger/gating inputs of the adc0/1. table 29-16 ccu60 digita l connections in TC1798 (cont?d) signal from/to module i/o to ccu60 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-146 v1.1, 2011-03 ccu6, v1.0 29.12.2 connectio ns of ccu61 this table describes the module interconnections of ccu61. table 29-17 ccu61 digita l connections in TC1798 signal from/to module i/o to cc61 can be used to/as cc60ina see port chapter i input signals for capture event on channel cc60 cc60inb see port chapter i cc60inc see port chapter i cc60ind ccu62_lbe i cc61ina see port chapter i input signals for capture event on channel cc61 cc61inb see port chapter i cc61inc see port chapter i cc61ind ccu63_lbe i cc62ina see port chapter i input signals for capture event on channel cc62 cc62inb see port chapter i cc62inc 0 i cc62ind gpt12_1_t6ofl i ctrapa see port chapter i input signals for ctrap ctrapb see port chapter i ctrapc ccu61_ctrapa and ccu61_ctrapb i ctrapd scu_eru_pdout 1 i www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-147 v1.1, 2011-03 ccu6, v1.0 ccpos0a see port chapter i input signals for ccpos0 edge detection off ccpos0b ccu60_sr2 i ccpos0c 0 i ccpos0d 0 i ccpos1a see port chapter i input signals for ccpos1 edge detection off ccpos1b adc_sr2 i ccpos1c 0 i ccpos1d 0 i ccpos2a see port chapter i input signals for ccpos2 edge detection off ccpos2b 0 i ccpos2c 0 i ccpos2d 0 i t12hra cctrig0 i input signals for t12hr t12hrb see port chapter i t12hrc see port chapter i t12hrd gpta_trig00 i t12hre see port chapter i t12hrf gpt12_0_t6ofl i t12hrg ccu60_sr2 i t12hrh 0 i table 29-17 ccu61 digita l connections in TC1798 (cont?d) signal from/to module i/o to cc61 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-148 v1.1, 2011-03 ccu6, v1.0 t13hra cctrig0 i input signals for t13hr t13hrb see port chapter i t13hrc see port chapter i t13hrd gpta_trig00 i t13hre see port chapter i t13hrf gpt12_0_t6ofl i t13hrg ccu60_sr2 i t13hrh ccu61_sr1 i cc60 see port chapter o compare outputs of channel cc60 cout60 see port chapter o cc61 see port chapter o compare outputs of channel cc61 cout61 see port chapter o cc62 see port chapter o compare outputs of channel cc62 cout62 see port chapter o cout63 see port chapter o compare output of channel cc63 lbe ccu63_cc61ind o lost bit event output t12_zm ? o t12 zero match t13_pm ? o t13 period match mcm_st ? o mcm shadow transfer sr0 dma chm5_reqi13, m = 0, 1 odma triggers table 29-17 ccu61 digita l connections in TC1798 (cont?d) signal from/to module i/o to cc61 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-149 v1.1, 2011-03 ccu6, v1.0 sr1 ccu61_t13hrh, eru_ogu11 o t13 count trigger, output gating unit trigger adc0_reqtrx_5, adc1_reqgtx_7,x =0,1,2,3,4 adc0 and adc1 trigger capability, pls see ccu60_mosel for the respective trigger select to the request trigger/gating inputs of the adc0/1. sr2 ccu60_ccpos0b, ccu60_t12hrg, ccu60_t13hrg o ccu60 triggers sr3 adc0_reqtrx_5, adc1_reqgtx_7, x=0,1,2,3,4 o adc0 and adc1 trigger capability, pls see ccu60_mosel for the respective trigger select to the request trigger/gating inputs of the adc0/1. table 29-17 ccu61 digita l connections in TC1798 (cont?d) signal from/to module i/o to cc61 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-150 v1.1, 2011-03 ccu6, v1.0 29.12.3 connectio ns of ccu62 this table describes the module interconnections of ccu62. table 29-18 ccu62 digita l connections in TC1798 signal from/to module i/o to ccu62 can be used to/as cc60ina see port chapter i input signals for capture event on channel cc60 cc60inb see port chapter i cc60inc see port chapter i cc60ind 0 i cc61ina see port chapter i input signals for capture event on channel cc61 cc61inb see port chapter i cc61inc see port chapter i cc61ind 0 i cc62ina see port chapter i input signals for capture event on channel cc62 cc62inb see port chapter i cc62inc 0 i cc62ind 0 i ctrapa see port chapter i input signals for ctrap ctrapb see port chapter i ctrapc ccu62_ctrapa and ccu62_ctrapb i ctrapd scu_eru_pdout 2 i www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-151 v1.1, 2011-03 ccu6, v1.0 ccpos0a see port chapter i input signals for ccpos0 edge detection off ccpos0b ccu63_sr2 i ccpos0c 0 i ccpos0d 0 i ccpos1a see port chapter i input signals for ccpos1 edge detection off ccpos1b adc_sr2 i ccpos1c 0 i ccpos1d 0 i ccpos2a see port chapter i input signals for ccpos2 edge detection off ccpos2b 0 i ccpos2c 0 i ccpos2d 0 i t12hra cctrig1 i input signals for t12hr t12hrb see port chapter i t12hrc see port chapter i t12hrd gpta_trig02 i t12hre see port chapter i t12hrf gpt12_1_t6ofl i t12hrg ccu63_sr2 i t12hrh 0 i table 29-18 ccu62 digita l connections in TC1798 (cont?d) signal from/to module i/o to ccu62 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-152 v1.1, 2011-03 ccu6, v1.0 t13hra cctrig1 i input signals for t13hr t13hrb see port chapter i t13hrc see port chapter i t13hrd gpta_trig02 i t13hre see port chapter i t13hrf gpt12_1_t6ofl i t13hrg ccu63_sr2 i t13hrh ccu62_sr1 i cc60 see port chapter o compare outputs of channel cc60 cout60 see port chapter o cc61 see port chapter o compare outputs of channel cc61 cout61 see port chapter o cc62 see port chapter o compare outputs of channel cc62 cout62 see port chapter o cout63 see port chapter o compare output of channel cc63 lbe ccu61_cc60ind o lost bit event output t12_zm ? o t12 zero match t13_pm ? o t13 period match mcm_st ? o mcm shadow transfer sr0 dma chm6_reqi13, m = 0, 1 ccu62_t13hrh odma triggers table 29-18 ccu62 digita l connections in TC1798 (cont?d) signal from/to module i/o to ccu62 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-153 v1.1, 2011-03 ccu6, v1.0 sr1 ccu62_t13hrh, eru_ogu21 o t13 count trigger, output gating unit trigger adc0_reqgtx_7, adc1_reqtrx_5,x =0,1,2,3,4 adc0 and adc1 trigger capability, pls see ccu62_mosel for the respective trigger select to the request trigger/gating inputs of the adc0/1. sr2 ccu63_ccpos0b, ccu63_t12hrg, ccu63_t13hrg o ccu63 triggers sr3 adc0_reqgtx_7, adc1_reqtrx_5, x=0,1,2,3,4 o adc0 and adc1 trigger capability, pls see ccu62_mosel for the respective trigger select to the request trigger/gating inputs of the adc0/1. table 29-18 ccu62 digita l connections in TC1798 (cont?d) signal from/to module i/o to ccu62 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-154 v1.1, 2011-03 ccu6, v1.0 29.12.4 connectio ns of ccu63 this table describes the module interconnections of ccu63. table 29-19 ccu63 digita l connections in TC1798 signal from/to module i/o to cc63 can be used to/as cc60ina see port chapter i input signals for capture event on channel cc60 cc60inb see port chapter i cc60inc see port chapter i cc60ind ccu60_lbe i cc61ina see port chapter i input signals for capture event on channel cc61 cc61inb see port chapter i cc61inc see port chapter i cc61ind ccu61_lbe i cc62ina see port chapter i input signals for capture event on channel cc62 cc62inb see port chapter i cc62inc 0 i cc62ind gpt12_0_t6ofl i ctrapa see port chapter i input signals for ctrap ctrapb see port chapter i ctrapc ccu63_ctrapa and ccu63_ctrapb i ctrapd scu_eru_pdout 3 i www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-155 v1.1, 2011-03 ccu6, v1.0 ccpos0a see port chapter i input signals for ccpos0 edge detection off ccpos0b ccu62_sr2 i ccpos0c 0 i ccpos0d 0 i ccpos1a see port chapter i input signals for ccpos1 edge detection off ccpos1b adc_sr2 i ccpos1c 0 i ccpos1d 0 i ccpos2a see port chapter i input signals for ccpos2 edge detection off ccpos2b 0 i ccpos2c 0 i ccpos2d 0 i t12hra cctrig1 i input signals for t12hr t12hrb see port chapter i t12hrc see port chapter i t12hrd gpta_trig02 i t12hre see port chapter4 i t12hrf gpt12_1_t6ofl i t12hrg ccu62_sr2 i t12hrh 0 i table 29-19 ccu63 digita l connections in TC1798 (cont?d) signal from/to module i/o to cc63 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-156 v1.1, 2011-03 ccu6, v1.0 t13hra cctrig1 i input signals for t13hr t13hrb see port chapter i t13hrc see port chapter i t13hrd gpta_trig02 i t13hre see port chapter i t13hrf gpt12_1_t6ofl i t13hrg ccu62_sr2 i t13hrh ccu63_sr1 i cc60 see port chapter o compare outputs of channel cc60 cout60 see port chapter o cc61 see port chapter o compare outputs of channel cc61 cout61 see port chapter o cc62 see port chapter o compare outputs of channel cc62 cout62 see port chapter o cout63 see port chapter o compare output of channel cc63 lbe ccu61_cc61ind o lost bit event output t12_zm ? o t12 zero match t13_pm ? o t13 period match mcm_st ? o mcm shadow transfer sr0 dma chm7_reqi13, m = 0, 1 ccu63_t13hrh odma triggers table 29-19 ccu63 digita l connections in TC1798 (cont?d) signal from/to module i/o to cc63 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-157 v1.1, 2011-03 ccu6, v1.0 sr1 ccu63_t13hrh, eru_ogu31 o t13 count trigger, output gating unit trigger adc0_reqgtx_7, adc1_reqtrx_5,x =0,1,2,3,4 adc0 and adc1 trigger capability, pls see ccu62_mosel for the respective trigger select to the request trigger/gating inputs of the adc0/1. sr2 ccu62_ccpos0b, ccu62_t12hrg, ccu62_t13hrg o ccu62 triggers sr3 adc0_reqgtx_7, adc1_reqtrx_5, x=0,1,2,3,4 o adc0 and adc1 trigger capability, pls see ccu62_mosel for the respective trigger select to the request trigger/gating inputs of the adc0/1. table 29-19 ccu63 digita l connections in TC1798 (cont?d) signal from/to module i/o to cc63 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 capture/compare unit 6 (ccu6) users manual 29-158 v1.1, 2011-03 ccu6, v1.0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-1 v1.1, 2011-03 gpt12, v1.5 30 the general pur pose timer 12 (gpt12) the general purpose timer 12 consist out of the blocks gpt1 and gpt2, that have a very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. they incorporate five 16-bit timers that are grouped into the two timer blocks gpt1 and gpt2. each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. each block has alternate input/output functions and specific interrupts associated with it. note: input signals can be selected from several sources by register pisel. block gpt1 contains three timers/counters: the core timer t3 and the two auxiliary timers t2 and t4. the maximum resolution is f gpt /4. the auxiliary timers of gpt1 may optionally be configured as reload or capture registers for the core timer. these registers are listed in section 30.1.6 . ? f gpt /4 maximum resolution ? 3 independent timers/counters ? timers/counters can be concatenated ? 4 operating modes: ? timer mode ? gated timer mode ? counter mode ? incremental interface mode ? reload and capture functionality ? separate interrupts block gpt2 contains two timers/counters: the core timer t6 and the auxiliary timer t5. the maximum resolution is f gpt /2. an additional capture/reload register (caprel) supports capture and reload operation with extended functionality. these registers are listed in section 30.2.7 . the following list summarizes the features which are supported: ? f gpt /2 maximum resolution ? 2 independent timers/counters ? timers/counters can be concatenated ? 3 operating modes: ? timer mode ? gated timer mode ? counter mode ? extended capture/reload functions via 16-bit capture/reload register caprel ? separate interrupts www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-2 v1.1, 2011-03 gpt12, v1.5 30.1 timer block gpt1 all three timers of block gpt1 (t2, t3, t4) can run in one of 4 basic modes: timer mode, gated timer mode, counter mode, or incremental interface mode. all timers can count up or down. each timer of gpt1 is controlled by a separate control register txcon. each timer has an input pin txin (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. the count direction (up/down) may be progra mmed via software or may be dynamically altered by a signal at the external up/down control input txeud (alternate pin function). an overflow/underflow of core timer t3 is indicated by the output toggle latch t3otl, whose state may be output on the associated pin t3out (alternate pin function). the auxiliary timers t2 and t4 may additionally be concatenated with the core timer t3 (through t3otl) or may be used as capture or reload registers for the core timer t3. the current contents of each timer can be read or modified by the cpu by accessing the corresponding timer count registers t2, t3, or t4. when any of the timer registers is written to by the cpu in the state immediat ely preceding a timer increment, decrement, reload, or capture operation, the cpu write operation has priority in order to guarantee correct results. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-3 v1.1, 2011-03 gpt12, v1.5 figure 30-1 gpt1 block diagram note: the gpt1 block uses a finite state machine to control the actions. since multiple interactions are possible between the time rs (t2, t3, t4), these elements are processed sequentially. however, all ac tions are normally completed within one basic clock cycle. the gpt1 state machine has 8 states (4 states when bps1 = 01 b ) and processes the timers in the order t3 - t2 (all actions except capture) - t4 - t2 (capture). t3 mode control 2 n : 1 f gpt t2 mode control aux. timer t2 reload capture t4 mode control aux. timer t4 reload capture core timer t 3 t3otl u/d t2eud t2in t3in t3eud t4in t4eud toggle latch u/d u/d interrupt request (src0) interrupt request (src1) interrupt request (src2) mc_gpt0101_bldiax1_mod.vsd t3out basic clock t3con.bps1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-4 v1.1, 2011-03 gpt12, v1.5 30.1.1 gpt1 core timer t3 control the current contents of the core timer t3 are reflected by its count register t3. this register can also be written to by the cpu, for example, to set the initial start value. t3con timer 3 control register (14 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t3 r dir t3 ch dir t3e dge bps1 t3 otl t3 oe t3 ude t3 ud t3 r t3m t3i rh rwh rwh rw rwh rw rw rw rw rw rw field bits type description t3i [2:0] rw timer t3 input parameter selection depends on the operating mode, see respective sections for encoding: table 30-8 for timer mode and gated timer mode table 30-2 for counter mode table 30-3 for incremental interface mode t3m [5:3] rw timer 3 mode control 000 b timer mode 001 b counter mode 010 b gated timer mode with gate active low 011 b gated timer mode with gate active high 100 b reserved. do not use this combination 101 b reserved. do not use this combination 110 b incremental interface mode (rotation detection mode) 111 b incremental interface mode (edge detection mode) t3r 6rw timer 3 run bit 0 b timer 3 stops 1 b timer runs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-5 v1.1, 2011-03 gpt12, v1.5 t3ud 7rw timer t3 up/down control 1) 0 b timer t3 counts up 1 b timer t3 counts down t3ude 8rw timer t3 external up/down enable 1) 0 b input t3eud is disconnected 1 b direction influenced by input t3eud t3oe 9rw overflow/underflow output enable 0 b alternate output function disabled 1 b state of t3 toggle latch is output on pin t3out t3otl 10 rwh timer t3 overflow toggle latch toggles on each overflow/underflow of t3. can be set or cleared by software (see separate description) bps1 [12:11] rw gpt1 block prescaler control selects the basic clock for block gpt1 (see also section 30.1.5 ) 00 b f gpt /8 01 b f gpt /4 10 b f gpt /32 11 b f gpt /16 t3edge 13 rwh timer t3 edge detection flag the bit is set each time a count edge is detected. t3edge must be cleared by software. 0 b no count edge was detected 1 b a count edge was detected t3chdir 14 rwh timer t3 count direction change flag this bit is set each time the count direction of timer t3 changes. t3chdir must be cleared by software. 0 b no change of count direction was detected 1 b a change of count direction was detected t3rdir 15 rh timer t3 rotation direction flag 0 b timer t3 counts up 1 b timer t3 counts down 0 [31:16] r reserved read as 0; should be written with 0. 1) see table 30-1 for encoding of bits t3ud and t3ude. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-6 v1.1, 2011-03 gpt12, v1.5 timer t3 run control the core timer t3 can be started or stopped by software through bit t3r (timer t3 run bit). this bit is relevant in all operating modes of t3. setting bit t3r will start the timer, clearing bit t3r stops the timer. in gated timer mode, t he timer will only run if t3r = 1 and the gate is active (high or low, as programmed). note: when bit t2rc or t4rc in timer control register t2con or t4con is set, bit t3r will also control (start and stop) t he auxiliary timer(s) t2 and/or t4. count direct ion control the count direction of the gpt1 timers (core timer and auxiliary timers) can be controlled either by software or by the external in put pin txeud (timer tx external up/down control input). these options are selected by bits txud and txude in the respective control register txcon. when the up/down control is provided by software (bit txude = 0), the count direction can be altered by setting or clearing bit txud. when bit txude = 1, pin txeud is selected to be the controlling source of the count direction. however, bit txud can still be used to reverse the actual count direction, as shown in table 30-1 . the count direction can be changed regardless of whether or not the timer is running. note: when pin txeud is used as external count direction control input, it must be configured as input (its corresponding di rection control bit must be cleared). table 30-1 gpt1 timer count direction control pin txeud bit txude bit txud count direction bit txrdir x 0 0 count up 0 x 0 1 count down 1 0 1 0 count up 0 1 1 0 count down 1 0 1 1 count down 1 1 1 1 count up 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-7 v1.1, 2011-03 gpt12, v1.5 timer 3 output toggle latch the overflow/underflow signal of timer t3 is connected to a block named ?toggle latch?, shown in the timer mode diagrams. figure 30-2 illustrates the details of this block. an overflow or underflow of t3 will clock two latches: the first latch represents bit t3otl in control register t3con. the second latch is an internal latch toggled by t3otl?s output. both latch outputs are connected to the input control blocks of the auxiliary timers t2 and t4. the output le vel of the shadow latch will match the output level of t3otl, but is delayed by one clock cycle. when the t3otl value changes, this will result in a temporarily different output level from t3otl and the shadow latch, which can trigger the selected count event in t2 and/or t4. when software writes to t3otl, both latche s are set or cleared simultaneously. in this case, both signals to the aux iliary timers carry the same level and no edge will be detected. bit t3oe (overflow/underflow output enable) in register t3con enables the state of t3otl to be monitored via an exte rnal pin t3out. when t3otl is linked to an external port pin (must be configured as output), t3out can be used to control external hw. if t3oe = 1, pin t3out outputs the state of t3otl. if t3oe = 0, pin t3out outputs a high level (as long as the t3out alternate function is selected for the port pin). the trigger signals can serve as an input for the counter function or as a trigger source for the reload function of the auxiliary timers t2 and t4. as can be seen from figure 30-2 , when latch t3otl is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. therefore, no trigger condit ion is detected by t2/t4 in this case. figure 30-2 block diagram of the toggle latch logic of core timer t3 mc_gpt0106_otl.vsd toggle latch logic txout set/clear (sw) core timer overflow/ underflow shadow latch 1 0 mux 1 txoe txotl to port logic to aux. timer input logic www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-8 v1.1, 2011-03 gpt12, v1.5 30.1.2 gpt1 core time r t3 operating modes timer t3 can operate in one of several modes. timer 3 in timer mode timer mode for the core timer t3 is selected by setting bitfield t3m in register t3con to 000 b . in timer mode, t3 is clocked with the module?s input clock f gpt divided by two programmable prescalers controlled by bitfields bps1 and t3i in register t3con. please see section 30.1.5 for details on the input clock options. figure 30-3 block diagram of core timer t3 in timer mode prescaler core timer t3 toggle latch mcb05391 _mod bps1 t3i mux up/down 0 1 t3eu d f gpt =1 t3ud f t3 t3 r count t3out interrupt (src1) to t2/t4 t3ude www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-9 v1.1, 2011-03 gpt12, v1.5 gated timer mode gated timer mode for the core timer t3 is selected by setting bitfield t3m in register t3con to 010 b or 011 b . bit t3m.0 (t3con.3) selects the active level of the gate input. the same options for the input frequency are available in gated timer mode as in timer mode (see section 30.1.5 ). however, the input clock to the timer in this mode is gated by the external input pin t3in (timer t3 external input). to enable this operation, the associated pin t3in must be configured as input, that is, the corresponding direction control bit must contain 0. figure 30-4 block diagram of core timer t3 in gated timer mode if t3m = 010 b , the timer is enabled when t3in shows a low level. a high level at this line stops the timer. if t3m = 011 b , line t3in must have a high level in order to enable the timer. additionally, the timer can be turned on or off by software using bit t3r. the timer will only run if t3r is 1 and t he gate is active. it will stop if either t3r is 0 or the gate is inactive. note: a transition of the gate signal at pin t3 in does not cause an interrupt request via src1. prescaler gate ctrl. core timer t3 toggle latch mcb05392 _mod bps 1 t3i mux up/down 0 1 t3eud f gpt =1 t3ud f t3 t3r count t3out interrupt (src1) to t2 /t 4 t3u d e t3in www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-10 v1.1, 2011-03 gpt12, v1.5 counter mode counter mode for the core timer t3 is selected by setting bitfield t3m in register t3con to 001 b . in counter mode, timer t3 is clocked by a transition at the external input pin t3in. the event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative tran sition at this line. bitfield t3i in control register t3con selects the triggering transition (see table 30-2 ). figure 30-5 block diagram of co re timer t3 in counter mode for counter mode operation, pin t3in must be configured as input (the respective direction control bit dpx.y must be 0). the maximum input frequency allowed in counter mode depends on the selected prescaler value. to ensure that a transition of the count input signal applied to t3in is recognized correctly, its level must be held high or low for a minimum number of module clock cycles be fore it changes. this information can be found in section 30.1.5 . table 30-2 gpt1 core timer t3 (counter mode) input edge selection t3i triggering edge for counter increment/decrement 000 b none. counter t3 is disabled 001 b positive transition (rising edge) on t3in 010 b negative transition (falling edge) on t3in 011 b any transition (rising or falling edge) on t3in 1xx b reserved. do not use this combination mcb05393_mod core timer t3 toggle latch mux up/down 0 1 t3eud t3in =1 t3u d t3r count t3out interrput (src1 ) to t2/t4 t3ude t3i edge select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-11 v1.1, 2011-03 gpt12, v1.5 incremental interface mode incremental interface mode for the core timer t3 is selected by setting bitfield t3m in register t3con to 110 b or 111 b . in incremental interface mode, the two inputs associated with core timer t3 (t3in, t3eud) are used to interface to an incremental encoder. t3 is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold reso lution of the encoder input. figure 30-6 block diagram of core time r t3 in incremental interface mode bitfield t3i in control register t3con selects the triggering transitions (see table 30-3 ). the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal. so t3 is modified automatically according to the speed and the direction of the incremental en coder and, therefore, its contents always represent the encoder?s current position. the interrupt request generation can be selected: in rotation detection mode (t3m = 110 b ), an interrupt request is generated each time the count direction of t3 changes. in edge detection mode (t3m = 111 b ), an interrupt request is generated each time a count edge for t3 is detected. count direction, changes in the count direction, and count requests are monitored by status bits t3rdir, t3chdir, and t3edge in register t3con. mcb05394_mod count t3eu d t3 edge t3 rdir mux 0 1 =1 t3ud t3ude change detect t3ch dir t3m t3m >1 _ phase detect t3r t3i n t3i interrupt (src1) core timer t3 toggle latch t3ou t to t2/ t 4 edge select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-12 v1.1, 2011-03 gpt12, v1.5 the incremental encoder can be connected directly to the TC1798 without external interface logic. in a standard system, however, comparators will be employed to convert the encoder?s differential outputs (such as a, a ) to digital signals (such as a). this greatly increases noise immunity. note: the third encoder output t0, that indicates the mechanical zero position, may be connected to an external interrupt input and trigger a reset of timer t3. if input t4in is available, t0 can be connected there and clear t3 automatically without requiring an interrupt. figure 30-7 connection of the encoder to the TC1798 for incremental interface mode operation, the following conditions must be met: ? bitfield t3m must be 110 b or 111 b . ? both pins t3in and t3eud must be configured as input. ? pin t4in must be configured as input, if used for t0. ? bit t3ude must be 1 to enable automatic external direction control. the maximum count frequency allowed in incremental interface mode depends on the selected prescaler value. to ensure that a transition of any input signal is recognized table 30-3 core timer t3 (incremental interface mode) input edge selection t3i triggering edge for counter increment/decrement 000 b none. counter t3 stops. 001 b any transition (rising or falling edge) on t3in. 010 b any transition (rising or falling edge) on t3eud. 011 b any transition (rising or falling edge) on any t3 input (t3in or t3eud). 1xx b reserved. do not use this combination. encoder controller a b t0 t3input t3input interrupt or t4in a b b t0 t0 a signal conditioning mc_gpt1_encoder www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-13 v1.1, 2011-03 gpt12, v1.5 correctly, its level must be held high or low for a minimum number of module clock cycles before it changes. this information can be found in section 30.1.5 . as in incremental interface mode two input signals with a 90 phase shift are evaluated, their maximum input frequency can be half the maximum count frequency. in incremental interface mode, the count direction is automatically derived from the sequence in which the input signals change, which corresponds to the rotation direction of the connected sensor. table 30-4 summarizes the poss ible combinations. figure 30-8 and figure 30-9 give examples of t3?s operation, visualizing count signal generation and direction control. they also show how input jitter is compensated, which might occur if the sensor rests near to one of its switching points. figure 30-8 evaluation of incremental encoder signals, 2 count inputs table 30-4 gpt1 core timer t3 (incremental interface mode) count direction level on respective other input t3in input t3eud input rising falling rising falling high down up up down low up down down up mct0437 3 forward jitter backward jitter forward t3in t3eud contents of t3 up down up note: this example shows the timer behaviour assuming that t3 counts upon any transition on input, i.e. t3i = '011 b '. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-14 v1.1, 2011-03 gpt12, v1.5 figure 30-9 evaluation of incremental encoder signals, 1 count input note: timer t3 operating in incremental interface mode automatically provides information on the sensor?s current position. dynamic information (speed, acceleration, deceleration) may be obtai ned by measuring the incoming signal periods (see ?combined capture modes? on page 30-59 ). mct04374 forward jitter backward jitter forward t3in up down up t3eud contents of t3 note: this example shows the timer behaviour assuming that t3 counts upon any transition on input t3in, i.e. t3i = '001 b '. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-15 v1.1, 2011-03 gpt12, v1.5 30.1.3 gpt1 auxiliary timers t2/t4 control auxiliary timers t2 and t4 have exactly the same functionality. they can be configured for timer mode, gated timer mode, counter mode, or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer t3. in addition to these 4 counting modes, the auxiliary timers can be concatena ted with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. the start/stop fu nction of the auxiliary timers can be remotely controlled by the t3 run control bit. several timers may thus be controlled synchronously. the current contents of an auxiliary timer are reflected by its count register t2 or t4, respectively. these registers can also be written to by the cpu, for example, to set the initial start value. the individual configurations for timers t2 and t4 are determined by their control registers t2con and t4con, that are organi zed identically. note that functions which are present in all 3 timers of block gpt1 are controlled in the same bit positions and in the same manner in each of the specific control registers. note: the auxiliary timers have no output toggle latch and no alternate output function. t2con timer 2 control register (10 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t2 r dir t2 ch dir t2e dge t2 ir dis 0 t2 rc t2 ude t2 ud t2 r t2m t2i rh rwh rwh rw r rw rw rw rw rw rw field bits type description t2i [2:0] rw timer tx input parameter selection depends on the operating mode, see respective sections for encoding: table 30-8 for timer mode and gated timer mode table 30-2 for counter mode table 30-3 for incremental interface mode www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-16 v1.1, 2011-03 gpt12, v1.5 t2m [5:3] rw timer 2 mode control (basic operating mode) 000 b timer mode 001 b counter mode 010 b gated timer mode with gate active low 011 b gated timer mode with gate active high 100 b reload mode 101 b capture mode 110 b incremental interface mode (rotation detection mode) 111 b incremental interface mode (edge detection mode) t2r 6rw timer 2 run bit 0 b timer / counter 2 stops 1 b timer / counter 2 runs t2ud 7rw timer 2 up/down control (when t2ude = ?0?) 0 b counting ?up? 1 b counting ?down? t2ude 8rw timer 2 external up/down enable 0 b counting direction is internally controlled by software 1 b counting direction is externally controlled by line txeud t2rc 9rw timer 2 remote control 0 b timer / counter 2 is controlled by its own run bit t2r 1 b timer / counter 2 is controlled by the run bit of core timer 3 t2irdis 12 rw timer 2 interrupt disable 0 b interrupt generation for t2chdir and t2edge interrupts in incremental interface mode is enabled 1 b interrupt generation for t2chdir and t2edge interrupts in incremental interface mode is disabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-17 v1.1, 2011-03 gpt12, v1.5 t2edge 13 rwh timer 2 edge detection the bit is set on each successful edge detection. the bit has to be cleared by software. 0 b no count edge was detected 1 b a count edge was detected t2chdir 14 rwh timer 2 count direction change the bit is set on a change of the count direction of timer 2. the bit has to be cleared by software. 0 b no change in count direction was detected 1 b a change in count direction was detected t2rdir 15 rh timer 2 rotation direction 0 b timer 2 counts up 1 b timer 2 counts down 0 [11:10], [31:16] r reserved read as 0; should be written with 0. t4con timer 4 control register (18 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t4 r dir t4 ch dir t4e dge t4 ir dis clr t3 en clr t2 en t4 rc t4 ude t4 ud t4 r t4m t4i rh rwh rwh rw rw rw rw rw rw rw rw rw field bits type description t4i [2:0] rw timer tx input parameter selection depends on the operating mode, see respective sections for encoding: table 30-8 for timer mode and gated timer mode table 30-2 for counter mode table 30-3 for incremental interface mode field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-18 v1.1, 2011-03 gpt12, v1.5 t4m [5:3] rw timer 4 mode control (basic operating mode) 000 b timer mode 001 b counter mode 010 b gated timer mode with gate active low 011 b gated timer mode with gate active high 100 b reload mode 101 b capture mode 110 b incremental interface mode (rotation detection mode) 111 b incremental interface mode (edge detection mode) t4r 6rw timer 4 run bit 0 b timer / counter 4 stops 1 b timer / counter 4 runs t4ud 7rw timer 4 up/down control (when t4ude = ?0?) 0 b counting ?up? 1 b counting ?down? t4ude 8rw timer 4 external up/down enable 0 b counting direction is internally controlled by software 1 b counting direction is externally controlled by line t4eud t4rc 9rw timer 4 remote control 0 b timer / counter 4 is controlled by its own run bit t4r 1 b timer / counter 4 is controlled by the run bit of core timer 3 clrt2en 10 rw clear timer 2 enable enables the automatic clearing of t2 upon a falling edge of the selected t4eud input. 0 b no effect of t4eud on t2 1 b a falling edge on t4eud clears timer t2 clrt3en 11 rw clear timer 3 enable enables the automatic clearing of t3 upon a falling edge of the selected t4in input. 0 b no effect of t4in on t3 1 b a falling edge on t4in clears timer t3 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-19 v1.1, 2011-03 gpt12, v1.5 timer t2/t4 run control each of the auxiliary timers t2 and t4 can be started or stopped by software in two different ways: ? through the associated timer run bit (t2r or t4r). in this case it is required that the respective control bit txrc = 0. ? through the core timer?s run bit (t3r). in this case the respective remote control bit must be set (txrc = 1). the selected run bit is relevant in all operating modes of t2/t4. setting the bit will start the timer, clearing the bit stops the timer. in gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed). note: if remote control is selected t3r will start/stop timer t3 and the selected auxiliary timer(s) synchronously. t4irdis 12 rw timer 4 interrupt disable 0 b interrupt generation for t4chdir and t4edge interrupts in incremental interface mode is enabled 1 b interrupt generation for t4chdir and t4edge interrupts in incremental interface mode is disabled t4edge 13 rwh timer 4 edge detection the bit is set on each successful edge detection. the bit has to be cleared by software. 0 b no count edge was detected 1 b a count edge was detected t4chdir 14 rwh timer 4 count direction change the bit is set on a change of the count direction of timer 4. the bit has to be cleared by software. 0 b no change in count direction was detected 1 b a change in count direction was detected t4rdir 15 rh timer 4 rotation direction 0 b timer 4 counts up 1 b timer 4 counts down 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-20 v1.1, 2011-03 gpt12, v1.5 count direct ion control the count direction of the gpt1 timers (core timer and auxiliary ti mers) is controlled in the same way, either by software or by the external input pin txeud. please refer to the description in table 30-1 . note: when pin txeud is used as external count direction control input, it must be configured as input (its corresponding di rection control bit must be cleared). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-21 v1.1, 2011-03 gpt12, v1.5 30.1.4 gpt1 auxiliary timers t2/t4 operating modes the operation of the auxiliary timers in the basic operating modes is almost identical with the core timer?s operation, with very few exceptions. additionally, some combined operating modes can be selected. timers t2 and t4 in timer mode timer mode for an auxiliary timer tx is selected by setting its bitfield txm in register txcon to 000 b . figure 30-10 block diagram of an auxiliary timer in timer mode prescaler auxiliary timer tx bps 1 txi f gpt f tx count interrupt (src0 or src2) mcb05395_mod mux up/down 0 1 txeud =1 txud txude mux txrc txr t3r x = 2, 4 0 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-22 v1.1, 2011-03 gpt12, v1.5 timers t2 and t4 in gated timer mode gated timer mode for an auxiliary timer tx is selected by setting bitfield txm in register txcon to 010 b or 011 b . bit txm.0 (txcon.3) selects the active level of the gate input. note: a transition of the gate signal at txin does not cause an interrupt request. interrupts of timer 2 are handled by register src0 and interrupts of timer 4 are handled by register src2. figure 30-11 block diagram of an au xiliary timer in gated timer mode note: there is no output toggle latch for t2 and t4. start/stop of an auxiliary timer can be controlled locally or remotely. prescaler gate ctrl. auxiliary timer tx bps 1 txi f gpt f tx count interrupt (src0 or src2) txm mcb05396 _mod mux up/down 0 1 txeud =1 txud txude mux txrc txr t3r x = 2, 4 0 1 txin www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-23 v1.1, 2011-03 gpt12, v1.5 timers t2 and t4 in counter mode counter mode for an auxiliary timer tx is selected by setting bitfield txm in register txcon to 001 b . in counter mode, an auxiliary timer can be clocked either by a transition at its external input line txin, or by a transition of timer t3?s toggle latch t3otl. the event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin or at the toggle latch. bitfield txi in control register txcon selects the triggering transition (see table 30-5 ). figure 30-12 block diagram of an auxiliary timer in counter mode note: only state transitions of t3otl which are caused by the overflows/underflows of t3 will trigger the counter function of t2/t4. modifications of t3otl via software will not trigger the counter function of t2/t4. table 30-5 gpt1 auxiliary timer (counter mode) input edge selection t2i/t4i triggering edge for counter increment/decrement x00 b none. counter tx is disabled 001 b positive transition (rising edge) on txin 010 b negative transition (falling edge) on txin 011 b any transition (rising or falling edge) on txin 101 b positive transition (rising edge) of t3 toggle latch t3otl 110 b negative transition (falling edge) of t3 toggle latch t3otl 111 b any transition (rising or falling edge) of t3 toggle latch t3otl auxiliary timer tx count interrupt (src0 or src2 ) mcb05397 _mod mux up/down 0 1 txeud =1 txud txude mux txrc txr t3r x = 2, 4 txi mux txi.2 txin t3 toggle latch 0 1 0 1 edge select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-24 v1.1, 2011-03 gpt12, v1.5 for counter operation, pin txin must be configured as input. the maximum input frequency allowed in counter mode depends on the selected prescaler value. to ensure that a transition of the count input signal applied to txin is recognized correctly, its level must be held high or low for a minimu m number of module clock cycles before it changes. this information can be found in section 30.1.5 . timers t2 and t4 in incremental interface mode incremental interface mode for an auxiliary timer tx is selected by setting bitfield txm in the respective register txcon to 110 b or 111 b . in incremental interface mode, the two inputs associated with an auxiliary timer tx (txin, txeud) are used to interface to an incremental encoder. tx is clocked by each transition on one or both of the external input pins to provide 2-fold or 4-fold resolution of the encoder input. figure 30-13 block diagram of an auxiliary timer in incremental interface mode the operation of the auxiliary timers t2 and t4 in incremental interface mode and the interrupt generation are the same as described for the core timer t3. the descriptions, figures and tables apply accordingly. note: timers t2 and t4 operating in increment al interface mode automatically provide information on the sensor?s current position. for dynamic information (speed, acceleration, deceleration) see ?combined capture modes? on page 30-59 ). mcb05398_mod count overflow underflow txeud tx edge tx rdir mux 0 1 =1 txud txude change detect & txch dir txm txm & >1 _ phase detect mux txrc txr t3r txin txi txirdis interrupt (src0 or src2) auxiliary timer tx 0 1 edge select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-25 v1.1, 2011-03 gpt12, v1.5 timer concatenation using the toggle bit t3otl as a clock source for an auxiliary timer in counter mode concatenates the core timer t3 with the respective auxiliary timer. this concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of t3otl is selected to clock the auxiliary timer. ? 32-bit timer/counter: if both a positive and a negative transition of t3otl are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer t3. thus, the two timers form a 32-bit timer. ? 33-bit timer/counter: if either a positive or a negative transition of t3otl is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer t3. this configuration forms a 33-bit timer (16-bit core timer + t3otl + 16 -bit auxiliary timer). as long as bit t3otl is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer. the count directions of the two concatenated timers are not required to be the same. this offers a wide variety of different configurations. t3, which represents the low-order part of th e concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case. figure 30-14 concatenation of core timer t3 and an auxiliary timer mca05399 _mod toggle latch t3out interrupt (src1 ) count t3r core timer t3 operating mode control bps 1 txi t3i n f gpt auxiliary timer tx txi 0 1 mux txi.2 txin interrupt (src0 or src2) up/down up/down count mux txrc txr t3r 0 1 x = 2, 4 edge select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-26 v1.1, 2011-03 gpt12, v1.5 when reading the low and high parts of the concatenated timer, care must be taken to obtain consistent values in particular after a timer overflow/underflow (e.g. one part may already have considered an overflow, while the other has not). note: this is a general issue when readin g multi-word results with consecutive instructions, and not necessarily unique to the gpt12 module architecture. the following algorithm may be used to read concatenated gpt1 timers, represented by timer_high (for auxiliary timer, here t2 ) and timer_low (for core timer t3). the high part is read twice, and reading of the low part is repeated if two different values were read for the high part: ? timer_high_tmp = t2 ? timer_low = t3 ? wait two basic clock cycles (to allow increm ent/decrement of auxiliary timer in case of core timer overflow/underflow) - see table 30-6 ? timer_high = t2 ? if timer_high is not equal to timer_high_tmp then timer_low = t3 after execution of this algorithm, timer_high and timer_low represent a consistent time stamp of the concatenated timers. the equivalent number of system clock cycles corresponding to two basic clock cycles is shown in table 30-6 . in case the required timer resolution can be ac hieved with different combinations of the block prescaler bps1 and the individual prescalers txi, the variant with the smallest value for the block prescaler may be chosen to minimize the waiting time. auxiliary timer in reload mode reload mode for an auxiliary timer tx is selected by setting bitfield txm in the respective register txcon to 100 b . in reload mode, the core timer t3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals. the trigger signal is selected the same way as the clock source for counter mode (see table 30-5 ), i.e. a transition of the auxiliary timer?s input txin or the toggle latch t3otl may trigger the reload. note: when programmed for reload mode, the respective auxiliary timer (t2 or t4) stops independently of its run flag t2r or t4r. the timer input pin txin must be configured as input if it shall trigger a reload operation. table 30-6 number of system clock cycles to wait for two basic clock cycles block prescaler bps1 = 01 b bps1 = 00 b bps1 = 11 b bps1 = 10 b number of system clocks 8 163264 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-27 v1.1, 2011-03 gpt12, v1.5 figure 30-15 gpt1 auxiliary timer in reload mode upon a trigger signal, t3 is loaded with the co ntents of the respective timer register (t2 or t4) and the respective serv ice request flag (srr) is set. note: when a t3otl transition is selected for the trigger signal, the service request flag will also be set upon a trigger, indicating t3?s overflow or underflow. modifications of t3otl via software will not trig ger the counter function of t2/t4. to ensure that a transition of the reload input signal applied to txin is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in section 30.1.5 . the reload mode triggered by the t3 toggl e latch can be used in a number of different configurations. the following functions can be performed, depending on the selected active transition: ? if both a positive and a negative transition of t3otl are selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows. this is the standard reload mode (reload on overflow/underflow). ? if either a positive or a negative transition of t3otl is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow. ? using this ?single-transition? mode for both auxiliary timers allows to perform very flexible pulse width modulation (pwm). one of the auxiliary timers is programmed to reload the core timer on a positive transition of t3otl, the other is programmed for a reload on a negative transition of t3otl. with this combination the core timer is alternately reloaded from the two auxiliary timers. mca05400 _mod toggle latch t3 ou t interrupt (src1) count t3r core timer t3 operating mode control bps 1 txi up/down t3i n f gpt auxiliary timer tx txi reload 0 1 mux txi.2 txin interrupt (src0 or src2) x = 2, 4 edge select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-28 v1.1, 2011-03 gpt12, v1.5 figure 30-16 shows an example for the generation of a pwm signal using the ?single- transition? reload mechanism. t2 defines the high time of the pwm signal (reloaded on positive transitions) and t4 defines the low time of the pwm signal (reloaded on negative transitions). the pwm signal can be output on pin t3out if t3oe = 1. with this method, the high and low time of the pwm signal can be varied in a wide range. note: the output toggle latch t3otl is accessible via software and may be changed, if required, to modify the pwm signal. however, this will not trigger the reloading of t3. figure 30-16 gpt1 timer reload configuration for pwm generation note: although possible, selecting the same re load trigger event for both auxiliary timers should be avoided. in such a case, both reload registers would try to load the core timer at the same time. if this combination is selected, t2 is disregarded and the contents of t4 is reloaded. the implementation of the gpt1 finite state machine may require special consideration in following applications: ? reading t3 by software with t2/t4 in reload mode ? reload of t3 from t2 with setting bps1 = 01 b and t3i = 000 b mca05401_mod interrupt (src0) auxiliary timer t2 edge select t2i reload 0 1 mux t2i.2 toggle latch t3ou t interrupt (src1) count t3r core timer t3 operating mode control bps 1 t3i up/down t3i n f gpt t2i n auxiliary timer t4 edge select t4i reload 0 1 mux t4i.2 t4i n interrupt (src2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-29 v1.1, 2011-03 gpt12, v1.5 when t2 or t4 are used to reload t3 on overflow/underflow, and t3 is read by software on the fly, the following unexpected values may be read from t3: ? when t3 is counting up, 0000 h or 0001 h may be read from t3 directly after an overflow, although the reload value in t2/t4 is higher (0001 h may be read in particular if bps1 = 01 b and t3i = 000 b ). ? when t3 is counting down, ffff h or fffe h may be read from t3 directly after an underflow, although the reload value in t2/t4 is lower (fffe h may be read in particular if bps1 = 01 b and t3i = 000 b ). note: all timings derived from t3 in this configuration (e.g. distance between interrupt requests, pwm waveform on t3out, etc.) are accurate except for the specific case described below. workaround: ? when t3 counts up, and value_x < reload value is read from t3, value_x should be replaced with the reload value for further calculations. ? when t3 counts down, and value_x > reload value is read from t3, value_x should be replaced with the reload value for further calculations. alternatively, if the intention is to identify the overflow/underflow of t3, the t3 interrupt request may be used. when t2 is used to reload t3 in the configuration with bps1 = 01 b and t3i = 000 b (i.e. fastest configuration/highest resolution of t3), the reload of t3 is performed with a delay of one basic clock cycle. workaround 1: to compensate the delay and achieve correct timing, ? increment the reload value in t2 by 1 when t3 is configured to count up, ? decrement the reload value in t2 by 1 when t3 is configured to count down. workaround 2: use t4 instead of t2 as reload register for t3. in this configuration the reload of t3 is not delayed, i.e. the effect described above does not occur with t4. auxiliary timer in capture mode capture mode for an auxiliary timer tx is sele cted by setting bitfield txm in the respective register txcon to 101 b . in capture mode, the contents of the core timer t3 are latched into an auxiliary timer register in response to a signal transit ion at the respective auxiliary timer?s external input pin txin. the capture trigger signal can be a positive, a negative, or both a positive and a negative transition. the two least significant bits of bitfield txi select the active transition (see table 30-5 ). bit 2 of txi is irrelevant for capture mode and must be cleared (txi.2 = 0). note: when programmed for capture mode, the respective auxiliary timer (t2 or t4) stops independently of its run flag t2r or t4r. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-30 v1.1, 2011-03 gpt12, v1.5 figure 30-17 gpt1 auxiliary timer in capture mode upon a trigger (selected transition) at the corresponding input pin txin the contents of the core timer are loaded into the auxiliary timer register and the associated service request flag srr will be set. for capture mode operation, the respective timer input pin txin must be configured as input. to ensure that a transition of the capture input signal applied to txin is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in section 30.1.5 . mca05402_mod toggle latch t3 ou t interrupt (src1) count t3r core timer t3 operating mode control bps 1 t3i up/down t3i n f gpt auxiliary timer tx txi capture txin x = 2, 4 y = 4, 2 to ty edge select interrupt (src0 or src2) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-31 v1.1, 2011-03 gpt12, v1.5 30.1.5 gpt1 clock signal control all actions within the timer block gpt1 are triggered by transitions of its basic clock. this basic clock is derived from the system clo ck by a basic block prescaler, controlled by bitfield bps1 in register t3con (see figure 30-1 ). the count clock can be generated in two different ways: ? internal count clock , derived from gpt1?s basic clock via a programmable prescaler, is used for (gated) timer mode. ? external count clock , derived from the timer?s input pin(s), is used for counter mode. for both ways, the basic clock determines the maximum count frequency and the timer?s resolution: internal count clock generation in timer mode and gated timer mode, the count clock for each gpt1 timer is derived from the gpt1 basic clock by a programmable prescaler, controlled by bitfield txi in the respective timer?s control register txcon. the count frequency f tx for a timer tx and its resolution r tx are scaled linearly with lower clock frequencies, as can be seen from the following formula: (30.1) the effective count frequency depends on the common module clock prescaler factor f(bps1) as well as on the indivi dual input prescaler factor 2 TC1798 the general purpose timer 12 (gpt12) users manual 30-32 v1.1, 2011-03 gpt12, v1.5 table 30-8 gpt1 overall prescaler factors for internal count clock individual prescaler for tx common prescaler for module clock 1) 1) please note the non-linear encoding of bitfield bps1. bps1 = 01 b bps1 = 00 b bps1 = 11 b bps1 = 10 b txi = 000 b 481632 txi = 001 b 8 163264 txi = 010 b 16 32 64 128 txi = 011 b 32 64 128 256 txi = 100 b 64 128 256 512 txi = 101 b 128 256 512 1024 txi = 110 b 256 512 1024 2048 txi = 111 b 512 1024 2048 4096 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-33 v1.1, 2011-03 gpt12, v1.5 external count clock input the external input signals of the gpt1 block are sampled with the gpt1 basic clock (see figure 30-1 ). to ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing. a signal transition is recognized if two subsequent samples of the input signal represent different levels. therefore, a minimum of two basic clock periods are required for the sampling of an external input signal. thus, the maximum frequency of an input signal must not be higher than half the basic clock. table 30-9 summarizes the resulting requirements for external gpt1 input signals. these limitations are valid for all external input signals to gpt1, including the external count signals in counter mode and incremental interface mode, the gate input signals in gated timer mode, and the external direction signals. table 30-9 gpt1 external input signal limits gpt1 basic clock = 10 mhz input frequ. factor gpt1 divider bps1 input phase duration gpt1 basic clock = 40 mhz max. input frequency min. level hold time max. input frequency min. level hold time 1.25 mhz 400 ns f gpt /8 01 b 4 t gpt 5.0 mhz 100 ns 625.0 khz 800 ns f gpt /16 00 b 8 t gpt 2.5 mhz 200 ns 312.5 khz 1.6 s f gpt /32 11 b 16 t gpt 1.25 mhz 400 ns 156.25 khz 3.2 s f gpt /64 10 b 32 t gpt 625.0 khz 800 ns www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-34 v1.1, 2011-03 gpt12, v1.5 30.1.6 gpt1 timer registers t2 timer 2 register (34 h ) reset value: 0000 0000 h t3 timer 3 register (38 h ) reset value: 0000 0000 h t4 timer 4 register (3c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 tx rwh field bits type description tx [15:0] rwh timer x contains the current value of timer x. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-35 v1.1, 2011-03 gpt12, v1.5 30.1.7 interrupt cont rol for gpt1 timers when a timer overflows from ffff h to 0000 h (when counting up), or when it underflows from 0000 h to ffff h (when counting down), its service request flag (srr) in register srcx will be set. interrupts of timer 2 are connected with register src0. interrupts of timer 3 are connected with register src1. interrupts of timer 4 are connected with register src2. src0 service request control 0 register (fc h ) reset value: 0000 0000 h src1 service request control 1 register (f8 h ) reset value: 0000 0000 h src2 service request control 2 register (f4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number 00 h service request is never serviced 01 h service request is on lowest priority ... ff h service request is on highest priority tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp service is initiated sre 12 rw service request enable 0 b service request is disabled 1 b service request is enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-36 v1.1, 2011-03 gpt12, v1.5 srr 13 rh service request flag 0 b no service request is pending 1 b a service request is pending clrr 14 w request clear bit clrr is required to clear srr. 0 b no action 1 b clear srr; bit value is not stored; read always returns 0; no action if setr is set also. setr 15 w request set bit setr is required to set srr. 0 b no action 1 b set srr; bit value is not stored; read always returns 0; no action if clrr is set also. 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-37 v1.1, 2011-03 gpt12, v1.5 30.2 timer block gpt2 both timers of block gpt2 (t5, t6) can run in one of 3 basic modes: timer mode, gated timer mode, or counter mode. all timers can count up or down. each timer of gpt2 is controlled by a separate control register txcon. each timer has an input pin txin (alternate pin function) associated with it, which serves as the gate control in gated timer mode, or as the count input in counter mode. the count direction (up/down) may be progra mmed via software or may be dynamically altered by a signal at the external up/down control input txeud (alternate pin function). an overflow/underflow of core timer t6 is indicated by the output toggle latch t6otl, whose state may be output on the associated pin t6out (alternate pin function). the auxiliary timer t5 may additionally be concatenated with core timer t6 (through t6otl). the capture/reload register caprel can be used to capture the contents of timer t5, or to reload timer t6. a special mode facilitates the use of register caprel for both functions at the same time. this mode allows frequency multiplication. the capture function is triggered by the input pin capin, or by gpt1 timer?s t3 input lines t3in and t3eud. the reload function is triggered by an overflow or underflow of timer t6. the current contents of each timer can be read or modified by the cpu by accessing the corresponding timer count registers t5 or t6. when any of the timer registers is written by the cpu in the state immediately preceding a timer increment, decrement, reload, or capture operation, the cpu write operation has priority in order to guarantee correct results. the interrupts of gpt2 are controlled through the service request control registers src3, src4, and src5. note: the timing requirements for external input signals can be found in section 30.2.6 , section 30.5 summarizes the module interface signals, including pins. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-38 v1.1, 2011-03 gpt12, v1.5 figure 30-18 gpt2 block diagram note: the gpt2 module uses a finite state ma chine to control the actions. since multiple interactions are possible between the time rs (t5, t6) and register caprel, these elements are processed sequentially. however, all actions are normally completed within one basic clock cycle. the gpt2 state machine has 4 states (1 states when bps1 = 01 b ) and processes t6 before t5. caprel mode control t5 mode control gpt2 timer t 5 t6 mode control gpt2 timer t 6 gpt2 caprel t6otl t5in t3in/ t3eud capin t6in t6out u/d u/d interrupt (src3) interrupt (src5) interrupt (src4) t6ofl clear capture mc_gpt0108_bldiax4_mod.vsd toggle ff clear 2 n : 1 f gpt basic clock t6con.bps2 reload t5eud t6eud www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-39 v1.1, 2011-03 gpt12, v1.5 30.2.1 gpt2 core timer t6 control the current contents of the core timer t6 are reflected by its count register t6. this register can also be written to by the cpu, for example, to set the initial start value. the core timer t6 is configured and controlled via its control register t6con. t6con timer 6 control register (20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t6 sr t6 clr 0bps2 t6 otl t6 oe t6 ude t6 ud t6 r t6m t6i rw rw r rw rwh rw rw rw rw rw rw field bits type description t6i [2:0] rw timer t6 input parameter selection depends on the operating mode, see respective sections for encoding: table 30-16 for timer mode and gated timer mode table 30-11 for counter mode t6m [5:3] rw timer t6 mode control (basic operating mode) 000 b timer mode 001 b counter mode 010 b gated timer mode with gate active low 011 b gated timer mode with gate active high 100 b reserved. do not use this combination 101 b reserved. do not use this combination 110 b reserved. do not use this combination 111 b reserved. do not use this combination t6r 6rw timer t6 run bit 0 b timer t6 stops 1 b timer t3 runs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-40 v1.1, 2011-03 gpt12, v1.5 t6ud 7rw timer 6 up / down control 1) (when t6ude = ?0?) 0 b timer t6 counts up 1 b timer t6 counts down t6ude 8rw timer t6 up/down control 1) 0 b timer t6 counts up 1 b timer t6 counts down t6oe 9rw overflow/underflow output enable 0 b alternate output function disabled 1 b state of t6 toggle latch is output on pin t6out t6otl 10 rwh timer t6 overflow toggle latch toggles on each overflow/underflow of t6. can be set or cleared by software (see separate description) bps2 [12:11] rw gpt2 block prescaler control selects the basic clock for block gpt2 (see also section 30.2.6 ) 00 b f gpt /4 01 b f gpt /2 10 b f gpt /16 11 b f gpt /8 t6clr 14 rw timer t6 clear enable bit 0 b timer t6 is not cleared on a capture event 1 b timer t6 is cleared on a capture event t6sr 15 rw timer 6 reload mode enable 0 b reload from register caprel disabled 1 b reload from register caprel enabled 0 [31:16], 13 r reserved read as 0; should be written with 0. 1) see table 30-10 for coding of bits t6ud and t6ude field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-41 v1.1, 2011-03 gpt12, v1.5 timer t6 run control the core timer t6 can be started or stopped by software through bit t6r (timer t6 run bit). this bit is relevant in all operating modes of t6. setting bit t6r will start the timer, clearing bit t6r stops the timer. in gated timer mode, the timer will only run if t6r = 1 and the gate is active (high or low, as programmed). note: when bit t5rc in timer control register t5con is set, bit t6r will also control (start and stop) the auxiliary timer t5. count direct ion control the count direction of the gpt2 timers (core timer and auxiliary timer) can be controlled either by software or by the external in put pin txeud (timer tx external up/down control input). these options are selected by bits txud and txude in the respective control register txcon. when the up/down control is provided by software (bit txude = 0), the count direction can be altered by setting or clearing bit txud. when bit txude = 1, pin txeud is selected to be the controlling source of the count direction. however, bit txud can still be used to reverse the actual count direction, as shown in table 30-10 . the count direction can be changed regardless of whether or not the timer is running. table 30-10 gpt2 timer count direction control pin txeud bit txude bit txud count direction x 0 0 count up x 0 1 count down 0 1 0 count up 1 1 0 count down 0 1 1 count down 1 1 1 count up www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-42 v1.1, 2011-03 gpt12, v1.5 timer 6 output toggle latch the overflow/underflow signal of timer t6 is connected to a block named ?toggle latch?, shown in the timer mode diagrams. figure 30-19 illustrates the details of this block. an overflow or underflow of t6 will clock two latches: the first latch represents bit t6otl in control register t6con. the second latch is an internal latch toggled by t6otl?s output. both latch outputs are connected to the input control block of the auxiliary timer t5. the output level of the shadow latch will match the output level of t6otl, but is delayed by one clock cycle. when the t6otl value changes, this will result in a temporarily different output level from t6otl and the shadow latch, which can trigger the selected count event in t5. when software writes to t6otl, both latche s are set or cleared simultaneously. in this case, both signals to the aux iliary timers carry the same level and no edge will be detected. bit t6oe (overflow/underflow output enable) in register t6con enables the state of t6otl to be monitored via an exte rnal pin t6out. when t6otl is linked to an external port pin (must be configured as output), t6out can be used to control external hw. if t6oe = 1, pin t6out outputs the state of t6otl. if t6oe = 0, pin t6out outputs a high level (while it selects the timer output signal). as can be seen from figure 30-19 , when latch t6otl is modified by software to determine the state of the output line, also the internal shadow latch is set or cleared accordingly. therefore, no trigger cond ition is detected by t5 in this case. figure 30-19 block diagram of the toggle latch logic of core timer t6 30.2.2 gpt2 core time r t6 operating modes timer t6 can operate in one of several modes. mc_gpt0106_otl.vsd toggle latch logic txout set/clear (sw) core timer overflow/ underflow shadow latch 1 0 mux 1 txoe txotl to port logic to aux. timer input logic www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-43 v1.1, 2011-03 gpt12, v1.5 timer 6 in timer mode timer mode for the core timer t6 is selected by setting bitfield t6m in register t6con to 000 b . in this mode, t6 is clocked with the module?s input clock f gpt divided by two programmable prescalers controlled by bitfields bps2 and t6i in register t6con. please see section 30.2.6 for details on the input clock options. figure 30-20 block diagram of core timer t6 in timer mode prescaler core timer t6 toggle latch mcb05403_x4_mod bps2 t6i up/down f gpt f t6 t6r count t6ou t interrupt (src4) to t5/ caprel t6 of l mux 0 1 t6eu d =1 t6u d t6u d e www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-44 v1.1, 2011-03 gpt12, v1.5 gated timer mode gated timer mode for the core timer t6 is selected by setting bitfield t6m in register t6con to 010 b or 011 b . bit t6m.0 (t6con.3) selects the active level of the gate input. the same options for the input frequency are available in gated timer mode as in timer mode (see section 30.2.6 ). however, the input clock to the timer in this mode is gated by the external input pin t6in (timer t6 external input). to enable this operation, the associated pin t6in must be configured as input (the corresponding direction control bit must contain 0). figure 30-21 block diagram of core timer t6 in gated timer mode if t6m = 010 b , the timer is enabled when t6in shows a low level. a high level at this line stops the timer. if t6m = 011 b , line t6in must have a high level in order to enable the timer. additionally, the timer can be turned on or off by software using bit t6r. the timer will only run if t6r is 1 and t he gate is active. it will stop if either t6r is 0 or the gate is inactive. note: a transition of the gate signal at pin t6in does not cause an interrupt request. prescaler gate ctrl. core timer t6 toggle latch mcb05404 _x4_mod bps 2 t6i up/down f gpt f t6 t6r count t6 ou t interrupt (src4) to t5, caprel clear t6ofl t6in mux 0 1 t6eud =1 t6u d t6 u d e www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-45 v1.1, 2011-03 gpt12, v1.5 counter mode counter mode for the core timer t6 is selected by setting bitfield t6m in register t6con to 001 b . in counter mode, timer t6 is clocked by a transition at the external input pin t6in. the event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative tran sition at this line. bitfield t6i in control register t6con selects the triggering transition (see table 30-11 ). figure 30-22 block diagram of core timer t6 in counter mode for counter mode operation, pin t6in must be configured as input. the maximum input frequency allowed in counter mode depends on the selected prescaler value. to ensure that a transition of the count input signal applied to t6in is recognized correctly, its level must be held high or low for a minimu m number of module clock cycles before it changes. this information can be found in section 30.2.6 . table 30-11 gpt2 core timer t6 (counter mode) input edge selection t6i triggering edge for counter increment/decrement 000 b none. counter t6 is disabled 001 b positive transition (rising edge) on t6in 010 b negative transition (falling edge) on t6in 011 b any transition (rising or falling edge) on t6in 1xx b reserved. do not use this combination mcb05405_x4_mod core timer t6 toggle latch up/down t6i n t6 r count t6out interrupt (src4 ) to t5, caprel t6i clear t6ofl edge select mux 0 1 t6eud =1 t6ud t6ude www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-46 v1.1, 2011-03 gpt12, v1.5 30.2.3 gpt2 auxiliary timer t5 control auxiliary timer t5 can be configured for timer mode, gated timer mode, or counter mode with the same options for the timer frequencies and the count signal as the core timer t6. in addition to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. the contents of t5 may be captured to register caprel upon an external or an internal trigger. the start/stop function of the auxiliary timers can be remotely controlled by the t6 run control bit. several timers may thus be controlled synchronously. the current content s of the auxiliary timer are reflec ted by its count register t5. this register can also be written to by the cpu, for example, to set the initial start value. the individual configurations for timer t5 are determined by its control register t5con. some bits in this register also control the function of the caprel register. note that functions which are present in all timers of block gpt2 are controlled in the same bit positions and in the same manner in each of the specific control registers. note: the auxiliary timer has no output togg le latch and no alternate output function. t5con timer 5 control register (1c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 t5 sc t5 clr ci 0 ct3 t5 rc t5 ude t5 ud t5 r t5m t5i rwrwh rw rwrwrwrwrwrw rw rw field bits type description t5i [2:0] rw timer t5 input parameter selection depends on the operating mode, see respective sections for encoding: table 30-16 for timer mode and gated timer mode table 30-11 for counter mode www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-47 v1.1, 2011-03 gpt12, v1.5 t5m [5:3] rw timer t5 mode control (basic operating mode) 000 b timer mode 001 b counter mode 010 b gated timer mode with gate active low 011 b gated timer mode with gate active high 1xx b reserved. do not use this combination t5r 6rw timer t5 run bit 0 b timer t5 stops 1 b timer t5 runs note: this bit only controls timer t5 if bit t5rc = 0. t5ud 7rw timer t5 up/down control 1) 0 b timer t5 counts up 1 b timer t5 counts down t5ude 8rw timer t5 external up/down enable 1) 0 b input t5eud is disconnected 1 b direction influenced by input t5eud t5rc 9rw timer t5 remote control 0 b timer t5 is controlled by its own run bit t5r 1 b timer t5 is controlled by the run bit t6r of core timer 6, not by bit t5r ct3 10 rw timer t3 capture trigger enable 0 b capture trigger from input line capin 1 b capture trigger from t3 input lines t3in and/or t3eud ci [13:12] rw register caprel capture trigger selection 2) 00 b capture disabled 01 b positive transition (rising edge) on capin 3) or any transition on t3in 10 b negative transition (falling edge) on capin or any transition on t3eud 11 b any transition (rising or falling edge) on capin or any transition on t3in or t3eud t5clr 14 rw timer t5 clear enable bit 0 b timer t5 is not cleared on a capture event 1 b timer t5 is cleared on a capture event t5sc 15 rw timer 5 capture mode enable 0 b capture into register caprel disabled 1 b capture into register caprel enabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-48 v1.1, 2011-03 gpt12, v1.5 0 11 rw reserved have be written with 0. 0 [31:16] r reserved read as 0; should be written with 0. 1) see table 30-10 for encoding of bits t5ud and t5ude. 2) to define the respective trigger source si gnal, also bit ct3 must be regarded (see table 30-14 ). 3) rising edge must be selected if capturing is triggered by the internal gpt1 read signals (see register pisel and ?combined capture modes? on page 30-59 ). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-49 v1.1, 2011-03 gpt12, v1.5 timer t5 run control the auxiliary timer t5 can be started or stopped by software in two different ways: ? through the associated timer run bit (t5r). in this case it is required that the respective control bit t5rc = 0. ? through the core timer?s run bit (t6r). in this case the respective remote control bit must be set (t5rc = 1). the selected run bit is relevant in all operating modes of t5. setting the bit will start the timer, clearing the bit stops the timer. in gated timer mode, the timer will only run if the selected run bit is set and the gate is active (high or low, as programmed). note: if remote control is selected t6r will st art/stop timer t6 and the auxiliary timer t5 synchronously. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-50 v1.1, 2011-03 gpt12, v1.5 30.2.4 gpt2 auxiliary timer t5 operating modes the operation of the auxiliary timer in the basic operating modes is almost identical with the core timer?s operation, with very few exceptions. additionally, some combined operating modes can be selected. timer t5 in timer mode timer mode for the auxiliary timer t5 is selected by setting its bitfield t5m in register t5con to 000 b . figure 30-23 block diagram of au xiliary timer t5 in timer mode prescaler auxiliary timer t5 bps2 t5i f gpt f t5 count interrupt (src3) mcb05406_x4_mod up/down mux t5rc t5r t6r 0 1 clear mux 0 1 t5eud =1 t5 u d t5ude www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-51 v1.1, 2011-03 gpt12, v1.5 timer t5 in gated timer mode gated timer mode for the auxiliary timer t5 is selected by setting bitfield t5m in register t5con to 010 b or 011 b . bit t5m.0 (t5con.3) selects the active level of the gate input. note: a transition of the gate signal at line t5in does not cause an interrupt request. figure 30-24 block diagram of auxili ary timer t5 in gated timer mode note: there is no output toggle latch for t5. start/stop of the auxiliary timer ca n be controlled locally or remotely. timer t5 in counter mode counter mode for auxiliary timer t5 is selected by setting bitfield t5m in register t5con to 001 b . in counter mode, the auxiliary timer can be clocked either by a transition at its external input line t5in, or by a transition of timer t6?s toggle latch t6otl. the event causing an increment or decrement of a time r can be a positive, a negative, or both a positive and a negative transition at either t he respective input pin or at the toggle latch. bitfield t5i in control register t5con selects the triggering transition (see table 30-12 ). prescaler gate ctrl. auxiliary timer t5 bps2 t5i t5i n f gpt f t5 count interrupt (src3) mcb05407_x4_mod mux t5 r c t5r t6r clear up/down 0 1 mux 0 1 t5eud =1 t5u d t5u d e www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-52 v1.1, 2011-03 gpt12, v1.5 figure 30-25 block diagram of aux iliary timer t5 in counter mode note: only state transitions of t6otl which are caused by the overflows/underflows of t6 will trigger the counter function of t5 . modifications of t6otl via software will not trigger the counter function of t5. for counter operation, pin t5in must be configured as input (the respective direction control bit dpx.y must be 0). the maximum input frequency allowed in counter mode depends on the selected prescaler value. to ensure that a transition of the count input signal applied to t5in is recognized correctly, its level must be held high or low for a minimum number of module clock cycles bef ore it changes. this information can be found in section 30.2.6 . table 30-12 gpt2 auxiliary timer (counter mode) input edge selection t5i triggering edge for counter increment/decrement x00 b none. counter t5 is disabled 001 b positive transition (rising edge) on t5in 010 b negative transition (falling edge) on t5in 011 b any transition (rising or falling edge) on t5in 101 b positive transition (rising edge) of t6 toggle latch t6otl 110 b negative transition (falling edge) of t6 toggle latch t6otl 111 b any transition (rising or falling edge) of t6 toggle latch t6otl auxiliary timer t5 count interrupt (src3) mcb05408_x4_mod up/down mux t5rc t5r t6r t5i mux t5 i. 2 t5i n t6 toggle latch 0 1 clear 0 1 edge select mux 0 1 t5eu d =1 t5ud t5ude www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-53 v1.1, 2011-03 gpt12, v1.5 timer concatenation using the toggle bit t6otl as a clock source for the auxiliary timer in counter mode concatenates the core timer t6 with the auxiliary timer t5. this concatenation forms either a 32-bit or a 33-bit timer/counter, depending on which transition of t6otl is selected to clock the auxiliary timer. ? 32-bit timer/counter: if both a positive and a negative transition of t6otl are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer t6. thus, the two timers form a 32-bit timer. ? 33-bit timer/counter: if either a positive or a negative transition of t6otl is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer t6. this configuration forms a 33-bit timer (16-bit core timer + t6otl + 16 -bit auxiliary timer). as long as bit t6otl is not modified by software, it represents the state of the internal toggle latch, and can be regarded as part of the 33-bit timer. the count directions of the two concatenated timers are not required to be the same. this offers a wide variety of different configurations. t6, which represents the low-order part of th e concatenated timer, can operate in timer mode, gated timer mode or counter mode in this case. figure 30-26 concatenation of core timer t6 and auxiliary timer t5 when reading the low and high parts of the concatenated timer, care must be taken to obtain consistent values in particular after a timer overflow/underflow (e.g. one part may already have considered an overflow, while the other has not). mca05409 _mod toggle latch t6out interrupt (src4) count t6r core timer t6 operating mode control bps 2 t6i clear t6i n f gpt auxiliary timer t5 t5i 0 1 mux t5i.2 t5i n interrupt (src3) up/down clear up/down count mux t5rc t5r t6r 0 1 edge select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-54 v1.1, 2011-03 gpt12, v1.5 note: this is a general issue when readin g multi-word results with consecutive instructions, and not necessarily unique to the gpt12 module architecture. the following algorithm may be used to read concatenated gpt1 timers, represented by timer_high (for auxiliary timer, here t5 ) and timer_low (for core timer t6). the high part is read twice, and reading of the low part is repeated if two different values were read for the high part: ? timer_high_tmp = t5 ? timer_low = t6 ? wait two basic clock cycles (to allow increm ent/decrement of auxiliary timer in case of core timer overflow/underflow) - see table 30-13 ? timer_high = t5 ? if timer_high is not equal to timer_high_tmp then timer_low = t6 after execution of this algorithm, timer_high and timer_low represent a consistent time stamp of the concatenated timers. the equivalent number of system clock cycles corresponding to two basic clock cycles is shown in table 30-13 . in case the required timer resolution can be ac hieved with different combinations of the block prescaler bps2 and the individual prescalers txi, the variant with the smallest value for the block prescaler may be chosen to minimize the waiting time. e.g. in order to run t6 at f fpi /512, select bps2 = 00 b , t6i = 111 b , and insert 8 nops (or other instructions) to ensure the required waiting time before reading timer_high the second time. table 30-13 number of system clock cycl es to wait for two basic clock cycles block prescaler bps2 = 01 b bps2 = 00 b bps2 = 11 b bps2 = 10 b number of system clocks 481632 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-55 v1.1, 2011-03 gpt12, v1.5 30.2.5 gpt2 register caprel operating modes the capture/reload register caprel can be used to capture the contents of timer t5, or to reload timer t6. a special mode facilitates the use of register caprel for both functions at the same time. this mode allows frequency multiplication. the capture function is triggered by the input pin capin, by gpt1 timer?s t3 input lines t3in and t3eud, or by read accesses to gpt1 timers. the reload function is triggered by an overflow or underflow of timer t6. in addition to the capture function, the capture trigger signal can also be used to clear the contents of timers t5 and t6 individually. the functions of register caprel are controlled via several bit(field)s in the timer control registers t5con and t6con. gpt2 capture/reload register caprel in capture mode capture mode for register caprel is selected by setting bit t5sc in control register t5con (set bitfield ci in register t5con to a non-zero value to select a trigger signal). in capture mode, the contents of the auxiliary timer t5 are latched into register caprel in response to a signal transition at the selected external input pin(s). bit ct3 selects the external input line capin or the input lines t3in and/or t3eud of gpt1 timer t3 as the source for a capture trigger. either a posi tive, a negative, or both a positive and a negative transition at line capin can be selected to trigger the capture function, or transitions on input t3in or input t3eud or both inputs, t3in and t3eud. the active edge is controlled by bitfield ci in register t5con. table 30-14 summarizes these options. table 30-14 caprel register input edge selection ct3 ci triggering signal/edge for capture mode x00 b none. capture mode is disabled. 001 b positive transition (rising edge) on capin. 1) 1) rising edge must be selected if capturing is triggered by the internal gpt1 read signals (see register pisel and ?combined capture modes? on page 30-59 ). 010 b negative transition (f alling edge) on capin. 011 b any transition (rising or falling edge) on capin. 101 b any transition (rising or falling edge) on t3in. 110 b any transition (rising or falling edge) on t3eud. 111 b any transition (rising or falling edge) on t3in or t3eud. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-56 v1.1, 2011-03 gpt12, v1.5 figure 30-27 gpt2 register caprel in capture mode when a selected trigger is detected, the cont ents of the auxiliary timer t5 are latched into register caprel and the interrupt request is activated. the same event can optionally clear timer t5 and/or timer t6. this option is enabled by bit t5clr in register t5con and bit t6clr in register t6con, respectively. if txclr = 0 the contents of timer tx is not affected by a capture. if txclr = 1 timer tx is cleared after the current timer t5 value has been latched into register caprel. note: bit t5sc only controls whether or not a capture is performed. if t5sc is cleared the external input pin(s) can still be used to clear timer t5 and/or t6, or as external interrupt input(s). this in terrupt is controlled by the caprel interrupt control register src5. when capture triggers t3in or t3eud are ena bled (ct3 = 1), register caprel captures the contents of t5 upon transitions of the selected input(s). these values can be used to measure t3?s input signals. this is useful, for example, when t3 operates in incremental interface mode, in order to derive dynamic information (speed, acceleration) from the input signals. for capture mode operation, the selected pins capin, t3in, or t3eud must be configured as input. to ensure that a transiti on of a trigger input signal applied to one of signal select auxiliary timer t5 interrupt (src3) mca05410 x11_mod up/down clear t5clr t5 sc capture caprel register t6clr 0 1 mux ct3 ci capin t3i n t3eu d count clock interrupt (src5 ) clear t6 edge select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-57 v1.1, 2011-03 gpt12, v1.5 these inputs is recognized correctly, its level must be held high or low for a minimum number of module clock cycles, detailed in section 30.2.6 . gpt2 capture/reload regist er caprel in reload mode reload mode for register caprel is selected by setting bit t6sr in control register t6con. in reload mode, the core timer t6 is reloaded with the contents of register caprel, triggered by an overflow or underflow of t6. this will not activate the interrupt request src5.srr associated with the caprel register. however, an interrupt request will be activated, indicating the overflow/underflow of t6. figure 30-28 gpt2 register caprel in reload mode mca05411 _mod caprel register t6sr core timer t6 reload up/down count clock toggle latch t6out interrupt (src4) t6ofl to t5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-58 v1.1, 2011-03 gpt12, v1.5 gpt2 capture/reload register caprel in capture-and-reload mode since the reload function and the capture function of register caprel can be enabled individually by bits t5sc and t6sr, the two functions can be enabled simultaneously by setting both bits. this feature can be used to generate an output frequency that is a multiple of the input frequency. figure 30-29 gpt2 register capre l in capture-and-reload mode this combined mode can be used to detect consecutive external events which may occur aperiodically, but where a finer resolution, that means, more ?ticks? within the time between two external events is required. for this purpose, the time between the extern al events is measured using timer t5 and the caprel register. timer t5 runs in timer mode counting up with a frequency of e.g. f gpt /32. the external events are applied to pin capin. when an external event occurs, auxiliary timer t5 interrupt (src3) up/down clear t5 sc capture caprel register 0 1 mux ct3 ci capin t3i n t3eu d count clock t5clr interrupt (src5) mca05412 x11_mod t6sr core timer t6 clear t6clr reload up/down count clock toggle latch t6out interrupt (src4) t6ofl to t5 edge select edge select www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-59 v1.1, 2011-03 gpt12, v1.5 the contents of timer t5 are latched into register caprel and timer t5 is cleared (t5clr = 1). thus, register caprel always contains the correct time between two events, measured in timer t5 increments. ti mer t6, which runs in timer mode counting down with a frequency of e.g. f gpt /4, uses the value in register caprel to perform a reload on underflow. this means, the value in register caprel represents the time between two underflows of timer t6, now measured in timer t6 increments. since (in this example) timer t6 runs 8 times faster than timer t5, it will underflow 8 times within the time between two external events. thus, the underflow signal of timer t6 generates 8 ?ticks?. upon each underflow, the interrupt request src4.srr will be activated and bit t6otl will be toggled. the state of t6otl may be output on pin t6out. this signal has 8 times more transitions than the signal which is applied to pin capin. capture correction a certain deviation of the output frequency is generated by the fact that timer t5 will count actual time units (e.g. t5 running at 1 mhz will count up to the value 64 h /100 d for a 10 khz input signal), while t6otl will only toggle upon an underflow of t6 (i.e. the transition from 0000 h to ffff h ). in the above mentioned example, t6 would count down from 64 h , so the underflow would occur after 101 timing ti cks of t6. the actual output frequency then is 79.2 khz, instead of the expected 80 khz. another possibility is to use t6 overflows. in this case, t5 counts down and t6 counts up. upon a signal transition on pin capin, the count value in t5 is captured into caprel and t5 is cleared to 0000 h . in its next clock cycle, t5 underflows to ffff h , and continues to count down with the following clocks. t6 is reloaded from caprel upon an overflow, and continues to count up with its fo llowing clock cycles (8 times faster in the above example). in this case, t5 and t6 c ount the same number of steps with their respective internal count frequency. in the above example, t5 running at 1 mhz will count down to the value ff9c h /-100 d for a 10 khz input signal applied at capin, while t6 counts up from ff9c h through ffff h to 0000 h . so the overflow occurs after 100 timing ticks of t6, and the actual output frequency at t6out then is the expected 80 khz. however, in this case caprel does not directly contain the time between two capin events, but rather its 2's complement. software will have to convert th is value, if it is required for the operation. combined capture modes for incremental interface applications in particular, several timer features can be combined to obtain dynamic information such as speed, acceleration, or deceleration. the current position itself can be obtained directly from the timer register (t2, t3, t4). the time information to determine the dynami c parameters is generated by capturing the contents of the free-running timer t5 into register caprel. two trigger sources for this event can be selected: www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-60 v1.1, 2011-03 gpt12, v1.5 ? capture trigger on sensor signal transitions ? capture trigger on position read operations capturing on sensor signal transitions is available for timer t3 inputs. this mode is selected by setting bit ct3 and selecting the intended signal(s) via bitfield ci in register t5con. caprel then indicates the time between two selected transitions (measured in t5 counts). capturing on position read operations is available for timers t2, t3, and t4. this mode is selected by clearing bit ct3 and selecting the rising edge via bitfield ci in register t5con. bitfield iscapin in register pisel then selects either a read access from t3 or a read access from any of t2 or t3 or t4. caprel then indicates the time between two read accesses. these operating modes directly support th e measurement of position and rotational speed. acceleration and deceleration can then be determined by evaluating subsequent speed measurements. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-61 v1.1, 2011-03 gpt12, v1.5 30.2.6 gpt2 clock signal control all actions within the timer block gpt2 are triggered by transitions of its basic clock. this basic clock is derived from the system clo ck by a basic block prescaler, controlled by bitfield bps2 in register t6con (see figure 30-18 ). the count clock can be generated in two different ways: ? internal count clock , derived from gpt2?s basic clock via a programmable prescaler, is used for (gated) timer mode. ? external count clock , derived from the timer?s input pin(s), is used for counter mode. for both ways, the basic clock determines the maximum count frequency and the timer?s resolution: internal count clock generation in timer mode and gated timer mode, the count clock for each gpt2 timer is derived from the gpt2 basic clock by a programmable prescaler, controlled by bitfield txi in the respective timer?s control register txcon. the count frequency f tx for a timer tx and its resolution r tx are scaled linearly with lower clock frequencies, as can be seen from the following formula: (30.2) the effective count frequency depends on the common module clock prescaler factor f(bps2) as well as on the indivi dual input prescaler factor 2 TC1798 the general purpose timer 12 (gpt12) users manual 30-62 v1.1, 2011-03 gpt12, v1.5 table 30-17 lists a timer?s parameters (such as count frequency, resolution, and period) resulting from the selected overall presca ler factor and the app lied system frequency. note that some numbers may be rounded. table 30-16 gpt2 overall prescaler factors for internal count clock individual prescaler for tx common prescaler for module clock 1) 1) please note the non-linear encoding of bitfield bps2. bps2 = 01 b bps2 = 00 b bps2 = 11 b bps2 = 10 b txi = 000 b 24816 txi = 001 b 481632 txi = 010 b 8 163264 txi = 011 b 16 32 64 128 txi = 100 b 32 64 128 256 txi = 101 b 64 128 256 512 txi = 110 b 128 256 512 1024 txi = 111 b 256 512 1024 2048 table 30-17 gpt2 timer parameters fpi_bus clock = 10 mhz overall divider factor fpi_bus clock = 40 mhz frequency resolution period frequency resolution period 5.0 mhz 200 ns 13.11 ms 2 20.0 mhz 50 ns 3.28 ms 2.5 mhz 400 ns 26.21 ms 4 10.0 mhz 100 ns 6.55 ms 1.25 mhz 800 ns 52.43 ms 8 5.0 mhz 200 ns 13.11 ms 625.0 khz 1.6 s 104.9 ms 16 2.5 mhz 400 ns 26.21 ms 312.5 khz 3.2 s 209.7 ms 32 1.25 mhz 800 ns 52.43 ms 156.25 khz 6.4 s 419.4 ms 64 625.0 khz 1.6 s104.9 ms 78.125 khz 12.8 s 838.9 ms 128 312.5 khz 3.2 s209.7 ms 39.06 khz 25.6 s 1.678 s 256 156.25 khz 6.4 s419.4 ms 19.53 khz 51.2 s 3.355 s 512 78.125 khz 12.8 s838.9 ms 9.77 khz 102.4 s 6.711 s 1024 39.06 khz 25.6 s1.678 s 4.88 khz 204.8 s 13.42 s 2048 19.53 khz 51.2 s3.355 s www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-63 v1.1, 2011-03 gpt12, v1.5 external count clock input the external input signals of the gpt2 block are sampled with the gpt2 basic clock (see figure 30-18 ). to ensure that a signal is recognized correctly, its current level (high or low) must be held active for at least one complete sampling period, before changing. a signal transition is recognized if two subsequent samples of the input signal represent different levels. therefore, a minimum of two basic clock periods are required for the sampling of an external input signal. thus, the maximum frequency of an input signal must not be higher than half the basic clock. table 30-18 summarizes the resulting requirements for external gpt2 input signals. these limitations are valid for all external input signals to gpt2, including the external count signals in counter mode and the gate input signals in gated timer mode. table 30-18 gpt2 external input signal limits fpi_bus clock = 10 mhz input frequ. factor gpt2 divider bps2 input phase duration fpi_bus clock = 40 mhz max. input frequency min. level hold time max. input frequency min. level hold time 2.5 mhz 200 ns f gpt /4 01 b 2 t gpt 10.0 mhz 50 ns 1.25 mhz 400 ns f gpt /8 00 b 4 t gpt 5.0 mhz 100 ns 625.0 khz 800 ns f gpt /16 11 b 8 t gpt 2.5 mhz 200 ns 312.5 khz 1.6 s f gpt /32 10 b 16 t gpt 1.25 mhz 400 ns www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-64 v1.1, 2011-03 gpt12, v1.5 30.2.7 gpt2 timer registers t5 timer 5 register (40 h ) reset value: 0000 0000 h t6 timer 6 register (44 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 tx rwh field bits type description tx [15:0] rwh timer x contains the current value of timer x. 0 [31:16] r reserved read as 0; should be written with 0. caprel capture and reload register (30 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 caprel rwh field bits type description caprel [15:0] rwh current reload value or captured value www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-65 v1.1, 2011-03 gpt12, v1.5 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-66 v1.1, 2011-03 gpt12, v1.5 30.2.8 interrupt control fo r gpt2 timers and caprel when a timer overflows from ffff h to 0000 h (when counting up), or when it underflows from 0000 h to ffff h (when counting down), its service request flag (srr) in register srcx will be set. whenever a transition ac cording to the selection in bit field ci is detected at pin capin, interrupt request flag srr in register src5 is set. interrupts of timer 5 are connected with register src3. interrupts of timer 6 are connected with register src4. interrupts of the caprel function ar e connected with register src5. src3 service request control 3 register (f0 h ) reset value: 0000 0000 h src4 service request control 4register (ec h ) reset value: 0000 0000 h src5 service request control 5 register (e8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number 00 h service request is never serviced 01 h service request is on lowest priority ... ff h service request is on highest priority tos 10 rw type of service control 0 b cpu service is initiated 1 b pcp service is initiated sre 12 rw service request enable 0 b service request is disabled 1 b service request is enabled www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-67 v1.1, 2011-03 gpt12, v1.5 srr 13 rh service request flag 0 b no service request is pending 1 b a service request is pending clrr 14 w request clear bit clrr is required to clear srr. 0 b no action 1 b clear srr; bit value is not stored; read always returns 0; no action if setr is set also. setr 15 w request set bit setr is required to set srr. 0 b no action 1 b set srr; bit value is not stored; read always returns 0; no action if clrr is set also. 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-68 v1.1, 2011-03 gpt12, v1.5 30.3 miscellaneous registers pisel port input select register (04 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 iscapin ist6 eud ist6 in ist5 eud ist5 in ist4eud ist4in ist3eud ist3in ist2 eud ist2 in rw rw rw rw rw rw rw rw rw rw rw field bits type description ist2in 0rw input select for t2in 0 b signal t2ina is selected 1 b signal t2inb is selected ist2eud 1rw input select for t2eud 0 b signal t2euda is selected 1 b signal t2eudb is selected ist3in [3:2] rw input select for t3in 00 b signal t3ina is selected 01 b signal t3inb is selected 10 b signal t3inc is selected 11 b signal t3ind is selected ist3eud [5:4] rw input select for t3eud 00 b signal t3euda is selected 01 b signal t3eudb is selected 10 b signal t3eudc is selected 11 b signal t3eudd is selected ist4in [7:6] rw input select for t4in 00 b signal t4ina is selected 01 b signal t4inb is selected 10 b signal t4inc is selected 11 b signal t4ind is selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-69 v1.1, 2011-03 gpt12, v1.5 ist4eud [9:8] rw input select for t4eud 00 b signal t4euda is selected 01 b signal t4eudb is selected 10 b signal t4eudc is selected 11 b signal t4eudd is selected ist5in 10 rw input select for t5in 0 b signal t5ina is selected 1 b signal t5inb is selected ist5eud 11 rw input select for t5eud 0 b signal t5euda is selected 1 b signal t5eudb is selected ist6in 12 rw input select for t6in 0 b signal t6ina is selected 1 b signal t6inb is selected ist6eud 13 rw input select for t6eud 0 b signal t6euda is selected 1 b signal t6eudb is selected iscapin [15:14] rw input select for capin 00 b signal capina is selected 01 b signal capinb is selected 10 b signal capinc (read trigger from t3) is selected 11 b signal capind (read trigger from t2 or t3 or t4) is selected 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-70 v1.1, 2011-03 gpt12, v1.5 clc clock control register (00 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we e dis sp en dis s dis r r rwwrwrwrhrw field bits type description disr 0rw module disable request bit used for enable/disable control of the module. 0 b module disable is not requested 1 b module disable is requested diss 1rh module disable status bit bit indicates the current status of the module 0 b module is enabled 1 b module is disabled if the rmc field is implemented and if it is 0, diss is set automatically. spen 2rw module suspend enable used for enabling the suspend mode. 0 b module cannot be suspended (suspend is disabled) 1 b module can be suspended (suspend is enabled) this bit can be written only if sbwe is set during the same write operation. edis 3rw sleep mode en able control used for module sleep mode control. 0 b sleep mode request is regarded. module is enabled to go into sleep mode. 1 b sleep mode request is disregarded: sleep mode cannot be entered on a request. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-71 v1.1, 2011-03 gpt12, v1.5 sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. 0 b bits spen and fsoe are write-protected 1 b bits spen and fsoe are overwritten by respective value of spen or fsoe reading this bit returns always 0. fsoe 5rw fast switch off enable used for fast clock switch-off in suspend mode. 0 b clock switch-off in suspend mode via disable control feature (secure clock switch off) selected 1 b fast clock switch off in suspend mode selected this bit can be written only if sbwe is set during the same write operation. 0 [31:6] r reserved read as 0; should be written with 0. id identification register (08 h ) reset value: 0068 c0xx h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 modnumber r 1514131211109876543210 modtype modrev rr field bits type description modrev [7:0] r module revision number this bit field indicates the revision number of the TC1798 module (01 h = first revision). modtype [15:8] r module type this bit field is c0 h . it defines a 32-bit module field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-72 v1.1, 2011-03 gpt12, v1.5 30.4 gpt12 kernel register overview modnumb er [31:16] r module number this bit field defines the module identification number. table 30-19 register overview of gpt12 short name long name offset addr. 1) access mode reset description see read write clc clock control register 00 h u, sv sv, e application reset page 30-70 pisel port input select register 04 h u, sv u, sv application reset page 30-68 id identification register 08 h u, sv be application reset page 30-71 ?reserved0c h be be ? ? t2con timer 2 control register 10 h u, sv u, sv application reset page 30-15 t3con timer 3 control register 14 h u, sv u, sv application reset page 30-4 t4con timer 4 control register 18 h u, sv u, sv application reset page 30-17 t5con timer 5 control register 1c u, sv u, sv application reset page 30-46 t6con timer 6 control register 20 h u, sv u, sv application reset page 30-39 ?reserved24 h - 2c h be be ? ? caprel capture and reload register 30 h u, sv u, sv application reset page 30-64 t2 timer 2 register 34 h u, sv u, sv application reset page 30-34 t3 timer 3 register 38 h u, sv u, sv application reset page 30-34 field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-73 v1.1, 2011-03 gpt12, v1.5 t4 timer 4 register 3c h u, sv u, sv application reset page 30-34 t5 timer 5 register 40 h u, sv u, sv application reset page 30-64 t6 timer 6 register 44 h u, sv u, sv application reset page 30-64 ?reserved48 h - e4 h be be ? ? src5 service request control register 5 e8 h u, sv sv application reset page 30-66 src4 service request control register 4 ec h u, sv sv application reset page 30-66 src3 service request control register 3 f0 h u, sv sv application reset page 30-66 src2 service request control register 2 f4 h u, sv sv application reset page 30-35 src1 service request control register 1 f8 h u, sv sv application reset page 30-35 src0 service request control register 0 fc h u, sv sv application reset page 30-35 1) the absolute register addres s is calculated as follows: module base address + offset address (shown in this column) table 30-19 register overview of gpt12 short name long name offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-74 v1.1, 2011-03 gpt12, v1.5 30.5 implementation of the gpt12 modules this chapter describes the implementation of the gpt12 modules in the TC1798 device. 30.5.1 address map there are two gpt12 kernels in the TC1798, namely gpt120 and gpt121. 30.5.2 module connections the following tables show the digital connections of the gpt12 modules with other modules or pins in the TC1798 device. the gpt module is clocked wi th the fpi_bus clock, so f gpt = f fpi . table 30-20 registers address space module base address end address note gpt120 f000 3400 h f000 34ff h gpt121 f000 3500 h f000 35ff h table 30-21 gpt120 digital connections in TC1798 signal from/to module i/o to gpt12 can be used to/as t2ina p4.10 i count input signals for timer t2 t2inb p3.14 i t2euda p4.12 i direction input signals for timer t2 t2eudb p5.4 i t3ina p2.14 i count input signals for timer t3 t3inb p3.8 i t3inc p14.14 i t3ind 0 i t3euda p4.8 i direction input signals for timer t3 t3eudb p3.10 i t3eudc p14.15 i t3eudd 0 i t3out p1.7 p14.8 o count output signal for timer t3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-75 v1.1, 2011-03 gpt12, v1.5 t4ina p4.9 i count input signals for timer t4 t4inb p3.12 i t4inc p15.0 i t4ind 0 i t4euda p4.14 i direction input signals for timer t4 t4eudb p5.5 i t4eudc p15.1 i t4eudd 0 i t5ina p3.0 i count input signals for timer t5 t5inb p0.11 i t5euda p0.12 i direction input signals for timer t5 t5eudb p0.13 i t6ina p0.14 i count input signals for timer t6 t6inb p4.7 i t6euda p5.0 i direction input signals for timer t6 t6eudb p3.6 i t6out p8.6 p14.10 o count output signal for timer t6 t6ofl p6.7 ccu60_t12hrf ccu60_t13hrf ccu61_t12hrf ccu61_t13hrf ccu63_cc62ind o over/under-flow signal from timer t6 capina p8.2 i input capture signals capinb p6.8 i table 30-21 gpt120 digital connections in TC1798 (cont?d) signal from/to module i/o to gpt12 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-76 v1.1, 2011-03 gpt12, v1.5 table 30-22 gpt121 digital connections in TC1798 signal from/to module i/o to gpt12 can be used to/as t2ina p3.14 i count input signals for timer t2 t2inb p4.10 i t2euda p5.4 i direction input signals for timer t2 t2eudb p4.12 i t3ina p3.8 i count input signals for timer t3 t3inb p2.14 i t3inc 0 i t3ind p14.14 i t3euda p3.10 i direction input signals for timer t3 t3eudb p4.8 i t3eudc 0 i t3eudd p14.15 i t3out p8.4 p14.9 o count output signal for timer t3 t4ina p3.12 i count input signals for timer t4 t4inb p4.9 i t4inc 0 i t4ind p15.0 i t4euda p5.5 i direction input signals for timer t4 t4eudb p4.14 i t4eudc 0 i t4eudd p15.1 i t5ina p0.11 i count input signals for timer t5 t5inb p3.0 i t5euda p0.13 i direction input signals for timer t5 t5eudb p0.12 i t6ina p4.7 i count input signals for timer t6 t6inb p0.14 i www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-77 v1.1, 2011-03 gpt12, v1.5 t6euda p3.6 i direction input signals for timer t6 t6eudb p5.0 i t6out p8.7 p14.11 o count output signal for timer t6 t6ofl p6.9 ccu62_t12hrf ccu62_t13hrf ccu63_t12hrf ccu63_t13hrf ccu61_cc62ind o over/under-flow signal from timer t6 capina p6.8 i input capture signals capinb p8.2 i table 30-22 gpt121 digital connections in TC1798 (cont?d) signal from/to module i/o to gpt12 can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 the general purpose timer 12 (gpt12) users manual 30-78 v1.1, 2011-03 gpt12, v1.5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-1 v1.1, 2011-03 adc, v1.5.2 31 analog to digital converter (adc) the a nalog to d igital c onverter module (adc) of the TC1798 allows the conversion of analog input values into discrete digital values based on the successive approximation method. with this method, the conversion result is elaborated bit by bit, starting with the most significant bit. as a consequence, an analog to digital conversion requires a certain number of clock cycles. this chapter is structured as follows: ? introduction (see section 31.1 ) ? operating the adc (see section 31.2 ) ? module implementation in TC1798 (see section 31.3 ) 31.1 introduction this section gives an overview about the feature set of the adc module and introduces the general structure. it describes the: ? adc block diagram (see section 31.1.1 ) ? feature set description (see section 31.1.2 ) ? abbreviations (see section 31.1.3 ) ? kernel overview (see section 31.1.4 ) ? conversion request handling (see section 31.1.5 ) ? conversion result handling (see section 31.1.6 ) ? interrupt structure (see section 31.1.7 ) ? electrical models (see section 31.1.8 ) ? transfer characteristics and error definitions (see section 31.1.9 ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-2 v1.1, 2011-03 adc, v1.5.2 31.1.1 adc block diagram the adc module contains four independent kernels (adc0, adc1, adc2, adc3) that can operate autonomously or can be synchronized to each other. an adc kernel is a unit used to convert an analog input signal into a digital value and provides means for triggering conversions, data handling and storage. with this structure, parallel conversion of up to four analog input channels is supported. figure 31-1 adc module block diagram adc kernel 2 ad converter conversion control adc kernel 1 ... analog inputs data (result) handling request control bus inter- face ad converter conversion control ... data (result) handling request control analog inputs ad converter conversion control adc kernel 0 ... analog inputs data (result) handling request control adc kernel 3 adc_ 4_kernels ad converter conversion control ... data (result) handling request control analog inputs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-3 v1.1, 2011-03 adc, v1.5.2 31.1.2 feature set features of each adc kernel: ? analog supply voltage range from 3.3 v (minimum) to 5 v (nominal) for v ddm ? input voltage range from 0 v to analog supply voltage v ddm ? input multiplexer for a maximum of 16 possible analog input channels ? one standard reference input (v aref ) and one alternative reference input (ch0) available ? broken wire detection support for each input channel ? multiplexer test support for input channels with odd channel numbers ? 5 conversion request sources for exte rnal or timer-driven events, auto-scan, programmable sequences, sw-driven conversions, etc. ? synchronization of the adc kernels for concurrent conversion starts and parallel sampling and measuring of analog input signals, e.g. for phase current measurements in ac drives ? control capability for an external analog multiplexer, respecting the additional set up time ? adjustable sampling times to accommodate output impedance of different analog signal sources (sensors, etc.) ? possibility to cancel running conversions on demand with automatic restart ? flexible interrupt generation (possibility of dma support) ? limit checking to reduce interrupt l oad (e.g. for temperature measurements or overload detection, only values exceeding a programmable level lead to an interrupt) ? programmable data reduction filter, e.g. for digital anti-aliasing filtering, by adding a programmable number of conversion results ? independent result registers (16 independent registers) ? programmable result data filter providing 3rd order fir or 1st order iir filter structure ? support of conversion result fifo mechanism to allow a longer interrupt latency ? support of suspend and power saving modes ? individually programmable reference selection for each channel, e.g. to allow measurements of 3.3 v and 5 v signals in the full measurement range with the same adc kernel (with exception of dedicated channels always referring to v aref ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-4 v1.1, 2011-03 adc, v1.5.2 31.1.3 abbreviations the following acronyms and terms are used in the adc chapter: table 31-1 abbreviations in adc chapter abbreviation meaning adc analog to digital converter dma direct memory access mechanism dnl differential non-linearity error fifo first-in-first-out data buffer mechanism fir finite impulse resonse (digital filter) inl integral non-linearity error iir infinite impulse resonse (digital filter) lsb n finest granularity of the analog valu e in digital format, represented by one least significant bit of the conversion result with n bits resolution (measurement range divided in 2 n equally distributed steps) scu system control unit of the device tue total unadjusted error www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-5 v1.1, 2011-03 adc, v1.5.2 31.1.4 adc kernel overview each adc kernel comprises: ?an analog to digital converter with a maximum of 16 analog inputs (ch0 - ch15). this block selects an input signal and translates the analog voltage into a digital value. not all analog input channels are necessarily available in all packages, please refer to the implementation description in section 31.3 . ?a conversion control unit defining the conversion parameters like the length of the sample phase, the resolution and the reference for each conversion. the length of the sample phase and the resolution depend on the type of sensor (or other analog sources) connected to the adc. these values are similar for several channels and, therefore, are grouped together to form the so-called input classes. each channel can be individually assigned to an input class to define these parameters. the conversion control also handles the start conditions for the conversions, such as the immediate start (cancel-inject-repeat), overwrite of former results (wait-for-read), or synchronization of the adc kernels (parallel conversions). additionally, an external analog multiplexer can be controlled by the output signals emux[2:0] of dedicated adc kernels. ?a request control unit defining which analog input channel has to be converted next. it contains 5 request sources that can trigger conversions depending on different events, such as edges of pwm or timer si gnals or events at port pins. each request source can trigger either 1, up to 4, or up to 16 conversions in a sequence. ?a result handling unit providing 16 result registers for the conversion results. the conversion result of each analog input channel can be directed to one of the result registers to be stored there. the result handling block also supports data reduction (e.g. for digital anti-aliasing filtering) by automatically adding up to 4 conversion results before informing the cpu that new data is available. additionally, the results registers can be co ncatenated to fifo structures to provide storage capability for more than one conversion result without overwriting previous data. this feature also helps to handle cpu latency effects. ?an interrupt generation unit issuing interrupt requests to the cpu depending on adc events. the interrupt generation in the adc kernels support different mechanisms, e.g. some interrupts can be c oupled to a value range of the conversion result (limit checking), some interrupts can be used to transport conversion data to locations in memory for further treatment, and other interrupts are generated after a complete sequence of conversions. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-6 v1.1, 2011-03 adc, v1.5.2 figure 31-2 adc kernel block diagram adc_kernel _overv ad converter conversion control result handling request control interrupt generation adc kernel ... analog input channel ch0 analog input channel ch15 standard analog reference v aref analog reference ground v agnd external multi- plexer control emux[2:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-7 v1.1, 2011-03 adc, v1.5.2 31.1.5 conversion request unit the conversion request unit of each adc kernel autonomously handles the generation of conversion requests. it contains 5 independent request sources that are connected to several modules to trigger the start of a conversion. a request source defines the analog input channel to be converted if a defined event occurs. for example, a trigger pulse from a timer unit generating a pwm signal can start the conversion of a single input channel or a programmed sequence of input channels. depending on the application, the request sour ces can be triggered by different events, either issued by other modules or under sw control. as a consequence, there can be two or more conversion requests pending at the same time. to allow the user to adapt the request source mechanism to the application needs, the trigger capability, the channel number(s) to be converted, and the pr iority can be individually programmed for each request source. an arbiter block regularly scans the request sources for pending conversion requests and acts upon the conversion request with the highest priority. this conversion request is forwarded to the converter to start the conversion of the requested channel. figure 31-3 conversion request unit adc_request_handling_5 request control request source 3 (16-ch scan) request source 4 (4-stage queue) request source arbiter timer unit(s) external request(s) analog part request source 2 (4-stage queue) adc kernel request source 1 (16-ch scan) request source 0 (1-stage queue) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-8 v1.1, 2011-03 adc, v1.5.2 the functional characteristics of the request sources are adapted to the most common application requirements. in all request sour ces, a continuous operation or a single-shot operation can be selected. for continuous operation, the programmed sequence of conversions requests are continuously is sued (once started), whereas in single-shot mode, each sequence of conversion requests has to be explicitly started. the trigger for a conversion request or a sequence can be handled under sw control or can be synchronized to adc-external events, such as timer signals or port pins. for each request source, the user can select an input signal (from 8 possible signals reqtrx_[7:0]) as trigger input reqtrx a nd an input signal (from 8 possible signals reqgtx_[7:0]) as gating input reqgtx. ? request source 0 (1-stage sequential source) can issue a conversion request for a single input channel. the channel number can directly be programmed. this mechanism could be used for sw -controlled conversion requests or hw- triggered conversions of a single input c hannel. if programmed with a high priority, it can interrupt the sequences of the other request sources to inject a single conversion. ? request sources 1 and 3 (16-channel scan sources) can issue conversion requests for a sequence of up to 16 input channels. it can be programmed which channel takes part in this sequence. the sequence always starts with the highest enabled channel number and continues towards lower channel numbers (order defined by the channel number, each channel can be converted only once per sequence). this mechanism could be used to scan input channels permanently or on a regular time base. for example, if programmed with a low priority, some input channels can be scanned in a background task to update information that is not time-critical. ? request sources 2 and 4 (4-stage sequential sources) can issue a conversion request for a sequence of up to 4 input channels. the channel numbers can be freely programmed, especially multiple conversions of the same channel within the sequence are supported. this mechanism could be used to support application-specific conversion sequences that can not be covered by the scanning mechanism of request sources 1 or 3. especially for timing-critical sequences containing multiple conversions of the same channel, one of these request sources shoul d be used. for example, if programmed with a medium priority, some input chan nels can be converted when a specified event occurs (e.g. synchronized to a pwm) while the scan of other input channels of the background task (handled by request source 1) is interrupted. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-9 v1.1, 2011-03 adc, v1.5.2 31.1.6 conversion result unit the conversion result unit co mprises for each adc kernel: ? a set of 16 result registers for storing the conversion results. a pointer mechanism for each analog input channel distributes the conversion results to the result registers. especially for auto-scan applicatio ns, this feature simplifies dma use (only one dma channel needed to transfer a complete auto-scan sequence into the device memory). ? the result registers provide valid flags to indicate if new data has been stored since it has been read out (new data indication). ?a result fifo mechanism for conversion results handling with a ?relaxed? cpu timing. result registers not directly used as target for a conversion result can be concatenated to form a result fifo. this structure allows to store a sequence of conversion results before the cpu has to interact. ?a digital anti-aliasing or data reduction filter , accumulating a programmable number of conversion results before generating a result event interrupt. this feature can be used to avoid cpu inte rvention on each conversion result if a certain number of conversion results are added before further treatment, especially for fast conversions sequences and averaging of results. ?a wait-for-rea d mechanism can be enabled independently for each result register to delay conversions targeting a result register that has not yet been read out. ?a flexible interr upt generation based on result register events. a result register event occurs if a new valid data word becomes available in a result register and can be read out. especially when using data reduction or digital anti-aliasing filtering, the result register event indicates that the final result is available. ? debugger support for adc result registers supporting read out of adc conversion results without changing the result status (new data indication). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-10 v1.1, 2011-03 adc, v1.5.2 31.1.7 interrupt structure each adc kernel provides 8 independent service request output signals (adcx_sr[7:0]) used for interrupt handling. the interrupt generation inside the adc kernel is based on three different types of events. ? channel events: a channel event is detected if a conversion is finished and the conversion result is within a programmable value range. this type of event can be used to check if analog input values are inside or out of a nominal operating range, es pecially to reduce cpu load for background tasks. this allows the user to interrupt the cpu only if the specified conversion result range is met (or not met) instead of comparing each result by sw. ? result events: a result event is detected if a new result is available in a result register and can be read out, e.g. to store the data in memory for further treatment by sw. this type of event can be used to trigger a read action by the cpu (or dma). especially when using data reduction or digi tal anti-aliasing filtering, not all finished conversion leads to a new result. furthermore, when using a result fifo, a result event decouples the cpu (dma) read out from the channel events and tolerates a higher interrupt latency. the result register structure allows to use a single dma channel for a complete auto-scan sequence by triggering the read out by a result event (if the conversion results of all channels taking part in the auto-scan sequence target the same resu lt register, e.g. with fifo mechanism or with a wait-for-read condition to avoid data loss). ? request source events: a request source event is detected if a scan source has completely finished the requested conversion sequence. for a seque ntial source, the user can define where inside a conversion sequence a re quest source event is generated. this type of event can be used to inform the cpu that a conversion sequence has reached a defined state and sw can start the treatment of the related results in a block. each adc event is indicated by a dedicated fl ag that can be cleared by sw. an interrupt can be generated (if enabled) for each event, independently from the status of the corresponding event indication flag. this structure ensures efficient dma handling of adc events (the adc event can generate an interrupt without the need to clear the indication flag). a node pointer mechanism allo ws the user to group interrupts events by selecting which service request output signals srx becomes activated by which event. each adc event can be individually directed to one of the service request output signals to adapt easily to application needs. note: a conversion can lead to three interrupts, one of each type. in this case, the adc module first triggers the request source event interrupt, then the channel event interrupt, followed by the result event interrupt (all within a few f adc clock cycles). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-11 v1.1, 2011-03 adc, v1.5.2 31.1.8 electrical models each conversion of an analog input voltage into a digital value consists of two consecutive phases. during the sample phase, the input voltage is sampled and prepared for the following conversion phase. a simplified model for the sample phase describes the input signal path, whereas a second simplified model for the conversion phase is related to the reference voltage handling. 31.1.8.1 input signal path the adc kernel in the TC1798 is based on one switched capacitor field for measurement with a total capacity represented by c ain and a small static capacitor at each input pin. during the sample phase, the capacitor field c ain is connected to one of the analog input chx via an input multiplexer. the multiplexer is modeled by ideal switches and series resistors r ain . only the switch to the selected analog input is closed during the sample phase. during the conversion phase or while no conversion is running (adc is idle), all switches are open. the voltage at the analog input channel chx is represented by v ainx . figure 31-4 signal path model a simplified model for the analog input signal path is given in figure 31-4 . an analog voltage source (value v s ) with an internal impedance of r ext delivers the analog input that should be converted. during the sample phase the corresponding switch is closed and the capacitor field c ain is charged. due to the low-pass behavior of the resulting rc combination, the voltage v c to be actually converted does not immediately follow v s . the value r ext of the analog voltage source and the desired precision of the conversion strongly define the required length of the sample phase. to reduce the influence of r ext and to filter input noise, it is recommended to introduce adc_signal_path_model adc kernel ... ... c ain r ain v agnd chx ch0 ch15 c ext v ainx r ext v s v c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-12 v1.1, 2011-03 adc, v1.5.2 a fast external blocking capacitor c ext at the analog input pin of the adc. like this, mainly c ext delivers the charge during the sample phase. this structure allows a significantly shorter sample phase than with out a blocking capacitor, because the low- pass time constant defining the sample time is mainly given by the values of r ain and c ain . additionally, the capacitor c ain is automatically precharged to a voltage of approximately the half of the standard reference voltage v aref to minimize the average difference between v ainx and v c at the beginning of a sample phase. due to varying parameters and parasitic effects, the precharge voltage of c ain is typically smaller than v aref /2. on the other hand, the charge redistribution between c ext and c ain leads to a voltage change of v ainx during the sample phase. in order to keep this voltage change lower than 1lsb n , it is recommended to use an external blocking capacitor c ext in the range of at least 2 n c ain . the resulting low-pass filter of r ext and c ext should be dimensioned in a way to allow v ainx to follow v s between two sample phases of the same analog input channel. please note that, especially at high temperatures, the analog input structure of an adc can lead to a leakage current and introduces an error due to a voltage drop over r ext . the adc input leakage current increases if the input voltage level is close to the analog supply ground v ssm or to the analog power supply v ddm . it is recommended to use an operating range for the input voltage between approximately 3% and 97% of v ddm to reduce input leakage values. furthermore, the leakage is influenced by an overload condition at adjacent analog inputs. during an overload condition, an input voltage exceeding the supply range is applied at an input and the built-in protection circuit limits the resulting input voltage. this leads to an overload current through the protection circuit that is translated (by a coupling factor) into an additional leakage at adjacent inputs. 31.1.8.2 reference path during the conversion phase, parts of the capacitor field c ain are switched to a reference input or to v agnd . the adc kernel supports two possible reference inputs, v aref as standard reference and ch0 as alternative reference. the reference selection between both possibilities is handled individually for each analog input channel. for example, this structure allows conversions of 5 v and 3.3 v based analog input signals with the same adc kernel. a high accuracy of the conversion results requires a stable and noise-free reference voltage and analog supply voltages during the conversion phase. instable voltages or noise on the supply or reference inputs lead to a reduced conversion accuracy. please note that noise can also be introduced into the adc module by other modules, e.g. by switching of neighboring pins. it is strongly recommended to carefully decouple analog from digital signal domains. due to the switching of parts of c ain , the adc requires a dynamic current at the selected reference input. thus, the impedance r aref of the reference voltage source v r has to www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-13 v1.1, 2011-03 adc, v1.5.2 be low enough to supply the reference current during the conversion phase. an external blocking capacitor c aref should be used to supply the peak currents and to minimize the current delivered by the reference source. due to the charge redistribution between c aref and parts of c ain , the voltage v aref decreases during the conversion phase. in or der to limit the error introduced by this effect to 1/2 lsb n , the external blocking capacitor c aref for the reference input should be at least 2 n c ain . the reference current i aref introduces a voltage drop at r aref that should not be neglected for the calculation of the over all accuracy. the average reference current during a conversion depends on the reference voltage level and the time t conv between two conversion starts. i aref =c ain v aref /t conv figure 31-5 refere nce path model adc_ref_path_model adc kernel c ain r ain v agnd ch0 c aref v aref r aref v r v c v aref i aref www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-14 v1.1, 2011-03 adc, v1.5.2 31.1.9 transfer characteristics and error definitions the ideal transfer characteristic of the adc translates a continuous analog input voltage into a discrete digital value out of a result range of 2 n steps for n bit resolution over a measurement range between 0 and a reference voltage. each digital value in the available result range (from 0 to 2 n -1) represents an input voltage range that is defined by the reference voltage divided by 2 n . this range (called quantization step) represents the smallest granularity (called lsb n ) that can be handled by the adc. due to the discrete character of the digital result, ea ch adc conversion result has a system- inherent quantization uncertainty of 0.5 lsb n . according to the ideal transfer characteristics, the first digital transition (between the digital values 0 and 1) takes place when the analog input reaches 0.5 lsb n . an analog input voltage above the reference voltage leads to a saturation of the digital result at 2 n -1. deviations of the conversion result from the ideal transfer characteristics can appear: ?an offset error is the deviation from the ideal transfer characteristics for an input voltage close to 0. it describes the difference between 0.5 lsb n and the input voltage where the first digital transition (between the values of 0 and 1) occurs. ?a gain error is the deviation from the ideal transfer characteristics for an input voltage close to the reference voltage. it describes the difference between the reference voltage and the input voltage where the last digital transition (between the values of 2 n -2 and 2 n -1) occurs. ?a differential non-linearity error (dnl) describes the variations in the analog input voltage between two adjacent digital conversion results, over the full measurement range. if each step between the digital conversion results x and x+1 is exactly 1 lsb n , the dnl value is zero. if the dnl value is lower than 1 lsb n , the possibility of missing codes is excluded. a missing code occurs if not all values of the possible conversion result range can be reached. ?an integral non-linearity error (inl) describes the maximum difference between the transfer characteristics between the first and the last point of the measurement range and the real transfer characteristics (without quantization uncertainty, offset and gain errors). ?the total unadjusted error (tue) describes the maximum deviation between a real conversion result and the ideal transfer characteristics over a given measurement range. since some of these errors noted above can compensate each other, the tue value generally is much less than the sum of the individual errors. the tue also covers production process variations and internal noise effects (if switching noise is generated by the system, this generally leads to an increased tue value). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-15 v1.1, 2011-03 adc, v1.5.2 31.2 operating the adc this section describes the kernel functions and how to operate the kernel. it provides the functional descriptions and the associated register descriptions. ? register overview (see section 31.2.1 ) general module, kernel and arbiter operation: ? enabling the adc module for configuration of the behavior for the different device operating modes (see mode control description in section 31.2.2 ). ? enabling the converter for operation or selecting the desired power saving mode (see section 31.2.3 ) ? selecting the appropriate frequency for the converter and for the request source arbiter (see section 31.2.4 ). ? adc module registers (see section 31.2.5 ) ? general adc kernel registers (see section 31.2.6 ) ? configuring the request source arbiter (see section 31.2.7 ) ? arbiter registers (see section 31.2.8 ) request source operation: ? scan request source handling (see section 31.2.9 ) ? scan request source registers (see section 31.2.10 ) ? sequential request source handling (see section 31.2.11 ) ? sequential request source registers (see section 31.2.12 ) channel and result register operation: ? configuring the channel-related functions (see section 31.2.13 ) ? channel-related registers (see section 31.2.14 ) ? conversion result handling (see section 31.2.15 ) ? conversion request handling (see section 31.2.16 ) additional features: ? multiplexer test support (see section 31.2.17 ) ? external multiplexer control (see section 31.2.18 ) ? synchronization for parallel conversions (see section 31.2.19 ) ? equidistant sampling (see section 31.2.20 ) ? access protection (see section 31.2.21 ) ? broken-wire detection (see section 31.2.22 ) ? additional feature registers (see section 31.2.23 ) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-16 v1.1, 2011-03 adc, v1.5.2 31.2.1 register overview table 31-2 shows all registers required for programming the adc module. it summarizes the adc kernel registers and defines their relative addresses and the reset values. the relative addresses have to be added to the base addresses for the adc kernels (see section 31.3 ) to obtain the absolute address for each register. each adc kernel is located in an address window of 4 * 256 bytes. all registers can be accessed with 8 bit, 16 bit, or 32 bit wide accesses. the prefix ? adcx_ ? has to be added to the register names in this table for each adc kernel to distinguish registers of the different kernels. in this naming convention, x indicates the kernel number (e.g. adc0_ for the adc0 kernel and ?adc1_? for the adc1 kernel). the registers that are implemented only once in the adc module are located in the address range of adc0. all adc registers (including kscfg.nomcf g and kscfg.comcfg) are reset by an application reset (class 3), whereas bit fiel d kscfg.sumcfg is reset by a debug reset (class 1). note: register bits marked ?w? always deliver 0 when read. access rights within the address range of an adc kernel: ? read or write access to defined register addresses: u, sv ? accesses to empty addresses: reserved, be table 31-2 register overview of adc short name description offset addr. 1) access mode reset description see read write adc module registers (only available in the address range of adc0) clc clock control register 000 h u, sv sv, e class 3 page 31-25 kscfg kernel state configuration register 00c h u, sv sv, e class 3 page 31-26 srcx x=0 - 8 service request control registers 3fc h - x * 4 h u, sv u, sv class 3 page 31-28 general kernel registers (available in the address range of each kernel) id module identification register 008 h u, sv u, sv class 3 page 31-32 rsirx (x = 0 - 4) request source x input register 010 h + x * 4 u, sv u, sv class 3 page 31-29 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-17 v1.1, 2011-03 adc, v1.5.2 intr interrupt activation register 204 h u, sv u, sv class 3 page 31-33 globctr global control register 030 h u, sv u, sv class 3 page 31-34 globcfg global configuration register 034 h u, sv u, sv class 3 page 31-37 globstr global status register 038 h u, sv u, sv class 3 page 31-39 arbiter registers (available in the address range of each kernel) asenr arbitration slot enable register 03c h u, sv u, sv class 3 page 31-47 rspr0 request source priority register 0 040 h u, sv u, sv class 3 page 31-48 rspr4 request source priority register 4 044 h u, sv u, sv class 3 page 31-49 request source 0 registers (available in the address range of each kernel) qmr0 queue 0 mode register 080 h u, sv u, sv class 3 page 31-65 qsr0 queue 0 status register 084 h u, sv u, sv class 3 page 31-68 q0r0 queue 0 register 0 088 h u, sv u, sv class 3 page 31-70 qbur0 queue 0 backup register 08c h u, sv u, sv class 3 page 31-72 qinr0 queue 0 input register 08c h u, sv u, sv class 3 page 31-74 request source 1 registers (available in the address range of each kernel) crcr1 conversion request 1 control register 090 h u, sv u, sv class 3 page 31-54 table 31-2 register overview of adc (cont?d) short name description offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-18 v1.1, 2011-03 adc, v1.5.2 crpr1 conversion request 1 pending register 094 h u, sv u, sv class 3 page 31-56 crmr1 conversion request 1 mode register 098 h u, sv u, sv class 3 page 31-57 request source 2 registers (available in the address range of each kernel) qmr2 queue 2 mode register 0a0 h u, sv u, sv class 3 page 31-65 qsr2 queue 2 status register 0a4 h u, sv u, sv class 3 page 31-68 q0r2 queue 2 register 0 0a8 h u, sv u, sv class 3 page 31-70 qbur2 queue 2 backup register 0ac h u, sv u, sv class 3 page 31-72 qinr2 queue 2 input register 0ac h u, sv u, sv class 3 page 31-74 request source 3 registers (available in the address range of each kernel) crcr3 conversion request 3 control register 0b0 h u, sv u, sv class 3 page 31-54 crpr3 conversion request 3 pending register 0b4 h u, sv u, sv class 3 page 31-56 crmr3 conversion request 3 mode register 0b8 h u, sv u, sv class 3 page 31-57 request source 4 registers (available in the address range of each kernel) qmr4 queue 4 mode register 0c0 h u, sv u, sv class 3 page 31-65 qsr4 queue 4 status register 0c4 h u, sv u, sv class 3 page 31-68 q0r4 queue 4 register 0 0c8 h u, sv u, sv class 3 page 31-70 table 31-2 register overview of adc (cont?d) short name description offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-19 v1.1, 2011-03 adc, v1.5.2 qbur4 queue 4 backup register 0cc h u, sv u, sv class 3 page 31-72 qinr4 queue 4 input register 0cc h u, sv u, sv class 3 page 31-74 channel registers (available in the address range of each kernel) chctrx (x = 0 -15) channel x control register 100 h + x * 4 u, sv u, sv class 3 page 31-81 inpcrx (x = 0 -3) input class x register 050 h + x * 4 u, sv u, sv class 3 page 31-83 alr0 alias register 0 210 h u, sv u, sv class 3 page 31-84 lcbrx (x = 0 - 3) limit check boundary register x 0f0 h + x * 4 u, sv u, sv class 3 page 31-85 chfr channel flag register 060 h u, sv u, sv class 3 page 31-86 chfcr channel flag clear register 064 h u, sv u, sv class 3 page 31-87 chenpr0 channel event node pointer register 0 068 h u, sv u, sv class 3 page 31-88 chenpr8 channel event node pointer register 8 06c h u, sv u, sv class 3 page 31-89 result registers (available in the address range of each kernel) resr0 result register 0 180 h u, sv u, sv class 3 page 31-100 resrx (x = 1 - 15) result register x 180 h + x * 4 u, sv u, sv class 3 page 31-102 resrd0 result register 0 for debugging 1c0 h u, sv u, sv class 3 page 31-100 resrdx (x = 1 - 15) result register x for debugging 1c0 h + x * 4 u, sv u, sv class 3 page 31-102 table 31-2 register overview of adc (cont?d) short name description offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-20 v1.1, 2011-03 adc, v1.5.2 vfr valid flag register 200 h u, sv u, sv class 3 page 31-104 rcrx (x = 0 - 15) result control register x 140 h + x * 4 u, sv u, sv class 3 page 31-105 evfr event flag register 070 h u, sv u, sv class 3 page 31-107 evfcr event flag clear register 074 h u, sv u, sv class 3 page 31-109 evnpr source event node pointer register 078 h u, sv u, sv class 3 page 31-110 rnpr0 result node pointer register 0 208 h u, sv u, sv class 3 page 31-111 rnpr8 result node pointer register 8 20c h u, sv u, sv class 3 page 31-112 additional feature registers (available in the address range of each kernel) apr access protection register 218 h u, sv sv, e class 3 page 31-125 emctr external multiplexer control register 220 h u, sv u, sv class 3 page 31-126 synctr synchronization control register 048 h u, sv u, sv class 3 page 31-130 bwdenr broken wire detection enable register 224 h u, sv u, sv class 3 page 31-132 bwdcfg r broken wire detection configuration register 228 h u, sv u, sv class 3 page 31-133 1) the absolute register addres s is calculated as follows: module base address + offset address (shown in this column) table 31-2 register overview of adc (cont?d) short name description offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-21 v1.1, 2011-03 adc, v1.5.2 31.2.2 mode control the mode control concept fo r system control tasks, such as suspend request for debugging, allows to program the module behavior under different device operating conditions. the behavior of the adc kernels can be programmed for each of the device operating modes. it is advantageous that the adc kernels of an adc module show an identical behavior regarding the device operating modes (e.g. to avoid that a non- suspended kernel waits for a suspended kernel to start a synchronized conversion). therefore, the adc module has a common associated register adc0_kscfg defining the behavior of all kernels of the module in the following device operating modes: ? normal operation: this operating mode is the default operating mode when no suspend request is pending. the kernel behavior is defined by kscfg.nomcfg. ? suspend mode: this operating mode is requested when a suspend request (issued by a debugger) is pending in the device. the kernel behavior is defined by kscfg.sumcfg. for the adc module, the following internal actions can be influenced by mode control: ? a current conversion of an analog value: if the request control unit has found a pendi ng conversion request, the conversion can be started. this start has to be enabled by the mode control. if the current kernel mode allows the conversion start (run modes 0 and 1), it will be executed. if the kernel mode does not allow a start (stop modes 0 and 1), the conversion is not started. the start request is not cancelled, but frozen. a ?frozen? conversion is started as programmed if the kernel mode is changed to a run mode again. ? an arbiter round: the start of a new arbiter round has to be enabled by the kernel modes. in stop mode 1, a new arbiter round will not start. the behavior of the adc kernels can be programmed for each of the device operating modes (normal operation, suspend mode). th erefore, the adc kernels support four kernel modes, as shown in table 31-3 . table 31-3 adc kernel behavior kernel mode kernel behavior code run mode 0 kernel operation as specified, no impact on data transfer (same behavior for run mode 0 and run mode 1) 00 b run mode 1 01 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-22 v1.1, 2011-03 adc, v1.5.2 generally, bit field kscfg.nomcfg should be configured for run mode 0 as default setting for standard operation. if the adc kernels should not react to a suspend request (and to continue operation as in normal mode), bit field kscfg.sumcfg has to be configured with the same value as kscfg.n omcfg. if the adc kernels should show a different behavior and stop operation when a specific stop condition is reached, the code for stop mode 0 or stop mode 1 has to be written to kscfg.sumcfg. note: the stop mode selection strongly depends on the application needs and it is very unlikely that different stop modes are required in parallel in the same application. as a result, only one stop mode type (either 0 or 1) should be used in the bit fields in register kscfg. do not mix stop mode 0 and stop mode 1 and avoid transitions from stop mode 0 to stop mode 1 (or vice versa) for the adc module. stop mode 0 a currently running ad c onversion is completely finished and the result is treated. pending conversion request to start a new conversion are not taken into account (but not deleted). they start conversions after entering a run mode as programmed. the arbiter continues as programmed. 10 b stop mode 1 like stop mode 0, but the arbiter is stopped after it has finished its arbitration round. 11 b table 31-3 adc kernel behavior (cont?d) kernel mode kernel behavior code www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-23 v1.1, 2011-03 adc, v1.5.2 31.2.3 module activation and power saving modes the converter of the adc supports specific power down modes allowing an automatic reduction of the power consumption betwe en two conversions. the following modes are determined by bit field globstr .anon: ?anon=00 b : converter switched off (default after reset) the complete converter is switched off and held in its reset state, conversions are not possible. to start a conversion, anon has to be programmed to the desired mode. a maximum wake-up time of about 10 s has to be respected before starting a conversion. furthermore, digital logic blocks are set to their initial state. ?anon=01 b and 10 b : reserved these modes are reserved and must not be selected. ?anon=11 b : normal operation conversions are always possible with the de sired sample time. the converter stays active permanently. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-24 v1.1, 2011-03 adc, v1.5.2 31.2.4 clocking scheme the different parts of an adc kernel are dr iven by clock signals that are based on the clock f adc of the bus that is used to access the adc module. ? the analog clock f adci is used as internal clock for the converter and defines the conversion length and the sample time. it can be adjusted by programming bit field globctr .diva. ? the digital clock f adcd is used for the arbiter and defines the duration of an arbiter round. it can be adjusted by programming bit field globctr .divd. ? all other digital structures (such as interrupts, etc.) are directly driven by the module clock f adc . figure 31-6 clocking scheme note: if the clock generation for the converter of the adc falls below a minimum value or is stopped during a running conversion, the conversion result can be corrupted. for correct adc result s, the frequency of f adci must not exceed the range indicated in the electrical characteristics chapter. adc_clocking converter analog clock f adci digital clock f adcd module clock f adc arbiter divider for f adcd interrupts, etc. clock generation unit (in scu) divider for f adci adc kernel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-25 v1.1, 2011-03 adc, v1.5.2 31.2.5 adc module registers 31.2.5.1 clock control register the clock control register allows the programmer to control (enable/disable) the clock signals to the adc module. note: after a hardware reset operation, the f clc and f adc clocks are switched off and the adc module is disabled (diss set). adc0_clc adc clock control register (000 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we e dis sp en dis s dis r r rwwrwrw r rw field bits type description disr 0rw module disable request bit used for enable/disable control of the module. diss 1r module disable status bit bit indicates the current status of the module. spen 2rw module suspend enable for ocds used to enable the suspend mode edis 3rw sleep mode en able control used to control module?s sleep mode. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. fsoe 5rw fast switch off enable used to switch off fast clock in suspend mode. 0 [31:6] r reserved; returns 0 if read; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-26 v1.1, 2011-03 adc, v1.5.2 31.2.5.2 kernel state configuration register the kernel state configuration register kscfg allows the selection of the desired kernel modes. the adc kernels are controlled by the same register adc0_kscfg. all bits in kscfg, e xcept kscfg.sumcfg are reset by an application (class3) reset. bit field kscfg.sumcfg is reset by the debug reset. if a module should be switched off, sw can program a stop mode in bit field nomcfg and check for ack = 1 afterwards. note: the coding of the bit fields no mcfg, sumcfg and comcfg is described in table 31-3 . adc0_kscfg kernel state configuration register (00c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 bp sum 0 sumcfg bp nom 0nomcfg sus req ack 0 r wrrwwrrwrhrhr field bits type description ack 2rh module acknowledge this bit monitors the state of the adc module?s acknowledge on incoming requests. 0 b the acknowledge is not activated, because at least one of the module kernels is in a transition phase. 1 b the acknowledge is activated, because all module kernels have reached the requested state. susreq 3rh suspend request this bit monitors the state of the adc module?s suspend request input. 0 b a suspend mode is not requested and bit field nomcfg defines the adc kernel mode. 1 b a suspend mode is requested and bit field sumcfg defines the adc kernel mode. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-27 v1.1, 2011-03 adc, v1.5.2 nomcfg [5:4] rw normal operation mode configuration this bit field defines the kernel mode applied in normal operation mode. 00 b run mode 0 is selected. 01 b run mode 1 is selected. 10 b stop mode 0 is selected. 11 b stop mode 1 is selected. bpnom 7w bit protection for nomcfg this bit enables the write access to the bit field nomcfg. it always reads 0. 0 b the bit field nomcfg is not changed. 1 b the bit field nomcfg is updated with the written value. sumcfg [9:8] rw suspend mode configuration this bit field defines the kernel mode applied in suspend mode. coding like nomcfg. bpsum 11 w bit protection for sumcfg this bit enables the write access to the bit field sumcfg. it always reads 0. 0 b the bit field sumcfg is not changed. 1 b the bit field sumcfg is updated with the written value. 0 [1:0], 6, 10, [31:12] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-28 v1.1, 2011-03 adc, v1.5.2 31.2.5.3 service request control registers the service request control registers of the adc module are located in the address range of adc0. note: additional details on service reques t nodes and the service request control registers are described in the TC1798 system units part (volume 1). adc0_srcx (x = 0-8) adc service request control register x (3fc h - x*4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-29 v1.1, 2011-03 adc, v1.5.2 31.2.6 general adc kernel registers 31.2.6.1 request sour ce input registers the setting of the request source input registers selects the desired input signal for the gating and trigger signals of the request sources. the status of the selected inputs is monitored. additionally, the edge sensitivity for the trigger signal and the timer mode for equidistant sampling can be enabled/disabled. the actual connections depending on the device implementation, please refer to the implementation description in section 31.3 for details. note: signals from a synchronous domain can of course be connected to inputs with a synchronization stage. the additional synchronization delay of two adc module clock cycles and an additional uncertainty of one adc module clock cycle for asynchronous signals have to be taken into account when using a synchronization stage. rsirx (x = 0 - 4) request source x input register (010 h + x * 4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 tri 0 r en f en 0 trsel gti 0 tm en 0gtsel rh r rw rw r rw rh r rw r rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-30 v1.1, 2011-03 adc, v1.5.2 field bits type description gtsel [2:0] rw input selection for reqgt of source x this bit field defines the input signal used for request gating in request source x. the inputs selected by codes 0xx h are considered as synchronous to the adc module. the inputs selected by codes 1xx h are considered as asynchronous to the adc module. 000 b the input signal reqgtx_0 is selected. 001 b the input signal reqgtx_1 is selected. 010 b the input signal reqgtx_2 is selected. 011 b the input signal reqgtx_3 is selected. 100 b the input signal reqgtx_4 is selected. 101 b the input signal reqgtx_5 is selected. 110 b the input signal reqgtx_6 is selected. 111 b the input signal reqgtx_7 is selected. tmen 4rw timer mode enable of source x this bit enables the timer mode for equidistant sampling for request source x. 0 b the timer mode is disabled. the standard gating mechanism can be used. 1 b the timer mode for equidistant sampling is enabled. the standard gating mechanism has to be disabled. gti 7rh gating input of source x this flag monitors the status of the selected gating signal reqgtx for request source x. 0 b the selected gating signal is 0. 1 b the selected gating signal is 1. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-31 v1.1, 2011-03 adc, v1.5.2 trsel [10:8] rw input selection for reqtr of source x this bit field defines the input signal used for request triggering in request source x. the inputs selected by codes 0xx h are considered as synchronous to the adc module. the inputs selected by codes 1xx h are considered as asynchronous to the adc module. 000 b the input signal reqtrx_0 is selected. 001 b the input signal reqtrx_1 is selected. 010 b the input signal reqtrx_2 is selected. 011 b the input signal reqtrx_3 is selected. 100 b the input signal reqtrx_4 is selected. 101 b the input signal reqtrx_5 is selected. 110 b the input signal reqtrx_6 is selected. 111 b the input signal reqtrx_7 is selected. fen 12 rw falling edge enable of source x this bit enables the request trigger for falling edges of the selected reqtrx signa l for request source x. 0 b the request trigger with a falling edge is disabled. 1 b the request trigger with a falling edge is enabled. ren 13 rw rising edge enable of source x this bit enables the request trigger for rising edges of the selected reqtrx signa l for request source x. 0 b the request trigger with a rising edge is disabled. 1 b the request trigger with a rising edge is enabled. tri 15 rh trigger input of source x this flag monitors the status of the selected trigger signal reqtrx for request source x. 0 b the selected trigger signal is 0. 1 b the selected trigger signal is 1. 0 3, [6:5], 11, 14, [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-32 v1.1, 2011-03 adc, v1.5.2 31.2.6.2 module identification register id module identificat ion register (008 h ) reset value: 005a c001 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision this bit field indicates the revision number of the module implementation (depending on the design step). the given value of 00 h is a placeholder for the actual number. bits [3:0] refer to the version of the digital part and bits [7:4] indicate the version of the analog part (anid). mod_type [15:8] r module type mod_number [31:16] r module number www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-33 v1.1, 2011-03 adc, v1.5.2 31.2.6.3 interrupt ac tivation register the interrupt activation register contains bit locations allowing to activate one or more service request outputs sr[7:0] of the adc kern el. writing a 1 to a bit position x activates the corresponding srx line. all bit positions read as 0. intr interrupt activa tion register (204 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 si sr7 si sr6 si sr5 si sr4 si sr3 si sr2 si sr1 si sr0 r wwwwwwww field bits type description sisrx (x = 0 - 7) xw set interrupt for srx line writing a 1 to a bit position sets an interrupt request at the srx output of the adc kernel (the activation is finished automatically). writing a 0 has no effect. the read value is always 0. 0 b no action 1 b the service request output srx of the adc kernel becomes activated. 0 [31:8] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-34 v1.1, 2011-03 adc, v1.5.2 31.2.6.4 global control the global control register contains bits to control the arbiter timing and the general enable function for the analog part. globctr global control register (030 h ) reset value: 0000 00ff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 arb m 0 arbrnd anon divd diva rw rw rw rw rw rw field bits type description diva [5:0] rw divider factor for analog internal clock this bit field defines the number of f adc clock cycles to generate the f adci clock for the converter (used as internal base for the conversions and the sample time calculation). the minimum divider is 4. 00 h f adci = f adc / 4 01 h f adci = f adc / 4 02 h f adci = f adc / 4 03 h f adci = f adc / 4 04 h f adci = f adc / 4 05 h f adci = f adc / 5 06 h f adci = f adc / 6 07 h f adci = f adc / 7 ... 3f h f adci = f adc / 63 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-35 v1.1, 2011-03 adc, v1.5.2 divd [7:6] rw divider factor for digital arbiter clock this bit field defines the number of f adc clock cycles within each arbitration slot (each arbitration slots last one periods of f adcd ). it is recommended to use the default setting 00 b to obtain the minimum arbiter reaction time. 00 b f adcd = f adc 01 b f adcd = f adc / 2 10 b f adcd = f adc / 3 11 b f adcd = f adc / 4 anon [9:8] rw analog part switched on this bit field defines the setting of bit field globstr .anon (bit description see there) if this kernel is the synchronization master or without synchronization feature. for a synchronization slave, this bit field is not taken into account. arbrnd [11:10] rw arbitration round length this bit field defines the number of arbitration slots per arbitration round (arbitration round length = t arb ). 00 b an arbitration round contains 4 arbitration slots (t arb =4/f adcd ). 01 b an arbitration round contains 8 arbitration slots (t arb =8/f adcd ). 10 b an arbitration round contains 16 arbitration slots (t arb =16/f adcd ). 11 b an arbitration round contains 20 arbitration slots (t arb =20/f adcd ). field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-36 v1.1, 2011-03 adc, v1.5.2 arbm 15 rw arbitration mode this bit field defines whether the arbiter runs permanently or only while at least one conversion request is pending. 0 b the arbiter runs permanently. this setting has to be chosen in a synchronization slave (see section 31.2.19 ) and for equidistant sampling using the signal arbcnt (see section 31.2.20 ). 1 b the arbiter only runs if at least one conversion request of an enabled request source is pending. this setting leads to a reproducible latency from an incoming request to the conversion start if the converter is idle. synchronized conversi ons are not supported. 0 [14:12], [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-37 v1.1, 2011-03 adc, v1.5.2 31.2.6.5 global configuration the global configuration register configures the general adc kernel setting. globcfg global configuration register (034 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 mtm en 0mtmch0 dp cal su cal mtm 7 0 rw r rw r rw rw rw r field bits type description mtm7 4rw multiplexer test mode for channel 7 this bit enables/disables the multiplexer test mode for the input channel 7, see section 31.2.17 . this feature is independent of the current mode of the adc (anon, selected channel for conversion). 0 b the multiplexer test mode is disabled. the analog input ch7 can be used for normal measurements. 1 b the multiplexer test mode is enabled. the analog input ch7 is internally connected to ground via voltage divider based on an additional resistor. 1) sucal 5rw start-up calibration the transition from 0 to 1 of this bit starts the start-up calibration phase of the analog part. this should be done after reset before starting the first conversion to reduce analog errors. during the calibration phase (indicated by globstr .cal = 1), conversions must not be started. it can take a few f adc clock cycles before bit cal is set after a rising edge of sucal. 0 b start-up calibration can be started. 1 b start-up calibration has been started. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-38 v1.1, 2011-03 adc, v1.5.2 dpcal 6rw disable post calibration this bit enables/disables the automatic post calibration of the analog part. 0 b the automatic post calibration is enabled. 1 b the automatic post calibration is disabled. mtmch [11:8] rw multiplexer test mode channel this bit field defines the input channel number that can be enabled for multiplexer test mode in addition to channel ch7 (a value of 000001 b defines channel ch1, 000011 b channel ch3, 000101 b channel ch5, etc.). the multiplexer test mode is enabled for the selected input if mtmen = 1. mtmen 15 rw multiplexer test mode enable this bit enables the multiplexer test mode for the channel number selected by mtmch. if an even channel number is selected, this bit is internally considered as 0. 0 b the multiplexer test mode for the selected input channel is disabled. this analog input can be used for normal measurements. 1 b the multiplexer test mode for the selected input channel is enabled. this analog input is internally connected to ground via voltage divider based on an additional resistor. 1) 0 [3:0], 7, [14:12], [31:16] r reserved read as 0; should be written with 0. 1) please refer to the ac/dc chapter for the value of the grounding resistor and its current capability. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-39 v1.1, 2011-03 adc, v1.5.2 31.2.6.6 global status the status control register contains bits i ndicating the current status of a conversion. globstr global status register (038 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0csrc syn run anon 0 chnr cal sam ple bu sy r rh rh rh r rh rh rh rh field bits type description busy 0rh analog part busy this bit indicates that a conversion is currently active. 0 b the analog part is idle. 1 b a conversion is currently active. sample 1rh sample phase this bit indicates that an analog input signal is currently sampled. 0 b the analog part is not in the sampling phase. 1 b the analog part is in the sampling phase. cal 2rh calibration phase this bit indicates that the analog part is in the startup calibration phase. 0 b the analog part is not in the calibration phase. 1 b the analog part is in the calibration phase. chnr [6:3] rh channel number this bit field indicates which analog input channel is currently converted. this information is updated when a new conversion is started. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-40 v1.1, 2011-03 adc, v1.5.2 anon [9:8] rh analog part switched on this bit field defines the operation mode of the converter. it monitors either bit field globctr.anon of the same adc kernel (in master mode or without synchronization feature) or bit field globctr.anon of the adc kernel selected as synchronization ma ster for this kernel (in slave mode). this ensures that all kernels of a synchronization group can be controlled with a single write operation to bit field globctr of the synchronization master. 00 b the analog part is switched off and conversions are not possible. to achieve a minimal power consumption, the internal analog circuitry is in its power-down state and the generation of f adci and f adcd is stopped (counters set to an initial value). furthermore, the arbiter finishes its current arbitration round (if running) and then remains in the idle state. 01 b reserved, do not use 10 b reserved, do not use 11 b the analog part of the adc module is switched on and conversions are possible. synrun 10 rh synchronous conversion running this bit indicates that a synchronous (= parallel) conversion is currently running. 0 b there is no synchronous conversion running (either there is no conversion currently running or a parallel conversion has not been requested). a running conversion can be cancelled and repeated in case of a new incoming conversion request with higher priority. 1 b a synchronous conversion is running. this conversion can not be cancelled while running. higher priority requests can trigger conversions only after the end of the currently running synchronous conversion. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-41 v1.1, 2011-03 adc, v1.5.2 csrc [13:11] rh currently converted request source this bit field indicates the arbitration slot number of the current conversion (if busy = 1, a conversion is still running) or of the last conversion (if busy = 0, no conversion is running). this bit field is updated with each conversion start. 000 b the channel requested by the request source of arbitration slot 0 is (has been) converted. 001 b the channel requested by the request source of arbitration slot 1 is (has been) converted. ... 110 b the channel requested by the request source of arbitration slot 6 is (has been) converted. 111 b the channel requested by a synchronous injection is (has been) converted. 0 7, [31:14] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-42 v1.1, 2011-03 adc, v1.5.2 31.2.7 request source arbiter the request source arbiter evaluates which analog input channel has to be converted. therefore, it regularly polls the request sources one after the other for pending conversion requests. the polling sequence is based on time slots with programmable length, called arbitration slots. if a request source is disabled or if no request source is available for an arbitration slot, the slot is considered as being empty and has no influence on the evaluation of the arbitration winner. after reset, all request sources are disabled and have to be enabled by bits in register asenr to take part in the arbitration process. the number of arbitration slots forming an arbitration round can be programmed to obtain a similar arbiter timing for different devices, even if the number of available request sources differs from one device to ano ther. at the end of each arbitration round, the arbiter has determined the request sour ce with the highest priority and a pending conversion request. this arbitration result is stored as arbitration winner for further actions. if a conversion is started in an arbi tration round, this arbitration round does not deliver an arbitration winner. in the TC1798, the following request sources are available: ? request source 0 in arbitration slot 0: 1-stage sequential source this request source can issue a conver sion request for a single input channel. ? request source 1 in arbitration slot 1: 16-channel scan source this request source can issue a conversi on request sequence of up to 16 input channels in a defined order. ? request source 2 in arbitration slot 2: 4-stage sequential source this request source can issue a conversi on request sequence of up to 4 input channels in a freely programmable order. ? request source 3 in arbitration slot 3: 16-channel scan source this request source can issue a conversi on request sequence of up to 16 input channels in a defined order. ? request source 4 in arbitration slot 4: 4-stage sequential source this request source can issue a conversi on request sequence of up to 4 input channels in a freely programmable order. ? last arbitration slot of the arbitration round: synchronization source in this slot, the arbiter checks for a synchronized request from another adc kernel and does not evaluate any internal requ est source. a request for a synchronized conversion is always handled with the hi ghest priority in a synchronization slave kernel (pending requests from other sources are not considered). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-43 v1.1, 2011-03 adc, v1.5.2 figure 31-7 arbitration round with 4 arbitration slots the period t arb of an arbitration round is given by: t arb =n (globctr.divd + 1) / f adc with n being 4, 8, 16, or 20 as defined by globctr .arbrnd the period of the arbitration round introduces a timing granularity to detect an incoming conversion request signal and the earliest point to start the related conversion. this granularity can introduce a jitter of maxi mum one arbitration round. the jitter can be reduced by minimizing the period of an arbitr ation round (numbers of arbitration slots and their length). to achieve a reproducible reaction time (constant delay without jitter) between the trigger event of a conversion request (e.g. by a timer unit or due to an external event) and the start of the related conversion, mainly the following two options exist. for both options, the converter has to be idle and ot her conversion requests must not be pending for at least one arbiter round before the trigger event occurs: ? if bit globctr .arbm = 0, the arbiter runs permanently . in this mode, synchronized conversions of more than one adc kernel are possible. the trigger for the conversion triggers has to be generated synchronously to the arbiter timing. incoming triggers should have exactly n-times the granularity of the arbiter (n = 1, 2, 3, ...). in order to allow some flexibility, the duration of an arbitration slot can be programmed in cycles of f adc . ? if bit globctr .arbm = 1, the arbiter stops after an arbitration round when no conversion request have been found pending any more. the arbiter is started again if at least one enabled request source indicates a pending conversion request. the trigger of a conversion request does need not to be synchronous to the arbiter timing. in this mode, parallel conversions are not possible for synchronization slave kernels. 31.2.7.1 request source priority each request source has an individually programmable priority to be able to adapt to different applications (see registers rspr0 , rspr4 ). the priorities define the order the request sources are handled by the arbiter if two or more request sources indicate adc_arbiter_roun d arbitration slot 0 polling of request source 0 arbitration slot 2 arbitration slot 3 arbitration round arbitration slot 1 polling of request source 1 polling of request source 2 check for synchronized start request arbitration winner found conversion can be started www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-44 v1.1, 2011-03 adc, v1.5.2 pending conversion requests at the same time. starting with request source 0, the arbiter checks if an enabled request source has a pending request for a conversion. the arbitr ation winner is the request source with a pending conversion request and the highest priority that has been found first in an arbitration round. 31.2.7.2 conversion start modes to start the requested conversion of the ar bitration winner, the following aspects are automatically taken into consideration by the arbiter: ? if the converter is currently idle (no conversion running), the conversion of the arbitration winner is started immediately. ? if a conversion is currently running, the ar bitration winner is compared to the priority of the currently running conversion. in t he case that the current conversion has the same or a higher priority, it is complete d. then, the conversion of the arbitration winner is started. ? if a conversion is currently running, the ar bitration winner is compared to the priority of the currently running conversion. in t he case that the current conversion has the lower priority and the arbiter winner has been programmed for wait-for-start mode , the currently running conversion is completed. then, the conversion of the arbitration winner is started. this mode can be used if the timing requi rement for the higher priority conversions allow a jitter (between t3 and t4 in figure 31-8 ) in the range of a running conversion. ? if a conversion is currently running, the ar bitration winner is compared to the priority of the currently running conversion. in t he case that the current conversion has the lower priority and the arbiter winner has been programmed for cancel-inject-repeat mode , the current conversion is aborted imme diately if a new request with a higher priority has been found, unless both requests target the same result register with wait-for-read active (see section 31.2.15.2 ). the conversion of the arbitration winner is started after the abort action. the abort ed conversion request is restored in the request source that has requested the aborted conversion. as a consequence, it takes part again in the next arbitration round. please note that the abort mechanism can take between 1 and 3 f adci cycles, depending on the state of the current conversion. this mode can be used if higher priority conversions only tolerate a small jitter (between t8 and t9 in figure 31-8 ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-45 v1.1, 2011-03 adc, v1.5.2 figure 31-8 conversion start modes the conversion start mode can be individually programmed for each request source by bits in registers rspr0 and rspr4 and is applied to all channels requested by the source. figure 31-8 shows the influence of both conversion start modes on the conversion sequence if two request source s generate conversion requests. in this example, channel a is issued by a request source with a lower priority than the request source requesting the conversion of channel b. ? t1: the trigger event for channel a occurs and a conversion request is activated. ? t2: at the end of the arbitration round, channel a is determined as arbitration winner, the conversion of channel a is started. wi th the start of the conversion, the related conversion request is cleared. ? t3: the trigger event for channel b occurs and a conversion request is activated. in wait-for-read mode, the currently running conversion of channel a is finished normally. ? t4: after the conversion of channel a is finished, the conversion of channel b is started. with the start of the conversion , the related conversion request is cleared. ? t5: the conversion of channel b is finished. ? t6: the trigger event for channel a occurs and a conversion request is activated. ? t7: at the end of the arbitration round, channel a is determined as arbitration winner, the conversion of channel a is started. wi th the start of the conversion, the related conversion request is cleared. ? t8: the trigger event for channel b occurs and a conversion request is activated. ? t9: at the end of the arbitration round, channel b is determined as arbitration winner. in cancel-inject-repeat mode, the currently running conversion of channel a is aborted and the conversion of channel b is started. with the abort of the conversion, adc_conv_starts conversions b a a a b request channel a request channel b t2 t1 t3 t6 t8 t4 t5 t7 t9 t10 t11 wait-for-start mode cancel-inject-repeat mode www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-46 v1.1, 2011-03 adc, v1.5.2 the related conversion request is set agai n. with the start of the conversion, the related conversion request is cleared. ? t10: the conversion of channel b is fini shed. in the meantime, the pending request for channel a has been identified as arbitration winner and the conversion of channel a is started. with the start of the conversion, the related conversion request is cleared. ? t11: the conversion of channel a is finished. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-47 v1.1, 2011-03 adc, v1.5.2 31.2.8 arbiter registers 31.2.8.1 arbitration slot enable register the arbitration slot enable register contains bits to enable/disable the conversion request treatment in the arbitration slots. asenr arbitration slot enable register (03c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 as en4 as en3 as en2 as en1 as en0 r rwrwrwrwrw field bits type description asenx (x = 0-4) xrw arbitration slot x enable each bit enables an arbitration slot of the arbiter round. asen0 enables the arbitration slot 0, asen1 the slot 1, etc. if an arbitration slot is disabled, it is considered as being empty. the request bits of the request sources are not modified by write actions to asenr. 0 b the corresponding arbitration slot is disabled and is not taken into account by the arbiter. conversions are not requested, even for the request source(s) with pending request bit(s). 1 b the corresponding arbitration slot is enabled. conversions are requested for the request source(s) with pending request bit(s). 0 [31:5] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-48 v1.1, 2011-03 adc, v1.5.2 31.2.8.2 request source priority register the request source priority registers contain bi ts to define the request source priority and the conversion start mode. rspr0 request source priority register 0 (040 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 csm 3 0 prio 3 csm 2 0 prio 2 csm 1 0 prio 1 csm 0 0 prio 0 rw r rw rw r rw rw r rw rw r rw field bits type description prio0, prio1, prio2, prio3 [1:0], [5:4], [9:8], [13:12] rw priority of request source x this bit field defines the priority of the conversion request source x, located in arbitration slot x. 00 b lowest priority is selected. ... 11 b highest priority is selected. csm0, csm1, csm2, csm3 3, 7, 11, 15 rw conversion start mode of request source x this bit defines the conversion start mode of the conversion request source x, located in arbitration slot x. 0 b the wait-for-start mode is selected. 1 b the cancel-inject-repeat mode is selected. 0 2, 6, 10, 14, [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-49 v1.1, 2011-03 adc, v1.5.2 rspr4 request source priority register 4 (044 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 000000 csm 4 0 prio 4 r rwr rw r rw rwr rw field bits type description prio4 [1:0] rw priority of request source 4 this bit field defines the priority of the conversion request source 4, located in arbitration slot 4. 00 b lowest priority is selected. ... 11 b highest priority is selected. csm4 3rw conversion start mode of request source 4 this bit defines the conversion start mode of the conversion request source 4, located in arbitration slot 4. 0 b the wait-for-start mode is selected. 1 b the cancel-inject-repeat mode is selected. 0 [5:4], [9:7], 11 rw reserved these bits are reserved for future use and have to be written with 000 b . 0 2, 6, 10, [31:12] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-50 v1.1, 2011-03 adc, v1.5.2 31.2.9 scan request source handling a scan request source can issue conversion requests for a sequence of up to 16 input channels. it can be programmed individually fo r each input channel if it takes part in the scan sequence. the scan sequence always starts with the highest enabled channel number and continues towards lower channel numbers (order defined by the channel number, each channel can be converted only once per sequence). figure 31-9 scan request source 31.2.9.1 overview a scan request source performs the: ? conversion request control: the conversion request control defines if an analog input channel takes part in the scan sequence (see bits in registers crcr1 , crcr3 ). the programmed register value is kept unchanged by an ongoing scan sequence. ? conversion request pending: the pending conversion requests indicate if an input channel has to be converted in an ongoing scan sequence (see bits in registers crpr1 , crpr3 ). a conversion request can only be issued to the request sour ce arbiter if at least one pending bit is set. with each conversion start that has been triggered by the scan request source, the corresponding pending bit is automatically cleared. the scan sequence is considered finished and a request source ev ent is generated if the last conversion triggered by the scan source is finished and all pending bits have been cleared. ? request handling: the request handling blocks interfaces with the request source arbiter. it requests conversion due to pending bits in th e scan sequence and handles the conversion adc _ scan_ reqsrc conversion request control load event conversion requests pending request handling request source arbiter request status request source event trigger & gating unit gating inputs reqgtx_[7:0] trigger inputs reqtrx_[7:0] scan request source x reqgtx reqtrx www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-51 v1.1, 2011-03 adc, v1.5.2 status information. if a conversion triggered by the scan request source is aborted due to a conversion request from another re quest source with a higher priority, the corresponding pending bit is automatically set. this mechanism ensures that an aborted conversion takes part in the next ar bitration round and does not get lost. the control of the scan sequence is done based on bits in registers crmr1 , crmr3 . ? trigger and gating signal handling: the trigger and gating unit interfaces with signals and modules outside the adc module that can request conversions. for example, a timer unit can issue a request signal to synchronize conversions to pwm events. a load event starts a scan sequence by modifying the request pending bits according to the request control bits. 31.2.9.2 scan sequence operation to operate a scan request source , the following aspects should be taken into account: ? the bits in register crcrx have to be programmed to define the channels participating in the scan sequence. ? if a trigger or gating function by external signals is desired, the gating and trigger inputs have to be defined by bit fields in the related registers rsirx (x = 0 - 4) , the value of x defines the number of the arbitration slot where the scan source is connected. also the edge selection for the trigger event is done in these registers. ? the gating mechanism has to be defined by crmrx.engt. ? the corresponding arbitration slot has to be enabled to accept conversion requests from the scan source (see register asenr ). ? the load event has to be defined by bits in crmrx to start a scan sequence. ? if a load event occurs while crmrx.ldm = 0, the content of crcrx is copied to crprx (overwrite). this setting allows starting a new scan sequence and to ?forget? remaining pending bits if a load event occurs while a scan sequence is running. ? if a load event occurs while crmrx.ldm = 1, the content of crcrx is bit-wisely logical or-combined to crprx (no overwrit e). this setting allows starting a new scan sequence without ?forgetting? remaining pending bits if a load event occurs while a scan sequence is running. to start a scan sequence , the following mechanisms are supported to generate a load event: ? an external trigger signal can be selected to start a scan sequence controlled by hw by an external module or signal, e.g. a timer unit or an input pin. the trigger feature is enabled by crmrx.entr = 1. the load event is generated if the selected edge is detected at the selected trigger input reqtrx. the edge selection is done in register rsirx. ? a load event is generated under sw control by writing crmrx.ldev = 1. this mechanism starts a scan sequence without modifying the bits in register crcrx. a data write action to crcrx does not lead to a load event (first prepare the channel control, then start the sequence). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-52 v1.1, 2011-03 adc, v1.5.2 ? if sw writes data to register crprx, the wr itten data is stored in register crcrx and a load event is generated automatically. th is mechanism starts a scan sequence with the channels defined by the written data (the sequence is defined and started with a single data write action, e.g. under dma control). ? a load event is generated each time a scan sequence has finished and the request source event occurs if bit crmrx.scan = 1. this setting leads to a permanent repetition of the scan sequence. to stop or abort an ongoing scan sequence , the following mechanisms are supported: ? an external gating signal can be selected to stop and to continue a scan sequence at any point in time controlled by an external module or signal, e.g. a timer unit or an input pin. the gating feature can be enabled and the polarity of the gating signal reqgtx can be selected by crmrx.engt . the gating mechanism does not modify the contents of the conversion pending bits , but only prevents the request handling block from issuing conversion requests to the arbiter. ? the arbiter can be disabled by sw for this arbiter slot by clearing the corresponding bit asenr .asenx. this mechanism does not modify the contents of the conversion pending bits, but only prevents the arbiter from accepting requests from the request handling block. ? the pending request bits can be clear ed by writing bit crmrx.clrpnd = 1. it is recommended to stop the scan sequence before clearing the pending bits. 31.2.9.3 request source event and interrupt a request source event of a scan source occurs if the last conversion of a scan sequence is finished (all pending bits = 0). a request source event interrupt can be generated based on a request source event according to the structure shown in figure 31-10 . if a request source event is detected, it sets the corresponding indication flag in register evfr . these flags can also be set by writing a 1 to the corresponding bit position, whereas writing 0 has no effect. additionally, a gated event flag evfr .gfsx indicates that a request source interrupt has been activated. the indication flags can be cleared by sw by writing a 1 to the corre sponding bit position in register evfcr . the service request output adcy_srx that is selected by the request source event interrupt node pointer bit fields in register evnpr becomes activated each time the related request source event is detected and the interrupt generation is enabled for this event in registers crcr1 (for request source 1) or crcr3 (for request source 3). a service request output can be activated under sw control by writing intr .sisrx. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-53 v1.1, 2011-03 adc, v1.5.2 figure 31-10 interrupt generation of a scan request source adc_scan_source_in t evfr. fsx request source event request source event indication flag set crmrx. ensi request source event interrupt enable evnpry. senpx request source event interrupt node pointer scan sequence finished evfr. gfsx gated event indication flag set www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-54 v1.1, 2011-03 adc, v1.5.2 31.2.10 scan request source registers 31.2.10.1 conversion request control registers these registers contain the control and stat us bits of a scan request source. in the TC1798, two scan sources are available (s ources 1 and 3). the index describes the number of the arbitration slot where the reque st source is taking part in the arbitration. the conversion request control register contai ns the bits that are copied to the pending register when the load event occurs. this register can be accessed at two different addresses. one address for read and write access is given for crcrx (attribute ?rw?), leading to a data write to the bits in crcrx without an automatic load event. the second address only used for write actions is given for crprx (additional attribute ?h?), leading to a data write to the bits in crcrx with an automatic load event one clock cycle later. crcr1 conversion request 1 control register (090 h ) reset value: 0000 0000 h crcr3 conversion request 3 control register (0b0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-55 v1.1, 2011-03 adc, v1.5.2 field bits type description chx (x = 0-15) xrwh channel bit x each bit corresponds to one analog input channel, the channel number chx is defined by the bit position x in this register. the corresponding bit x in the conversion request pending register will be overwritten by this bit (ldm = 0) or bit-wisely or-combined with this bit (ldm = 1) when the load event occurs. 0 b the analog channel chx will not be requested for conversion by this request source. 1 b the analog channel chx will be requested for conversion by this request source. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-56 v1.1, 2011-03 adc, v1.5.2 31.2.10.2 conversion request pending registers the conversion request pending register contains the bits that are requesting a conversion of the corresponding analog channel. a read operation to crprx delivers the pending bits (attribute ?rh?). a write operation to crprx leads to a data write to the bits in crcrx with an automatic load event generation (additional attribute ?w?). crpr1 conversion request 1 pending register (094 h ) reset value: 0000 0000 h crpr3 conversion request 3 pending register (0b4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 chp 15 chp 14 chp 13 chp 12 chp 11 chp 10 chp 9 chp 8 chp 7 chp 6 chp 5 chp 4 chp 3 chp 2 chp 1 chp 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description chpx (x = 0-15) xrwh channel pending bit x write view: a write to this address targets the bits in register crcr1 (for crpr1) or crcr3 (for crpr3). read view: each bit corresponds to one analog channel, the channel number chx is defined by the bit position in the register. 0 b the analog channel chx is not requested for conversion by this request source. 1 b the analog channel chx is requested for conversion by this request source. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-57 v1.1, 2011-03 adc, v1.5.2 31.2.10.3 conversion request mode registers the conversion request mode registers contai n bits to configure the desired operating mode of the scan request sources. crmr1 conversion request 1 mode register (098 h ) reset value: 0000 0000 h crmr3 conversion request 3 mode register (0b8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ld ev clr pnd req gt 0 ld m sc an en si en tr engt r w w rh r rw rw rw rw rw field bits type description engt [1:0] rw enable gate this bit field enables the gating functionality for the request source. 00 b the request source does not issue conversion requests. 01 b the request source issues conversion requests if at least one pending bit is set. 10 b the request source issues conversion requests if at least one pending bit is set and the selected gating signal reqgtx = 1. 11 b the request source issues conversion requests if at least one pending bit is set and the selected gating signal reqgtx = 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-58 v1.1, 2011-03 adc, v1.5.2 entr 2rw enable external trigger this bit enables the extern al trigger possibility. if enabled, the load event takes place if the selected edge is detected at the external trigger input reqtrx. 0 b the external trigger is disabled. 1 b the external trigger is enabled. ensi 3rw enable source interrupt this bit enables the request source interrupt generation if a request source event occurs (last pending conversion is finished). 0 b the request source interrupt is disabled. 1 b the request source interrupt is enabled. scan 4rw autoscan enable this bit enables a permanent scan functionality. if enabled, the load event is automatically generated if a request source event occurs. 0 b the permanent scan functionality is disabled. 1 b the permanent scan functionality is enabled. ldm 5rw load event mode this bit defines the transfer mechanism triggered by the load event. 0 b with the load event, the value of register crcrx is copied to the pending register crprx (overwrite). 1 b with the load event, the value of register crcrx is bit-wisely logical or combined to the pending register crprx. reqgt 7rh request gate level this bit monitors the level at the reqgtx input. 0 b the level is 0. 1 b the level is 1. clrpnd 8w clear pending bits 0 b no action. 1 b the bits in register crprx are cleared. ldev 9w generate load event 0 b no action. 1 b a load event is generated. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-59 v1.1, 2011-03 adc, v1.5.2 0 6, [31:10] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-60 v1.1, 2011-03 adc, v1.5.2 31.2.11 sequential reque st source handling sequential request sources have been introduc ed to allow short conversion sequences with freely programmable channel numbers (contrary to a scan request source with a fixed conversion order for the enabled channel s). two versions of the sequential sources are available in each adc kernel: ? request sources in arbitration slots 2 and 4: these request sources can handle a sequence of up to 4 input channels (4-stage queue for 4 entries). this mechanism could be used to support application-specific conversion sequences, especially for timing-critical sequences containing multiple conversions of the same channel. ? request source in arbitration slot 0: this request source can handle a single input channel (1-stage queue for 1 entry). this mechanism could be used for sw -controlled conversion requests or hw- triggered conversions of a single input channe l (to ?inject? a single conversion into a running sequence). figure 31-11 sequential request source the internal structure and the handling of the sequential sources is similar for both versions. the programmed sequence is stored in a queue buffer (based on a fifo mechanism) with at least one queue stage (stage 0) and a backup stage for aborted conversions. the only difference between bot h versions is given by the number of intermediate queue stages for storing the sequence. the request source in arbitration adc_seq_reqsrc intermediate queue stages queue stage 0 request handling request source arbiter request status request source event trigger & gating unit sequential request source reqgtx reqtrx queue input refill wait for trigger backup stage abort restart e v gating inputs reqgtx_[7:0] trigger inputs reqtrx_[7:0] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-61 v1.1, 2011-03 adc, v1.5.2 slot 0 does not provide intermediate queue stages (1-stage queue with only queue stage 0), whereas the ones in arbitration slots 2 and 4 provides 3 intermediate queue stages in additional to queue stage 0 (leading to a 4-stage queue each). 31.2.11.1 overview a sequential request source performs the: ? queue input: the queue input represents the program ming interface where the sequence is defined (see qinr0 , qinr2 , qinr4 ). it does not provide any buffer capability, but handles the filling of the queue buffer (queue stage 0 plus optional intermediate queue stages) by writing data to it. the contents of the queue stages can not be directly modified by program, except by the command for flushing the complete queue. the queue input also handles the refill mechanism, an automatic re-insertion of a started conversion from queue stage 0 (including the control parameters) as new queue input. this feature allows a single setup (by sw) of a conversion sequence and multiple repetitions of the same sequence without the need to re-program it each time. a conversion sequence is repeated if all queue entries of the sequence are setup for refill mode. ? queue stage 0: the contents of this queue stage defines which channel will be requested next for a conversion (see q0r0 , q0r2 , q0r4 ). it also defines if the request should be triggered by an external event or if t he requested conversion should follow the previous one as soon as possible. it also enables the request source interrupt generation after the conversion. the contents of this queue stage is cleared when the requested conversion is started and the next queue entry can be handled (if available). ? queue backup stage: the queue backup stage is used to store the request control parameters when a conversion requested by this request source is aborted. a validation bit indicates that the aborted conversion has to be requeste d next (before the current contents of queue stage 0) to maintain the original sequence (see qbur0 , qbur2 , qbur4 ). ? request handling: the request handling block interfaces with the request source arbiter. it requests a conversion due to a valid information in queue stage 0 and handles the conversion status information. the control of the queue sequence is done based on bits in registers qmr0 , qmr2 , and qmr4 (for the arbitration slot x). ? trigger and gating signal handling: the trigger and gating unit interfaces with signals and modules outside the adc module that can request conversions. for example, a timer unit can issue a request signal to synchronize conversions to pwm events. a trigger event can start a conversion request for the entry in queue stage 0 (see qmr0 , qmr2 , qmr4 ). an www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-62 v1.1, 2011-03 adc, v1.5.2 event flag qsrx.ev indicates that a trigger event has been detected (selected edge of selected trigger input signal reqtrx if enabled by qmrx.entr or write action with qmrx.trev = 1). this bit is cleared with each conversion start requested by this source or by writing bits cev = 1, flush = 1, or clrv = 1. 31.2.11.2 sequential source operation to operate a sequential request source , the following aspects should be taken into account: ? the sequence has to be initialized by writing to the queue input qinr0 (for arbitration slot 0), qinr2 (for arbitration slot 2), or qinr4 (for arbitration slot 4) when using the refill mechanism. each write access co rresponds to one c onversion request. the desired sequence should be completely initialized before enabling the request source, because with enabled refill featur e, write accesses by sw to qinrx are not allowed. ? if a trigger or gating function by external signals is desired, the gating and trigger inputs have to be defined by bit fields in the related registers rsirx (x = 0 - 4) , the value of x defines the number of the arbi tration slot where the request source is connected. also the edge selection for the trigger event is done in these registers. ? the gating mechanism has to be defined by qmrx.engt. ? the corresponding arbitration slot has to be enabled to accept conversion requests from the sequential source (see register asenr ). to start a sequence of a sequential request source, the following mechanisms are supported: ? an external trigger signal can be selected to start a scan sequence controlled by hw by an external module or signal, e.g. a timer unit or an input pin. the trigger feature is enabled by qmrx.entr = 1. the trigger event is generated if the selected edge is detected at the selected trigger input. ? a trigger event is generated under sw control by writing qmrx.trev = 1. this mechanism starts a request if queue stage 0 contains valid data (or the queue backup stage respectively). ? a write operation to a queue input leads to a (new) valid queue entry. if the queue is empty (no valid entry), the written data arrives in queue stage 0 and starts a conversion request (if enabled by qmrx .engt and without waiting for an external trigger). if the refill mechanism is used, the queue inputs must not be written while the queue is running. write operations to a completely filled queue are ignored. to stop or abort an ongoing sequence of a sequential request source, the following mechanisms are supported: ? an external gating signal can be selected to stop and to continue a sequence at any point in time controlled by an external module or signal, e.g. a timer unit or an input pin. the gating feature can be enabled and the polarity of the gating signal reqgtx can be selected by qmrx.engt. the gating mechanism does not modify the queue www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-63 v1.1, 2011-03 adc, v1.5.2 entries, but only prevents the request handling block from issuing conversion requests to the arbiter. ? the arbiter can be disabled by sw for this arbiter slot by clearing the corresponding bit asenr .asenx. this mechanism does not modify the queue entries, but only prevents the arbiter from accepting r equests from the request handling block. ? the next pending queue entry is cleared by writing bit qmrx.clrv = 1. it is recommended to stop the sequence before clearing a queue entry (engt = 00 b ). if the queue backup stage contains a valid entry, this one is cleared, otherwise a valid entry in queue register 0 is cleared. ? all queue entries are cleared by writing bit qmrx.flush = 1. it is recommended to stop the sequence before clearing queue entries. 31.2.11.3 request source event and interrupt a request source event occurs when a conversion that has been requested by this source is completely finished. the interr upt enable bits are located in the queue 0 register (if this has not been a repeated st art after an abort) or in the queue backup register (if this has been a repeated start after an abort), e.g. see q0r0 for request source 0) or in the queue backup register (if this has been a repeated start after an abort, e.g. see qbur0 for request source 0). a request source event interrupt can be generated based on a request source event according to the structure shown in figure 31-12 . if a request source event is detected, it sets the corresponding indication flag in register evfr . these flags can also be set by writing a 1 to the corresponding bit position, whereas writing 0 has no effect. the indication flags can be cleared by sw by writing a 1 to the corresponding bit position in register evfcr . the service request output adcy_srx that is selected by the request source event interrupt node pointer bit fields in register evnpr becomes activated each time the related request source event is detected. a service request output can be activated under sw control by writing intr .sisrx. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-64 v1.1, 2011-03 adc, v1.5.2 figure 31-12 interrupt generation of a sequential request source adc_seq_source_in t to sr0 evfr. fsx to sr1 to sr7 request source event request source event indication flag ... set q0rx. ensi request source event interrupt enable evnpry. senpx request source event interrupt node pointer conversion finished triggered by request source qburx. ensi qburx. v 1 0 evcr. gfsx gated event indication flag set www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-65 v1.1, 2011-03 adc, v1.5.2 31.2.12 sequential source registers 31.2.12.1 queue mode registers these registers contain the control and status bits of a sequential source. the index describes the number of the arbitration slot where the request source is taking part in the arbitration. note: before sw modifies the queue content by qmrx.clrv or qmrx.flush, all hw actions related to this queue have to be fini shed. therefore, the arbitration slot has to be disabled and sw has to wait for at least two arbitration rounds (to be sure that this request source can no longer be an arbitration winner). then, it has to check globstr .crsc and globstr .busy to be sure that a conversion triggered by this request source is no longer running. then sw can read qburx and q0rx and can start modification of the queue content. qmr0 queue 0 mode register (080 h ) reset value: 0000 0000 h qmr2 queue 2 mode register (0a0 h ) reset value: 0000 0000 h qmr4 queue 4 mode register (0c0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0cev flu sh tr ev clr v 0 en tr engt r w w w w r rw rw www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-66 v1.1, 2011-03 adc, v1.5.2 field bits type description engt [1:0] rw enable gate this bit field enables the gating functionality for the request source. 00 b the request source does not issue conversion requests. 01 b the request source issues conversion requests if a valid conversion request is pending in the queue 0 register or in the backup register. 10 b the request source issues conversion requests if a valid conversion request is pending in the queue 0 register or in the backup register and the selected gating signal reqgtx = 1. 11 b the request source issues conversion requests if a valid conversion request is pending in the queue 0 register or in the backup register and the selected gating signal reqgtx = 0. entr 2rw enable external trigger this bit enables the exte rnal trigger possibility. 0 b the external trigger is disabled and the trigger event is not generated. 1 b the external trigger is enabled and a trigger event is generated if the selected edge is detected at the selected trigger input signal for reqtrx. clrv 8w clear v bit 0 b no action. 1 b the next pending valid queue entry in the sequence and the event flag ev are cleared. if there is a valid entry in the queue backup register (qburx.v = 1), this entry is cleared, otherwise the entry in queue register 0 is cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-67 v1.1, 2011-03 adc, v1.5.2 trev 9w trigger event 0 b no action. 1 b a trigger event is generated by sw. if the a valid entry in the request source waits for a trigger event, a conversion request is started. flush 10 w flush queue 0 b no action. 1 b all entries in the queue (including the backup stage) and the event flag ev are cleared. the queue contains no more valid entry. cev 11 w clear event flag 0 b no action. 1 b bit ev is cleared. 0 [7:3], [31:12] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-68 v1.1, 2011-03 adc, v1.5.2 31.2.12.2 queue status registers the queue status registers contain bits indicating the status of the sequential source. the filling level and t he empty information refer to t he queue intermed iate stages (if available) and to the queue register 0. an aborted conversion stored in the backup stage is not indicated by these bits (therefore, see qburx.v). qsr0 queue 0 status register (084 h ) reset value: 0000 0020 h qsr2 queue 2 status register (0a4 h ) reset value: 0000 0020 h qsr4 queue 4 status register (0c4 h ) reset value: 0000 0020 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0ev req gt 0 emp ty 0fill rrhrhrrhrrh field bits type description fill [3:0] rh filling level 1) this bit field indicates how many queue entries are valid in the sequential source. it is incremented each time a new entry is written to qinrx or by an enabled refill mechanism. it is decremented each time a requested conversion has been started. a new entry is ignored if the filling le vel has reached its maximum value. 00 b empty = 1:there is no valid entry in the queue. empty = 0:there is 1 valid entries in the queue. 01 b there are 2 valid entries in the queue. 10 b there are 3 valid entries in the queue. 11 b there are 4 valid entries in the queue. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-69 v1.1, 2011-03 adc, v1.5.2 empty 5rh queue empty this bit indicates if the sequential source contains valid entries. 0 b there are fill+1 valid entries in the queue. 1 b there are no valid entries (queue is empty). reqgt 7rh request gate level this bit monitors the level at the reqgtx input. 0 b the level is 0. 1 b the level is 1. ev 8rh event detected this bit indicates that an event has been detected while at least one valid entry has been in the queue (queue register 0 or backup stage). once set, this bit is cleared automatically when the requested conversion is started. 0 b a trigger event has not been detected. 1 b a trigger event has been detected. 0 4, 6, [31:9] r reserved read as 0; should be written with 0. 1) this bit field is always 00 b for the 1-stage queue in arbitration slot 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-70 v1.1, 2011-03 adc, v1.5.2 31.2.12.3 queue 0 registers the queue x registers 0 monitor the status of the current sequential request (queue stage 0). q0r0 queue 0 register 0 (088 h ) reset value: 0000 0000 h q0r2 queue 2 register 0 (0a8 h ) reset value: 0000 0000 h q0r4 queue 4 register 0 (0c8 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0v ex tr ensi rf 0 reqchnr r rhrhrhrh r rh field bits type description reqchnr [3:0] rh request channel number this bit field indicates the channel number that will be or is currently requested. rf 5rh refill this bit indicates if the pending request is discarded after the conversion start or if it is automatically refilled into the queue input of the request queue. 0 b the request is discarded after the conversion start. 1 b the request is refilled into the queue after the conversion start. ensi 6rh enable source interrupt this bit indicates if a request source interrupt is generated when the conversion is finished. 0 b the request source interrupt generation is disabled. 1 b the request source interrupt generation is enabled. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-71 v1.1, 2011-03 adc, v1.5.2 extr 7rh external trigger this bit indicates if a valid queue entry immediately leads to a conversion request or if the request handler waits for a trigger event. 0 b the request handler does not wait for a trigger event. 1 b the request handler waits for a trigger event. v 8rh request channel number valid this bit indicates if the queue register 0 contains a valid queue entry. 0 b the queue entry is not valid and does not lead to a conversion request. 1 b the queue entry is valid and leads to a conversion request. 0 4, [31:9] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-72 v1.1, 2011-03 adc, v1.5.2 31.2.12.4 queue backup registers the queue backup registers monitor the status of an aborted sequential request. the registers qburx and qinrx share the same register address. a read operation at this register address will deliver the ?rh? bits of register qburx. a write operation to this address will target register qinrx. qbur0 queue 0 backup register (08c h ) reset value: 0000 0000 h qbur2 queue 2 backup register (0ac h ) reset value: 0000 0000 h qbur4 queue 4 backup register (0cc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0v ex tr en si rf 0 reqchnr r rhrhrhrh r rh field bits type description reqchnr [3:0] rh request channel number this bit field contains the channel number of an aborted conversion that ha s been requested by this request source. rf 5rh refill this bit contains the refill bit of an aborted conversion that has been r equested by this request source. ensi 6rh enable source interrupt this bit contains the request source event interrupt enable bit of an aborted conversion that has been requested by this request source. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-73 v1.1, 2011-03 adc, v1.5.2 extr 7rh external trigger this bit contains the external trigger bit of an aborted conversion that has been r equested by this request source. v 8rh request channel number valid this bit indicates if the entry in the queue backup register is valid (reqchnr, rf, tr and ensi are valid). bit v is set if a running conversion that has been requested by this request source is aborted. it is cleared when the repeate d conversion is started. 0 b the backup register does not contain a valid entry. 1 b the backup register contains a valid entry. it will be requested before a valid entry in queue register 0 will be requested. 0 4, [31:9] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-74 v1.1, 2011-03 adc, v1.5.2 31.2.12.5 queue input registers the queue input registers are the entry registers for sequential requests for each sequential source (queue). the registers qburx and qinrx share the same register address. a read operation at this register address will deliver the ?rh? bits of register qburx. a write operation to this address will target the ?w? bits in register qinrx. qinr0 queue 0 input register (08c h ) reset value: 0000 0000 h qinr2 queue 2 input register (0ac h ) reset value: 0000 0000 h qinr4 queue 4 input register (0cc h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 ex tr en si rf 0 reqchnr r www r w field bits type description reqchnr [3:0] w request channel number this bit field defines the requested channel number. rf 5w refill this bit defines the refill functionality for this queue entry. 0 b the content of this queue entry is not entered again in qinrx when the related conversion is started. 1 b the content of this queue entry is automatically entered again in qinrx when the related conversion is started. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-75 v1.1, 2011-03 adc, v1.5.2 ensi 6w enable source interrupt this bit defines the request source event interrupt functionality. 0 b a request source event interrupt is not generated if the related conversion is finished. 1 b a request source event interrupt is generated if the related conversion is finished. extr 7w external trigger this bit defines the external trigger functionality. 0 b a valid queue entry immediately leads to a conversion request. 1 b a valid queue entry waits for a trigger event to occur before issuing a conversion request. 0 4, [31:8] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-76 v1.1, 2011-03 adc, v1.5.2 31.2.13 channel-related functions the channel control unit defines the conv ersion settings, that can be programmed individually for each analog input channel. therefore, a channel control register chctrx (x = 0 - 15) is associated to each analog input channel chx. after the arbiter has determined the channel to be converted, the defined settings are applied to the ad converter, comprising information about: ? conversion parameters: bit field iclsel defines which input class is taken into account for the conversion (see section 31.2.13.1 ). ? reference selection: bit field refsel defines which reference input is used for the conversion (see section 31.2.13.2 ) ? channel event handling: bit fields lcc, bndasel, and bndbsel de fine which boundaries are used for limit checking (see section 31.2.13.4 ) and which channel event leads to a channel event interrupt (see section 31.2.13.5 ). ? synchronous conversion request: bit sync defines if the channel triggers a synchronized conversion (see section 31.2.19 ). ? alias feature: in addition to the general channel control, the adc kernel supports a mechanism (named alias feature, see section 31.2.13.3 ) to redirect a conversion request to another channel number. 31.2.13.1 input classes an input class defines the length of the sample phase and the resolution of the conversion. in most applications, the characte ristics of the input circuitries (rc input low- pass filter and impedance of the signal source) are quite similar for several analog input signals, leading to similar timings for the sample phase of these channels. as a consequence, input channels with similar par ameters can be grouped together to form an input class. all channels with the same iclsel setting belong to the same input class and have the same sample phase length and resolution. in the TC1798, 4 input classes are supported. registers inpcrx (x = 0 - 3) can be programmed to adjust the sample time and the resolution to the application requirements independently for each input class. the default setting of these registers lead to the minimum sample phase length of 2 f adci cycles and conversions with 10 bits resolution. if this default se tting fits to the application requirements, bit fields chctrx (x = 0 - 15) .iclsel and registers inpcrx (x = 0 - 3) need not to be changed. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-77 v1.1, 2011-03 adc, v1.5.2 31.2.13.2 reference selection the conversion result of the adc is always referring to a reference voltage. the maximum digital result value (full scale) is obtained if the analog input voltage equals the reference voltage. in order to support more than one measurement range with full scale digital representation, the user can sele ct between the standard reference input v aref and an alternative reference input at the analog input channel ch0 for each adc kernel. the reference selection can be individually programmed for each input channel. this feature can be used to connect 5 v bas ed sensors and 3.3 v based sensors to the same adc kernel. in this case, one set of input channels refers to the standard reference input, whereas the other one refers to the voltage level at input ch0. please note that the smallest granularity 1 lsb n for n bit resolution refers to the selected reference voltage. the granularity becomes very small if a low reference voltage is applied, and as a consequence, the resulting tue increases due to noise effects. therefore it is recommended to avoid small reference voltages. 31.2.13.3 alias feature the adc kernel provides an alias feature, allowing a re-direction of conversion requests for channels ch0 or ch1 to other channel numbers. this feature can be used to measure the same input channel and to store the conversion results in two different result registers. ? the same signal can be measured twice wi thout the need to read out the conversion result to avoid data loss. this allows trig gering both conversions quickly one after the other and being independent from cpu interrupt latency. ? the sensor signal is connected to only one input channel (instead of two analog inputs). this saves input pins in low-cost applications and only the leakage of one input has to be considered in the error calculation. ? even if the analog input ch0 is used as alternative reference (see figure 31-13 ), the internal trigger and data handling features for channel ch0 can be used. ? the channel settings for both conversions can be different (boundary values, interrupts, etc.). ? if a sequential conversion request source has been set up, a conversion request for channels ch0 or ch1 can be easily directed to other input channels without flushing the queue. in typical low-cost ac-drive applications, only one common current sensor is used to determine the phase currents. depending on the applied pwm pattern, the measured value has different meanings and the sample points have to be precisely located in the pwm period. figure 31-13 shows an example where the sensor signal is connected to one input channel (chx) but two conversions are triggered for two different channels (chx and ch0). with the alias feature, a conversion request for ch0 leads to a conversion of the analog input chx instead of ch0, but taking into account the settings for ch0. although the same analog inpu t (chx) has been measured, the conversion www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-78 v1.1, 2011-03 adc, v1.5.2 results can be stored and read out from the result registers resrx (conversion triggered for chx) and resry (conversion triggered for ch0). additionally, different interrupts or limit boundaries can be selected, enabled or disabled. figure 31-13 alias feature 31.2.13.4 limit checking the limit checking mechanism automatically compares each conversion result to two boundary values (boundaries a and b). for each channel, the user can select these boundaries from a set of 4 programmable values ( lcbr0 to lcbr3 ). with this structure, the conversion result range is split into three areas: ? area i: the conversion result is below or equal to both boundaries. ? area ii: the conversion result is above one boundary and below or equal to the other boundary. ? area iii: the conversion resu lt is above both boundaries. figure 31-14 channel event generation adc_alias pwm timer resrx trigger chx resry trigger ch0 sensor adc chx reference ch0 adc_channel_events_overv channel event arbiter analog part conversion result channel number limit checking boundaries ab conversion finished www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-79 v1.1, 2011-03 adc, v1.5.2 bit field lcc in the channel control register defines the condition to generate a channel event, leading to a channel event interrupt: ? lcc = 000 b : no trigger, the channel event generation is disabled. ? lcc = 001 b : a channel event is generated if the co nversion result is not in area i. ? lcc = 010 b : a channel event is generated if the co nversion result is not in area ii. ? lcc = 011 b : a channel event is generated if the co nversion result is not in area iii. ? lcc = 100 b : a channel event is always generated (regardless of the boundaries). ? lcc = 101 b : a channel event is generated if the conversion result is in area i. ? lcc = 110 b : a channel event is generated if the conversion result is in area ii. ? lcc = 111 b : a channel event is generated if the conversion result is in area iii. figure 31-15 shows an example for limit checking where channel events are generated only if the conversion results are not in the normal operating range defined by area ii (lcc = 010 b ). typical applications for limit checking ar e temperature monitoring or overcurrent sensing. as long as the measured temper ature value is below a boundary value, the cpu does not need to be informed. in this case, a channel event should be generated only if the conversion result is in area iii (lcc = 111 b ) to indicate an over-temperature condition. if the conversion of the analog te mperature input signal is part of an auto-scan sequence autonomously triggered on a regular time base, the cpu load for the temperature monitoring is zero until the over-temperature condition is detected. figure 31-15 limit checking note: it is also possible to select the same boundary register for boundaries a and b. in this case, the conversion result range is sp lit into two ranges (area ii is empty). adc_limit_check 2 -1 conv ersion result range for n bit resolution n 0 boundary b boundary a area i area ii area iii conversion results without channel events conversion results with channel events conversion results with channel events www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-80 v1.1, 2011-03 adc, v1.5.2 31.2.13.5 channel event interrupts a channel event interrupt can be generated based on a channel event according to the structure shown in figure 31-16 . if a channel event is detected, it sets the corresponding indication flag fcx in register chfr . these flags can also be set by writing a 1 to the corresponding bit position, whereas writing 0 has no effect. the indication flags can be cleared by sw by writing a 1 to the corresponding bit position in register chfcr . figure 31-16 channel even t interrupt generation the service request output adcy_srx that is selected by the channel node pointer bit fields in registers chenpr0 , or chenpr8 is activated each time the related channel event is detected. a service request output can be activated under sw control by writing intr .sisrx. adc_channel_events_routin g to sr0 fc0 fc1 fc15 to sr1 to sr7 chenp0 chenp1 chenp15 . . . . . . channel number channel event channel event flags channel event node pointers ... www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-81 v1.1, 2011-03 adc, v1.5.2 31.2.14 channel-related registers 31.2.14.1 channel control registers the channel control registers contain bits to select the targeted result register, to control the limit check mechanism and to select an input class. the channel control register 0 defines the settings for the input channel 0, etc. chctrx (x = 0 - 15) channel x control register (100 h + x * 4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 resr sel icl sel ref sel syn c lcc bndb sel bnda sel rw rw rw rw rw rw rw field bits type description bndasel [1:0] rw boundary a selection this bit field defines which boundary will be taken as boundary a for the limit checking. 00 b the value given by lcbr0 is selected. 01 b the value given by lcbr1 is selected. 10 b the value given by lcbr2 is selected. 11 b the value given by lcbr3 is selected. bndbsel [3:2] rw boundary b selection this bit field defines which boundary will be taken as boundary b for the limit checking. 00 b the value given by lcbr0 is selected. 01 b the value given by lcbr1 is selected. 10 b the value given by lcbr2 is selected. 11 b the value given by lcbr3 is selected. lcc [6:4] rw limit check control this bit field defines the behavior of the limit checking mechanism. please refer to the coding in section 31.2.13.4 on page 31-78 . www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-82 v1.1, 2011-03 adc, v1.5.2 sync 7rw synchronization request this bit defines if a conversion request for this channel leads to a synchronized (parallel) conversion with other adc kernels. this bit is only taken into account if the adc kernel is a potential conversion master ( synctr .stsel = 00), otherwise it is considered to be 0. 0 b this channel does not request a synchronized conversion. 1 b this channel requests a synchronized conversion if the adc kernel is a potential synchronization master. refsel [9:8] rw reference input selection this bit field defines the reference source for this channel. 00 b the standard reference input v aref is selected. 01 b the alternative reference input ch0 is selected. 10 b reserved, do not use 11 b reserved, do not use iclsel [11:10] rw input class selection these bits are used to select the input class. 00 b the input class 0 is selected. 01 b the input class 1 is selected. 10 b the input class 2 is selected. 11 b the input class 3 is selected. resrsel [15:12] rw result register selection this bit field defines which result register will be the target of a conversion of this channel. 0 h result register 0 is selected. 1 h result register 1 is selected. ... f h result register 15 is selected. 0 [31:16] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-83 v1.1, 2011-03 adc, v1.5.2 31.2.14.2 input class registers the input class registers contain bits to control the sample time and the resolution for each input class. the input class register 0 defines the settings for the input class 0, etc. inpcrx (x = 0 - 3) input class register x (050 h + x * 4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0dw stc rrw rw field bits type description stc [7:0] rw sample time control this bit field defines the additional length of the sample phase, given in analog clock cycles f adci . a minimum sample phase of 2 analog clock cycles is extended by the programmed value. sample phase length = (2 + stc) / f adci dw [9:8] rw data width this bit field defines how many bits are converted for the result. the msbs of conversion results with different dw settings are left aligned in the result bit fields. bit positions that are not converted are 0. 00 b the result is 10 bits wide. 01 b the result is 12 bits wide. 10 b the result is 8 bits wide. 11 b reserved 0 [31:10] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-84 v1.1, 2011-03 adc, v1.5.2 31.2.14.3 alias register the alias register contains bits to change a requested channel number from ch0 and ch1 to another channel number, see also section 31.2.13.3 . the programmed alias channel number is replacing the internally requested number for analog input multiplexer (of the converter). the internally requested channel number is taken into account for all other internal actions and the synchronization request. alr0 alias register 0 (210 h ) reset value: 0000 0100 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 00alias1 00alias0 r rw rw r rw rw field bits type description alias0 [3:0] rw alias value for ch0 conversion requests the channel indicated in this bit field is converted instead of channel ch0. the conversion is done with the settings defined for channel ch0. alias1 [11:8] rw alias value for ch1 conversion requests the channel indicated in this bit field is converted instead of channel ch1. the conversion is done with the settings defined for channel ch1. 0 4, 12 rw reserved for future use bit is reserved for future use and has to be written with 0 b . 0 [7:5], [31:13] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-85 v1.1, 2011-03 adc, v1.5.2 31.2.14.4 limit check boundary registers the bit fields in these registers define compare value (boundary) for the limit checking unit. the reset values of the boundaries are defined as 10%, 90%, 33% and 66% of the complete result range (the msb located at bit position 11) of each conversion. lcbr0 limit check boundary register 0 (0f0 h ) reset value: 0000 0198 h lcbr1 limit check boundary register 1 (0f4 h ) reset value: 0000 0e64 h lcbr2 limit check boundary register 2 (0f8 h ) reset value: 0000 0554 h lcbr3 limit check boundary register 3 (0fc h ) reset value: 0000 0aa8 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 boundary 0 rrwr field bits type description boundary [11:2] rw boundary for limit checking this bit field contains the value for the limit checking unit that is compared to the actual conversion result. the result of the limit check is used for the generation of the channel event, see section 31.2.13.4 . 0 [1:0], [31:12] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-86 v1.1, 2011-03 adc, v1.5.2 31.2.14.5 channel flag register the channel event indication flag register chfr monitors the detected channel events. chfr channel flag register (060 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 f c15 f c14 f c13 f c12 f c11 f c10 f c9 f c8 f c7 f c6 f c5 f c4 f c3 f c2 f c1 f c0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description fcx (x = 0 - 15) xrwh event flag for channel x flag fcx indicates that a channel event for channel x has been detected. writing a 0 has no effect, whereas writing a 1 sets the written bit position without generating an interrupt. bit fcx is cleared by writing chfcr.cfcx = 1. 0 b a channel x event has not occurred. 1 b a channel x event has occurred. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-87 v1.1, 2011-03 adc, v1.5.2 31.2.14.6 channel flag clear register writing a 1 to a bit position in register chfcr clears the corresponding channel flag in register chfr. if a hardware event triggers the setting of bit chfr.x and software writes chfcr.x = 1, bit chfr.x is cleared (software overrules hardware). chfcr channel flag clear register (064 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 cf c15 cf c14 cf c13 cf c12 cf c11 cf c10 cf c9 cf c8 cf c7 cf c6 cf c5 cf c4 cf c3 cf c2 cf c1 cf c0 wwwwwwwwwwwwwwww field bits type description cfcx (x = 0 - 15) xw clear event flag for channel x 0 b no action. 1 b bit chfr.fcx is cleared. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-88 v1.1, 2011-03 adc, v1.5.2 31.2.14.7 channel event node pointer registers the bit fields in these registers define the service request output adcy_sr[7:0] that is activated if a channel event occurs and the interrupt generation is enabled for this channel. chenpr0 channel event node pointer register 0 (068 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 chenp7 0 chenp6 0 chenp5 0 chenp4 rrwrrwrrwrrw 1514131211109876543210 0 chenp3 0 chenp2 0 chenp1 0 chenp0 rrwrrwrrwrrw field bits type description chenp0, chenp1, chenp2, chenp3, chenp4, chenp5, chenp6, chenp7 [2:0], [6:4], [10:8], [14:12], [18:16], [22:20], [26:24], [30:28] rw node pointer for channel x this bit field defines which service request output becomes activated if the channel x event of kernel adcy occurs while enabled by chctrx (x = 0 - 15) .lcc. 000 b adcy_sr0 is selected. 001 b adcy_sr1 is selected. ... 111 b adcy_sr7 is selected. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-89 v1.1, 2011-03 adc, v1.5.2 chenpr8 channel event node pointer register 8 (06c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 chenp15 0 chenp14 0 chenp13 0 chenp12 rrwrrwrrwrrw 1514131211109876543210 0 chenp11 0 chenp10 0 chenp9 0 chenp8 rrwrrwrrwrrw field bits type description chenp8, chenp9, chenp10, chenp11, chenp12, chenp13, chenp14, chenp15 [2:0], [6:4], [10:8], [14:12], [18:16], [22:20], [26:24], [30:28] rw node pointer for channel x this bit field defines which service request output becomes activated if the channel x event of kernel adcy occurs while enabled by chctrx (x = 0 - 15) .lcc. 000 b adcy_sr0 is selected. 001 b adcy_sr1 is selected. ... 111 b adcy_sr7 is selected. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-90 v1.1, 2011-03 adc, v1.5.2 31.2.15 conversion result handling the result generation part handles the: ? storage of the conversion results (see section 31.2.15.1 ) ? wait-for-read mode (see section 31.2.15.2 ) ? result event interrupts (see section 31.2.15.3 ) ? result fifo buffer (see section 31.2.15.4 ) ? data reduction or anti-aliasing filtering (see section 31.2.15.5 ) figure 31-17 conversion result handling 31.2.15.1 storage of conversion results for each analog input channel, the associated channel control register chctrx (x = 0 - 15) contains a pointer bit field (resrsel) defining the result register to store the conversion result of this channel. this structure allows the user to direct conversion results of different channels to one or more result registers. depending on the application needs (data reduction, auto-scan, alias feature, result fifo, etc.), the user can distribute the conversion results to minimize cpu load or to be more tolerant against interrupt latency. an individual data valid flag vfr .vfx for each result register indicates that ?new? valid data has been stored in the corresponding result register and can be read out. due to different result handling mechanisms, the conversion result can be represented in different ways: ? data reduction filter disabled: the conversion result is maximum 12 bits wide with the msb of the conversion result being always at bit positio n 11 and the remaining lsbs filled with 0. the data valid flag is set and a result event occurs each time a new conversion result is stored in the result register. it is possible to share a result register among several analog input channels. ? data reduction filter enabled: the conversion result is maximum 12 bits wide with the msb of the conversion result being always at bit position 11 and the remaining lsbs filled with 0. the additional bits [13:12] show the msbs of the data accumulation. adc_result_handlin g result registers 0 - 15 ad conversion stage data valid flags set condition result events data reduction unit pointer to www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-91 v1.1, 2011-03 adc, v1.5.2 the data valid flag is set and a result event occurs each time a data reduction sequence is finished and the final result is available in the result register. in order to support a wait-for-read and fifo buffer features, the valid flag has to be cleared automatically when sw does a read access or the result is transferred into another fifo element (if result fifo buffering is enabled). this behavior is contradictory to debugging requirements. for debugging, it has to be possible to introduce read or write comm ands into the normal program flow, e.g. to monitor conversion results. if a debugger reads out a result register, it would change the status of the conversion result from valid = ?new? (not yet read out) to ?old? (already read out). this would have an undesired impact on the application. therefore, the read views with ?d? deliver the same value as the read views without ?d?, but without clearing the valid bit. as a result, a debugger using read views with ?d? can monitor the conversion results without influencing their status for the application. to allow debugger accesses without the risk of data sequence corruption, two different result register read views are supported. the read views refer to the same result register contents, but show a different behavior according to the address that has been read: ? standard read view resr0 and resrx (x = 1 - 15) : a read action clears the corresponding valid bit. ? read view resrd0 and resrdx (x = 1 - 15) for debugger: a read action does not clear the corresponding valid bit. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-92 v1.1, 2011-03 adc, v1.5.2 31.2.15.2 wait-for-read mode the wait-for-read mode is a feature of a result register allowing the cpu (or dma) to treat each conversion result independently without the risk of data loss. data loss could occur if the cpu does not read a conversion result from a result register before a new result overwrites the previous one. especially for auto-scan conversion sequences (or other sequences with ?relaxed? timing requirements), the wait-for-read offers the possibility to request a conversion sequence according to an event (hw or sw), but to start a new conversion according to the cpu capability to read the formerly converted result. if wait-for-read mode is enabled for a result register by setting bit wfr in register rcrx (x = 0 - 15) , a request source does not generate a conversion request while the targeted result register contains valid data (indicated by the valid flag vfx = 1) or if a currently running conversion targets the same result register. a new conversion request is generated only after the targeted result register has been read out. if two request sources target th e same result register with wait-for-read selected, a lower priority request started before the higher pr iority source has requested its conversion can not be interrupted by the higher priority request. if a higher priority request targets a different result register, the lower priority conversion can be cancelled and repeated afterwards. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-93 v1.1, 2011-03 adc, v1.5.2 31.2.15.3 result event interrupts a result event interrupt can be generated based on a result event according to the structure shown in figure 31-18 . if a result event is detected, it sets the corresponding indication flag in register evfr . these flags can also be set by writing a 1 to the corresponding bit position, whereas writing 0 has no effect. the indication flags can be cleared by sw by writing a 1 to the corresponding bit position in register evfcr . figure 31-18 result even t interrupt generation the service request output adcy_srx that is selected by the result event interrupt node pointer bit fields in registers rnpr0 or rnpr8 issues an interrupt each time the related result event is detected. a service request output can be activated under sw control by writing intr .sisrx. adc_result_event_in t to sr0 evfr. frx to sr1 to sr7 result event result event indication flag ... set rcrx. ien result event interrupt enable rnpry. renpx result event interrupt node pointer new data available www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-94 v1.1, 2011-03 adc, v1.5.2 31.2.15.4 result fifo buffer if a result register is not used as direct target for a conversion result, it can be concatenated with other result registers of the same adc kernel to form a result fifo buffer (first-in-first-out buffer mechanism). this allows to store measurement results and to read them out later with a ?relaxed? cpu access timing. it is possible to set up more than one fifo buffer structure with the available result registers. a fifo structure can be built by at least two ?neighbor? result registers with the indices x and z = x+1, where result register z represents the input and result register x represents the output of the fifo buffer. the conversion result has to be delivered by the converter stage to the fifo input, wher eas the buffered data has to be read out from the fifo output. the fifo buffer function can be enabled by setting bit fen in registers rcrx (x = 0 - 15) . in the example shown in figure 31-19 , the result registers have been configured to form two fifo buffers with two buffer stages (result registers 0/1 and 6/7, respectively), one fifo buffer with three buffer stages (result registers 2/3/4), whereas result register 5 is used as ?normal? result register without additional fifo buffer functionality. figure 31-19 result fifo buffers if more than two result neighbor registers are concatenated to a fifo buffer (from result register z to result register x, with z > x), the one with the highest index (z) is always the input and the one with the lowest index (x) is always the output. all intermediate result registers y (x < y < z) are used as intermediate fifo stages without data input or data output functionality. adc_result_fifo result register 7 cpu read out result register 6 result register 5 result register 4 result register 3 result register 2 result register 1 result register 0 cpu read out cpu read out cpu read out conversion results ch3 ad conversion stage conversion results all other channels (e.g. for scan) conversion results ch8 conversion results ch2, 7, 10 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-95 v1.1, 2011-03 adc, v1.5.2 result register features for each fifo buffer: ? result register z ( fifo buffer input ): this result regi ster can be enabled fo r data reduction. the wait-for-read mode is supported to avoid data loss if the fifo is full. result event interrupt generation is not supported. must not be read at a read view modifying the valid bit. ? result register y ( intermediate buffer stage ): this/these result register(s) must not be enabled neither for wait-for-read mode, nor for data reduction. result event interrupt generation is not supported. must not be read at a read view modifying the valid bit, nor be the target of a conversion result. ? result register x ( fifo buffer output ): this result register can be enabled for result event interrupt generation to inform the cpu that new data can be read out from this register location. data reduction and wait-for-read are not supported and have to be disabled. must not be the target of a conversion result. if enabled, a result interrupt is generated for each data word in the fifo. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-96 v1.1, 2011-03 adc, v1.5.2 31.2.15.5 data reduction filter the data reduction filter can be used as digital filter for anti-aliasing or decimation purposes. it can accumulate a maximum of 4 conversion results to generate a final result. each result register can be individually enabled for data reduction. the feature is controlled by bit field drctr in registers rcrx (x = 0 - 15) . the actual status is given by bit field drc (data reduction counter) in the related result register. conversion delivering results to other result registers do not influence the data reduction filter of result register x. as a cons equence, other channels can be converted between two conversions targeting result register x. figure 31-20 data reduction filter in the example given in figure 31-20 , a data reduction sequence of 4 accumulated conversion results is shown. the data reduction is based on three rules: ? each time bit field drc is 0 and a conversion targeting result register x is completed (t1, t5, t9), the contents of bit field rcrx.drctr is loaded into bit field drc and the conversion result is stored in result register x. ? each time bit field drc is not 0 and a conversion targeting result register x is completed (t2, t3, t4 for the first final result and t6, t7, t8 for the next one), bit field drc is decremented by 1 and the conversion result is added to the value already stored in result register x. ? each time bit field drc is 0 after decrementing or after loading it with rcrx.drctr = 0 (t4 for the first final result and t8 for the next one), the valid bit for the result register x becomes set and a result register event occurs. the final result of a data reduction sequence has to be read out from result register x before the next data reduction sequence starts (interval between t4 and t5, or t8 and t9 respectively). with the read out of the final result from this register, the valid flag is automatically cleared. if this interval is too short, it is reco mmended to associate a se cond result register z to conversion results r0 r1 r2 r3 r4 r5 r6 r7 drc 3 2 1 0 3 2 1 0 0 contents of result register x r0 r0 + r1 r0 + r1 + r2 r0 + r1 + r2 + r3 0 r4 r4 + r5 r4 + r5 + r6 r4 + r5 + r6 + r7 vfr.vfx adc_drc r8 t1 t2 t3 t4 t5 t6 t7 t8 t9 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-97 v1.1, 2011-03 adc, v1.5.2 result register x by enabling the result fifo mechanism for result register x, see figure 31-21 (z = x + 1). in this case, result register x is loaded with the final result elaborated by result register z when a dat a reduction sequence is finished. the final result has to be read out from result register x before the next data reduction sequence is finished (interval between t4 and t8). figure 31-21 data reduction filter with result fifo r0 r0 + r1 r0 + r1 + r2 r0 + r1 + r2 + r3 0 r4 r4 + r5 r4 + r5 + r6 r4 + r5 + r6 + r7 vfr.vfz adc_drc_fifo t1 t2 t3 t4 t5 t6 t7 t8 t9 contents of result register x r0 + r1 + r2 + r3 0 r4 + r5 + r6 + r7 vfr.vfx contents of result register z www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-98 v1.1, 2011-03 adc, v1.5.2 31.2.15.6 result data filter a certain number of the result registers can be individually enabled for data filtering. as the result registers can be individually assigned to the channels, these filters can be selected for all channels within the same adc kernel. conversions delivering results to other result registers do not influence the value of this data filter activated at result register x. as a consequence, other channels can be converted between two conversions targeting result register x. there are two different filter types implemented: ? a third order fir filter with adjustable coefficients ? a first order iir filter with adjustable coefficients the result buffer are cleared as long as no result data filter is selected by parameter drctr in register rcrx (x = 0 - 15) . only the output of this data filter can be used together with the result fifo buffer function, described in section 31.2.15.4 . fir (finite impul se response) filter each fir filter contains three filter tab coefficients a, b and c and two result buffer (rb1 and rb2) for storing the intermediate values. figure 31-22 shows the structure of the filter. figure 31-22 fir filter fir filter x contents of result register 0 + b*r0 + a*r1 c*r0 + b*r1 + a*r2 c*r1 + b*r2 + a*r3 c*r2 + b*r3 + a*r4 0 + 0 + a*r0 c*r3 + b*r4 + a*r5 c*r4 + b*r5 + a*r6 c*r5 + b*r6 + a*r7 c*r6 + b*r7 + a*r8 vfr.vfx adc_ fir t1 t2 t3 t4 t5 t6 t7 t8 t9 conversion results 0 0 0 r0 r1 r2 r3 r4 r5 r6 r7 r8 result buffer1 result buffer2 r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 conversion result result buffer1 result buffer2 result register x a b c + + www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-99 v1.1, 2011-03 adc, v1.5.2 the values from the result buffer and the conversion result are added to the result register according to their coefficients. ther e are predefined coefficients selectable in register rcrx (x = 0 - 15) , which cause a gain of 3 or 4 to the adc result leading to a 14 bit value. the valid flag ( vfr .vfx) indicates a valid result , at the first sample after activation and the result is valid for each sample. iir (infinite impulse response) filter the iir filter contains two filter tab coefficients a and b. figure 31-23 shows the structure of the filter. figure 31-23 iir filter this iir filter represents a first order low pass filter. the conversion result is added a- times to the fractional (:b) amount of the previous value of the result buffer which is copied to the associated result register. there are predefined coefficients selectable in register rcrx (x = 0 - 15) , which cause a gain of 4 to the adc result leading to a 14 bit value. the valid flag ( vfr .vfx) indicates a valid result, at the first sample after activation and the result is valid for each sample. iir filter x contents of result register rb1 = rb0/b + a*r1 rb2 = rb1/b + a*r2 rb3 = rb2/b + a*r3 rb4 = rb3/b + a*r4 rb5 = rb4/b + a*r5 rb6 = rb5/b + a*r6 rb7 = rb6/b + a*r7 rb8 = rb7/b + a*r8 vfr.vfx adc_ iir t1 t2 t3 t4 t5 t6 t7 t8 t9 conversion results r0 r1 r2 r3 r4 r5 r6 r7 r8 conversion result result buffer a :b + result register x rb0 = 0 + a*r0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-100 v1.1, 2011-03 adc, v1.5.2 31.2.16 conversion result-related registers 31.2.16.1 result register 0 the result registers deliver the conversion results and associated information. additionally to this information, result register resr0 also indicates the setting of an external analog multiplexer. the conversion results of the channel used with an external multiplexer have to be directed to resr0 in order to indicate the multiplexer setting used during the conversion. if this information is not necessary, the conversion result can be directed to any other result register. the valid flag vf indicates that a result register contains updated data and can be used to poll for new data. the valid flag of a result register is cleared automatically if at least the low byte of register resr0 is read, whereas it is left unchanged when reading resrd0. resr0 result register 0 (180 h ) reset value: 0000 0000 h resrd0 result register 0 for debugging (1c0 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vf drc 0 chnr 0 crs 0 emux rh rh r rh r rh r rh 1514131211109876543210 0 result rrh field bits type description result [13:0] rh conversion result this bit field contains the conversion result, or respectively, the result of the data reduction filter. emux [18:16] rh external multiplexer setting this bit field indicates the external multiplexer setting leading to the result stored in bit field result. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-101 v1.1, 2011-03 adc, v1.5.2 crs [22:20] rh converted request source this bit field indicates the request source that has requested the conversion leading to the result stored in bit field result. 000 b the conversion was requested by source 0. 001 b the conversion was requested by source 1. 010 b the conversion was requested by source 2. 011 b the conversion was requested by source 3. 100 b the conversion was requested by source 4. else reserved chnr [27:24] rh channel number this bit field contains the channel number of the latest register update. drc [30:29] rh data reduction counter this bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction. the valid flag is automatically set when this bit field becomes 0. it can be cleared by sw by writing a 1 to the related bit position in register vfr. 00 b the final result is available in the result register. the valid flag is automatically set when this bit field is set to 0. 01 b 1 more conversion result has to be added to obtain the final result in the result register. 10 b 2 more conversion results have to be added to obtain the final result in the result register. 11 b 3 more conversion results have to be added to obtain the final result in the result register. vf 31 rh valid flag this bit indicates that bit field result has been updated with valid data since it has been read out. it is another view of the corresponding bit in register vfr. 0 b the result register has not been updated. 1 b the result register has been updated. 0 [15:14], 19, 23, 28 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-102 v1.1, 2011-03 adc, v1.5.2 31.2.16.2 result registers 1 to 15 the result registers deliver the conversion results and associated information. the valid flag vf indicates that the result register contain updated data and can be used to poll for new data. the valid flag of a result register is cleared automatically if at least the low byte of register resrx is read, whereas it is left unchanged when reading resrdx. resrx (x = 1 - 15) result register x (180 h + x * 4) reset value: 0000 0000 h resrdx (x = 1 - 15) result register x for debugging (1c0 h + x * 4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vf drc 0 chnr 0 crs 0 rh rh r rh r rh r 1514131211109876543210 0 result rrh field bits type description result [13:0] rh conversion result this bit field contains the conversion result, or respectively, the result of the data reduction filter. crs [22:20] rh converted request source this bit field indicates the request source that has requested the conversion leading to the result stored in bit field result. 000 b the conversion was requested by source 0. 001 b the conversion was requested by source 1. 010 b the conversion was requested by source 2. 011 b the conversion was requested by source 3. 100 b the conversion was requested by source 4. else reserved chnr [27:24] rh channel number this bit field contains the channel number of the latest register update. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-103 v1.1, 2011-03 adc, v1.5.2 drc [30:29] rh data reduction counter this bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction. the valid flag is automatically set and a result event is generated when this bit field becomes 0 (by decrementing or by reload). bit field drc is cleared by writing the related vfr .vfx = 1. 00 b the final result is available in the result register. 01 b 1 more conversion result has to be added to obtain the final result in the result register. 10 b 2 more conversion results have to be added to obtain the final result in the result register. 11 b 3 more conversion results have to be added to obtain the final result in the result register. vf 31 rh valid flag this bit indicates that bit field result has been updated with valid data since it has been read out. it is another view of the corresponding bit in register vfr. 0 b the result register has not been updated. 1 b the result register has been updated. 0 [19:14], 23, 28 r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-104 v1.1, 2011-03 adc, v1.5.2 31.2.16.3 valid flag register the valid flag register contains the flags indicating that the corresponding result register contents are valid (valid = ?new? = not read out). these bits are another (condensed) view of the valid flags in the result registers. vfr valid flag register (200 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 vf 15 vf 14 vf 13 vf 12 vf 11 vf 10 vf 9 vf 8 vf 7 vf 6 vf 5 vf 4 vf 3 vf 2 vf 1 vf 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description vfx (x = 0 - 15) xrwh valid flag for result register x this bit indicates that the contents of the result register x is valid. writing a 0 has no effect, whereas writing a 1 clears the written bit position and the bit field drc in the related result register. if a hardware event triggers the setting of a bit vfx and sw writes a 1 to the same bit position, the bit vfx is cleared (software overrules hardware). 0 b the result register x does not contain valid data. either this register has been read out or no data has been moved to it. 1 b the result register x contains valid data that has not yet been read out. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-105 v1.1, 2011-03 adc, v1.5.2 31.2.16.4 result control registers the result control registers contain bits to control the behavior of the result registers and to monitor their status. result register x is controlled by result control register x. rcrx (x = 0 - 15) result control register x (140 h + x * 4) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 rfctr 0 wfr fen enri 0 drctr r rw r rw rw rw r rw field bits type description drctr [2:0] rw data reduction and filter control this bit field defines the processing of the result register (see section 31.2.15.5 and section 31.2.15.6 ). it defines the reload value for bit field drc. 000 b the data reduction filter is disabled. the reload value for drc is 0, so no accumulation is done. 001 b the data reduction filter is enabled. the reload value for drc is 1, so the accumulation is done over 2 conversions. 010 b the data reduction filter is enabled. the reload value for drc is 2, so the accumulation is done over 3 conversions. 011 b the data reduction filter is enabled. the reload value for drc is 3, so the accumulation is done over 4 conversions. 100 b the result data filter x is enabled. the filter coefficients are selected by rfctr [11:8] in the same register. 1) 101 b reserved, do not use 110 b reserved, do not use 111 b reserved, do not use www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-106 v1.1, 2011-03 adc, v1.5.2 enri 4rw enable result interrupt this bit enables the result event interrupt if a result event is detected for result register x. 0 b the result event interrupt is disabled. 1 b the result event interrupt is enabled. fen 5rw fifo enable this bit enables the fifo functionality for result register x, see section 31.2.15.4 . 0 b the fifo functionality is disabled. 1 b the fifo functionality is enabled. wfr 6rw wait-for-read mode this bit enables the wait-for-read mode for result register x. 0 b the wait-for-read mode is disabled. 1 b the wait-for-read mode is enabled. rfctr [11:8] rw result filter control 1) this bit field defines the filter coefficients of the data filter. 0000 b fir: a=2, b=1 c=0 0001 b fir: a=1, b=2 c=0 0010 b fir: a=2, b=0 c=1 0011 b fir: a=1, b=1 c=1 0100 b fir: a=1, b=0 c=2 0101 b fir: a=3, b=1 c=0 0110 b fir: a=2, b=2 c=0 0111 b fir: a=1, b=3 c=0 1000 b fir: a=3, b=0 c=1 1001 b fir: a=2, b=1 c=1 1010 b fir: a=1, b=2 c=1 1011 b fir: a=2, b=0 c=2 1100 b fir: a=1, b=1 c=2 1101 b fir: a=1, b=0 c=3 1110 b iir: a=2, b=2 1111 b iir: a=3, b=4 0 3, 7, [31:12] r reserved read as 0; should be written with 0. 1) availability of field rfctr and selection drctr = 100b depends on implementation. please refer to section 31.3.3 . field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-107 v1.1, 2011-03 adc, v1.5.2 31.2.16.5 event flag register the event flag register contains flags related to request source events and result register events. evfr event flag register (070 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 gf s4 gf s3 gf s2 gf s1 gf s0 0 f s4 f s3 f s2 f s1 f s0 r rhrhrhrhrh r rwhrwhrwhrwhrwh 1514131211109876543210 f r15 f r14 f r13 f r12 f r11 f r10 f r9 f r8 f r7 f r6 f r5 f r4 f r3 f r2 f r1 f r0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh field bits type description frx (x = 0 - 15) xrwh event flag for result register x flag frx indicates that a result event of result register x has been detected. writing a 0 has no effect, whereas writing a 1 sets the written bit position without generating an interrupt. bit frx is cleared by writing evfcr.cfrx = 1. 0 b an event of result register x has not yet been detected. 1 b an event of result register x has been detected. fsx (x = 0 - 4) x + 16 rwh event flag for request source x flag fsx indicates that a request source event of request source x has been detected. writing a 0 has no effect, whereas writing a 1 sets the written bit position without generating an interrupt. bit fsx is cleared by writing evfcr.cfsx = 1. 0 b an event of request source x has not yet been detected. 1 b an event of request source x has been detected. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-108 v1.1, 2011-03 adc, v1.5.2 gfsx (x = 0 - 4) x + 24 rh gated event flag for request source x flag gfsx indicates that a request source event of request source x has been detected while the related interrupt was enabled. writing to this bit position has no effect. bit gfsx is cleared by writing evfcr.cfsx = 1. 0 b an event of request source x has not yet been detected or the related interrupt was not enabled. 1 b an event of request source x has been detected while the related event interrupt was enabled. 0 [23:21], [31:29] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-109 v1.1, 2011-03 adc, v1.5.2 31.2.16.6 event flag clear register writing a 1 to a bit position in register evfcr clears the corresponding event flag in register evfr. if a hardware event triggers the setting of bit evfr.x and software writes evfcr.x = 1, bit evfr.x is cleared (software overrules hardware). evfcr event flag clear register (074 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 cf s4 cf s3 cf s2 cf s1 cf s0 r wwwww 1514131211109876543210 cf r15 cf r14 cf r13 cf r12 cf r11 cf r10 cf r9 cf r8 cf r7 cf r6 cf r5 cf r4 cf r3 cf r2 cf r1 cf r0 wwwwwwwwwwwwwwww field bits type description cfrx (x = 0 - 15) xw clear event flag for result register x 0 b no action. 1 b bit evfr.frx is cleared. cfsx (x = 0 - 4) x + 16 w clear event flag for source x 0 b no action. 1 b bits evfr.fsx and evfr.gfsx are cleared. 0 [31:21] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-110 v1.1, 2011-03 adc, v1.5.2 31.2.16.7 event node pointer registers the bit fields in these registers define the service request output adcy_sr[7:0] that is activated if a request source event or a re sult register event occurs and the interrupt generation is enabled for this event. evnpr event node pointer register (078 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 senp4 rrw 1514131211109876543210 0 senp3 0 senp2 0 senp1 0 senp0 rrwrrwrrwrrw field bits type description senp0, senp1, senp2, senp3, senp4 [2:0], [6:4], [10:8], [14:12], [18:16] rw node pointer for request source x this bit field defines which service request output becomes activated if the request source x event of kernel adcy occurs while the interrupt generation is enabled for this event. 000 b adcy_sr0 is selected. 001 b adcy_sr1 is selected. ... 111 b adcy_sr7 is selected. 0 3, 7, 11, 15, [31:19] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-111 v1.1, 2011-03 adc, v1.5.2 rnpr0 result node pointer register 0 (208 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 renp7 0 renp6 0 renp5 0 renp4 rrwrrwrrwrrw 1514131211109876543210 0 renp3 0 renp2 0 renp1 0 renp0 rrwrrwrrwrrw field bits type description renp0, renp1, renp2, renp3, renp4, renp5, renp6, renp7 [2:0], [6:4], [10:8], [14:12], [18:16], [22:20], [26:24], [30:28] rw node pointer for result register x this bit field defines which service request output becomes activated if the result register x event of kernel adcy occurs while the interrupt generation is enabled for this event. 000 b adcy_sr0 is selected. 001 b adcy_sr1 is selected. ... 111 b adcy_sr7 is selected. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-112 v1.1, 2011-03 adc, v1.5.2 rnpr8 result node pointer register 8 (20c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 renp15 0 renp14 0 renp13 0 renp12 rrwrrwrrwrrw 1514131211109876543210 0 renp11 0 renp10 0 renp9 0 renp8 rrwrrwrrwrrw field bits type description renp8, renp9, renp10, renp11, renp12, renp13, renp14, renp15 [2:0], [6:4], [10:8], [14:12], [18:16], [22:20], [26:24], [30:28] rw node pointer for result register x this bit field defines which service request output becomes activated if the result register x event of kernel adcy occurs while the interrupt generation is enabled for this event. 000 b adcy_sr0 is selected. 001 b adcy_sr1 is selected. ... 111 b adcy_sr7 is selected. 0 3, 7, 11, 15, 19, 23, 27, 31 r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-113 v1.1, 2011-03 adc, v1.5.2 31.2.17 multiplexer test support a specific multiplexer test mode has been implemented for the analog input ch7 that can be enabled during run time by the user to check the connection to the sensor. ? multiplexer test mode disabled ( globcfg .mtm7 = 0): the switch for the voltage divider and static load r mtm7 is open. the analog input ch7 can be used for normal measurements. ? multiplexer test mode enabled ( globcfg .mtm7 = 1): the switch for the voltage divider and static load r mtm7 is closed. the analog input ch7 is loaded by a resulting resistance and the measured voltage is reduced by a voltage divider. please refer to the ac/dc chapter for the value of the resulting grounding resistor and its curr ent capability. figure 31-24 multiplexer test mode for ch7 in addition to the multiplexer test support for channel ch7 based on bit mtm7, one of the input channels listed below can also be enabled for the same function. the additional channel number is selected by bit field globcfg.mtmch and the test mode becomes enabled for this channel if globcfg.mtmen = 1. the following channels can be selected for the additional multiplexer test mode support: ch1, ch3, ch5, ch7, ch9, ch11, ch13, ch15 the channels with an even channel number do not support this test mode, even if their channel number is selected and mtmen = 1. the multiplexer test mode for input channel ch7 can be activated by both mechanisms. adc_mtm7_ adc kernel c ain r ain v agnd ch7 c ext v ainx r ext v s v c r mtm7 v ssm www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-114 v1.1, 2011-03 adc, v1.5.2 31.2.18 external mu ltiplexer control if an application requires more analog inputs channels than available on the TC1798, the adc kernel supports an extension of analog channels by adding an external analog multiplexer. three output signals emux[2:0] are delivered by the adc kernel to control the settings of an external analog multiplexer. they can be used to extend the number of analog input channels by adding an external 1-out-of-8 multiplexer. the external multiplexer control behavior is defined by the bits in register emctr . the current setting of emux[2:0] is given by bit field emux. if another extended input channel should be converted, bit field set emux has to be programmed to the desired value or the scan function has to be ena bled. the setemux value is automatically applied with the start of the next conversion of the related analog adc input channel. in the example shown in figure 31-25 and in the description below, the analog input ch7 has been extended, leading to additional analog inputs named ch70 to ch77. the channel number where the external multiplexer is connected to is defined by bit field emuxchnr. figure 31-25 external analog multiplexer if the external multiplexer is located far from the adc analog input, it is recommended to introduce an rc filter r ext1 -c ext1 directly at the analog input ch7 of the adc. if needed for signal filtering, local rc filters r ext2 -c ext2 can be optionally added at the inputs of the external analog multiplexer. if the external multiplexer is located close to the analog adc input, the components r ext1 and c ext1 are not necessarily needed. in this case it is strongly recommended to . . . adc_ext_mux ch0 adc . . . emux control internal analog multiplexer external analog 8-to-1 multiplexer channel control emux[2:0] adc kernel c ext1 r ext2 c ext2 r ext1 c ext c ext r ext r ext r ext2 c ext2 r ext2 c ext2 ch6 ch7 ch70 ch71 ch77 extended input signals direct input signals www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-115 v1.1, 2011-03 adc, v1.5.2 introduce rc filters (r ext2 , c ext2 ) at the multiplexer inputs. please note that each rc filter limits the bandwidth of the analog input signal. the rc filters used with an external multiplexer may lead to another impedance ?seen? by the adc analog input ch7 than for the other (direct) analog inputs. the adaptation of the sample phase length can be done by us ing a different input class with a different value for the sample phase extension. this value can be adapted to execute conversions with an emux[2:0] setting that has changed a sufficiently long time before the conversion of ch7 starts. ?a sufficiently long time before? signifies that signal transitions at the analog adc input due to changing multiplexer setting are finished and the input signal is stable enough. after changing the emux[2:0] setting of the external multiplexer, an additional settling time has to elapse before the switched analog signal is stable and can be measured. to compensate for this settling time, an alternative sample phase length (instead of the one given by the input class) is automatically applied for the first conversion of ch7 after emux[2:0] has changed. the alternative sample phase length can be programmed by bit field emctr .emsample. if the first conversion of ch7 after the emux[2:0] setting has changed is aborted due to a higher priori ty request, the repeated conversion of ch7 also uses the value of emsample. the settlin g time is considered to be finished after the complete conversion of ch7. the external multiplexer control block suppor ts different modes, that are programmed by the bits in register emctr : ? sw control without any hw interaction (emuxen = 0): the automatic control of the external multiplexer setting and of the sampling time is disabled. bit field emux is permanently updated with the value of setemux. the changes of emux are related to write ac tions to setemux and not to conversion timing. the setting of emsample is not taken into account. it is recommended to write the start value of the first scan sequence to setemux while emuxen = 0. ? hw control without scan (emuxen = 1, scanen = 0): the update of emux with the value of setemux happens with each conversion start of the channel selected by emuxchnr. for the first conversion with a new emux value, the setting of emsample is applied. ? hw control with single-input scan (emuxen = 1, scanen = 1, troen = 0): the update of emux with a new value happens after each conversion of the channel selected by emuxchnr. for each update, emux is automatically decremented by 1. if emux = 0, it is reloaded with the value of setemux for the next update. for each conversion of the selected channel, the setting of emsample is applied. with this setting, an autoscan sequence requesting the conversion of the channel defined by emuxchnr leads to one conversion of the channel connected to the external multiplexer. as a result, for each completed auto scan sequence, another emux setting is applied. assuming inputs 1, 2, 70, 71, and 72 being selected for scan, the following sequence will be executed: 1, 2, 72, 1, 2, 71, 1, 2, 70, 1, 2, 72, 1, 2, 71, 1, 2, 70, 1, 2, 72, ... www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-116 v1.1, 2011-03 adc, v1.5.2 ? hw control with multi-input scan (emuxen = 1, scanen = 1, troen = 1): the update of emux with a new value happens after each conversion of the channel selected by emuxchnr. for each update, emux is automatically decremented by 1. if emux = 0, it is reloaded with the value of setemux for the next update. for each conversion of the selected channel, the setting of emsample is applied. with enabled trigger option, the external multiplexer control block triggers a new conversion request each time a conversion is started of the channel defined by emuxchnr while emux > 0. in a scan request source, the corresponding pending bit becomes set, whereas in a sequential request source, the content of the backup stage becomes valid (v bit of backup stage becomes set). with this setting, all external multiplexer inputs are scanned during a single autoscan sequence, starting with the channel indicated by setemux (same update rate of all channels of this sequence). assuming inputs 1, 2, 70, 71, and 72 being selected for scan, the following sequence will be executed: 1, 2, 72, 71, 70, 1, 2, 72, 71, 70, 1, 2, 72, 71, 70, 1, 2, 72, ... www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-117 v1.1, 2011-03 adc, v1.5.2 31.2.19 synchronized conversions for parallel sampling the independent adc kernels implemented in the TC1798 can be synchronized for simultaneous (parallel) measurements of analog input channels. while no parallel conversion is requested, the kernels can work independently. the synchronization mechanism for parallel conversions ensures that the sample phases of the related channel start simultaneously. different values for the resolution and the sample phase length of each kernel for a parallel conversion are supported. a parallel conversion can be requested indivi dually for each input channel (also several channels can be enabled for parallel conversions). in the example shown in the figure below, input channels ch3 of the adc kernels adc0 and adc1 are converted synchronously, whereas other input channels do not lead to parallel conversions. this leads to the following structure: ?a synchronization master adc kernel can request a conversion of an analog channel. if this channel is selected for a synch ronized conversion, it is also requested in the connected slave adc kernel(s). ?a synchronization slave adc kernel reacts to inco ming synchronized conversion requests from its master. while no incoming master requests are active, the slave kernel can convert its own requests. ? all adc kernels in an adc module being similar, each kernel can be set up to be a synchronization master or a synchronization slave (depending on the application needs, such as trigger capability of request sources). ? a synchronization master can synchronize several slave kernels, whereas a slave kernel can only be synchronized to one master kernel. figure 31-26 parallel conversions ch0 conversions kernel adc0 adc_parallel_conv conversions kernel adc1 ch2 ch3 ch3 ch2 ch4 ch3 ch3 ch5 ch7 ch8 parallel conversions requested by adc0 ch1 parallel conversions triggering adc1 running conversion is aborted and repeated afterwards www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-118 v1.1, 2011-03 adc, v1.5.2 the term ?conversion group? has been introduced to define the kernel behavior allowing parallel sampling: ? kernels in the same conversion group can execute parallel conversions. ? a conversion group contains at least 1 ad c kernel and can contain a maximum of all adc kernels of the adc module. ? each conversion group contains exactly one synchronization master kernel that issues a parallel conversion request a nd defines the internal frequencies f adci and f adcd and the channel number for a parallel conversion of the conversion group. ? all other kernels in a conversion group are synchronization slaves and have to be programmed with the same values of globctr .diva, divd and arbrnd as the synchronization master. ? if there is no need for parallel conversions, each kernel can be considered to form an own conversion group with only an a dc kernel as synchronization master, but without any synchronization slave. ? the channel number and the synchronization request are issued by the synchronization master to the kernels in the same synchronization group if a conversion is requested with chctrx (x = 0 - 15) .sync = 1 in the synchronization master kernel. synchronization slaves can not issue synchronization requests. ? once started, a parallel conversion can not be aborted. ? a parallel conversion request is alwa ys handled with highest priority and cancel- inject-repeat mode in a synchronization slave (see section 31.2.7.2 ). ?bit globctr .arbm has to be 0 for synchronization slaves. ? the wait-for-read mode is supported for the master kernel, whereas the setting is ignored in the slave kernels (previous results may be overwritten). the synchronization request issuing mechanism of the master to the slave kernels is based on bit field globstr .anon. the information given by globctr .anon is distributed by the synchronization master to all kernels in the conversion group (the bit fields synctr .stsel of all kernels must be programmed in a way that all kernels refer to the same information). in addition to the anon information, the master delivers the requested channel number to the slave (not explicitly shown in figure 31-27 ). the start of the converters of all kernels of a conversion group is based on signals indicating when a kernel is ready and can start the sample phase of a parallel conversion. bit synctr .evalrx defines if a ke rnel has to wait fo r the other kernel(s) (to allow parallel conversions) or can star t without waiting (no parallel conversions possible). to support parallel conversions, all ready signals of the kernels of a conversion group have to be considered. the alias feature is independent of synchronized conversions. all kernels of a conversion group request the same channel number (defined by the master), but can convert analog signals from different inpu ts. the requested channel number can be redirected by its alias setting. e.g., if the channel number requested in a conversion group is channel ch0, but for a kernel, an alte rnative reference is connected to this input, www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-119 v1.1, 2011-03 adc, v1.5.2 the actually converted analog input can be changed to any value. this can be done by programming bit field alias0 accordingly. note: a parallel conversion in a slave adc sh ould not target a resu lt register that is already used for data reduction of other channels. figure 31-27 synchronization via anon and ready signals the connections of the adcx_anon and adcx_ready signals, as well as the programming hints for register emctr are de scribed in the implementation chapter, see section 31.3 . adc_anon_sync adc0 kernel kernel control globctr. anon adc0_anon synctr. stsel 00 01 10 11 globstr . anon adc1_anon globctr. anon synctr. stsel 00 01 10 11 ci1 ci1 ci2 ci2 ci3 ci3 synctr. evalr1-3 r1 r2 r3 adc1 kernel kernel control globstr . anon synctr. evalr1-3 r1 r2 r3 adc3_ready adc2_ready adc2 kernel kernel control globctr. anon adc2_anon synctr. stsel 00 01 10 11 globstr. anon adc3_anon globctr. anon synctr. stsel 00 01 10 11 ci1 ci1 ci2 ci2 ci3 ci3 synctr. evalr1-3 r1 r2 r3 adc3 kernel kernel control globstr. anon synctr. evalr1-3 r1 r2 r3 adc1_ready adc0_ready www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-120 v1.1, 2011-03 adc, v1.5.2 31.2.20 equidistant sampling each adc kernel supports equidistant sampling of one (or more) analog input channels, e.g. for audio purposes or digital filters. therefore, each request source can be programmed to take part in the arbitration round and to win the arbitration (depending on t he programmed priority levels), but without starting the conversion immediately. the exact start point of the conversion is given by a control signal (generated outside the adc module, e.g. by a timer module) that is selected as trigger input reqtrx of reques t source x. equidistant sampling is ensured if the reqtrx signal is generated synchronously to the arbiter timing, mainly for the arbiter. each adc kernel provides an output arbcnt, that is activated once per arbitration round to count the arbiter cycles as timing base for the equidistant sampling by a timer located outside the adc module. a requested equidistant conversion can start its sampling phase if the converter is idle and the arbiter has decided which channel to convert. to ensure that the converter is idle, the arbiter decides which channel to conv ert (winner of the arbitration round), but it waits for the timer control signal to really start the measurement (preface time). if the request source selected for equidistant sampling has been programmed with the highest priority, no other request source can disturb the equidistant sampling. the interpretation of the trigger signal reqtrx for equidistant sampling is enabled by selecting timer mode in the corresponding request source input register (rsirx.tmen = 1). the frequency of signal reqtrx defines the sampling rate and its high time defines the length of the preface time interval where the corresponding request source takes part in the arbitration. during the preface time, the currently running conversion can be finished. it has to be programmed to a value allowing the converter to become idle. if signal arbcnt is used as counting input signal for a timer, the arbiter has to be programmed to run permanently (globctr.arbm = 0). if the timer has an independent time base, the arbiter can be stopped while no requests are pending. the preface time has to be longer than one arbitration round. depending on the request source requesting equidistant sampling, one or more channels can be converted one after the other. the order of the requested channels being fixed by the request source, the equidistant sampling is also supported for several channels. it is also possible to do equidistant sampling for more than one request source in parallel if the preface times and the equidistant conversions do not overlap. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-121 v1.1, 2011-03 adc, v1.5.2 figure 31-28 timer mode for equidistant sampling adc_timer_mode equidistant sampling period ed reqtrx ed ed c c c c equidistant sampling period preface time preface time equidistant conversions lower priority conversions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-122 v1.1, 2011-03 adc, v1.5.2 31.2.21 access protection an access protection scheme has been implemented to avoid unintended modification of some adc control registers. it can be enabled by bits in register apr that itself is protected by the endinit mechanism. if the access protection is enabled for a group of registers and a write access occurs to one of them, the write access is discarded, the targeted register is not modified, the written data is ignored and the error flag accerr is set. the protected adc registers are located in one of the following register groups (registers not listed below can not be protected): ? register group 0: globctr ? register group 1: globcfg , emctr , rsirx (x = 0 - 4) , alr0 ? register group 2: asenr , rspr0 , rspr4 , inpcrx (x = 0 - 3) , synctr ? register group 3: chctrx (x = 0 - 15) ? register group 4: rcrx (x = 0 - 15) , vfr , lcbr0 , lcbr1 , lcbr2 , lcbr3 ? register group 5: chenpr0 , chenpr8 , evnpr , rnpr0 , rnpr8 , intr , chfr , evfr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-123 v1.1, 2011-03 adc, v1.5.2 31.2.22 broken wire detection to support self-test in safety-critical applications, each adc kernel provides a broken wire detection mechanism to check the connec tion of sensors or other voltage sources to the analog inputs of the adc kernels. this mechanism allows to prepare the capacitor field c ain before starting the sample phase and the conversion phase. a preparat ion phase is added to each conversion of an input channel with bwdenr .enx = 1 (the broken wire detection can be individually enabled for each input channel ch0 to ch15). an analog to digital conversion consists of the following phases: ? optional preparation phase: if a channel is enabled for broken wire detection, the capacitor field c ain is connected to the analog input chx defined by bwdcfgr .chp before the sample phase starts. the preparation phase length is identical to the sample phase length for this conversion. if a channel is disabled for broken wire detection, the preparation phase is omitted (default setting). ? sample phase: during this phase, the capacitor field c ain is connected to one of the analog inputs chx via an input multiplexer (see section 31.1.8.1 ). the request sources and the arbiter define which analog input has the highest priority. ? conversion phase: during this phase, the capacitor field c ain is not connected to an analog input and the analog to digital conversion takes place. at the end of this phase, c ain is loaded to about v aref /2. figure 31-29 broken wire detection adc_broken_wire complete a/d conversion without broken wire detection optional preparation phase sample phase conversion phase sample phase conversion phase complete a/d conversion with broken wire detection www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-124 v1.1, 2011-03 adc, v1.5.2 the broken wire detection mechanism allows to apply a voltage outside the expected measurement value range of the connected sens or. if the actual digital conversion result is located outside the expected measurement range (e.g. by using limit checking) with enabled broken wire detection, a defective connection has been detected. it is recommended to ensure enough margin between the voltage applied during the preparation phase and the sensors output range to minimize the effects of parasitics and leakage. input channels ch30 (v agnd ) and ch31 (v aref ) have been especially introduced to allow the selection of the maximum or the minimum voltage of the measurement range. note: the length of the complete analog to di gital conversion is increased by the length of the preparation phase if the broken wir e detection is enabled. this influences the timing of conversion sequences. the preparation phase is introduced as add itional presample phase (same behavior as the standard sampling phase, but with the possibility to select a different channel number). the analog part provides additional inputs for the channel number to be used during the presample phase and an enable line. the channel number is directly connected to bwdcfgr.chp, whereas the enable line corresponds to the bwdenr.enx bit for the arbitration winner ch x. the analog part expects these values at the beginning of the conversion (like all other signals) and automatically handles the insertion of the presample phase (handled like two consecutive sample phases with different channel numbers (but same lengt h) before starting the conversion phase). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-125 v1.1, 2011-03 adc, v1.5.2 31.2.23 additional feature registers 31.2.23.1 access protection register the access protection register apr contains bits to enable/disable modification of adc control/configuration registers by write accesse s. register apr itself is protected by the endinit mechanism. apr access protection register (218 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 acc err 0 rg5 rg4 rg3 rg2 rg1 rg0 rwh r rw rw rw rw rw rw field bits type description rgx (x = 0 - 5) xrw register group x this bit enables/disables write accesses to registers of register group x. 0 b write actions to register group x are enabled and can modify the register contents. 1 b write actions to register group x are disabled and do not modify the register contents. accerr 15 rwh access error this flag indicates a violation of the access protection mechanism for the adc kernel. it can be cleared by writing 1 to this bit position. writing 0 has no effect. 0 b a write access to a protected register group has not been detected. 1 b a write access to a protected register group has been detected and discarded. 0 [31:16], [14:6] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-126 v1.1, 2011-03 adc, v1.5.2 31.2.23.2 external mu ltiplexer control the external multiplexer control register defines the settings of the external analog multiplexer. emctr external multiplexer control register (220 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 emu xen sca nen tro en 0 emuxchnr rrwrwrwrrw 1514131211109876543210 emsample 0 emux 0 setemux rw r rh r rw field bits type description setemux [2:0] rw setting of external multiplexer if the external multiplexer control is disabled, emux is loaded with the setemux value. if enabled, the following two options are available: scan mode disabled: this bit field defines the input of the external multiplexer that will be selected for the next conversion of the channel selected by emuxchnr. bit field emux will be updated by setemux at the beginning of the next conversion of this channel. scan mode enabled: this bit field defines the start value of the scan of the external multiplexer inputs. the scan starts with the programmed input down to input 0. bit field emux is updated by setemux at the end of the conversion of this channel if emux = 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-127 v1.1, 2011-03 adc, v1.5.2 emux [6:4] rh current setting for ex ternal multiplexer this bit field defines the input of the external multiplexer selected for conversion. its value is available at the output lines emux[2:0]. if the external multiplexer control is disabled, emux is loaded with the setemux value. if enabled, the following two options are available: scan mode disabled: this bit field becomes updated by setemux at the beginning of the conversion of the channel selected by emuxchnr. scan mode enabled: this bit field is decremented by 1 at the end of the conversion of the channel selected by emuxchnr. after reaching 0, it is reloaded with the value of bit field setemux. emsample [15:8] rw external multipl exer sampling time this bit field defines the alternative sample phase length in the case the ex ternal multiplexer setting has changed with the start of a conversion with enabled external multiplexer (the value given by the selected input class is not taken into account). a minimum sample phase of 2 analog clock cycles is extended by the programmed value. sample phase length = (2 + emsample) / f adci emuxchnr [19:16] rw channel number for external multiplexer if external multiplexer control is enabled (emuxen = 1), this bit field defines the analog adc input channel connected to the external analog multiplexer. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-128 v1.1, 2011-03 adc, v1.5.2 troen 21 rw trigger option enable this bit selects the scan mode behavior of the external multiplexer (if enabled). description see section 31.2.18 . 0 b single-input scan is selected. the trigger option is disabled (no automatic trigger of more conversions of chx). 1 b multi-input scan is selected. the trigger option is enabled leading to an automatic scan through the externally connected multiplexer inputs by automatically triggering additional conversions of chx until emux = 0. scanen 22 rw scan enable this bit enables/disables the automatic scan of the inputs of the external multiplexer for conversions of the channel selected by bit field emuxchnr (taken into account only if emuxen=1). 0 b the scan mode is disabled. bit field emux is updated by bit field setemux at the beginning of a conversion of the selected channel. if bit emux is changed, the value of emsample is applied. 1 b the scan mode is enabled. bit field emux is decremented by 1 for each conversion of the selected channel. after reaching 0, bit field emux is updated by bit field setemux. the value of emsample is always applied for the selected channel. it is recommended to write the start value of the first scan sequence to setemux while emuxen=0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-129 v1.1, 2011-03 adc, v1.5.2 emuxen 23 rw external multipl exer control enable this bit enables/disables the automatic control of the external multiplexer. 0 b the external multiplexer control by hw is disabled. bit field emux is immediately updated under sw control by writing to setemux. the settings of scanen and troen are ignored. 1 b the external multiplexer control is enabled. the update of emux is under hw control respecting the conversion timings. 0 3, 7, 20, [31:24] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-130 v1.1, 2011-03 adc, v1.5.2 31.2.23.3 synchronization control register the synchronization control register contains bits controlling the synchronization between several kernels for parallel conver sions. the programming of register synctr in the kernels of a conversion group has to be done while the bit fields globctr .anon = 00 b in all adc kernels of the conversion group. bit field globctr .anon of the synchronization master can be set to 11 b afterwards. the bits evalrx are only taken into account if a synchronized, parallel conversion is requested by a master. this ensures that the conversions of the adc kernels of the same synchronization group are started at the same time for parallel sampling (although a kernel might be idle, the master and all its connected slaves have to wait for all of them being ready). synctr synchronization control register (048 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 eva lr3 eva lr2 eva lr1 0 stsel r rwrwrw r rw field bits type description stsel [1:0] rw start selection this bit field controls the synchronization mechanism of the adc kernel. 00 b the kernel is a synchronization master. the kernels own bit field globctr.anon is taken into account. 01 b the kernel is a synchronization slave. the control information at input ci1 is taken into account instead. 10 b the kernel is a synchronization slave. the control information at input ci2 is taken into account instead. 11 b the kernel is a synchronization slave. the control information at input ci3 is taken into account instead. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-131 v1.1, 2011-03 adc, v1.5.2 evalr1 4rw evaluate ready input r1 this bit defines if a kernel is considered to be part of a synchronization group. parallel conversions can only be started if the synchronization master and all slaves of the conversion group indicate that they are ready to start a parallel conversion. 0 b the ready input r1 is not considered for the start of a parallel conversion of this conversion group. 1 b the ready input r1 is considered for the start of a parallel conversion of this conversion group. evalr2 5rw evaluate ready input r2 this bit defines if a kernel is considered to be part of a synchronization group. parallel conversions can only be started if the synchronization master and all slaves of the conversion group indicate that they are ready to start a parallel conversion. 0 b the ready input r2 is not considered for the start of a parallel conversion of this conversion group. 1 b the ready input r2 is considered for the start of a parallel conversion of this conversion group. evalr3 6rw evaluate ready input r3 this bit defines if a kernel is considered to be part of a synchronization group. parallel conversions can only be started if the synchronization master and all slaves of the conversion group indicate that they are ready to start a parallel conversion. 0 b the ready input r3 is not considered for the start of a parallel conversion of this conversion group. 1 b the ready input r3 is considered for the start of a parallel conversion of this conversion group. 0 [3:2], [31:7] r reserved read as 0; should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-132 v1.1, 2011-03 adc, v1.5.2 31.2.23.4 broken wire detection enable register the broken wire detection enable register defin es if a channel is enabled for broken wire detection by introducing an additional preparation phase to the sample phase (see section 31.2.22 ). the channel number refers to the arbitration winner (can be directed to another input by the alias feature). bwdenr broken wire detection enable register (224 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 en 15 en 14 en 13 en 12 en 11 en 10 en 9 en 8 en 7 en 6 en 5 en 4 en 3 en 2 en 1 en 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw field bits type description enx (x=0-15) xrw broken wire detection enable for channel chx this bit defines if the broken wire detection is enabled for chx. 0 b the broken wire detection is disabled. 1 b the broken wire detection is enabled. 0 [31:16] r reserved read as 0; should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-133 v1.1, 2011-03 adc, v1.5.2 31.2.23.5 broken wire detection configuration register the broken wire detection configuration regi ster defines which channel number is used for the additional preparation phase. bwdcfgr broken wire detection configuration register (228 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 chp rrw field bits type description chp [4:0] rw channel number for preparation phase this bit field defines which input channel is used for the preparation phase for the broken wire detection. 0 [31:5] r reserved returns 0 if read; should be written with 0; www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-134 v1.1, 2011-03 adc, v1.5.2 31.3 implementation this chapter describes the implementation of the adc kernels in the TC1798 device. it contains the following sections: ? request sources (see section 31.3.1 ) ? address map (see section 31.3.2 ) ? result data filter (see section 31.3.3 ) ? connections to modules and pins (see section 31.3.4 ) 31.3.1 request sources in TC1798 in each adc kernel 5 request sources are implemented. they are numbered source 0 to source 4, with source x being evaluated in arbitration slot x. each request source has the possibility to select one trigger input reqtrx out of a vector reqtrx_[7:0] and one gating input reqgtx out of a vector reqgtx_[7:0]. each input vector contains 8 possible input signals, but not all of them are necessarily connected. ? source 0: 1-stage sequential source ? source 1: parallel source for up to 16 channels ? source 2: 4-stage sequential source ? source 3: parallel source for up to 16 channels ? source 4: 4-stage sequential source 31.3.2 address map the common kscfg register of the adc module can be accessed in the address range of kernel adc0. the corresponding address in the range of kernel adc1 to adc3 is not used and delivers a dummy value when read. the adc kernels are available at the following base addresses: table 31-4 registers address space module base address end address note adc0 f010 1000 h f010 13ff h adc1 f010 1400 h f010 17ff h adc2 f010 1800 h f010 1bff h adc3 f010 1c00 h f010 1fff h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-135 v1.1, 2011-03 adc, v1.5.2 31.3.3 result data filter the implementation of the result data filter as part of the result handling is individual for each adc kernel. the result register numb ers providing a data filter have been chosen in order to allow the maximum number of fifo stages (e.g. the filtered result of resr15 can be fifo-buffered in resr14). the result data filter are available at the following adc kernels: table 31-5 registers overview register short name register long name offset address page number please refer to register table in section 31.2.1 h table 31-6 availability of result data filter in the adc kernels adc kernel number of data filter r esult registers with data filter adc0 4 resr3, resr7, resr11, resr15 adc1 4 resr3, resr7, resr11, resr15 adc2 8 resr1, resr3, resr5, resr7, resr9, resr11 resr13, resr15 adc3 0 - www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-136 v1.1, 2011-03 adc, v1.5.2 31.3.4 adc module connections in addition to the standard signals of the interface between the analog and the digital parts, some side band signals have been introduced. the adc module consists of four adc kernels. all kernels support the feature set listed above and share a common adc0_kscfg register. the kernels can be synchronized to each other for parallel sampling. the channels ch4, ch5, ch6, and ch7 of adc0 and the channels ch0 of all adc kernels are always converted referring to the v aref input of the corresponding adc kernel. for these channels, the programmed alternative reference selection is not taken into account. all other channels are converted with respect to the selected reference. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-137 v1.1, 2011-03 adc, v1.5.2 31.3.4.1 adc0 connections signals of the adc module referring to the kernel of adc0 are generally named with the prefix adc0_. the kernel adc0 has its own reference inputs adc0_v agnd and adc0_v aref . depending on the package, these lines can be available as independent pins for high pin count packages or can be combined with the corresponding inputs of the other kernels for low pin count packages. the respective voltage supply lines of all adc analog parts are connected together. table 31-7 adc0 connections to analog part in TC1798 adc0 signal of analog part from/to module or pin input or output can be used to/as v ddm v ddm i analog power supply 3.3v - 5v v dda v ddmf i analog power supply for comparator, connected to fadc 3.3v supply v ssm v ssm i analog power ground v aref v aref i positive analog reference v agnd v agnd i negative analog reference, combined with other kernels ch0 an0 i analog input channel 0 ch1 an1 i analog input channel 1 ch2 an2 i analog input channel 2 ch3 an3 i analog input channel 3 ch4 an4 i analog input channel 4 ch5 an5 i analog input channel 5 ch6 an6 i analog input channel 6 ch7 an7 i analog input channel 7 ch8 an8 i analog input channel 8, overlaid with sent ch9 an9 i analog input channel 9, overlaid with sent ch10 an10 i analog input channel 10, overlaid with sent ch11 an11 i analog input channel 11, overlaid with sent www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-138 v1.1, 2011-03 adc, v1.5.2 the following table shows the digital connections of the adc0 kernel with other modules or pins in the TC1798 device. signals of the adc module referring to the kernel of adc0 are named with the prefix adc0_. ch12 an12 i analog input channel 12, overlaid with sent ch13 an13 i analog input channel 13, overlaid with sent ch14 an14 i analog input channel 14, overlaid with sent ch15 an15 i analog input channel 15, overlaid with sent table 31-8 adc0 connections of digital part in TC1798 adc0 signal of digital part from/to module or pin input 1) or output can be used to/as kernel signals arbcnt - o counting signal for arbiter rounds emuxtr - o trigger output for scanning the external multiplexer inputs emux0 p7.2 o control of external analog multiplexer(s) emux1 p7.3 emux2 p7.1 request source 0 reqgt0_0 trig10 i gpta reqgt0_1 trig12 i gpta reqgt0_2 trig14 i gpta reqgt0_3 pdout2 i eru reqgt0_4 req0 i (s) p1.0 reqgt0_5 irq1 i (s) stm (do not use for gating, but for triggering) table 31-7 adc0 connections to analog part in TC1798 (cont?d) adc0 signal of analog part from/to module or pin input or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-139 v1.1, 2011-03 adc, v1.5.2 reqgt0_6 0 i (s) not (yet) connected reqgt0_7 ccu6263_trig0 i (s) ccu6263 reqtr0_0 trig00 i gpta reqtr0_1 iout2 i eru reqtr0_2 0 i not (yet) connected reqtr0_3 adc_sr6 i common service request output 6 of adc module reqtr0_4 req1 i (s) p1.1 reqtr0_5 ccu6061_trig0 i (s) ccu6061 reqtr0_6 adc0_reqgt0 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr0_7 adc0_sr7 i (s) service request output 7 of adc0 reqtr0 - o selected trigger signal for source 0 (used as reqtrs for source 0) reqgt0 adc0_reqtr0_6 o selected gating signal for source 0 request source 1 reqgt1_0 trig10 i gpta reqgt1_1 trig12 i gpta reqgt1_2 trig14 i gpta reqgt1_3 pdout3 i eru reqgt1_4 req0 i (s) p1.0 reqgt1_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt1_6 0 i (s) not (yet) connected reqgt1_7 ccu6263_trig1 i (s) ccu6263 reqtr1_0 trig03 i gpta reqtr1_1 iout3 i eru reqtr1_2 trig16 i gpta reqtr1_3 adc_sr6 i common service request output 6 of adc module table 31-8 adc0 connections of digital part in TC1798 (cont?d) adc0 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-140 v1.1, 2011-03 adc, v1.5.2 reqtr1_4 req1 i (s) p1.1 reqtr1_5 ccu6061_trig1 i (s) ccu6061 reqtr1_6 adc0_reqgt1 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr1_7 adc0_sr7 i (s) service request output 7 of adc0 reqtr1 - o selected trigger signal for source 1 (used as reqtrs for source 1) reqgt1 adc0_reqtr1_6 o selected gating signal for source 1 request source 2 reqgt2_0 trig10 i gpta reqgt2_1 trig12 i gpta reqgt2_2 trig14 i gpta reqgt2_3 pdout3 i eru reqgt2_4 req4 i (s) p7.0 reqgt2_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt2_6 0 i (s) not (yet) connected reqgt2_7 ccu6263_trig1 i (s) ccu6263 reqtr2_0 trig04 i gpta reqtr2_1 iout3 i eru reqtr2_2 trig16 i gpta reqtr2_3 adc_sr6 i common service request output 6 of adc module reqtr2_4 req5 i (s) p7.1 reqtr2_5 ccu6061_trig1 i (s) ccu6061 reqtr2_6 adc0_reqgt2 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr2_7 adc0_sr7 i (s) service request output 7 of adc0 reqtr2 - o selected trigger signal for source 2 (used as reqtrs for source 2) table 31-8 adc0 connections of digital part in TC1798 (cont?d) adc0 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-141 v1.1, 2011-03 adc, v1.5.2 reqgt2 adc0_reqtr2_6 o selected gating signal for source 2 request source 3 reqgt3_0 trig10 i gpta reqgt3_1 trig12 i gpta reqgt3_2 trig14 i gpta reqgt3_3 pdout2 i eru reqgt3_4 req4 i (s) p7.0 reqgt3_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt3_6 0 i (s) not (yet) connected reqgt3_7 ccu6263_trig2 i (s) ccu6263 reqtr3_0 trig07 i gpta reqtr3_1 iout2 i eru reqtr3_2 trig16 i gpta reqtr3_3 adc_sr6 i common service request output 6 of adc module reqtr3_4 req5 i (s) p7.1 reqtr3_5 ccu6061_trig2 i (s) ccu6061 reqtr3_6 adc0_reqgt3 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr3_7 adc0_sr7 i (s) service request output 7 of adc0 reqtr3 - o selected trigger signal for source 3 (used as reqtrs for source 3) reqgt3 adc0_reqtr3_6 o selected gating signal for source 3 request source 4 reqgt4_0 trig10 i gpta reqgt4_1 trig12 i gpta reqgt4_2 trig14 i gpta reqgt4_3 pdout2 i eru reqgt4_4 req0 i (s) p1.0 table 31-8 adc0 connections of digital part in TC1798 (cont?d) adc0 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-142 v1.1, 2011-03 adc, v1.5.2 reqgt4_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt4_6 0 i (s) not (yet) connected reqgt4_7 ccu6263_trig2 i (s) ccu6263 reqtr4_0 trig11 i gpta reqtr4_1 iout2 i eru reqtr4_2 0 i not (yet) connected reqtr4_3 adc_sr6 i common service request output 6 of adc module reqtr4_4 i (s) p7.4 reqtr4_5 ccu6061_trig2 i (s) ccu6061 reqtr4_6 adc0_reqgt4 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr4_7 adc0_sr7 i (s) service request output 7 of adc0 reqtr4 - o selected trigger signal for source 4 (used as reqtrs for source 4) reqgt4 adc0_reqtr4_6 o selected gating signal for source 4 1) in case of input signals, the lines marked ?i? don?t contain synchronization stages, whereas the lines marked ?i (s)? contain synchronization stages (so they can directly handle asynchronous input signals). a signal connected to an input line marked ?i? has to be delivered from a block located in the same clock domain as the adc (the signal has to be synchronous to the adc clock domain). table 31-8 adc0 connections of digital part in TC1798 (cont?d) adc0 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-143 v1.1, 2011-03 adc, v1.5.2 31.3.4.2 adc1 connections signals of the adc module referring to the kernel of adc1 are named with the prefix adc1_. the kernel adc1 has its own reference inputs adc1_v agnd and adc1_v aref . depending on the package, these lines can be available as independent pins for high pin count packages or can be combined with the corresponding inputs of the other kernels for low pin count packages. the respective voltage supply lines of the adc analog parts are connected together. table 31-9 adc1 connections of analog part in TC1798 adc1 signal of analog part from/to module or pin input or output can be used to/as v ddm v ddm i analog power supply 3.3v - 5v v dda v ddmf i analog power supply for comparator, taken from fadc 3.3v supply v ssm v ssm i analog power ground v aref v aref i positive analog reference v agnd v agnd i negative analog reference, combined with other kernels ch0 an16 i analog input channel 16 ch1 an17 i analog input channel 17 ch2 an18 i analog input channel 18 ch3 an19 i analog input channel 19 ch4 an20 i analog input channel 20 ch5 an21 i analog input channel 21 ch6 an22 i analog input channel 22 ch7 an23 i analog input channel 23 ch8 an24 i analog input channel 24 ch9 an25 i analog input channel 25 ch10 an26 i analog input channel 26 ch11 an27 i analog input channel 27 ch12 an28 i analog input channel 28 ch13 an29 i analog input channel 29 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-144 v1.1, 2011-03 adc, v1.5.2 the following table shows the digital connections of the adc1 kernel with other modules or pins in the TC1798 device. output signals of the adc module referring to the kernel of adc1 are named with the prefix adc1_. ch14 an30 i analog input channel 30 ch15 an31 i analog input channel 31 table 31-10 adc1 connections of digital part in TC1798 adc1 signal of digital part from/to module or pin input 1) or output can be used to/as kernel signals arbcnt - o counting signal for arbiter rounds emuxtr - o trigger output for scanning the external multiplexer inputs emux0 p7.6 o control of external analog multiplexer(s) emux1 p7.7 emux2 - request source 0 reqgt0_0 trig10 i gpta reqgt0_1 trig12 i gpta reqgt0_2 trig14 i gpta reqgt0_3 pdout2 i eru reqgt0_4 req4 i (s) p7.0 reqgt0_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt0_6 adc0_sr7 i (s) adc1 trigger by adc0 reqgt0_7 ccu6061_trig0 i (s) ccu6061 reqtr0_0 trig00 i gpta reqtr0_1 iout2 i eru reqtr0_2 0 i not (yet) connected table 31-9 adc1 connections of analog part in TC1798 (cont?d) adc1 signal of analog part from/to module or pin input or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-145 v1.1, 2011-03 adc, v1.5.2 reqtr0_3 adc_sr6 i common service request output 6 of adc module reqtr0_4 req5 i (s) p7.1 reqtr0_5 ccu6263_trig0 i (s) ccu6263 reqtr0_6 adc1_reqgt0 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr0_7 adc1_sr7 i (s) service request output 7 of adc1 reqtr0 - o selected trigger signal for source 0 (used as reqtrs for source 0) reqgt0 adc1_reqtr0_6 o selected gating signal for source 0 request source 1 reqgt1_0 trig10 i gpta reqgt1_1 trig12 i gpta reqgt1_2 trig14 i gpta reqgt1_3 pdout3 i eru reqgt1_4 req4 i (s) p7.0 reqgt1_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt1_6 adc0_sr7 i (s) adc1 trigger by adc0 reqgt1_7 ccu6061_trig1 i (s) ccu6061 reqtr1_0 trig05 i gpta reqtr1_1 iout3 i eru reqtr1_2 trig16 i gpta reqtr1_3 adc_sr6 i common service request output 6 of adc module reqtr1_4 req5 i (s) p7.1 reqtr1_5 ccu6263_trig1 i (s) ccu6263 reqtr1_6 adc1_reqgt1 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr1_7 adc1_sr7 i (s) service request output 7 of adc1 table 31-10 adc1 connections of digital part in TC1798 (cont?d) adc1 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-146 v1.1, 2011-03 adc, v1.5.2 reqtr1 - o selected trigger signal for source 1 (used as reqtrs for source 1) reqgt1 adc1_reqtr1_6 o selected gating signal for source 1 request source 2 reqgt2_0 trig10 i gpta reqgt2_1 trig12 i gpta reqgt2_2 trig14 i gpta reqgt2_3 pdout3 i eru reqgt2_4 req0 i (s) p1.0 reqgt2_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt2_6 adc0_sr7 i (s) adc1 trigger by adc0 reqgt2_7 ccu6061_trig1 i (s) ccu6061 reqtr2_0 trig06 i gpta reqtr2_1 iout3 i eru reqtr2_2 trig16 i gpta reqtr2_3 adc_sr6 i common service request output 6 of adc module reqtr2_4 req1 i (s) p1.1 reqtr2_5 ccu6263_trig1 i (s) ccu6263 reqtr2_6 adc1_reqgt2 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr2_7 adc1_sr7 i (s) service request output 7 of adc1 reqtr2 - o selected trigger signal for source 2 (used as reqtrs for source 2) reqgt2 adc1_reqtr2_6 o selected gating signal for source 2 request source 3 reqgt3_0 trig10 i gpta reqgt3_1 trig12 i gpta reqgt3_2 trig14 i gpta table 31-10 adc1 connections of digital part in TC1798 (cont?d) adc1 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-147 v1.1, 2011-03 adc, v1.5.2 reqgt3_3 pdout2 i eru reqgt3_4 req0 i (s) p1.0 reqgt3_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt3_6 adc0_sr7 i (s) adc1 trigger by adc0 reqgt3_7 ccu6061_trig2 i (s) ccu6061 reqtr3_0 trig01 i gpta reqtr3_1 iout2 i eru reqtr3_2 trig16 i gpta reqtr3_3 adc_sr6 i common service request output 6 of adc module reqtr3_4 req1 i (s) p1.1 reqtr3_5 ccu6263_trig2 i (s) ccu6263 reqtr3_6 adc1_reqgt3 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr3_7 adc1_sr7 i (s) service request output 7 of adc1 reqtr3 - o selected trigger signal for source 3 (used as reqtrs for source 3) reqgt3 adc1_reqtr3_6 o selected gating signal for source 3 request source 4 reqgt4_0 trig10 i gpta reqgt4_1 trig12 i gpta reqgt4_2 trig14 i gpta reqgt4_3 pdout3 i eru reqgt4_4 req0 i (s) p1.0 reqgt4_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt4_6 adc0_sr7 i (s) adc1 trigger by adc0 reqgt4_7 ccu6061_trig2 i (s) ccu6061 reqtr4_0 trig13 i gpta table 31-10 adc1 connections of digital part in TC1798 (cont?d) adc1 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-148 v1.1, 2011-03 adc, v1.5.2 reqtr4_1 iout3 i eru reqtr4_2 0 i not (yet) connected reqtr4_3 adc_sr6 i common service request output 6 of adc module reqtr4_4 i (s) p7.5 reqtr4_5 ccu6263_trig2 i (s) ccu6263 reqtr4_6 adc1_reqgt4 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr4_7 adc1_sr7 i (s) service request output 7 of adc1 reqtr4 - o selected trigger signal for source 4 (used as reqtrs for source 4) reqgt4 adc1_reqtr4_6 o selected gating signal for source 4 1) in case of input signals, the lines marked ?i? don?t contain synchronization stages, whereas the lines marked ?i (s)? contain synchronization stages (so they can directly handle asynchronous input signals). a signal connected to an input line marked ?i? has to be delivered from a block located in the same clock domain as the adc (the signal has to be synchronous to the adc clock domain). table 31-10 adc1 connections of digital part in TC1798 (cont?d) adc1 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-149 v1.1, 2011-03 adc, v1.5.2 31.3.4.3 adc2 connections signals of the adc module referring to the kernel of adc2 are generally named with the prefix adc2_. the kernel adc2 has its own reference inputs adc2_v agnd and adc2_v aref . depending on the package, these lines can be available as independent pins for high pin count packages or can be combined with the corresponding inputs of the other kernels for low pin count packages. the respective voltage supply lines of all adc analog parts are connected together. table 31-11 adc2 connections to analog part in TC1798 adc2 signal of analog part from/to module or pin input or output can be used to/as v ddm v ddm i analog power supply 3.3v - 5v v dda v ddmf i analog power supply for comparator, connected to fadc 3.3v supply v ssm v ssm i analog power ground v aref v aref i positive analog reference, independent from other kernels v agnd v agnd i negative analog reference, combined with other kernels ch0 an32 i analog input channel 0 ch1 an33 i analog input channel 1 ch2 an34 i analog input channel 2 ch3 an35 i analog input channel 3 ch4 an36 i analog input channel 4, overlaid with sent ch5 an37 i analog input channel 5, overlaid with sent ch6 an38 i analog input channel 6, overlaid with sent ch7 an39 i analog input channel 7, overlaid with sent ch8 an40 i analog input channel 8, overlaid with sent ch9 an41 i analog input channel 9, overlaid with sent www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-150 v1.1, 2011-03 adc, v1.5.2 the following table shows the digital connections of the adc2 kernel with other modules or pins in the TC1798 device. signals of the adc module referring to the kernel of adc2 are named with the prefix adc2_. ch10 an42 i analog input channel 10, overlaid with sent ch11 an43 i analog input channel 11, overlaid with sent ch12 an44 i analog input channel 12 ch13 an45 i analog input channel 13 ch14 an46 i analog input channel 14 ch15 an47 i analog input channel 15 table 31-12 adc2 connections of digital part in TC1798 adc2 signal of digital part from/to module or pin input 1) or output can be used to/as kernel signals arbcnt - o counting signal for arbiter rounds emuxtr - o trigger output for scanning the external multiplexer inputs emux0 p7.4 o control of external analog multiplexer(s) emux1 p7.5 emux2 p7.0 request source 0 reqgt0_0 trig10 i gpta reqgt0_1 trig12 i gpta reqgt0_2 trig14 i gpta reqgt0_3 pdout2 i eru reqgt0_4 req6 i (s) p7.4 reqgt0_5 irq1 i (s) stm (do not use for gating, but for triggering) table 31-11 adc2 connections to analog part in TC1798 (cont?d) adc2 signal of analog part from/to module or pin input or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-151 v1.1, 2011-03 adc, v1.5.2 reqgt0_6 adc1_sr7 i (s) adc2 trigger by adc1 reqgt0_7 0 i (s) not (yet) connected reqtr0_0 trig00 i gpta reqtr0_1 iout2 i eru reqtr0_2 0 i not (yet) connected reqtr0_3 adc_sr6 i common service request output 6 of adc module reqtr0_4 req7 i (s) p7.5 reqtr0_5 0 i (s) not (yet) connected reqtr0_6 adc2_reqgt0 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr0_7 adc2_sr7 i (s) service request output 7 of adc2 reqtr0 - o selected trigger signal for source 0 (used as reqtrs for source 0) reqgt0 adc0_reqtr0_6 o selected gating signal for source 0 request source 1 reqgt1_0 trig10 i gpta reqgt1_1 trig12 i gpta reqgt1_2 trig14 i gpta reqgt1_3 pdout3 i eru reqgt1_4 req7 i (s) p7.5 reqgt1_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt1_6 adc1_sr7 i (s) adc2 trigger by adc1 reqgt1_7 0 i (s) not (yet) connected reqtr1_0 trig14 i gpta reqtr1_1 iout3 i eru reqtr1_2 trig16 i gpta reqtr1_3 adc_sr6 i common service request output 6 of adc module table 31-12 adc2 connections of digital part in TC1798 (cont?d) adc2 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-152 v1.1, 2011-03 adc, v1.5.2 reqtr1_4 req6 i (s) p7.4 reqtr1_5 0 i (s) not (yet) connected reqtr1_6 adc2_reqgt1 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr1_7 adc2_sr7 i (s) service request output 7 of adc2 reqtr1 - o selected trigger signal for source 1 (used as reqtrs for source 1) reqgt1 adc2_reqtr1_6 o selected gating signal for source 1 request source 2 reqgt2_0 trig10 i gpta reqgt2_1 trig12 i gpta reqgt2_2 trig14 i gpta reqgt2_3 pdout3 i eru reqgt2_4 req7 i (s) p7.5 reqgt2_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt2_6 adc1_sr7 i (s) adc2 trigger by adc1 reqgt2_7 0 i (s) not (yet) connected reqtr2_0 trig14 i gpta reqtr2_1 iout3 i eru reqtr2_2 trig16 i gpta reqtr2_3 adc_sr6 i common service request output 6 of adc module reqtr2_4 req6 i (s) p7.4 reqtr2_5 0 i (s) not (yet) connected reqtr2_6 adc2_reqgt2 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr2_7 adc2_sr7 i (s) service request output 7 of adc2 reqtr2 - o selected trigger signal for source 2 reqgt2 adc2_reqtr2_6 o selected gating signal for source 2 table 31-12 adc2 connections of digital part in TC1798 (cont?d) adc2 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-153 v1.1, 2011-03 adc, v1.5.2 request source 3 reqgt3_0 trig10 i gpta reqgt3_1 trig12 i gpta reqgt3_2 trig14 i gpta reqgt3_3 pdout2 i eru reqgt3_4 req6 i (s) p7.4 reqgt3_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt3_6 adc1_sr7 i (s) adc2 trigger by adc1 reqgt3_7 0 i (s) not (yet) connected reqtr3_0 trig15 i gpta reqtr3_1 iout2 i eru reqtr3_2 trig16 i gpta reqtr3_3 adc_sr6 i common service request output 6 of adc module reqtr3_4 req7 i (s) p7.5 reqtr3_5 0 i (s) not (yet) connected reqtr3_6 adc2_reqgt3 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr3_7 adc2_sr7 i (s) service request output 7 of adc2 reqtr3 - o selected trigger signal for source 3 (used as reqtrs for source 3) reqgt3 adc2_reqtr3_6 o selected gating signal for source 3 request source 4 reqgt4_0 trig10 i gpta reqgt4_1 trig12 i gpta reqgt4_2 trig14 i gpta reqgt4_3 pdout2 i eru reqgt4_4 req6 i (s) p7.4 table 31-12 adc2 connections of digital part in TC1798 (cont?d) adc2 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-154 v1.1, 2011-03 adc, v1.5.2 reqgt4_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt4_6 adc1_sr7 i (s) adc2 trigger by adc1 reqgt4_7 0 i (s) not (yet) connected reqtr4_0 trig15 i gpta reqtr4_1 iout2 i eru reqtr4_2 0 i not (yet) connected reqtr4_3 adc_sr6 i common service request output 6 of adc module reqtr4_4 req7 i (s) p7.5 reqtr4_5 0 i (s) not (yet) connected reqtr4_6 adc2_reqgt4 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr4_7 adc2_sr7 i (s) service request output 7 of adc2 reqtr4 - o selected trigger signal for source 4 (used as reqtrs for source 4) reqgt4 adc2_reqtr4_6 o selected gating signal for source 4 1) in case of input signals, the lines marked ?i? don?t contain synchronization stages, whereas the lines marked ?i (s)? contain synchronization stages (so they can directly handle asynchronous input signals). a signal connected to an input line marked ?i?has to be delivered from a block located in the same clock domain as the adc (the signal has to be synchr onous to the adc clock domain). table 31-12 adc2 connections of digital part in TC1798 (cont?d) adc2 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-155 v1.1, 2011-03 adc, v1.5.2 31.3.4.4 adc3 connections signals of the adc module referring to the kernel of adc3 are generally named with the prefix adc3_. the kernel adc3 has its own reference inputs adc4_v agnd and adc4_v aref . depending on the package, these lines can be available as independent pins for high pin count packages or can be combined with the corresponding inputs of the other kernels for low pin count packages. the respective voltage supply lines of all adc analog parts are connected together. table 31-13 adc3 connections to analog part in TC1798 adc3 signal of analog part from/to module or pin input or output can be used to/as v ddm v ddm i analog power supply 3.3v - 5v v dda v ddmf i analog power supply for comparator, connected to fadc 3.3v supply v ssm v ssm i analog power ground v aref v aref i positive analog reference, independent from other kernels v agnd v agnd i negative analog reference, combined with other kernels ch0 an48 i analog input channel 0 ch1 an49 i analog input channel 1 ch2 an50 i analog input channel 2 ch3 an51 i analog input channel 3 ch4 an52 i analog input channel 4 ch5 an53 i analog input channel 5 ch6 an54 i analog input channel 6 ch7 an55 i analog input channel 7 ch8 an56 i analog input channel 8 ch9 an57 i analog input channel 9 ch10 an58 i analog input channel 10 ch11 an59 i analog input channel 11 ch12 an60 i analog input channel 12 ch13 an61 i analog input channel 13 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-156 v1.1, 2011-03 adc, v1.5.2 the following table shows the digital connections of the adc3 kernel with other modules or pins in the TC1798 device. signals of the adc module referring to the kernel of adc3 are named with the prefix adc3_. ch14 an62 i analog input channel 14 ch15 an63 i analog input channel 15 table 31-14 adc3 connections of digital part in TC1798 adc3 signal of digital part from/to module or pin input 1) or output can be used to/as kernel signals arbcnt - o counting signal for arbiter rounds emuxtr - o trigger output for scanning the external multiplexer inputs emux0 - o control of external analog multiplexer(s) emux1 - emux2 - request source 0 reqgt0_0 trig10 i gpta reqgt0_1 trig12 i gpta reqgt0_2 trig14 i gpta reqgt0_3 pdout2 i eru reqgt0_4 req6 i (s) p7.4 reqgt0_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt0_6 adc2_sr7 i (s) adc3 trigger by adc2 reqgt0_7 0 i (s) not (yet) connected reqtr0_0 trig00 i gpta reqtr0_1 iout2 i eru reqtr0_2 0 i not (yet) connected table 31-13 adc3 connections to analog part in TC1798 (cont?d) adc3 signal of analog part from/to module or pin input or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-157 v1.1, 2011-03 adc, v1.5.2 reqtr0_3 adc_sr6 i common service request output 6 of adc module reqtr0_4 req7 i (s) p7.5 reqtr0_5 0 i (s) not (yet) connected reqtr0_6 adc3_reqgt0 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr0_7 adc3_sr7 i (s) service request output 7 of adc3 reqtr0 - o selected trigger signal for source 0 (used as reqtrs for source 0) reqgt0 adc0_reqtr0_6 o selected gating signal for source 0 request source 1 reqgt1_0 trig10 i gpta reqgt1_1 trig12 i gpta reqgt1_2 trig14 i gpta reqgt1_3 pdout3 i eru reqgt1_4 req7 i (s) p7.5 reqgt1_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt1_6 adc2_sr7 i (s) adc3 trigger by adc2 reqgt1_7 0 i (s) not (yet) connected reqtr1_0 trig14 i gpta reqtr1_1 iout3 i eru reqtr1_2 trig16 i gpta reqtr1_3 adc_sr6 i common service request output 6 of adc module reqtr1_4 req6 i (s) p7.4 reqtr1_5 0 i (s) not (yet) connected reqtr1_6 adc3_reqgt1 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr1_7 adc3_sr7 i (s) service request output 7 of adc2 table 31-14 adc3 connections of digital part in TC1798 (cont?d) adc3 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-158 v1.1, 2011-03 adc, v1.5.2 reqtr1 - o selected trigger signal for source 1 (used as reqtrs for source 1) reqgt1 adc3_reqtr1_6 o selected gating signal for source 1 request source 2 reqgt2_0 trig10 i gpta reqgt2_1 trig12 i gpta reqgt2_2 trig14 i gpta reqgt2_3 pdout3 i eru reqgt2_4 req7 i (s) p7.5 reqgt2_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt2_6 adc2_sr7 i (s) adc3 trigger by adc2 reqgt2_7 0 i (s) not (yet) connected reqtr2_0 trig14 i gpta reqtr2_1 iout3 i eru reqtr2_2 trig16 i gpta reqtr2_3 adc_sr6 i common service request output 6 of adc module reqtr2_4 req6 i (s) p7.4 reqtr2_5 0 i (s) not (yet) connected reqtr2_6 adc3_reqgt2 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr2_7 adc3_sr7 i (s) service request output 7 of adc3 reqtr2 - o selected trigger signal for source 2 reqgt2 adc3_reqtr2_6 o selected gating signal for source 2 request source 3 reqgt3_0 trig10 i gpta reqgt3_1 trig12 i gpta reqgt3_2 trig14 i gpta reqgt3_3 pdout2 i eru table 31-14 adc3 connections of digital part in TC1798 (cont?d) adc3 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-159 v1.1, 2011-03 adc, v1.5.2 reqgt3_4 req6 i (s) p7.4 reqgt3_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt3_6 adc2_sr7 i (s) adc3 trigger by adc2 reqgt3_7 0 i (s) not (yet) connected reqtr3_0 trig15 i gpta reqtr3_1 iout2 i eru reqtr3_2 trig16 i gpta reqtr3_3 adc_sr6 i common service request output 6 of adc module reqtr3_4 req7 i (s) p7.5 reqtr3_5 0 i (s) not (yet) connected reqtr3_6 adc3_reqgt3 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr3_7 adc3_sr7 i (s) service request output 7 of adc3 reqtr3 - o selected trigger signal for source 3 (used as reqtrs for source 3) reqgt3 adc3_reqtr3_6 o selected gating signal for source 3 request source 4 reqgt4_0 trig10 i gpta reqgt4_1 trig12 i gpta reqgt4_2 trig14 i gpta reqgt4_3 pdout2 i eru reqgt4_4 req6 i (s) p7.4 reqgt4_5 irq1 i (s) stm (do not use for gating, but for triggering) reqgt4_6 adc3_sr7 i (s) adc3 trigger by adc2 reqgt4_7 0 i (s) not (yet) connected reqtr4_0 trig15 i gpta reqtr4_1 iout2 i eru table 31-14 adc3 connections of digital part in TC1798 (cont?d) adc3 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-160 v1.1, 2011-03 adc, v1.5.2 reqtr4_2 0 i not (yet) connected reqtr4_3 adc_sr6 i common service request output 6 of adc module reqtr4_4 req7 i (s) p7.5 reqtr4_5 0 i (s) not (yet) connected reqtr4_6 adc3_reqgt4 i (s) extend input selection for triggering by using gating inputs (with engt = 0x) reqtr4_7 adc3_sr7 i (s) service request output 7 of adc3 reqtr4 - o selected trigger signal for source 4 (used as reqtrs for source 4) reqgt4 adc3_reqtr4_6 o selected gating signal for source 4 1) in case of input signals, the lines marked ?i? don?t contain synchronization stages, whereas the lines marked ?i (s)? contain synchronization stages (so they can directly handle asynchronous input signals). a signal connected to an input line marked ?i?has to be delivered from a block located in the same clock domain as the adc (the signal has to be synchr onous to the adc clock domain). table 31-14 adc3 connections of digital part in TC1798 (cont?d) adc3 signal of digital part from/to module or pin input 1) or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-161 v1.1, 2011-03 adc, v1.5.2 31.3.4.5 service request connections each adc kernel provides the service request output lines adcy_sr[7:0]. the adc module?s service request outputs adc_sr[11:0] are generated based on these lines according to the following table. if a line adcy_srx can be activated by more than one adc kernel, the corresponding request lines of the adc kernels are logical or- combinations of the kernel outputs. the wiring of the adc_srx signals to the dma channels is given in the dma chapter. the signal adcy_sr7 of each adc kernel is available as input for the request sources for this kernel. additionally, adc0_sr7 is connected to adc1 inputs, adc1_sr7 is connected to adc2 and adc2_sr7 is connected to adc3 inputs. the common signal adc_sr6 is available as input for the request sources of all kernels. table 31-15 adc module service request generation module service request output from adc0 kernel from adc1 kernel from adc2 kernel from adc3 kernel service request node adc_sr0 adc0_sr0 adc1_sr0 - - adc0_src0 adc_sr1 adc0_sr1 adc1_sr1 - - adc0_src1 adc_sr2 adc0_sr2 adc1_sr2 - - adc0_src2 adc_sr3 adc0_sr3 adc1_sr3 - - adc0_src3 adc_sr4 adc0_sr4 adc1_sr4 adc2_sr4 adc3_sr4 adc0_src4 adc_sr5 adc0_sr5 adc1_sr5 adc2_sr5 adc3_sr5 adc0_src5 adc_sr6 adc0_sr6 adc1_sr6 adc2_sr6 adc3_sr6 - adc_sr7 adc0_sr7 adc1_sr7 adc2_sr7 adc3_sr7 - adc_sr8 - - adc2_sr0 adc3_sr0 adc0_src6 adc_sr9 - - adc2_sr1 adc3_sr1 adc0_src7 adc_sr10 - - adc2_sr2 adc3_sr2 adc0_src8 adc_sr11 - - adc2_sr3 adc3_sr3 - www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-162 v1.1, 2011-03 adc, v1.5.2 31.3.4.6 kernel synchronization the independent adc kernels of the adc module can be synchronized to each other by selecting the corresponding connections. the table below shows the setting of the bits in the synchronization control re gisters in the adc to allow synchronization. a kernel can operate completely autonomously if it is c onfigured as master adc. a slave adc can be synchronized by the se lected master adc. note: a master adc can synch ronize several slave adcs, whereas a slave adc can only be synchronized by one master adc. table 31-16 synctr setting for kernel synchronization operating mode synctr. evalr3 synctr. evalr2 synctr. evalr1 synctr. stsel adc0 kernel (values to be programmed to adc0_synctr) no sync 0 0 0 00 b master of only adc1 00100 b master of only adc2 01000 b master of only adc3 10000 b master of adc1 and adc2 01100 b master of adc1 and adc3 10100 b master of adc2 and adc3 11000 b master of adc1, adc2 and adc3 11100 b single slave of adc1 00101 b adc0 and adc2 are slaves of adc1 01101 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-163 v1.1, 2011-03 adc, v1.5.2 adc0 and adc3 are slaves of adc1 10101 b adc0, adc2 and adc3 are slaves of adc1 11101 b single slave of adc2 01010 b adc0 and adc1 are slaves of adc2 01110 b adc0 and adc3 are slaves of adc2 11010 b adc0, adc1 and adc3 are slaves of adc2 11110 b single slave of adc3 10011 b adc0 and adc1 are slaves of adc3 10111 b adc0 and adc2 are slaves of adc3 11011 b adc0, adc1 and adc2 are slaves of adc3 11111 b adc1 kernel (values to be programmed to adc1_synctr) no sync 0 0 0 00 b master of only adc0 00100 b master of only adc2 01000 b table 31-16 synctr setting for kernel synchronization (cont?d) operating mode synctr. evalr3 synctr. evalr2 synctr. evalr1 synctr. stsel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-164 v1.1, 2011-03 adc, v1.5.2 master of only adc3 10000 b master of adc0 and adc2 01100 b master of adc1 and adc3 10100 b master of adc2 and adc3 11000 b master of adc1, adc2 and adc3 11100 b single slave of adc0 00101 b adc1 and adc2 are slaves of adc0 01101 b adc1 and adc3 are slaves of adc0 10101 b adc1, adc2 and adc3 are slaves of adc0 11101 b single slave of adc2 01010 b adc0 and adc1 are slaves of adc2 01110 b adc1 and adc3 are slaves of adc2 11010 b adc0, adc1 and adc3 are slaves of adc2 11110 b single slave of adc3 10011 b table 31-16 synctr setting for kernel synchronization (cont?d) operating mode synctr. evalr3 synctr. evalr2 synctr. evalr1 synctr. stsel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-165 v1.1, 2011-03 adc, v1.5.2 adc0 and adc1 are slaves of adc3 10111 b adc1 and adc2 are slaves of adc3 11011 b adc0, adc1 and adc2 are slaves of adc3 11111 b adc2 kernel (values to be programmed to adc2_synctr) no sync 0 0 0 00 b master of only adc0 00100 b master of only adc1 01000 b master of only adc3 10000 b master of adc0 and adc1 01100 b master of adc0 and adc3 10100 b master of adc1 and adc3 11000 b master of adc0, adc1 and adc3 11100 b single slave of adc0 00101 b adc1 and adc2 are slaves of adc0 01101 b table 31-16 synctr setting for kernel synchronization (cont?d) operating mode synctr. evalr3 synctr. evalr2 synctr. evalr1 synctr. stsel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-166 v1.1, 2011-03 adc, v1.5.2 adc2 and adc3 are slaves of adc0 10101 b adc1, adc2 and adc3 are slaves of adc0 11101 b single slave of adc1 01010 b adc0 and adc2 are slaves of adc1 01110 b adc2 and adc3 are slaves of adc1 11010 b adc0, adc2 and adc3 are slaves of adc1 11110 b single slave of adc3 10011 b adc0 and adc2 are slaves of adc3 10111 b adc1 and adc2 are slaves of adc3 11011 b adc0, adc1 and adc2 are slaves of adc3 11111 b adc3 kernel (values to be programmed to adc2_synctr) no sync 0 0 0 00 b master of only adc0 00100 b master of only adc1 01000 b table 31-16 synctr setting for kernel synchronization (cont?d) operating mode synctr. evalr3 synctr. evalr2 synctr. evalr1 synctr. stsel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-167 v1.1, 2011-03 adc, v1.5.2 master of only adc2 10000 b master of adc0 and adc1 01100 b master of adc0 and adc2 10100 b master of adc1 and adc2 11000 b master of adc0, adc1 and adc2 11100 b single slave of adc0 00101 b adc1 and adc3 are slaves of adc0 01101 b adc2 and adc3 are slaves of adc0 10101 b adc1, adc2 and adc3 are slaves of adc0 11101 b single slave of adc1 01010 b adc0 and adc3 are slaves of adc1 01110 b adc2 and adc3 are slaves of adc1 11010 b adc0, adc2 and adc3 are slaves of adc1 11110 b single slave of adc2 10011 b table 31-16 synctr setting for kernel synchronization (cont?d) operating mode synctr. evalr3 synctr. evalr2 synctr. evalr1 synctr. stsel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 analog to digital converter (adc) users manual 31-168 v1.1, 2011-03 adc, v1.5.2 ? adc0 and adc3 are slaves of adc2 10111 b adc1 and adc3 are slaves of adc2 11011 b adc0, adc1 and adc2 are slaves of adc2 11111 b table 31-16 synctr setting for kernel synchronization (cont?d) operating mode synctr. evalr3 synctr. evalr2 synctr. evalr1 synctr. stsel www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-1 v1.1, 2011-03 fadc, v2.6 32 fast analog to digi tal converter (fadc) the TC1798 contains a fast analog to digital converter (fadc) with differential input channels, thus allowing sampling of high frequency signals. for slow and mid-range frequency signals, an anti-aliasing filter by data reduction is implemented to avoid expensive external filters. ? functional description of the fadc kernel (see section 32.2 ) ? fadc kernel register descriptions (see section 32.3 ) ? TC1798 implementation-specific details and registers of the fadc module, including on-chip interconnections, service request control, address decoding, and clock control (see section 32.4 ) note: the fadc kernel register names described in section 32.3 are referenced in the TC1798 users manual by the module name prefix ?fadc_? for the fadc interface. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-2 v1.1, 2011-03 fadc, v2.6 32.1 fadc short description general features ? extreme fast conversion, 21 cycles of f fadc clock (262.5 ns @ f fadc = 80 mhz) ? 10-bit a/d conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) ? successive approximation conversion method ? each differential input channel can also be used as single-ended input ? offset calibration support for each channel ? programmable gain of 1, 2, 4, or 8 for each channel ? free-running (channel timers) or triggered conversion modes ? trigger and gating control for external signals ? built-in channel timers for internal triggering ? channel timer request periods independently selectable for each channel ? selectable, programmable digital anti-aliasing and data reduction filter block with four independent filter units figure 32-1 block diagram of the fadc module with 4 input channels srx mcb06065_m4 v fagnd v ddaf v ssaf v ddmf v faref v ssmf interrupt control ts[h:a] gs[h:a] clock control f fadc f clc a/d converter stage data reduction unit fain0p fain0n fain1p fain1n input structure channel trigger control channel timers srx dma a/d control v ddif input channel 0 input channel 1 fain2p fain2n fain3p fain3n input channel 2 input channel 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-3 v1.1, 2011-03 fadc, v2.6 as shown in figure 32-1 , the main fadc functional blocks are: ? an input structure containing the diff erential inputs and impedance control. ? an a/d converter stage responsible for the analog-to-digital conversion including an input multiplexer to select between the channel amplifiers ? a data reduction unit containing programmable anti-aliasing and data reduction filters ? a channel trigger control block determining the trigger and gating conditions for the fadc channels ? a channel timer for each channel to independently trigger the conversions ? an a/d control block responsible for the overall fadc functionality the analog block of the fadc in the TC1798 contains: ? a differential analog input stage for each input channel to select the input impedance (differential or single-ended measurement) and to decouple the fadc input signal from the pins. it is supplied by v ddif / v ssmf (3.3 v - 5 v). the v ddif supply does not appear as supply pin in the pin list, because it is internally connected to the v ddm supply of the adc that is sharing the fadc input pins. ? a channel amplifier with a settling time of about 5s if its configuration is changed by sw (changing between unused, differential, single-ended n, or single-ended p mode). it is supplied by v ddmf / v ssmf (3.3 v) . ? a 10-bit analog converter stage supplied by v ddaf / v ssaf (1.2 v)externally. the inputs for the fadc reference voltage (3.3 v max.) and the fadc reference ground v faref / v fagnd are connected to pins. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-4 v1.1, 2011-03 fadc, v2.6 figure 32-2 fadc input structure in TC1798 note: the analog voltages of the fadc have to be stable and noise-free to ensure a high quality of the conversions. mca06432_m4n fain0n fain0p analog input stages rp rn channel amplifier stages gain a/d a/d control conversion control converter stage chnr v ddaf v ssaf fain2n fain2p rp rn fain1n fain1p rp rn v ddif fain3n fain3p rp rn v ssmf v ssmf v ddmf v ssmf v ddmf v ssmf v ddmf v ssmf v ddmf www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-5 v1.1, 2011-03 fadc, v2.6 32.2 fadc kernel description the fadc kernel description covers the following items: ? analog input stage configurations (see section 32.2.1 ) ? conversion timing (see section 32.2.3 ) ? channel triggers (see section 32.2.4 ) ? channel timers (see section 32.2.5 ) ? conversion control (see section 32.2.6 ) ? data reduction unit (see section 32.2.7 ) ? neighbor channel trigger (see section 32.2.8 ) ? offset calibration (see section 32.2.9 ) ? interrupt generation (see section 32.2.10 ) 32.2.1 analog input stage configurations the analog input stage makes it possible to control the input impedance by selecting different configurations independently for each fadc channel x. these combinations are shown in figure 32-3 . figure 32-3 analog input stage configurations mca06452 v faref /2 rn configuration 1: single-ended measureme nt of v faref /2 - fainxn rp rp rn configuration 2: single-ended measureme nt of fainxp - v faref /2 configuration 3: differential measurement o f fainxp - fainxn configuration 0: channel amplifier is in power down mode n.c. v faref /2 - + - + - + - + f ainxn f ainxp f ainxp f ainxn f ainxn f ainxp high impedance high impedance f ainxp high impedance f ainxn high impedance www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-6 v1.1, 2011-03 fadc, v2.6 note: due to the temperature characteristics of offset and gain of the internal amplifiers a tue (total unadjusted error) cannot be specified. the input impedance for r p and r n is defined in the TC1798 data sheet. note: the analog input lines of the fadc can also be used as input lines for other adcs. if both (regular adc and fadc) are connected to the same pin at the same time, the input impedances of the analog inputs must be taken into account in order to minimize signal distortions and measurement errors. configuration 0: ch annel not used (acrx.enp = acrx.enn = 0) fadc channel x inputs fainxp and fainxn are in a high impedance state. the channel amplifier of the analog input stage is in power-down mode if both connected input channels are switched off for measurements. configuration 1: single-ended of fa inxn (acrx.enp = 0 and acrx.enn = 1) this configuration enables the single-ended measurement mode for v varef /2 - fainxn: the positive analog input fainxp is disconnected is in a high impedance state. the negative analog input fainxn is connected to the channel amplifier (input impedance is determined by r n ). the positive input of the channel amplifier is connected to v faref /2 (1.65 v with v faref = 3.3 v). if the voltage at the negative input fainxn varies, the fadc will deliver conversion results as follows (gain = 1 selected by acrx.gain = 00 b ): ? fainxn = 0 v: fadc conversion result is 768 ? fainxn = 3.3 v: fadc conversion result is 256 to cover the full range of the measurement result in this single-ended measurement mode, a gain of 2 must be selected (acrx.gain = 01 b ). with gain = 2, the fadc will deliver conversion results as follows: ? fainxn = 0 v: fadc conversion result is 1023 ? fainxn = 3.3 v: fadc conversion result is 0 the voltage at the disconnected positive analog input fainxp has no influence on the conversion result. configuration 2: single-ended of fainxp (acrx.enp = 1 and acrx.enn = 0) this configuration enables the single-ended measurement mode for fainxp - v varef /2. the negative analog input fainxn is disconnected and in a high impedance state. the positive analog input fainxp is connected to the channel amplifier (input impedance is determined by r p ). the negative input of the channel amplifier is connected to v faref /2 (1.65 v with v faref = 3.3 v). if the voltage at the positive input fainxp varies, the fadc will deliver conversion results as follows (gain = 1 selected by acrx.gain = 00 b ): ? fainxp = 0 v: fadc conversion result is 256 ? fainxp = 3.3 v: fadc conversion result is 768 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-7 v1.1, 2011-03 fadc, v2.6 to cover the full range of the measurement result in this single-ended measurement mode, a gain of 2 must be selected (acrx.gain = 01 b ). with gain = 2, the fadc will deliver conversion results as follows: ? fainxp = 0 v: fadc conversion result is 0 ? fainxp = 3.3 v: fadc conversion result is 1023 the voltage at the disconnected negative analog input fainxn has no influence on the conversion result. configuration 3: differential measurement (acrx.enp = acrx.enn = 1) this configuration enables the differenti al measurement mode for fainxp - fainxn. both analog inputs, fainx.n and fainxp, are connected to the channel amplifier inputs. their impedances are determined by r n and r p . the full measurement range is available. 32.2.2 result representation the conversion result for fadc channel x is given by the following equations: (32.1) the absolute value of the result v mx is limited to v faref . the mapping of the conversion result v mx to the result rchx.adres is as follows: for single-ended measurements, the following values are taken into account: ?if enp x = 0 then v fainxp = v farefm ?if enn x = 0 then v fainxn = v farefm note: in multiplexer test mode (gcr.muxtm = 1), the channel amplifiers are disconnected from the converter stage. the measured conversion result in multiplexer test mode is 512 plus/minus the offset of the converter stage. 32.2.3 conversion timing the conversion time of the fadc is determined by the frequency of clock f fadc . the conversion time including sampling, converting, and storing of the conversion result takes 21 periods of f fadc . v mx = - v faref leads to rchx.adres = 0 v mx = 0 leads to rchx.adres = 512 v mx = + v faref leads to rchx.adres = 1023 conversion result v mx gain x v fainxp v farefm ? () v farefm v fainxn ? () + () = with v farefm v fagnd v faref v fagnd ? () 2 ? + = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-8 v1.1, 2011-03 fadc, v2.6 32.2.4 channel triggers as shown figure 32-4 , the trigger behavior of an fadc channel x is determined by its channel x trigger control logic. an fadc channel x can be triggered by three trigger sources: ? external trigger source input signal, se lectable from an input vector ts[h:a] ? internal channel x timer trigger signal ? internal neighbor channel trigger signal if one of these trigger sources is select ed, becomes active, and the gating logic is programmed to enable trigger signals (signal echtimx set), the conversion request flag crfx becomes set indicating a valid request for fadc channel x. the gating source input and gating mode selection logic generate an enable signal for channel x timer that determines whether any of the three conversion trigger signal sources is allowed to set the channel x conversion request flag crfx. it can select an input signal from the input vector gs[h:a]. the control logic does the following tasks, independently in each of the fadc channels: ? gating source input selection (cfgrx.gsel) ? gating mode selection (cfgrx.gm) ? trigger source input selection (cfgrx.tsel) ? trigger mode selection (cfgrx.tm) ? channel timer request generation ? conversion request flag set/clear www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-9 v1.1, 2011-03 fadc, v2.6 figure 32-4 channel trigger control logic table 32-1 describes the possible gating modes (enabled, disabled, active gating source input polarity) of an fadc channel. table 32-1 gating modes cfgrx.gm gating mode 00 b conversion requests are disabled and channel timer is stopped. bit crsr.crfx never becomes set (by hardware). 01 b conversion requests and channel timer are always enabled. bit crsr.crfx becomes set by hardware with each active trigger signal. 10 b when gating source input gsn = 1 (as selected by cfgrx.gsel), the channel timer is enabled and the conversion request bit crsr.crfx becomes set by hardware with each active trigger signal. 11 b when gating source input gsn = 0 (as selected by cfgrx.gsel), the channel timer is enabled and the conversion request bit crsr.crfx becomes set by hardware with each active trigger signal. mca06433_m gsel cfgrx gating mode selection gm cfgrx & tsel cfgrx edge detection unit tm cfgrx channel x conversion trigger channel x timer enable trigger gs[h:a] ts[h:a] set crfx crsr channel x trigger control to other fadc channels neighbor channel trigger nctx rcrfx fmr scrfx set clear conversion started clear echtimx 3 2 3 2 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-10 v1.1, 2011-03 fadc, v2.6 an edge detection unit determines which edge of the trigger source input signal (as selected by cfgrx.tsel) is generating a conversion request trigger signal. rising, falling or both edges can be selected for trigger signal generation. the conversion request flag crsr.crfx is cleared by hardware when the conversion of channel x is started. bit crfx can be also set or cleared by software via bits in the flag modification register fmr. writing a 1 to fmr.scrf sets crfx. writing a 1 to fmr.rcrf clears crfx (independently of fmr.scrf). table 32-2 trigger modes cfgrx.tm trigger mode 00 b no trigger signal generated. 01 b a conversion request trigger signal is generated on a rising edge of trigger source input tsn (selected by cfgrx.tsel). 10 b a conversion request trigger signal is generated on a falling edge of trigger source input tsn (selected by cfgrx.tsel). 11 b a conversion request trigger signal is generated on a rising or falling edge of trigger source input tsn (selected by cfgrx.tsel). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-11 v1.1, 2011-03 fadc, v2.6 32.2.5 channel timer each of the fadc channels contains an 8-bit channel timer that can be used to generate periodic conversion requests. the channel timer is built up by a decrementing counter that is reloaded with a programmable value. when the channel timer reaches zero while running, a channel timer trigger event is generated and the channel timer is reloaded with the reload value cfgrx.ctrel when the requested conversion is started. with the start of the a/d conversion, request bit crsr.crfx is cleared. note that the request flag is set by a timer trigger event only if the gating condition is met (signal echtimx in figure 32-4 set). a clock divider, fed by the module clock f fadc and common for all channel timers, generates several clock signals with different periods. bit field cfgrx.ctf selects whether or not the channel x timer clock f ctx is enabled and, if enabled, determines the frequency of channel x timer input clock f ctx . while the channel timer is disabled (cfgrx.ctm = 00 b ) or if the gating condition is not met (gating line echtimx delivers 0), the channel x timer value is set to 04 h . this value ensures a fast conversion trigger afte r the gating becomes enabled, but prevents unintended conversion starts in case of short pulses (bouncing) at the gating input. figure 32-5 channel timer block diagram due to the common divider, the first event at the trigger output of chtimx after the start has a maximum jitter of one clock cycle of the selected channel x timer clock f ctx . a channel x timer input clock pulse at f ctx is ignored if it occurs in the f fadc clock cycle directly after the channel x timer has reached 0. if there is at least one f fadc clock cycle between two channel x timer input clock pulses, all channel x timer input clock pulses mca06434 channel timer channel conversio n started and chann el timer is running ctf cfgrx ctrel channel x timer trigger event channel x timer enable echtimx ctm 8 run control channel x timer to other channel timers 4 16 64 256 1024 f fadc clock divider for channel timers f ctx 0 3 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-12 v1.1, 2011-03 fadc, v2.6 are taken into account. this leads to a channel x timer reload value (cfgrx.ctrel) whose definition depends on the ratio of f fadc / f ctx : in case of a f fadc / f ctx ratio between 1 and 2, a mixture of both divide factor definitions occurs depending on the divider ratio as programmed by the fractional divider value. therefore, it is recommended that this ratio should not be used. 32.2.6 conversion control a conversion is started when at least one of the crsr.crfx bits is set. a running conversion cannot be aborted and is indicated by the busy flag crsr.bsyx set. the corresponding bit crsr.crfx is reset by hardware when the conversion starts. 32.2.6.1 static channel priority if more than one conversion request flag crsr.crfx (x = 0-3) is set, the channels are converted according to a priority scheme as defined by the bit field gcr.crprio (without respecting the status of the current filter sequences). 32.2.6.2 dynamic priority assignment if dynamic priority assignment is enabl ed (gcr.dpaen = 1), a cha nnel that has the only active gate signal (signal echtimx in figure 32-4 ) among the four channels gets the highest priority (gcr.crprio is set to the number of the channel). if more than one channel gating signal is active, gcr.crprio is not changed automatically. in this case, it can be changed by software. f fadc / f ctx = 1 channel x timer divide factor = ctrel + 2 1 < f fadc / f ctx < 2 not recommended to be used! 2 f fadc / f ctx channel x timer divide factor = ctrel + 1 table 32-3 static chan nel request priority priority gcr.crprio 00 b 01 b 10 b 11 b high low channel 0 channel 1 channel 2 channel 3 channel 1 channel 2 channel 3 channel 0 channel 2 channel 3 channel 0 channel 1 channel 3 channel 0 channel 1 channel 2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-13 v1.1, 2011-03 fadc, v2.6 32.2.6.3 clock generation the fadc module is provided with two clock signals: f clc and f fadc . clock f clc is used inside the fadc kernel for control purposes such as clocking of control logic, register operations, trigger detection , or filter calculation. the clock rate of f fadc is programmable. it is used inside the fadc kernel for the channel timers and other internal timings. 32.2.6.4 suspend mode behavior when a suspend/idle mode request is generated for the fadc module via the fractional divider, a currently running conversion is co mpletely finished (not aborted) and, if selected, a filter calculation still takes place. thereafter, no new conversion will be started and the state of the fadc module is frozen until the suspend/idle mode request is released again. if enabled, the related interrupts are signaled. if suspend mode is needed, it is recommended to use to the suspend control by the fractional divider and not by the clc register. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-14 v1.1, 2011-03 fadc, v2.6 32.2.6.5 alias feature the alias feature is mainly meant for emulation purposes and does not need to be used in standard applications. it allows a reassignment of the channel to be converted with respect to the channel number that has been requested for conversion. this feature can be used to redirect conversion requests to other input channels without changing the request sw. for example, a sw from tc1766 (with only the two input channels 0 and 1), can be adapted to either channels 0 and 1 (compatibility to older products) or to channels 2 and 3 instead. especially when emulating several different devices with a common emulation chip, the channel reassignment allows compatible sw usage with different channel wiring to pins. the setting of the input stages (incl. calibrat ion information) is defined by register acrx of the input channel that is requested (no al ias-mapping). i.e. the acrx register of the actually converted channel is used as it is permanently conntected to its channel. the result handling (incl. interrupts) also refers to the requested channel number. the alias feature is only taken into account as channel number for the conversion start. figure 32-6 alias feature f adc_ali as requested channel number input stages and channel amplifiers conversion trigger generation 0 alias register 1 2 3 conversion control fadc input channels a/d converter stage selected channel conversion start alias2 alias1 alias0 alias3 conversion request channel number to be converted chnr channel settings (enn, enp, gain, calibration data) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-15 v1.1, 2011-03 fadc, v2.6 32.2.7 data reduction unit a data reduction unit is implemented in the fadc that operates as anti-aliasing filter. this unit allows the number of conversion data requests that are issued to the cpu or other bus masters to be reduced by adding multiple conversion results according to a certain algorithm and presenting it to the cpu or other bus masters with a reduced conversion request rate. figure 32-7 TC1798 fadc filter blocks the data reduction unit contains four filter blocks. each filter block allows selection of its input data source. the input data sources are the conversion result registers of the four a/d converter channels. filter blocks can also be concatenated (blo ck 0 and block 1 can be concatenated, same for block 2 and block 3). when the result of a filter operation is stored in one of the final result registers, a service request can be generated. each filter block basically contains adder logic and intermediate storage registers that allow support for typical digital filter operations such as moving average calculations with intermediate results. mcb06435_m4 rch0 conversion result registers rch1 filter block 1 filter block 0 frr0 frr1 final result registers 0 rch2 rch3 filter block 3 filter block 2 frr2 frr3 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-16 v1.1, 2011-03 fadc, v2.6 32.2.7.1 filter block structure the filter block consists of an adder and several result registers for calculating filter output data from the filter input data. for filter n, the current result register crrn is used for adding up conversion results. after a programmable number of conversion results have been added, the contents of crrn are stored as intermediate result in the intermediate result register irr1n. the thr ee intermediate result registers operate like a pipeline. before irr1n is overwritten, irr2n is transferred to irr3n, and irr1n is transferred to irr2n. the final result register frrn stores the sum that is built by the contents of the current result register and the intermediate result registers. all result registers of the filter block can be read at any time. please note that only one intermediate result register is available in filter block 1 (irr11) and in filter block 3 (irr13). figure 32-8 filter block structure 32.2.7.2 filter block operation a filter block can be used for data-reduction or anti-aliasing filtering of the conversion results (n indicates the number of the filter block). it performs a combination of data reduction by adding and a moving average operation. ? a continuous a/d conversion is running on channel x. ? the filter input selection is set to channel x (fcrn.insel = 100 b +x). ? the addition length is controlled by fcrn.addl defining how many conversion results are added to build one interm ediate result (intermediate cycle). mca06436_m filter block n frrn crrn irr1n irr2n irr3n 1) 1) 1) registers are not available in filter blocks 1 and 3 filter output value filter input value sfrrn 2) 2) registers available only in filter blocks 1 and 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-17 v1.1, 2011-03 fadc, v2.6 ? the moving average length is controlled by fcrn.mavl defining how many intermediate results are taken into account for a moving average to build the final result (final result cycle). intermediate result calculation each incoming conversion result is added to the content of crrn until the programmed number of conversion results have been summed up in crrn. at that point, crrn contains a new intermediate result and the calculation of the next final result value by moving average is started. then crrn is cleared automatically after the final result cycle to be prepared for the first conversion re sult for the next intermediate cycle. before the filter operation of continuous conversion results of channel x is started, the filter block n has to be cleared (writing gcr.rstfn = 1) after programming the filter control bit fields. final result calculation the calculation of a final re sult is started when an inte rmediate cycle has been finished. the new intermediate result (stored in crrn) and the contents of the intermediate registers irrnx are added to build the final result in frrn. the number of intermediate results taking part in the moving average operation to build the final result is programmable, the maximum is given by: ? filter block 0: frr0 := crr0 + irr10 + irr20 + irr30 ? filter block 1: frr1 := crr1 + irr11 ? filter block 2: frr2 := crr2 + irr12 + irr22 + irr32 ? filter block 3: frr3 := crr3 + irr13 at the end of the final result cycle, the contents of irr2n are transferred into irr3n, then the contents of irr1n into irr2n, then the contents of crrn into irr10 (for filter blocks 0 and 2). the former contents of irr3n are lost. bit field fcrn.mavl determines the number of intermediate results that are used for the final result calculation. for filter blocks 1 and 3, only two bit comb inations are valid and the intermediate result registers irr2n and 3n are not available and handled as if they were 0. each update of a result register frrn with a new final result value generates a filter block n service request. 32.2.7.3 filter concatenation filter block 1 and 3 allow filter concatenation to support more filter stages. filter 1 can be programmed to use the resu lt value of filter 0, similar for filter blocks 2 and 3. filter blocks 0 and 2 operate with the following parameters: ? intermediate results are calculated based on the conversion results of one of the input channels (fcrn.insel = 1xx b ). www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-18 v1.1, 2011-03 fadc, v2.6 ? an intermediate cycle can contain a maximum of 8 conversion results. ? a final result cycle can contain a maximum of 4 intermediate results. filter blocks 1 and 3 operate with the following parameters: ? intermediate results are based on the final results of filter block 0 (for filter block 1) and of filter block 2 (for filter block 3) . filter block concatenation is enabled by fcrn.insel = 010 b . ? an intermediate cycle can contain a maximum of 8 conversion results. ? a final result cycle can contain a maximum of 2 intermediate results. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-19 v1.1, 2011-03 fadc, v2.6 32.2.7.4 width of result registers the additions executed in filter 0 and filter 1 together with the possible maximum values of the filter parameters determine the width of the current, intermediate, and final result registers (same for filter blocks 2 and 3). in addition to the final result registers frr1 and frr3 with 20 bit width, another view is available that is shifted by 5 bit positions to the right, given by registers sfrr1 and sfrr3. this allows a representation of the data within a 16 bit word for further digital data handling. table 32-4 data width of result registers register long name register short name result width filter 0 current result register crr0 13-bit filter 0 intermediate result register 1 irr10 filter 0 intermediate result register 2 irr20 filter 0 intermediate result register 3 irr30 filter 0 final result register frr0 15-bit filter 1 current result register crr1 18-bit filter 1 intermediate result register 1 irr11 filter 1 final result register frr1 20-bit filter 1 shifted final result register sfrr1 15-bit filter 2 current result register crr2 13-bit filter 2 intermediate result register 1 irr12 filter 2 intermediate result register 2 irr22 filter 2 intermediate result register 3 irr32 filter 2 final result register frr2 15-bit filter 3 current result register crr3 18-bit filter 3 intermediate result register 1 irr13 filter 3 final result register frr3 20-bit filter 3 shifted final result register sfrr3 15-bit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-20 v1.1, 2011-03 fadc, v2.6 32.2.8 neighbor channel trigger the neighbor channel trigger feature allows the concatenation of channel conversions. this means that the start of a conversion for one channel can generate multiple channel trigger requests for the other three channels. a channel conversion request flag of a neighbor channel becomes only set by a neig hbor channel trigger request if the gating condition (gating mode selection output at high level in figure 32-4 ) in the corresponding neighbor channel is valid. all neighbor channel trigger enable bits enxy are located in the neighbor channel trigger register nctr. index ?x? indicates the number of the channel that starts a neighbor channel trigger. index ?y? is the numbe r of the neighbor channel to be triggered. figure 32-9 neighbor channel trigger fadc_nct neighbor channel trigger signal nct0 start of channel 3 2 1 0 en10 nctr en20 en30 en01 en21 en31 > 1 > 1 en02 nctr en12 en32 en03 en13 en23 > 1 > 1 neighbor channel trigger signal nct1 neighbor channel trigger signal nct2 neighbor channel trigger signal nct3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-21 v1.1, 2011-03 fadc, v2.6 32.2.9 calibration the calibration is used to minimize the error of the fadc conversion results independently for each channel. the output of each channel amplifier can be adjusted to deliver a minimum offset value for zero input voltage difference. the channel which is calibrated is selected by gcr.calch. the calibration mode is selected by gcr.calmode. during the calibration process of a channel, the other channels can be used in normal conversion mode without restrictions. figure 32-10 analog input and channel amplifier configuration at calibration figure 32-10 shows the channel amplifier configuration as well as the analog input pin configurations that are selected during offset and gain calibration. note that in the calibration modes, the impedance of the analog inputs depends on the settings of the enn and enp bits of the corresponding channel x analog control register acrx. mc_fadc_cfg_ calibration fainxp rp fainxn rn analog input configuration during offset calibration v faref /2 fainxp fainxn high impedance high impedance acrx.enn = acrx.enp = 1 other combinations than acrx.enn = acrx.enp = 1 offset calibration (gcr.calmode = 01 b ) channel amplifier v faref /2 - + www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-22 v1.1, 2011-03 fadc, v2.6 32.2.9.1 offset calibration when offset calibration is selected (gcr.calmode = 01 b ), the channel amplifier inputs of the selected channel are both connected to v faref /2. after enabling a channel amplifier for offset calibration, a delay of minimum 5 s must be respected before starting a conversion for this channel. the conversi on result must be compared by software with the tolerated offset value (a conversion result with zero offset is equal to 512). if the conversion result exceeds the tolerated range, bit field acrx.caloff (with x specifying the calibrated channel) can be adjusted an d a new conversion can be started. the calibration process is finished when the conversion result is in the tolerated offset range. after switching back to normal mode for channel x, a delay of minimum 5 s must be respected before starting a new conversion for this channel. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-23 v1.1, 2011-03 fadc, v2.6 32.2.10 interrupt generation a flexible service request control structure is implemented in the fadc. the fadc provides the channel conversion request so urces and the filter block request sources, that can be programmed to generate one of fo ur service request output signals sr[3:0]. the service request compressor also makes it possible to assign more than one service request source to one service request output. figure 32-11 service request configuration all service requests are controlled by an identical control logic. this control logic as shown in figure 32-12 provides the following functionality: ? service request flag ? set/clear request flag control bits ? service request enable bit ? service request node pointer figure 32-12 service request control logic mca06441_m channel conversion requests service request compressor filter block 0 calculation finished channel 2 conversion finished sr0 sr1 sr2 sr3 filter block requests channel 3 conversion finished filter block 1 calculation finished filter block 2 calculation finished filter block 3 calculation finished channel 0 conversion finished channel 1 conversion finished mca06442 request flag crsr set s ervice request t rigger signal reset enable bit cfgrx/fcrn reset req. flag bit fmr set req. flag bit 01 10 11 00 node pointer cfgrx/fcrn to sr0 or-ga te to sr1 or-ga te to sr2 or-ga te to sr3 or-ga te 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-24 v1.1, 2011-03 fadc, v2.6 the request flag is always set by hardware when the corresponding request event occurs. it can also be set or cleared by software when writing a 1 to the corresponding set/clear request flag bit in the flag modification register fmr. finally, a service request event is directed to one of the four service request output lines sr[3:0] when the corresponding service request enable bit ien is set. the service request node pointer determines which of the service request output lines sr[3:0] becomes activated. table 32-5 lists the six service request sources of the fadc module with its related control and status flags/bits. in the service request compressor logic shown in figure 32-13 , the inputs of one srx or-gate are connected to all demultiplexer out puts with identical inp node pointer value. therefore, one service request event can be only assigned to one of the four service request outputs, but one service request outp ut can be used by multiple service request events. figure 32-13 service request compressor logic table 32-5 service request control/status bits/flags service request source request flag enable bit set request bit / clear request bit service request node pointer channel x conversion request (x = 0-3) crsr.irqx cfgrx.ien fmr.sirqx / fmr.rirqx cfgrx.inp filter block n request (n = 0-3) crsr.irqfn fcrn.ien fmr.sirqfn / fmr.rirqfn fcrn.inp mca06443_m inp cfgrx service request output sr0 01 10 11 00 channel x request event (x = 0-3) . . . . . . . to sr1 or-gate to sr2 or-gate sr0 or-gate service request output sr3 sr3 or-gate inp fcrx 01 10 11 00 filter block n request event (n = 0-3) to sr1 or-gate to sr2 or-gate . . . . . . . 1 1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-25 v1.1, 2011-03 fadc, v2.6 depending on the implementation of the fadc module in a specific micro controller, the service request output signals sr[3:0] can either be connected to an interrupt node (controlled by a service request control register) or can be used as dma request input of a dma controller unit. the TC1798 specific request output connections are described in the fadc implementation chapter. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-26 v1.1, 2011-03 fadc, v2.6 32.3 fadc register description this section describes the kernel registers of the fadc module. all fadc kernel register names described in this section will be referenced in other parts of the TC1798 users manual by the module name prefix ?fadc_?. all registers can accessed with 8-bit, 16-bit, or 32-bit read or write operations. figure 32-14 fadc kernel registers access rights within the address range of an fadc kernel: ? read access to defined register addresses: u, sv ? write access to defined re gister addresses: u, sv ? accesses to empty addresses: reserved, be table 32-6 register overview of fadc short name description offset addr. 1) access mode reset description see read write fadc module registers clc clock control register 000 h u, sv sv, e class 3 page 32-30 fdr fractional divider register 00c h u, sv sv, e class 3 page 32-31 mca06444_m4 crsr fmr fcr0 channel registers nctr system registers gcr cfgr0 acr0 filter registers fcr1 rch0 crr0 crr1 irr10 irr11 irr20 irr30 frr0 frr1 cfgr1 acr1 rch1 cfgr2 acr2 rch2 cfgr3 acr3 rch3 sfrr1 fcr2 fcr3 crr2 crr3 irr12 irr13 irr22 irr32 frr2 frr3 sfrr3 clc fdr srcx global registers alr www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-27 v1.1, 2011-03 fadc, v2.6 id module identification register 008 h u, sv u, sv class 3 page 32-33 srcx x=0 - 3 service request control registers 0fc h - x * 4 h u, sv u, sv class 3 page 32-34 global registers crsr conversion request status register 010 h u, sv u, sv class 3 page 32-35 fmr flag modification register 014 h u, sv u, sv class 3 page 32-37 nctr neighbor channel trigger register 018 h u, sv u, sv class 3 page 32-39 gcr global control register 01c h u, sv u, sv class 3 page 32-42 reserved no be, has to be written with 0 050 h alr alias register 054 h u, sv sv, e class 3 page 32-46 channel registers cfgrx channel x configuration register (x = 0-3) 020 h + (x 4) u, sv u, sv class 3 page 32-48 acrx channel x analog control reg. (x = 0-3) 030 h + (x 4) u, sv u, sv class 3 page 32-52 rchx channel x conversion result register (x = 0-3) 040 h + (x 4) u, sv u, sv class 3 page 32-54 filter 0 registers fcr0 filter 0 control register 060 h u, sv u, sv class 3 page 32-55 crr0 filter 0 current result register 064 h u, sv u, sv class 3 page 32-58 table 32-6 register overview of fadc short name description offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-28 v1.1, 2011-03 fadc, v2.6 irr10 filter 0 intermediate result register 1 068 h u, sv u, sv class 3 page 32-60 irr20 filter 0 intermediate result register 2 06c h u, sv u, sv class 3 page 32-60 irr30 filter 0 intermediate result register 3 070 h u, sv u, sv class 3 page 32-60 frr0 filter 0 final result register 074 h u, sv u, sv class 3 page 32-62 filter 1 registers fcr1 filter 1 control register 080 h u, sv u, sv class 3 page 32-55 crr1 filter 1 current result register 084 h u, sv u, sv class 3 page 32-58 irr11 filter 1 intermediate result register 1 088 h u, sv u, sv class 3 page 32-60 frr1 filter 1 final result register 094 h u, sv u, sv class 3 page 32-62 sfrr1 filter 1 shifted final result register 098 h u, sv u, sv class 3 page 32-63 filter 2 registers fcr2 filter 2 control register 0a0 h u, sv u, sv class 3 page 32-55 crr2 filter 2 current result register 0a4 h u, sv u, sv class 3 page 32-58 irr12 filter 2 intermediate result register 1 0a8 h u, sv u, sv class 3 page 32-60 irr22 filter 2 intermediate result register 2 0ac h u, sv u, sv class 3 page 32-60 irr32 filter 2 intermediate result register 3 0b0 h u, sv u, sv class 3 page 32-60 table 32-6 register overview of fadc short name description offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-29 v1.1, 2011-03 fadc, v2.6 frr2 filter 2 final result register 0b4 h u, sv u, sv class 3 page 32-62 filter 3 registers fcr3 filter 3 control register 0c0 h u, sv u, sv class 3 page 32-55 crr3 filter 3 current result register 0c4 h u, sv u, sv class 3 page 32-58 irr13 filter 3 intermediate result register 1 0c8 h u, sv u, sv class 3 page 32-60 frr3 filter 3 final result register 0d4 h u, sv u, sv class 3 page 32-62 sfrr3 filter 3 shifted final result register 0d8 h u, sv u, sv class 3 page 32-63 1) the absolute register addres s is calculated as follows: module base address + offset address (shown in this column) table 32-6 register overview of fadc short name description offset addr. 1) access mode reset description see read write www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-30 v1.1, 2011-03 fadc, v2.6 32.3.1 system registers 32.3.1.1 clock control register the clock control register allows the progra mmer to control (enable/disable) the clock signal f clc under certain conditions. after a reset operation, the fadc module is disabled and its module clock signal f clc is switched off. clc clock control register (000 h ) reset value: 0000 0003 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 fs oe sb we e dis sp en dis s dis r field bits type description disr 0rw module disable request bit used for enable/disable control of the module. diss 1r module disable status bit bit indicates the current status of the module. spen 2rw module suspend enable for ocds used to enable the suspend mode. edis 3rw sleep mode en able control used to control module?s sleep mode. sbwe 4w module suspend bit write enable for ocds determines whether spen and fsoe are write- protected. fsoe 5rw fast switch off enable used for fast clock swit ch off in suspend mode. 0 [31:6] r reserved read as 0. should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-31 v1.1, 2011-03 fadc, v2.6 32.3.1.2 fractional divider register the fractional divider register allows the programmer to control the clock rate of the module clock f fadc . fdr fractional divider register (00c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dis clk en hw sus req sus ack 0result rwh rw rh rh r rh 1514131211109876543210 dm sc sm fdis step rw rw rw rw rw field bits type description step [9:0] rw step value reload or addition value for result. fdis 10 rw freeze disable this bit controls the freeze function for this module. 0 b module operates on co rrected clock, with reduced modulation jitter 1 b module operates on uncorrected clock with full modulation jitter sm 11 rw suspend mode sm selects between granted or immediate suspend mode. sc [13:12] rw suspend control this bit field determines the behavior of the fractional divider in suspend mode. dm [15:14] rw divider mode this bit field selects normal divider mode, fractional divider mode, and off-state. result [25:16] rh result value bit field for the addition result. susack 28 rh suspend mode acknowledge indicates state of spndack signal. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-32 v1.1, 2011-03 fadc, v2.6 susreq 29 rh suspend mode request indicates state of spnd signal. enhw 30 rw enable hardware clock control controls operation of ecen input and disclk bit. should be always written with 0. disclk 31 rwh disable clock hardware controlled disable for f fadc signal. 0 10, [27:26] r reserved read as 0. should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-33 v1.1, 2011-03 fadc, v2.6 32.3.1.3 module identification register the register table can be found on page 32-26 . id module identification register (008 h ) reset value: 0027 c000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mod_number r 1514131211109876543210 mod_type mod_rev rr field bits type description mod_rev [7:0] r module revision this bit field indicates the revision number of the module implementation (depending on the design step). the given value of 00 h is a placeholder for the actual number. bits [3:0] refer to the version of the digital part and bits [7:4] indicate the version of the analog part (anid). mod_type [15:8] r module type mod_number [31:16] r module number www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-34 v1.1, 2011-03 fadc, v2.6 32.3.1.4 service request control registers each of the interrupts of the fadc is controlled by a service request control register. srcx (x = 0-3) service request control register x (0fc h - x*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 set r clr r srr sre 0 tos 0 srpn w w rh rw r rw r rw field bits type description srpn [7:0] rw service request priority number tos 10 rw type of service control sre 12 rw service request enable srr 13 rh service request flag clrr 14 w request clear bit setr 15 w request set bit 0 [9:8], 11, [31:16] r reserved read as 0. should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-35 v1.1, 2011-03 fadc, v2.6 32.3.2 global registers 32.3.2.1 conversion re quest status register the conversion request status register crsr contains the flags for monitoring the state of pending conversions and the interrupt request flags. crsr conversion request status register (010 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 irq f3 irq f2 irq f1 irq f0 irq 3 irq 2 irq 1 irq 0 r rhrhrhrhrhrhrhrh 1514131211109876543210 0 bsy 3 bsy 2 bsy 1 bsy 0 0 crf 3 crf 2 crf 1 crf 0 r rhrhrhrh r rhrhrhrh field bits type description crfx (x = 0-3) xrh conversion request flag this bit monitors whether a conversion request is pending for channel x. crfx is set by hardware when a trigger event is detected while the gating condition delivers 1. crfx is automatically cleared by hardware when a conversion of the channel x is started. 0 b a conversion of channel x has not been requested. 1 b a conversion of channel x has been requested. bits crfx can be set/cleared by software via bits fmr.rcrfx and fmr.scrfx. if a set and a clear condition for crfx occur simultaneously (generat ed by hardware and/or software), the clear condition always wins. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-36 v1.1, 2011-03 fadc, v2.6 bsyx (x = 0-3) 8 + x rh busy flag this bit indicates if a conversion is currently running for channel x. 0 b a conversion is not running. 1 b a conversion is running. irqx (x = 0-3) 16 + x rh interrupt request flag this bit indicates that a conversion of channel x has been finished since it has been cleared by software. interrupt requests can also be generated while irqx is still set. an interrupt can only be generated when cfgrx.ien = 1. 0 b a conversion has not been finished. 1 b a conversion has been finished. bits irqx can be set/cleared by software via bits fmr.sirqx and fmr.rirqx. irqfn (n = 0-3) 20 + n rh interrupt request fl ag for filter n this bit indicates that a filter sequence of filter n has been finished (new final result is available) since it has been cleared by software. interrupt requests can also be generated while irq is still set. an interrupt can only be generated when fcrn.ien = 1. 0 b a filter sequence has not been finished. 1 b a filter sequence has been finished. bits irqfn can be set/clear ed by software via bits fmr.sirqfn and fmr.rirqfn. 0 [7:4], [15:12], 24[31:2 4] r reserved read as 0. should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-37 v1.1, 2011-03 fadc, v2.6 32.3.2.2 flag modification register the bits of the flag modification register fmr allow the flags of the conversion request status register to be set/cleared by software. if a clear and set request are issued at the same time, the target flag is cleared. it is recommended to avoid writing both bit positions (for set and for clear) of the same target bit with 1 within the same write operation. fmr flag modificatio n register (014 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s irq f3 s irq f2 s irq f1 s irq f0 s irq 3 s irq 2 s irq 1 s irq 0 r irq f3 r irq f2 r irq f1 r irq f0 r irq 3 r irq 2 r irq 1 r irq 0 wwwwwwwwwwwwwwww 1514131211109876543210 0 s crf 3 s crf 2 s crf 1 s crf 0 0 r crf 3 r crf 2 r crf 1 r crf 0 r wwww r wwww field bits type description rcrfx (x = 0-3) xw clear conversion request flag this bit allows bit crsr.crfx to be cleared by software. 0 b no operation 1 b bit crsr.crfx is cleared. scrfx (x = 0-3) 8 + x w set conversion request flag this bit allows bit crsr.crfx to be set by software. 0 b no operation 1 b bit crsr.crfx is set. rirqx (x = 0-3) 16 + x w clear interrupt request flag this bit allows bit crsr.irqx to be cleared by software. 0 b no operation 1 b bit crsr.irqx is cleared. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-38 v1.1, 2011-03 fadc, v2.6 rirqfn (n = 0-3) 20 + n w clear interrupt request flag for filter n this bit allows bit crsr.irqfn to be cleared by software. 0 b no operation 1 b bit crsr.irqfn is cleared. sirqx (x = 0-3) 24 + x w set interrupt request flag this bit allows bit crsr.irqx to be set by software. 0 b no operation 1 b bit crsr.irqx is set and an interrupt is generated if cfgrx.ien = 1. sirqfn (n = 0-3) 28 + n w set interrupt request flag for filter n this bit allows bit crsr.irqfn to be set by software. 0 b no operation 1 b bit crsr.irqfn is set and an interrupt is generated if fcrn.ien = 1. 0 [7:4], [15:12]1 212121 2 r reserved read as 0. should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-39 v1.1, 2011-03 fadc, v2.6 32.3.2.3 neighbor channel trigger register the neighbor channel trigger register nctr contains the enable bits for the neighbor channel trigger signal (nctx) generation (see page 32-20 ). nctr neighbor channel trigger register (018 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 en 32 en 31 en 30 0 en 23 0 en 21 en 20 r rwrwrw r 1514131211109876543210 0 en 13 en 12 0 en 10 0 en 03 en 02 en 01 0 rrwrrwr field bits type description en01 1rw enable neighbor channel trigger 01 this bit enables the neighbor channel trigger for channel 1 when a conversion of channel 0 is started. 0 b no action. 1 b a trigger will be generated. en02 2rw enable neighbor channel trigger 02 this bit enables the neighbor channel trigger for channel 2 when a conversion of channel 0 is started. 0 b no action. 1 b a trigger will be generated. en03 3rw enable neighbor channel trigger 03 this bit enables the neighbor channel trigger for channel 3 when a conversion of channel 0 is started. 0 b no action. 1 b a trigger will be generated. en10 8rw enable neighbor channel trigger 10 this bit enables the neighbor channel trigger for channel 0 when a conversion of channel 1 is started. 0 b no action. 1 b a trigger will be generated. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-40 v1.1, 2011-03 fadc, v2.6 en12 10 rw enable neighbor channel trigger 12 this bit enables the neighbor channel trigger for channel 2 when a conversion of channel 1 is started. 0 b no action. 1 b a trigger will be generated. en13 11 rw enable neighbor channel trigger 13 this bit enables the neighbor channel trigger for channel 3 when a conversion of channel 1 is started. 0 b no action. 1 b a trigger will be generated. en20 16 rw enable neighbor channel trigger 20 this bit enables the neighbor channel trigger for channel 0 when a conversion of channel 2 is started. 0 b no action. 1 b a trigger will be generated. en21 17 rw enable neighbor channel trigger 21 this bit enables the neighbor channel trigger for channel 1 when a conversion of channel 2 is started. 0 b no action. 1 b a trigger will be generated. en23 19 rw enable neighbor channel trigger 23 this bit enables the neighbor channel trigger for channel 3 when a conversion of channel 2 is started. 0 b no action. 1 b a trigger will be generated. en30 24 rw enable neighbor channel trigger 30 this bit enables the neighbor channel trigger for channel 0 when a conversion of channel 3 is started. 0 b no action. 1 b a trigger will be generated. en31 25 rw enable neighbor channel trigger 31 this bit enables the neighbor channel trigger for channel 1 when a conversion of channel 3 is started. 0 b no action. 1 b a trigger will be generated. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-41 v1.1, 2011-03 fadc, v2.6 note: the hardware does not check whether the enable bits are set in such a way as to describe a loop of conversion requests (e.g . 0 triggers 2, 2 triggers 3 and 3 triggers 0, etc.). it is in the resp onsibility of the user to set th ese bits in an appropriate way. en32 26 rw enable neighbor channel trigger 32 this bit enables the neighbor channel trigger for channel 2 when a conversion of channel 3 is started. 0 b no action. 1 b a trigger will be generated. 0 0, [7:4], 9, [15:12], 18, [23:20], [31:27] r reserved read as 0. should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-42 v1.1, 2011-03 fadc, v2.6 32.3.2.4 global control register the global control register gcr contains bits used to reset the channel timers, the filters and to control global fadc settings. gcr global control register (01c h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 calch calmode 0 an on mux tm res wen dpa en crprio r rw rw r rw rw rw rw rwh 1514131211109876543210 0 rst f3 rst f2 rst f1 rst f0 rcd 0 rct 3 rct 2 rct 1 rct 0 r wwwww r wwww field bits type description rctx (x = 0-3) xw reload channel timer 0 b channel x timer will not be changed. 1 b channel x timer will be loaded with its reload value. rcd 8w reset common divider 0 b the common divider will not be changed. 1 b the common divider will be cleared. rstfn (n = 0-3) 9 + n w reset filter n 0 b the contents of filter n will not be changed. 1 b the contents of filter n will be cleared. the values of the bits in the filter registers will be cleared, except bit field crrn.ac that is loaded with the value of fcrn.addl. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-43 v1.1, 2011-03 fadc, v2.6 crprio [17:16] rwh conversion request priority this bit field determines the priority of the conversion requests if more than one channel is requested. if the dynamic priority assignment is enabled, the priority is automatically changed as a function of the gating inputs. the priority of the channels is: 00 b channel 0 before channel 1 before channel 2 before channel 3 01 b channel 1 before channel 2 before channel 3 before channel 0 10 b channel 2 before channel 3 before channel 0 before channel 1 11 b channel 3 before channel 0 before channel 1 before channel 2 dpaen 18 rw dynamic priority assignment enable if the dynamic priority assignment is enabled, the priority bit field crprio is automatically changed as a function of the gating input signals. in this case, the channel that is active while the other three channels are not active gets the highest priority. 0 b the dynamic priority assignment is disabled. 1 b the dynamic priority assignment is enabled. reswen 19 rw result write enable this bit enables a write action to the result registers rchx (x = 0-3) of the fadc. 0 b write accesses to the result registers are not taken into account. the written data is discarded. 1 b write accesses to the result registers are taken into account. the former value of the written result register is overwritten by the write data. if a filter is sensitive to the written result register, the written value is taken as new filter input value. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-44 v1.1, 2011-03 fadc, v2.6 muxtm 20 rw multiplexer test mode the input multiplexer to select a channel for the conversion can be tested by opening all multiplexer inputs. in multiplexer test mode, the channel amplifiers are not connected to the converter stage. 0 b the multiplexer test mode is disabled. 1 b the multiplexer test mode is enabled. anon 21 rw analog part on this bit enables the analog part of the fadc. this bit must be set to convert the analog input signal to a digital value. 0 b the complete analog part is in power-down mode, the amplifiers and comparators are switched off. conversions are not possible. 1 b the analog part is enabled. calmode [25:24] rw calibration mode this bit field enables the calibration for offset and gain for the channel selected by calch. 00 b no calibration process is running. all channels are in normal mode (default after reset). 01 b the analog channel selected by calch is in offset calibration mode. the other channels are in normal mode. 10 b reserved 11 b reserved calch [27:26] rw calibration channel this bit field selects the channel for the calibration process determined by calmode. the setting of calch is only taken into account while a calibration process is running. 00 b the analog input channel 0 is selected for a calibration process. 01 b the analog input channel 1 is selected for a calibration process. 10 b the analog input channel 2 is selected for a calibration process. 11 b the analog input channel 3 is selected for a calibration process. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-45 v1.1, 2011-03 fadc, v2.6 0 [7:4], [15:13], [23:22], [31:28] r reserved read as 0. should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-46 v1.1, 2011-03 fadc, v2.6 32.3.2.5 alias register the alias register contains bit fields a llowing a re-assignment of the requested channel number to the actually converted channel. alr alias register (054 h ) reset value: 0000 00e4 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 rrw 1514131211109876543210 0 alias3 alias2 alias1 alias0 r rwrwrwrw field bits type description alias0 [1:0] rw alias of channel 0 this bit field defines which channel is converted if a trigger for channel 0 occurs. 00 b channel 0 will be converted (default). 01 b channel 1 will be converted. 10 b channel 2 will be converted. 11 b channel 3 will be converted. alias1 [3:2] rw alias of channel 1 this bit field defines which channel is converted if a trigger for channel 1 occurs. 00 b channel 0 will be converted. 01 b channel 1 will be converted (default). 10 b channel 2 will be converted. 11 b channel 3 will be converted. alias2 [5:4] rw alias of channel 2 this bit field defines which channel is converted if a trigger for channel 2 occurs. 00 b channel 0 will be converted. 01 b channel 1 will be converted. 10 b channel 2 will be converted (default). 11 b channel 3 will be converted. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-47 v1.1, 2011-03 fadc, v2.6 alias3 [7:6] rw alias of channel 3 this bit field defines which channel is converted if a trigger for channel 3 occurs. 00 b channel 0 will be converted. 01 b channel 1 will be converted. 10 b channel 2 will be converted. 11 b channel 3 will be converted (default). 0 16 rw placeholder bit this bit position is a placeholder for further extensions and should be written with 0. 0 [31:17], [15:8] r reserved read as 0. should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-48 v1.1, 2011-03 fadc, v2.6 32.3.3 channel registers 32.3.3.1 channel conf iguration registers the channel x configuration register cfgrx contains the bits for the selection of the trigger source, the gating source, and other channel settings of channel x. cfgrx (x = 0-3) channel x configuration register (020 h +x*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ien 0 inp 0 ctrel rw r rw r rw 1514131211109876543210 0 ctf ctm tm gm tsel gsel r rw rwrwrw rw rw field bits type description gsel [2:0] rw gating selection this bit field selects the gating source input signal for channel x. 000 b gating source input signal gsa selected 001 b gating source input signal gsb selected 010 b gating source input signal gsc selected 011 b gating source input signal gsd selected 100 b gating source input signal gse selected 101 b gating source input signal gsf selected 110 b gating source input signal gsg selected 111 b gating source input signal gsh selected www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-49 v1.1, 2011-03 fadc, v2.6 tsel [5:3] rw trigger selection this bit field selects the trig ger source input signal for channel x. 000 b trigger source input signal tsa selected 001 b trigger source input signal tsb selected 010 b trigger source input signal tsc selected 011 b trigger source input signal tsd selected 100 b trigger source input signal tse selected 101 b trigger source input signal tsf selected 110 b trigger source input signal tsg selected 111 b trigger source input signal tsh selected gm [7:6] rw gating mode this bit field determines the functionality of the gating (enable) signal. it determines whether and under which condition the generation of conversion requests by trigger signals is possible. 00 b conversion requests are disabled and the channel timer is stopped. crfx never becomes set (by hardware). 01 b conversion requests and the channel timer are always enabled. crfx becomes set by hardware with each active trigger signal. 10 b conversion requests and the channel timer are enabled only if the gating source input (as selected by cfgrx.gsel) is at high level. 11 b conversion requests and the channel timer are enabled only if the gating source input (as selected by cfgrx.gsel ) is at low level. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-50 v1.1, 2011-03 fadc, v2.6 tm [9:8] rw trigger mode this bit field enables the triggering and determines the edge of the trigger source input signal that generates a conversion trigger signal. 00 b no conversion trigger signals are generated. edge detection unit is switched off. 01 b a conversion request is generated (if gating enabled) on a rising edge of a trigger source input (as selected by cfgrx.tsel). 10 b a conversion request is generated (if gating enabled) on a falling edge of a trigger source input (as selected by cfgrx.tsel). 11 b a conversion request is generated (if gating enabled) on bo th, rising and fa lling, edges of a trigger source input (as selected by cfgrx.tsel). ctm [11:10] rw channel timer mode this bit determines the operating mode of channel x timer. 00 b channel x timer is switched off. 01 b channel timer is permanently running. 10 b channel timer is running only if echtimx = 1. 11 b reserved a channel timer trigger event is generated each time the channel x timer value reaches 00 h . while the channel timer is not running (ctm = 00 b or signal echtimx = 0), the channel timer is loaded with 04 h . ctf [14:12] rw channel timer frequency this bit field controls the channel x timer input clock f ct (enable control and frequency selection). 000 b f ctx is disabled. 001 b f ctx is enabled with frequency f fadc . 010 b f ctx is enabled with frequency f fadc / 4. 011 b f ctx is enabled with frequency f fadc / 16. 100 b f ctx is enabled with frequency f fadc / 64. 101 b f ctx is enabled with frequency f fadc / 256. 110 b f ctx is enabled with frequency f fadc / 1024. 111 b reserved; do not use this combination. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-51 v1.1, 2011-03 fadc, v2.6 ctrel [23:16] rw channel timer reload value this bit field determines the reload value of the channel timer chtimx, see section 32.2.5 . if ctrel = 0, no trigger event is generated. inp [29:28] rw interrupt no de pointer this bit field selects which service request output line will be activated when a conversion of channel x is finished while cfgrx.ien is set. 00 b service request output sr0 is selected. 01 b service request output sr1 is selected. 10 b service request output sr2 is selected. 11 b service request output sr3 is selected. ien 31 rw interrupt enable this bit enables the generation of a service request when a conversion of channel x is finished. 0 b channel x conversion service request generation is disabled. 1 b channel x conversion service request generation is enabled. 0 15, [27:24], 30 r reserved read as 0. should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-52 v1.1, 2011-03 fadc, v2.6 32.3.3.2 analog control registers the channel x analog control register acrx contains the bits that control the analog input stage. acrx (x = 0-3) channel x analog control register (030 h +x*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 00 cal off 3 0 caloff [2:0] 0 enn enp gain r rwrwr rw r rwrwrw field bits type description gain [1:0] rw amplifier gain this bit field determines the amplifier gain for channel x. 00 b the selected amplifier gain is 1. 01 b the selected amplifier gain is 2. 10 b the selected amplifier gain is 4. 11 b the selected amplifier gain is 8. enp 2rw enable positive input this bit enables the voltage measurement on the fainxp analog input. 0 b analog input fainxp is high-impedance. the upper half of the measuring range is not available. 1 b analog input fainxp line is connected to the channel amplifier. the upper half of the measuring range is available. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-53 v1.1, 2011-03 fadc, v2.6 enn 3rw enable negative input this bit enables the voltage measurement on the fainxn analog input. 0 b analog input fainxn is high-impedance. the lower half of the measuring range is not available. 1 b analog input fainxn line is connected to the channel amplifier. the lower half of the measuring range is available. caloff[2:0] [10:8] rw calibrate offset this bit field determines the value applied for the offset calibration for channel x. the calibrate offset value is composed by the most significant bit caloff3 and bit field caloff[2:0], resulting in a 4-bit bit field caloff[3:0]. caloff3 12 rw 0 [7:4], 11, [14:13], [31:15] r reserved read as 0. should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-54 v1.1, 2011-03 fadc, v2.6 32.3.3.3 conversion result registers the channel x conversion result register rchx contains the conversion result of channel x. rchx (x = 0-3) channel x conversion result register (040 h +x*4 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 0 adres rrwh field bits type description adres [9:0] rwh ad conversion result this bit field contains the conversion result of channel x. adres can only be overwritten by software if gcr.reswen = 1. 0 [31:10] r reserved read as 0. should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-55 v1.1, 2011-03 fadc, v2.6 32.3.4 filter registers 32.3.4.1 filter control registers filter blocks are controlled by bits in the filter n cont rol registers fcrn. fcrn (n = 0-3) filter n control register (060 h +n*20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 1514131211109876543210 ien 0 inp 0 insel 0 mavl 0 addl rwrrwr rw r rwr rw field bits type description addl [2:0] rw addition length this bit field determines the number of filter input values that are added to obtain one intermediate result. 000 b each filter input value is considered as intermediate result. 001 b 2 filter input values are added up. 010 b 3 filter input values are added up. 011 b 4 filter input values are added up. 100 b 5 filter input values are added up. 101 b 6 filter input values are added up. 110 b 7 filter input values are added up. 111 b 8 filter input values are added up. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-56 v1.1, 2011-03 fadc, v2.6 mavl [5:4] rw moving average length this bit field determines the number of intermediate results that are added up for a final result. 00 b no moving average is selected. each intermediate result is co nsidered as final result value: frrn.fr = crrn.cr 01 b a moving average of 2 values is selected. the final result is calculated by 2 values: frrn.fr = crrn.cr + irr1n.ir 10 b a moving average of 3 values is selected. the final result is calculated by 3 values: frrn.fr = crrn.cr + irr1n.ir + irr2n.ir 11 b a moving average of 4 values is selected. the final result is calculated by 4 values: frrn.fr = crrn.cr + irr1n.ir + irr2n.ir + irr3n.ir bit combinations 10 b and 11 b are not available in filter blocks 1 and 3 and mu st not be selected there. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-57 v1.1, 2011-03 fadc, v2.6 insel [10:8] rw input selection this bit field enables the filter block and determines which input value is taken for filter block n. for the settings 010 b , set form = 00 b . 000 b the filter block is disabled. intermediate and final sum calculations are not executed. the filter register values are not changed (except by a filter block reset). 001 b any conversion result of any channel is taken as new filter input value. 010 b filter block 0: filter is stopped (as 000 b ). filter block 1: filter input value is the output value (final result) of filter block 0. filter block 2: filter is stopped (as 000 b ). filter block 3: filter input value is the output value (final result) of filter block 2. 011 b reserved 100 b channel 0 conversion result is taken as filter input value. 101 b channel 1 conversion result is taken as filter input value. 110 b channel 2 conversion result is taken as filter input value. 111 b channel 3 conversion result is taken as filter input value. note: channel 2/3 is only applicable for fadc modules having 4 channels inp [13:12] rw interrupt node pointer this bit field selects which service request output line will be activated when a final result of filter block n is available while bit ien is set. 00 b service request output sr0 selected 01 b service request output sr1 selected 10 b service request output sr2 selected 11 b service request output sr3 selected ien 15 rw interrupt enable this bit enables the generation of a new final result service request of filter block n. 0 b service request generation disabled 1 b service request generation enabled field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-58 v1.1, 2011-03 fadc, v2.6 32.3.4.2 current result registers the current result registers crrn store the current result of filter n. further, status information of filter block n can be read from crrn. 0 3, [7:6], 11, 14, [31:16] r reserved read as 0. should be written with 0. crrn (n = 0-3) filter n current result register (064 h + n * 20 h ) reset value: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0mavs0 ac 0 cr rrhrrh r rh 1514131211109876543210 cr rh field bits type description cr [17:0] rh current result this bit field (significant bits [12:0] for filter 0 and 2, [17:0] for filter 1 and 3) contains the right-aligned current result value of filter 0. cr is cleared when writing gcr.rstfn = 1. ac [26:24] rh addition count this bit field indicates the number of additions of filter input values with remain to be executed before the next intermediate result register transfer occurs. ac is loaded with the value of fcrn.addl for a new addition sequence, also when writing gcr.rstfn = 1. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-59 v1.1, 2011-03 fadc, v2.6 mavs [29:28] rh moving average state this bit field indicates how many intermediate registers transfers remain to be executed for the generation of the next final result. mavs = 0 indicates the end of a filter calculation operation. since the filter calculation is executed very fast in comparison to a conversion, mavs > 0 can be interpreted only as a kind of calculation busy flag. therefore, it is recommended to read a valid filter result from register frrn only when the corresponding interrupt request flag crsr.irqfn is set. mavs is reset when wr iting gcr.rstfn = 1. 0 [23:18], 27, [31:30] r reserved read as 0. should be written with 0. field bits type description www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-60 v1.1, 2011-03 fadc, v2.6 32.3.4.3 interme diate result registers the intermediate result registers irrmn hold the intermediate results y of filter n. irry0 (y = 1-3) filter 0 intermediate result register y (064 h +y*4 h ) reset value: 0000 0000 h irry2 (y = 1-3) filter 2 intermediate result register y (0a4 h +y*4 h ) reset value: 0000 0000 h 31 13 12 0 0ir rrh field bits type description ir [12:0] rh intermediate result this bit field contains the right-aligned intermediate result. ir is cleared when writing gcr.rstfn = 1. 0 [31:13] rh reserved read as 0. should be written with 0. irr11 filter 1 intermediate result register 1 (088 h ) reset value: 0000 0000 h irr13 filter 3 intermediate result register 1 (0c8 h ) reset value: 0000 0000 h 31 18 17 0 0ir rrh www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-61 v1.1, 2011-03 fadc, v2.6 field bits type description ir [17:0] rh intermediate result this bit field contains the right-aligned intermediate result. ir is reset when writing gcr.rstfn = 1. 0 [31:18] rh reserved read as 0. should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-62 v1.1, 2011-03 fadc, v2.6 32.3.4.4 final result registers the final result registers frrn hold the final results of filter block n. the data width being different for the filter block 0 and 2 from the one from data blocks 1 and 3, two different register layouts are necessary. frr0 filter 0 final result register (074 h ) reset value: 0000 0000 h frr2 filter 2 final result register (0b4 h ) reset value: 0000 0000 h 31 15 14 0 0fr rrh field bits type description fr [14:0] rh final result this bit field contains the right-aligned final result. fr is cleared when writing gcr.rstfn = 1. 0 [31:15] rh reserved read as 0. should be written with 0. frr1 filter 1 final result register (094 h ) reset value: 0000 0000 h frr3 filter 3 final result register (0d4 h ) reset value: 0000 0000 h 31 20 19 0 0fr rrh field bits type description fr [19:0] rh final result this bit field contains the right-aligned final result. fr is cleared when writing gcr.rstfn = 1. 0 [31:20] rh reserved read as 0. should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-63 v1.1, 2011-03 fadc, v2.6 the shifted final result registers sfrrn hold the final results of filter blocks 1 and 3 that are shifted right by 5 bit positions. the data representation allows the use of 16-bit data operations for further treatment. sfrr1 filter 1 shifted final result register (098 h ) reset value: 0000 0000 h sfrr3 filter 3 shifted final result register (0d8 h ) reset value: 0000 0000 h 31 15 14 0 0fr rrh field bits type description fr [14:0] rh final result this bit field contains the right-aligned final result from the corresponding final result register frrn shifted right by 5 bit positions. fr is cleared when writing gcr.rstfn = 1. 0 [31:15] rh reserved read as 0. should be written with 0. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-64 v1.1, 2011-03 fadc, v2.6 32.4 implementation of fadc this section describes the implementation of the fadc module in the TC1798. 32.4.1 register overview all fadc kernel register names described in this section are referenced in other parts of the TC1798 users manual by the module name prefix ?fadc_?. table 32-7 registers address space - fadc module module base address end address note fadc f010 0400 h f010 05ff h - table 32-8 registers overview register short name register long name offset address page number intentionally left blank, please refer to register table in section 32.3 h www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-65 v1.1, 2011-03 fadc, v2.6 32.4.2 fadc connections the following table shows the analog connections of the fadc kernel with other modules or pins in the TC1798 device. the following table shows the digital connections of the fadc kernel with other modules or pins in the TC1798 device. table 32-9 connections to fadc analog part in TC1798 fadc signal of analog part from/to module or pin input or output can be used to/as v ddif v ddm i analog power supply 3 v - 5.5 v of input stage, connected to the power supply of the adc v ddmf v dda i analog power supply 3.3 v v ssmf v ssmf i analog power ground v ddaf v ddaf i analog power supply 1.2 v v ssaf v ssm i analog power ground v faref v faref i positive analog reference, v fagnd v fagnd i negative analog reference, fain0p an64 i analog input p channel 0 fain0n an65 i analog input n channel 0 fain1p an66 i analog input p channel 1 fain1n an67 i analog input n channel 1 fain2p an68 i analog input p channel 2 fain2n an69 i analog input n channel 2 fain3p an70 i analog input p channel 3 fain3n an71 i analog input n channel 3 table 32-10 connections of fadc digital part in TC1798 fadc signal of digital part from/to module or pin input or output can be used to/as gating inputs gsa req0 i p1.0p1.0p1.0p1.0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-66 v1.1, 2011-03 fadc, v2.6 32.4.3 service request connections the fadc kernel provides 4 service request output lines fadc_sr[3:0]. all 4 lines are connected to the dma (for more details, refer to dma chapter). gsb req4 i p7.0 gsc pdout2 i eru gsd pdout3 i eru gse trig11 i gpta gsf trig13 i gpta gsg trig15 i gpta gsh trig17 i gpta trigger inputs tsa req1 i p1.1 tsb req5 i p7.1 tsc iout2 i eru tsd iout3 i eru tse trig00 i gpta tsf trig02 i gpta tsg trig04 i gpta tsh trig06 i gpta others fadc_ sr[3:0] interrupt controller, dma o service request output lines of fadc (service request) table 32-11 fadc service request connections in TC1798 service request signal connected to service request node fadc_sr[0] fadc_src0 fadc_sr[1] fadc_src1 fadc_sr[2] fadc_src2 fadc_sr[3] fadc_src3 table 32-10 connections of fadc digital part in TC1798 (cont?d) fadc signal of digital part from/to module or pin input or output can be used to/as www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 fast analog to di gital converter (fadc) users manual 32-67 v1.1, 2011-03 fadc, v2.6 32.4.4 clock control the fadc module is provided with two clock signals: ? f clc this is the module clock that is used inside the fadc kernel for control purposes such as clocking of control logic and register operations. the frequency of f clc is always identical to the system clock frequency f fpi . the clock control register fadc_clc makes it possible to enable/disable f clc . ? f fadc this clock is the module clock that is used in the fadc as the clock for the channel timer and other internal timings, such as th e conversion timing. the fractional divider registers fadc_fdr controls the frequency of f fadc and allows it to be enabled/disabled independently of f clc . figure 32-15 fadc clock generation the following formulas define the frequency of f fadc : (32.2) (32.3) equation (32.2) is valid for fadc_fdr.dm = 01 b (normal divider mode). equation (32.3) is valid for fadc_fdr.dm = 10 b (fractional divider mode). mca0644 7 clock control register fadc_clc fadc clock generation f fpi fractional divider register fadc_fdr ecen v ss fadc module kernel f clc f fadc f fadc f fpi 1 n -- - with n = 1024 - fdr.step = f fadc f fpi n 1024 ------------ - with n = 0-1023 = www.datasheet.co.kr datasheet pdf - http://www..net/ users manual l-1 v1.1, 2011-03 TC1798 keyword index a abbreviations 1-4 access mode definitions 1-3 adc adc0 connections 31-137 adc1 connections 31-143 adc2 connections 31-149 , 31-155 equidistant sampling 31-120 registers alr0 31-84 apr 31-125 asenr 31-47 bwdcfgr 31-133 bwdenr 31-132 chctrx 31-81 chenprx 31-88 chfcr 31-87 chfr 31-86 clc 31-25 crcrx 31-54 crmrx 31-57 crprx 31-56 emctr 31-126 evfcr 31-109 evfr 31-107 evnpr 31-110 globcfg 31-37 globctr 31-34 globstr 31-39 id 31-32 inpcrx 31-83 intr 31-33 kscfg 31-26 lcbrx 31-85 q0rx 31-70 qburx 31-72 qinrx 31-74 qmrx 31-65 qsrx 31-68 rcrx 31-105 resr0 31-100 resrd0 31-100 resrdx 31-102 resrx 31-102 rnprx 31-111 rsirx 31-29 rsprx 31-48 srcx 31-28 synctr 31-130 vfr 31-104 asc asynchronous mode 20-4?20-8 data frames 20-5 baud rate generation 20-12?20-16 asynchronous modes 20-13 synchronous mode 20-16 block diagram asynchronous modes 20-4 synchronous mode 20-9 dma request outputs 20-40 error detection 20-17 features 20-2 implementation address map 20-42 interrupt generation 20-17 module implementation dma request outputs 20-40 input/output function selection 20-37 interrupt registers 20-39 module clock control 20-33 peripheral input select 20-35 registers 20-19 bg 20-27 con 20-22 fdv 20-27 id 20-21 offset addresses 20-19 overview 20-19 pisel 20-20 rbuf 20-29 keyword index www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-2 v1.1, 2011-03 tbuf 20-28 whbcon 20-25 synchronous mode 20-9?20-11 timings 20-11 asi field in mmu_asi register 2-25 b basic operation 10-3 bcu sbcu 4-70 bus agents and priorities 4-70 bus arbitration 4-70 bus error handling 4-72 starvation prevention 4-72 bmu registers clc 18-30 ctl 18-33 fmctl 18-43 fmsts 18-43 fmth 18-44 fullness 18-35 id 18-32 miecon 18-47 miecon2 18-47 pset0 18-36 pset1 18-39 ptr 18-34 smacon 18-46 src 18-49 tid 18-42 bootrom 5-5 c can address map 24-214 basics 24-2 addressing and arbitration 24-2 basic-/full-can 24-10 error detection and handling 24-9 frame formats 24-3 nominal bit time 24-8 block diagram 24-14 dma requests 24-209 module implementation 24-202?24-213 external registers 24-203 i/o line control 24-208 input/output function selection 24-208 interfaces 24-202 interrupt control 24-211 module clock generation 24-204 multican bit timing 24-26 block diagram 24-18 clock generation 24-21, 24-22 interrupt structure 24-20 message acceptance filtering 24-39 message object data handling 24-46 message object fifo 24-53 message object functionality 24-52 message object interrupts 24-42 message object lists 24-31 node control 24-25 node interrupts 24-29 suspend mode 24-23 multican module features 24-15 multican registers address ranges 24-214 listi 24-71 mcr 24-69 mitr 24-70 moamrn 24-110 moarn 24-112 moctrn 24-94 modatahn 24-116 modataln 24-115 mofcrn 24-104 mofgprn 24-109 moiprn 24-102 mostatn 24-97 msidk 24-74 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-3 v1.1, 2011-03 msimask 24-75 mspndk 24-73 nbtrx 24-87 ncrx 24-76 necntx 24-89 nfcrx 24-90 niprx 24-84 npcrx 24-86 nsrx 24-80 overview 24-60 panctr 24-65 registers offset addresses 24-61 ttcan 24-117 application watchdog 24-153 automatic tur adjust 24-118 configuration 24-151 cycle time 24-118 error handling 24-153 interrupt control 24-155 local offset and global time 24-121 local time generation 24-117 master reference mark 24-120 msc handling 24-154 reference message 24-123 scheduler 24-126 scheduler entry setup 24-145 scheduler entry types 24-128 arbe 24-134 bce 24-143 eos 24-144 ice 24-132 rce 24-139, 24-141 tce 24-136, 24-129 scheduler instruction sequence 24-148 scheduler memory 24-127 transmit enable window 24-120 transmit trigger 24-122 ttcan extension features 24-17 ttcan basics 24-11 basic cycle 24-11 global system time 24-12 network time unit 24-13 system matrix 24-12 time reference 24-11 ttcan extension registers 24-157 address map 24-159 awdr 24-171 cyctmr 24-166 gmr 24-169 lgmr 24-170 lor 24-167 lrefmr 24-165 ltr 24-162 offset addresses 24-157 overview 24-157 refmr 24-164 sisr 24-198 stptr0 24-195 stsrh 24-197 stsrl 24-196 synmr 24-163 ttcfgr 24-176 ttcr 24-172 ttfmr 24-183 ttier 24-189 ttinpr 24-193 ttirr 24-185 ttsr 24-178 turr 24-160 capcom6 1-47 capture mode gpt1 30-29 gpt2 (caprel) 30-55 capture/compare unit 6 1-47 chip select outputs 15-53 clc register 3-54 implementation in the modules 3-57 clock output signal 3-30 clock system oscillator run detection 3-9 clock system www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-4 v1.1, 2011-03 clock source 3-8, 3-17 clock tree diagram 3-3 features 3-2 module clock generation 3-53 clc register 3-54 fractional divider 3-58 oscillator run detection 3-6 overview 3-2 pll, see ?pll? concatenation of timers 30-25, 30-53 count direction 30-6, 30-41 counter 30-23, 30-51 counter mode (gpt1) 30-10, 30-45 cpu registers 2-59 compat 2-29 cpu_id 2-26 cpu_sbsrc 2-61 cpu_srcn 2-60 diear 2-53 dietr 2-51 fpu_id 2-39 icr 2-23 miecon 2-42 , 2-44 mmu_con 2-24 piear 2-49 pietr 2-47 psw 2-22 smacon 2-55 see also proc essor subsystem cscomb control 15-53 d direction count 30-6, 30-41 dma 12-2 access protection 12-44 access protection assignment 12-111 block diagram 12-2, 13-2 bridge functionality 12-26 bus switch 12-21, 13-21 bus switch priorities 12-23 bus switch priorities of dma move en- gines 12-23 channel operation 12-6, 13-6 channel operation modes 12-11, 13-11 channel request control 12-10, 13-10 channel reset operation 12-16, 13-16 circular buffer 12-19, 13-19 control registers offset addresses 12-48 debug capabilities 12-27, 13-23 definition of terms 12-4, 13-4 dma principle 12-5 error conditions 12-15, 13-15 features 12-3, 13-3 implementation diagram 12-100, 13-84 interrupts 12-30, 13-26 channel interrupts 12-30, 13-26 interrupt request compressor 12-36, 13-31 move engine interrupts 12-33, 13-29 transaction lost interrupts 12-32, 13-28 wrap buffer interrupts 12-35, 13-30 memory checker control registers offset addresses 12-132 on chip bus access rights, rmw support 12-24, 13-21 on chip bus master interfaces 12-25, 13-21 pattern detection 12-37, 13-32 priorities on on chip busses 12-24 registers adrcr0x 12-92 adrcr1x 12-92 block address map 12-129, 13-95 chcr0x 12-85 chcr1x 12-85 chicr0x 12-90 chicr1x 12-90 chrstr 12-59 chsr0x 12-89 chsr1x 12-89 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-5 v1.1, 2011-03 clre 12-71 dadr0x 12-98 dadr1x 12-98 dma_mli0srcx 12-127 dma_mli1srcy 12-127 dma_srcx 12-126 eer 12-65 errsr 12-68 gintr 12-58 htreq 12-63 id 12-53 intcr 12-77 intsr 12-73 me0aenr0 12-81 me0aenr1 12-81 me0arr0 12-83 me0arr1 12-83 me0pr 12-80 me0r 12-80 me1aenr0 12-81 me1aenr1 12-81 me1arr 12-83 me1arr0 12-83 me1pr 12-80 me1r 12-80 mesr 12-78 ocdsr 12-54 overview 12-47 , 13-40 sadr0x 12-97 sadr1x 12-97 shadr0x 12-99 shadr1x 12-99 streq 12-62 suspmr 12-56 trsr 12-60 wrpsr 12-75 request wiring matrix 12-101, 13-84 transaction control 12-20, 13-20 dmi features 2-88 overlay control 7-1 dmi data memory interface 2-88 document structure 1-1 terminology and abbreviations 1-3 textual conventions 1-1 e ebu 15-1 access phases 15-62 address phase 15-63 burst phase 15-65 command delay phase 15-64 command phase 15-64 data hold phase 15-65 recovery phase 15-67 address region selection 15-49 asynchronous accesses signals 15-69 wait control 15-76 boot operation 15-41 boot read access cycle 15-43 configuration word 15-44 external boot mode 15-41 external bus arbitration 15-28 arbitration modes 15-30 arbitration signals 15-28 arbitration timing 15-32 ebu as participant 15-35 ebu as sole master 15-30 locking external bus 15-39 modes 15-28 memory regions 15-45 registers addrselx 15-163 busrapx 15-172 busrconx 15-165 buswapx 15-175 buswconx 15-169 clc 15-156 ddrncon 15-190 ddrnmod 15-192 ddrnmod2 15-194 ddrnprld 15-197 ddrnsrr 15-196 ddrntagx 15-198 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-6 v1.1, 2011-03 extboot 15-161 modcon 15-158 overview 15-153 sdrmcon 15-178 sdrmod 15-180 sdrmref 15-183 sdrstat 15-185 usercon 15-199 ebu control register offset addresses 15-153 ebu_addrsel0 15-163 ebu, see ?external bus interface unit? emergency stop output control 3-155 register scu_emsr 3-157 entering sleep mode 3-122 e-ray block diagram 1-33, 26-1, 26-263 channel protocol controller 26-4 clock minimum 26-243 communication controller commands 26-92, 26-95 fifo 26-230 message ram 26-248 poc 26-116 protocol operation control 26-116 restrictions 26-262 service requests 26-259 customer host interface 26-3 frame processing 26-5 generic host interface 26-3 global time unit 26-5 input buffer 26-4 interrupt control 26-6 kernel clock minimum 26-243 ram test 26-30 release coding 26-167 service request 26-41, 26-87 test registers 26-23 kernel block diagram 26-3 kernel description 1-33, 26-1 message buffer pointer 26-140 message handler 26-4 message ram 26-4 module implementations 26-263 on-chip connections 26-266 service request 26-269 module registers 26-8 network management 26-5 output buffer 26-4 overview 1-34, 26-2 protocol clock 26-199 communication cycle 26-196 network management 26-222 register offsets 26-8??? registers 26-8???, 26-16 acs 26-130 ccev 26-120 ccsv 26-115 clc 26-268 communication controller control 26-88, 26-113 communication controller status 26-115?26-137 crel 26-166 cust1 26-17 cust3 26-20 customer registers 26-16 eier 26-65 eies 26-60 eils 26-52 eir 26-41 endn 26-168 esidnn (nn = 01-015) 26-133 fcm 26-144 frf 26-141 frfm 26-143 fsr 26-149 gtuc01 26-103 gtuc02 26-104 gtuc03 26-105 gtuc04 26-106 gtuc05 26-107 gtuc06 26-108 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-7 v1.1, 2011-03 gtuc07 26-109 gtuc08 26-110 gtuc09 26-111 gtuc10 26-112 gtuc11 26-113 ibcm 26-175 ibcr 26-177 id 26-16 identification 26-166?26-168 ile 26-80 input buffer 26-168?26-177 int0src 26-279 int1src 26-279 lck 26-39 ldts 26-148 mbs 26-186 mbsc0src 26-279 mbsc1 26-162 mbsc10src 26-279 mbsc2 26-163 mbsc3 26-164 mbsc4 26-165 message buffer control 26-138?26-144 message buffer status 26-145?26-165 mhdc 26-102 mhdf 26-151 mhds 26-145 mrc 26-138 msic1 26-274 msic2 26-275 msic3 26-276 msic4 26-277 mtccv 26-122 ndat0src 26-279 ndat1 26-158 ndat1src 26-279 ndat2 26-159 ndat3 26-160 ndat4 26-161 ndic1 26-270 ndic2 26-271 ndic3 26-272 ndic4 26-273 nemc 26-98 nmvx (x = 1-3) 26-137 obcm 26-191 obcr 26-194 ocv 26-124 osidnn (nn = 01-15) 26-135 output buffer 26-179?26-193 prt2 26-101 prtc1 26-99 rcv 26-123 rddsnn (nn = 01-64) 26-179 rdhs1 26-180 rdhs2 26-182 rdhs3 26-184 scv 26-121 service request 26-41, 26-87 service request nodes 26-269 sfs 26-125 sier 26-75 sies 26-70 sils 26-56 sir 26-47 stpw1 26-85 stpw2 26-87 succ1 26-88 succ2 26-96 succ3 26-97 swinit 26-127 t1c 26-83 test registers 26-23 test1 26-23 test2 26-28 , 26-31 , 26-33 , 26-35 , 26-37 , 26-38 tint0src 26-279 tint1src 26-279 toc 26-81 txrq1 26-154 txrq2 26-155 txrq3 26-156 txrq4 26-157 wrdsnn (nn = 01-64) 26-169 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-8 v1.1, 2011-03 wrhs 26-170 wrhs2 26-173 wrhs3 26-174 symbol processing 26-5 system universal control 26-5 transient buffer 26-4 esr registers esrcfg0 3-84 esrcfg1 3-84 scu_iocr 3-85 external bus interface unit, see ?ebu? external request unit registers 3-104 eicr0 3-105 eicr1 3-108 eifr 3-112 fmr 3-112 igcr0 3-114 igcr1 3-117 pddr 3-113 f fadc calibration 32-21 channel timers 32-11 channel triggers 32-8 clock generation 32-13 conversion priority 32-12 data reduction filter 32-15 filter block structure 32-16 filter concatenation 32-17 gating modes 32-9 interrupts 32-23 module implementation module clock control 32-67 neighbor channel triggers 32-20 registers acrx 32-52 alr 32-46 cfgrx 32-48 clc 32-30 crrn 32-58 crsr 32-35 fcrn 32-55 fdr 32-31 fmr 32-37 frrn 32-62 gcr 32-42 id 32-33 irryn 32-60 nctr 32-39 overview 32-26 rchx 32-54 sfrrn 32-63 srcn 32-34 trigger modes 32-10 fce block diagram 14-4 block diagram crc kernels 14-5 control registers offset addresses 14-15 features 14-3 programming guide 14-28 registers cfgm 14-22 checkm 14-25 clc 14-17 crcm 14-26 ctrm 14-27 id 14-20 irm 14-21 lengthm 14-25 overview 14-14 register map 14-15 resm 14-21 stsm 14-24 related documents 14-2 fdr register 3-51, 3-64 features instruction set 1-10 on-chip memory 1-10 flash 5-6 alse 5-78 application hints 5-64 command sequences 5-13 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-9 v1.1, 2011-03 clear status 5-18 disable read protection 5-17 disable sector write protection 5-17 enter page mode 5-14 erase physical sector 5-16 erase sector 5-15 erase user configuration block 5-16 load page 5-14 reset to read 5-13 resume protection 5-18 write page 5-15 write user configuration page 5-15 concurrent operations 5-18 configuration sector 5-7 ecc 5-23, 5-79 endurance 5-6 erasing 5-6 flash bank 5-7 flash module 5-7 flash structure 5-7 interrupts and traps 5-25 keyflash 5-7 logical sector 5-7 margin checks 5-24 operations 5-10 page 5-7 physical sector 5-7 power reduction 5-26 programming 5-6 protection 5-19 read buffers 5-9 registers eccr 5-61 eccw 5-60 fcon 5-41 fsr 5-32 id 5-47 mard 5-51 marp 5-50 procon0 5-52 procon1 5-55 procon2 5-58 rdbcfg0 5-46 rdbcfg1 5-46 rdbcfg2 5-46 sema 5-49 sheboot0-2 5-62 xfsr 5-39 reset 5-25 resets during flash operation 5-76 retention 5-6 sector 5-7 ucb 5-7, 5-21 user configuration block 5-7 word-line 5-7 fpi bus 4-65 basic operations 4-68 overview 4-65 transaction types 4-67 fractional divider 3-58 block diagram 3-28 fdr register 3-51, 3-64 implementation in the modules 3-61 operating modes 3-29 frequency output signal 3-30 g gated timer mode (gpt1) 30-9 gated timer mode (gpt2) 30-44 gpt1 30-2 gpt2 30-37 gpta address ranges 28-308 block diagram 28-8 clock generation cells (cgc) 28-10 clock distribution module 28-35 digital phase locked loop cell 28-30 duty cycle measurement cell 28-26 filter and prescaler cell 28-12 phase discrimination logic 28-21 features of gpta0 28-5 features of gpta0/gpta1 1-44 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-10 v1.1, 2011-03 features of gpta1 28-5 input in1 control 3-181 interrupt processing and control 28-123, 28-248 module implementations 28-274 block diagram 28-275 cascading limits 28-306 external registers 28-276 input/output function selection 28-279 module clock generation 28-296 on-chip connections 28-286 port control and connections 28-276 overview 28-4 programming hints 28-158 pseudo-code description 28-126?28-155 registers address ranges 28-308 signal generation cells (sgc) global timer cell 28-55 global timers 28-38 local timer cell 28-67 gpta0 registers ckbctr 28-185 clc 28-300 dbgctr 28-305 dcmcavk 28-175 dcmcovk 28-176 dcmctrk 28-173 dcmtimk 28-175 edctr 28-303 fdr 28-301 fpcctrk 28-168 fpcstat 28-167 fpctimk 28-170 gimcrhg 28-217 gimcrlg 28-215 gtcctrk 28-187 , 28-189 gtctrk 28-182 gtcxrk 28-191 gtrevk 28-184 gttimk 28-183 limcrhg 28-221 limcrlg 28-219 ltcctr63 28-204 ltcctrk 28-192 , 28-195 ltcxr63 28-206 ltcxrk 28-205 mmxctr00 28-291 mmxctr01 28-291 mmxctr10 28-292 mmxctr11 28-293 mractl 28-207 mradin 28-208 mradout 28-209 offset addresses 28-161 omcrhg 28-212 , 28-307 omcrlg 28-210 otmcrlg 28-214 overview 28-160 pdlctr 28-171 pllcnt 28-179 pllctr 28-177 plldtr 28-181 pllmti 28-178 pllrev 28-180 pllstp 28-179 srnr 28-232 srsc0 28-223 srsc1 28-226 srsc2 28-228 srsc3 28-230 srss0 28-225 srss1 28-227 srss2 28-229 srss3 28-231 gpta1 registers ckbctr 28-185 dcmcavk 28-175 dcmcovk 28-176 dcmctrk 28-173 dcmtimk 28-175 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-11 v1.1, 2011-03 fpcctrk 28-168 fpcstat 28-167 fpctimk 28-170 gimcrhg 28-217 gimcrlg 28-215 gtcctrk 28-187 , 28-189 gtctrk 28-182 gtcxrk 28-191 gtrevk 28-184 gttimk 28-183 limcrhg 28-221 limcrlg 28-219 ltcctr63 28-204 ltcctrk 28-192 , 28-195 ltcxr63 28-206 ltcxrk 28-205 mractl 28-207 mradin 28-208 mradout 28-209 offset addresses 28-161 omcrhg 28-212 omcrlg 28-210 otmcrg 28-214 overview 28-160 pdlctr 28-171 pllcnt 28-179 pllctr 28-177 plldtr 28-181 pllmti 28-178 pllrev 28-180 pllstp 28-179 srck 28-307 srnr 28-232 srsc0 28-223 srsc1 28-226 srsc2 28-228 srsc3 28-230 srss0 28-225 srss1 28-227 srss2 28-229 srss3 28-231 i idle mode 3-121 incremental interface mode (gpt1) 30-11 interrupt system arbitration cycles 16-12 arbitration process 16-12 block diagram 16-2 control register icr 16-8 external interrupts 16-22 hints for applications 16-18?16-22 interrupt control unit 16-8 interrupt vector table 16-15 overview 16-1 priorities 16-19 service request control register 16-3 service request node table 16-23 service request nodes 16-3 service routine entering 16-13 service routine exiting 16-14 software initiate d interrupts 16-22 l lmu register clc 6-5 id 6-9 memcon 6-6 ltca2 registers limcrhg 28-272 limcrlg 28-271 ltcctr31 28-261 ltcctrk 28-252 ltcxr31 28-263 ltcxrk 28-263 mractl 28-264 mradin 28-266 mradout 28-266 offset addresses 28-250 omcrhg 28-269 omcrlg 28-268 overview 28-250 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-12 v1.1, 2011-03 srck 28-307 srsc2 28-228 srsc3 28-230 srss2 28-229 srss3 28-231 m memory checker 12-130 functionality 12-130 registers mchk_id 12-133 mchk_irx 12-135 mchk_rrx 12-135 , 12-136 mchk_wr 12-136 memory maps 9-1 access restrictions 9-21, 9-22 segment 0 to 14 from spb 9-8 segment 15 from spb 9-13 segment contents 9-6 memory protection system registers 2-33 mli access protection 27-49 block diagram 27-51 communication principles 27-6 frames 27-10 answer frame 27-18 command frame 27-17 copy base address frame 27-12 layout 27-11 optimized read frame 27-16 optimized write frame 27-14 write offset and data frame 27-13 handshake signalling 27-19 interrupts 27-57 receiver interrupts 27-62 transmitter interrupts 27-59 kernel registers 27-77 module implementation 27-127 clock generation 27-131 input/output function selection 27-133 mli0 block diagram 27-128, 27-129 on-chip connections 27-136 transfer window map 27-138 naming conventions 27-4 receiver i/o line control 27-53 registers aer 27-90 aer1 27-90 arr0 27-91 arr1 27-91 fdr 27-79 gintr 27-83 offset addresses 27-78 oicr 27-86 overview 27-77 radrr 27-118 rcr 27-113 rdatar 27-119 rier 27-120 rinpr 27-125 risr 27-123 rpxbar 27-117 rpxstatr 27-116 scr 27-84 tcbar 27-106 tcr 27-92 tdrar 27-104 tier 27-107 tinpr 27-111 tisr 27-109 tpxaofr 27-103 tpxbar 27-105 tpxdatar 27-104 tpxstatr 27-97 trstatr 27-101 tstatr 27-95 , 27-99 transaction flow diagrams command frame 27-41 copy base address 27-28 read frame 27-35 write frame 27-30 transmitter description of frame transmission www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-13 v1.1, 2011-03 27-28 i/o line control 27-53 typical application 27-2 mmu_asi address space identifier register def- inition 2-25 module clock generation 3-53 msc applications 23-2 downstream channel 23-5 baud rate 23-20 block diagram 23-5 command frames 23-7 data frames 23-9 data repetition mode 23-15 downstream counter 23-19 frame formats 23-6 output control 23-27 passive time frames 23-11 shift register operation 23-12 transmission mode 23-14 triggered mode 23-14 features 23-4 i/o control 23-27 interrupts 23-31 command frame interrupt 23-32 data frame interrupt 23-32 interrupt request compressor 23-35 receive data interrupt 23-34 time frame finished interrupt 23-33 kernel block diagram 23-3 module implementation input/output function selection 23-69 module clock control 23-65 overview 23-3 registers dc 23-59 dd 23-59 dsc 23-41 dsdsh 23-47 dsdsl 23-46 dss 23-44 esr 23-48 icr 23-49 id 23-38 , 27-82 isc 23-54 isr 23-52 ocr 23-56 offset addresses 23-37 overview 23-36 udx 23-60 usr 23-39 upstream channel 23-21 baud rate 23-25 block diagram 23-21 data frame protocol 23-22 data reception 23-23, 23-24 input control 23-30 parity checking 23-22 sampling 23-26 o ocds cerberus 19-10 communication mode 19-11 features 19-10 multi-core break switch 19-11 registers 19-14 rw mode 19-10 triggered transfers 19-11 components 19-4 jtag interface 19-13 registers 19-14 ocds level 1 19-5 debug actions 19-8 debug event generation 19-7 of bcu 19-9 of cpu 19-6 of dma 19-9 of pcp 19-9 registers 19-8 ocds level 3 19-1 overview 19-1 system block diagram 19-3 operational 14-4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-14 v1.1, 2011-03 ovc access performance 7-6 data access overlay control 7-1 data access redirection 7-2 emulation memory overlay 7-6 external memory overlay 7-6 overlay memory control registers 7-7 offset addresses 7-7 overview 7-7 overlay registers ocon 7-14, 7-16 omaskx 7-12 otarx 7-11 rabrx 7-9 overlay control 7-1 p pcon 2-85 pcp 11-1 accessing from fpi bus 11-57 architecture 11-3 channel programs 11-27 context models 11-13 control and interrupt registers 11-62, 11-66 debugging 11-60 error handling 11-44 general purpose registers 11-8 instruction set details 11-98 instruction set overview 11-49 instruction times 11-138 instruction timing 11-135 interrupt operation 11-34 overview 11-2 programming 11-145 programming model 11-8 programming tips 11-151 registers pcp_clc 11-67 pcp_cs 11-69 pcp_es 11-71 pcp_icon 11-77 pcp_icr 11-74 pcp_id 11-68 pcp_itr 11-76 pcp_smacon 11-81 , 11-82 , 11-83 , 11-84 , 11-85 , 11-86 , 11-87 , 11-91 pcp_src0 11-92 pcp_src1 11-92 pcp_src10 11-96 pcp_src11 11-96 pcp_src2 11-94 pcp_src3 11-94 pcp_src4 11-95 pcp_src5 11-95 pcp_src6 11-95 pcp_src7 11-95 pcp_src8 11-95 pcp_src9 11-96 pcp_ssr 11-79 peripheral control processor, see pcp pll 3-7 , 3-16 features 3-7, 3-16 functionality 3-7, 3-16 pmi features 2-79 registers 2-82 pmi_con0 2-83 pmi_con1 2-84 pmi program memory interface 2-79 pmu block diagram 5-2 bootrom 5-5 changes to audo-ng and audo-f 5-64 configuration 5-2 data access overlay operation 1-23 flash 5-6 registers id 5-28 tuning protection 5-5 port temperature compensation 3-136 ports emergency stop control 3-155 function table 10-5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-15 v1.1, 2011-03 general port structure 10-3 i/o functions 10-5 output register pn_out 3-87 pad driver control 10-16, 10-20 pad driver mode selection 10-16 port 0 10-27 function table 10-28, 10-102, 10-142 register overview 10-32, 10-144, 10-155 port 1 10-33 function table 10-34, 10-153 register overview 10-37 port 10 10-96 function table 10-96 register overview 10-98 port 11 10-101 function table 10-102 register overview 10-106 port 12 10-107 function table 10-108 register overview 10-109 port 13 10-111 function table 10-112 register overview 10-117 port 14 10-118 function table 10-119 register overview 10-124 port 15 10-125 function table 10-126 register overview 10-131 port 16 10-132 function table 10-133 register overview 10-137 port 17 10-141 port 18 10-152 port 2 10-39 function table 10-39 register overview 10-44 port 3 10-48 function table 10-48 register overview 10-54 port 4 10-55 function table 10-55 register overview 10-60 port 5 10-62 function table 10-64 register overview 10-69 port 6 10-70 function table 10-71 register overview 10-75 port 7 10-77 function table 10-78 register overview 10-80 port 8 10-81 function table 10-82, 10-96 register overview 10-85 port 9 10-86 function table 10-87 register overview 10-92 port control coding 10-14 registers 10-7, 10-63 emergency stop register 10-24 input register 10-25 input/output control registers 3-84, 10-11, 10-145 output modification register 10-22 output register 10-21 pad driver mode register 10-16, 10-20 power management register pmcsr 3-122 power management 3-120 idle mode 3-121 mode definitions 3-120 sleep mode 3-122 processor subsystem core debug registers 2-62 cpu block diagram 2-4 csfrs 2-20 execution unit 2-6 features 2-2, 2-8 general purpose register file 2-7 implementation-specific features 2-2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-16 v1.1, 2011-03 instruction fetch unit 2-5 registers 2-19 data cache 2-17 data side memories 2-16 data tag 2-17 error handling 2-13 general purpose registers 2-30 implementation-specific features 2-10 instruction cache 2-15 instruction timing 2-66 interrupt system 2-12 local data ram 2-16 memory protection registers 2-33 pmi block diagram 2-79 program side memories 2-14 program tag 2-15 scratchpad ram 2-14 see also cpu subsystem block diagram 2-1 r register mmu_asi 2-25 pcon 2-85 reset 3-68 module behavior 3-69 registers rstcntcon 3-78 scu_arstdis 3-80 scu_rstcon 3-78 scu_rststat 3-75 swrstcon 3-81 s sbcu registers sbcu_con 4-83 sbcu_dbadr! 4-93 sbcu_dbadr2 4-93 sbcu_dbadrt 4-97 sbcu_dbbos 4-94 sbcu_dbbost 4-98 sbcu_dbcntl 4-88 sbcu_dbdat 4-100 sbcu_dbgrnt 4-91 sbcu_dgntt 4-95 sbcu_eadd 4-86 sbcu_econ 4-84 sbcu_edat 4-87 sbcu_id 4-82 sbcu_src 4-102 sbcu control registers offset ad- dresses 4-80 scu miscellaneous registers scu_chipid 3-183 scu_id 3-184 scu_manid 3-185 scu_rtid 3-185 registers scu_dtscon 3-137 scu_dtsstat 3-138 sdma 13-2 control registers offset addresses 13-41 registers adrcr0x 13-72 chcr0x 13-65 chicr0x 13-70 chrstr 13-51 chsr0x 13-69 clre 13-59 dadr0x 13-78 damax0x 13-81 damin0x 13-81 eer 13-55 errsr 13-57 gintr 13-50 htreq 13-54 id 13-46 intsr 13-60 me0pr 13-64 me0r 13-64 mesr 13-63 ocdsr 13-47 rdcrc0x 13-83 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-17 v1.1, 2011-03 sadr0x 13-77 samax0x 13-80 samin0x 13-80 scrc0x 13-82 sdcrc0x 13-82 sdma_srcx 13-94 shadr0x 13-79 streq 13-53 suspmr 13-49 trsr 13-52 wrpsr 13-61 sdma principle 13-5 sfi bridge 4-64 sleep mode 3-122 sri terms 4-4 ssc baud rate generation 21-14, 21-48, 22-34 baud rate generation formulas 21-50, 22-35 block diagram 21-4 chip select generation 21-17 continuous transfer 21-10 dma request outputs 21-46 error detection 21-20 full-duplex operation 21-6 half-duplex operation 21-9 interrupts 21-20 module implementation 21-43, 22-30 dma request outputs 21-46 interrupt registers 21-58, 22-39 module clock control 21-48, 22-34 port control 21-53 parity mode 21-11 registers 3-187, 21-27, 22-8 address map 21-59, 22-40 br 21-41 , 22-23 con 21-31 , 22-13 efm 21-36 , 22-18 id 21-28 offset addresses 21-28, 22-9 overview 21-27, 22-8, 22-40 pisel 21-29 , 22-11 rb 21-42 , 22-24 , 22-26 ssoc 21-38 , 22-20 stat 21-34 , 22-16 , 22-27 , 22-28 , 22-29 tb 21-42 , 22-24 , 22-25 slave select input operation 21-16 slave select output operation 21-17 sscg registers id 22-10 stm, see ?system timer? 17-1 system peripheral bus 4-65 system timer block diagram 1-16, 17-3 compare register operation 17-5 implementation details 17-21 interrupt control 17-6 on-chip interconnections 17-21 operation 17-1 overview 17-1 registers address map 17-21 offset addresses 17-8 overview 17-7 stm_cap 17-14 stm_clc 17-9 stm_cmcon 17-15 stm_cmpx 17-14 stm_icr 17-17 stm_id 17-10 stm_isrr 17-19 stm_srcx 17-20 stm_tim0 17-11 stm_tim1 17-11 stm_tim2 17-12 stm_tim3 17-12 stm_tim4 17-12 stm_tim5 17-13 stm_tim6 17-13 resolutions and ranges 17-4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 keyword index users manual l-18 v1.1, 2011-03 t temperature measurement 3-136 timer 30-2, 30-37 auxiliary timer 30-15, 30-46 concatenation 30-25, 30-53 core timer 30-4, 30-39 counter mode (gpt1) 30-10, 30-45 gated mode (gpt1) 30-9 gated mode (gpt2) 30-44 incremental interface mode (gpt1) 30-11 mode (gpt1) 30-8 mode (gpt2) 30-43 ttcan, see ?can? tuning protection 5-5 w watchdog timer period calculation 3-145 watchdog timer 3-139?3-154 during power-saving modes 3-148 endinit function 3-140 features 3-139 modify access to wdt_con0 3-143 operating modes disable mode 3-146 normal mode 3-146 prewarning mode 3-146 time-out mode 3-145 overview 3-139 registers 3-149 wdt_con0 3-149 wdt_con1 3-151 wdt_sr 3-152 servicing 3-147 wdt operating modes 3-145 wdt, see ?watchdog timer? x xbar_sri registers xbar_arbcon 4-42 xbar_dbadd 4-55 xbar_dbcon 4-52 xbar_dbmadd 4-59 xbar_dbsat 4-35 xbar_dmadd 4-59 xbar_err 4-51 xbar_erraddr 4-50 xbar_extcon 4-40 xbar_id 4-34 xbar_idinten 4-39 xbar_idintsat 4-37 xbar_intsat 4-36 xbar_prioh 4-44 xbar_priol 4-44 xbar_src 4-63 xbar_sri control registers offset addresses 4-28 www.datasheet.co.kr datasheet pdf - http://www..net/ users manual l-19 v1.1, 2011-03 TC1798 register index a a0 2-31 a1 2-31 a10 2-32 a11 2-32 a12 2-32 a13 2-32 a14 2-32 a15 2-32 a2 2-31 a3 2-31 a4 2-31 a5 2-32 a6 2-32 a7 2-32 a8 2-32 a9 2-32 adc_alr0 31-84 adc_apr 31-125 adc_asenr 31-47 adc_bwdcfgr 31-133 adc_bwdenr 31-132 adc_chctrx 31-81 adc_chenprx 31-88 adc_chfcr 31-87 adc_chfr 31-86 adc_crcrx 31-54 adc_crmrx 31-57 adc_crprx 31-56 adc_emctr 31-126 adc_evfcr 31-109 adc_evfr 31-107 adc_evnpr 31-110 adc_globcfg 31-37 adc_globctr 31-34 adc_globstr 31-39 adc_id 31-32 adc_inprx 31-83 adc_intr 31-33 adc_lcbrx 31-85 adc_q0rx 31-70 adc_qburx 31-72 adc_qinrx 31-74 adc_qmrx 31-65 adc_qsrx 31-68 adc_rcrx 31-105 adc_resr0 31-100 adc_resrd0 31-100 adc_resrdx 31-102 adc_resrx 31-102 adc_rnprx 31-111 adc_rsirx 31-29 adc_rsprx 31-48 adc_synctr 31-130 adc_vfr 31-104 adc0_clc 31-25 adc0_kscfg 31-26 adc0_srcx 31-28 asc module registers 20-19 asc0 register address map 20-42 asc0_bg 20-27, 20-42 asc0_clc 20-33, 20-42 asc0_con 20-22, 20-42 asc0_esrc 20-39, 20-43 asc0_fdv 20-27, 20-42 asc0_id 20-21, 20-42 asc0_pisel 20-36, 20-42 asc0_rbuf 20-29, 20-42 asc0_rsrc 20-39, 20-42 asc0_tbsrc 20-39, 20-43 asc0_tbuf 20-28, 20-42 asc0_tsrc 20-39, 20-42 asc0_whbcon 20-25, 20-42 asc1 register address map 20-43 asc1_bg 20-27, 20-43 asc1_con 20-22, 20-43 asc1_esrc 20-39, 20-44 asc1_fdv 20-27, 20-43 asc1_id 20-21, 20-43 asc1_pisel 20-36, 20-43 asc1_rbuf 20-29, 20-43 register index www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-20 v1.1, 2011-03 asc1_rsrc 20-39, 20-43 asc1_tbsrc 20-39, 20-44 asc1_tbuf 20-28, 20-43 asc1_tsrc 20-39, 20-43 asc1_whbcon 20-25, 20-43 b biv 2-20 bmu_clc 18-30 bmu_ctl 18-33 bmu_fmctl 18-43 bmu_fmsts 18-43 bmu_fmth 18-44 bmu_fullness 18-35 bmu_id 18-32 bmu_miecon 18-47 bmu_miecon2 18-47 bmu_pset0 18-36 bmu_pset1 18-39 bmu_ptr 18-34 bmu_smacon 18-46 bmu_src 18-49 bmu_tid 18-42 btv 2-20 c can_awdr 24-171 can_clc 24-205 can_cyctmr 24-166 can_fdr 24-206 can_gmr 24-169 can_lgmr 24-170 can_listi 24-71 can_lor 24-167 can_lrefmr 24-165 can_ltr 24-162 can_mcr 24-69 can_mitr 24-70 can_moamrn 24-110 can_moarn 24-112 can_moctrn 24-94 can_modatahn 24-116 can_modataln 24-115 can_module registers 24-61 can_mofcrn 24-104 can_mofgprn 24-109 can_moiprn 24-102 can_mostatn 24-97 can_msidk 24-74 can_msimask 24-75 can_mspndk 24-73 can_nbtrx 24-87 can_ncrx 24-76 can_necntx 24-89 can_nfcrx 24-90 can_niprx 24-84 can_npcrx 24-86 can_nsrx 24-80 can_panctr 24-65 can_refmr 24-164 can_sisr 24-198 can_srcm 24-213 can_stptr0 24-195 can_stsrh 24-197 can_stsrl 24-196 can_synmr 24-163 can_ttcfgr 24-176 can_ttcr 24-172 can_ttfmr 24-183 can_ttier 24-189 can_ttinpr 24-193 can_ttirr 24-185 can_ttsr 24-178 can_turr 24-160 cbs_comdata 19-16 cbs_ictsa 19-16 cbs_ictta 19-16 cbs_intmod 19-16 cbs_iosr 19-16 cbs_jdpid 19-16 cbs_mcdbbs 19-16 cbs_mcdbbss 19-16 cbs_mcdssg 19-16 cbs_mcdssgc 19-16 cbs_ocntrl 19-16 cbs_oec 19-16 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-21 v1.1, 2011-03 cbs_ostate 19-16 cbs_src 19-16 ccdier 2-40 ccpier 2-40 compat 2-21, 2-29 cpm0 2-36 cpm1 2-36 cpm2 2-36 cpm3 2-36 cpu_id 2-20, 2-26 cpu_sbsrc 2-59, 2-61 cpu_src0 2-59 cpu_src1 2-59 cpu_src2 2-59 cpu_src3 2-59 cpu_srcn 2-60 d d0 2-30 d1 2-30 d10 2-31 d11 2-31 d12 2-31 d13 2-31 d14 2-31 d15 2-31 d2 2-30 d3 2-30 d4 2-30 d5 2-31 d6 2-31 d7 2-31 d8 2-31 d9 2-31 diear 2-40, 2-53 dietr 2-41, 2-51 dma control registers 12-48 dma_adrcr0x 12-92 dma_adrcr1x 12-92 dma_chcr0x 12-85 dma_chcr1x 12-85 dma_chicr0x 12-90 dma_chicr1x 12-90 dma_chrstr 12-59 dma_chsr0x 12-89 dma_chsr1x 12-89 dma_clc 12-125 dma_clre 12-71 dma_dadr0x 12-98 dma_dadr1x 12-98 dma_eer 12-65 dma_errsr 12-68 dma_gintr 12-58 dma_htreq 12-63 dma_id 12-53 dma_intcr 12-77 dma_intsr 12-73 dma_me0aenr0 12-81 dma_me0aenr1 12-81 dma_me0arr0 12-83 dma_me0arr1 12-83 dma_me0pr 12-80 dma_me0r 12-80 dma_me1aenr0 12-81 dma_me1aenr1 12-81 dma_me1arr0 12-83 dma_me1arr1 12-83 dma_me1pr 12-80 dma_me1r 12-80 dma_mesr 12-78 dma_mli0src0 12-51, 12-127 dma_mli0src1 12-51, 12-127 dma_mli0src2 12-51, 12-127 dma_mli0src3 12-51, 12-127 dma_mli1src0 12-51, 12-127 dma_mli1src1 12-51, 12-127 dma_ocdsr 12-54 dma_sadr0x 12-97 dma_sadr1x 12-97 dma_shadr0x 12-99 dma_shadr1x 12-99 dma_src0 12-52, 12-126 dma_src1 12-52, 12-126 dma_src2 12-52, 12-126 dma_src3 12-52, 12-126 dma_src4 12-52, 12-126 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-22 v1.1, 2011-03 dma_src5 12-52, 12-126 dma_src6 12-52, 12-126 dma_src7 12-52, 12-126 dma_streq 12-62 dma_suspmr 12-56 dma_trsr 12-60 dma_wrpsr 12-75 dmi_atr 2-93 dmi_con 2-93 dmi_str 2-93 dpm0 2-36 dpm1 2-36 dpm2 2-36 dpm3 2-36 e ebu registers 15-153 ebu_addrsel0 15-163 ebu_addrsel1 15-163 ebu_addrsel2 15-163 ebu_addrsel3 15-163 ebu_busrap0 15-172 ebu_busrap1 15-172 ebu_busrap2 15-172 ebu_busrap3 15-172 ebu_busrcon0 15-165 ebu_busrcon1 15-165 ebu_busrcon2 15-165 ebu_busrcon3 15-165 ebu_buswap0 15-175 ebu_buswap1 15-175 ebu_buswap2 15-175 ebu_buswap3 15-175 ebu_buswcon0 15-169 ebu_buswcon1 15-169 ebu_buswcon2 15-169 ebu_buswcon3 15-169 ebu_clc 15-156 ebu_ddrncon 15-190 ebu_ddrnmod 15-192 ebu_ddrnmod2 15-194 ebu_ddrnprld 15-197 ebu_ddrnsrr 15-196 ebu_ddrntag0 15-198 ebu_ddrntag1 15-198 ebu_ddrntag2 15-198 ebu_ddrntag3 15-198 ebu_extboot 15-161 ebu_id 15-200 ebu_modcon 15-158 ebu_sdrmcon 15-178 ebu_sdrmod 15-180 ebu_sdrmref 15-183 ebu_sdrstat 15-185 ebu_usercon 15-199 eicr0 3-105 eicr1 3-108 eifr 3-112 eray_acs 26-11, 26-130 eray_ccev 26-10, 26-120 eray_ccsv 26-10, 26-115 eray_clc 26-8, 26-268 eray_crel 26-14, 26-166 eray_cust1 26-8, 26-17 eray_cust3 26-8, 26-20 eray_data_read 26-37 eray_data_write 26-38 eray_ded_con 26-35 eray_dedcon 26-15 eray_eccr 26-15 eray_eccw 26-15 eray_eier 26-9, 26-65 eray_eies 26-9, 26-60 eray_eils 26-8, 26-52 eray_eir 26-8, 26-41 eray_endn 26-14, 26-168 eray_esidnn (nn = 01-15) 26-11, 26-133 eray_fcl 26-11 eray_fcm 26-144 eray_frf 26-11, 26-141 eray_frfm 26-11, 26-143 eray_fsr 26-12, 26-149 eray_gtuc01 26-10, 26-103 eray_gtuc02 26-10, 26-104 eray_gtuc03 26-10, 26-105 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-23 v1.1, 2011-03 eray_gtuc04 26-10, 26-106 eray_gtuc05 26-10, 26-107 eray_gtuc06 26-10, 26-108 eray_gtuc07 26-10, 26-109 eray_gtuc08 26-10, 26-110 eray_gtuc09 26-10, 26-111 eray_gtuc10 26-10, 26-112 eray_gtuc11 26-10, 26-113 eray_ibcm 26-14, 26-175 eray_ibcr 26-14, 26-177 eray_ibusysrc 26-13, 26-279 eray_id 26-8, 26-16 eray_ile 26-9, 26-80 eray_int0src 26-14, 26-279 eray_int1src 26-14, 26-279 eray_lck 26-8, 26-39 eray_ldts 26-11, 26-148 eray_mbs 26-14, 26-186 eray_mbsc0src 26-13, 26-279 eray_mbsc1 26-12, 26-162 eray_mbsc1src 26-13, 26-279 eray_mbsc2 26-12, 26-163 eray_mbsc3 26-12, 26-164 eray_mbsc4 26-12, 26-165 eray_mhdc 26-9, 26-102 eray_mhdf 26-12, 26-151 eray_mhds 26-11, 26-145 eray_mrc 26-11, 26-138 eray_msic1 26-13, 26-274 eray_msic2 26-13, 26-275 eray_msic3 26-13, 26-276 eray_msic4 26-13, 26-277 eray_mtccv 26-11, 26-122 eray_ndat0src 26-13, 26-279 eray_ndat1 26-12, 26-158 eray_ndat1src 26-13, 26-279 eray_ndat2 26-12, 26-159 eray_ndat3 26-12, 26-160 eray_ndat4 26-12, 26-161 eray_ndic1 26-12, 26-270 eray_ndic2 26-12, 26-271 eray_ndic3 26-12, 26-272 eray_ndic4 26-13, 26-273 eray_nemc 26-9, 26-98 eray_nmvx (x = 1-3) 26-11, 26-137 eray_obcm 26-14, 26-191 eray_obcr 26-15, 26-194 eray_obusysrc 26-13, 26-279 eray_ocv 26-11, 26-124 eray_osidnn (nn = 01-15) 26-11, 26-135 eray_prtc1 26-9, 26-99 eray_prtc2 26-9, 26-101 eray_rcv 26-11, 26-123 eray_rddsnn (nn = 01-64) 26-14, 26-179 eray_rdhs1 26-14, 26-180 eray_rdhs2 26-14, 26-182 eray_rdhs3 26-14, 26-184 eray_scv 26-10, 26-121 eray_sec_con 26-31 eray_seccon 26-15 eray_sed_con 26-33 eray_sedcon 26-15 eray_sfs 26-11, 26-125 eray_sier 26-9, 26-75 eray_sies 26-9, 26-70 eray_sils 26-56 eray_sir 26-8, 26-47 eray_stpw1 26-9, 26-85 eray_stpw2 26-9, 26-87 eray_succ1 26-9, 26-88 eray_succ2 26-9, 26-96 eray_succ3 26-9, 26-97 eray_swinit 26-127 eray_swnit 26-11 eray_t0c 26-9, 26-81 eray_t1c 26-9, 26-83 eray_test1 26-8, 26-23 eray_test2 26-8, 26-28 eray_tint0src 26-13, 26-279 eray_tint1src 26-13, 26-279 eray_txrq1 26-12, 26-154 eray_txrq2 26-12, 26-155 eray_txrq3 26-12, 26-156 eray_txrq4 26-12, 26-157 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-24 v1.1, 2011-03 eray_wrdsnn (nn = 01-64) 26-14, 26-169 eray_wrhs1 26-14, 26-170 eray_wrhs2 26-14, 26-173 eray_wrhs3 26-14, 26-174 esrcfg0 3-84 esrcfg1 3-84 f fadc_acrx 32-52 fadc_alr 32-46 fadc_cfgrx 32-48 fadc_clc 32-30 fadc_crr0 32-58 fadc_crrn 32-58 fadc_crsr 32-35 fadc_fcr0 32-55 fadc_fcr1 32-55 fadc_fcrn 32-55 fadc_fdr 32-31 fadc_fmr 32-37 fadc_frrn 32-62 fadc_gcr 32-42 fadc_id 32-33 fadc_irr10 32-60, 32-62, 32-63 fadc_irr20 32-60, 32-62, 32-63 fadc_irr30 32-60, 32-62, 32-63 fadc_irryn 32-60 fadc_nctr 32-39 fadc_rch0 32-54 fadc_rch1 32-54 fadc_rch2 32-54 fadc_rch3 32-54 fadc_rchx 32-54 fadc_sfrrn 32-63 fadc_srcn 32-34 fce control registers 14-15 fce_cfgm 14-22 fce_checkm 14-25 fce_clc 14-17 fce_crcm 14-26 fce_ctrm 14-27 fce_id 14-20 fce_irm 14-21 fce_lengthm 14-25 fce_resm 14-21 fce_src 14-18 fce_stsm 14-24 fcx 2-21 flash module registers 5-30 flash0_id 5-47 flash1_id 5-48 flashx_eccr 5-61 flashx_eccw 5-60 flashx_fcon 5-41 flashx_fsr 5-32 flashx_mard 5-51 flashx_marp 5-50 flashx_procon0 5-52 flashx_procon1 5-55 flashx_procon2 5-58 flashx_rdbcfg0 5-46 flashx_rdbcfg1 5-46 flashx_rdbcfg2 5-46 flashx_sema 5-49 flashx_shebo ot0-2 5-62 flashx_xfsr 5-39 fmr 3-112 fpu_id 2-38, 2-39 fpu_trap_con 2-38 fpu_trap_opc 2-38 fpu_trap_pc 2-38 fpu_trap_src1 2-38 fpu_trap_src2 2-38 fpu_trap_src3 2-38 g gpt12e_caprel 30-64 gpt12e_id 30-71 gpt12e_pisel 30-68 gpt12e_src0 30-35 gpt12e_src1 30-35 gpt12e_src2 30-35 gpt12e_src3 30-66 gpt12e_src4 30-66 gpt12e_src5 30-66 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-25 v1.1, 2011-03 gpt12e_t2 30-34 gpt12e_t2con 30-15, 30-17 gpt12e_t3 30-34 gpt12e_t3con 30-4 gpt12e_t4 30-34 gpt12e_t5 30-64 gpt12e_t5con 30-46 gpt12e_t6 30-64 gpt12e_t6con 30-39 gpta0_ckbctr 28-185 gpta0_clc 28-300 gpta0_dbgctr 28-305 gpta0_dcmcavk 28-175 gpta0_dcmcovk 28-176 gpta0_dcmctrk 28-173 gpta0_dcmtimk 28-175 gpta0_edctr 28-303 gpta0_fdr 28-301 gpta0_fpcctrk 28-168 gpta0_fpcstat 28-167 gpta0_fpctimk 28-170 gpta0_gimcrh 28-217 gpta0_gimcrl 28-215 gpta0_gtcctrk 28-187, 28-189 gpta0_gtctrk 28-182 gpta0_gtcxrk 28-191 gpta0_gtrevk 28-184 gpta0_gttimk 28-183 gpta0_limcrh 28-221 gpta0_limcrl 28-219 gpta0_ltcctr63 28-204 gpta0_ltcctrk 28-192, 28-195 gpta0_ltcxr63 28-206 gpta0_ltcxrk 28-205 gpta0_mmxctr00 28-291 gpta0_mmxctr01 28-291 gpta0_mmxctr10 28-292 gpta0_mmxctr11 28-293 gpta0_mractl 28-207 gpta0_mradin 28-208 gpta0_mradout 28-209 gpta0_omcrh 28-212 gpta0_omcrl 28-210 gpta0_otmcr 28-214 gpta0_pdlctr 28-171 gpta0_pllcnt 28-179 gpta0_pllctr 28-177 gpta0_plldtr 28-181 gpta0_pllmti 28-178 gpta0_pllrev 28-180 gpta0_pllstp 28-179 gpta0_srck 28-307 gpta0_srnr 28-232 gpta0_srsc0 28-223 gpta0_srsc1 28-226 gpta0_srsc2 28-228 gpta0_srsc3 28-230 gpta0_srss0 28-225 gpta0_srss1 28-227 gpta0_srss2 28-229 gpta0_srss3 28-231 gpta1_ckbctr 28-185 gpta1_dcmcavk 28-175 gpta1_dcmcovk 28-176 gpta1_dcmctrk 28-173 gpta1_dcmtimk 28-175 gpta1_fpcctrk 28-168 gpta1_fpcstat 28-167 gpta1_fpctimk 28-170 gpta1_gimcrh 28-217 gpta1_gimcrl 28-215 gpta1_gtcctrk 28-187, 28-189 gpta1_gtctrk 28-182 gpta1_gtcxrk 28-191 gpta1_gtrevk 28-184 gpta1_gttimk 28-183 gpta1_limcrh 28-221 gpta1_limcrl 28-219 gpta1_ltcctr63 28-204 gpta1_ltcctrk 28-192, 28-195 gpta1_ltcxr63 28-206 gpta1_ltcxrk 28-205 gpta1_mractl 28-207 gpta1_mradin 28-208 gpta1_mradout 28-209 gpta1_omcrh 28-212 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-26 v1.1, 2011-03 gpta1_omcrl 28-210 gpta1_otmcr 28-214 gpta1_pdlctr 28-171 gpta1_pllcnt 28-179 gpta1_pllctr 28-177 gpta1_plldtr 28-181 gpta1_pllmti 28-178 gpta1_pllrev 28-180 gpta1_pllstp 28-179 gpta1_srck 28-307 gpta1_srnr 28-232 gpta1_srsc0 28-223 gpta1_srsc1 28-226 gpta1_srsc2 28-228 gpta1_srsc3 28-230 gpta1_srss0 28-225 gpta1_srss1 28-227 gpta1_srss2 28-229 gpta1_srss3 28-231 i icr 2-21, 2-23, 16-8 igcr0 3-114 igcr1 3-117 isp 2-21 l lcx 2-21 lmu_clc 6-5 lmu_memcon 6-6 lmu_modid 6-9 ltca2_limcrh 28-272 ltca2_limcrl 28-271 ltca2_ltcctr31 28-261 ltca2_ltcctrk 28-252 ltca2_ltcxr31 28-263 ltca2_ltcxrk 28-263 ltca2_mractl 28-264 ltca2_mradin 28-266 ltca2_mradout 28-266 ltca2_omcrh 28-269 ltca2_omcrl 28-268 ltca2_srck 28-307 ltca2_srsc2 28-228 ltca2_srsc3 28-230 ltca2_srss2 28-229 ltca2_srss3 28-231 m mchk_crcx 12-136 mchk_id 12-133 mchk_irx 12-135 mchk_rrx 12-135 mchk_wr 12-136 memory checker control registers 12-132 miecon 2-40, 2-42, 2-44 mli module registers 27-78 mli0 register address map 27-139 mli0_aer0 27-90, 27-141 mli0_aer1 27-90, 27-142 mli0_arr0 27-91, 27-142 mli0_arr1 27-91, 27-142 mli0_fdr 27-79, 27-139 mli0_gintr 27-83, 27-141 mli0_id 27-139 mli0_oicr 27-86, 27-141 mli0_radrr 27-118, 27-141 mli0_rcr 27-113, 27-140 mli0_rdatar 27-119, 27-141 mli0_rier 27-120, 27-141 mli0_rinpr 27-125, 27-141 mli0_risr 27-123, 27-141 mli0_rp0bar 27-117, 27-140 mli0_rp0statr 27-116, 27-141 mli0_rp1bar 27-117, 27-140 mli0_rp1statr 27-116, 27-141 mli0_rp2bar 27-117, 27-140 mli0_rp2statr 27-116, 27-141 mli0_rp3bar 27-117, 27-140 mli0_rp3statr 27-116, 27-141 mli0_scr 27-84, 27-141 mli0_tcbar 27-106, 27-140 mli0_tcmdr 27-99, 27-139 mli0_tcr 27-92, 27-139 mli0_tdrar 27-104, 27-140 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-27 v1.1, 2011-03 mli0_tier 27-107, 27-141 mli0_tinpr 27-111, 27-141 mli0_tisr 27-109, 27-141 mli0_tp0aofr 27-103, 27-139 mli0_tp0bar 27-105, 27-140 mli0_tp0datar 27-104, 27-140 mli0_tp0statr 27-97, 27-139 mli0_tp1aofr 27-103, 27-139 mli0_tp1bar 27-105, 27-140 mli0_tp1datar 27-104, 27-140 mli0_tp1statr 27-97, 27-139 mli0_tp2aofr 27-103, 27-139 mli0_tp2bar 27-105, 27-140 mli0_tp2datar 27-104, 27-140 mli0_tp2statr 27-97, 27-139 mli0_tp3aofr 27-103, 27-140 mli0_tp3bar 27-105, 27-140 mli0_tp3datar 27-104, 27-140 mli0_tp3statr 27-97, 27-139 mli0_trstatr 27-101, 27-139 mli0_tstatr 27-95, 27-139 mli1 register address map 27-142 mli1_aer0 27-90, 27-145 mli1_aer1 27-90, 27-145 mli1_arr0 27-91, 27-145 mli1_arr1 27-91, 27-145 mli1_fdr 27-79, 27-142 mli1_gintr 27-83, 27-144 mli1_id 27-142 mli1_oicr 27-86, 27-145 mli1_radrr 27-118, 27-144 mli1_rcr 27-113, 27-143 mli1_rdatar 27-119, 27-144 mli1_rier 27-120, 27-144 mli1_rinpr 27-125, 27-144 mli1_risr 27-123, 27-144 mli1_rp0bar 27-117, 27-143 mli1_rp0statr 27-116, 27-144 mli1_rp1bar 27-117, 27-143 mli1_rp1statr 27-116, 27-144 mli1_rp2bar 27-117, 27-144 mli1_rp2statr 27-116, 27-144 mli1_rp3bar 27-117, 27-144 mli1_rp3statr 27-116, 27-144 mli1_scr 27-84, 27-144 mli1_tcbar 27-106, 27-143 mli1_tcmdr 27-99, 27-142 mli1_tcr 27-92, 27-142 mli1_tdrar 27-104, 27-143 mli1_tier 27-107, 27-144 mli1_tinpr 27-111, 27-144 mli1_tisr 27-109, 27-144 mli1_tp0aofr 27-103, 27-142 mli1_tp0bar 27-105, 27-143 mli1_tp0datar 27-104, 27-143 mli1_tp0statr 27-97, 27-142 mli1_tp1aofr 27-103, 27-143 mli1_tp1bar 27-105, 27-143 mli1_tp1datar 27-104, 27-143 mli1_tp1statr 27-97, 27-142 mli1_tp2aofr 27-103, 27-143 mli1_tp2bar 27-105, 27-143 mli1_tp2datar 27-104, 27-143 mli1_tp2statr 27-97, 27-142 mli1_tp3aofr 27-103, 27-143 mli1_tp3bar 27-105, 27-143 mli1_tp3datar 27-104, 27-143 mli1_tp3statr 27-97, 27-142 mli1_trstatr 27-101, 27-142 mli1_tstatr 27-95, 27-142 mmu_con 2-20, 2-24 msc module registers 23-37 msc0 register address map 23-75 msc0_clc 23-67, 23-75 msc0_dc 23-59, 23-75 msc0_dd 23-59, 23-75 msc0_dsc 23-41, 23-75 msc0_dsdsh 23-47, 23-75 msc0_dsdsl 23-46, 23-75 msc0_dss 23-44, 23-75 msc0_esr 23-48, 23-75 msc0_fdr 23-68, 23-75 msc0_icr 23-49, 23-76 msc0_id 23-38, 23-75, 27-82 msc0_isc 23-54, 23-76 msc0_isr 23-52, 23-76 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-28 v1.1, 2011-03 msc0_ocr 23-56, 23-76 msc0_src0 23-74, 23-76 msc0_src1 23-74, 23-76 msc0_ud0 23-60, 23-75 msc0_ud1 23-60, 23-75 msc0_ud2 23-60, 23-76 msc0_ud3 23-60, 23-76 msc0_usr 23-39, 23-75 msc1 register address map 23-76 msc1_clc 23-67, 23-76 msc1_dc 23-59, 23-77 msc1_dd 23-59, 23-77 msc1_dsc 23-41, 23-76 msc1_dsdsh 23-47, 23-77 msc1_dsdsl 23-46, 23-77 msc1_dss 23-44, 23-77 msc1_esr 23-48, 23-77 msc1_fdr 23-68, 23-76 msc1_icr 23-49, 23-77 msc1_id 23-38, 23-76, 27-82 msc1_isc 23-54, 23-77 msc1_isr 23-52, 23-77 msc1_ocr 23-56, 23-77 msc1_src0 23-74, 23-78 msc1_src1 23-74, 23-78 msc1_ud0 23-60, 23-77 msc1_ud1 23-60, 23-77 msc1_ud2 23-60, 23-77 msc1_ud3 23-60, 23-77 msc1_usr 23-39, 23-76 o ovc_ocon 7-14, 7-16 ovc_omaskx 7-12 ovc_otarx 7-11 ovc_rabrx 7-9 overlay memory control registers 7-7 p p0_esr 10-24 p0_in 10-25, 10-148 p0_iocr0 10-11, 10-145 p0_iocr12 10-14, 10-147 p0_iocr4 10-12, 10-146 p0_iocr8 10-13, 10-146 p0_omr 10-22 p0_out 10-21 p0_pdr0 10-18 p0_pdr1 10-19 p1_esr 10-24 p1_in 10-25, 10-148 p1_iocr0 10-11, 10-145 p1_iocr12 10-14, 10-147 p1_iocr4 10-12, 10-146 p1_iocr8 10-13, 10-146 p1_omr 10-22 p1_out 10-21 p1_pdr0 10-18 p1_pdr1 10-19 p10_in 10-25, 10-148 p10_iocr0 10-11 p10_iocr4 10-12, 10-146 p10_omr 10-22 p10_out 10-21 p10_pdr0 10-100 p11_in 10-25, 10-148 p11_iocr0 10-11 p11_iocr12 10-14 p11_iocr4 10-12, 10-146 p11_iocr8 10-13 p11_omr 10-22 p11_out 10-21 p11_pdr0 10-18 p11_pdr1 10-19 p12_in 10-25 p12_iocr0 10-11 p12_iocr4 10-12 p12_omr 10-22 p12_out 10-21 p12_pdr0 10-18 p13_esr 10-24 p13_in 10-25 p13_iocr0 10-11 p13_iocr12 10-14 p13_iocr4 10-12 p13_iocr8 10-13 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-29 v1.1, 2011-03 p13_omr 10-22 p13_out 10-21 p13_pdr0 10-18 p13_pdr1 10-19 p14_esr 10-24 p14_in 10-25 p14_iocr0 10-11 p14_iocr12 10-14 p14_iocr4 10-12 p14_iocr8 10-13 p14_omr 10-22 p14_out 10-21 p14_pdr0 10-18 p14_pdr1 10-19 p15_in 10-25 p15_iocr0 10-11 p15_iocr12 10-14 p15_iocr4 10-12 p15_iocr8 10-13 p15_omr 10-22 p15_out 10-21 p15_pdr0 10-18 p15_pdr1 10-19 p16_in 10-25 p16_iocr0 10-11 p16_iocr12 10-138 p16_iocr4 10-12 p16_iocr8 10-13 p16_omr 10-22 p16_out 10-21 p16_pdr0 10-18 p16_pdr1 10-140 p17_in 10-25 p18_in 10-25 p18_iocr0 10-11 p18_iocr4 10-12 p18_omr 10-22 p18_out 10-21 p18_pdr0 10-18 p2_esr 10-24 p2_in 10-25, 10-148 p2_iocr0 10-45, 10-99 p2_iocr12 10-14, 10-147 p2_iocr4 10-12, 10-146 p2_iocr8 10-13, 10-146 p2_omr 10-22 p2_out 10-21 p2_pdr0 10-46 p2_pdr1 10-19 p3_esr 10-24 p3_in 10-25, 10-148 p3_iocr0 10-11 p3_iocr12 10-14, 10-147 p3_iocr4 10-12, 10-146 p3_iocr8 10-13, 10-146 p3_omr 10-22 p3_out 10-21 p3_pdr0 10-18 p3_pdr1 10-19 p4_esr 10-24 p4_in 10-25, 10-148 p4_iocr0 10-11 p4_iocr12 10-14, 10-147 p4_iocr4 10-12, 10-146 p4_iocr8 10-13, 10-146 p4_omr 10-22 p4_out 10-21 p4_pdr0 10-18 p4_pdr1 10-19 p5_esr 10-24 p5_in 10-25, 10-148 p5_iocr0 10-11 p5_iocr4 10-12, 10-146 p5_iocr8 10-13, 10-146 p5_omr 10-22 p5_out 10-21 p5_pdr0 10-18 p5_pdr1 10-19 p6_in 10-25, 10-148 p6_iocr0 10-11 p6_iocr12 10-14, 10-147 p6_iocr4 10-12, 10-146 p6_iocr8 10-13, 10-146 p6_omr 10-22 p6_out 10-21 p6_pdr0 10-76 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-30 v1.1, 2011-03 p6_pdr1 10-19 p7_in 10-25, 10-148 p7_iocr0 10-11 p7_iocr4 10-12, 10-146 p7_omr 10-22 p7_out 10-21 p7_pdr0 10-18 p8_esr 10-24 p8_in 10-25, 10-148 p8_iocr0 10-11 p8_iocr4 10-12, 10-146 p8_omr 10-22 p8_out 10-21 p8_pdr0 10-18 p8_pdr1 10-19 p9_esr 10-24 p9_in 10-25, 10-148 p9_iocr0 10-11 p9_iocr4 10-12, 10-146 p9_iocr8 10-13, 10-93 p9_omr 10-22 p9_out 10-21 p9_pdr0 10-18 p9_pdr1 10-95 pc 2-20 pcp_clc 11-67 pcp_cs 11-69 pcp_es 11-71 pcp_icon 11-77 pcp_icr 11-74 pcp_id 11-68 pcp_itr 11-76 pcp_smacon 11-81, 11-82, 11-83, 11-84, 11-85, 11-86, 11-87, 11-91 pcp_src0 11-92 pcp_src1 11-92 pcp_src10 11-96 pcp_src11 11-96 pcp_src2 11-94 pcp_src3 11-94 pcp_src4 11-95 pcp_src5 11-95 pcp_src6 11-95 pcp_src7 11-95 pcp_src8 11-95 pcp_src9 11-96 pcp_ssr 11-79 pcxi 2-20 pdrr 3-113 piear 2-40, 2-49 pietr 2-40, 2-47 pmi_con0 2-82, 2-83 pmi_con1 2-82, 2-84 pmi_con2 2-82 pmi_str 2-82 pmu module registers 5-27 pmu0_id 5-28 pmu1_id 5-29 psw 2-20, 2-22 r rstcntcon 3-78 s sbcu control registers 4-80 sbcu_con 4-80, 4-83 sbcu_dbadr1 4-81, 4-93 sbcu_dbadr2 4-81, 4-93 sbcu_dbadrt 4-81, 4-97 sbcu_dbbos 4-81, 4-94 sbcu_dbbost 4-81, 4-98 sbcu_dbcntl 4-81, 4-88 sbcu_dbdat 4-81, 4-100 sbcu_dbgntt 4-81, 4-95 sbcu_dbgrnt 4-81, 4-91 sbcu_eadd 4-81, 4-86 sbcu_econ 4-81, 4-84 sbcu_edat 4-81, 4-87 sbcu_id 4-80, 4-82 sbcu_src 4-81, 4-102 scu_arstdis 3-80 scu_ccucon0 3-42 scu_ccucon1 3-45 scu_ccucon2 3-47 scu_chipid 3-183 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-31 v1.1, 2011-03 scu_dtscon 3-137 scu_dtsstat 3-138 scu_eccclr 3-134 scu_ecccon 3-130 scu_eccstat 3-132 scu_emsr 3-157 scu_extcon 3-49 scu_fdr 3-51 scu_id 3-184 scu_in 3-90 scu_intclr 3-164 scu_intdis 3-165 scu_intnp 3-167 scu_intset 3-162 scu_intstat 3-160 scu_iocr 3-85 scu_manid 3-185 scu_memtest 3-187 scu_omr 3-89 scu_osccon 3-31 scu_out 3-88 scu_pllcon0 3-35, 3-40 scu_pllcon1 3-37, 3-42 scu_pllcon2 3-38 scu_pllstat 3-33, 3-38 scu_pmcsr 3-123 scu_rstcon 3-78 scu_rststat 3-75 scu_rtid 3-185 scu_src0 3-169, 25-71 scu_src1 3-169, 25-71 scu_src2 3-169, 25-71 scu_src3 3-169, 25-71 scu_stcon 3-128 scu_ststat 3-126 scu_syscon 3-182 scu_trapclr 3-177 scu_trapdis 3-179 scu_trapset 3-175 scu_trapstat 3-172 sdma registers intcr 13-62 sdma control registers 13-41 sdma_adrcr0x 13-72 sdma_chcr0x 13-65 sdma_chicr0x 13-70 sdma_chrstr 13-51 sdma_chsr0x 13-69 sdma_clc 13-92 sdma_clre 13-59 sdma_dadr0x 13-78 sdma_damax0x 13-81 sdma_damin0x 13-81 sdma_dcrc0x 13-82 sdma_eer 13-55 sdma_errsr 13-57 sdma_gintr 13-50 sdma_htreq 13-54 sdma_id 13-46 sdma_intcr 13-62 sdma_intsr 13-60 sdma_me0pr 13-64 sdma_me0r 13-64 sdma_mesr 13-63 sdma_ocdsr 13-47 sdma_rdcrc0x 13-83 sdma_sadr0x 13-77 sdma_samax0x 13-80 sdma_samin0x 13-80 sdma_scrc0x 13-82 sdma_shadr0x 13-79 sdma_src0 13-45, 13-94 sdma_src1 13-45, 13-94 sdma_src2 13-44, 13-94 sdma_src3 13-44, 13-94 sdma_src4 13-44, 13-94 sdma_src5 13-44, 13-94 sdma_src6 13-44, 13-94 sdma_src7 13-44, 13-94 sdma_streq 13-53 sdma_suspmr 13-49 sdma_trsr 13-52 sdma_wrpsr 13-61 smacon 2-41, 2-55 ssc www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-32 v1.1, 2011-03 registers ssotc 21-39, 22-21 ssc module registers 21-28, 22-9 ssc0 register address map 21-59 ssc0_br 21-41, 21-59, 22-23 ssc0_clc 21-51, 21-59, 22-36 ssc0_con 21-31, 21-59, 22-13 ssc0_efm 21-36, 21-59, 22-18 ssc0_esrc 21-58, 21-60 ssc0_fdr 21-52, 21-59, 22-37 ssc0_id 21-28, 21-59 ssc0_pisel 21-29, 21-59, 22-11 ssc0_rb 21-42, 21-59, 22-24, 22-26 ssc0_rsrc 21-58, 21-60 ssc0_ssoc 21-38, 22-20 ssc0_ssotc 21-39, 21-59, 22-21 ssc0_stat 21-34, 21-59, 22-16, 22-27, 22-28, 22-29 ssc0_tb 21-42, 21-59, 22-24, 22-25 ssc0_tsrc 21-58, 21-59, 22-39 ssc1 register address map 21-60 ssc1_br 21-41, 21-60, 22-23 ssc1_clc 21-51, 21-60 ssc1_con 21-31, 21-60, 22-13 ssc1_efm 21-36, 21-60, 22-18 ssc1_esrc 21-58, 21-61 ssc1_fdr 21-52, 21-60 ssc1_id 21-28, 21-60 ssc1_pisel 21-29, 21-60, 22-11 ssc1_rb 21-42, 21-60, 22-24, 22-26 ssc1_rsrc 21-58, 21-60 ssc1_ssoc 21-38, 21-60, 22-20 ssc1_ssotc 21-39, 21-60, 22-21 ssc1_stat 21-34, 21-60, 22-16, 22-27, 22-28, 22-29 ssc1_tb 21-42, 21-60, 22-24, 22-25 ssc1_tsrc 21-58, 21-60, 22-39 ssc2 register address map 21-61, 21-62 ssc2_br 21-61 ssc2_clc 21-51, 21-61 ssc2_con 21-61 ssc2_efm 21-61 ssc2_esrc 21-58, 21-61 ssc2_fdr 21-52, 21-61 ssc2_id 21-61 ssc2_pisel 21-61 ssc2_rb 21-61 ssc2_rsrc 21-58, 21-61 ssc2_ssoc 21-61 ssc2_ssotc 21-61 ssc2_stat 21-61 ssc2_tb 21-61 ssc2_tsrc 21-58, 21-61 ssc3_br 21-62 ssc3_clc 21-51, 21-62 ssc3_con 21-62 ssc3_efm 21-62 ssc3_esrc 21-62 ssc3_fdr 21-52, 21-62 ssc3_id 21-62 ssc3_pisel 21-62 ssc3_rb 21-62 ssc3_rsrc 21-62 ssc3_ssoc 21-62 ssc3_ssotc 21-62 ssc3_stat 21-62 ssc3_tb 21-62 ssc3_tsrc 21-62 sscgx_br 22-41 sscgx_clc 22-41 sscgx_con 22-41 sscgx_efm 22-41 sscgx_fdr 22-41 sscgx_gefm 22-41 sscgx_gen 22-41 sscgx_gsrc 22-41 sscgx_gstat 22-41 sscgx_id 22-41 sscgx_pisel 22-41 sscgx_rb 22-41 sscgx_rbsnap 22-41 sscgx_ssotc 22-41 sscgx_stat 22-41 sscgx_tb 22-41 sscgx_tb1 22-41 sscgx_tb1snap 22-41 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1798 register index users manual l-33 v1.1, 2011-03 stm register address map 17-22 stm_cap 17-14, 17-22 stm_clc 17-9, 17-22 stm_cmcon 17-15, 17-22 stm_cmp0 17-14, 17-22 stm_cmp1 17-14, 17-22 stm_icr 17-17, 17-22 stm_id 17-10, 17-22 stm_isrr 17-19, 17-22 stm_src0 17-20, 17-22 stm_src1 17-20, 17-22 stm_tim0 17-11, 17-22 stm_tim1 17-11, 17-22 stm_tim2 17-12, 17-22 stm_tim3 17-12, 17-22 stm_tim4 17-12, 17-22 stm_tim5 17-13, 17-22 stm_tim6 17-13, 17-22 swrstcon 3-81 syscon 2-20 w wdt_con0 3-149 wdt_con1 3-151 wdt_sr 3-152 x xbar_arbcon 4-42 xbar_dbadd 4-55 xbar_dbcon 4-52 xbar_dbmadd 4-59 xbar_dbsat 4-35 xbar_err 4-51 xbar_erraddr 4-50 xbar_extcon 4-40 xbar_id 4-34 xbar_idinten 4-39 xbar_idintsat 4-37 xbar_intsat 4-36 xbar_prioh 4-44 xbar_src 4-63 xbar_sri control registers 4-28 www.datasheet.co.kr datasheet pdf - http://www..net/ www.infineon.com published by infineon technologies ag doc_number www.datasheet.co.kr datasheet pdf - http://www..net/ |
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